本發明為顯示驅動晶片之相關技術領域，尤指一種MIPI數據同步方法，用以供顯示驅動晶片執行，從而在阻抗匹配失調、ESD擾動等情況下仍可以對接收自應用處理器的多通道(multiple lanes)MIPI數據進行精準同步。The present invention relates to the field of display driver chips, and in particular to a MIPI data synchronization method for display driver chips to perform, so that multiple lanes MIPI data received from an application processor can be accurately synchronized under conditions such as impedance matching mismatch and ESD disturbance.
已知，MIPI為一種移動行業處理器介面(Mobile industry processor interface)，其被開發用以使得一應用處理器與一顯示驅動晶片之間實現高速數據傳輸，因此已被廣泛地應用於智慧型手機、平板電腦、穿戴式電子裝置、頭戴式顯示裝置、車載娛樂裝置等電子裝置之中。圖1為習知的一種使用MIPI技術的電子裝置的方塊圖。如圖1所示，該電子裝置1a包括一應用處理器(Application processor,AP)11a、一顯示驅動晶片12a以及一顯示面板13a，其中，該應用處理器11a通過其內部的一第一MIPI數據傳輸模塊111a向該顯示驅動晶片12a傳送多通道(multi lanes)MIPI數據，且該顯示驅動晶片12a以其內部的一第二MIPI數據傳輸模塊121a接收所述多通道(multi lanes)MIPI數據。As is known, MIPI is a mobile industry processor interface (MIPI), which is developed to enable high-speed data transmission between an application processor and a display driver chip, and has therefore been widely used in electronic devices such as smart phones, tablet computers, wearable electronic devices, head-mounted display devices, and in-vehicle entertainment devices. FIG1 is a block diagram of a known electronic device using MIPI technology. As shown in FIG1 , the electronic device 1a includes an application processor (AP) 11a, a display driver chip 12a, and a display panel 13a, wherein the application processor 11a transmits multi-lanes MIPI data to the display driver chip 12a through a first MIPI data transmission module 111a therein, and the display driver chip 12a receives the multi-lanes MIPI data through a second MIPI data transmission module 121a therein.
圖2為圖1所示之第二MIPI數據傳輸模塊121a的方塊圖。如圖2所示，應知道，通過MIPI介面，該應用處理器11a通過一個通道傳送一時鐘信號CLK至該顯示驅動晶片12a，且通過四通道傳送多通道(multi lanes)MIPI數據至該顯示驅動晶片12a。圖3為多通道MIPI數據的第一工作時序圖。如圖2與圖3所示，由於四個通道的MIPI數據皆含有複數個虛位元(dummy bits)、包含複數個位元的同步字組(sync word)以及包含複數個位元的有效數據(valid data)，因此，正常工作時，該第二MIPI數據傳輸模塊121a內部的一數位實體層(D-PHY)單元1211a會利用滑窗法(sliding window)使四個通道的MIPI數據的同步字組相互對齊。之後，通過實體層協議介面(PHY protocol interface,PPI)將完成對齊的四個通道的MIPI數據傳送至後端的一數據處理單元1212a。最終，該數據處理單元1212a將四個通道的MIPI數據解析(Depack)為對應的顯示數據(pixel stream)與控制命令。FIG2 is a block diagram of the second MIPI data transmission module 121a shown in FIG1. As shown in FIG2, it should be known that through the MIPI interface, the application processor 11a transmits a clock signal CLK to the display driver chip 12a through one channel, and transmits multi-lanes MIPI data to the display driver chip 12a through four channels. FIG3 is a first working timing diagram of multi-lane MIPI data. As shown in FIG. 2 and FIG. 3 , since the MIPI data of the four channels all contain a plurality of dummy bits, a sync word containing a plurality of bits, and valid data containing a plurality of bits, during normal operation, a digital physical layer (D-PHY) unit 1211a inside the second MIPI data transmission module 121a will use a sliding window method to align the sync words of the MIPI data of the four channels. Afterwards, the aligned MIPI data of the four channels are transmitted to a data processing unit 1212a at the back end through a physical layer protocol interface (PHY protocol interface, PPI). Finally, the data processing unit 1212a parses (depacks) the MIPI data of the four channels into corresponding display data (pixel stream) and control commands.
圖4為多通道MIPI數據的第二工作時序圖。如圖2與圖4所示，在該應用處理器11a傳送多通道MIPI數據傳送至該顯示驅動晶片12a的過程中，若至少一通道(Lane)存在阻抗匹配失調或受到ESD擾動之影響，此時，至少一通道的MIPI數據會多出一個dummy數據，導致發生傳輸數據與時脈錯位的現象，使該通道(如圖4所示之Lane 4)的MIPI數據與其它通道的MIPI數據之間出現同步字組(sync word)不對齊的情況。最終，由於四個通道的MIPI數據無法實現同步字組對齊，因此該數據處理單元1212a無法成功地將四個通道的MIPI數據解析為顯示數據與控制命令。FIG4 is a second working timing diagram of multi-channel MIPI data. As shown in FIG2 and FIG4, when the application processor 11a transmits multi-channel MIPI data to the display driver chip 12a, if at least one lane has impedance mismatch or is affected by ESD disturbance, at this time, the MIPI data of at least one lane will have an additional dummy data, resulting in a misalignment of the transmission data and the clock, causing the MIPI data of the lane (Lane 4 shown in FIG4) to be out of sync with the MIPI data of other lanes. Finally, since the MIPI data of the four lanes cannot achieve synchronization word alignment, the data processing unit 1212a cannot successfully parse the MIPI data of the four lanes into display data and control commands.
綜上所述，現有的顯示驅動晶片12a所執行的MIPI數據同步方案顯然存在明顯缺陷。因此，應考慮對現有的顯示驅動晶片12a所執行的MIPI數據同步方案進行變更設計或改良，以解決其相關缺陷。In summary, the MIPI data synchronization scheme implemented by the existing display driver chip 12a obviously has obvious defects. Therefore, it should be considered to change the design or improve the MIPI data synchronization scheme implemented by the existing display driver chip 12a to solve its related defects.
由上述說明可知，本領域亟需一種新式的MIPI數據同步方法。From the above description, it can be seen that a new MIPI data synchronization method is urgently needed in this field.
本發明之主要目的在於提供一種MIPI數據同步方法，其係由例如為DDI或TDDI之顯示驅動晶片執行，以在阻抗匹配失調、ESD擾動等情況下仍可以對接收自上位機的多通道(multiple lanes)MIPI數據實現同步，並接著將多通道MIPI數據解析(Depack)為一顯示數據流(pixel)與至少一控制命令。The main purpose of the present invention is to provide a MIPI data synchronization method, which is executed by a display driver chip such as DDI or TDDI, so as to synchronize the multi-channel (multiple lanes) MIPI data received from the host computer under the conditions of impedance matching imbalance, ESD disturbance, etc., and then parse (Depack) the multi-channel MIPI data into a display data stream (pixel) and at least one control command.
為達成上述目的，本發明提出所述MIPI數據同步方法的一實施例，其係由一電子晶片執行以同步自一上位機接收的N個MIPI數據；其中，N為正整數，且所述MIPI數據同步方法包括：對N個MIPI數據執行一同步字組檢出操作，從而獲得自M個所述MIPI數據所檢出的M個同步字組；其中，M為正整數，且M≦N；執行一同步字組緩存操作，從而將M個所述同步字組對應地緩存在M個緩存器之中；在M個所述MIPI數據完成所述同步字組緩存操作之後，接著執行一有效數據檢出操作從而獲得自M個所述MIPI數據所檢出的M個有效數據，且在存在L個所述MIPI數據未被檢出其同步字組的情況下持續對該L個MIPI數據執行所述同步字組檢出操作；其中，L為至少為1的正整數；執行一有效數據緩存操作以將M個所述有效數據對應地緩存在M個所述緩存器之中，且執行所述同步字組緩存操作以將檢出的L個所述同步字組對應地緩存在L個緩存器之中；重複執行前述同步字組檢出操作、同步字組緩存操作、有效數據檢出操作以及有效數據緩存操作，直至每個所述MIPI數據所包含之所述同步字組和所述有效數據皆已被緩存在其對應的所述緩存器之中；以及自N個所述緩存器讀出N個所述同步字組與N個所述有效數據以組成N個MIPI數據。To achieve the above-mentioned purpose, the present invention proposes an embodiment of the MIPI data synchronization method, which is executed by an electronic chip to synchronize N MIPI data received from a host computer; wherein N is a positive integer, and the MIPI data synchronization method comprises: performing a synchronization word group detection operation on the N MIPI data, thereby obtaining M synchronization word groups detected from the M MIPI data; wherein M is a positive integer, and M≦N; performing a synchronization word group cache operation, thereby correspondingly caching the M synchronization word groups in the M buffers; after the M MIPI data complete the synchronization word group cache operation, then performing a valid data detection operation to obtain M valid data detected from the M MIPI data, and when there are L MIPI data When the synchronization word group is not detected, the synchronization word group detection operation is continuously performed on the L MIPI data; wherein L is a positive integer of at least 1; a valid data cache operation is performed to cache the M valid data in the M buffers correspondingly, and the synchronization word group cache operation is performed to cache the detected L synchronization word groups in the L buffers correspondingly; and Repeat the aforementioned synchronization word group detection operation, synchronization word group buffering operation, valid data detection operation and valid data buffering operation until the synchronization word group and the valid data contained in each MIPI data have been buffered in the corresponding buffer; and read N synchronization word groups and N valid data from N buffers to form N MIPI data.
在一實施例中，該電子晶片具有一MIPI數據傳輸模塊，且該MIPI數據傳輸模塊包括：一數位實體層(D-PHY)單元，用以執行所述同步字組檢出操作以及所述同步字組緩存操作以將檢出的所述同步字組緩存在對應的所述緩存器之中，且用以執行所述有效數據檢出操作以及所述有效數據緩存操作以將檢出的所述有效數據緩存在對應的所述緩存器之中；以及一數據處理單元，自該數位實體層單元接收以完成同步的N個所述MIPI數據，並將該N個MIPI數據解析(Depack)為一顯示數據流(pixel stream)與至少一控制命令。In one embodiment, the electronic chip has a MIPI data transmission module, and the MIPI data transmission module includes: a digital physical layer (D-PHY) unit, which is used to perform the synchronization word group detection operation and the synchronization word group buffering operation to buffer the detected synchronization word group in the corresponding buffer, and to perform the valid data detection operation and the valid data buffering operation to buffer the detected valid data in the corresponding buffer; and a data processing unit, which receives the N MIPI data to complete synchronization from the digital physical layer unit, and parses (Depack) the N MIPI data into a display data stream (pixel stream) and at least one control command.
在一實施例，該數位實體層單元內含用以檢出所述同步字組的一同步字組檢出器以及包括N個所述緩存器的一緩存單元。In one embodiment, the digital physical layer unit includes a synchronization word detector for detecting the synchronization word and a buffer unit including N of the buffers.
在一實施例，在所述同步字組檢出操作的一執行時間超過一時間閥值的情況下仍未成功地自N個所述MIPI數據對應檢出N個所述同步字組，該同步字組檢出器係輸出一檢出錯誤信號。In one embodiment, when the execution time of the synchronization word detection operation exceeds a time threshold and the N synchronization words are not successfully detected from the N MIPI data, the synchronization word detector outputs a detection error signal.
在一實施例，該電子晶片為選自於顯示驅動晶片與觸控和顯示驅動整合(Touch and Display Driver Integration,TDDI)晶片所組成群組之中的任一者。In one embodiment, the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip.
並且，本發明還一種電子晶片的一實施例，其係用於和一顯示面板一同組成一顯示器，且內含一MIPI數據傳輸模塊；其特徵在於，該MIPI數據傳輸模塊被配置以執行一種MIPI數據同步方法從而同步自一上位機接收的N個MIPI數據；其中，N為正整數，且所述MIPI數據同步方法包括：對N個MIPI數據執行一同步字組檢出操作，從而獲得自M個所述MIPI數據所檢出的M個同步字組；其中，M為正整數，且M≦N；執行一同步字組緩存操作，從而將M個所述同步字組對應地緩存在M個緩存器之中；在M個所述MIPI數據完成所述同步字組緩存操作之後，接著執行一有效數據檢出操作從而獲得自M個所述MIPI數據所檢出的M個有效數據，且在存在L個所述MIPI數據未被檢出其同步字組的情況下持續對該L個MIPI數據執行所述同步字組檢出操作；其中，L為至少為1的正整數；執行一有效數據緩存操作以將M個所述有效數據對應地緩存在M個所述緩存器之中，且執行所述同步字組緩存操作以將檢出的L個所述同步字組對應地緩存在L個緩存器之中；重複執行前述同步字組檢出操作、同步字組緩存操作、有效數據檢出操作以及有效數據緩存操作，直至每個所述MIPI數據所包含之所述同步字組和所述有效數據皆已被緩存在其對應的所述緩存器之中；以及自N個所述緩存器讀出N個所述同步字組與N個所述有效數據以組成N個MIPI數據。Furthermore, the present invention also provides an embodiment of an electronic chip, which is used to form a display together with a display panel, and contains a MIPI data transmission module; the MIPI data transmission module is configured to execute a MIPI data synchronization method to synchronize N MIPI data received from a host computer; wherein N is a positive integer, and the MIPI data synchronization method comprises: According to the embodiment of the present invention, a synchronization word group detection operation is performed to obtain M synchronization word groups detected from the M MIPI data; wherein M is a positive integer and M≦N; a synchronization word group buffering operation is performed to correspondingly buffer the M synchronization word groups in the M buffers; after the M MIPI data complete the synchronization word group buffering operation, a valid data detection operation is then performed to obtain the M synchronization word groups detected from the M MIPI data. According to the M valid data detected, and when there are L MIPI data whose synchronization word groups have not been detected, continue to perform the synchronization word group detection operation on the L MIPI data; wherein L is a positive integer of at least 1; perform a valid data cache operation to cache the M valid data in the M buffers accordingly, and perform the synchronization word group cache operation to cache the detected L synchronization word groups in the M buffers accordingly. Cache the sync word group in L buffers; repeatedly execute the aforementioned sync word group detection operation, sync word group cache operation, valid data detection operation and valid data cache operation until the sync word group and the valid data contained in each MIPI data have been cached in the corresponding buffer; and read N sync word groups and N valid data from N buffers to form N MIPI data.
在一實施例中，該MIPI數據傳輸模塊包括：一數位實體層(D-PHY)單元，用以執行所述同步字組檢出操作以及所述同步字組緩存操作以將檢出的所述同步字組緩存在對應的所述緩存器之中，且用以執行所述有效數據檢出操作以及所述有效數據緩存操作以將檢出的所述有效數據緩存在對應的所述緩存器之中；以及一數據處理單元，自該數位實體層單元接收以完成同步的N個所述MIPI數據，並將該N個MIPI數據解析(Depack)為一顯示數據流(pixel stream)與至少一控制命令。In one embodiment, the MIPI data transmission module includes: a digital physical layer (D-PHY) unit, which is used to perform the synchronization word group detection operation and the synchronization word group buffering operation to buffer the detected synchronization word group in the corresponding buffer, and to perform the valid data detection operation and the valid data buffering operation to buffer the detected valid data in the corresponding buffer; and a data processing unit, which receives the N MIPI data to complete synchronization from the digital physical layer unit, and parses (Depack) the N MIPI data into a display data stream (pixel stream) and at least one control command.
在一實施例，該數位實體層單元內含用以檢出所述同步字組的一同步字組檢出器以及包括N個所述緩存器的一緩存單元。In one embodiment, the digital physical layer unit includes a synchronization word detector for detecting the synchronization word and a buffer unit including N of the buffers.
在一實施例，在所述同步字組檢出操作的一執行時間超過一時間閥值的情況下仍未成功地自N個所述MIPI數據對應檢出N個所述同步字組，該同步字組檢出器係輸出一檢出錯誤信號。In one embodiment, when the execution time of the synchronization word detection operation exceeds a time threshold and the N synchronization words are not successfully detected from the N MIPI data, the synchronization word detector outputs a detection error signal.
在一實施例，該電子晶片為選自於顯示驅動晶片與觸控和顯示驅動整合(Touch and Display Driver Integration,TDDI)晶片所組成群組之中的任一者。In one embodiment, the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip.
進一步地，本發明還提出一種資訊處理裝置的一實施例，其特徵在於，具有至少一個顯示器，且該顯示器包括一顯示面板以及至少一個如前所述本發明之電子晶片。Furthermore, the present invention also proposes an embodiment of an information processing device, which is characterized in that it has at least one display, and the display includes a display panel and at least one electronic chip of the present invention as described above.
在可行的實施例中，該資訊處理裝置為選自於由多媒體資訊顯示裝置(KIOSK)、頭戴式顯示裝置、智慧型電視、智慧型手機、智慧型手錶、平板電腦、一體式電腦、筆記型電腦、車載娛樂裝置、數位相機、和視訊式門口機所組成群組之中的一種電子裝置。In a feasible embodiment, the information processing device is an electronic device selected from the group consisting of a multimedia information display device (KIOSK), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a notebook computer, an in-vehicle entertainment device, a digital camera, and a video door machine.
為使 貴審查委員能進一步瞭解本發明之結構、特徵、目的、與其優點，茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.
圖5為應用本發明之一種MIPI數據同步方法的資訊處理裝置的方塊圖。如圖5所示，該資訊處理裝置1包括一應用處理器(Application processor,AP)11、一電子晶片12以及一顯示面板13，其中，該應用處理器11通過多個MIPI傳輸通道向該電子晶片12傳送多通道(multi lanes)MIPI數據，且該電子晶片12以其內部的一MIPI數據傳輸模塊121接收所述多通道(multi lanes)MIPI數據。在可行的實施例中，該資訊處理裝置可以是但不限於、多媒體資訊顯示裝置(KIOSK)、頭戴式顯示裝置、智慧型電視、智慧型手機、智慧型手錶、平板電腦、一體式電腦、筆記型電腦、車載娛樂裝置、數位相機、或視訊式門口機。並且，圖5所示之顯示面板13以及電子晶片12係組成一顯示器，其中該電子晶片12可以是顯示驅動晶片(Display driver IC,DDIC)或觸控和顯示驅動整合(Touch and Display Driver Integration,TDDI)晶片。FIG5 is a block diagram of an information processing device that applies a MIPI data synchronization method of the present invention. As shown in FIG5, the information processing device 1 includes an application processor (AP) 11, an electronic chip 12, and a display panel 13, wherein the application processor 11 transmits multi-lane MIPI data to the electronic chip 12 through multiple MIPI transmission channels, and the electronic chip 12 receives the multi-lane MIPI data through a MIPI data transmission module 121 inside it. In a feasible embodiment, the information processing device may be, but is not limited to, a multimedia information display device (KIOSK), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a notebook computer, a car entertainment device, a digital camera, or a video door station. Moreover, the display panel 13 and the electronic chip 12 shown in FIG. 5 form a display, where the electronic chip 12 can be a display driver IC (DDIC) or a touch and display driver integration (Touch and Display Driver Integration, TDDI) chip.
圖6為圖5所示之MIPI數據傳輸模塊121的方塊圖。如圖5與圖6所示，應知道，通過多個MIPI傳輸通道，該應用處理器11經由一個通道傳送一時鐘信號CLK至該電子晶片12，且經由四個通道傳送四個MIPI數據至該電子晶片12。並且，該MIPI數據傳輸模塊121包括一數位實體層(D-PHY)單元1211與一數據處理單元1212。進一步地，圖7為四個通道的MIPI數據的第一工作時序圖。如圖7所示，每個通道的MIPI數據皆含有：複數個虛位元(dummy bits)、包含複數個位元的同步字組(sync word)以及包含複數個位元的有效數據(valid data)。正常工作時，該數位實體層單元1211自四個通道的MIPI數據對應檢出四個同步字組，從而通過四個同步字組使四個MIPI數據相互對齊。之後，該數位實體層單元1211通過實體層協議介面(PHY protocol interface,PPI)將完成對齊的四個通道的MIPI數據傳送至後端的一數據處理單元1212。最終，該數據處理單元1212將四個通道的MIPI數據解析(Depack)為一顯示數據流(pixel stream)與至少一控制命令。FIG6 is a block diagram of the MIPI data transmission module 121 shown in FIG5. As shown in FIG5 and FIG6, it should be known that through multiple MIPI transmission channels, the application processor 11 transmits a clock signal CLK to the electronic chip 12 through one channel, and transmits four MIPI data to the electronic chip 12 through four channels. In addition, the MIPI data transmission module 121 includes a digital physical layer (D-PHY) unit 1211 and a data processing unit 1212. Further, FIG7 is a first working timing diagram of the MIPI data of the four channels. As shown in FIG7, the MIPI data of each channel contains: a plurality of dummy bits, a synchronization word (sync word) containing a plurality of bits, and valid data (valid data) containing a plurality of bits. During normal operation, the digital physical layer unit 1211 detects four synchronization words corresponding to the MIPI data of the four channels, thereby aligning the four MIPI data with each other through the four synchronization words. Afterwards, the digital physical layer unit 1211 transmits the aligned MIPI data of the four channels to a data processing unit 1212 at the back end through the physical layer protocol interface (PHY protocol interface, PPI). Finally, the data processing unit 1212 parses (Depack) the MIPI data of the four channels into a display data stream (pixel stream) and at least one control command.
圖8為圖6所示之數位實體層單元1211的方塊圖，且圖9為四個通道的MIPI數據的第二工作時序圖。如圖7與圖8所示，該數位實體層單元1211含有一同步字組檢出器1215用於執行一同步字組檢出操作。並且，在未受到阻抗匹配失調、ESD擾動的影響之情況下，該同步字組檢出器1215利用滑窗法(sliding window)完成所述同步字組檢出操作，從而自四個通道的MIPI數據對應檢出四個同步字組。然而，如圖9所示，當有任一通道出現阻抗匹配失調、ESD擾動等異常狀況時，受到影響的通道的MIPI數據會多出一個dummy數據(如圖9之中的Lane 3通道)，導致發生傳輸數據與時脈錯位的現象。在此情況下，該同步字組檢出器1215無法同時間自四個通道的MIPI數據對應檢出四個同步字組。最終，由於四個通道的MIPI數據無法實現同步字組對齊，因此該數據處理單元1212無法成功地將四個通道的MIPI數據解析為顯示數據流與控制命令。FIG8 is a block diagram of the digital physical layer unit 1211 shown in FIG6, and FIG9 is a second operation timing diagram of the MIPI data of four channels. As shown in FIG7 and FIG8, the digital physical layer unit 1211 includes a synchronization word group detector 1215 for performing a synchronization word group detection operation. In addition, without being affected by impedance matching imbalance and ESD disturbance, the synchronization word group detector 1215 uses a sliding window method to complete the synchronization word group detection operation, thereby detecting four synchronization words corresponding to the MIPI data of four channels. However, as shown in FIG9 , when any channel has an abnormal condition such as impedance mismatch or ESD disturbance, the MIPI data of the affected channel will have an additional dummy data (such as Lane 3 in FIG9 ), resulting in a misalignment of the transmission data and clock. In this case, the synchronization word detector 1215 cannot detect four synchronization words corresponding to the MIPI data of the four channels at the same time. Finally, since the MIPI data of the four channels cannot achieve synchronization word alignment, the data processing unit 1212 cannot successfully parse the MIPI data of the four channels into display data streams and control commands.
圖10為本發明之一種MIPI數據同步方法的流程圖。如圖5、圖8與圖10所示，因此，必須配置使該MIPI數據傳輸模塊121的該數位實體層單元1211執行本發明之MIPI數據同步方法從而實現該四個MIPI數據之同步處理。如圖5、圖8與圖10所示，方法流程係首先執行步驟S1：對N個MIPI數據執行一同步字組檢出操作，從而獲得自M個所述MIPI數據所檢出的M個同步字組(sync word)，其中N例如為4，但隨著實際應用需求可以為2~4之中的一個整數。並且，M≦N。FIG10 is a flow chart of a MIPI data synchronization method of the present invention. As shown in FIG5, FIG8 and FIG10, therefore, the digital physical layer unit 1211 of the MIPI data transmission module 121 must be configured to execute the MIPI data synchronization method of the present invention to achieve synchronization processing of the four MIPI data. As shown in FIG5, FIG8 and FIG10, the method flow is to first execute step S1: perform a synchronization word detection operation on N MIPI data, thereby obtaining M synchronization words detected from the M MIPI data, where N is, for example, 4, but can be an integer between 2 and 4 according to actual application requirements. And, M≦N.
圖11為利用滑窗法完成對一MIPI數據的一同步字組檢出操作的示意圖。如圖6、圖8與圖11所示，在步驟S1中，該數位實體層單元1211內部的同步字組檢出器1215利用滑窗法(sliding window)完成對Lane 0通道的MIPI數據的同步字組檢出操作，從而獲得一同步字組0001 1101=0XB8h。同時，在沒有外力干擾的情況下，該同步字組檢出器1215同時可以完成Lane 1通道、Lane 2通道、Lane 3通道的MIPI數據的同步字組檢出操作。在此情況下，M=N。可惜的是，如圖9所示，Lane 3通道因為受到阻抗匹配失調、ESD擾動等外力干擾，致使其傳輸的MIPI數據會多出dummy數據，導致該同步字組檢出器1215只能夠同時完成Lane 0通道、Lane 1通道與Lane 2通道的MIPI數據的同步字組檢出操作，而無法自Lane 3通道的MIPI數據之中檢出對應的一同步字組。在此情況下，M<N。FIG11 is a schematic diagram of a synchronous word detection operation for a MIPI data using a sliding window method. As shown in FIG6, FIG8 and FIG11, in step S1, the synchronous word detector 1215 inside the digital entity layer unit 1211 uses a sliding window method to complete the synchronous word detection operation for the MIPI data of Lane 0 channel, thereby obtaining a synchronous word 0001 1101=0XB8h. At the same time, in the absence of external interference, the synchronous word detector 1215 can simultaneously complete the synchronous word detection operation of the MIPI data of Lane 1 channel, Lane 2 channel, and Lane 3 channel. In this case, M=N. Unfortunately, as shown in FIG9 , Lane 3 is disturbed by external forces such as impedance matching mismatch and ESD disturbance, resulting in dummy data in the transmitted MIPI data, causing the sync word detector 1215 to only be able to complete the sync word detection operation of the MIPI data of Lane 0, Lane 1, and Lane 2 at the same time, and unable to detect a corresponding sync word from the MIPI data of Lane 3. In this case, M<N.
如圖8所示，本發明特別在該數位實體層單元1211之中增設一個緩存單元1216，且進一步配置該緩存單元1216包括對應N個MIPI數據的N個緩存器。如圖6、圖8與圖10所示，完成步驟S1之後，方法流程係接著執行步驟S2：執行一同步字組緩存操作，從而將M個所述同步字組對應地緩存在M個緩存器之中。進一步地，圖12為圖8所示的緩存單元1216所包含的四個緩存器在多個不同時間點的緩存狀態的示意圖。如圖6、圖8、圖9、與圖12所示，以N=4且M=3為例，該數位實體層單元1211的該同步字組檢出器1215自Lane 0通道的MIPI數據、Lane 1通道的MIPI數據和Lane 2通道的MIPI數據之中檢出三個同步字組(即，0001 1101=0XB8h)，並接著於時間點t1將三個同步字組緩存於該緩存單元1216的三個緩存器121F之中。As shown in FIG8 , the present invention particularly adds a cache unit 1216 in the digital entity layer unit 1211, and further configures the cache unit 1216 to include N caches corresponding to N MIPI data. As shown in FIG6 , FIG8 and FIG10 , after completing step S1, the method flow then executes step S2: executing a synchronization word group cache operation, thereby correspondingly caching the M synchronization words in the M caches. Furthermore, FIG12 is a schematic diagram of the cache status of the four caches included in the cache unit 1216 shown in FIG8 at multiple different time points. As shown in FIG. 6, FIG. 8, FIG. 9, and FIG. 12, taking N=4 and M=3 as an example, the synchronization word detector 1215 of the digital physical layer unit 1211 detects three synchronization words (i.e., 0001 1101=0XB8h) from the MIPI data of Lane 0, the MIPI data of Lane 1, and the MIPI data of Lane 2, and then buffers the three synchronization words in the three buffers 121F of the buffer unit 1216 at time point t1.
如圖10所示，方法流程接著執行步驟S3：在M個所述MIPI數據完成所述同步字組緩存操作之後，接著執行一有效數據檢出操作從而獲得自M個所述MIPI數據所檢出的M個有效數據(valid data)，且在存在L個所述MIPI數據未被檢出其同步字組的情況下持續對該L個MIPI數據執行所述同步字組檢出操作；其中，L為至少為1的正整數。並且，方法流程接著執行步驟S4：執行一有效數據緩存操作以將M個所述有效數據對應地緩存在M個所述緩存器121F之中，且執行所述同步字組緩存操作以將檢出的L個所述同步字組對應地緩存在L個緩存器121F之中。特別說明的是，較佳情況是，執行第二次的所述同步字組檢出操作可以完成所有通道(Lane0~Lane3)的同步字組(sync word)檢出，此時N-M=L。然而，在較差的情況中(worst case)，有可能第三次的所述同步字組檢出操作時才完成所有通道的sync word檢出，此時N-M≧L。As shown in FIG. 10 , the method flow then executes step S3: after the synchronization word group cache operation is completed for the M MIPI data, a valid data detection operation is then performed to obtain M valid data (valid data) detected from the M MIPI data, and when there are L MIPI data whose synchronization words have not been detected, the synchronization word group detection operation is continuously performed on the L MIPI data; wherein L is a positive integer of at least 1. Furthermore, the method flow then executes step S4: executing a valid data cache operation to cache the M valid data in the M buffers 121F accordingly, and executing the sync word cache operation to cache the detected L sync words in the L buffers 121F accordingly. It is particularly noted that in the best case, the sync word detection of all channels (Lane0~Lane3) can be completed by executing the second sync word detection operation, and N-M=L at this time. However, in the worst case, it is possible that the sync word detection of all channels is completed during the third sync word detection operation, and N-M≧L at this time.
如圖6、圖8、圖9、與圖12所示，該數位實體層單元1211自Lane 0通道的MIPI數據、Lane 1通道的MIPI數據和Lane 2通道的MIPI數據之中檢出三個有效數據(Valid data)，並接著於時間點t2將三個有效數據緩存於該緩存單元1216的三個緩存器121F之中。同時，該數位實體層單元1211自Lane 3通道的MIPI數據之中檢出同步字組(即，0001 1101=0XB8h)，並於時間點t2將該同步字組緩存於其對應的所述緩存器121F之中。As shown in Figures 6, 8, 9, and 12, the digital physical layer unit 1211 detects three valid data (Valid data) from the MIPI data of Lane 0, the MIPI data of Lane 1, and the MIPI data of Lane 2, and then caches the three valid data in the three buffers 121F of the buffer unit 1216 at time point t2. At the same time, the digital physical layer unit 1211 detects a synchronization word group (i.e., 0001 1101=0XB8h) from the MIPI data of Lane 3, and caches the synchronization word group in the corresponding buffer 121F at time point t2.
繼續地，方法流程接著執行步驟S5：重複執行前述同步字組檢出操作、同步字組緩存操作、有效數據檢出操作以及有效數據緩存操作，直至每個所述MIPI數據所包含之所述同步字組和所述有效數據皆已被緩存在其對應的所述緩存器之中。最終，方法流程接著執行步驟S6：自N個所述緩存器讀出N個所述同步字組與N個所述有效數據以組成N個MIPI數據。Continuing, the method flow then executes step S5: repeatedly executing the aforementioned synchronization word group detection operation, synchronization word group buffering operation, valid data detection operation and valid data buffering operation until the synchronization word group and the valid data contained in each of the MIPI data have been buffered in the corresponding buffer. Finally, the method flow then executes step S6: reading N synchronization word groups and N valid data from N buffers to form N MIPI data.
如圖6、圖8、圖9、與圖12所示，該數位實體層單元1211繼續地自Lane 3通道的MIPI數據之中檢出其有效數據(Valid data)，並接著於時間點t3將檢出的有效數據緩存於其對應的緩存器121F之中。同時，由於該數位實體層單元1211在時間點t2完成了四個通道的MIPI數據的同步字組的檢出與緩存，因此，在時間點t3，該數位實體層單元1211自四個緩存器121F讀出四個同步字組。之後，該數位實體層單元1211接著四個緩存器121F讀出四個有效數據，最終以該四個同步字組與四個有效數據以組成四個MIPI數據，從而完成四個MIPI數據的同步處理。As shown in FIG6, FIG8, FIG9, and FIG12, the digital physical layer unit 1211 continues to detect the valid data (Valid data) from the MIPI data of Lane 3, and then caches the detected valid data in the corresponding buffer 121F at time point t3. At the same time, since the digital physical layer unit 1211 completes the detection and caching of the synchronous word groups of the MIPI data of the four channels at time point t2, the digital physical layer unit 1211 reads four synchronous word groups from the four buffers 121F at time point t3. Afterwards, the digital physical layer unit 1211 reads out four valid data from four buffers 121F, and finally uses the four synchronization words and four valid data to form four MIPI data, thereby completing the synchronization processing of the four MIPI data.
補充說明的是，MIPI協定標準係定義了由多個位元組成的一錯誤報告(error report)，例如：bit0~bit13，其中bit1的描述(description)為sot_sync_error，即用以表示是否同步成功之位元。因此，在所述同步字組檢出操作的一執行時間超過一時間閥值的情況下仍未成功地自N個所述MIPI數據對應檢出N個所述同步字組(即，步驟S5)，該同步字組檢出器1215係輸出一檢出錯誤信號，據此該數位實體層單元1211將所述錯誤報告的bit1(即，sot_sync_error)設為1，使該電子晶片12及/或該應用處理器11得知多通道MIPI數據在傳輸過程中出現了數據同步錯誤之狀況。It should be noted that the MIPI protocol standard defines an error report consisting of multiple bits, for example: bit0~bit13, where the description of bit1 is sot_sync_error, which is a bit used to indicate whether the synchronization is successful. Therefore, when the execution time of the synchronization word detection operation exceeds a time threshold and the N synchronization words corresponding to the N MIPI data are not successfully detected (i.e., step S5), the synchronization word detector 1215 outputs a detection error signal, and accordingly the digital physical layer unit 1211 sets the bit 1 (i.e., sot_sync_error) of the error report to 1, so that the electronic chip 12 and/or the application processor 11 know that a data synchronization error occurs during the transmission of the multi-channel MIPI data.
如此，上述已完整且清楚地說明本發明之一種MIPI數據同步方法；並且，經由上述可得知本發明具有下列優點：Thus, the above has completely and clearly described a MIPI data synchronization method of the present invention; and, from the above, it can be known that the present invention has the following advantages:
(1)本發明揭示一種MIPI數據同步方法，MIPI數據同步方法，其係由例如為DDI或TDDI之顯示驅動晶片執行，以在阻抗匹配失調、ESD擾動等情況下仍可以對接收自上位機的多通道(multiple lanes)MIPI數據實現同步，並接著將多通道MIPI數據解析(Depack)為一顯示數據流(pixel)與至少一控制命令。(1) The present invention discloses a MIPI data synchronization method, which is executed by a display driver chip such as DDI or TDDI, so as to synchronize the multi-channel (multiple lanes) MIPI data received from the host computer under the conditions of impedance matching imbalance, ESD disturbance, etc., and then parse (Depack) the multi-channel MIPI data into a display data stream (pixel) and at least one control command.
(2)本發明還揭示一種電子晶片，其用以和一顯示面板一同組成一顯示器，且內含一MIPI數據傳輸模塊；其特徵在於，該MIPI數據傳輸模塊被配置以執行如前所述本發明之MIPI數據同步方法，從而在阻抗匹配失調、ESD擾動等情況下仍可以對接收自上位機的多通道(multiple lanes)MIPI數據實現同步。(2) The present invention also discloses an electronic chip, which is used to form a display together with a display panel, and contains a MIPI data transmission module; its characteristic is that the MIPI data transmission module is configured to execute the MIPI data synchronization method of the present invention as described above, so that the multi-channel (multiple lanes) MIPI data received from the host computer can still be synchronized under the conditions of impedance matching imbalance, ESD disturbance, etc.
(3)進一步地，本發明還揭示一種資訊處理裝置，其特徵在於，具有至少一個顯示器，且該顯示器包括一顯示面板以及至少一個如前所述本發明之電子晶片。(3) Furthermore, the present invention also discloses an information processing device, which is characterized in that it has at least one display, and the display includes a display panel and at least one electronic chip of the present invention as described above.
必須加以強調的是，前述本案所揭示者乃為較佳實施例，舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者，俱不脫本案之專利權範疇。It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.
綜上所陳，本案無論目的、手段與功效，皆顯示其迥異於習知技術，且其首先發明合於實用，確實符合發明之專利要件，懇請 貴審查委員明察，並早日賜予專利俾嘉惠社會，是為至禱。In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.
1a:電子裝置1a: Electronic devices
11a:應用處理器11a: Application Processor
111a:第一MIPI數據傳輸模塊111a: First MIPI data transmission module
12a:顯示驅動晶片12a: Display driver chip
121a:第二MIPI數據傳輸模塊121a: Second MIPI data transmission module
1211a:數位實體層(D-PHY)單元1211a: Digital physical layer (D-PHY) unit
1212a:數據處理單元1212a: Data processing unit
13a:顯示面板13a: Display panel
1:資訊處理裝置1: Information processing device
11:應用處理器11: Application processor
12:電子晶片12: Electronic chips
121:MIPI數據傳輸模塊121:MIPI data transmission module
1211:數位實體層單元1211: Digital entity layer unit
1212:數據處理單元1212: Data processing unit
1215:同步字組檢出器1215: Sync word detector
1216:緩存單元1216: Cache unit
121F:緩存器121F: Cache
13:顯示面板13: Display panel
S1:對N個MIPI數據執行一同步字組檢出操作，從而獲得自M個所述MIPI數據所檢出的M個同步字組S1: Perform a synchronization word detection operation on N MIPI data, thereby obtaining M synchronization words detected from the M MIPI data
S2:執行一同步字組緩存操作，從而將M個所述同步字組對應地緩存在M個緩存器之中S2: Perform a synchronous word group cache operation, thereby correspondingly caching the M synchronous word groups in M buffers
S3:在M個所述MIPI數據完成所述同步字組緩存操作之後，接著執行一有效數據檢出操作從而獲得自M個所述MIPI數據所檢出的M個有效數據，且在存在L個所述MIPI數據未被檢出其同步字組的情況下持續對該L個MIPI數據執行所述同步字組檢出操作S3: After the synchronization word group cache operation is completed for the M MIPI data, a valid data detection operation is then performed to obtain M valid data detected from the M MIPI data, and if there are L MIPI data whose synchronization words have not been detected, the synchronization word group detection operation is continued for the L MIPI data.
S4:執行一有效數據緩存操作以將M個所述有效數據對應地緩存在M個所述緩存器之中，且執行所述同步字組緩存操作以將檢出的L個所述同步字組對應地緩存在L個緩存器之中S4: Perform a valid data cache operation to cache the M valid data in the M buffers accordingly, and perform the synchronization word group cache operation to cache the detected L synchronization word groups in the L buffers accordingly.
S5:重複執行前述同步字組檢出操作、同步字組緩存操作、有效數據檢出操作以及有效數據緩存操作，直至每個所述MIPI數據所包含之所述同步字組和所述有效數據皆已被緩存在其對應的所述緩存器之中S5: Repeat the aforementioned synchronization word group detection operation, synchronization word group buffering operation, valid data detection operation and valid data buffering operation until the synchronization word group and the valid data contained in each MIPI data have been buffered in the corresponding buffer.
S6:自N個所述緩存器讀出N個所述同步字組與N個所述有效數據以組成N個MIPI數據S6: Read N synchronization words and N valid data from N buffers to form N MIPI data
圖1為習知的一種使用MIPI技術的電子裝置的方塊圖；圖2為圖1所示之第二MIPI數據傳輸模塊的方塊圖；圖3為多通道MIPI數據的第一工作時序圖；圖4為多通道MIPI數據的第二工作時序圖；圖5為應用本發明之一種MIPI數據同步方法的資訊處理裝置的方塊圖；圖6為圖5所示之MIPI數據傳輸模塊的方塊圖；圖7為四個通道的MIPI數據的第一工作時序圖；圖8為圖6所示之數位實體層單元的方塊圖；圖9為四個通道的MIPI數據的第二工作時序圖；圖10為本發明之一種MIPI數據同步方法的流程圖；圖11為利用滑窗法完成對一MIPI數據的一同步字組檢出操作的示意圖；以及圖12為圖8所示的緩衝單元所包含的四個緩存器在多個不同時間點的緩存狀態的示意圖。FIG. 1 is a block diagram of a known electronic device using MIPI technology; FIG. 2 is a block diagram of a second MIPI data transmission module shown in FIG. 1; FIG. 3 is a first working timing diagram of multi-channel MIPI data; FIG. 4 is a second working timing diagram of multi-channel MIPI data; FIG. 5 is a block diagram of an information processing device using a MIPI data synchronization method of the present invention; FIG. 6 is a block diagram of the MIPI data transmission module shown in FIG. 5; and FIG. 7 is a block diagram of a MIPI data transmission module of four channels. FIG. 8 is a block diagram of the digital physical layer unit shown in FIG. 6; FIG. 9 is a second working timing diagram of MIPI data of four channels; FIG. 10 is a flow chart of a MIPI data synchronization method of the present invention; FIG. 11 is a schematic diagram of a synchronous word detection operation of a MIPI data using a sliding window method; and FIG. 12 is a schematic diagram of the buffer status of the four buffers included in the buffer unit shown in FIG. 8 at multiple different time points.
S1:對N個MIPI數據執行一同步字組檢出操作，從而獲得自M個所述MIPI數據所檢出的M個同步字組S1: Perform a synchronization word group detection operation on N MIPI data, thereby obtaining M synchronization word groups detected from the M MIPI data.
S2:執行一同步字組緩存操作，從而將M個所述同步字組對應地緩存在M個緩存器之中S2: Perform a synchronous word group cache operation, thereby caching the M synchronous word groups correspondingly in M buffers
S3:在M個所述MIPI數據完成所述同步字組緩存操作之後，接著執行一有效數據檢出操作從而獲得自M個所述MIPI數據所檢出的M個有效數據，且在存在L個所述MIPI數據未被檢出其同步字組的情況下持續對該L個MIPI數據執行所述同步字組檢出操作S3: After the synchronization word group cache operation is completed for the M MIPI data, a valid data detection operation is then performed to obtain M valid data detected from the M MIPI data, and if there are L MIPI data whose synchronization words have not been detected, the synchronization word group detection operation is continued for the L MIPI data.
S4:執行一有效數據緩存操作以將M個所述有效數據對應地緩存在M個所述緩存器之中，且執行所述同步字組緩存操作以將檢出的L個所述同步字組對應地緩存在L個緩存器之中S4: Perform a valid data cache operation to cache the M valid data in the M buffers accordingly, and perform the synchronization word group cache operation to cache the detected L synchronization word groups in the L buffers accordingly.
S5:重複執行前述同步字組檢出操作、同步字組緩存操作、有效數據檢出操作以及有效數據緩存操作，直至每個所述MIPI數據所包含之所述同步字組和所述有效數據皆已被緩存在其對應的所述緩存器之中S5: Repeat the aforementioned synchronization word group detection operation, synchronization word group buffering operation, valid data detection operation and valid data buffering operation until the synchronization word group and the valid data contained in each MIPI data have been buffered in the corresponding buffer.
S6:自N個所述緩存器讀出N個所述同步字組與N個所述有效數據以組成N個MIPI數據S6: Read N synchronization words and N valid data from N buffers to form N MIPI data
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW112150852ATWI863777B (en) | 2023-12-26 | 2023-12-26 | MIPI data synchronization method, electronic chip, and information processing device |
| Application Number | Priority Date | Filing Date | Title |
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| TW112150852ATWI863777B (en) | 2023-12-26 | 2023-12-26 | MIPI data synchronization method, electronic chip, and information processing device |
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| TWI863777Btrue TWI863777B (en) | 2024-11-21 |
| TW202527556A TW202527556A (en) | 2025-07-01 |
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| TW112150852ATWI863777B (en) | 2023-12-26 | 2023-12-26 | MIPI data synchronization method, electronic chip, and information processing device |
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| US20180246725A1 (en)* | 2013-08-08 | 2018-08-30 | Linear Algebra Technologies Limited | Apparatus, systems, and methods for low power computational imaging |
| CN109639380A (en)* | 2018-11-29 | 2019-04-16 | 青岛海信电器股份有限公司 | Processing method, device, equipment and the storage medium of MIPI signal |
| US20200003862A1 (en)* | 2018-07-02 | 2020-01-02 | Nxp Usa, Inc. | Communication unit, integrated circuits and method for clock and data synchronization |
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| US20130290581A1 (en)* | 2010-02-11 | 2013-10-31 | Silicon Image, Inc. | Hybrid interface for serial and parallel communication |
| US20180246725A1 (en)* | 2013-08-08 | 2018-08-30 | Linear Algebra Technologies Limited | Apparatus, systems, and methods for low power computational imaging |
| US20200003862A1 (en)* | 2018-07-02 | 2020-01-02 | Nxp Usa, Inc. | Communication unit, integrated circuits and method for clock and data synchronization |
| CN109639380A (en)* | 2018-11-29 | 2019-04-16 | 青岛海信电器股份有限公司 | Processing method, device, equipment and the storage medium of MIPI signal |
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| TW202527556A (en) | 2025-07-01 |
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