實施形態係大致關於一種記憶裝置。Embodiments generally relate to a memory device.
已知有一種使用具有動態可變之電阻之元件記憶資料之記憶裝置。記憶裝置謀求於短時間讀出資料。A memory device is known that uses a device having a dynamically variable resistance to store data. The memory device is intended to read out data in a short time.
本發明欲解決之問題在於提供一種於短時間讀出資料之記憶裝置。The problem that the present invention aims to solve is to provide a memory device that can read out data in a short time.
一實施形態之記憶裝置具備第1配線、第2配線、記憶胞、第1電路、第2電路、第3電路、第4電路及感測放大器電路。A memory device according to one embodiment includes a first wiring, a second wiring, a memory cell, a first circuit, a second circuit, a third circuit, a fourth circuit, and a sense amplifier circuit.
上述記憶胞連接於上述第1配線與上述第2配線之間，包含可變電阻元件與開關元件。上述可變電阻元件包含第1強磁性層、第2強磁性層、及上述第1強磁性層與上述第2強磁性層間之絕緣層。上述第1電路以對上述第1配線施加第1電壓之方式構成。上述第2電路以對上述第2配線施加第2電壓之方式構成。上述第3電路以對上述第2配線施加第3電壓之方式構成。上述第4電路以對上述第1配線施加第4電壓之方式構成。上述感測放大器電路與上述第1配線及上述第2配線連接。The memory cell is connected between the first wiring and the second wiring, and includes a variable resistance element and a switch element. The variable resistance element includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The first circuit is configured to apply a first voltage to the first wiring. The second circuit is configured to apply a second voltage to the second wiring. The third circuit is configured to apply a third voltage to the second wiring. The fourth circuit is configured to apply a fourth voltage to the first wiring. The sense amplifier circuit is connected to the first wiring and the second wiring.
以下，參照圖式記述實施形態。有某實施形態或不同實施形態中具有大致同一功能及構成之複數個構成要件為了互相區分而於參照符號之末尾進而附加數字或文字之情形。於某已記述之實施形態之後續實施形態中，主要記述與已記述之實施形態之不同點。某實施形態之所有記述只要未明示或明顯排除，則亦適合作為其他實施形態之記述。The following describes the embodiments with reference to the drawings. In some embodiments or different embodiments, a number or letter is added to the end of the reference symbol to distinguish between multiple components having substantially the same function and structure. In the subsequent embodiments of an already described embodiment, the differences from the already described embodiment are mainly described. All descriptions of an embodiment are also applicable to the descriptions of other embodiments unless explicitly stated or clearly excluded.
各功能區塊並非必須如以下之例般區分。例如，一部分功能亦可由與例示之功能區塊不同之功能區塊執行。再者，亦可將例示之功能區塊分割成更細之功能子區塊。Each functional block does not necessarily need to be divided as in the following example. For example, a portion of the functions may be performed by a functional block different from the illustrated functional block. Furthermore, the illustrated functional block may also be divided into smaller functional sub-blocks.
本說明書及申請專利範圍中，某第1要件「連接於」其他第2要件包含第1要件直接或始終或選擇性經由導電性要件連接於第2要件。In this specification and patent application, a first element "connected to" another second element includes the first element being directly, permanently or selectively connected to the second element via a conductive element.
1.第1實施形態 1.1.構造(構成) 1.1.1全體之構成 圖1顯示第1實施形態之記憶裝置之功能區塊。記憶裝置1為記憶資料之裝置。記憶裝置1使用表示可變電阻之磁性體之積層體記憶資料。記憶裝置1包含核心電路11、輸入輸出電路12、控制電路13、解碼電路14、頁面緩衝器15及電壓產生電路16。1. First embodiment1.1. Structure1.1.1 Overall structureFIG. 1 shows the functional blocks of the memory device of the first embodiment. The memory device 1 is a device for storing data. The memory device 1 uses a multilayer body of a magnetic material representing a variable resistor to store data. The memory device 1 includes a core circuit 11, an input-output circuit 12, a control circuit 13, a decoding circuit 14, a page buffer 15, and a voltage generating circuit 16.
核心電路11為包含記憶胞MC、及用以存取記憶胞MC之配線以及周邊電路之電路。記憶胞MC為非揮發性記憶資料之元件。配線包含全域字元線GWL(未圖示)、局域字元線LWL、全域位元線GBL(未圖示)及局域位元線LBL。各記憶胞MC與1個局域字元線LWL及1個局域位元線LBL連接。局域字元線LWL分配有1個列位址。局域位元線LBL分配有1個行位址。The core circuit 11 is a circuit including memory cells MC, wiring for accessing memory cells MC, and peripheral circuits. Memory cells MC are elements for non-volatile memory data. The wiring includes global word lines GWL (not shown), local word lines LWL, global bit lines GBL (not shown), and local bit lines LBL. Each memory cell MC is connected to one local word line LWL and one local bit line LBL. The local word line LWL is assigned one column address. The local bit line LBL is assigned one row address.
輸入輸出電路12為進行資料及信號之輸入輸出之電路。輸入輸出電路12自記憶裝置1之外部例如記憶體控制器接收控制信號CNT、指令CMD、位址信號ADD及寫入至記憶胞MC之資料DAT。The input/output circuit 12 is a circuit for inputting and outputting data and signals. The input/output circuit 12 receives control signals CNT, commands CMD, address signals ADD and data DAT to be written into the memory cell MC from the outside of the memory device 1, such as a memory controller.
控制電路13為控制記憶裝置1之動作之電路。控制電路13自輸入輸出電路12接收指令CMD及控制信號CNT。控制電路13基於由指令CMD及控制信號CNT指示之控制，控制核心電路11，控制自記憶胞MC之資料讀出及對記憶胞MC之資料寫入。控制電路13基於由指令CMD及控制信號CNT指示之控制，控制電壓產生電路16。The control circuit 13 is a circuit for controlling the operation of the memory device 1. The control circuit 13 receives the command CMD and the control signal CNT from the input/output circuit 12. The control circuit 13 controls the core circuit 11 based on the control indicated by the command CMD and the control signal CNT, and controls the reading of data from the memory cell MC and the writing of data to the memory cell MC. The control circuit 13 controls the voltage generating circuit 16 based on the control indicated by the command CMD and the control signal CNT.
解碼電路14為將位址信號ADD解碼之電路。解碼電路14自輸入輸出電路12接收位址信號ADD。解碼電路14將位址信號ADD解碼，基於解碼結果，產生用以選擇資料讀出或資料寫入之對象之記憶胞MC之信號。將產生之信號發送至核心電路11。The decoding circuit 14 is a circuit for decoding the address signal ADD. The decoding circuit 14 receives the address signal ADD from the input/output circuit 12. The decoding circuit 14 decodes the address signal ADD and generates a signal for selecting the memory cell MC of the object of data reading or data writing based on the decoding result. The generated signal is sent to the core circuit 11.
頁面緩衝器15為暫時記憶某尺寸之資料之電路。頁面緩衝器15自輸入輸出電路12接收寫入至記憶胞MC之資料DAT，暫時記憶資料，將資料傳輸至核心電路11。頁面緩衝器15接收自記憶胞MC讀出之資料，暫時記憶讀出之資料，將資料DAT傳輸至輸入輸出電路12。The page buffer 15 is a circuit for temporarily storing data of a certain size. The page buffer 15 receives data DAT written to the memory cell MC from the input-output circuit 12, temporarily stores the data, and transmits the data to the core circuit 11. The page buffer 15 receives data read from the memory cell MC, temporarily stores the read data, and transmits the data DAT to the input-output circuit 12.
電壓產生電路16為產生記憶裝置1中使用之各種電壓之電路。電壓產生電路16基於控制電路13之控制產生電壓。電壓產生電路16於對記憶胞MC寫入資料之期間，將用於資料寫入之電壓供給至核心電路11。電壓產生電路16於自記憶胞MC讀出資料之期間，將用於資料讀出之電壓供給至核心電路11。The voltage generating circuit 16 is a circuit for generating various voltages used in the memory device 1. The voltage generating circuit 16 generates voltages based on the control of the control circuit 13. When writing data to the memory cell MC, the voltage generating circuit 16 supplies the voltage used for data writing to the core circuit 11. When reading data from the memory cell MC, the voltage generating circuit 16 supplies the voltage used for data reading to the core circuit 11.
1.1.2核心電路之構成 圖2顯示第1實施形態之核心電路11之功能區塊。如圖2所示，核心電路11包含1個以上子核心電路SCC、1個以上之全域字元線GWL、1個以上之全域位元線GBL、1個以上之讀出電路RC以及1個以上之寫入電路WC。圖2僅顯示1個子核心電路SCC、1個全域字元線GWL、1個全域位元線GBL、1個讀出電路RC以及1個寫入電路WC。1.1.2 Core circuit configurationFIG2 shows the functional blocks of the core circuit 11 of the first embodiment. As shown in FIG2 , the core circuit 11 includes one or more sub-core circuits SCC, one or more global word lines GWL, one or more global bit lines GBL, one or more read circuits RC, and one or more write circuits WC. FIG2 only shows one sub-core circuit SCC, one global word line GWL, one global bit line GBL, one read circuit RC, and one write circuit WC.
子核心電路SCC包含記憶胞陣列MA、列選擇器RS及行選擇器CS。The sub-core circuit SCC includes a memory cell array MA, a row selector RS and a row selector CS.
記憶胞陣列MA為排列之複數個記憶胞MC之集合。複數個局域字元線LWL及複數個局域位元線LBL位於記憶胞陣列MA。The memory cell array MA is a collection of a plurality of arranged memory cells MC. A plurality of local word lines LWL and a plurality of local bit lines LBL are located in the memory cell array MA.
列選擇器RS為選擇包含該列選擇器RS之子核心電路SCC中之記憶胞陣列MA之1個列之電路。列選擇器RS接收列位址，基於接收到之列位址，將列選擇器RS之選擇對象之記憶胞陣列(或對應之記憶胞陣列)MA之局域字元線LWL之一者連接於1個全域字元線GWL。列選擇器RS包含複數個開關。各開關於一端與1個全域字元線GWL連接，於另一端與1個局域字元線LWL連接。開關例如為MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金屬氧化物半導體場效電晶體)，例如為n型MOSFET。The column selector RS is a circuit for selecting a column of a memory cell array MA in a sub-core circuit SCC including the column selector RS. The column selector RS receives a column address, and based on the received column address, connects one of the local word lines LWL of the memory cell array (or the corresponding memory cell array) MA selected by the column selector RS to a global word line GWL. The column selector RS includes a plurality of switches. Each switch is connected to a global word line GWL at one end and to a local word line LWL at the other end. The switch is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), for example, an n-type MOSFET.
行選擇器CS為選擇包含該行選擇器CS之子核心電路SCC中之記憶胞陣列MA之1個行之電路。行選擇器CS接收行位址，基於接收到之行位址，將行選擇器CS之選擇對象之記憶胞陣列(或對應之記憶胞陣列)MA之局域位元線LBL之一者連接於1個全域位元線GBL。行選擇器CS包含複數個開關。各開關於一端與1個全域位元線GBL連接，於另一端與1個局域位元線LBL連接。開關例如為MOSFET，例如為n型MOSFET。The row selector CS is a circuit for selecting a row of a memory cell array MA in a sub-core circuit SCC including the row selector CS. The row selector CS receives a row address, and based on the received row address, connects one of the local bit lines LBL of the memory cell array (or corresponding memory cell array) MA selected by the row selector CS to a global bit line GBL. The row selector CS includes a plurality of switches. Each switch is connected to a global bit line GBL at one end and to a local bit line LBL at the other end. The switch is, for example, a MOSFET, for example, an n-type MOSFET.
全域字元線GWL連接於1個以上子核心電路SCC各者之列選擇器RS。全域字元線GWL還連接於1個讀出電路RC及1個寫入電路WC。The global word line GWL is connected to the row selector RS of each of more than one sub-core circuit SCC. The global word line GWL is also connected to a read circuit RC and a write circuit WC.
全域位元線GBL連接於1個以上子核心電路SCC各者之行選擇器CS。全域位元線GBL還連接於1個讀出電路RC及1個寫入電路WC。The global bit line GBL is connected to the row selector CS of each of more than one sub-core circuit SCC. The global bit line GBL is also connected to a read circuit RC and a write circuit WC.
讀出電路RC為控制自記憶胞MC讀出資料之電路。讀出電路RC使用基於記憶於資料讀出對象之記憶胞MC之資料之電壓，判斷記憶於資料讀出對象之記憶胞MC之資料。讀出電路RC包含複數個感測放大器電路SAC(未圖示)。感測放大器電路SAC為使用基於記憶於資料讀出對象之記憶胞MC之資料之電壓，輸出表示記憶於資料讀出對象之記憶胞MC之資料之信號的電路。感測放大器電路SAC基於2個電壓之大小關係，輸出記憶於資料讀出對象之記憶胞MC之已決定之資料。The read circuit RC is a circuit that controls the reading of data from the memory cell MC. The read circuit RC uses a voltage based on the data stored in the memory cell MC that is the target of data reading to determine the data stored in the memory cell MC that is the target of data reading. The read circuit RC includes a plurality of sense amplifier circuits SAC (not shown). The sense amplifier circuit SAC is a circuit that uses a voltage based on the data stored in the memory cell MC that is the target of data reading to output a signal representing the data stored in the memory cell MC that is the target of data reading. The sense amplifier circuit SAC outputs the determined data stored in the memory cell MC that is the target of data reading based on the magnitude relationship between the two voltages.
寫入電路WC為控制對記憶胞MC寫入資料之電路。寫入電路WC接收寫入之資料。寫入電路WC藉由基於寫入之資料使電流流動至資料寫入對象之記憶胞MC，而對資料寫入對象之記憶胞MC寫入資料。The write circuit WC is a circuit for controlling data writing to the memory cell MC. The write circuit WC receives the written data. The write circuit WC writes data to the data writing target memory cell MC by causing a current to flow to the data writing target memory cell MC based on the written data.
1.1.3.記憶胞陣列之電路構成 圖3係第1實施形態之記憶胞陣列MA之電路圖。如圖3所示，M+1(M為自然數)個局域字元線LWL(LWL＜0＞、LWL＜1＞、…、LWL＜M＞)及N+1(N為自然數)個局域位元線LBL(LBL＜0＞、LBL＜1＞、…、LBL＜N＞)位於記憶胞陣列MA中。1.1.3. Circuit structure of memory cell arrayFIG3 is a circuit diagram of the memory cell array MA of the first embodiment. As shown in FIG3, M+1 (M is a natural number) local word lines LWL (LWL<0>, LWL<1>, ..., LWL<M>) and N+1 (N is a natural number) local bit lines LBL (LBL<0>, LBL<1>, ..., LBL<N>) are located in the memory cell array MA.
各記憶胞MC與1個局域字元線LWL及1個局域位元線LBL連接。各記憶胞MC包含1個MTJ元件MTJ及1個開關元件SE。各記憶胞MC中，MTJ元件MTJ與開關元件SE串聯連接。各記憶胞MC之開關元件SE與1個局域位元線LBL連接。各記憶胞MC之MTJ元件MTJ與1個局域字元線LWL連接。Each memory cell MC is connected to a local word line LWL and a local bit line LBL. Each memory cell MC includes an MTJ element MTJ and a switch element SE. In each memory cell MC, the MTJ element MTJ is connected in series with the switch element SE. The switch element SE of each memory cell MC is connected to a local bit line LBL. The MTJ element MTJ of each memory cell MC is connected to a local word line LWL.
MTJ元件MTJ顯示隧道磁阻效應，且為例如包含磁隧道接面(Magnetic Tunnel Junction；MTJ)之元件。MTJ元件MTJ為可於低電阻狀態與高電阻狀態間切換之可變電阻元件。MTJ元件MTJ可利用2個電阻狀態之差異，記憶1位元之資料。例如，MTJ元件MTJ藉由低電阻狀態記憶“0”資料，藉由高電阻狀態記憶“1”資料。The MTJ element MTJ exhibits a tunnel magnetoresistance effect and is, for example, an element including a magnetic tunnel junction (MTJ). The MTJ element MTJ is a variable resistance element that can be switched between a low resistance state and a high resistance state. The MTJ element MTJ can use the difference between the two resistance states to store 1 bit of data. For example, the MTJ element MTJ stores "0" data in a low resistance state and stores "1" data in a high resistance state.
開關元件SE為進行自身之兩端之電性連接或切斷之元件。開關元件SE具有2個端子。開關元件SE在施加於2端子間之電壓未達某第1閾值之情形時，為高電阻狀態，例如電性非導通狀態(斷開狀態)。若施加於2端子間之電壓上升，變為第1閾值以上，則開關元件SE成為低電阻狀態，例如電性導通狀態(接通狀態)。若施加於低電阻狀態之開關元件SE之2端子間之電壓降低，變為第2閾值以下，則開關元件SE成為高電阻狀態。開關元件SE於與第1方向相反之第2方向上，亦具有與此種基於施加於第1方向之電壓之大小而於高電阻狀態及低電阻狀態之間切換之功能相同的功能。即，開關元件SE為雙向開關元件。藉由開關元件SE之接通或斷開，可控制有無對與該開關元件SE連接之MTJ元件MTJ供給電流，即，選擇或非選擇MTJ元件MTJ。The switching element SE is an element that electrically connects or disconnects its two ends. The switching element SE has two terminals. When the voltage applied between the two terminals does not reach a certain first threshold, the switching element SE is in a high resistance state, such as an electrically non-conductive state (disconnected state). If the voltage applied between the two terminals rises and becomes above the first threshold, the switching element SE becomes a low resistance state, such as an electrically conductive state (connected state). If the voltage applied between the two terminals of the switching element SE in the low resistance state decreases and becomes below the second threshold, the switching element SE becomes a high resistance state. The switching element SE also has the same function of switching between the high resistance state and the low resistance state based on the size of the voltage applied in the first direction in the second direction opposite to the first direction. That is, the switch element SE is a bidirectional switch element. By turning the switch element SE on or off, it is possible to control whether current is supplied to the MTJ element MTJ connected to the switch element SE, that is, to select or not select the MTJ element MTJ.
1.1.4.記憶胞陣列之構造 圖4係第1實施形態之記憶胞陣列MA之一部分立體圖。如圖4所示，設有複數個導電體21及複數個導電體22。1.1.4. Structure of memory cell arrayFigure 4 is a partial three-dimensional diagram of the memory cell array MA of the first embodiment. As shown in Figure 4, a plurality of conductors 21 and a plurality of conductors 22 are provided.
導電體21沿x軸延伸，沿y軸排列。各導電體21作為1個局域字元線LWL發揮功能。The conductors 21 extend along the x-axis and are arranged along the y-axis. Each conductor 21 functions as a local word line LWL.
導電體22位於導電體21之上方。導電體22沿y軸延伸，沿x軸排列。各導電體22作為1個局域位元線LBL發揮功能。The conductor 22 is located above the conductor 21. The conductors 22 extend along the y-axis and are arranged along the x-axis. Each conductor 22 functions as a local bit line LBL.
於導電體21與導電體22之交點各者設有1個記憶胞MC。記憶胞MC沿xy面矩陣狀排列。各記憶胞MC包含作為開關元件SE發揮功能之構造、與作為MTJ元件MTJ發揮功能之構造。作為開關元件SE發揮功能之構造、及作為MTJ元件MTJ發揮功能之構造各自包含1個或複數個層。例如，作為MTJ元件MTJ發揮功能之構造位於作為開關元件SE發揮功能之構造之上表面上。記憶胞MC之下表面與1個導電體21之上表面相接。記憶胞MC之上表面與1個導電體22之下表面相接。作為開關元件SE發揮功能之構造亦可位於作為MTJ元件MTJ發揮功能之構造之上表面上。A memory cell MC is provided at each intersection of the conductor 21 and the conductor 22. The memory cells MC are arranged in a matrix along the xy plane. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as an MTJ element MTJ. The structure that functions as a switching element SE and the structure that functions as an MTJ element MTJ each include one or more layers. For example, the structure that functions as an MTJ element MTJ is located on the upper surface of the structure that functions as a switching element SE. The lower surface of the memory cell MC is in contact with the upper surface of a conductor 21. The upper surface of the memory cell MC is in contact with the lower surface of a conductor 22. The structure that functions as a switch element SE may also be located on the upper surface of the structure that functions as an MTJ element MTJ.
1.1.5.記憶胞 圖5顯示第1實施形態之記憶胞MC之構造例之剖面。1.1.5. Memory cellFigure 5 shows a cross-section of a structural example of a memory cell MC in the first embodiment.
開關元件SE包含可變電阻材料32。可變電阻材料32為表示動態可變之電阻之材料，例如具有層之形狀。可變電阻材料32為2端子間開關元件，2端子中之第1端子為可變電阻材料32之上表面及下表面之一者，2端子中之第2端子為可變電阻材料32之上表面及下表面之另一者。施加於2端子間之電壓未達某第1閾值之情形時，可變電阻材料為“高電阻”狀態，例如電性非導電狀態。若施加於2端子間之電壓上升，變為第1閾值以上，則可變電阻材料成為“低電阻”狀態，例如電性導通狀態。若施加於低電阻狀態之可變電阻材料32之2端子間之電壓降低，變為第2閾值以下，則可變電阻材料成為高電阻狀態。可變電阻材料32包含絕緣體與藉由離子注入導入至絕緣體之摻雜物。絕緣體例如包含氧化物，包含SiO2或實質上由SiO2組成之材料。摻雜物例如包含砷(As)、鍺(Ge)。本說明書及申請專利範圍中，「實質上(或構成)」之記載及同種記載意指容許「實質上」之構成要件含有未意圖之雜質。The switch element SE includes a variable resistance material 32. The variable resistance material 32 is a material representing a dynamically variable resistance, for example, having a layered shape. The variable resistance material 32 is a two-terminal switch element, wherein the first terminal of the two terminals is one of the upper surface and the lower surface of the variable resistance material 32, and the second terminal of the two terminals is the other of the upper surface and the lower surface of the variable resistance material 32. When the voltage applied between the two terminals does not reach a certain first threshold value, the variable resistance material is in a "high resistance" state, for example, an electrically non-conductive state. If the voltage applied between the two terminals rises and becomes above the first threshold value, the variable resistance material becomes a "low resistance" state, for example, an electrically conductive state. If the voltage applied between the two terminals of the variable resistor material 32 in the low resistance state decreases and becomes below the second threshold, the variable resistor material becomes a high resistance state. The variable resistor material 32 includes an insulator and a dopant introduced into the insulator by ion implantation. The insulator includes, for example, an oxide, includingSiO2 or a material substantially composed ofSiO2 . The dopant includes, for example, arsenic (As) and germanium (Ge). In this specification and the scope of the patent application, the description of "substantially (or constituted)" and the same description means that the constituent element of "substantially" is allowed to contain unintentional impurities.
開關元件SE可進而包含下部電極31及上部電極33。圖5顯示此種例。可變電阻材料32位於下部電極31之上表面上，上部電極33位於可變電阻材料32之上表面上。The switch element SE may further include a lower electrode 31 and an upper electrode 33. Such an example is shown in FIG5. The variable resistance material 32 is located on the upper surface of the lower electrode 31, and the upper electrode 33 is located on the upper surface of the variable resistance material 32.
MTJ元件MTJ包含強磁性層35、絕緣層36及強磁性層37。作為例，如圖5所示，絕緣層36位於強磁性層35之上表面上，強磁性層37位於絕緣層36之上表面上。The MTJ element MTJ includes a ferromagnetic layer 35, an insulating layer 36, and a ferromagnetic layer 37. For example, as shown in FIG. 5 , the insulating layer 36 is located on the upper surface of the ferromagnetic layer 35, and the ferromagnetic layer 37 is located on the upper surface of the insulating layer 36.
強磁性層35為表示強磁性之材料之層。強磁性層35具有沿貫通強磁性層35、絕緣層36及強磁性層37之界面之方向之易磁化軸，例如具有相對於界面為45°以上90°以下之角度之易磁化軸，例如具有沿與界面正交之方向之易磁化軸。意圖使強磁性層35之磁化方向不根據記憶胞MC中之資料之讀出及寫入而變。強磁性層35可作為所謂參照層發揮功能。強磁性層35亦可包含複數層。以下，有將強磁性層35稱為參照層35之情形。The ferromagnetic layer 35 is a layer of a material representing ferromagnetism. The ferromagnetic layer 35 has an easy magnetization axis along the direction of the interface penetrating the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37, for example, an easy magnetization axis with an angle of 45° to 90° relative to the interface, for example, an easy magnetization axis along a direction orthogonal to the interface. It is intended that the magnetization direction of the ferromagnetic layer 35 does not change according to the reading and writing of data in the memory cell MC. The ferromagnetic layer 35 can function as a so-called reference layer. The ferromagnetic layer 35 can also include a plurality of layers. In the following, the ferromagnetic layer 35 is referred to as the reference layer 35.
絕緣層36為絕緣體之層。絕緣層36例如包含氧化鎂(MgO)，或實質上由MgO構成，作為所謂之隧道障壁發揮功能。The insulating layer 36 is a layer of an insulator. The insulating layer 36 contains, for example, magnesium oxide (MgO), or is substantially composed of MgO, and functions as a so-called tunnel barrier.
強磁性層37為表示強磁性之材料之層。強磁性層37例如包含鈷鐵硼(CoFeB)或硼化鐵(FeB)，或實質上由CoFeB或FeB構成。強磁性層37具有沿貫通強磁性層35、絕緣層36及強磁性層37之界面之方向之易磁化軸，例如具有相對於界面為45°以上90°以下之角度之易磁化軸，例如具有沿與界面正交之方向之易磁化軸。強磁性層37之磁化方向根據對記憶胞MC之資料寫入而可變，強磁性層37可作為所謂之記憶層發揮功能。以下，有將強磁性層37稱為記憶層37之情形。The ferromagnetic layer 37 is a layer of a material representing ferromagnetism. The ferromagnetic layer 37 includes, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or is substantially composed of CoFeB or FeB. The ferromagnetic layer 37 has an easy magnetization axis along the direction of the interface penetrating the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37, for example, an easy magnetization axis with an angle of 45° to 90° relative to the interface, for example, an easy magnetization axis along a direction orthogonal to the interface. The magnetization direction of the ferromagnetic layer 37 is variable according to the data written to the memory cell MC, and the ferromagnetic layer 37 can function as a so-called memory layer. In the following, the ferromagnetic layer 37 may be referred to as the memory layer 37.
若記憶層37之磁化方向與參照層35之磁化方向平行，則MTJ元件MTJ具有某低電阻。若記憶層37之磁化方向與參照層35之磁化方向反平行，則MTJ元件MTJ具有高於記憶層37之磁化方向與參照層35之磁化方向反平行時之電阻的電阻。以下，有將某MTJ元件MTJ之強磁性層37之磁化方向與參照層35之磁化方向平行之狀態稱為MTJ元件MTJ「處於平行狀態」或「處於P狀態」之情形。有將某MTJ元件MTJ之強磁性層37之磁化方向與參照層35之磁化方向反平行之狀態稱為MTJ元件MTJ「處於反平行狀態」或「處於AP狀態」之情形。If the magnetization direction of the memory layer 37 is parallel to the magnetization direction of the reference layer 35, the MTJ element MTJ has a low resistance. If the magnetization direction of the memory layer 37 is antiparallel to the magnetization direction of the reference layer 35, the MTJ element MTJ has a resistance higher than the resistance when the magnetization direction of the memory layer 37 is antiparallel to the magnetization direction of the reference layer 35. In the following, the state in which the magnetization direction of the ferromagnetic layer 37 of a certain MTJ element MTJ is parallel to the magnetization direction of the reference layer 35 is referred to as the MTJ element MTJ "in a parallel state" or "in a P state". The state in which the magnetization direction of the ferromagnetic layer 37 of a certain MTJ element MTJ is antiparallel to the magnetization direction of the reference layer 35 is referred to as the MTJ element MTJ "in an antiparallel state" or "in an AP state".
若自記憶層37向參照層35流動某大小之電流Icp以上之大小之電流Iwp，則記憶層37之磁化方向與參照層35之磁化方向平行。若自強磁性層35向記憶層37流動某大小之電流Icap以上之大小之電流Iwap，則記憶層37之磁化方向與參照層35之磁化方向反平行。電流Icap大於電流Icp。If a current Iwp greater than a certain current Icp flows from the memory layer 37 to the reference layer 35, the magnetization direction of the memory layer 37 becomes parallel to the magnetization direction of the reference layer 35. If a current Iwap greater than a certain current Icap flows from the ferromagnetic layer 35 to the memory layer 37, the magnetization direction of the memory layer 37 becomes antiparallel to the magnetization direction of the reference layer 35. The current Icap is greater than the current Icp.
以下，有將自參照層35朝向記憶層37之方向稱為AP方向之情形，有將自記憶層37朝向參照層35之方向稱為P方向之情形。有將開關電流Icp稱為P方向開關電流Icp之情形。有將開關電流Icap稱為AP方向開關電流Icap之情形。有將電流Iwp稱為P寫入電流Iwp之情形。有將電流Iwap稱為AP寫入電流Iwap之情形。In the following, the direction from the reference layer 35 toward the memory layer 37 is referred to as the AP direction, and the direction from the memory layer 37 toward the reference layer 35 is referred to as the P direction. The switching current Icp is referred to as the P direction switching current Icp. The switching current Icap is referred to as the AP direction switching current Icap. The current Iwp is referred to as the P write current Iwp. The current Iwap is referred to as the AP write current Iwap.
MTJ元件MTJ亦可包含更多之層。The MTJ element MTJ may also include more layers.
圖6係顯示第1實施形態之記憶胞MC之電壓與電流之特性之曲線例之圖表。圖表之橫軸表示記憶胞MC之端子電壓之大小。圖表之縱軸以對數刻度表示流過記憶胞MC之電流之大小。圖6由虛線表示實際上未顯現之假想性特性。圖6顯示記憶胞MC處於低電阻狀態之情形與處於高電阻狀態之情形。以下之記述相當於記憶胞MC處於低電阻狀態之情形與處於高電阻狀態之情形之任一者。FIG6 is a graph showing an example of a curve of the voltage and current characteristics of the memory cell MC of the first embodiment. The horizontal axis of the graph represents the magnitude of the terminal voltage of the memory cell MC. The vertical axis of the graph represents the magnitude of the current flowing through the memory cell MC in a logarithmic scale. FIG6 represents hypothetical characteristics that are not actually displayed by the dotted line. FIG6 shows the case where the memory cell MC is in a low resistance state and the case where it is in a high resistance state. The following description is equivalent to either the case where the memory cell MC is in a low resistance state or the case where it is in a high resistance state.
若電壓自0增大，則電流持續增加，直至達到閾值電壓Vth為止。於電壓達到閾值電壓Vth之前，記憶胞MC之開關元件SE斷開，即非導通。If the voltage increases from 0, the current continues to increase until it reaches the threshold voltage Vth. Before the voltage reaches the threshold voltage Vth, the switch element SE of the memory cell MC is disconnected, that is, non-conducting.
若電壓進而增大，電壓達到閾值電壓Vth，即，達到A點，則電壓與電流之關係顯示不連續之變化，而顯示點B1及點B2所示之特性。點B1及點B2處之電流大小大幅大於點A處之電流大小。該電流之急劇變化基於記憶胞MC之開關元件SE接通。點B1及點B2處之電流大小依存於記憶胞MC之MTJ元件MTJ之電阻狀態。If the voltage further increases and reaches the threshold voltage Vth, that is, reaches point A, the relationship between voltage and current shows a discontinuous change, and shows the characteristics shown by points B1 and B2. The current magnitude at points B1 and B2 is much larger than the current magnitude at point A. The rapid change in current is based on the switching element SE of the memory cell MC being turned on. The current magnitude at points B1 and B2 depends on the resistance state of the MTJ element MTJ of the memory cell MC.
若電壓自開關元件SE接通之狀態，例如電壓與電流顯示點B1或點B2所示關係之狀態減小，則電流持續減少。If the voltage decreases from the state where the switching element SE is turned on, for example, the state where the voltage and current show the relationship shown by point B1 or point B2, the current continues to decrease.
若電壓進而減小，達到某大小，則電壓與電流之關係顯示不連續之變化。電壓與電流之關係開始顯示不連續性時之電壓依存於記憶胞MC之MTJ元件MTJ之端子電壓，即MTJ元件MTJ處於高電阻狀態還是低電阻狀態。MTJ元件MTJ為低電阻狀態之情形時，電壓與電流之關係自點C1起顯示不連續性。MTJ元件MTJ為高電阻狀態之情形時，電壓與電流之關係自點C2起顯示不連續性。若電壓與電流之關係達到點C1及點C2，則分別顯示點D1及D2所示之特性。點D1及點D2處之電流大小分別大幅小於點C1及點C2處之電流大小。該電流之急劇變化基於記憶胞MC之開關元件SE斷開。If the voltage further decreases and reaches a certain size, the relationship between the voltage and the current shows a discontinuous change. The voltage at which the relationship between the voltage and the current begins to show discontinuity depends on the terminal voltage of the MTJ element MTJ of the memory cell MC, that is, whether the MTJ element MTJ is in a high resistance state or a low resistance state. When the MTJ element MTJ is in a low resistance state, the relationship between the voltage and the current shows discontinuity from point C1. When the MTJ element MTJ is in a high resistance state, the relationship between the voltage and the current shows discontinuity from point C2. If the relationship between the voltage and the current reaches point C1 and point C2, the characteristics shown by points D1 and D2 are displayed respectively. The current magnitudes at points D1 and D2 are significantly smaller than the current magnitudes at points C1 and C2, respectively. The rapid change in current is based on the disconnection of the switch element SE of the memory cell MC.
包含低電阻狀態之MTJ元件MTJ之記憶胞MC之點D1處之端子電壓稱為低保持電壓VhdL。包含高電阻狀態之MTJ元件MTJ之記憶胞MC之點D2處之端子電壓稱為高保持電壓VhdH。複數個記憶胞MC之各個高保持電壓VhdH之大小可能根據記憶胞MC之未意圖之特性偏差而不同。複數個記憶胞MC各者之低保持電壓VhdL之大小可能根據記憶胞MC之未意圖之特性偏差而不同。The terminal voltage at point D1 of the memory cell MC including the MTJ element MTJ in the low resistance state is called the low holding voltage VhdL. The terminal voltage at point D2 of the memory cell MC including the MTJ element MTJ in the high resistance state is called the high holding voltage VhdH. The magnitude of each high holding voltage VhdH of the plurality of memory cells MC may differ according to the unintended characteristic deviation of the memory cells MC. The magnitude of each low holding voltage VhdL of the plurality of memory cells MC may differ according to the unintended characteristic deviation of the memory cells MC.
1.1.7.讀出電路之構成 圖7顯示第1實施形態之讀出電路之構成要件及構成要件之連接。如圖7所示，讀出電路RC包含讀出控制電路ROC、驅動器電路RDUB、RDPB、RDUW及RDPW、同步電路RDSB及RDSW以及感測放大器電路SAC。圖7僅顯示1個全域位元線GBL及1個全域字元線GWL相關之構成要件。對其他全域位元線GBL亦設置驅動器電路RDUB及RDPB以及同步電路RDSB。又，對其他全域字元線GWL亦設置驅動器電路RDUW及RDPW、同步電路RDSW以及感測放大器電路SAC。1.1.7. Configuration of the readout circuitFIG. 7 shows the components of the readout circuit of the first embodiment and the connection of the components. As shown in FIG. 7, the readout circuit RC includes a readout control circuit ROC, driver circuits RDUB, RDPB, RDUW and RDPW, synchronous circuits RDSB and RDSW, and a sense amplifier circuit SAC. FIG. 7 only shows the components related to one global bit line GBL and one global word line GWL. Driver circuits RDUB and RDPB and a synchronous circuit RDSB are also provided for other global bit lines GBL. In addition, driver circuits RDUW and RDPW, a synchronous circuit RDSW, and a sense amplifier circuit SAC are also provided for other global word lines GWL.
同步電路RDSB以可對全域位元線GBL施加接地電壓(或共通電壓)Vss之方式構成。接地電壓Vss例如為0 V。同步電路RDSB只要可對全域位元線GBL施加接地電壓Vss，則亦可具有任意之構成。例如，同步電路RDSB包含開關SW1。開關SW1於一端與全域位元線GBL連接，於另一端與記憶裝置1中(例如電壓產生電路16)被施加接地電壓Vss之節點連接。開關SW1基於控制信號S1接通或斷開，於接通之期間，將接地電壓Vss傳輸至全域位元線GBL。開關SW1例如自讀出控制電路ROC接收控制信號S1。開關SW1例如為MOSFET。The synchronous circuit RDSB is configured to apply a ground voltage (or common voltage) Vss to the global bit line GBL. The ground voltage Vss is, for example, 0 V. The synchronous circuit RDSB may have any configuration as long as the ground voltage Vss can be applied to the global bit line GBL. For example, the synchronous circuit RDSB includes a switch SW1. The switch SW1 is connected to the global bit line GBL at one end and to a node in the memory device 1 (for example, the voltage generating circuit 16) to which the ground voltage Vss is applied at the other end. The switch SW1 is turned on or off based on the control signal S1, and while on, the ground voltage Vss is transmitted to the global bit line GBL. The switch SW1 receives the control signal S1, for example, from the read-out control circuit ROC. The switch SW1 is, for example, a MOSFET.
同步電路RDSW以可對全域字元線GWL施加接地電壓Vss之方式構成。同步電路RDSW只要可對全域字元線GWL施加接地電壓Vss，則可具有任意之構成。例如，同步電路RDSW包含開關SW4。開關SW4於一端與全域字元線GWL連接，於另一端與被施加接地電壓Vss之節點連接。開關SW4基於控制信號S4接通或斷開，於接通之期間，將接地電壓Vss傳輸至全域字元線GWL。開關SW4例如自讀出控制電路ROC接收控制信號S4。開關SW4例如為MOSFET。The synchronous circuit RDSW is configured to apply the ground voltage Vss to the global word line GWL. The synchronous circuit RDSW may have any configuration as long as the ground voltage Vss can be applied to the global word line GWL. For example, the synchronous circuit RDSW includes a switch SW4. The switch SW4 is connected to the global word line GWL at one end and to a node to which the ground voltage Vss is applied at the other end. The switch SW4 is turned on or off based on the control signal S4, and transmits the ground voltage Vss to the global word line GWL during the on period. The switch SW4 receives the control signal S4, for example, from the readout control circuit ROC. The switch SW4 is, for example, a MOSFET.
驅動器電路RDPB以可對全域位元線GBL施加預充電電壓Vpcp之方式構成。預充電電壓Vpcp具有如下之大小，藉由將預充電電壓Vpcp大小之電壓施加於1個記憶胞MC，而使該記憶胞MC之開關元件SE接通。又，預充電電壓Vpcp具有如下之大小，藉由施加於1個記憶胞MC，可使超過P方向開關電流Icp大小之大小之電流流過該記憶胞MC。驅動器電路RDPB只要可對全域位元線GBL施加預充電電壓Vpcp，則可具有任意之構成。例如，驅動器電路RDPB包含開關SW3。開關SW3於一端與全域位元線GBL連接，於另一端與記憶裝置1中(例如電壓產生電路16)被施加預充電電壓Vpcp之節點連接。開關SW3基於控制信號S3接通或斷開，於接通之期間，將預充電電壓Vpcp傳輸至全域位元線GBL。開關SW3例如自讀出控制電路ROC接收控制信號S3。開關SW3例如為MOSFET。The driver circuit RDPB is configured to apply a precharge voltage Vpcp to the global bit line GBL. The precharge voltage Vpcp has a magnitude such that by applying a voltage of the magnitude of the precharge voltage Vpcp to a memory cell MC, the switch element SE of the memory cell MC is turned on. Furthermore, the precharge voltage Vpcp has a magnitude such that by applying it to a memory cell MC, a current exceeding the magnitude of the P-direction switch current Icp can flow through the memory cell MC. The driver circuit RDPB may have any configuration as long as the precharge voltage Vpcp can be applied to the global bit line GBL. For example, the driver circuit RDPB includes a switch SW3. The switch SW3 is connected to the global bit line GBL at one end and to a node in the memory device 1 (e.g., the voltage generating circuit 16) to which the precharge voltage Vpcp is applied at the other end. The switch SW3 is turned on or off based on the control signal S3, and when turned on, the precharge voltage Vpcp is transmitted to the global bit line GBL. The switch SW3 receives the control signal S3 from the readout control circuit ROC, for example. The switch SW3 is, for example, a MOSFET.
驅動器電路RDPW以可對全域字元線GWL施加預充電電壓Vpcap之方式構成。預充電電壓Vpcap具有如下大小：高於接地電壓Vss及高保持電壓VhdH，低於預充電電壓Vpcp，藉由將預充電電壓Vpcap大小之電壓施加於1個記憶胞MC，而使該記憶胞MC之開關元件SE接通。又，預充電電壓Vpcap具有藉由施加於1個記憶胞MC，可使未達AP方向開關電流Icap大小之電流流過該記憶胞MC之大小。驅動器電路RDPW只要可對全域字元線GWL施加預充電電壓Vpcap，則亦可具有任意之構成。例如，驅動器電路RDPW包含開關SW6。開關SW6於一端與全域字元線GWL連接，於另一端與記憶裝置1中(例如電壓產生電路16)被施加預充電電壓Vpcap之節點連接。開關SW6基於控制信號S6接通或斷開，於接通之期間，將預充電電壓Vpcap傳輸至全域字元線GWL。開關SW6例如自讀出控制電路ROC接收控制信號S6。開關SW6例如為MOSFET。The driver circuit RDPW is constructed in such a way that a precharge voltage Vpcap can be applied to the global word line GWL. The precharge voltage Vpcap has the following magnitude: higher than the ground voltage Vss and the high holding voltage VhdH, and lower than the precharge voltage Vpcp, and by applying a voltage of the magnitude of the precharge voltage Vpcap to a memory cell MC, the switch element SE of the memory cell MC is turned on. Furthermore, the precharge voltage Vpcap has a magnitude that, by being applied to a memory cell MC, allows a current that does not reach the magnitude of the AP direction switch current Icap to flow through the memory cell MC. The driver circuit RDPW may have any structure as long as the precharge voltage Vpcap can be applied to the global word line GWL. For example, the driver circuit RDPW includes a switch SW6. The switch SW6 is connected to the global word line GWL at one end and is connected to a node in the memory device 1 (e.g., the voltage generating circuit 16) to which the precharge voltage Vpcap is applied at the other end. The switch SW6 is turned on or off based on the control signal S6, and during the on period, the precharge voltage Vpcap is transmitted to the global word line GWL. The switch SW6 receives the control signal S6 from the read-out control circuit ROC, for example. The switch SW6 is, for example, a MOSFET.
驅動器電路RDUB以可對全域位元線GBL施加非選擇電壓Vusel之方式構成。非選擇電壓Vusel高於接地電壓Vss，低於預充電電壓Vpcap及預充電電壓Vpcp。非選擇電壓Vusel具有即使將非選擇電壓Vusel大小之電壓施加於1個記憶胞MC，亦不使該記憶胞MC之開關元件SE接通之大小。又，非選擇電壓Vusel具有即使將預充電電壓Vpcp與非選擇電壓Vusel之差的大小之電壓施加於1個記憶胞MC，亦不使該記憶胞MC之開關元件SE接通之大小。再者，非選擇電壓Vusel具有即使將預充電電壓Vpcap與非選擇電壓Vusel之差的大小之電壓施加於1個記憶胞MC，亦不使該記憶胞MC之開關元件SE接通之大小。驅動器電路RDUB只要可對全域位元線GBL施加非選擇電壓Vusel，則可具有任意之構成。例如，驅動器電路RDUB包含開關SW2。開關SW2於一端與全域位元線GBL連接，於另一端與記憶裝置1中(例如電壓產生電路16)被施加非選擇電壓Vusel之節點連接。開關SW2基於控制信號S2接通或斷開，於接通之期間，將非選擇電壓Vusel傳輸至全域位元線GBL。開關SW2例如自讀出控制電路ROC接收控制信號S2。開關SW2例如為MOSFET。The driver circuit RDUB is configured to apply a non-selection voltage Vusel to the global bit line GBL. The non-selection voltage Vusel is higher than the ground voltage Vss and lower than the pre-charge voltage Vpcap and the pre-charge voltage Vpcp. The non-selection voltage Vusel has a magnitude such that even if a voltage of the magnitude of the non-selection voltage Vusel is applied to a memory cell MC, the switch element SE of the memory cell MC is not turned on. Furthermore, the non-selection voltage Vusel has a magnitude such that even if a voltage of the magnitude of the difference between the pre-charge voltage Vpcp and the non-selection voltage Vusel is applied to a memory cell MC, the switch element SE of the memory cell MC is not turned on. Furthermore, the non-selection voltage Vusel has a magnitude that does not turn on the switch element SE of a memory cell MC even if a voltage having a magnitude of the difference between the pre-charge voltage Vpcap and the non-selection voltage Vusel is applied to a memory cell MC. The driver circuit RDUB may have any configuration as long as it can apply the non-selection voltage Vusel to the global bit line GBL. For example, the driver circuit RDUB includes a switch SW2. The switch SW2 is connected to the global bit line GBL at one end and to a node in the memory device 1 (e.g., the voltage generating circuit 16) to which the non-selection voltage Vusel is applied at the other end. The switch SW2 is turned on or off based on the control signal S2, and while on, the non-selection voltage Vusel is transmitted to the global bit line GBL. The switch SW2 receives the control signal S2 from the read-out control circuit ROC, for example. The switch SW2 is, for example, a MOSFET.
驅動器電路RDUW以可對全域字元線GWL施加非選擇電壓Vusel之方式構成。驅動器電路RDUW只要可對全域字元線GWL施加非選擇電壓Vusel，則亦可具有任意之構成。例如，驅動器電路RDUW包含開關SW5。開關SW5於一端與全域字元線GWL連接，另一端與被施加非選擇電壓Vusel之節點連接。開關SW5基於控制信號S5接通或斷開，於接通之期間，將非選擇電壓Vusel傳輸至全域字元線GWL。開關SW5例如自讀出控制電路ROC接收控制信號S5。開關SW5例如為MOSFET。The driver circuit RDUW is configured in such a way that a non-selection voltage Vusel can be applied to the global word line GWL. The driver circuit RDUW may have any configuration as long as the non-selection voltage Vusel can be applied to the global word line GWL. For example, the driver circuit RDUW includes a switch SW5. The switch SW5 is connected to the global word line GWL at one end and is connected to a node to which the non-selection voltage Vusel is applied at the other end. The switch SW5 is turned on or off based on the control signal S5, and when it is turned on, the non-selection voltage Vusel is transmitted to the global word line GWL. The switch SW5 receives the control signal S5, for example, from the read-out control circuit ROC. The switch SW5 is, for example, a MOSFET.
讀出控制電路ROC為控制讀出電路RC中之構成要件之電路。讀出控制電路ROC基於控制信號而動作，且該控制信號藉由控制電路13及解碼電路14基於控制信號CNT、指令CMD及位址信號ADD而產生。The read control circuit ROC is a circuit that controls a constituent element of the read circuit RC. The read control circuit ROC operates based on a control signal, and the control signal is generated by the control circuit 13 and the decoding circuit 14 based on the control signal CNT, the command CMD and the address signal ADD.
感測放大器電路SAC與全域位元線GBL及全域字元線GWL連接。The sense amplifier circuit SAC is connected to the global bit line GBL and the global word line GWL.
圖8顯示第1實施形態之感測放大器電路SAC之構成要件及構成要件之連接。如圖8所示，感測放大器電路SAC包含電晶體Tr1及Tr2、電壓調整電路VMC以及運算放大器OP。電晶體Tr1連接於全域位元線GBL與節點N1之間。電晶體Tr1於閘極電極中，例如自讀出控制電路ROC接收控制信號S11。FIG8 shows the components of the sense amplifier circuit SAC of the first embodiment and the connection of the components. As shown in FIG8, the sense amplifier circuit SAC includes transistors Tr1 and Tr2, a voltage adjustment circuit VMC, and an operational amplifier OP. Transistor Tr1 is connected between the global bit line GBL and the node N1. Transistor Tr1 receives a control signal S11 in the gate electrode, for example, from the readout control circuit ROC.
電晶體Tr2連接於全域字元線GWL與節點N2之間。電晶體Tr2於閘極電極中，例如自讀出控制電路ROC接收控制信號S11。The transistor Tr2 is connected between the global word line GWL and the node N2. The transistor Tr2 receives a control signal S11 at a gate electrode, for example, from a readout control circuit ROC.
運算放大器OP於非反轉輸入端子與節點N3連接。運算放大器OP於反轉輸入端子與節點N4連接。運算放大器OP之輸出OUT為表示記憶於連接有運算放大器OP之記憶胞陣列MA中之讀出對象之記憶胞MC之資料的1位元資料。The operational amplifier OP is connected to the node N3 at a non-inverting input terminal. The operational amplifier OP is connected to the node N4 at an inverting input terminal. The output OUT of the operational amplifier OP is 1-bit data representing data stored in the memory cell MC of the read target in the memory cell array MA connected to the operational amplifier OP.
電壓調整電路VMC為使接收到之電壓偏移，輸出偏移後之電壓之電路。電壓調整電路VMC於第1輸入中與節點N1連接。電壓調整電路VMC於第2輸入中與節點N2連接。電壓調整電路VMC於第1輸出中與節點N3連接。電壓調整電路VMC於第2輸出中與節點N4連接。The voltage regulating circuit VMC is a circuit that offsets the received voltage and outputs the offset voltage. The voltage regulating circuit VMC is connected to the node N1 at the first input. The voltage regulating circuit VMC is connected to the node N2 at the second input. The voltage regulating circuit VMC is connected to the node N3 at the first output. The voltage regulating circuit VMC is connected to the node N4 at the second output.
電壓調整電路VMC具有如下構成：可使用運算放大器OP判別節點N1之電壓與節點N2之電壓實質相等之情形及節點N1之電壓與節點N2之電壓不同之情形。因此，電壓調整電路VMC對節點N3施加以預先規定之方法調整節點N1之電壓後之大小之電壓，及(或)對節點N4施加以預先規定之方法調整節點N2之電壓後之大小之電壓。調整方法為任意，以下記述一例，後續之記述基於該例。The voltage adjustment circuit VMC has the following structure: the operational amplifier OP can be used to distinguish the situation where the voltage of the node N1 is substantially equal to the voltage of the node N2 and the situation where the voltage of the node N1 is different from the voltage of the node N2. Therefore, the voltage adjustment circuit VMC applies a voltage of a magnitude adjusted by a predetermined method to the node N3, and (or) applies a voltage of a magnitude adjusted by a predetermined method to the node N2 to the node N4. The adjustment method is arbitrary, and an example is described below, and the subsequent description is based on this example.
電壓調整電路VMC於節點N1之電壓與節點N2之電壓實質相同之情形時，使一者之電壓偏移，於節點N3中輸出節點N1之電壓或節點N1之電壓大小的偏移後之大小之電壓，及(或)於節點N4中輸出節點N2之電壓或節點N2之電壓大小的偏移後之大小之電壓。某要件A與某要件B「實質相同」意指雖意圖相同，但容許因不可避免之誤差等而要件A與要件B不完全相同。When the voltage at node N1 and the voltage at node N2 are substantially the same, the voltage adjustment circuit VMC offsets the voltage of one of them, outputs the voltage at node N1 or a voltage of the magnitude of the voltage at node N1 at node N3, and (or) outputs the voltage at node N2 or a voltage of the magnitude of the voltage at node N2 at node N4. "Substantially the same" between a certain requirement A and a certain requirement B means that although the intention is the same, it is allowed that the requirements A and B are not completely the same due to unavoidable errors.
電壓調整電路VMC例如對節點N3施加節點N1之電壓於負方向偏移△V大小之電壓，對節點N4施加與節點N2之電壓實質相同大小之電壓。△V小於低保持電壓VhdL與高保持電壓VhdH之差。The voltage regulating circuit VMC applies a voltage of △V offset in the negative direction of the voltage of the node N1 to the node N3, and applies a voltage substantially the same as the voltage of the node N2 to the node N4. △V is smaller than the difference between the low holding voltage VhdL and the high holding voltage VhdH.
1.2.動作 圖9按時間顯示第1實施形態之記憶裝置1中之資料讀出期間之若干配線之電位。圖9顯示與包含資料讀出對象之記憶胞(讀出對象記憶胞)MC之子核心電路SCC連接之1個全域位元線GBL及1個全域字元線GWL。圖9還於下部按時間顯示第1實施形態之記憶裝置1之資料讀出期間流過讀出對象記憶胞MC之電流。圖9之下部顯示於縱軸之電流為正之區域，自參照層35朝向記憶層37之方向即AP方向之電流。圖9之下部顯示於縱軸之電流為負之區域，自記憶層37朝向參照層35之方向即P方向之電流。以下之記述中，對某配線施加某電壓之主旨之記述指持續施加該電壓直到施加另外電壓為止。1.2. OperationFIG. 9 shows the potentials of several wirings during the data read period in the memory device 1 of the first embodiment over time. FIG. 9 shows a global bit line GBL and a global word line GWL connected to the sub-core circuit SCC including the memory cell MC of the data read object (read object memory cell). FIG. 9 also shows the current flowing through the read object memory cell MC during the data read period of the memory device 1 of the first embodiment over time at the bottom. The lower part of FIG. 9 shows the current in the direction from the reference layer 35 toward the memory layer 37, i.e., the AP direction, in the area where the current on the vertical axis is positive. The lower part of Figure 9 shows the current in the negative vertical current region, which is the current in the P direction from the memory layer 37 toward the reference layer 35. In the following description, the description of applying a certain voltage to a certain wiring means that the voltage is continuously applied until another voltage is applied.
於開始資料讀出之時點，全域字元線GWL由驅動器電路RDUW施加非選擇電壓Vusel，而被充電成非選擇電壓Vusel。其可藉由將驅動器電路RDUW之開關SW5維持接通，將其他開關SW4及SW6維持斷開而進行。又，全域位元線GBL由驅動器電路RDUB施加非選擇電壓Vusel，而被充電成非選擇電壓Vusel。其可藉由將驅動器電路RDUB之開關SW2維持接通，將其他開關SW1及SW3維持斷開而進行。At the time of starting data reading, the global word line GWL is charged to the non-selection voltage Vusel by the driver circuit RDUW. This can be done by keeping the switch SW5 of the driver circuit RDUW turned on and keeping the other switches SW4 and SW6 turned off. In addition, the global bit line GBL is charged to the non-selection voltage Vusel by the driver circuit RDUB. This can be done by keeping the switch SW2 of the driver circuit RDUB turned on and keeping the other switches SW1 and SW3 turned off.
隨著開始自讀出對象記憶胞MC讀出資料，讀出對象記憶胞MC經由局域位元線LBL(導電體22)連接於全域位元線GBL，且經由局域字元線LWL(導電體21)連接於全域字元線GWL。As data starts to be read from the read target memory cell MC, the read target memory cell MC is connected to the global bit line GBL via the local bit line LBL (conductor 22) and is connected to the global word line GWL via the local word line LWL (conductor 21).
如圖9所示，自時刻t0起為第1感測期間。於時刻t0，藉由驅動器電路RDPW對全域字元線GWL施加預充電電壓Vpcap。其可藉由將驅動器電路RDPW之開關SW6維持接通，將其他開關SW4及SW5維持斷開而進行。藉由施加預充電電壓Vpcap，藉此，全域字元線GWL被充電成預充電電壓Vpcap。其後，藉由驅動器電路RDPW之開關SW1斷開，將全域字元線GWL設為浮動。As shown in FIG9 , the first sensing period starts from time t0. At time t0, the driver circuit RDPW applies a precharge voltage Vpcap to the global word line GWL. This can be done by keeping the switch SW6 of the driver circuit RDPW turned on and keeping the other switches SW4 and SW5 turned off. By applying the precharge voltage Vpcap, the global word line GWL is charged to the precharge voltage Vpcap. Thereafter, the switch SW1 of the driver circuit RDPW is turned off, and the global word line GWL is set to float.
於時刻t1，藉由同步電路RDSB對全域位元線GBL施加接地電壓Vss。其可藉由將同步電路RDSB之開關SW4維持接通，將其他開關SW5及SW6維持斷開而進行。此時之狀態模式性顯示於圖10。再者，如圖10所示，藉由電晶體Tr1維持斷開，全域位元線GBL與節點N1切斷。又，藉由電晶體Tr2維持接通，全域字元線GWL連接於節點N2。圖10及後續之圖11中，未描繪斷開之電晶體，以實線表示接通之電晶體。At time t1, the ground voltage Vss is applied to the global bit line GBL by the synchronous circuit RDSB. This can be done by keeping the switch SW4 of the synchronous circuit RDSB turned on and keeping the other switches SW5 and SW6 turned off. The state at this time is schematically shown in FIG10. Furthermore, as shown in FIG10, by keeping the transistor Tr1 turned off, the global bit line GBL is disconnected from the node N1. Moreover, by keeping the transistor Tr2 turned on, the global word line GWL is connected to the node N2. In FIG10 and the subsequent FIG11, the transistors that are turned off are not depicted, and the transistors that are turned on are represented by solid lines.
藉由對全域位元線GBL施加接地電壓Vss，對讀出對象記憶胞MC之兩端施加Vpcap-Vss之大小之電壓，即預充電電壓Vpcap。其結果，讀出對象記憶胞MC之開關元件SE接通，如圖9之下部及圖10所示，自參照層35向記憶層37即於AP方向流動讀出電流Irap。藉由讀出電流Irap，全域字元線GWL之電位降低。其結果，讀出對象記憶胞MC之兩端之電位差降低。讀出電流Irap之大小於時刻t1之後立即達到峰值，之後逐漸降低。By applying the ground voltage Vss to the global bit line GBL, a voltage of Vpcap-Vss, i.e., the pre-charge voltage Vpcap, is applied to both ends of the read target memory cell MC. As a result, the switch element SE of the read target memory cell MC is turned on, and as shown in the lower part of FIG. 9 and FIG. 10, the read current Irap flows from the reference layer 35 to the memory layer 37, i.e., in the AP direction. The potential of the global word line GWL is reduced by the read current Irap. As a result, the potential difference between the two ends of the read target memory cell MC is reduced. The magnitude of the read current Irap reaches a peak immediately after the moment t1, and then gradually decreases.
若讀出對象記憶胞MC兩端之電位差降低至某大小，則讀出對象記憶胞MC之開關元件SE斷開。其結果，讀出對象記憶胞MC之開關元件SE斷開時之全域字元線GWL之電位保存於全域字元線GWL。保存之電位係低保持電位VhdL及高保持電壓VhdH中基於讀出對象記憶胞MC之電阻狀態之一者。再者，感測放大器電路SAC之電晶體Tr2斷開。其結果，於節點N2保存全域字元線GWL之電位。If the potential difference between the two ends of the read target memory cell MC is reduced to a certain value, the switch element SE of the read target memory cell MC is turned off. As a result, the potential of the global word line GWL when the switch element SE of the read target memory cell MC is turned off is stored in the global word line GWL. The stored potential is one of the low holding potential VhdL and the high holding voltage VhdH based on the resistance state of the read target memory cell MC. Furthermore, the transistor Tr2 of the sense amplifier circuit SAC is turned off. As a result, the potential of the global word line GWL is stored at the node N2.
如圖9所示，於時刻t2，對全域字元線GWL施加非選擇電壓Vusel。於時刻t3，對全域位元線GBL施加非選擇電壓Vusel。As shown in FIG9 , at time t2, a non-select voltage Vusel is applied to the global word line GWL, and at time t3, a non-select voltage Vusel is applied to the global bit line GBL.
自時刻t4起為參照資料寫入及第2感測之期間。於時刻t4，藉由驅動器電路RDPB對全域位元線GBL施加預充電電壓Vpcp。其可藉由將驅動器電路RDPB之開關SW3維持接通，且將其他開關SW1及SW2維持斷開而進行。藉由施加預充電電壓Vpcp，將全域位元線GBL充電成預充電電壓Vpcp。其後，藉由驅動器電路RDPB之開關SW3斷開，將全域位元線GBL設為浮動。From time t4, it is the period of reference data writing and second sensing. At time t4, the precharge voltage Vpcp is applied to the global bit line GBL by the driver circuit RDPB. This can be done by keeping the switch SW3 of the driver circuit RDPB turned on and keeping the other switches SW1 and SW2 turned off. By applying the precharge voltage Vpcp, the global bit line GBL is charged to the precharge voltage Vpcp. Thereafter, by turning off the switch SW3 of the driver circuit RDPB, the global bit line GBL is set to floating.
於時刻t5，藉由同步電路RDSW對全域字元線GWL施加接地電壓Vss。其可藉由將同步電路RDSW之開關SW4維持接通，且將其他開關SW5及SW6維持斷開而進行。此時之狀態模式性顯示於圖11。再者，如圖11所示，藉由電晶體Tr1維持接通，全域位元線GBL連接於節點N1。又，藉由電晶體Tr2維持斷開，全域字元線GWL與節點N2切斷。At time t5, the ground voltage Vss is applied to the global word line GWL by the synchronous circuit RDSW. This can be done by keeping the switch SW4 of the synchronous circuit RDSW turned on and keeping the other switches SW5 and SW6 turned off. The state at this time is schematically shown in FIG11. Furthermore, as shown in FIG11, by keeping the transistor Tr1 turned on, the global bit line GBL is connected to the node N1. Moreover, by keeping the transistor Tr2 turned off, the global word line GWL is disconnected from the node N2.
藉由對全域字元線GWL施加接地電壓Vss，對讀出對象記憶胞MC之兩端施加Vpcp-Vss之大小之電壓，即預充電電壓Vpcp。其結果，讀出對象記憶胞MC之開關元件SE接通，如圖9之下部及圖11所示，自記憶層37向參照層35即於P方向流動讀出電流Irp。讀出電流Irp流過讀出對象記憶胞MC。如參照圖7所記述，預充電電壓Vpcp具有如下之大小，可藉由施加於1個記憶胞MC，使超過P方向開關電流Icp大小的大小之電流流過該記憶胞MC。因此，讀出電流Irp之大小大於P方向開關電流Icp之大小。因此，藉由讀出電流Irp，讀出對象記憶胞MC之MTJ元件MTJ成為P狀態。By applying the ground voltage Vss to the global word line GWL, a voltage of Vpcp-Vss, i.e., a precharge voltage Vpcp, is applied to both ends of the read target memory cell MC. As a result, the switch element SE of the read target memory cell MC is turned on, and as shown in the lower part of FIG. 9 and FIG. 11, a read current Irp flows from the memory layer 37 to the reference layer 35, i.e., in the P direction. The read current Irp flows through the read target memory cell MC. As described with reference to FIG. 7, the precharge voltage Vpcp has the following magnitude, and by being applied to one memory cell MC, a current exceeding the magnitude of the P direction switch current Icp can flow through the memory cell MC. Therefore, the magnitude of the read current Irp is greater than the magnitude of the P-direction switch current Icp. Therefore, by the read current Irp, the MTJ element MTJ of the read-out target memory cell MC becomes the P state.
再者，藉由讀出電流Irp，全域位元線GBL之電位降低。其結果，讀出對象記憶胞MC之兩端之電位差降低。讀出電流Irp之大小於時刻t5之後立即達到峰值，之後逐漸降低。讀出電流Irp之大小之峰值大於讀出電流Irap之大小之峰值。Furthermore, the potential of the global bit line GBL is reduced by the read current Irp. As a result, the potential difference between the two ends of the read target memory cell MC is reduced. The magnitude of the read current Irp reaches a peak value immediately after the moment t5, and then gradually decreases. The peak value of the magnitude of the read current Irp is greater than the peak value of the magnitude of the read current Irap.
若讀出對象記憶胞MC兩端之電位差降低至某大小，則讀出對象記憶胞MC之開關元件SE斷開。其結果，讀出對象記憶胞MC之開關元件SE斷開時之全域位元線GBL之電位保存於全域位元線GBL。由於讀出對象記憶胞MC之MTJ元件MTJ為P狀態，故保存之電位為低保持電壓VhdL。再者，感測放大器電路SAC之電晶體Tr1斷開。其結果，於節點N1保存全域位元線GBL之電位。If the potential difference between the two ends of the read target memory cell MC is reduced to a certain value, the switch element SE of the read target memory cell MC is turned off. As a result, the potential of the global bit line GBL when the switch element SE of the read target memory cell MC is turned off is stored in the global bit line GBL. Since the MTJ element MTJ of the read target memory cell MC is in the P state, the stored potential is the low holding voltage VhdL. Furthermore, the transistor Tr1 of the sense amplifier circuit SAC is turned off. As a result, the potential of the global bit line GBL is stored at the node N1.
如圖9所示，於時刻t6，對全域位元線GBL施加非選擇電壓Vusel。於時刻t7，對全域字元線GWL施加非選擇電壓Vusel。As shown in FIG9 , at time t6, a non-select voltage Vusel is applied to the global bit line GBL, and at time t7, a non-select voltage Vusel is applied to the global word line GWL.
於時刻t5之後，運算放大器OP例如由讀出控制電路ROC設為啟動。其結果，自運算放大器OP輸出基於資料讀出開始時點之讀出對象記憶胞MC之MTJ元件MTJ之電阻狀態之大小的輸出OUT。即，若MTJ元件MTJ為低電阻狀態，則運算放大器OP輸出L位準之輸出OUT。另一方面，若MTJ元件MTJ為高電阻狀態，則運算放大器OP輸出H位準之輸出OUT。如此，記憶於讀出對象記憶胞MC之資料之讀出完成。After time t5, the operational amplifier OP is set to be activated by, for example, the read control circuit ROC. As a result, the operational amplifier OP outputs an output OUT based on the size of the resistance state of the MTJ element MTJ of the read target memory cell MC at the start time of data reading. That is, if the MTJ element MTJ is in a low resistance state, the operational amplifier OP outputs an output OUT of an L level. On the other hand, if the MTJ element MTJ is in a high resistance state, the operational amplifier OP outputs an output OUT of an H level. In this way, the reading of the data stored in the read target memory cell MC is completed.
1.3.優點(效果) 根據第1實施形態，如以下所記述，可提供一種於短時間讀出資料之記憶裝置。1.3. Advantages (Effects)According to the first embodiment, as described below, a memory device that can read out data in a short time can be provided.
為了比較及參考，記述記憶裝置100之概要。資料讀出與第1實施形態相同，可藉由比較如下之電壓而進行，即：藉由第1感測而得之基於記憶於讀出對象記憶胞之資料之電壓；藉由對寫入有參照資料之讀出對象記憶胞之第2感測而得之電壓。有將該方式稱為自參照方式之情形。For comparison and reference, the outline of the memory device 100 is described. Data reading is similar to the first embodiment and can be performed by comparing the voltage based on the data stored in the read target memory cell obtained by the first sensing and the voltage obtained by the second sensing of the read target memory cell in which the reference data is written. This method is sometimes called a self-reference method.
圖12與圖9同樣，按時間顯示記憶裝置100之資料讀出期間之若干配線之電位。如圖12所示，根據與第1實施形態(圖9)相同之方法，於自時刻t0至時刻t2之期間進行第1感測。一般而言，用以將MTJ元件設為AP狀態之開關電流大於用以將MTJ元件設為P狀態之開關電流。因此，為了抑制讀出干擾，用於以第1感測之讀出電流於AP方向流動。FIG12 is similar to FIG9, and shows the potential of several wirings during the data readout period of the memory device 100 in time. As shown in FIG12, the first sensing is performed from time t0 to time t2 according to the same method as the first embodiment (FIG9). Generally speaking, the switch current used to set the MTJ element to the AP state is greater than the switch current used to set the MTJ element to the P state. Therefore, in order to suppress the readout interference, the readout current used for the first sensing flows in the AP direction.
於自時刻t2後之時刻t11至時刻t12之期間，寫入參照資料。於自時刻t12後之時刻t13至時刻t15之期間，以與自時刻t0至時刻t2之第1感測相同之方法進行第2感測。為了抑制讀出干擾，用於第2感測之讀出電流亦於AP方向流動。時刻t15之後，基於藉由第1感測而得之電壓與藉由第2感測而得之電壓，以與第1實施形態相同之方法，可獲得表示記憶於讀出對象記憶胞之資料之信號。藉由自參照方式之資料讀出，可抑制因不可避免之記憶胞之特性偏差引起之資料讀出結果之偏差。這是因為比較基於讀出對象記憶胞中記憶的是未知之“0”資料或“1”資料之哪一者之電壓、與自身記憶有“0”資料時而得之電壓。During the period from time t11 after time t2 to time t12, reference data is written. During the period from time t13 after time t12 to time t15, the second sensing is performed in the same manner as the first sensing from time t0 to time t2. In order to suppress readout interference, the readout current used for the second sensing also flows in the AP direction. After time t15, based on the voltage obtained by the first sensing and the voltage obtained by the second sensing, a signal representing the data stored in the readout target memory cell can be obtained in the same manner as the first implementation form. By reading out data in a self-reference manner, the deviation of the data reading result caused by the inevitable deviation of the characteristics of the memory cell can be suppressed. This is because the comparison is based on the voltage of reading out whether the target memory cell stores unknown "0" data or "1" data, and the voltage obtained when the memory itself stores "0" data.
然而，如由圖12而明確，因自參照方式需要寫入參照資料。這會延長資料讀出所需之時間。However, as is clear from FIG. 12 , since the self-reference method requires writing reference data, this will extend the time required to read the data.
根據第1實施形態，第1感測後，不進行參照資料寫入。取而代之，繼第1感測後進行第2感測，第2感測中，於P方向流動且可將讀出對象記憶胞MC之MTJ元件MTJ設為P狀態之大小之讀出電流Irp流動至讀出對象記憶胞MC。藉由讀出電流Irp，讀出對象記憶胞MC之MTJ元件MTJ被設為P狀態，接著，藉由讀出電流Irp，對包含P狀態之MTJ元件MTJ之讀出對象記憶胞MC進行第2感測。此種資料讀出無須如圖12之用於參照資料寫入之專用時間。藉此，如圖12與第1實施形態之圖9之比較而明確，根據第1實施形態，可以較參考用記憶裝置100之資料讀出短之時間讀出資料。再者，由於使用了自參照方式，故亦抑制因記憶胞之特性偏差引起之資料讀出結果之偏差。According to the first implementation form, after the first sensing, reference data is not written. Instead, the second sensing is performed after the first sensing, and in the second sensing, a read current Irp that flows in the P direction and has a size that can set the MTJ element MTJ of the read target memory cell MC to the P state flows to the read target memory cell MC. The MTJ element MTJ of the read target memory cell MC is set to the P state by the read current Irp, and then, the second sensing is performed on the read target memory cell MC including the MTJ element MTJ in the P state by the read current Irp. This type of data reading does not require a dedicated time for reference data writing as shown in FIG. 12 . 12 and FIG. 9 of the first embodiment, the first embodiment can read data in a shorter time than the data read of the reference memory device 100. Furthermore, since the self-reference method is used, the variation of the data read result caused by the variation of the characteristics of the memory cell is also suppressed.
1.4.變化例 藉由驅動器電路RDUB、RDPB、RDUW或RDPW施加電壓可以各種方法進行。作為第1方法，如參照圖7所記述，藉由驅動器電路產生期望施加之電壓，將產生之電壓經由開關即開關SW2、SW3、SW5或SW6傳輸至配線。1.4. VariationsThe voltage applied by the driver circuit RDUB, RDPB, RDUW or RDPW can be performed in various ways. As a first method, as described with reference to FIG. 7, the desired voltage is generated by the driver circuit, and the generated voltage is transmitted to the wiring via a switch, namely, switch SW2, SW3, SW5 or SW6.
作為第2方法，於配線經由n型MOSFET連接與期望傳輸之電壓不同之基準電壓(例如內部電源電壓)之節點。且，藉由調整MOSFET之閘極電壓，對配線施加藉由基準電壓下降產生之期望傳輸之大小之電壓。以下，有將第2方法稱為閘極偏壓方式之情形。As the second method, a node of a reference voltage (e.g., internal power supply voltage) different from the voltage to be transmitted is connected to the wiring via an n-type MOSFET. Then, by adjusting the gate voltage of the MOSFET, a voltage of the magnitude of the desired transmission generated by the reference voltage drop is applied to the wiring. Hereinafter, the second method may be referred to as the gate bias method.
2.第2實施形態 第2實施形態附加於第1實施形態而進行。第2實施形態係關於讀出電流流動之路徑之電阻之大小調整。2. Second Implementation FormThe second implementation form is performed in addition to the first implementation form. The second implementation form is related to the adjustment of the size of the resistance of the path where the current flows.
2.1.構造(構成) 第2實施形態之記憶裝置1b包含核心電路11b，而取代第1實施形態之核心電路11。2.1. StructureThe memory device 1b of the second embodiment includes a core circuit 11b instead of the core circuit 11 of the first embodiment.
圖13顯示第2實施形態之核心電路11b之功能區塊。圖3與第1實施形態之圖2相同，僅顯示1個子核心電路SCC、1個全域字元線GWL、1個全域位元線GBL、1個讀出電路RC以及1個寫入電路WC。如圖3所示，核心電路11b包含1個以上子核心電路SCCb。子核心電路SCCb除記憶胞陣列MA、列選擇器RS及行選擇器CS外，還包含子全域字元線GWLI、GWL電阻調整電路WRA、子全域位元線GBLI及GBL電阻調整電路BRA。FIG13 shows the functional blocks of the core circuit 11b of the second embodiment. FIG3 is the same as FIG2 of the first embodiment, and only shows one sub-core circuit SCC, one global word line GWL, one global bit line GBL, one read circuit RC, and one write circuit WC. As shown in FIG3, the core circuit 11b includes one or more sub-core circuits SCCb. The sub-core circuit SCCb includes a sub-global word line GWLI, a GWL resistance adjustment circuit WRA, a sub-global bit line GBLI, and a GBL resistance adjustment circuit BRA in addition to a memory cell array MA, a column selector RS, and a row selector CS.
列選擇器RS接收列位址，基於接收到之列位置，將對應之記憶胞陣列MA之局域字元線LWL之一者連接於1個子全域字元線GWLI。The row selector RS receives the row address, and based on the received row position, connects one of the local word lines LWL of the corresponding memory cell array MA to one sub-global word line GWLI.
行選擇器CS接收行位址，基於接收到之行位置，將對應之記憶胞陣列MA之局域位元線LBL之一者連接於1個子全域位元線GBLI。The row selector CS receives the row address, and based on the received row position, connects one of the local bit lines LBL of the corresponding memory cell array MA to one sub-global bit line GBLI.
GWL電阻調整電路WRA為調整全域字元線GWL與子全域字元線GWLI之間之電阻之電路。GWL電阻調整電路WRA連接於全域字元線GWL與子全域字元線GWLI之間。GWL電阻調整電路WRA以可動態變更全域字元線GWL與子全域字元線GWLI之間之電阻之方式構成。GWL電阻調整電路WRA接收行位址，基於接收到之行位址，動態變更全域字元線GWL與子全域字元線GWLI之間之電阻。The GWL resistance adjustment circuit WRA is a circuit for adjusting the resistance between the global word line GWL and the sub-global word line GWLI. The GWL resistance adjustment circuit WRA is connected between the global word line GWL and the sub-global word line GWLI. The GWL resistance adjustment circuit WRA is configured to dynamically change the resistance between the global word line GWL and the sub-global word line GWLI. The GWL resistance adjustment circuit WRA receives a row address and dynamically changes the resistance between the global word line GWL and the sub-global word line GWLI based on the received row address.
GBL電阻調整電路BRA為調整全域位元線GBL與子全域位元線GBLI之間之電阻之電路。GBL電阻調整電路BRA連接於全域位元線GBL與子全域位元線GBLI之間。GBL電阻調整電路BRA以可動態變更全域位元線GBL與子全域位元線GBLI之間之電阻之方式構成。GBL電阻調整電路BRA接收列位址，基於接收到之列位址，動態變更全域位元線GBL與子全域位元線GBLI之間之電阻。The GBL resistance adjustment circuit BRA is a circuit for adjusting the resistance between the global bit line GBL and the sub-global bit line GBLI. The GBL resistance adjustment circuit BRA is connected between the global bit line GBL and the sub-global bit line GBLI. The GBL resistance adjustment circuit BRA is configured to dynamically change the resistance between the global bit line GBL and the sub-global bit line GBLI. The GBL resistance adjustment circuit BRA receives a column address and dynamically changes the resistance between the global bit line GBL and the sub-global bit line GBLI based on the received column address.
圖14係第2實施形態之GWL電阻調整電路WRA及列選擇器RS之電路圖。圖14亦一併顯示第2實施形態之解碼電路14b。Fig. 14 is a circuit diagram of a GWL resistance adjustment circuit WRA and a column selector RS of the second embodiment. Fig. 14 also shows a decoding circuit 14b of the second embodiment.
如圖14所示，列選擇器RS包含n型MOSFET TA0～TAM。電晶體TA0～TAM分別於一端與局域字元線LWL＜0＞～LWL＜M＞連接。電晶體TA0～TAM於另一端與子全域字元線GWLI連接。電晶體TA0～TAM各自於閘極自解碼電路14b接收控制信號。藉由來自解碼電路14b之控制信號之一者確立，接收已確立之信號之1個電晶體TA與子全域字元線GWLI連接。解碼電路14b確立由供給至電晶體TA0～TAM之複數個控制信號中之列位址規定之一者。As shown in FIG. 14 , the column selector RS includes n-type MOSFETs TA0 to TAM. Transistors TA0 to TAM are connected to local word lines LWL<0> to LWL<M> at one end, respectively. Transistors TA0 to TAM are connected to sub-global word lines GWLI at the other end. Transistors TA0 to TAM each receive a control signal at a gate from a decoding circuit 14b. One transistor TA receiving the established signal is established by one of the control signals from the decoding circuit 14b, and is connected to the sub-global word line GWLI. The decoding circuit 14b establishes one of the column address specifications from the plurality of control signals supplied to the transistors TA0 to TAM.
電晶體TA0～TAN具有實質相同之接通電阻。因此，例如電晶體TA0～TAN具有實質相同尺寸及實質相同濃度之雜質，藉由共通之製程形成。The transistors TA0-TAN have substantially the same on-resistance. Therefore, for example, the transistors TA0-TAN have substantially the same size and substantially the same concentration of impurities and are formed by a common process.
GWL電阻調整電路WRA將J設為1以上之整數，包含n型MOSFET、TB0～TBJ及開關SC0～SCj。電晶體TB0～TBJ依「TBα」之「α」之升序串聯連接。電晶體TB0～TBJ之串聯構造於電晶體TB0中與子全域字元線GWLI連接，於電晶體TBJ中與全域字元線GWL連接。電晶體TB0～TBJ分別於閘極自解碼電路14b接收控制信號NB0～NBJ。解碼電路14b基於行位址產生控制信號NB0～NBJ。The GWL resistance adjustment circuit WRA sets J to an integer greater than 1, and includes an n-type MOSFET, TB0~TBJ, and switches SC0~SCj. The transistors TB0~TBJ are connected in series in ascending order of "α" of "TBα". The series structure of the transistors TB0~TBJ is connected to the sub-global word line GWLI in the transistor TB0, and is connected to the global word line GWL in the transistor TBJ. The transistors TB0~TBJ receive control signals NB0~NBJ at the gate self-decoding circuit 14b, respectively. The decoding circuit 14b generates control signals NB0~NBJ based on the row address.
開關SC0於一端與子全域字元線GWLI連接，於另一端與全域字元線GWL連接。對於α為1以上J以下之整數之所有實例，將β設為α-1，開關SCα於一端與連接有電晶體TBα及電晶體TBβ之節點連接，另一端與全域字元線GWL連接。開關SC0～SCJ分別自解碼電路14b接收控制信號NC0～NCJ，基於控制信號NC0～NCJ接通或斷開。解碼電路14b基於行位址產生控制信號NC0～NCJ。The switch SC0 is connected to the sub-global word line GWLI at one end and to the global word line GWL at the other end. For all instances where α is an integer greater than 1 and less than J, β is set to α-1, and the switch SCα is connected to the node connected to the transistor TBα and the transistor TBβ at one end and to the global word line GWL at the other end. The switches SC0-SCJ receive control signals NC0-NCJ from the decoding circuit 14b, respectively, and are turned on or off based on the control signals NC0-NCJ. The decoding circuit 14b generates the control signals NC0-NCJ based on the row address.
圖15係第2實施形態之GBL電阻調整電路BRA及行選擇器CS之電路圖。圖15亦一併顯示解碼電路14b。Fig. 15 is a circuit diagram of the GBL resistance adjustment circuit BRA and the row selector CS of the second embodiment. Fig. 15 also shows the decoding circuit 14b.
如圖15所示，行選擇器CS包含n型MOSFET TD0～TDN。電晶體TD0～TDN分別於一端與局域位元線LBL＜0＞～LBL＜N＞連接。電晶體TD0～TDN於另一端與子全域位元線GBLI連接。電晶體TD0～TDN各自於閘極自解碼電路14b接收控制信號。藉由來自解碼電路14b之控制信號之一者確立，接收確立之信號之1個電晶體TD與子全域位元線GBLI連接。解碼電路14b確立供給至電晶體TD0～TDN之複數個控制信號中藉由行位址規定之一者。As shown in FIG. 15 , the row selector CS includes n-type MOSFETs TD0 to TDN. Transistors TD0 to TDN are connected to local bit lines LBL<0> to LBL<N> at one end, respectively. Transistors TD0 to TDN are connected to sub-global bit lines GBLI at the other end. Transistors TD0 to TDN each receive a control signal at the gate from the decoding circuit 14b. One transistor TD receiving the confirmed signal is connected to the sub-global bit line GBLI by being confirmed by one of the control signals from the decoding circuit 14b. The decoding circuit 14b confirms one of the multiple control signals supplied to transistors TD0 to TDN specified by the row address.
電晶體TD0～TDN具有實質相同之電阻。因此，例如電晶體TD0～TDN具有實質相同尺寸及實質相同濃度之雜質，藉由共通之製程形成。Transistors TD0 to TDN have substantially the same resistance. Therefore, for example, transistors TD0 to TDN have substantially the same size and substantially the same concentration of impurities and are formed by a common process.
GBL電阻調整電路BRA將K設為1以上之整數，包含n型MOSFET TE0～TEK及開關SF0～SFK。電晶體TE0～TEK依「TEγβ」之「γ」之升序串聯連接。電晶體TE0～TEK之串聯構造於電晶體TE0中與子全域位元線GBLI連接，於電晶體TEK中與全域位元線GBL連接。電晶體TE0～TEK分別於閘極自解碼電路14b接收控制信號NE0～NEK。解碼電路14b基於列位址產生控制信號NE0～NEK。The GBL resistance adjustment circuit BRA sets K to an integer greater than 1, and includes n-type MOSFETs TE0-TEK and switches SF0-SFK. The transistors TE0-TEK are connected in series in ascending order of "γ" of "TEγβ". The series structure of the transistors TE0-TEK is connected to the sub-global bit line GBLI in the transistor TE0, and is connected to the global bit line GBL in the transistor TEK. The transistors TE0-TEK receive control signals NE0-NEK at the gate self-decoding circuit 14b, respectively. The decoding circuit 14b generates control signals NE0-NEK based on the column address.
開關SF0於一端與子全域位元線GBLI連接，於另一端與全域位元線GBL連接。對於γ為1以上K以下之整數之所有實例，將ε設為γ-1，開關SEγ於一端與連接有電晶體TEγ及電晶體TEε之節點連接，於另一端與全域位元線GBL連接。開關SF0～SFK分別自解碼電路14b接收控制信號NF0～NFK，基於控制信號NF0～NFK接通或斷開。解碼電路14b基於列位址產生控制信號NF0～NFK。The switch SF0 is connected to the sub-global bit line GBLI at one end and to the global bit line GBL at the other end. For all instances where γ is an integer greater than 1 and less than K, ε is set to γ-1, and the switch SEγ is connected to the node connected to the transistor TEγ and the transistor TEε at one end and to the global bit line GBL at the other end. The switches SF0 to SFK receive control signals NF0 to NFK from the decoding circuit 14b, respectively, and are turned on or off based on the control signals NF0 to NFK. The decoding circuit 14b generates the control signals NF0 to NFK based on the column address.
圖16顯示第2實施形態之解碼電路14b之功能區塊。如圖16所示，解碼電路14b包含控制信號產生電路14b1及14b2。控制信號產生電路14b1接收行位址，基於接收到之行位址，產生控制信號NB0～NBJ及控制信號NC0～NCJ。控制信號產生電路14b2接收列位址，基於接收到之列位址，產生控制信號NE0～NEK及控制信號NF0～NFK。FIG16 shows the functional blocks of the decoding circuit 14b of the second embodiment. As shown in FIG16, the decoding circuit 14b includes control signal generating circuits 14b1 and 14b2. The control signal generating circuit 14b1 receives a row address and generates control signals NB0 to NBJ and control signals NC0 to NCJ based on the received row address. The control signal generating circuit 14b2 receives a column address and generates control signals NE0 to NEK and control signals NF0 to NFK based on the received column address.
2.2.動作 2.2.1.GWL電阻調整電路WRA 圖17及圖18分別顯示第2實施形態之GWL電阻調整電路WRA之動作期間之一狀態之例。圖17及圖18顯示於第1感測或參照資料寫入及第2感測期間所形成之狀態之例。圖17及圖18以虛線表示斷開之電晶體TB及斷開之開關SC。圖17及圖18以實線表示接通之電晶體TB。圖17及圖18以連結開關SC之兩端之實線表示接通之該開關SC。2.2. Operation2.2.1. GWL resistance adjustment circuit WRAFigures 17 and 18 show an example of a state during the operation of the GWL resistance adjustment circuit WRA of the second embodiment. Figures 17 and 18 show an example of a state formed during the first sensing or reference data writing and the second sensing. Figures 17 and 18 use dotted lines to represent the disconnected transistor TB and the disconnected switch SC. Figures 17 and 18 use solid lines to represent the connected transistor TB. Figures 17 and 18 use a solid line connecting the two ends of the switch SC to represent the connected switch SC.
GWL電阻調整電路WRA使用電晶體TB0～TBJ之接通或斷開，及開關SC0～SCJ之接通或斷開之組合，調整連結子全域字元線GWLI與全域字元線GWL之電流路徑之電阻。為此，電晶體TB0～TBJ中自子全域字元線GWLI之側起0以上串聯連接之電晶體TB全部接通。此外，開關SC0～SCJ中僅與連接有接通之電晶體TB與斷開之電晶體TB之節點連接之開關SC接通。藉此，對連結子全域字元線GWLI與全域字元線GWL之電流路徑插入接通之電晶體TB之接通電阻。藉由選擇電晶體TB0～TBJ中接通之電晶體TB之數量，可動態選擇連結子全域字元線GWLI與全域字元線GWL之電流路徑之電阻。The GWL resistance adjustment circuit WRA uses the combination of the on or off of transistors TB0 to TBJ and the on or off of switches SC0 to SCJ to adjust the resistance of the current path connecting the sub-global word line GWLI and the global word line GWL. To this end, all transistors TB connected in series from 0 or more on the side of the sub-global word line GWLI among transistors TB0 to TBJ are turned on. In addition, among switches SC0 to SCJ, only the switch SC connected to the node connecting the on transistor TB and the off transistor TB is turned on. In this way, the on resistance of the on transistor TB is inserted into the current path connecting the sub-global word line GWLI and the global word line GWL. By selecting the number of transistors TB that are turned on among transistors TB0-TBJ, the resistance of the current path connecting the sub-global word line GWLI and the global word line GWL can be dynamically selected.
為了控制GWL電阻調整電路WRA，解碼電路14b基於行位址，控制控制信號NB0～NBJ及控制信號NC0～NCJ之確立及否定。更具體而言，解碼電路14b於行位址指定有離列選擇器RS更遠之局域位元線LBL之情形時，使電晶體TB0～TBJ中更多之電晶體TB接通。In order to control the GWL resistance adjustment circuit WRA, the decoding circuit 14b controls the assertion and negation of the control signals NB0-NBJ and the control signals NC0-NCJ based on the row address. More specifically, the decoding circuit 14b turns on more transistors TB among the transistors TB0-TBJ when the row address specifies a local bit line LBL that is farther from the column selector RS.
圖17所示之例中，電晶體TB0～TBJ全部斷開，僅開關SC0～SCJ中之開關SC0接通。這可藉由將控制信號NB0～NBJ全部否定，且僅將控制信號NC0～NCJ中之控制信號NC0確立而進行。由於電晶體TB0～TBJ全部斷開且僅開關SC0接通，故連結子全域字元線GWLI與全域字元線GWL之電流路徑中未插通電晶體TB。因此，連結子全域字元線GWLI與全域字元線GWL之電流路徑之電阻亦不包含任一電晶體TB之接通電阻。In the example shown in FIG. 17 , transistors TB0 to TBJ are all turned off, and only switch SC0 among switches SC0 to SCJ is turned on. This can be done by negating all control signals NB0 to NBJ and asserting only control signal NC0 among control signals NC0 to NCJ. Since transistors TB0 to TBJ are all turned off and only switch SC0 is turned on, transistor TB is not inserted in the current path connecting sub-global word line GWLI and global word line GWL. Therefore, the resistance of the current path connecting sub-global word line GWLI and global word line GWL does not include the on-resistance of any transistor TB.
圖18所示之例中，電晶體TB0及TB1接通，僅開關SC0～SCJ中之開關SC2接通。這可藉由僅控制信號NB0～NBJ中之控制信號NB0及NB1確立，且僅控制信號NC0～NCJ中之控制信號NC2確立而進行。由於電晶體TB0及TB1接通且僅開關SC2接通，故連結子全域字元線GWLI與全域字元線GWL之電流路徑中插入有電晶體TB0及TB1。因此，連結子全域字元線GWLI與全域字元線GWL之電流路徑之電阻包含電晶體TB0及TB1各者之接通電阻之合計接通電阻RW1。一般化之記述如下所述。即，將ζ設為0以上之整數及將η設為ζ+1，將電晶體TB0～TBζ接通，且僅將開關SC0～SCJ中之開關SWη接通。In the example shown in FIG. 18 , transistors TB0 and TB1 are turned on, and only switch SC2 among switches SC0 to SCJ is turned on. This can be achieved by asserting only control signals NB0 and NB1 among control signals NB0 to NBJ, and asserting only control signal NC2 among control signals NC0 to NCJ. Since transistors TB0 and TB1 are turned on and only switch SC2 is turned on, transistors TB0 and TB1 are inserted into the current path connecting the sub-global word line GWLI and the global word line GWL. Therefore, the resistance of the current path connecting the sub-global word line GWLI and the global word line GWL includes the total on-resistance RW1 of the on-resistances of each of transistors TB0 and TB1. A generalized description is as follows. That is, ζ is set to an integer greater than 0 and η is set to ζ+1, transistors TB0~TBζ are turned on, and only switch SWη among switches SC0~SCJ is turned on.
2.2.2.GBL電阻調整電路BRA GBL電阻調整電路BRA之動作與GWL電阻調整電路WRA相同。2.2.2.GBL resistance adjustment circuit BRAThe operation of the GBL resistance adjustment circuit BRA is the same as that of the GWL resistance adjustment circuit WRA.
圖19及圖20各自顯示第2實施形態之GBL電阻調整電路BRA之動作期間之一狀態之例。圖19及圖20顯示於第1感測或參照資料寫入及第2感測期間形成之狀態之例。圖19及圖20以虛線表示斷開之電晶體TE及斷開之開關SF。圖19及圖20以實線表示接通之電晶體TE。圖19及圖20以連結該開關SF之兩端之實線表示接通之開關SF。FIG. 19 and FIG. 20 each show an example of a state during the operation of the GBL resistance adjustment circuit BRA of the second embodiment. FIG. 19 and FIG. 20 show an example of a state formed during the first sensing or reference data writing and the second sensing. FIG. 19 and FIG. 20 represent the disconnected transistor TE and the disconnected switch SF with a dotted line. FIG. 19 and FIG. 20 represent the connected transistor TE with a solid line. FIG. 19 and FIG. 20 represent the connected switch SF with a solid line connecting the two ends of the switch SF.
GBL電阻調整電路BRA使用電晶體TE0～TEK之接通或斷開，及開關SF0～SFK之接通或斷開之組合，調整連結子全域位元線GBLI與全域位元線GBL之電流路徑之電阻。因此，電晶體TE0～TEK中，自子全域位元線GBLI之側起0以上串聯連接之電晶體TE全部接通。此外，開關SF0～SFK中，僅與連接有接通之電晶體TE與斷開之電晶體TE之節點連接之開關SF接通。藉此，對連結子全域位元線GBLI與全域位元線GBL之電流路徑插入接通之電晶體TE之接通電阻。藉由選擇電晶體TE0～TEK中接通之電晶體TE之數量，可動態選擇連結子全域位元線GBLI與全域位元線GBL之電流路徑之電阻。The GBL resistance adjustment circuit BRA uses the combination of the on or off of transistors TE0 to TEK and the on or off of switches SF0 to SFK to adjust the resistance of the current path connecting the sub-global bit line GBLI and the global bit line GBL. Therefore, among the transistors TE0 to TEK, all the transistors TE connected in series from 0 or more on the side of the sub-global bit line GBLI are turned on. In addition, among the switches SF0 to SFK, only the switch SF connected to the node connecting the on transistor TE and the off transistor TE is turned on. In this way, the on resistance of the on transistor TE is inserted into the current path connecting the sub-global bit line GBLI and the global bit line GBL. By selecting the number of transistors TE that are turned on among transistors TE0-TEK, the resistance of the current path connecting the sub-global bit line GBLI and the global bit line GBL can be dynamically selected.
為了控制GBL電阻調整電路BRA，解碼電路14b基於列位址，控制控制信號NE0～NEK及控制信號NF0～NFK之確立及否定。更具體而言，解碼電路14b於列位址指定有離行選擇器CS更遠之局域字元線LWL之情形時，使電晶體TE0～TEK中之更多電晶體TE接通。In order to control the GBL resistance adjustment circuit BRA, the decoding circuit 14b controls the assertion and negation of the control signals NE0-NEK and the control signals NF0-NFK based on the column address. More specifically, the decoding circuit 14b turns on more transistors TE among the transistors TE0-TEK when the column address specifies a local word line LWL further from the row selector CS.
圖19所示之例中，電晶體TE0～TEK全部斷開，僅開關SF0～SFK中之開關SF0接通。這可藉由控制信號NE0～NEK全部否定且僅控制信號NF0～NFK中之控制信號NF0確立而進行。由於電晶體TE0～TEK全部斷開通且僅開關SF0接通，故連結子全域位元線GBLI與全域位元線GBL之電流路徑中未插入電晶體TE。因此，連結子全域位元線GBLI與全域位元線GBL之電流路徑之電阻不包含任一電晶體TE之接通電阻。In the example shown in FIG. 19 , transistors TE0 to TEK are all turned off, and only switch SF0 among switches SF0 to SFK is turned on. This can be done by negating all control signals NE0 to NEK and asserting only control signal NF0 among control signals NF0 to NFK. Since transistors TE0 to TEK are all turned off and only switch SF0 is turned on, transistor TE is not inserted in the current path connecting sub-global bit line GBLI and global bit line GBL. Therefore, the resistance of the current path connecting sub-global bit line GBLI and global bit line GBL does not include the on-resistance of any transistor TE.
圖20所示之例中，電晶體TE0、TE1及TE2接通，僅開關SF0～SFK中之開關SF3接通。這可藉由僅控制信號控制信號NE0～NEK中之控制信號NE0、NE1及NE2確立，且僅控制信號NF0～NFK中之控制信號NF3確立而進行。由於電晶體TE0、TE1及TE2接通且僅開關SF3接通，故連結子全域位元線GBLI與全域位元線GBL之電流路徑中插入有電晶體體TE0、TE1及TE2。因此，連結子全域位元線GBLI與全域位元線GBL之電流路徑之電阻包含電晶體TE0、TE1及TE2各者之接通電阻之合計接通電阻RB1。一般化之記述如下所述。即，將θ設為0以上之整數及將ι設為θ+1，將電晶體TE0～TEK中之電晶體TE0～TEθ接通，且僅將開關SF0～SFK中之開關SFι接通。In the example shown in FIG. 20 , transistors TE0, TE1, and TE2 are turned on, and only switch SF3 among switches SF0 to SFK is turned on. This can be achieved by asserting only control signals NE0, NE1, and NE2 among control signals NE0 to NEK, and asserting only control signal NF3 among control signals NF0 to NFK. Since transistors TE0, TE1, and TE2 are turned on, and only switch SF3 is turned on, transistors TE0, TE1, and TE2 are inserted into the current path connecting the sub-global bit line GBLI and the global bit line GBL. Therefore, the resistance of the current path connecting the sub-global bit line GBLI and the global bit line GBL includes the total on-resistance RB1 of the on-resistances of each of transistors TE0, TE1, and TE2. A generalized description is as follows. That is, θ is set to an integer greater than 0 and ι is set to θ+1, transistors TE0~TEθ among transistors TE0~TEK are turned on, and only switch SFι among switches SF0~SFK is turned on.
2.2.3.第1感測及第2感測期間之電阻調整 圖21及圖22各自顯示第2實施形態之記憶裝置之資料讀出期間之一狀態之例。具體而言，圖21顯示第1感測期間之列選擇器RS、行選擇器CS、GWL電阻調整電路WRA及GBL電阻調整電路BRA之一狀態之例。圖22分別顯示第2感測期間之列選擇器RS、行選擇器CS、GWL電阻調整電路WRA及GBL電阻調整電路BRA之一狀態之例。2.2.3. Resistance adjustment during the first sensing and second sensing periodsFigures 21 and 22 each show an example of a state of the memory device of the second embodiment during the data readout period. Specifically, Figure 21 shows an example of a state of the column selector RS, the row selector CS, the GWL resistance adjustment circuit WRA, and the GBL resistance adjustment circuit BRA during the first sensing period. Figure 22 shows an example of a state of the column selector RS, the row selector CS, the GWL resistance adjustment circuit WRA, and the GBL resistance adjustment circuit BRA during the second sensing period.
圖21及圖22各自顯示M=N=4之例，即顯示於各局域字元線LWL連接有4個記憶胞MC，且於各局域位元線LBL連接有4個記憶胞之例。圖21及圖22顯示資料讀出對象之記憶胞MCS與自列選擇器RS之側起第2個局域位元線LBL、及自行選擇器CS之側起第3個局域字元線LWL連接之例。有將與讀出對象記憶胞MCS連接之局域字元線LWL稱為選擇局域字元線LWLS之情形。有將與讀出對象記憶胞MCS連接之局域位元線LBL稱為選擇局域位元線LBLS之情形。FIG. 21 and FIG. 22 each show an example where M=N=4, that is, an example where 4 memory cells MC are connected to each local word line LWL, and 4 memory cells are connected to each local bit line LBL. FIG. 21 and FIG. 22 show an example where the memory cell MCS to be read out is connected to the second local bit line LBL from the side of the self-selector RS, and the third local word line LWL from the side of the self-selector CS. There is a case where the local word line LWL connected to the memory cell MCS to be read out is called a selected local word line LWLS. There is a case where the local bit line LBL connected to the memory cell MCS to be read out is called a selected local bit line LBLS.
如圖21及圖22所示，選擇局域字元線LWLS藉由與列選擇器RS中之選擇局域字元線LWLS連接之電晶體TA(未圖示)接通，而與子全域字元線GWLI連接。選擇局域位元線LBLS藉由與行選擇器CS中之選擇局域位元線LBLS連接之電晶體TD(未圖示)接通，而與子全域位元線GBLI連接。As shown in Figures 21 and 22, the selected local word line LWLS is connected to the sub-global word line GWLI by turning on the transistor TA (not shown) connected to the selected local word line LWLS in the row selector RS. The selected local bit line LBLS is connected to the sub-global bit line GBLI by turning on the transistor TD (not shown) connected to the selected local bit line LBLS in the row selector CS.
如圖21所示且參照圖10所述，為了執行第1感測，全域字元線GWL與驅動器電路RDPW連接，且全域位元線GBL與同步電路RDSB連接。As shown in FIG. 21 and described with reference to FIG. 10 , to perform the first sensing, the global word line GWL is connected to the driver circuit RDPW, and the global bit line GBL is connected to the synchronous circuit RDSB.
基於選擇局域位元線LBLS為自列選擇器RS之側起第2個局域位元線LBL之數量的電晶體TB接通。圖21顯示3個電晶體TB接通之例。再者，所有開關SC中，僅與連接有接通之電晶體TB及斷開之電晶體TB之節點連接之開關SC接通。根據此種電晶體TB及開關SC之狀態，於子全域字元線GWLI與全域字元線GWL之間，插入有3個電晶體TB之接通電阻之合計電阻ROW1。其結果，連結讀出對象記憶胞MCS與驅動器電路RDPW之電流路徑(由粗線表示)具有某大小之電阻RP1。Based on the selection of the local bit line LBLS, transistors TB of the number corresponding to the second local bit line LBL from the side of the column selector RS are turned on. FIG. 21 shows an example in which three transistors TB are turned on. Furthermore, among all switches SC, only the switch SC connected to the node to which the turned-on transistor TB and the disconnected transistor TB are connected is turned on. According to the state of such transistor TB and switch SC, a total resistance ROW1 of the turned-on resistance of the three transistors TB is inserted between the sub-global word line GWLI and the global word line GWL. As a result, the current path (indicated by the thick line) connecting the read target memory cell MCS and the driver circuit RDPW has a resistance RP1 of a certain size.
基於選擇局域字元線LWLS為自行選擇器CS之側起第3個局域字元線LWL之數量的電晶體TE接通。圖21顯示2個電晶體TE接通之例。再者，所有開關SF中，僅與連接有接通之電晶體TE及斷開之電晶體TE之節點連接之開關SF接通。根據此種電晶體TE及開關SF之狀態，於子全域位元線GBLI與全域位元線GBL之間，插入有2個電晶體TE之接通電阻之合計電阻ROB1。其結果，連結讀出對象記憶胞MCS與同步電路RDSB之電流路徑(由粗線表示)具有某大小之電阻RP2。Based on the selection of the local word line LWLS, the number of transistors TE from the third local word line LWL on the side of the self-selector CS is turned on. FIG. 21 shows an example of two transistors TE being turned on. Furthermore, among all switches SF, only the switch SF connected to the node to which the turned-on transistor TE and the disconnected transistor TE are connected is turned on. According to the state of such transistor TE and switch SF, a total resistance ROB1 of the turned-on resistance of the two transistors TE is inserted between the sub-global bit line GBLI and the global bit line GBL. As a result, the current path (indicated by the thick line) connecting the read target memory cell MCS and the synchronous circuit RDSB has a resistance RP2 of a certain size.
電阻RP1與電阻RP2具有大致或實質相同之大小。換言之，以形成將電阻RP1與電阻RP2之差最小化之接通電阻ROW1及ROB1之方式，形成接通電阻ROW1及ROB1，即選擇接通之電晶體TB之數量及接通之電晶體TE之數量。The resistor RP1 and the resistor RP2 have substantially or substantially the same size. In other words, the on-resistances ROW1 and ROB1 are formed in such a way as to minimize the difference between the resistor RP1 and the resistor RP2, that is, the number of transistors TB turned on and the number of transistors TE turned on are selected.
應接通之電晶體TB之數量依存於選擇局域位元線LBLS。選擇局域位元線LBLS由指定資料讀出之行位址指定。因此，應接通之電晶體TB之數量依存於行位址。解碼電路14b基於行位址，產生控制信號NB0～NBJ及控制信號NC0～NCJ。The number of transistors TB to be turned on depends on the selected local bit line LBLS. The selected local bit line LBLS is specified by the row address of the designated data to be read. Therefore, the number of transistors TB to be turned on depends on the row address. The decoding circuit 14b generates control signals NB0-NBJ and control signals NC0-NCJ based on the row address.
同樣地，應接通之電晶體TE之數量依存於選擇局域字元線LWLS。選擇局域字元線LWLS由指定資料讀出之列位址指定。因此，應接通之電晶體TE之數量依存於列位址。解碼電路14b基於列位址，產生控制信號NE0～NEK及控制信號NF0～NFK。Similarly, the number of transistors TE to be turned on depends on the selected local word line LWLS. The selected local word line LWLS is specified by the column address of the designated data to be read. Therefore, the number of transistors TE to be turned on depends on the column address. The decoding circuit 14b generates control signals NE0-NEK and control signals NF0-NFK based on the column address.
如圖22所示且參照圖11所述，為了寫入參照資料及執行第2感測，全域字元線GWL與同步電路RDSW連接且全域位元線GBL與驅動器電路RDPB連接。關於其他構成要件之連接與圖21相同。因此，連結讀出對象記憶胞MCS與同步電路RDSW之電流路徑(由粗線表示)具有電阻RP1。又，連結讀出對象記憶胞MCS與驅動器電路RDPB之電流路徑(由粗線表示)具有電阻RP2。As shown in FIG. 22 and described with reference to FIG. 11 , in order to write reference data and perform the second sensing, the global word line GWL is connected to the synchronous circuit RDSW and the global bit line GBL is connected to the driver circuit RDPB. The connection of other components is the same as that of FIG. 21 . Therefore, the current path (indicated by a thick line) connecting the read target memory cell MCS and the synchronous circuit RDSW has a resistance RP1. In addition, the current path (indicated by a thick line) connecting the read target memory cell MCS and the driver circuit RDPB has a resistance RP2.
於圖21之第1感測期間與圖22之參照資料寫入及第2感測期間之各者，連結讀出對象記憶胞MCS及驅動器電路(RDPW或RDPB)之電流路徑之電阻(RP1或RP2)與連結讀出對象記憶胞MCS及同步電路(RDSB或RDSW)之電流路徑之電阻(RP1或RP2)實質上相同。因此，連結讀出電流Irap流動時之驅動器電路(RDPW)及讀出對象記憶胞MCS之電流路徑之電阻，即圖21之電阻RP1，與連結讀出電流Irp流動時之驅動器電路(RDPB)及讀出對象記憶胞MCS之電流路徑之電阻，即圖22之電阻RP2實質上相同。同樣，連結讀出電流Irap流動時之讀出對象記憶胞MCS及同步電路(RDSB)之電流路徑之電阻，即圖21之電阻RP2，與連結讀出電流Irp流動時之讀出對象記憶胞MCS及同步電路(RDSW)之電流路徑之電阻，即圖22之電阻RP1實質上相同。因此，連結讀出對象記憶胞MCS與驅動器電路之電流路徑之電阻，及連結讀出對象記憶胞MCS與同步電路之電流路徑之電阻於讀出電流Irap流動時及讀出Irp流動時實質上皆相同。In each of the first sensing period of Figure 21 and the reference data writing and second sensing periods of Figure 22, the resistance (RP1 or RP2) of the current path connecting the read target memory cell MCS and the driver circuit (RDPW or RDPB) and the resistance (RP1 or RP2) of the current path connecting the read target memory cell MCS and the synchronization circuit (RDSB or RDSW) are substantially the same. Therefore, the resistance of the current path connecting the driver circuit (RDPW) and the read target memory cell MCS when the read current Irap flows, that is, the resistance RP1 in Figure 21, and the resistance of the current path connecting the driver circuit (RDPB) and the read target memory cell MCS when the read current Irp flows, that is, the resistance RP2 in Figure 22 are substantially the same. Similarly, the resistance of the current path connecting the read target memory cell MCS and the synchronous circuit (RDSB) when the read current Irap flows, that is, the resistance RP2 in FIG. 21, is substantially the same as the resistance of the current path connecting the read target memory cell MCS and the synchronous circuit (RDSW) when the read current Irp flows, that is, the resistance RP1 in FIG. 22. Therefore, the resistance of the current path connecting the read target memory cell MCS and the driver circuit, and the resistance of the current path connecting the read target memory cell MCS and the synchronous circuit are substantially the same when the read current Irap flows and when the read current Irp flows.
2.3.優點 根據第2實施形態，與第1實施形態相同，繼第1感測後進行第2感測，於第2感測中，於P方向流動且可將讀出對象記憶胞MC之MTJ元件MTJ設為P狀態之大小之讀出電流Irp流動至讀出對象記憶胞MC。因此，可獲得與第1實施形態相同之優點。2.3. AdvantagesAccording to the second embodiment, the second sensing is performed after the first sensing, and in the second sensing, a read current Irp of a magnitude that flows in the P direction and can set the MTJ element MTJ of the read target memory cell MC to the P state flows to the read target memory cell MC. Therefore, the same advantages as the first embodiment can be obtained.
第2實施形態之記憶裝置1b包含GWL電阻調整電路WRA及GBL電阻調整電路BRA。GWL電阻調整電路WRA可對子全域字元線GWLI與全域字元線GWL之間插入可變數量之接通之電晶體TB。GBL電阻調整電路BRA可對子全域位元線GBLI與全域位元線GBL之間插入可變數量之接通之電晶體TE。GWL電阻調整電路WRA及GBL電阻調整電路BRA於第1感測及第2感測之任一者，皆以連結讀出對象記憶胞MCS及驅動器電路之電流路徑之電阻與連結讀出對象記憶胞MCS及同步電路之電流路徑之電阻實質相等之方式，調整接通之電晶體TB及TE之數量。因此，連結讀出對象記憶胞MCS與驅動器電路之電流路徑之電阻、及連結讀出對象記憶胞MCS與同步電路之電流路徑之電阻於讀出電流Irap流動時與讀出電流Irp流動時實質上皆相同。因此，抑制藉由對讀出對象記憶胞MCS之第1感測而得之低保持電壓VhdL、與藉由對讀出對象記憶胞MCS之第2感測而得之低保持電壓VhdL之差。這可實現更正確之資料讀出。因此，即使第1感測及第2感測中讀出電流之流動方向不同，亦可高精度讀出資料。The memory device 1b of the second embodiment includes a GWL resistance adjustment circuit WRA and a GBL resistance adjustment circuit BRA. The GWL resistance adjustment circuit WRA can insert a variable number of turned-on transistors TB between the sub-global word line GWLI and the global word line GWL. The GBL resistance adjustment circuit BRA can insert a variable number of turned-on transistors TE between the sub-global bit line GBLI and the global bit line GBL. The GWL resistance adjustment circuit WRA and the GBL resistance adjustment circuit BRA adjust the number of transistors TB and TE that are turned on in either the first sensing or the second sensing in such a way that the resistance of the current path connecting the read target memory cell MCS and the driver circuit and the resistance of the current path connecting the read target memory cell MCS and the synchronous circuit are substantially equal. Therefore, the resistance of the current path connecting the read target memory cell MCS and the driver circuit and the resistance of the current path connecting the read target memory cell MCS and the synchronous circuit are substantially the same when the read current Irap flows and when the read current Irp flows. Therefore, the difference between the low holding voltage VhdL obtained by the first sensing of the read target memory cell MCS and the low holding voltage VhdL obtained by the second sensing of the read target memory cell MCS is suppressed. This can realize more accurate data reading. Therefore, even if the flow direction of the read current in the first sensing and the second sensing is different, the data can be read with high accuracy.
3.第3實施形態 第3實施形態係關於資料寫入。3. The third implementation formThe third implementation form is about data writing.
3.1.構成 圖23顯示第3實施形態之寫入電路之構成要件及構成要件之連接。如圖23所示，寫入電路WC包含寫入控制電路WOC、驅動器電路WDUB、WDPB、WDUW及WDPW以及同步電路WDSB及WDSW。圖23僅顯示1個全域位元線GBL及1個全域字元線GWL相關之構成要件。對其他全域位元線GBL亦設置驅動器電路WDUB及WDPB以及同步電路WDSB。又，對其他全域字元線GWL亦設置驅動器電路WDUW及WDPW以及同步電路WDSW。3.1. ConfigurationFIG. 23 shows the components of the write circuit of the third embodiment and the connection of the components. As shown in FIG. 23 , the write circuit WC includes a write control circuit WOC, driver circuits WDUB, WDPB, WDUW and WDPW, and synchronization circuits WDSB and WDSW. FIG. 23 only shows the components related to one global bit line GBL and one global word line GWL. Driver circuits WDUB and WDPB and synchronization circuit WDSB are also provided for other global bit lines GBL. In addition, driver circuits WDUW and WDPW and synchronization circuit WDSW are also provided for other global word lines GWL.
同步電路WDSB以可對全域位元線GBL施加接地電壓VSS之方式構成。同步電路WDSB之功能及(或)構成除設置開關SW21取代開關SW1，及使用控制信號S21取代控制信號S1外，與同步電路RDSB相同。將第1實施形態之同步電路RDSB相關之記述中之「SW1」及「S1」分別置換成「SW21」及「S21」之記述適用於同步電路WDSB。開關SW21例如自寫入控制電路WOC接收控制信號S21。亦可使用同步電路RDSB取代同步電路WDSB。The synchronous circuit WDSB is configured to apply the ground voltage VSS to the global bit line GBL. The function and/or configuration of the synchronous circuit WDSB are the same as those of the synchronous circuit RDSB, except that the switch SW21 is provided to replace the switch SW1, and the control signal S21 is used to replace the control signal S1. The description of replacing "SW1" and "S1" in the description related to the synchronous circuit RDSB of the first embodiment with "SW21" and "S21" respectively applies to the synchronous circuit WDSB. The switch SW21 receives the control signal S21 from the write control circuit WOC, for example. The synchronous circuit RDSB can also be used to replace the synchronous circuit WDSB.
同步電路WDSW以可對全域字元線GWL施加接地電壓VSS之方式構成。同步電路WDSW之功能及(或)構成除設置開關SW24取代開關SW4，及使用控制信號S24取代控制信號S4外，與同步電路RDSW相同。將第1實施形態之同步電路RDSW相關之記述中之「SW4」及「S4」分別置換成「SW4」及「S24」之記述適用於同步電路WDSW。開關SW24例如自寫入控制電路WOC接收控制信號S24。亦可使用同步電路RDSW取代同步電路WDSW。The synchronous circuit WDSW is configured to apply the ground voltage VSS to the global word line GWL. The function and/or configuration of the synchronous circuit WDSW are the same as those of the synchronous circuit RDSW, except that the switch SW24 is provided to replace the switch SW4, and the control signal S24 is used to replace the control signal S4. The description of replacing "SW4" and "S4" in the description related to the synchronous circuit RDSW of the first embodiment with "SW4" and "S24" respectively applies to the synchronous circuit WDSW. The switch SW24 receives the control signal S24 from the write control circuit WOC, for example. The synchronous circuit RDSW can also be used to replace the synchronous circuit WDSW.
驅動器電路WDPB以可對全域位元線GBL施加寫入電壓Vwp之方式構成。寫入電壓Vwp具有如下大小：藉由將寫入電壓Vwp之大小之電壓施加於1個記憶胞MC，而使該記憶胞MC之開關元件SE接通，且使記憶胞MC中流動P寫入電流Iwp。寫入電壓Vwp亦可與預充電電壓Vpcp相同。驅動器電路WDPB只要可對全域位元線GBL施加寫入電壓Vwp，則亦可具有任意之構成。例如，驅動器電路WDPB包含開關SW23。開關SW23於一端與全域位元線GBL連接，於另一端與記憶裝置1中(例如電壓產生電路16)被施加寫入電壓Vwp之節點連接。開關SW23基於控制信號S23接通或斷開，於接通之期間，將寫入電壓Vwp傳輸至全域位元線GBL。開關SW23例如自寫入控制電路WOC接收控制信號S23。開關SW23例如為MOSFET。The driver circuit WDPB is configured to apply a write voltage Vwp to the global bit line GBL. The write voltage Vwp has the following magnitude: by applying a voltage of the magnitude of the write voltage Vwp to one memory cell MC, the switch element SE of the memory cell MC is turned on, and a write current Iwp flows through the memory cell MC. The write voltage Vwp may be the same as the precharge voltage Vpcp. The driver circuit WDPB may have any configuration as long as the write voltage Vwp can be applied to the global bit line GBL. For example, the driver circuit WDPB includes a switch SW23. The switch SW23 is connected to the global bit line GBL at one end and to a node in the memory device 1 (e.g., the voltage generating circuit 16) to which the write voltage Vwp is applied at the other end. The switch SW23 is turned on or off based on the control signal S23, and transmits the write voltage Vwp to the global bit line GBL during the on period. The switch SW23 receives the control signal S23 from the write control circuit WOC, for example. The switch SW23 is, for example, a MOSFET.
驅動器電路WDPW以可對全域字元線GWL施加寫入電壓Vwap之方式構成。寫入電壓Vwap具有如下大小：藉由將寫入電壓Vwap之大小之電壓施加於1個記憶胞MC，而使該記憶胞MC之開關元件SE接通，且使記憶胞MC中流動AP寫入電流Iwap。驅動器電路WDPW只要可對全域字元線GWL施加寫入電壓Vwap，則亦可具有任意之構成。例如，驅動器電路WDPW包含開關SW26。開關SW26於一端與全域字元線GWL連接，於另一端與記憶裝置1中(例如電壓產生電路16)被施加寫入電壓Vwap之節點連接。開關SW26基於控制信號S26接通或斷開，於接通之期間，將寫入電壓Vwap傳輸至全域字元線GWL。開關SW26例如自寫入控制電路WOC接收控制信號S26。開關SW26例如為MOSFET。The driver circuit WDPW is configured to apply a write voltage Vwap to the global word line GWL. The write voltage Vwap has a magnitude such that by applying a voltage of the magnitude of the write voltage Vwap to a memory cell MC, the switch element SE of the memory cell MC is turned on, and the AP write current Iwap flows in the memory cell MC. The driver circuit WDPW may have any configuration as long as the write voltage Vwap can be applied to the global word line GWL. For example, the driver circuit WDPW includes a switch SW26. The switch SW26 is connected to the global word line GWL at one end and is connected to a node in the memory device 1 (e.g., the voltage generating circuit 16) to which the write voltage Vwap is applied at the other end. The switch SW26 is turned on or off based on the control signal S26, and when turned on, the write voltage Vwap is transmitted to the global word line GWL. The switch SW26 receives the control signal S26 from the write control circuit WOC, for example. The switch SW26 is, for example, a MOSFET.
寫入電壓Vwp亦可與寫入電壓Vwap相同。The write voltage Vwp may also be the same as the write voltage Vwap.
驅動器電路WDUB以可對全域位元線GBL施加非選擇電壓Vusel之方式構成。驅動器電路WDUB之功能及(或)構成除設置開關SW22取代開關SW2，及使用控制信號S22取代控制信號S2外，與驅動器電路RDUB相同。將第1實施形態之驅動器電路RDUB相關之記述中之「SW2」及「S2」分別置換成「SW22」及「S22」之記述適用於驅動器電路WDUB。開關SW22例如自寫入控制電路WOC接收控制信號S22。亦可使用驅動器電路RDUB取代驅動器電路WDUB。The driver circuit WDUB is configured in such a way that a non-selection voltage Vusel can be applied to the global bit line GBL. The function and/or configuration of the driver circuit WDUB are the same as those of the driver circuit RDUB, except that a switch SW22 is provided to replace the switch SW2, and a control signal S22 is used to replace the control signal S2. The description of replacing "SW2" and "S2" in the description related to the driver circuit RDUB of the first embodiment with "SW22" and "S22", respectively, is applicable to the driver circuit WDUB. The switch SW22 receives the control signal S22 from the write control circuit WOC, for example. The driver circuit RDUB can also be used to replace the driver circuit WDUB.
驅動器電路WDUW以可對全域字元線GWL施加非選擇電壓Vusel之方式構成。驅動器電路WDUW之功能及(或)構成除設置開關SW25取代開關SW5，及使用控制信號S25取代控制信號S5外，與驅動器電路RDUW相同。將第1實施形態之驅動器電路RDUW相關之記述中之「SW5」及「S5」分別置換成「SW25」及「S25」之記述適用於驅動器電路WDUW。開關SW25例如自寫入控制電路WOC接收控制信號S25。亦可使用驅動器電路RDUW取代驅動器電路WDUW。The driver circuit WDUW is constructed in such a way that a non-selection voltage Vusel can be applied to the global word line GWL. The function and/or structure of the driver circuit WDUW are the same as those of the driver circuit RDUW, except that a switch SW25 is provided instead of the switch SW5, and a control signal S25 is used instead of the control signal S5. The description of replacing "SW5" and "S5" in the description related to the driver circuit RDUW of the first embodiment with "SW25" and "S25", respectively, is applicable to the driver circuit WDUW. The switch SW25 receives the control signal S25, for example, from the write control circuit WOC. The driver circuit RDUW can also be used to replace the driver circuit WDUW.
寫入控制電路WOC為控制寫入電路WC中之構成要件之電路。寫入控制電路WOC基於控制信號而動作，且該控制信號由控制電路13及解碼電路14基於控制信號CNT、指令CMD及位址信號ADD產生。The write control circuit WOC is a circuit for controlling the components of the write circuit WC. The write control circuit WOC operates based on a control signal, and the control signal is generated by the control circuit 13 and the decoding circuit 14 based on the control signal CNT, the command CMD and the address signal ADD.
3.2.動作 圖24係按時間顯示第3實施形態之記憶裝置1c之資料寫入期間之若干配線之電位。圖24顯示與包含資料寫入對象之記憶胞(寫入對象記憶胞)MC之子核心電路SCC連接之1個全域位元線GBL及1個全域字元線GWL。圖24還於下部按時間顯示第3實施形態之記憶裝置1c之資料寫入期間流過寫入對象記憶胞MC之電流。圖24之下部與圖9相同，於縱軸之電流為正之區域中顯示AP方向之電流，於縱軸之電流為負之區域中顯示P方向之電流。3.2. ActionFIG. 24 shows the potential of several wirings during data writing of the memory device 1c of the third embodiment over time. FIG. 24 shows a global bit line GBL and a global word line GWL connected to the sub-core circuit SCC including the memory cell (write target memory cell) MC to which data is written. FIG. 24 also shows the current flowing through the write target memory cell MC during data writing of the memory device 1c of the third embodiment over time at the bottom. The lower part of FIG. 24 is the same as FIG. 9, showing the current in the AP direction in the area where the current on the vertical axis is positive, and showing the current in the P direction in the area where the current on the vertical axis is negative.
圖24為方便起見，繼AP寫入後顯示P寫入。不要求繼AP寫入後進行P寫入。FIG. 24 shows P writing following AP writing for convenience. It is not required to perform P writing following AP writing.
資料寫入之概要與第1實施形態中參照圖9記述之參照資料寫入相同。以下，主要記述與參照資料寫入不同之點。The outline of data writing is the same as the reference data writing described in the first embodiment with reference to Fig. 9. The following mainly describes the differences from the reference data writing.
於開始AP寫入或P寫入之時點，全域字元線GWL由驅動器電路WDUW被充電成非選擇電壓Vusel。這可藉由將驅動器電路WDUW之開關SW25維持接通，且將其他開關SW24及SW26維持斷開而進行。又，全域位元線GBL由驅動器電路WDUB被充電成非選擇電壓Vusel。這可藉由將驅動器電路WDUB之開關SW22維持接通，且將其他開關SW21及SW23維持斷開而進行。At the time of starting AP writing or P writing, the global word line GWL is charged to the non-selection voltage Vusel by the driver circuit WDUW. This can be done by keeping the switch SW25 of the driver circuit WDUW turned on and keeping the other switches SW24 and SW26 turned off. In addition, the global bit line GBL is charged to the non-selection voltage Vusel by the driver circuit WDUB. This can be done by keeping the switch SW22 of the driver circuit WDUB turned on and keeping the other switches SW21 and SW23 turned off.
隨著開始對寫入對象記憶胞MC寫入資料，寫入對象記憶胞MC經由局域位元線LBL(導電體22)連接於全域位元線GBL，且經由局域字元線LWL(導電體21)連接於全域字元線GWL。As data starts to be written to the write target memory cell MC, the write target memory cell MC is connected to the global bit line GBL via the local bit line LBL (conductor 22) and is connected to the global word line GWL via the local word line LWL (conductor 21).
於時刻t11，藉由驅動器電路WDPW對全域字元線GWL施加寫入電壓Vwap。這可藉由將驅動器電路WDPW之開關SW26維持接通，且將其他開關SW24及SW25維持斷開而進行。藉由施加寫入電壓Vwap，將全域字元線GWL充電成寫入電壓Vwap。其後，藉由驅動器電路WDPW之開關SW26斷開，將全域字元線GWL設為浮動。At time t11, the write voltage Vwap is applied to the global word line GWL by the driver circuit WDPW. This can be done by keeping the switch SW26 of the driver circuit WDPW turned on and keeping the other switches SW24 and SW25 turned off. By applying the write voltage Vwap, the global word line GWL is charged to the write voltage Vwap. Thereafter, by turning off the switch SW26 of the driver circuit WDPW, the global word line GWL is set to float.
於時刻t12，藉由同步電路WDSB對全域位元線GBL施加接地電壓Vss。這可藉由將同步電路WDSB之開關SW21維持接通，且將其他開關SW22及SW23維持斷開而進行。藉由對全域位元線GBL施加接地電壓Vss，而對寫入對象記憶胞MC之兩端施加Vwap-Vss之大小之電壓，即寫入電壓Vwap。該電壓具有使寫入對象記憶胞MC之開關元件SE接通之大小。因此，於AP方向流動寫入電流Iwap。At time t12, the ground voltage Vss is applied to the global bit line GBL by the synchronous circuit WDSB. This can be done by keeping the switch SW21 of the synchronous circuit WDSB turned on and keeping the other switches SW22 and SW23 turned off. By applying the ground voltage Vss to the global bit line GBL, a voltage of Vwap-Vss is applied to both ends of the write target memory cell MC, that is, the write voltage Vwap. This voltage has a magnitude that turns on the switch element SE of the write target memory cell MC. Therefore, the write current Iwap flows in the AP direction.
如參照圖23所記述，寫入電流Iwap之大小大於AP方向開關電流Icap。因此，藉由寫入電流Iwap流過寫入對象記憶胞MC，寫入對象記憶胞MC之MTJ元件MTJ成為AP狀態。As described with reference to Fig. 23, the magnitude of the write current Iwap is greater than the AP direction switch current Icap. Therefore, when the write current Iwap flows through the write target memory cell MC, the MTJ element MTJ of the write target memory cell MC becomes the AP state.
再者，藉由寫入電流Iwap，全域字元線GWL之電位降低。其結果，寫入對象記憶胞MC兩端之電位差降低。若寫入對象記憶胞MC兩端之電位差降低至高保持電壓VhdH，則寫入對象記憶胞MC之開關元件SE斷開。如此，AP寫入完成。Furthermore, the potential of the global word line GWL is reduced by the write current Iwap. As a result, the potential difference between the two ends of the write target memory cell MC is reduced. If the potential difference between the two ends of the write target memory cell MC is reduced to the high holding voltage VhdH, the switch element SE of the write target memory cell MC is turned off. In this way, AP writing is completed.
其後，自時刻t13對全域字元線GWL施加非選擇電壓Vusel，接著，對全域位元線GBL施加非選擇電壓Vusel。Thereafter, from time t13, a non-select voltage Vusel is applied to the global word line GWL, and then, a non-select voltage Vusel is applied to the global bit line GBL.
於時刻t21，藉由驅動器電路WDPB對全域位元線GBL施加寫入電壓Vwp。這可藉由將驅動器電路WDPB之開關SW23維持接通，且將其他開關SW21及SW22維持斷開而進行。藉由施加寫入電壓Vwp，全域位元線GBL被充電成寫入電壓Vwp。其後，藉由驅動器電路WDPB之開關SW23斷開，將全域位元線GBL設為浮動。At time t21, the write voltage Vwp is applied to the global bit line GBL by the driver circuit WDPB. This can be done by keeping the switch SW23 of the driver circuit WDPB turned on and keeping the other switches SW21 and SW22 turned off. By applying the write voltage Vwp, the global bit line GBL is charged to the write voltage Vwp. Thereafter, by turning off the switch SW23 of the driver circuit WDPB, the global bit line GBL is set to float.
於時刻t22，藉由同步電路WDSW對全域字元線GWL施加接地電壓Vss。這可藉由將同步電路WDSW之開關SW24維持接通，且將其他開關SW25及開關SW26維持斷開而進行。藉由對全域字元線GWL施加接地電壓Vss，而對寫入對象記憶胞MC之兩端施加Vwp-Vss之大小之電壓，即寫入電壓Vwp。該電壓具有使寫入對象記憶胞MC之開關元件SE接通之大小。因此，於P方向流動寫入電流Iwp。At time t22, the ground voltage Vss is applied to the global word line GWL by the synchronous circuit WDSW. This can be done by keeping the switch SW24 of the synchronous circuit WDSW turned on and keeping the other switches SW25 and SW26 turned off. By applying the ground voltage Vss to the global word line GWL, a voltage of Vwp-Vss, i.e., a write voltage Vwp, is applied to both ends of the write target memory cell MC. This voltage has a magnitude that turns on the switch element SE of the write target memory cell MC. Therefore, the write current Iwp flows in the P direction.
如參照圖23所記述，寫入電流Iwp之大小大於P方向開關電流Icp。因此，藉由寫入電流Iwp流過寫入對象記憶胞MC，寫入對象記憶胞MC之MTJ元件MTJ成為P狀態。As described with reference to Fig. 23, the magnitude of the write current Iwp is greater than the P-direction switch current Icp. Therefore, when the write current Iwp flows through the write-target memory cell MC, the MTJ element MTJ of the write-target memory cell MC becomes the P state.
再者，藉由寫入電流Iwp，全域位元線GBL之電位降低。其結果，寫入對象記憶胞MC兩端之電位差降低。若寫入對象記憶胞MC兩端之電位差降低至低保持電壓VhdL，則寫入對象記憶胞MC之開關元件SE斷開。如此，P寫入完成。Furthermore, the potential of the global bit line GBL is reduced by the write current Iwp. As a result, the potential difference between the two ends of the write target memory cell MC is reduced. If the potential difference between the two ends of the write target memory cell MC is reduced to the low holding voltage VhdL, the switch element SE of the write target memory cell MC is turned off. In this way, P writing is completed.
其後，自時刻t23，對全域位元線GBL施加非選擇電壓Vusel，接著，對全域字元線GWL施加非選擇電壓Vusel。Thereafter, from time t23, a non-select voltage Vusel is applied to the global bit line GBL, and then a non-select voltage Vusel is applied to the global word line GWL.
3.3.優點 根據第3實施形態，於資料寫入期間，如與第1感測及第2感測相同，將全域字元線GWL及全域位元線GBL中之一者充電，其後將之設為浮動，接著，將全域字元線GWL及全域位元線GBL中之另一者設為接地電壓Vss。藉由施加此種電壓，亦可對記憶胞MC寫入資料。3.3. AdvantagesAccording to the third embodiment, during data writing, as in the first and second sensing, one of the global word line GWL and the global bit line GBL is charged and then set to floating, and then the other of the global word line GWL and the global bit line GBL is set to the ground voltage Vss. By applying such a voltage, data can also be written to the memory cell MC.
3.4.變化例 與第1實施形態之變化例相同，驅動器電路WDPB及(或)WDPW亦可使用閘極偏壓方式實現。3.4. VariationsSimilar to the variation of the first embodiment, the driver circuits WDPB and (or) WDPW can also be implemented using a gate bias method.
第3實施形態可與第1實施形態或第2實施形態組合。第3實施形態與第1實施形態組合之情形時，若干驅動器電路可藉由使用1個驅動器電路與閘極偏壓方式而實現。用以對讀出電路RC中之全域位元線GBL施加預充電電壓Vpcp之驅動器電路RDPB之功能，及用以對寫入電路WC中之全域位元線GBL施加寫入電壓Vwp之驅動器電路WDPB之功能藉由1個驅動器電路實現。該情形時，驅動器電路例如包含與電源電壓之節點及全域位元線GBL連接之n型MOSFET。MOSFET於對全域位元線GBL施加預充電電壓Vpcp時及施加寫入電壓Vwp時，於閘極中接收不同之電壓。The third embodiment can be combined with the first embodiment or the second embodiment. When the third embodiment is combined with the first embodiment, a plurality of driver circuits can be realized by using one driver circuit and a gate bias method. The function of the driver circuit RDPB for applying a precharge voltage Vpcp to the global bit line GBL in the read circuit RC and the function of the driver circuit WDPB for applying a write voltage Vwp to the global bit line GBL in the write circuit WC are realized by one driver circuit. In this case, the driver circuit includes, for example, an n-type MOSFET connected to a node of a power supply voltage and the global bit line GBL. The MOSFET receives different voltages in the gate when a precharge voltage Vpcp and a write voltage Vwp are applied to the global bit line GBL.
用以對讀出電路RC中之全域字元線GWL施加預充電電壓Vpcap之驅動器電路RDPW之功能，及用以對寫入電路WC中之全域字元線GWL施加寫入電壓Vwap之驅動器電路WDPW之功能可藉由1個驅動器電路實現。該情形時，驅動器電路例如包含與電源電壓之節點及全域字元線GWL連接之n型MOSFET。MOSFET於對全域字元線GWL施加預充電電壓Vpcap時與施加寫入電壓Vwap時，於閘極中接收不同之電壓。The function of the driver circuit RDPW for applying the precharge voltage Vpcap to the global word line GWL in the read circuit RC and the function of the driver circuit WDPW for applying the write voltage Vwap to the global word line GWL in the write circuit WC can be realized by one driver circuit. In this case, the driver circuit includes, for example, an n-type MOSFET connected to the node of the power supply voltage and the global word line GWL. The MOSFET receives different voltages in the gate when the precharge voltage Vpcap is applied to the global word line GWL and when the write voltage Vwap is applied.
雖已說明本發明之若干實施形態，但該等實施形態係作為例而提示者，未意欲限定發明之範圍。該等實施形態可以其他各種形態實施，於不脫離發明主旨之範圍內，可進行各種省略、置換、變更。該等實施形態或其變化包含於發明範圍或主旨內，同樣包含於申請專利範圍所記載之發明及其均等之範圍內。Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other forms and may be omitted, replaced, or modified in various ways without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention and are also included in the invention described in the patent application and its equivalents.
[相關申請之參照] 本申請享有以日本專利申請第2022-038284號(申請日：2022年3月11日)及美國專利申請17/842486(申請日：2022年6月16日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之所有內容。[Reference to related applications]This application enjoys the priority of Japanese Patent Application No. 2022-038284 (filing date: March 11, 2022) and U.S. Patent Application No. 17/842486 (filing date: June 16, 2022). This application includes all the contents of the basic application by reference to the basic application.
1:記憶裝置 11:核心電路 11b:核心電路 12:輸入輸出電路 13:控制電路 14:解碼電路 14b:解碼電路 14b1:控制信號產生電路 14b2:控制信號產生電路 15:頁面緩衝器 16:電壓產生電路 21:導電體 22:導電體 31:下部電極 32:可變電阻材料 33:上部電極 35:強磁性層 36:絕緣層 37:強磁性層 A:點 ADD:位址信號 B1:點 B2:點 BRA:GBL電阻調整電路 C1:點 C2:點 CMD:指令 CNT:控制信號 CS:行選擇器 D1:點 D2:點 DAT:資料 GBL:全域位元線 GBLI:子全域位元線 GWL:全域字元線 GWLI:子全域字元線 Irap:讀出電流 Irp:讀出電流 Iwap:電流 Iwp:電流 LBL:局域位元線 LBL＜0＞～LBL＜N＞:局域位元線 LBLS:選擇局域位元線 LWL:局域字元線 LWL＜0＞～LWL＜M＞:局域字元線 LWLS:選擇局域字元線 MA:記憶胞陣列 MC:記憶胞 MCS:讀出對象記憶胞 MTJ:MTJ元件 N1～N4:節點 NB0～NBJ:控制信號 NC0～NCJ:控制信號 NE0～NEK:控制信號 NF0～NFK:控制信號 OP:運算放大器 OUT:輸出 RB1:合計接通電阻 RC:讀出電路 RDPB:驅動器電路 RDPW:驅動器電路 RDSB:同步電路 RDSW:同步電路 RDUB:驅動器電路 RDUW:驅動器電路 ROB1:接通電阻 ROC:讀出控制電路 ROW1:接通電阻 RP1:電阻 RP2:電阻 RS:列選擇器 RW1:合計接通電阻 S1～S6:控制信號 S11:控制信號 S12:控制信號 S21~S26:控制信號 SAC:感測放大器電路 SC0～SCJ:開關 SCC:子核心電路 SCCb:子核心電路 SE:開關元件 SF:開關元件 SF0～SFK:開關 SW1～SW6:開關 SW21～SW26:開關 t0～t7:時刻 t11～t15:時刻 t21～t23:時刻 TA0～TAM:n型MOSFET TB:電晶體 TB0～TBJ:電晶體 TD0～TDN:n型MOSFET TE:電晶體 TE0～TEK:電晶體 Tr1:電晶體 Tr2:電晶體 VhdH:高保持電壓 VhdL:低保持電壓 VMC:電壓調整電路 Vpcap:預充電電壓 Vpcp:預充電電壓 Vss:接地電壓 Vth:閾值電壓 Vusel:非選擇電壓 Vwap:寫入電壓 Vwp:寫入電壓 WC:寫入電路 WDPB:驅動器電路 WDPW:驅動器電路 WDSB:同步電路 WDUB:驅動器電路 WDUW:驅動器電路 WDSW:同步電路 WOC:寫入控制電路 WRA:GWL電阻調整電路1: Memory device11: Core circuit11b: Core circuit12: Input/output circuit13: Control circuit14: Decoding circuit14b: Decoding circuit14b1: Control signal generating circuit14b2: Control signal generating circuit15: Page buffer16: Voltage generating circuit21: Conductor22: Conductor31: Lower electrode32: Variable resistance material33: Upper electrode35: Strong magnetic layer36: Insulating layer37: Strong magnetic layerA: PointADD: Address signalB1: PointB2: PointBRA: GBL resistance adjustment circuitC1: PointC2: PointCMD: CommandCNT: Control signalCS: Row selectorD1: PointD2: PointDAT: DataGBL: Global bit lineGBLI: Sub-global bit lineGWL: Global word lineGWLI: Sub-global word lineIrap: Read currentIrp: Read currentIwap: CurrentIwp: CurrentLBL: Local bit lineLBL＜0＞～LBL＜N＞: Local bit lineLBLS: Select local bit lineLWL: Local word lineLWL＜0＞～LWL＜M＞: Local word lineLWLS: Select local word lineMA: Memory cell arrayMC: Memory cellMCS: Read target memory cellMTJ: MTJ elementN1～N4: NodeNB0~NBJ: control signalNC0~NCJ: control signalNE0~NEK: control signalNF0~NFK: control signalOP: operational amplifierOUT: outputRB1: total on-resistanceRC: readout circuitRDPB: driver circuitRDPW: driver circuitRDSB: synchronous circuitRDSW: synchronous circuitRDUB: driver circuitRDUW: driver circuitROB1: on-resistanceROC: readout control circuitROW1: on-resistanceRP1: resistorRP2: resistorRS: column selectorRW1: total on-resistanceS1~S6: control signalS11: control signalS12: control signalS21~S26: control signalSAC: Sense amplifier circuitSC0～SCJ: SwitchSCC: Sub-core circuitSCCb: Sub-core circuitSE: Switch elementSF: Switch elementSF0～SFK: SwitchSW1～SW6: SwitchSW21～SW26: Switcht0～t7: Timet11～t15: Timet21～t23: TimeTA0～TAM: n-type MOSFETTB: TransistorTB0～TBJ: TransistorTD0～TDN: n-type MOSFETTE: TransistorTE0～TEK: TransistorTr1: TransistorTr2: TransistorVhdH: High holding voltageVhdL: Low holding voltageVMC: Voltage adjustment circuitVpcap: Pre-charge voltageVpcp: pre-charge voltageVss: ground voltageVth: threshold voltageVusel: non-select voltageVwap: write voltageVwp: write voltageWC: write circuitWDPB: driver circuitWDPW: driver circuitWDSB: synchronous circuitWDUB: driver circuitWDUW: driver circuitWDSW: synchronous circuitWOC: write control circuitWRA: GWL resistance adjustment circuit
圖1顯示第1實施形態之記憶裝置之功能區塊。 圖2顯示第1實施形態之核心電路之功能區塊。 圖3係第1實施形態之記憶胞陣列之電路圖。 圖4係第1實施形態之記憶胞陣列之一部分之立體圖。 圖5顯示第1實施形態之記憶胞之構造例之剖面。 圖6係顯示第1實施形態之記憶胞之電壓與電流之特性例之圖表。 圖7顯示第1實施形態之讀出電路之構成要件及構成要件之連接。 圖8顯示第1實施形態之感測放大器電路之構成要件及構成要件之連接。 圖9按時間顯示第1實施形態之記憶裝置中之資料讀出期間之若干配線之電位。 圖10顯示第1實施形態之記憶裝置之一部分資料讀出期間之狀態之例。 圖11顯示第1實施形態之記憶裝置之一部分資料讀出期間之狀態之例。 圖12按時間顯示參考用之記憶裝置中之資料讀出期間之若干配線之電位。 圖13顯示第2實施形態之核心電路之功能區塊。 圖14係第2實施形態之GWL電阻調整電路及列選擇器之電路圖。 圖15係第2實施形態之GBL電阻調整電路及行選擇器之電路圖。 圖16顯示第2實施形態之解碼電路之功能區塊。 圖17顯示第2實施形態之GWL電阻調整電路之動作期間之一狀態之例。 圖18顯示第2實施形態之GWL電阻調整電路之動作期間之一狀態之例。 圖19顯示第2實施形態之GBL電阻調整電路之動作期間之一狀態之例。 圖20顯示第2實施形態之GBL電阻調整電路之動作期間之一狀態之例。 圖21顯示第2實施形態之記憶裝置之資料讀出期間之一狀態之例。 圖22顯示第2實施形態之記憶裝置之資料讀出期間之一狀態之例。 圖23顯示第3實施形態之寫入電路之構成要件及構成要件之連接。 圖24按時間顯示第3實施形態之記憶裝置中之資料寫入期間之若干配線之電位。FIG. 1 shows a functional block of a memory device of the first embodiment.FIG. 2 shows a functional block of a core circuit of the first embodiment.FIG. 3 is a circuit diagram of a memory cell array of the first embodiment.FIG. 4 is a perspective view of a portion of a memory cell array of the first embodiment.FIG. 5 shows a cross-section of a structural example of a memory cell of the first embodiment.FIG. 6 is a graph showing an example of voltage and current characteristics of a memory cell of the first embodiment.FIG. 7 shows constituent elements of a readout circuit of the first embodiment and connections of the constituent elements.FIG. 8 shows constituent elements of a sense amplifier circuit of the first embodiment and connections of the constituent elements.FIG. 9 shows the potential of several wirings during data reading in the memory device of the first embodiment in time.FIG. 10 shows an example of the state of a portion of the memory device of the first embodiment during data reading.FIG. 11 shows an example of the state of a portion of the memory device of the first embodiment during data reading.FIG. 12 shows the potential of several wirings during data reading in the reference memory device in time.FIG. 13 shows the functional blocks of the core circuit of the second embodiment.FIG. 14 is a circuit diagram of the GWL resistance adjustment circuit and the column selector of the second embodiment.FIG. 15 is a circuit diagram of the GBL resistance adjustment circuit and the row selector of the second embodiment.FIG. 16 shows a functional block of a decoding circuit of the second embodiment.FIG. 17 shows an example of a state of the GWL resistance adjustment circuit of the second embodiment during operation.FIG. 18 shows an example of a state of the GWL resistance adjustment circuit of the second embodiment during operation.FIG. 19 shows an example of a state of the GBL resistance adjustment circuit of the second embodiment during operation.FIG. 20 shows an example of a state of the GBL resistance adjustment circuit of the second embodiment during operation.FIG. 21 shows an example of a state of the memory device of the second embodiment during data readout.FIG. 22 shows an example of a state of the memory device of the second embodiment during data readout.FIG. 23 shows the components of the write circuit of the third embodiment and the connection of the components.FIG. 24 shows the potentials of several wirings during data writing in the memory device of the third embodiment over time.
GBL:全域位元線GBL: Global Bit Line
GWL:全域字元線GWL: Global Character Line
RC:讀出電路RC: Readout Circuit
RDPB:驅動器電路RDPB:Driver circuit
RDPW:驅動器電路RDPW:Driver circuit
RDSB:同步電路RDSB: Synchronous circuit
RDSW:同步電路RDSW: Synchronous circuit
RDUB:驅動器電路RDUB:Driver circuit
RDUW:驅動器電路RDUW:Driver circuit
ROC:讀出控制電路ROC: Read Out Control Circuit
S1:控制信號S1: control signal
S2:控制信號S2: Control signal
S3:控制信號S3: Control signal
S4:控制信號S4: Control signal
S5:控制信號S5: Control signal
S6:控制信號S6: Control signal
SAC:感測放大器電路SAC: Sense Amplifier Circuit
SCC:子核心電路SCC: Sub-core circuit
SW1:開關SW1: switch
SW2:開關SW2: switch
SW3:開關SW3: switch
SW4:開關SW4: switch
SW5:開關SW5: switch
SW6:開關SW6: switch
Vpcap:預充電電壓Vpcap: pre-charge voltage
Vpcp:預充電電壓Vpcp: pre-charge voltage
Vss:接地電壓Vss: ground voltage
Vusel:非選擇電壓Vusel: non-selective voltage
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022-038284 | 2022-03-11 | ||
| JP2022038284AJP2023132766A (en) | 2022-03-11 | 2022-03-11 | Storage device |
| US17/842,486US11961557B2 (en) | 2022-03-11 | 2022-06-16 | Memory device |
| US17/842,486 | 2022-06-16 |
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| TW202336761A TW202336761A (en) | 2023-09-16 |
| TWI861739Btrue TWI861739B (en) | 2024-11-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW112106697ATWI861739B (en) | 2022-03-11 | 2023-02-23 | Memory device |
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| TW (1) | TWI861739B (en) |
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