本發明是有關於固態儲存裝置，特別是有關於一種固態儲存裝置及其指令擷取方法。The present invention relates to a solid state storage device, and more particularly to a solid state storage device and an instruction capture method thereof.
固態儲存裝置(solid state storage device)是使用非揮發性記憶體(non-volatile memory)來儲存資料，隨著科技發展，其已廣泛地使用於不同的電腦系統之中。然而，由於非揮發性記憶體的特性，對非揮發性記憶體進行資料讀寫的次數與非揮發性記憶體的使用壽命息息相關。當主機端欲傳送大量的存取指令至傳統的固態儲存裝置時，傳統的固態儲存裝置往往會因為其硬體資源有限而無法從主機端持續擷取存取指令，且容易造成固態儲存裝置的快取記憶體被已擷取但尚未執行的存取指令佔用，進而降低固態儲存裝置的寫入或讀取效能。Solid state storage devices use non-volatile memory to store data. With the development of technology, they have been widely used in different computer systems. However, due to the characteristics of non-volatile memory, the number of times data is read and written to non-volatile memory is closely related to the service life of non-volatile memory. When the host wants to send a large number of access instructions to a traditional solid-state storage device, the traditional solid-state storage device is often unable to continuously capture access instructions from the host due to its limited hardware resources, and it is easy to cause the cache memory of the solid-state storage device to be occupied by access instructions that have been captured but not yet executed, thereby reducing the write or read performance of the solid-state storage device.
因此，本發明係提供一種固態儲存裝置及其指令擷取方法以解決上述問題。Therefore, the present invention provides a solid-state storage device and an instruction capture method thereof to solve the above-mentioned problem.
在一實施例中，本發明提供一種固態儲存裝置，經組態以電性連接至一主機。該固態儲存裝置包括：一控制器；一快取記憶體，電性連接至該控制器，其中該快取記憶體包括一第一區域及一第二區域；一揮發性記憶體，電性連接至該控制器；以及一非揮發性記憶體，電性連接至該控制器。該控制器經組態以由該主機擷取存取指令，並將該存取指令儲存於該第一區域。該控制器經組態以將儲存於該第一區域的該存取指令備份於該揮發性記憶體。該控制器經組態以將備份於該揮發性記憶體中的該存取指令儲存至該第二區域，並執行儲存至該第二區域的該存取指令。In one embodiment, the present invention provides a solid-state storage device configured to be electrically connected to a host. The solid-state storage device includes: a controller; a cache memory electrically connected to the controller, wherein the cache memory includes a first area and a second area; a volatile memory electrically connected to the controller; and a non-volatile memory electrically connected to the controller. The controller is configured to capture access instructions from the host and store the access instructions in the first area. The controller is configured to back up the access instructions stored in the first area in the volatile memory. The controller is configured to store the access command backed up in the volatile memory in the second area and execute the access command stored in the second area.
在另一實施例中，本發明更提供一種指令擷取方法，用於一固態儲存裝置，該固態儲存裝置電性連接至一主機，且該固態儲存裝置包括一控制器、一快取記憶體、一揮發性記憶體及一非揮發性記憶體。該方法包括：利用該控制器從該主機擷取存取指令，並將該存取指令儲存於該快取記憶體的第一區域；利用該控制器將儲存於該第一區域的該存取指令備份於該揮發性記憶體；以及利用該控制器將備份於該揮發性記憶體中的該存取指令儲存至該第二區域，並執行儲存至該第二區域的該存取指令。In another embodiment, the present invention further provides an instruction capture method for a solid state storage device, the solid state storage device is electrically connected to a host, and the solid state storage device includes a controller, a cache memory, a volatile memory, and a non-volatile memory. The method includes: using the controller to capture access instructions from the host, and storing the access instructions in a first area of the cache memory; using the controller to back up the access instructions stored in the first area in the volatile memory; and using the controller to store the access instructions backed up in the volatile memory in the second area, and executing the access instructions stored in the second area.
以下說明係為完成發明的較佳實現方式，其目的在於描述本發明的基本精神，但並不用以限定本發明。實際的發明內容必須參考之後的申請專利範圍。The following description is a preferred implementation method for completing the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the scope of the subsequent patent application.
必須了解的是，使用於本說明書中的「包含」、「包括」等詞，係用以表示存在特定的技術特徵、數值、方法步驟、作業處理、元件以及/或組件，但並不排除可加上更多的技術特徵、數值、方法步驟、作業處理、元件、組件，或以上的任意組合。It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, operation processes, elements and/or components, but do not exclude the addition of more technical features, numerical values, method steps, operation processes, elements, components, or any combination of the above.
於申請專利範圍中使用如「第一」、「第二」、「第三」等詞係用來修飾申請專利範圍中的元件，並非用來表示之間具有優先權順序，先行關係，或者是一個元件先於另一個元件，或者是執行方法步驟時的時間先後順序，僅用來區別具有相同名字的元件。The terms "first," "second," and "third" used in a patent application are used to modify the elements in the patent application and are not used to indicate a priority order, a precedence relationship, or that one element precedes another element, or a temporal sequence in performing method steps. They are only used to distinguish elements with the same name.
「經組態以(Configured To)」此用語可敘述或主張各種單元、電路、或其他組件為「經組態以」執行一任務或多個任務。在此類上下文中，「經組態以」此用語係用於藉由指示該等單元/電路/組件包括在操作期間執行彼等(一或多個)任務的結構(例如，電路系統)來暗示結構。因而，即使當指定單元/電路/組件當前並不操作(例如，未接通)，仍可稱該單元/電路/組件經組態以執行該任務。與「經組態以」此用語一起使用的該等單元/電路/組件包括硬體－例如：電路、記憶體（儲存可執行以實施操作之程式指令）等。此外，「經組態以」可包括通用結構(generic structure)(例如，通用電路系統)，其係藉由軟體及/或韌體(例如，FPGA或執行軟體的一般用途處理器)操縱，以能夠執行待解決之(一或多個)任務的方式進行操作。「經組態以」亦可包括調適一製造程序(例如，一半導體製造設備)以製造經調適以實施或執行一或多個任務的裝置(例如，積體電路)。The term "configured to" may describe or claim that various units, circuits, or other components are "configured to" perform a task or tasks. In such contexts, the term "configured to" is used to imply a structure by indicating that the units/circuits/components include a structure (e.g., a circuit system) that performs those task(s) during operation. Thus, even when the specified unit/circuit/component is not currently operating (e.g., not turned on), the unit/circuit/component may still be said to be configured to perform the task. The units/circuits/components used with the term "configured to" include hardware - e.g., circuits, memory (storing program instructions that can be executed to perform operations), etc. Additionally, "configured to" may include a generic structure (e.g., a generic circuit system) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the task(s) to be solved. "Configured to" may also include adapting a manufacturing process (e.g., semiconductor manufacturing equipment) to produce a device (e.g., an integrated circuit) that is adapted to implement or perform one or more tasks.
圖1係顯示依據本發明一實施例中之電腦系統的方塊圖。FIG. 1 is a block diagram showing a computer system according to an embodiment of the present invention.
如圖1所示，電腦系統1包括固態儲存裝置10及主機20，其中固態儲存裝置10係透過匯流排11以電性連接至主機20，藉以進行指令及資料傳輸。在一些實施例中，匯流排11可為通用序列匯流排(Universal Serial Bus，USB)、序列進階技術附接(Serial Advanced Technology Attachment，SATA)匯流排、週邊元件快速互連(PCI Express，PCIe)匯流排等等，但本揭露並不限於此。As shown in FIG1 , a computer system 1 includes a solid-state storage device 10 and a host computer 20, wherein the solid-state storage device 10 is electrically connected to the host computer 20 via a bus 11 for command and data transmission. In some embodiments, the bus 11 may be a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA) bus, a Peripheral Component Interconnect Express (PCI Express, PCIe) bus, etc., but the present disclosure is not limited thereto.
固態儲存裝置10包括控制器102、快取記憶體104、揮發性記憶體106及非揮發性記憶體108。控制器102係電性連接至快取記憶體104、揮發性記憶體106及非揮發性記憶體108，並用以控制快取記憶體104、揮發性記憶體106及非揮發性記憶體108之資料存取。在一些實施例中，控制器102例如可為通用處理器(general-purpose processor)、微控制器(microcontroller)、應用導向積體電路(application-specific integrated circuit，ASIC)、現場可程式化邏輯閘陣列(field-programmable gate array，FPGA)等等，但本揭露並不限於此。The solid state storage device 10 includes a controller 102, a cache memory 104, a volatile memory 106, and a non-volatile memory 108. The controller 102 is electrically connected to the cache memory 104, the volatile memory 106, and the non-volatile memory 108, and is used to control data access of the cache memory 104, the volatile memory 106, and the non-volatile memory 108. In some embodiments, the controller 102 may be, for example, a general-purpose processor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc., but the present disclosure is not limited thereto.
快取記憶體104例如包括靜態隨機存取記憶體(static random access memory，SRAM)。揮發性記憶體106例如包括動態隨機存取記憶體(dynamic random access memory，DRAM)，但本揭露並不限於此。在一些實施例中，快取記憶體104及揮發性記憶體106例如可設置於控制器102之外部。在另一些實施例中，快取記憶體104及揮發性記憶體106例如可整合至控制器102之中。非揮發性記憶體108例如為反及閘快閃記憶體(NAND flash memory)用以儲存主機20提供的寫入資料。The cache memory 104 includes, for example, a static random access memory (SRAM). The volatile memory 106 includes, for example, a dynamic random access memory (DRAM), but the present disclosure is not limited thereto. In some embodiments, the cache memory 104 and the volatile memory 106 may be disposed outside the controller 102. In other embodiments, the cache memory 104 and the volatile memory 106 may be integrated into the controller 102. The non-volatile memory 108 may be, for example, a NAND flash memory for storing write data provided by the host 20.
主機20例如包括處理器202及系統記憶體204，且處理器202係電性連接至系統記憶體204。在一些實施例中，處理器202例如包括中央處理器(central processing unit)、通用處理器、微處理器等等，但本揭露並不限於此。此外，處理器202包括控制器(未繪示)，用以控制系統記憶體204之資料存取。系統記憶體204例如包括動態隨機存取記憶體，但本揭露並不限於此。The host 20 includes, for example, a processor 202 and a system memory 204, and the processor 202 is electrically connected to the system memory 204. In some embodiments, the processor 202 includes, for example, a central processing unit, a general purpose processor, a microprocessor, etc., but the disclosure is not limited thereto. In addition, the processor 202 includes a controller (not shown) for controlling data access of the system memory 204. The system memory 204 includes, for example, a dynamic random access memory, but the disclosure is not limited thereto.
在一些實施例中，主機20例如可支援非揮發性記憶體通訊協定(NVM Express，NVMe)，且系統記憶體204中配置提交佇列(submission queue)2041、完成佇列(completion queue)2042及資料暫存器2043。提交佇列2041用以記錄處理器202所發出的存取指令，完成佇列2042用以記錄固態儲存裝置10回應已完成的存取指令之狀態。資料暫存器2043用以儲存主機20欲寫入至固態儲存裝置10的資料及用以儲存主機20從固態儲存裝置10所讀取的資料。In some embodiments, the host 20 may support the non-volatile memory communication protocol (NVM Express, NVMe), and the system memory 204 is configured with a submission queue 2041, a completion queue 2042, and a data register 2043. The submission queue 2041 is used to record the access instructions issued by the processor 202, and the completion queue 2042 is used to record the status of the solid state storage device 10 responding to the completed access instructions. The data register 2043 is used to store the data that the host 20 wants to write to the solid state storage device 10 and to store the data read by the host 20 from the solid state storage device 10.
在一些實施例中，固態儲存裝置10例如可支援非揮發性記憶體通訊協定(NVM Express，NVMe)，且控制器102可從主機20的提交佇列2041擷取存取指令，例如，寫入指令、讀取指令等，並將所擷取的存取指令儲存至快取記憶體104。In some embodiments, the solid state storage device 10 may support the non-volatile memory communication protocol (NVM Express, NVMe), and the controller 102 may capture access instructions, such as write instructions, read instructions, etc., from the submit queue 2041 of the host 20, and store the captured access instructions in the cache memory 104.
非揮發性記憶體108包括複數個區塊(block)，且每個區塊包括複數個頁面(page)。舉例來說，非揮發性記憶體108包含1024個區塊，且每個區塊包括64頁。假設每個頁面的容量為16Kbytes，則每個區塊的容量為1Mbytes。上述數據僅用於說明，且非揮發性記憶體108的製造商可以決定每個區塊中的頁面數以及每個頁面的容量。The non-volatile memory 108 includes a plurality of blocks, and each block includes a plurality of pages. For example, the non-volatile memory 108 includes 1024 blocks, and each block includes 64 pages. Assuming that the capacity of each page is 16Kbytes, the capacity of each block is 1Mbyte. The above data is for illustration only, and the manufacturer of the non-volatile memory 108 can determine the number of pages in each block and the capacity of each page.
圖2A為依據本發明一實施例中之快取記憶體的示意圖。圖2B～2D為依據本發明圖2A的實施例的快取記憶體的使用情境的示意圖。Fig. 2A is a schematic diagram of a cache memory according to an embodiment of the present invention. Fig. 2B to Fig. 2D are schematic diagrams of usage scenarios of the cache memory according to the embodiment of Fig. 2A of the present invention.
在一些實施例中，相較於主機20的提交佇列2041所能儲存的存取指令的數目(至多64K個)，因為固態儲存裝置10的快取記憶體104的容量通常有限，快取記憶體104所能儲存的存取指令的數目亦相當有限。在一些實施例中，快取記憶體104包括256個項目(entry)S0～S255，且各個項目S0～S255均具有對應的遮罩位元(mask bit)MB0～MB255。控制器102係依據各個遮罩位元MB0～M255的數值以決定是否將從主機20的提交佇列2041所擷取的存取指令儲存於空的項目S0~S255中。需注意的是，快取記憶體104中之項目的數量可視快取記憶體104的實際容量大小而改變，且上述實施例中的256個項目僅為說明之用，但本發明並不限於此。In some embodiments, compared to the number of access instructions that can be stored in the commit queue 2041 of the host 20 (up to 64K), because the capacity of the cache memory 104 of the solid state storage device 10 is usually limited, the number of access instructions that can be stored in the cache memory 104 is also quite limited. In some embodiments, the cache memory 104 includes 256 entries S0~S255, and each entry S0~S255 has a corresponding mask bit MB0~MB255. The controller 102 determines whether to store the access instruction captured from the commit queue 2041 of the host 20 in the empty entry S0~S255 according to the value of each mask bit MB0~M255. It should be noted that the number of entries in the cache memory 104 may vary depending on the actual capacity of the cache memory 104, and the 256 entries in the above embodiment are for illustration only, but the present invention is not limited thereto.
舉例來說，NVMe標準的存取指令大小固定為64位元組(bytes)，且提交佇列2041中的每個項目的尺寸(size)亦符合此固定指令尺寸。此外，快取記憶體104的各個項目的尺寸亦符合此固定指令尺寸。For example, the access instruction size of the NVMe standard is fixed to 64 bytes, and the size of each item in the submission queue 2041 also conforms to this fixed instruction size. In addition, the size of each item of the cache memory 104 also conforms to this fixed instruction size.
在一些實施例中，若特定項目相應的遮罩位元的數值為0，則表示該特定項目為空項目。因此，控制器102可將從主機20的提交佇列2041所擷取的一個存取指令儲存至該特定項目。若特定項目相應的遮罩位元的數值為1，則表示該特定項目已被佔用或被遮蔽。因此，當控制器102從主機20的提交佇列2041擷取一個存取指令後，控制器102不會將所擷取的此存取指令儲存於該特定項目中。In some embodiments, if the value of the mask bit corresponding to a specific item is 0, it indicates that the specific item is an empty item. Therefore, the controller 102 can store an access instruction captured from the submission queue 2041 of the host 20 to the specific item. If the value of the mask bit corresponding to the specific item is 1, it indicates that the specific item has been occupied or masked. Therefore, when the controller 102 captures an access instruction from the submission queue 2041 of the host 20, the controller 102 will not store the captured access instruction in the specific item.
在一些實施例中，當固態儲存裝置10開機時，快取記憶體104中的各項目S0～S255均為空項目，且各項目S0～S255相應的遮罩位元的數值均為0，如圖2B所示。當控制器102從主機20的提交佇列2041擷取一或多個存取指令，控制器102會將所擷取的一或多個存取指令逐一寫入至快取記憶體104中的空項目，例如控制器102從項目S0開始將擷取的存取指令CMD0~CMD2寫入至項目S0、S1及S2，並將項目S0、S1、S2相應的遮罩位元MB0、MB1及MB2的數值修改為1，如圖2C所示。當控制器102從主機20的提交佇列2041擷取的存取指令的數量足夠多時，快取記憶體104中的所有項目S0～S255均會存放一個存取指令(例如存取指令CMD0~CMD255)，且各項目S0～S255相應的遮罩位元的數值均會被修改為1，如圖2D所示。In some embodiments, when the solid state storage device 10 is powered on, each entry S0-S255 in the cache memory 104 is an empty entry, and the value of the mask bit corresponding to each entry S0-S255 is 0, as shown in FIG2B. When the controller 102 captures one or more access instructions from the submit queue 2041 of the host 20, the controller 102 writes the captured one or more access instructions one by one into the empty entry in the cache memory 104, for example, the controller 102 writes the captured access instructions CMD0-CMD2 into the entries S0, S1 and S2 starting from the entry S0, and modifies the values of the mask bits MB0, MB1 and MB2 corresponding to the entries S0, S1 and S2 to 1, as shown in FIG2C. When the controller 102 captures enough access instructions from the commit queue 2041 of the host 20, all entries S0-S255 in the cache memory 104 will store an access instruction (eg, access instructions CMD0-CMD255), and the values of the corresponding mask bits of each entry S0-S255 will be modified to 1, as shown in FIG. 2D.
然而，當圖2D的情況發生時，表示快取記憶體104的所有項目均已被佔用，故此時控制器102無法再從主機20的提交佇列2041擷取存取指令。此外，快取記憶體104中的各項目S0～S255並非全部用於暫時存放存取指令，有部分項目會用於指令執行階段(command execution stage)及指令完成階段(command completion stage)。因此快取記憶體104可用於暫時存放存取指令的項目數量會少於256個。However, when the situation shown in FIG. 2D occurs, it means that all entries in the cache memory 104 are occupied, so the controller 102 can no longer retrieve access instructions from the commit queue 2041 of the host 20. In addition, not all entries S0-S255 in the cache memory 104 are used to temporarily store access instructions, and some entries are used in the command execution stage and the command completion stage. Therefore, the number of entries in the cache memory 104 that can be used to temporarily store access instructions is less than 256.
圖3A為依據本發明另一實施例中的快取記憶體的示意圖。圖3B-3C為依據本發明圖3A實施例中的快取記憶體的使用情境的示意圖。Fig. 3A is a schematic diagram of a cache memory in another embodiment of the present invention. Fig. 3B-3C are schematic diagrams of usage scenarios of the cache memory in the embodiment of Fig. 3A according to the present invention.
在一些實施例中，快取記憶體104可劃分為指令擷取區域310及指令執行區域320。指令擷取區域310是用於儲存控制器102從主機20的提交佇列2041所擷取的存取指令。指令執行區域320則是用於儲存控制器102在執行指令階段所執行的一或多個存取指令，且指令執行區域320亦可視為是固態儲存裝置10的提交佇列。詳細而言，當固態儲存裝置10開機時，快取記憶體104中的256個項目S0～S255中的一第一部分會被控制器102配置為指令擷取區域310，且一第二部分會被控制器102配置為指令執行區域320。在指令擷取區域310及指令執行區域320中的項目數量可依實際情況而進行調整。In some embodiments, the cache memory 104 can be divided into an instruction capture area 310 and an instruction execution area 320. The instruction capture area 310 is used to store access instructions captured by the controller 102 from the commit queue 2041 of the host 20. The instruction execution area 320 is used to store one or more access instructions executed by the controller 102 in the instruction execution stage, and the instruction execution area 320 can also be regarded as the commit queue of the solid state storage device 10. Specifically, when the solid state storage device 10 is powered on, a first portion of the 256 entries S0-S255 in the cache memory 104 is configured by the controller 102 as the instruction capture area 310, and a second portion is configured by the controller 102 as the instruction execution area 320. The number of entries in the instruction capture area 310 and the instruction execution area 320 can be adjusted according to actual conditions.
詳細而言，當固態儲存裝置10開機時，指令擷取區域310及指令執行區域320中的各項目均為空項目，且控制器102會將指令擷取區域310中的各項目相應的遮罩位元的數值初始化為0(例如為第一數值)，並將指令執行區域320中的各項目相應的遮罩位元的數值初始化為1(例如為第二數值)，如圖3A所示。當指令執行區域320中的各項目相應的遮罩位元的數值初始化完畢後，控制器102即不會再修改指令執行區域320中的任一項目相應的遮罩位元的數值。意即，指令執行區域320的各項目相應的遮罩位元的數值會維持在1。因此，當控制器102從主機20的提交佇列2041擷取存取指令時，控制器102不會將所擷取的存取指令儲存至指令執行區域320。In detail, when the solid state storage device 10 is powered on, each item in the instruction capture area 310 and the instruction execution area 320 is an empty item, and the controller 102 initializes the value of the mask bit corresponding to each item in the instruction capture area 310 to 0 (for example, a first value), and initializes the value of the mask bit corresponding to each item in the instruction execution area 320 to 1 (for example, a second value), as shown in FIG3A. After the value of the mask bit corresponding to each item in the instruction execution area 320 is initialized, the controller 102 will no longer modify the value of the mask bit corresponding to any item in the instruction execution area 320. That is, the value of the mask bit corresponding to each item in the instruction execution area 320 will remain at 1. Therefore, when the controller 102 captures an access instruction from the commit queue 2041 of the host 20 , the controller 102 does not store the captured access instruction in the instruction execution area 320 .
當控制器102從主機20的提交佇列2041擷取一或多個存取指令(例如存取指令CMD0 、CMD1及CMD2)，控制器102會將所擷取的一或多個存取指令逐一寫入至指令擷取區域310的空項目，例如控制器102從項目S0開始將擷取的存取指令寫入至項目S0、S1及S2，並將項目S0、S1及S2相應的遮罩位元MB0、MB1及MB2的數值修改為1，如圖3B所示。需注意的是，在儲存所擷取的存取指令的上述過程中，指令執行區域320的各項目相應的遮罩位元的數值均維持在1。When the controller 102 captures one or more access instructions (e.g., access instructions CMD0, CMD1, and CMD2) from the commit queue 2041 of the host 20, the controller 102 writes the captured one or more access instructions one by one into the empty entries of the instruction capture area 310. For example, the controller 102 writes the captured access instructions into entries S0, S1, and S2 starting from entry S0, and modifies the values of the mask bits MB0, MB1, and MB2 corresponding to entries S0, S1, and S2 to 1, as shown in FIG3B. It should be noted that in the above process of storing the captured access instructions, the values of the mask bits corresponding to each entry in the instruction execution area 320 are all maintained at 1.
當控制器102將所擷取的一或多個存取指令逐一寫入至指令擷取區域310的空項目時，控制器102亦會同時將已儲存至指令擷取區域310的存取指令備份至揮發性記憶體106，例如可採用逐一備份或是批次備份的方式。如圖3C所示，控制器102除了將所擷取的存取指令CMD3寫入至項目S3並修改其相應的遮罩位元的數值之外，控制器102並將原本已儲存至項目S0～S2的存取指令CMD0～CMD2備份至揮發性記憶體106，並且將項目S0～S2相應的遮罩位元MB0～MB2的數值修改為0。在一些實施例中，當控制器102將已儲存至指令擷取區域310的存取指令備份至揮發性記憶體106時，控制器102可修改該存取指令之項目所對應的遮罩位元的數值為0以表示該項目已為空項目，可再將後續所擷取的存取指令寫入至該項目。在另一些實施例中，當控制器102將已儲存至指令擷取區域310的存取指令備份至揮發性記憶體106時，控制器102可清除該存取指令之項目的內容並修改該存取指令之項目所對應的遮罩位元的數值為0。When the controller 102 writes the captured one or more access instructions into the empty entries of the instruction capture area 310 one by one, the controller 102 will also simultaneously back up the access instructions stored in the instruction capture area 310 to the volatile memory 106, for example, by backing up one by one or in batches. As shown in FIG. 3C , in addition to writing the captured access instruction CMD3 into the entry S3 and modifying the value of the corresponding mask bit, the controller 102 also backs up the access instructions CMD0-CMD2 originally stored in the entries S0-S2 to the volatile memory 106, and modifies the values of the corresponding mask bits MB0-MB2 of the entries S0-S2 to 0. In some embodiments, when the controller 102 backs up the access instruction stored in the instruction capture area 310 to the volatile memory 106, the controller 102 may modify the value of the mask bit corresponding to the entry of the access instruction to 0 to indicate that the entry is an empty entry, and then write the access instruction captured subsequently to the entry. In other embodiments, when the controller 102 backs up the access instruction stored in the instruction capture area 310 to the volatile memory 106, the controller 102 may clear the content of the entry of the access instruction and modify the value of the mask bit corresponding to the entry of the access instruction to 0.
圖4為依據本發明一實施例中之固態儲存裝置的指令擷取及指令執行流程的示意圖。請同時參考圖1、圖3A及圖4。FIG4 is a schematic diagram of the instruction capture and instruction execution process of a solid state storage device according to an embodiment of the present invention. Please refer to FIG1, FIG3A and FIG4 at the same time.
當處理器202發出一存取指令(例如可為寫入指令或讀取指令)時，處理器202將該存取指令寫入至提交佇列2041(箭頭402)。若該存取指令為寫入指令，處理器202並將該存取指令相應的資料寫入至資料暫存器2043(箭頭404)。固態儲存裝置10的控制器102會定時查看提交佇列2041是否有新的存取指令被提交。若在提交佇列2041有新的存取指令，控制器102從提交佇列2041擷取新提交的存取指令(箭頭406)，並將所擷取的存取指令儲存至快取記憶體104中的指令擷取區域310(箭頭408)。When the processor 202 issues an access instruction (e.g., a write instruction or a read instruction), the processor 202 writes the access instruction to the commit queue 2041 (arrow 402). If the access instruction is a write instruction, the processor 202 also writes the data corresponding to the access instruction to the data register 2043 (arrow 404). The controller 102 of the solid state storage device 10 will periodically check whether there is a new access instruction submitted to the commit queue 2041. If there is a new access instruction in the commit queue 2041, the controller 102 captures the newly submitted access instruction from the commit queue 2041 (arrow 406), and stores the captured access instruction in the instruction capture area 310 in the cache memory 104 (arrow 408).
控制器102並接著將已儲存至指令擷取區域310中的存取指令備份至揮發性記憶體106(箭頭410)，並清除已備份的存取指令的項目的遮罩位元的數值(箭頭412)。上述箭頭410及412的操作可重複執行。當控制器102進入指令執行階段以執行存取指令時，控制器102將備份至揮發性記憶體106的一或多個存取指令寫入至快取記憶體104的指令執行區域320(箭頭414)，並從指令執行區域320讀取其中一個存取指令並執行(箭頭416)。若執行的該存取指令為寫入指令，則控制器102會從主機20的資料暫存器2043擷取該存取指令相應的寫入資料(箭頭418)，並將該寫入資料儲存至快取記憶體104(指令執行區域320)(箭頭420)。控制器102再將儲存至快取記憶體104的寫入資料編程(program)至非揮發性記憶體108(箭頭422)。The controller 102 then backs up the access instructions stored in the instruction capture area 310 to the volatile memory 106 (arrow 410), and clears the value of the mask bit of the item of the backed-up access instruction (arrow 412). The operations of the arrows 410 and 412 can be repeated. When the controller 102 enters the instruction execution phase to execute the access instructions, the controller 102 writes one or more access instructions backed up to the volatile memory 106 to the instruction execution area 320 of the cache memory 104 (arrow 414), and reads one of the access instructions from the instruction execution area 320 and executes it (arrow 416). If the access instruction executed is a write instruction, the controller 102 will capture the write data corresponding to the access instruction from the data register 2043 of the host 20 (arrow 418), and store the write data to the cache memory 104 (instruction execution area 320) (arrow 420). The controller 102 then programs the write data stored in the cache memory 104 to the non-volatile memory 108 (arrow 422).
當欲執行的該存取指令為讀取指令，控制器102同樣從指令執行區域320讀取該存取指令並執行(箭頭424)。若該存取指令的資料未暫存於快取記憶體104或揮發性記憶體106中，控制器102會從非揮發性記憶體108讀取該存取指令相應的讀取資料(箭頭426)，並將該筆讀取資料寫入至主機20的資料暫存器2043(箭頭428)。When the access instruction to be executed is a read instruction, the controller 102 also reads the access instruction from the instruction execution area 320 and executes it (arrow 424). If the data of the access instruction is not temporarily stored in the cache 104 or the volatile memory 106, the controller 102 reads the read data corresponding to the access instruction from the non-volatile memory 108 (arrow 426), and writes the read data to the data register 2043 of the host 20 (arrow 428).
需注意的是，儘管在圖4的流程中並未繪示主機20的完成佇列2042，當控制器102完成一個存取指令(可以是寫入指令或讀取指令)時，控制器102會將該存取指令的指令完成資訊寫入至快取記憶體104中的完成佇列(第1圖未繪示)，再將該已完成的存取指令從快取記憶體104的提交佇列(第1圖未繪示)刪除。接著，控制器102再將已完成的存取指令的指令完成資訊寫入至主機20的完成佇列2042，並將已完成的存取指令從主機20的提交佇列2041刪除。It should be noted that although the completion queue 2042 of the host 20 is not shown in the process of FIG. 4 , when the controller 102 completes an access instruction (which may be a write instruction or a read instruction), the controller 102 writes the instruction completion information of the access instruction into the completion queue (not shown in FIG. 1 ) of the cache memory 104, and then deletes the completed access instruction from the commit queue (not shown in FIG. 1 ) of the cache memory 104. Then, the controller 102 writes the instruction completion information of the completed access instruction into the completion queue 2042 of the host 20, and deletes the completed access instruction from the commit queue 2041 of the host 20.
在一些實施例中，主機20的處理器202所發出的複數個存取指令可能對於固態儲存裝置10而言是連續寫入(sequential write)的複數個寫入指令或是連續讀取(sequential read)的複數個讀取指令。然而，因為主機20所運行的作業系統(未繪示)可能會隨時需要對固態儲存裝置10寫入系統記錄檔(system log file)或從固態儲存裝置10讀取系統記錄檔，所以系統記錄檔的寫入指令或讀取指令可能穿插在連續的複數個寫入指令/讀取指令之間。在此情況下，傳統的固態儲存裝置的控制器會判斷該些存取指令為隨機寫入(random write)的寫入指令或是隨機讀取(random read)的讀取指令，這會對傳統的固態儲存裝置的寫入或讀取效能造成影響。然而，經由本發明的快取記憶體104的指令擷取區域310及指令執行區域320的設計，控制器102可將已儲存於指令擷取區域310的存取指令備份於揮發性記憶體106，並且在指令執行階段才將欲執行的存取指令儲存於指令執行區域320。因此，控制器102不但可持續地從主機20的提交佇列2041擷取新的存取指令，並且可從已備份至揮發性記憶體106的存取指令中過濾出主機20所發出的系統記錄檔的寫入指令，藉以讓後續儲存至指令執行區域320的待執行存取指令可以構成連續寫入的寫入指令，藉以提昇固態儲存裝置10的效能。In some embodiments, the plurality of access instructions issued by the processor 202 of the host 20 may be a plurality of sequential write instructions or a plurality of sequential read instructions for the solid state storage device 10. However, because the operating system (not shown) running by the host 20 may need to write a system log file to the solid state storage device 10 or read the system log file from the solid state storage device 10 at any time, the write instructions or read instructions of the system log file may be interspersed between the plurality of sequential write instructions/read instructions. In this case, the controller of the conventional solid-state storage device will determine that the access instructions are random write instructions or random read instructions, which will affect the write or read performance of the conventional solid-state storage device. However, through the design of the instruction capture area 310 and the instruction execution area 320 of the cache memory 104 of the present invention, the controller 102 can back up the access instructions stored in the instruction capture area 310 in the volatile memory 106, and store the access instructions to be executed in the instruction execution area 320 during the instruction execution stage. Therefore, the controller 102 can not only continuously capture new access instructions from the submit queue 2041 of the host 20, but also filter out the write instructions of the system log file issued by the host 20 from the access instructions that have been backed up to the volatile memory 106, so that the access instructions to be executed that are subsequently stored in the instruction execution area 320 can constitute continuous write instructions, thereby improving the performance of the solid state storage device 10.
圖5為依據本發明一實施例中用於固態儲存裝置的指令擷取方法的流程圖。請同時參考圖1、圖3A及圖5。FIG5 is a flow chart of a method for capturing instructions for a solid-state storage device according to an embodiment of the present invention. Please refer to FIG1, FIG3A and FIG5 at the same time.
在步驟510，控制器102由主機20的提交佇列2041擷取存取指令，並將存取指令儲存於快取記憶體104的指令擷取區域310。舉例而言，快取記憶體104可劃分為指令擷取區域310及指令執行區域320。指令擷取區域310是用於儲存控制器102從主機20的提交佇列2041所擷取的存取指令。指令執行區域320則是用於儲存控制器102在執行指令階段所執行的一或多個存取指令。In step 510, the controller 102 captures access instructions from the commit queue 2041 of the host 20 and stores the access instructions in the instruction capture area 310 of the cache memory 104. For example, the cache memory 104 can be divided into the instruction capture area 310 and the instruction execution area 320. The instruction capture area 310 is used to store the access instructions captured by the controller 102 from the commit queue 2041 of the host 20. The instruction execution area 320 is used to store one or more access instructions executed by the controller 102 in the instruction execution stage.
在步驟520，控制器102將指令擷取區域310中已儲存的存取指令備份於揮發性記憶體106。舉例而言，主機20的處理器202會發出大量的存取指令，並將該些存取指令儲存於提交佇列2041中。此外，在固態儲存裝置10的控制器102在執行存取指令之前，控制器102需先將從提交佇列2041所擷取的存取指令儲存至快取記憶體104的指令擷取區域310。然而，指令擷取區域310的容量有限，故控制器102在將從提交佇列2041擷取的存取指令寫入至指令擷取區域310時，控制器102同時將已儲存至指令擷取區域310的存取指令備份至揮發性記憶體106，並將已備份的存取指令之項目相應的遮罩位元的數值清除(例如設定為0)，藉以將指令擷取區域310中已被佔用的項目清除為空項目，故控制器102可進一步從主機20的提交佇列2041擷取更多的存取指令。在一實施例中，該備份的存取指令相同於剛剛從主機20的提交佇列2041擷取的存取命令，亦即當控制器102將從提交佇列2041所擷取的存取指令儲存至快取記憶體104的指令擷取區域310時，同步的將該存取指令備份至揮發性記憶體106。在一實施例中，該備份的存取指令不相同於剛剛從主機20的提交佇列2041擷取的存取命令，亦即控制器102備份的存取指令是之前已經儲存於指令擷取區域310的存取指令，而非剛從主機20的提交佇列2041擷取的存取命令。In step 520, the controller 102 backs up the access instructions stored in the instruction capture area 310 in the volatile memory 106. For example, the processor 202 of the host 20 issues a large number of access instructions and stores these access instructions in the commit queue 2041. In addition, before the controller 102 of the solid state storage device 10 executes the access instructions, the controller 102 needs to first store the access instructions captured from the commit queue 2041 in the instruction capture area 310 of the cache memory 104. However, the capacity of the instruction capture area 310 is limited. Therefore, when the controller 102 writes the access instruction captured from the submit queue 2041 to the instruction capture area 310, the controller 102 simultaneously backs up the access instruction stored in the instruction capture area 310 to the volatile memory 106, and clears the value of the mask bit corresponding to the item of the backed-up access instruction (for example, sets it to 0), thereby clearing the occupied items in the instruction capture area 310 to empty items, so that the controller 102 can further capture more access instructions from the submit queue 2041 of the host 20. In one embodiment, the backup access command is the same as the access command just captured from the commit queue 2041 of the host 20, that is, when the controller 102 stores the access command captured from the commit queue 2041 in the command capture area 310 of the cache 104, the access command is synchronously backed up to the volatile memory 106. In one embodiment, the backup access command is different from the access command just captured from the commit queue 2041 of the host 20, that is, the access command backed up by the controller 102 is the access command that has been previously stored in the command capture area 310, rather than the access command just captured from the commit queue 2041 of the host 20.
在步驟530，控制器102將儲存於揮發性記憶體106的存取指令儲存至快取記憶體104的指令執行區域320。舉例而言，當控制器102進入指令執行階段以執行存取指令時，控制器102將備份至揮發性記憶體106的存取指令寫入至快取記憶體104的指令執行區域320，並從指令執行區域320讀取其中一個存取指令並執行。In step 530, the controller 102 stores the access instructions stored in the volatile memory 106 in the instruction execution area 320 of the cache memory 104. For example, when the controller 102 enters the instruction execution phase to execute the access instructions, the controller 102 writes the access instructions backed up to the volatile memory 106 to the instruction execution area 320 of the cache memory 104, and reads one of the access instructions from the instruction execution area 320 and executes it.
在步驟540，控制器102執行儲存至指令執行區域320的存取指令，並清除指令執行區域320中的該存取指令相應的項目。In step 540 , the controller 102 executes the access instruction stored in the instruction execution area 320 , and clears the entry corresponding to the access instruction in the instruction execution area 320 .
圖6為本發明又一實施例中的快取記憶體的示意圖。FIG6 is a schematic diagram of a cache memory in another embodiment of the present invention.
在一些實施例中，快取記憶體104可劃分為指令擷取區域310、指令執行區域320及指令完成區域330，其中指令擷取區域310及指令執行區域320的功用請參考圖3A的實施例。指令完成區域330是用於儲存在指令執行區域320中已被控制器102執行完畢的存取指令的指令完成資訊，故指令完成區域330亦可視為是固態儲存裝置10的完成佇列。在指令擷取區域310、指令執行區域320及指令完成區域330中的項目數量可依實際情況而進行調整。In some embodiments, the cache memory 104 can be divided into an instruction capture area 310, an instruction execution area 320, and an instruction completion area 330, wherein the functions of the instruction capture area 310 and the instruction execution area 320 are shown in the embodiment of FIG. 3A. The instruction completion area 330 is used to store instruction completion information of the access instructions that have been executed by the controller 102 in the instruction execution area 320, so the instruction completion area 330 can also be regarded as the completion queue of the solid state storage device 10. The number of items in the instruction capture area 310, the instruction execution area 320, and the instruction completion area 330 can be adjusted according to actual conditions.
詳細而言，圖6的快取記憶體104之設計可將存取指令更進一步細分為指令擷取階段、指令執行階段及指令完成階段，且指令完成階段有個別的指令完成區域330以存放已執行完畢的存取指令的指令完成資訊，可不用將指令完成資訊與欲執行的存取指令混用於指令執行區域320中。因此，在某些情況下，圖6之快取記憶體104的設計可進一步提昇固態儲存裝置10的效能。In detail, the design of the cache memory 104 of FIG6 can further divide the access instruction into the instruction capture stage, the instruction execution stage and the instruction completion stage, and the instruction completion stage has a separate instruction completion area 330 to store the instruction completion information of the access instruction that has been executed, and the instruction completion information does not need to be mixed with the access instruction to be executed in the instruction execution area 320. Therefore, in some cases, the design of the cache memory 104 of FIG6 can further improve the performance of the solid state storage device 10.
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.
1:電腦系統 10:固態儲存裝置 11:匯流排 20:主機 102:控制器 104:快取記憶體 106:揮發性記憶體 108:非揮發性記憶體 202:處理器 204:系統記憶體 310:指令擷取區域 320:指令執行區域 330:指令完成區域 402-428:箭頭 500:方法 510-540:步驟 2041:提交佇列 2042:完成佇列 2043:資料暫存器 CMD0-CMD255:存取指令 MB0-MB255:遮罩位元 S0-S255:項目1: Computer system10: Solid-state storage device11: Bus20: Host102: Controller104: Cache memory106: Volatile memory108: Non-volatile memory202: Processor204: System memory310: Instruction capture area320: Instruction execution area330: Instruction completion area402-428: Arrow500: Method510-540: Steps2041: Submit queue2042: Completion queue2043: Data registerCMD0-CMD255: Access instructionMB0-MB255: Mask bitsS0-S255: Item
圖1係顯示依據本發明一實施例中之電腦系統的方塊圖。 圖2A為依據本發明一實施例中之快取記憶體的示意圖。 圖2B～2D為依據本發明圖2A的實施例的快取記憶體的使用情境的示意圖。 圖3A為依據本發明另一實施例中的快取記憶體的示意圖。 圖3B-3C為依據本發明圖3A實施例中的快取記憶體的使用情境的示意圖。 圖4為依據本發明一實施例中之固態儲存裝置的指令擷取及指令執行流程的示意圖。 圖5為依據本發明一實施例中用於固態儲存裝置的指令擷取方法的流程圖。 圖6為本發明又一實施例中的快取記憶體的示意圖。FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention.FIG. 2A is a schematic diagram of a cache memory according to an embodiment of the present invention.FIG. 2B to 2D are schematic diagrams of a use scenario of a cache memory according to the embodiment of FIG. 2A of the present invention.FIG. 3A is a schematic diagram of a cache memory according to another embodiment of the present invention.FIG. 3B-3C are schematic diagrams of a use scenario of a cache memory according to the embodiment of FIG. 3A of the present invention.FIG. 4 is a schematic diagram of an instruction capture and instruction execution process of a solid state storage device according to an embodiment of the present invention.FIG. 5 is a flow chart of an instruction capture method for a solid state storage device according to an embodiment of the present invention.Figure 6 is a schematic diagram of a cache memory in another embodiment of the present invention.
500:方法500:Methods
510-540:步驟510-540: Steps
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| US18/678,386US20250077414A1 (en) | 2023-09-01 | 2024-05-30 | Solid-state storage device and method for fetching commands thereof |
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| TW112133296ATWI850095B (en) | 2023-09-01 | 2023-09-01 | Solid state storage device and method for fetching commands thereof |
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| TW112133296ATWI850095B (en) | 2023-09-01 | 2023-09-01 | Solid state storage device and method for fetching commands thereof |
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| TW201823971A (en)* | 2016-12-12 | 2018-07-01 | 美商英特爾股份有限公司 | Apparatuses and methods for a processor architecture |
| TW202117550A (en)* | 2019-10-29 | 2021-05-01 | 南韓商三星電子股份有限公司 | Storage device and method for storage device characteristics self monitoring |
| TWI741425B (en)* | 2018-12-31 | 2021-10-01 | 美商美光科技公司 | Sequential data optimized sub-regions in storage devices |
| TW202225987A (en)* | 2020-12-21 | 2022-07-01 | 韓商愛思開海力士有限公司 | Method for assigning a plurality of channels of a storage device for stream data writing, storage device and storage medium thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201823971A (en)* | 2016-12-12 | 2018-07-01 | 美商英特爾股份有限公司 | Apparatuses and methods for a processor architecture |
| TWI741425B (en)* | 2018-12-31 | 2021-10-01 | 美商美光科技公司 | Sequential data optimized sub-regions in storage devices |
| TW202117550A (en)* | 2019-10-29 | 2021-05-01 | 南韓商三星電子股份有限公司 | Storage device and method for storage device characteristics self monitoring |
| TW202225987A (en)* | 2020-12-21 | 2022-07-01 | 韓商愛思開海力士有限公司 | Method for assigning a plurality of channels of a storage device for stream data writing, storage device and storage medium thereof |
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|---|---|
| TW202511958A (en) | 2025-03-16 |
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