本發明是有關於一種三維記憶體裝置，且特別是有關於一種可提升感測結果準確性的三維記憶體裝置。The present invention relates to a three-dimensional memory device, and in particular, to a three-dimensional memory device that can improve the accuracy of sensing results.
在記憶體裝置中，當高速的資料感測動作被執行時，由於位元線電壓無法快速的穩定，因此，感測放大器的感測路徑上常會出現額外的偏移電流。如果在記憶胞進行感測動作時，並同時對位元線的負載進行充電，那麼高達幾微安培的位移電流（與記憶胞的讀取電流相近）將影響感測的精確度。In memory devices, when high-speed data sensing operations are performed, additional offset current often appears on the sensing path of the sense amplifier because the bit line voltage cannot stabilize quickly. If the load of the bit line is charged while the memory cell is performing a sensing action, a displacement current of up to several microamps (similar to the read current of the memory cell) will affect the accuracy of the sensing.
本發明提供一種三維記憶體裝置，可提升資料讀取的準確性。The invention provides a three-dimensional memory device that can improve the accuracy of data reading.
本發明的三維記憶體裝置包括記憶胞區塊、多個源極線開關、多個第一位元線開關至多個第四位元線開關。記憶胞區塊區分為第一記憶胞子區塊以及第二記憶胞子區塊。第一記憶胞子區塊具有多個第一記憶胞，第二記憶胞子區塊具有多個第二記憶胞。多個源極線開關共同耦接至共用源極線，並分別耦接至該第一記憶胞子區塊的多條第一源極線以及第二記憶胞子區塊的多條第二源極線。第一位元線開關共同耦接至第一共用位元線，並分別耦接至第一記憶胞子區塊的第一部分的多條第一位元線。第二位元線開關共同耦接至第二共用位元線，並分別耦接至第一記憶胞子區塊的第二部分的多條第二位元線。第三位元線開關共同耦接至第三共用位元線，並分別耦接至第二記憶胞子區塊的第一部分的多條第三位元線。第四位元線開關共同耦接至第四共用位元線，並分別耦接至第二記憶胞子區塊的第二部分的多條第四位元線。The three-dimensional memory device of the present invention includes a memory cell block, a plurality of source line switches, a plurality of first cell line switches to a plurality of fourth bit line switches. The memory cell block is divided into a first memory cell sub-block and a second memory cell sub-block. The first memory cell sub-block has a plurality of first memory cells, and the second memory cell sub-block has a plurality of second memory cells. A plurality of source line switches are jointly coupled to a common source line, and are respectively coupled to a plurality of first source lines of the first memory cell sub-block and a plurality of second source lines of the second memory cell sub-block. . The first element line switches are commonly coupled to the first common bit line and are respectively coupled to the plurality of first element lines in the first part of the first memory cell sub-block. The second bit line switches are commonly coupled to the second common bit line and are respectively coupled to a plurality of second bit lines in the second part of the first memory cell sub-block. The third bit line switches are commonly coupled to the third common bit line and respectively coupled to a plurality of third bit lines in the first part of the second memory cell sub-block. The fourth bit line switches are commonly coupled to the fourth common bit line and respectively coupled to a plurality of fourth bit lines in the second part of the second memory cell sub-block.
基於上述，本發明的三維記憶體裝置透過使記憶胞區塊區分為兩個記憶胞子區塊。透過分別對應記憶胞子區塊的不同的位元線開關，在資料讀取動作中，使選中記憶胞，與未被選中的記憶胞子區塊提供參考記憶胞耦接至感測放大器。如此一來，感測放大器二輸入端上的負載均勻度可以上升，並提升資料讀取的準確性。Based on the above, the three-dimensional memory device of the present invention divides the memory cell block into two memory cell sub-blocks. Through different bit line switches respectively corresponding to the memory cell sub-blocks, during the data reading operation, the selected memory cells and the unselected memory cell sub-blocks provide reference memory cells coupled to the sense amplifier. In this way, the load uniformity on the two input terminals of the sense amplifier can be increased and the accuracy of data reading can be improved.
請參照圖1，圖1繪示本發明一實施例的三維記憶體裝置的示意圖。三維記憶體裝置100包括記憶胞區塊101、源極線開關SLT1~SLT16、位元線開關BLT1a~BLT16a以及位元線開關BLT1b~BLT16b。記憶胞區塊101可被區分為記憶胞子區塊110以及120。記憶胞子區塊110包括堆疊配置的多個記憶胞MC1，記憶胞子區塊120包括堆疊配置的多個記憶胞MC2。在本實施例中，記憶胞區塊101可以是三維堆疊式的及式（AND）快閃記憶區塊或反或式（NOR）快閃記憶區塊。Please refer to FIG. 1 , which is a schematic diagram of a three-dimensional memory device according to an embodiment of the present invention. The three-dimensional memory device 100 includes a memory cell block 101, source line switches SLT1 to SLT16, bit line switches BLT1a to BLT16a, and bit line switches BLT1b to BLT16b. The memory cell block 101 can be divided into memory cell sub-blocks 110 and 120 . The memory cell sub-block 110 includes a plurality of memory cells MC1 arranged in a stack, and the memory cell sub-block 120 includes a plurality of memory cells MC2 arranged in a stack. In this embodiment, the memory cell block 101 may be a three-dimensional stacked AND flash memory block or a NOR flash memory block.
此外，記憶胞子區塊110可被區分為第一部份Pa1以及第二部分Pa2。相對應的，記憶胞子區塊120可被區分為第一部份Pb1以及第二部分Pb2。In addition, the memory cell sub-block 110 can be divided into a first part Pa1 and a second part Pa2. Correspondingly, the memory cell sub-block 120 can be divided into a first part Pb1 and a second part Pb2.
源極線開關SLT1~SLT16的多個第一端共同耦接至共同源極線CSL，源極線開關SLT1~SLT16的多個第二端則分別耦接至記憶胞子區塊110的多條源極線。並且，源極線開關SLT1~SLT16的多個第二端也分別耦接至記憶胞子區塊120的多條源極線。也就是說，記憶胞子區塊110以及120可共用源極線開關SLT1~SLT16。The plurality of first terminals of the source line switches SLT1 ~ SLT16 are jointly coupled to the common source line CSL, and the plurality of second terminals of the source line switches SLT1 ~ SLT16 are respectively coupled to the plurality of sources of the memory cell sub-block 110 polar line. In addition, the plurality of second terminals of the source line switches SLT1 to SLT16 are also coupled to the plurality of source lines of the memory cell sub-block 120 respectively. That is to say, the memory cell sub-blocks 110 and 120 can share the source line switches SLT1~SLT16.
此外，位元線開關BLT1a~BLT8a的多個第一端共同耦接至共同位元線GBL1，位元線開關BLT9a~BLT16a的多個第一端共同耦接至共同位元線GBL2。其中，位元線開關BLT1a~BLT8a對應記憶胞子區塊110的第一部份Pa1，位元線開關BLT1a~BLT8a的多個第二端分別耦接至記憶胞子區塊110的第一部份Pa1中的多條位元線。位元線開關BLT9a~BLT16a對應記憶胞子區塊110的第二部份Pa2，位元線開關BLT9a~BLT16a的多個第二端分別耦接至記憶胞子區塊110的第二部份Pa2中的多條位元線。In addition, a plurality of first terminals of the bit line switches BLT1a to BLT8a are jointly coupled to the common bit line GBL1, and a plurality of first terminals of the bit line switches BLT9a to BLT16a are jointly coupled to the common bit line GBL2. Among them, the bit line switches BLT1a~BLT8a correspond to the first part Pa1 of the memory cell sub-block 110, and the plurality of second terminals of the bit line switches BLT1a~BLT8a are respectively coupled to the first part Pa1 of the memory cell sub-block 110. multiple bit lines in . The bit line switches BLT9a~BLT16a correspond to the second part Pa2 of the memory cell sub-block 110. The plurality of second terminals of the bit line switches BLT9a~BLT16a are respectively coupled to the second part Pa2 of the memory cell sub-block 110. Multiple bit lines.
並且，位元線開關BLT1b~BLT8b的多個第一端共同耦接至共同位元線GBL1，位元線開關BLT9b~BLT16b的多個第一端共同耦接至共同位元線GBL2。其中，位元線開關BLT1b~BLT8b對應記憶胞子區塊120的第一部份Pb1，位元線開關BLT1b~BLT8b的多個第二端分別耦接至記憶胞子區塊120的第一部份Pb1中的多條位元線。位元線開關BLT9b~BLT16b對應記憶胞子區塊120的第二部份Pb2，位元線開關BLT9b~BLT16b的多個第二端分別耦接至記憶胞子區塊120的第二部份Pb2中的多條位元線。Furthermore, a plurality of first terminals of the bit line switches BLT1b to BLT8b are commonly coupled to the common bit line GBL1, and a plurality of first terminals of the bit line switches BLT9b to BLT16b are commonly coupled to the common bit line GBL2. Among them, the bit line switches BLT1b~BLT8b correspond to the first part Pb1 of the memory cell sub-block 120, and the plurality of second terminals of the bit line switches BLT1b~BLT8b are respectively coupled to the first part Pb1 of the memory cell sub-block 120. multiple bit lines in . The bit line switches BLT9b~BLT16b correspond to the second part Pb2 of the memory cell sub-block 120. The plurality of second terminals of the bit line switches BLT9b~BLT16b are respectively coupled to the second part Pb2 of the memory cell sub-block 120. Multiple bit lines.
在位置佈局上，記憶胞子區塊110的第一區塊Pa1與記憶胞子區塊120的第二區塊Pb2可相對稱於一參考中心，記憶胞子區塊110的第二區塊Pa2與記憶胞子區塊120的第一區塊Pb1可相對稱於此參考中心。In terms of location layout, the first block Pa1 of the memory cell sub-block 110 and the second block Pb2 of the memory cell sub-block 120 can be relatively symmetrical to a reference center, and the second block Pa2 of the memory cell sub-block 110 and the memory cell sub-block 120 can be relatively symmetrical to a reference center. The first block Pb1 of block 120 may be relative to this reference center.
在動作細節上，當進行讀取動作時，若選中記憶胞子區塊110的第一區塊Pa1中的一記憶胞為選中記憶胞以進行讀取時，選中記憶胞以及相對應的源極線開關及位元線開關可提供感測放大器的感測輸入端的一第一負載。同時，相對稱的記憶胞子區塊120的第二區塊Pb2中可提供一參考記憶胞。此參考記憶胞對應的源極線開關以及位元線開關則可提供感測放大器的參考輸入端的一第二負載。基於參考記憶胞與選中記憶胞分別對應的源極線開關以及位元線開關可具有相同的電路架構，因此，感測放大器的感測輸入端以及參考輸入端間的負載可以平衡，使所產生的感測結果的準確度可以提升。In terms of action details, when performing a reading operation, if a memory cell in the first block Pa1 of the memory cell sub-block 110 is selected for reading, the selected memory cell and the corresponding The source line switch and the bit line switch can provide a first load for the sense input terminal of the sense amplifier. At the same time, a reference memory cell can be provided in the second block Pb2 of the relatively symmetrical memory cell sub-block 120 . The corresponding source line switch and bit line switch of the reference memory cell can provide a second load for the reference input terminal of the sense amplifier. Since the source line switches and bit line switches corresponding to the reference memory cell and the selected memory cell respectively can have the same circuit architecture, the load between the sensing input terminal and the reference input terminal of the sense amplifier can be balanced, so that all The accuracy of the resulting sensing results can be improved.
當然，在讀取動作中，當選中記憶胞位在記憶胞子區塊110的第二區塊Pa2中時，參考記憶胞可以位在記憶胞子區塊120的第一區塊Pb1；若當選中記憶胞位在記憶胞子區塊120的第一區塊Pb1中時，參考記憶胞可以位在記憶胞子區塊110的第二區塊Pa2；若當選中記憶胞位在記憶胞子區塊120的第二區塊Pb2中時，參考記憶胞可以位在記憶胞子區塊110的第一區塊Pa1。Of course, during the reading operation, when the selected memory cell is located in the second block Pa2 of the memory cell sub-block 110, the reference memory cell can be located in the first block Pb1 of the memory cell sub-block 120; When the cell is located in the first block Pb1 of the memory cell sub-block 120, the reference memory cell can be located in the second block Pa2 of the memory cell sub-block 110; if the selected memory cell is located in the second block of the memory cell sub-block 120 When in block Pb2, the reference memory cell may be located in the first block Pa1 of the memory cell sub-block 110.
附帶一提的，在本實施例中，位元線開關BLT1a~BLT16a、BLT1b~BLT16b以及源極線開關SLT1~SLT16的數量並沒有固定的限制。圖1繪示的數量僅只是為了說明上的便利，並不用以限縮本發明的範疇。Incidentally, in this embodiment, there is no fixed limit on the number of bit line switches BLT1a to BLT16a, BLT1b to BLT16b and source line switches SLT1 to SLT16. The numbers shown in Figure 1 are only for convenience of explanation and are not intended to limit the scope of the present invention.
附帶一提的，在本發明實施例中，源極線開關SLT1~SL8可以分別與源極線開關SLT9~SL16共用相同的8個開關元件。Incidentally, in the embodiment of the present invention, the source line switches SLT1 to SL8 may share the same eight switching elements with the source line switches SLT9 to SL16 respectively.
請參照圖2A以及圖2B，圖2A以及圖2B分別繪示本發明實施例的三維記憶體裝置的讀取動作的不同實施方式的示意圖。承繼三維記憶體裝置100的硬體架構。在本實施方式中，三維記憶體裝置100更包括路徑選擇器130以及感測放大器SA。感測放大器SA具有感測輸入端SE以及參考輸入端RE。感測輸入端SE用以接收被感測的電氣信號，參考輸入端RE則用以接收做為感測標準的參考信號。路徑選擇器130耦接在感測放大器SA以及記憶胞子區塊110、120間。其中路徑選擇器130包括四個由電晶體構成的開關T1~T4，開關T1耦接在共同位元線GBL1以及感測放大器SA的參考輸入端RE間；開關T2耦接在共同位元線GBL1以及感測放大器SA的感測輸入端SE間；開關T3耦接在共同位元線GBL2以及感測放大器SA的感測輸入端間SE；開關T4則耦接在共同位元線GBL2以及感測放大器SA的參考輸入端RE間。Please refer to FIG. 2A and FIG. 2B. FIG. 2A and FIG. 2B are schematic diagrams of different implementations of the reading operation of the three-dimensional memory device according to the embodiment of the present invention. The hardware architecture of the three-dimensional memory device 100 is inherited. In this embodiment, the three-dimensional memory device 100 further includes a path selector 130 and a sense amplifier SA. The sense amplifier SA has a sense input terminal SE and a reference input terminal RE. The sensing input terminal SE is used to receive the sensed electrical signal, and the reference input terminal RE is used to receive the reference signal as the sensing standard. The path selector 130 is coupled between the sense amplifier SA and the memory cell sub-blocks 110 and 120 . The path selector 130 includes four switches T1 to T4 composed of transistors. The switch T1 is coupled between the common bit line GBL1 and the reference input terminal RE of the sense amplifier SA; the switch T2 is coupled between the common bit line GBL1 and the sensing input terminal SE of the sense amplifier SA; the switch T3 is coupled between the common bit line GBL2 and the sensing input terminal SE of the sense amplifier SA; the switch T4 is coupled between the common bit line GBL2 and the sensing input terminal SE. between the reference input RE of amplifier SA.
在本實施方式中，當記憶胞子區塊110中的一記憶胞（選中記憶胞SMC1）被選中以進行讀取動作時，位置與選中記憶胞SMC1相對稱，位於記憶胞子區塊120中的一記憶胞可做為參考記憶胞RMC2。在讀取動作中，對應選中記憶胞SMC1的源極線開關SLT1以及位元線開關BLT1a均被導通，對應參考記憶胞RMC2的源極線開關SLT9以及位元線開關BLT9b也均被導通。此外，選中記憶胞SMC1對應的字元線接收讀取電壓Vread，並使選中記憶胞SMC1根據所儲存的資料以提供一讀取信號。參考記憶胞RMC2的字元線則例如接收參考接地電壓（0伏特），並為被截止的狀態。In this embodiment, when a memory cell (selected memory cell SMC1 ) in the memory cell sub-block 110 is selected for reading, the position is symmetrical to the selected memory cell SMC1 and is located in the memory cell sub-block 120 One of the memory cells can be used as the reference memory cell RMC2. During the reading operation, the source line switch SLT1 and the bit line switch BLT1a corresponding to the selected memory cell SMC1 are both turned on, and the source line switch SLT9 and the bit line switch BLT9b corresponding to the reference memory cell RMC2 are also turned on. In addition, the word line corresponding to the selected memory cell SMC1 receives the read voltage Vread, and causes the selected memory cell SMC1 to provide a read signal according to the stored data. The word line of the reference memory cell RMC2 receives, for example, the reference ground voltage (0 volt) and is in a cut-off state.
在讀取動作中，開關T1、T3被斷開，且開關T2、T4被導通。共同位元線GBL1可透過開關T2以被耦接至感測放大器SA的感測端SE，共同位元線GBL2則可透過開關T4以被耦接至感測放大器SA的參考端RE。During the reading operation, the switches T1 and T3 are turned off, and the switches T2 and T4 are turned on. The common bit line GBL1 can be coupled to the sensing terminal SE of the sense amplifier SA through the switch T2, and the common bit line GBL2 can be coupled to the reference terminal RE of the sense amplifier SA through the switch T4.
附帶一提，在本實施方式中，位元線開關BLT1b以及BLT9a是被斷開的。同時，其餘的位元線開關BLT2a~BLT8a，BLT10a~BLT16a、BLT2b~BLT8b、BLT10b~BLT16b也均為被斷開的狀態。Incidentally, in this embodiment, the bit line switches BLT1b and BLT9a are turned off. At the same time, the remaining bit line switches BLT2a~BLT8a, BLT10a~BLT16a, BLT2b~BLT8b, BLT10b~BLT16b are also disconnected.
在此請參照圖2C繪示的本發明實施例的三維記憶體裝置的感測放大器，在讀取動作中，二輸入端的負載狀態的示意圖。在位元線開關BLT1a與BLT9b，源極線開關SLT1與SLT9為相同的電路元件的前提下，感測放大器SA的感測輸入端SE與參考輸入端RE間的負載差異，僅與選中記憶胞SMC1的資料儲存狀態相關。因此，感測放大器SA可根據感測輸入端SE與參考輸入端RE上的信號，來感測出正確的感測結果。Please refer to FIG. 2C , which is a schematic diagram of the load status of the two input terminals of the sense amplifier of the three-dimensional memory device according to the embodiment of the present invention during the reading operation. Under the premise that the bit line switches BLT1a and BLT9b and the source line switches SLT1 and SLT9 are the same circuit components, the load difference between the sensing input terminal SE of the sense amplifier SA and the reference input terminal RE is only the same as that of the selected memory. It is related to the data storage status of cell SMC1. Therefore, the sense amplifier SA can sense the correct sensing result according to the signals on the sensing input terminal SE and the reference input terminal RE.
請參照圖2B，在本實施方式中，記憶胞子區塊110的另一部分的記憶胞（選中記憶胞SMC2）被選中以進行讀取動作時，位置與選中記憶胞SMC2相對稱，位於記憶胞子區塊120中的記憶胞可做為參考記憶胞RMC3。在讀取動作中，對應選中記憶胞SMC2的源極線開關SLT9以及位元線開關BLT9a均被導通，對應參考記憶胞RMC3的源極線開關SLT1以及位元線開關BLT1b也均被導通。此外，選中記憶胞SMC2對應的字元線接收讀取電壓Vread，並使選中記憶胞SMC2根據所儲存的資料以提供一讀取信號。參考記憶胞RMC3的字元線則例如接收參考接地電壓（0伏特），並為被截止的狀態。Please refer to FIG. 2B . In this embodiment, when the memory cell (selected memory cell SMC2 ) in another part of the memory cell sub-block 110 is selected for reading, the position is symmetrical to the selected memory cell SMC2 , located at The memory cells in the memory cell sub-block 120 can be used as the reference memory cell RMC3. During the reading operation, the source line switch SLT9 and the bit line switch BLT9a corresponding to the selected memory cell SMC2 are both turned on, and the source line switch SLT1 and the bit line switch BLT1b corresponding to the reference memory cell RMC3 are also turned on. In addition, the word line corresponding to the selected memory cell SMC2 receives the read voltage Vread, and causes the selected memory cell SMC2 to provide a read signal according to the stored data. The word line of the reference memory cell RMC3 receives, for example, the reference ground voltage (0 volt) and is in a cut-off state.
在讀取動作中，開關T2、T4被斷開，且開關T1、T3被導通。共同位元線GBL1可透過開關T1以被耦接至感測放大器SA的參考端RE，共同位元線GBL2則可透過開關T3以被耦接至感測放大器SA的感測端SE。During the reading operation, the switches T2 and T4 are turned off, and the switches T1 and T3 are turned on. The common bit line GBL1 can be coupled to the reference terminal RE of the sense amplifier SA through the switch T1, and the common bit line GBL2 can be coupled to the sensing terminal SE of the sense amplifier SA through the switch T3.
附帶一提，在本實施方式中，位元線開關BLT9b以及BLT1a是被斷開的。同時，其餘的位元線開關BLT2a~BLT8a，BLT10a~BLT16a、BLT2b~BLT8b、BLT10b~BLT16b也均為被斷開的狀態。Incidentally, in this embodiment, the bit line switches BLT9b and BLT1a are turned off. At the same time, the remaining bit line switches BLT2a~BLT8a, BLT10a~BLT16a, BLT2b~BLT8b, BLT10b~BLT16b are also disconnected.
以下請參照圖3，圖3繪示本發明實施例的三維記憶體裝置的程式化動作的示意圖。承繼三維記憶體裝置100的硬體架構。三維記憶體裝置100另包括頁緩衝器141、142以及開關T5、T6。頁緩衝器141、142分別透過由電晶體構成的開關T5、T6以連接至共同位元線GBL1以及GBL2。Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of the programming operation of the three-dimensional memory device according to the embodiment of the present invention. The hardware architecture of the three-dimensional memory device 100 is inherited. The three-dimensional memory device 100 further includes page buffers 141 and 142 and switches T5 and T6. Page buffers 141 and 142 are respectively connected to common bit lines GBL1 and GBL2 through switches T5 and T6 composed of transistors.
在執行程式化動作時，路徑選擇器130中的開關T1~T4均被斷開，以使共同位元線GBL1以及GBL2與感測放大器SA相互電性隔離。開關T5、T6則被導通，以使頁緩衝器141、142所分別接收的資料PD1、PD2被分別傳送至共同位元線GBL1以及GBL2。附帶一提的，在三維記憶體裝置100執行讀取動作時，開關T5、T6可以被斷開。When executing the programmed action, the switches T1 to T4 in the path selector 130 are all turned off, so that the common bit lines GBL1 and GBL2 and the sense amplifier SA are electrically isolated from each other. The switches T5 and T6 are turned on, so that the data PD1 and PD2 received by the page buffers 141 and 142 are respectively transmitted to the common bit lines GBL1 and GBL2. Incidentally, when the three-dimensional memory device 100 performs a reading operation, the switches T5 and T6 may be turned off.
此外，若記憶胞子區塊110中的兩個部分的記憶胞（選中記憶胞SMC3、SMC4）被選中以執行程式化動作時，選中記憶胞SMC3對應的位元線開關BLT1a以及選中記憶胞SMC4對應的位元線開關BLT9a均被導通。此時源極線開關SLT1、SLT9被斷開，而對應的位元線開關BLT1b以及BLT9b也可以被導通。In addition, if two parts of memory cells (selected memory cells SMC3 and SMC4) in the memory cell sub-block 110 are selected to perform programmed actions, the bit line switch BLT1a corresponding to the selected memory cell SMC3 and the selected The bit line switches BLT9a corresponding to the memory cell SMC4 are all turned on. At this time, the source line switches SLT1 and SLT9 are turned off, and the corresponding bit line switches BLT1b and BLT9b can also be turned on.
在此同時，選中記憶胞SMC3、SMC4的字元線（為相同的字元線）可接收程式化電壓VPGM，並使選中記憶胞SMC3、SMC4根據共同位元線GBL1以及GBL2上的資料PD1、PD2以執行程式化動作。At the same time, the word lines of the selected memory cells SMC3 and SMC4 (which are the same word lines) can receive the programmed voltage VPGM, and make the selected memory cells SMC3 and SMC4 act according to the data on the common bit lines GBL1 and GBL2. PD1 and PD2 are used to perform programmed actions.
另外，為使未被選中的記憶胞不受到程式化動作的干擾，不是選中記憶胞SMC3、SMC4的其餘的記憶胞所耦接的字元線可接收參考接地電壓（例如0伏特）。In addition, in order to prevent the unselected memory cells from being disturbed by programmed actions, the word lines coupled to the remaining memory cells other than the selected memory cells SMC3 and SMC4 can receive a reference ground voltage (for example, 0 volts).
在本實施例中，頁緩衝器141、142的電路架構可以應用記憶體領域中，具通常知識者所熟知的頁緩衝器電路來實施，沒有一定的限制。In this embodiment, the circuit architecture of the page buffers 141 and 142 can be implemented using page buffer circuits that are well known to those of ordinary skill in the memory field, without certain limitations.
本實施方式中的程式化動作，可以一次的寫入多個選中記憶胞，是一種頁程式化的實施方式。The programming action in this embodiment can write multiple selected memory cells at one time, which is a page programming implementation.
以下請參照圖4，圖4繪示本發明實施例的三維記憶體裝置的抹除動作的示意圖。同樣承繼三維記憶體裝置100的硬體架構。在本實施方式中，抹除動作為區塊抹除動作。在執行抹除動作時，位元線開關BLT1a~BLT16a、BLT1b~BLT16b均被導通，源極線開關SLT1~SLT16也均被導通，並對所有記憶胞的位元線以及源極線提供4伏特~6伏特的電壓。以記憶胞子區塊110為選中以進行抹除的區塊（記憶胞子區塊120不被抹除）為範例記憶胞子區塊110的字元線可均接收抹除電壓（例如為-6至-8伏特），而記憶胞子區塊120的字元線可均接收抹除遮蔽電壓（例如為+4.5伏特）。Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of the erasing operation of the three-dimensional memory device according to the embodiment of the present invention. The hardware architecture of the three-dimensional memory device 100 is also inherited. In this embodiment, the erasing operation is a block erasing operation. When performing the erase operation, the bit line switches BLT1a~BLT16a, BLT1b~BLT16b are all turned on, the source line switches SLT1~SLT16 are also turned on, and provide 4 volts to the bit lines and source lines of all memory cells. ~6 volts of voltage. Taking the memory cell sub-block 110 as the block selected for erasing (the memory cell sub-block 120 is not erased) as an example, the word lines of the memory cell sub-block 110 can all receive an erase voltage (for example, -6 to -8 volts), and the word lines of the memory cell sub-block 120 may all receive the erase shielding voltage (eg, +4.5 volts).
附帶一提的，在本發明實施例中，源極線開關SLT1~SL8可以分別與源極線開關SLT9~SL16共用相同的開關元件。Incidentally, in the embodiment of the present invention, the source line switches SLT1 to SL8 may share the same switching element with the source line switches SLT9 to SL16 respectively.
在此請注意，根據圖1至圖4的實施例可以得知，本發明的三維記憶體裝置100中，位元線開關BLT1b~BLT8b與位元線開關BLT9a~BLT16a的導通及斷開狀態，在任何的操作模式下，都分別是相同的。位元線開關BLT1a~BLT8a與位元線開關BLT9b~BLT16b的導通及斷開狀態，在任何的操作模式下，也都分別是相同的。也就是說，位元線開關BLT1b~BLT8b與位元線開關BLT9a~BLT16a可以共用相同的八條驅動信號，位元線開關BLT1a~BLT8a與位元線開關BLT9b~BLT16b也可以共用另外的八條驅動信號。如此一來，本發明實施例的三維記憶體裝置100中，用以操控位元線開關BLT1a~BLT16b的驅動信號可以減半，有效減低線路的佈局面積。Please note here that according to the embodiments of FIG. 1 to FIG. 4, it can be known that in the three-dimensional memory device 100 of the present invention, the on and off states of the bit line switches BLT1b~BLT8b and the bit line switches BLT9a~BLT16a, In any operating mode, they are the same. The on and off states of the bit line switches BLT1a~BLT8a and the bit line switches BLT9b~BLT16b are also the same in any operating mode. In other words, the bit line switches BLT1b~BLT8b and the bit line switches BLT9a~BLT16a can share the same eight driving signals, and the bit line switches BLT1a~BLT8a and the bit line switches BLT9b~BLT16b can also share another eight driving signals. driving signal. As a result, in the three-dimensional memory device 100 according to the embodiment of the present invention, the driving signals used to control the bit line switches BLT1a~BLT16b can be reduced by half, effectively reducing the circuit layout area.
以下請參照圖5，圖5繪示本發明一實施例的三維記憶體裝置的立體架構圖。三維記憶體裝置500包括記憶胞子區塊510以及520。記憶胞子區塊510包括多個堆疊成階梯狀的字元線結構SCWL1，記憶胞子區塊520則包括多個堆疊成階梯狀的字元線結構SCWL2。在記憶胞子區塊510以及520中間，並具備用以佈局位元線開關的佈局區域511以及521。其中佈局區域511以及521依序設置在記憶胞子區塊510以及520之間。另外，在記憶胞子區塊520未鄰近於佈局區域511以及521的側邊上，則具有源極線開關的佈局區域530。佈局區域511以及521分別用以設置對應記憶胞子區塊510以及520的多個位元線開關，佈局區域530則用以設置記憶胞子區塊510以及520所共用的多個源極線開關。Please refer to FIG. 5 below. FIG. 5 is a three-dimensional structural diagram of a three-dimensional memory device according to an embodiment of the present invention. The three-dimensional memory device 500 includes memory cell sub-blocks 510 and 520 . The memory cell sub-block 510 includes a plurality of word line structures SCWL1 stacked in a ladder shape, and the memory cell sub-block 520 includes a plurality of word line structures SCWL2 stacked in a ladder shape. Between the memory cell sub-blocks 510 and 520, there are layout areas 511 and 521 for laying out bit line switches. The layout areas 511 and 521 are sequentially arranged between the memory cell sub-blocks 510 and 520. In addition, on the side of the memory cell sub-block 520 that is not adjacent to the layout areas 511 and 521, there is a layout area 530 of the source line switch. The layout areas 511 and 521 are used to set a plurality of bit line switches corresponding to the memory cell sub-blocks 510 and 520 respectively, and the layout area 530 is used to set a plurality of source line switches shared by the memory cell sub-blocks 510 and 520 .
以下請參照圖6，圖6繪示本發明實施例的三維記憶體裝置的字元線開關的實施方式的示意圖。在本實施例中，以每一記憶胞子區塊具有16位元線為範例。三維記憶體裝置具有對應第一記憶胞子區塊的多個位元線開關BLT1a~BLT16a以及對應第一記憶胞子區塊的多個位元線開關BLT1b~BLT16b。位元線開關BLT1a~BLT16a以陣列方式進行排列，並分別耦接至16個位元線驅動器601a~616a。位元線開關BLT1b~BLT16b以陣列方式進行排列，並分別耦接至16個位元線驅動器601b~616b。Please refer to FIG. 6 below. FIG. 6 is a schematic diagram of a word line switch of a three-dimensional memory device according to an embodiment of the present invention. In this embodiment, each memory cell sub-block has 16 bit lines as an example. The three-dimensional memory device has a plurality of bit line switches BLT1a to BLT16a corresponding to the first memory cell sub-block and a plurality of bit line switches BLT1b to BLT16b corresponding to the first memory cell sub-block. The bit line switches BLT1a~BLT16a are arranged in an array and coupled to 16 bit line drivers 601a~616a respectively. The bit line switches BLT1b~BLT16b are arranged in an array and coupled to 16 bit line drivers 601b~616b respectively.
其中，位元線驅動器601a~616a以及601b~616b一對一的分別與位元線開關BLT1a~BLT16a、BLT1b~BLT16b相對應，並透過所產生的驅動信號以控制位元線開關BLT1a~BLT16a、BLT1b~BLT16b的導通及斷開狀態。Among them, the bit line drivers 601a to 616a and 601b to 616b correspond to the bit line switches BLT1a to BLT16a and BLT1b to BLT16b respectively, and control the bit line switches BLT1a to BLT16a and BLT16a through the generated driving signals. The on and off status of BLT1b~BLT16b.
以下請參照圖7，圖7繪示本發明實施例的三維記憶體裝置的字元線開關的另一實施方式的示意圖。根據前述的實施方式可以得知，本發明的三維記憶體裝置，其位元線開關的導通以及斷開狀態具有對應性。也就是說，本發明實施例的三維記憶體裝置中，第一子記憶胞的第一部分的位元線開關的導通與斷開狀態，與第二子記憶胞的第二部分的位元線開關的導通與斷開狀態相同。第一子記憶胞的第二部分的位元線開關的導通與斷開狀態，與第二子記憶胞的第一部分的位元線開關的導通與斷開狀態相同。因此，透過調整位元線開關BLT1a~BLT16a、BLT1b~BLT16b的佈局位置，使對應相對稱的位元線開關的驅動線DL對稱於參考軸RAX以進行配置。Please refer to FIG. 7 below. FIG. 7 is a schematic diagram of another implementation of a word line switch of a three-dimensional memory device according to an embodiment of the present invention. According to the foregoing embodiments, it can be known that the on and off states of the bit line switches of the three-dimensional memory device of the present invention are corresponding. That is to say, in the three-dimensional memory device according to the embodiment of the present invention, the on and off states of the bit line switches of the first part of the first sub-memory cell are different from the bit line switches of the second part of the second sub-memory cell. The on and off states are the same. The on and off states of the bit line switches in the second part of the first sub-memory cell are the same as the on and off states of the bit line switches in the first part of the second sub-memory cell. Therefore, by adjusting the layout positions of the bit line switches BLT1a~BLT16a, BLT1b~BLT16b, the drive lines DL corresponding to the symmetrical bit line switches are arranged symmetrically with the reference axis RAX.
另外，本發明實施例的三維記憶體裝置中並具有多條橋接線CW。橋接線CW用以使二對稱於參考軸RAX的驅動線DL相互連接，並用以傳送相同的驅動信號。In addition, the three-dimensional memory device according to the embodiment of the present invention also has a plurality of bridge lines CW. The bridge line CW is used to connect two driving lines DL that are symmetrical about the reference axis RAX to each other and to transmit the same driving signal.
在這樣的配置下，位元線驅動器701~716的數量可以減半，有效節省三維記憶體裝置的電路佈局所需要的面積，以及功率消耗。Under such a configuration, the number of bit line drivers 701 to 716 can be reduced by half, effectively saving the area required for the circuit layout of the three-dimensional memory device and the power consumption.
綜上所述，本發明的三維記憶體裝置透過使記憶胞區塊被區分為二記憶胞子區塊。並且，在讀取動作被執行時，使相對稱的選中記憶胞以及參考記憶胞被耦接至感測放大器，並藉此使感測放大器的參考輸入端以及感測輸入端上的負載可以均衡，可提升感測結果的準確性。To sum up, the three-dimensional memory device of the present invention divides the memory cell block into two memory cell sub-blocks. Moreover, when the read operation is performed, the relatively symmetrical selected memory cells and the reference memory cells are coupled to the sense amplifier, thereby allowing the load on the reference input end of the sense amplifier and the sensing input end to Balanced, can improve the accuracy of sensing results.
100、500:三維記憶體裝置 101:記憶胞區塊 110、120、510、520:記憶胞子區塊 130:路徑選擇器 141、142:頁緩衝器 511、521、530:佈局區域 601a~616a、601b~616b、701~716:位元線驅動器 BLT1a~BLT16a、BLT1b~BLT16b:位元線開關 CSL:共同源極線 CW:橋接線 DL:驅動線 GBL1、GBL2:共同位元線 MC1、MC2:記憶胞 Pa1、Pb1:第一部份 Pa2、Pb2:第二部分 PD1、PD2:資料 RAX:參考軸 RE:參考輸入端 RMC2、RMC3:參考記憶胞 SA:感測放大器 SE:感測輸入端 SLT1~SLT16:源極線開關 SMC1~SMC4:選中記憶胞 T1~T6:開關 VPGM:程式化電壓 Vread:讀取電壓 SCWL1、SCWL2:字元線結構100, 500: Three-dimensional memory device 101: Memory cell block 110, 120, 510, 520: memory cell sub-blocks 130:Path selector 141, 142: Page buffer 511, 521, 530: layout area 601a~616a, 601b~616b, 701~716: bit line driver BLT1a~BLT16a, BLT1b~BLT16b: bit line switches CSL: common source line CW: bridge wire DL: drive line GBL1, GBL2: common bit line MC1, MC2: memory cells Pa1, Pb1: the first part Pa2, Pb2: Part 2 PD1, PD2: information RAX: reference axis RE: reference input terminal RMC2, RMC3: reference memory cells SA: sense amplifier SE: sensing input terminal SLT1~SLT16: source line switch SMC1~SMC4: Select memory cells T1~T6: switch VPGM: programmed voltage Vread: read voltage SCWL1, SCWL2: word line structure
圖1繪示本發明一實施例的三維記憶體裝置的示意圖。 圖2A以及圖2B分別繪示本發明實施例的三維記憶體裝置的讀取動作的不同實施方式的示意圖。 圖2C繪示本發明實施例的三維記憶體裝置的感測放大器，在讀取動作中，二輸入端的負載狀態的示意圖。 圖3繪示本發明實施例的三維記憶體裝置的程式化動作的示意圖。 圖4繪示本發明實施例的三維記憶體裝置的抹除動作的示意圖。 圖5繪示本發明一實施例的三維記憶體裝置的立體架構圖。 圖6繪示本發明實施例的三維記憶體裝置的字元線開關的實施方式的示意圖。 圖7繪示本發明實施例的三維記憶體裝置的字元線開關的另一實施方式的示意圖。FIG. 1 is a schematic diagram of a three-dimensional memory device according to an embodiment of the present invention. 2A and 2B are schematic diagrams of different implementations of the reading operation of the three-dimensional memory device according to the embodiment of the present invention. 2C is a schematic diagram illustrating the load status of the two input terminals of the sense amplifier of the three-dimensional memory device during the reading operation according to the embodiment of the present invention. FIG. 3 is a schematic diagram of the programming operation of the three-dimensional memory device according to the embodiment of the present invention. FIG. 4 is a schematic diagram of the erasing operation of the three-dimensional memory device according to the embodiment of the present invention. FIG. 5 is a three-dimensional structural diagram of a three-dimensional memory device according to an embodiment of the present invention. FIG. 6 is a schematic diagram of an implementation of a word line switch of a three-dimensional memory device according to an embodiment of the present invention. FIG. 7 is a schematic diagram of another embodiment of a word line switch of a three-dimensional memory device according to an embodiment of the present invention.
100:三維記憶體裝置100:Three-dimensional memory device
101:記憶胞區塊101: Memory cell block
110、120:記憶胞子區塊110, 120: Memory cell sub-block
BLT1a~BLT16a、BLT1b~BLT16b:位元線開關BLT1a~BLT16a, BLT1b~BLT16b: bit line switches
CSL:共同源極線CSL: common source line
GBL1、GBL2:共同位元線GBL1, GBL2: common bit line
MC1、MC2:記憶胞MC1, MC2: memory cells
Pa1、Pb1:第一部份Pa1, Pb1: the first part
Pa2、Pb2:第二部分Pa2, Pb2: Part 2
SLT1~SLT16:源極線開關SLT1~SLT16: source line switch
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| TW111119044ATWI822051B (en) | 2022-05-23 | 2022-05-23 | Three dimension memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201214434A (en)* | 2010-07-29 | 2012-04-01 | Sony Corp | Variable-resistance memory device |
| TWI497496B (en)* | 2011-01-19 | 2015-08-21 | Macronix Int Co Ltd | Architecture for 3d memory array |
| TWI581370B (en)* | 2012-08-30 | 2017-05-01 | 美光科技公司 | Memory array with power-efficient read architecture |
| TWI603256B (en)* | 2014-12-27 | 2017-10-21 | 英特爾公司 | Tier mode for access operations to 3d memory |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201214434A (en)* | 2010-07-29 | 2012-04-01 | Sony Corp | Variable-resistance memory device |
| TWI497496B (en)* | 2011-01-19 | 2015-08-21 | Macronix Int Co Ltd | Architecture for 3d memory array |
| TWI581370B (en)* | 2012-08-30 | 2017-05-01 | 美光科技公司 | Memory array with power-efficient read architecture |
| TWI603256B (en)* | 2014-12-27 | 2017-10-21 | 英特爾公司 | Tier mode for access operations to 3d memory |
| Publication number | Publication date |
|---|---|
| TW202347338A (en) | 2023-12-01 |
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