TWI788869B - High electron mobility transistor and composite substrate thereof - Google Patents

Abstract

A composite substrate of a high electron mobility transistor includes a substrate, a stress-relaxed silicon germanium (SiGe) layer disposed on the substrate, and a strain silicon layer disposed on the stress-relaxed SiGe layer. In addition, the high electron mobility transistor includes the composite substrate, a nucleation layer disposed on the strain silicon layer, a buffer layer disposed on the nucleation layer, a high resistance layer disposed on the buffer layer, having a resistance higher than the resistance of the buffer layer, a channel layer disposed on the high resistance layer, a barrier layer disposed on the channel layer, a cap layer disposed on the barrier layer, a gate electrode disposed on the cap layer, and a source electrode and a drain electrode disposed on two sides of the gate electrode respectiyely and on the channel layer.

Description

Translated fromChinese

高電子遷移率電晶體及其複合基板High Electron Mobility Transistor and Its Composite Substrate

本揭露係關於一種供磊晶成長的複合基板，特別是關於一種高電子遷移率電晶體的複合基板以及在其上形成的高電子遷移率電晶體。The present disclosure relates to a composite substrate for epitaxial growth, and in particular to a composite substrate for high electron mobility transistors and high electron mobility transistors formed thereon.

氮化鎵材料因為具有寬能隙、高臨界電場、高導熱率、高飽和電子速度、高頻傳輸能力以及元件體積小等特性，使得氮化鎵在高功率及高速電晶體的應用上被視為是相當理想的材料，尤其是在高電子遷移率電晶體(high electron mobility transistor,HEMT)等高頻元件或是發光二極體(LED)元件的應用上相當廣泛。Gallium nitride material is regarded as a high-power and high-speed transistor application because of its wide energy gap, high critical electric field, high thermal conductivity, high saturation electron velocity, high-frequency transmission capability, and small component size. As an ideal material, it is widely used in high-frequency components such as high electron mobility transistor (HEMT) or light-emitting diode (LED) components.

矽基板在價格成本上有其競爭優勢，因此將氮化鎵等III-V族半導體化合物成長在矽基板上的電路設計方案正在蓬勃地研究與發展。由於氮化鎵與矽基板在晶格常數與熱膨脹係數等性質差異過大，因此通常會在氮化鎵和矽基板之間設置緩衝層，來幫助氮化鎵成長在矽基板上，然而，緩衝層的使用並無法完全滿足高電子遷移率電晶體對於氮化鎵等III-V族半導體化合物的薄膜品質要求。Silicon substrates have competitive advantages in terms of price and cost. Therefore, the circuit design scheme of growing III-V semiconductor compounds such as gallium nitride on silicon substrates is being vigorously researched and developed. Due to the large difference in properties such as lattice constant and thermal expansion coefficient between gallium nitride and silicon substrate, a buffer layer is usually set between gallium nitride and silicon substrate to help gallium nitride grow on the silicon substrate. However, the buffer layer The use of high electron mobility transistors cannot fully meet the film quality requirements of III-V semiconductor compounds such as gallium nitride.

有鑑於此，有必要提供一種高電子遷移率電晶體的複合基板，以解決習知技術中存在的缺失。In view of this, it is necessary to provide a composite substrate of high electron mobility transistors to solve the deficiencies in the prior art.

根據本揭露一實施例，提供一種高電子遷移率電晶體的複合基板，包括基底、設置於基底上的應力調控矽鍺層、以及設置於應力調控矽鍺層上的應力傳遞矽層。According to an embodiment of the present disclosure, a composite substrate of a high electron mobility transistor is provided, including a substrate, a stress-regulating silicon-germanium layer disposed on the substrate, and a stress-transferring silicon layer disposed on the stress-modulating silicon-germanium layer.

根據本揭露一實施例，提供一種高電子遷移率電晶體，包括基底、設置於基底上的應力調控矽鍺層、設置於應力調控矽鍺層上的應力傳遞矽層、設置於應力傳遞矽層上的成核層、設置於成核層上的緩衝層、設置於緩衝層上的高電阻層，其具有的電阻率高於緩衝層的電阻率、設置於高電阻層上的通道層、設置於通道層上的電子提供層、設置於電子提供層上的覆蓋層、設置於覆蓋層上的閘極電極、以及分別設置於閘極電極的兩側，且位於通道層上的源極電極和汲極電極。According to an embodiment of the present disclosure, a high electron mobility transistor is provided, including a substrate, a stress-regulating silicon-germanium layer disposed on the substrate, a stress-transferring silicon layer disposed on the stress-regulating silicon-germanium layer, and a stress-transferring silicon layer disposed on the stress-modulating silicon-germanium layer. The nucleation layer on the nucleation layer, the buffer layer arranged on the nucleation layer, the high resistance layer arranged on the buffer layer, which has a resistivity higher than the resistivity of the buffer layer, the channel layer arranged on the high resistance layer, the An electron supply layer on the channel layer, a cover layer provided on the electron supply layer, a gate electrode provided on the cover layer, and a source electrode and a source electrode respectively provided on both sides of the gate electrode and located on the channel layer Drain electrode.

100:複合基板100: composite substrate

102:核心層102: core layer

104:介電層104: Dielectric layer

106:元件晶圓106: Component wafer

108:半導體層108: Semiconductor layer

110:基底110: base

112:第一摻雜漸變矽鍺層112: the first doped graded silicon germanium layer

113:第一超晶格結構113: The first superlattice structure

114:第二摻雜漸變矽鍺層114: the second doped graded silicon germanium layer

115:第二超晶格結構115: Second superlattice structure

120:應力調控矽鍺層120: Stress control silicon germanium layer

130:應力傳遞矽層130: Stress transfer silicon layer

140:應力漸變層140: Stress gradient layer

200:高電子遷移率電晶體200: High Electron Mobility Transistor

202:步驟202: Step

204:步驟204: step

206:步驟206: Step

210:成核層210: nucleation layer

220:緩衝層220: buffer layer

230:高電阻層230: high resistance layer

240:通道層240: channel layer

250:電子提供層250: electron providing layer

260:覆蓋層260: Overlay

270:閘極電極270: gate electrode

280:源極電極280: source electrode

290:汲極電極290: Drain electrode

2DEG:二維電子氣2DEG: two-dimensional electron gas

為讓本揭露的上述與其他目的、特徵及實施例能更明顯易懂，所附圖式之說明如下，此外，為了清楚起見，圖式中的各特徵可能未必按照實際的比例繪製，因此某些圖式中的部分特徵的尺寸可能被刻意放大或縮小。In order to make the above and other objects, features and embodiments of the present disclosure more comprehensible, the attached drawings are described as follows. In addition, for the sake of clarity, each feature in the drawings may not necessarily be drawn according to the actual scale, so The dimensions of some features in some drawings may be intentionally enlarged or reduced.

第1圖是根據本揭露一實施例所繪示的複合基板的剖面示意圖。FIG. 1 is a schematic cross-sectional view of a composite substrate according to an embodiment of the present disclosure.

第2圖是根據本揭露一實施例所繪示的複合基板之基底的製造過程之剖面示意圖。FIG. 2 is a schematic cross-sectional view of the manufacturing process of the base of the composite substrate according to an embodiment of the present disclosure.

第3圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。FIG. 3 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure.

第4圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。FIG. 4 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure.

第5圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。FIG. 5 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure.

第6圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。FIG. 6 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure.

第7圖是根據本揭露一實施例所繪示的高電子遷移率電晶體的剖面示意圖。FIG. 7 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure.

為了使本揭示內容的敘述更加詳盡與完備，下文針對了本揭露的實施態樣與具體實施例提出了說明性的描述；但這並非實施或運用本發明具體實施例的唯一形式。實施方式中涵蓋了多個具體實施例的特徵以及用以建構與操作這些具體實施例的方法步驟與其順序。然而，亦可利用其他具體實施例來達成相同或均等的功能與步驟順序。In order to make the description of the present disclosure more detailed and complete, the following provides illustrative descriptions of the implementations and specific embodiments of the present disclosure; but this is not the only way to implement or use the specific embodiments of the present invention. The description covers features of various embodiments as well as method steps and their sequences for constructing and operating those embodiments. However, other embodiments can also be used to achieve the same or equivalent functions and step sequences.

以下描述的數值範圍與參數皆是約略的數值，在此處，「約」通常係指實際數值在一特定數值或範圍的正負10%、5%、1%或0.5%之內。當可理解此處所用的所有範圍、數量、數值、比例與百分比均經過「約」的修飾。因此，除非另有相反的說明，本說明書與附隨申請專利範圍所揭示的數值參數皆為約略的數值，且可視需求而更動。The numerical ranges and parameters described below are approximate numerical values. Here, "about" usually means that the actual numerical value is within plus or minus 10%, 5%, 1% or 0.5% of a specific numerical value or range. It should be understood that all ranges, amounts, values, ratios and percentages used herein are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the appended patent claims are approximate values and may be changed as required.

第1圖是根據本揭露一實施例所繪示的複合基板的剖面示意圖。如第1圖所示，複合基板100包含基底110，基底110可以是絕緣層上覆矽(silicon-on-insulator，SOI)基底、單晶半導體基底、多晶半導體基底、鑽石基底或藍寶石基底，其中單晶半導體基底或多晶半導體基底的材料可以是矽、氮化鋁、碳化矽、氧化鎵或氮化硼。基底110之矽材料可以是無摻雜的Si<111>、Si<110>或Si<100>，或是矽材料可摻雜例如鍺(Ge)、砷(As)、氧(O)原子或前述之組合，摻雜濃度例如為1x10¹³至1x10²⁰atom/cm^-3。此外，複合基板100還包含應力調控矽鍺層120設置於基底110上，以及應力傳遞矽層130設置於應力調控矽鍺層120上。根據本揭露一些實施例，應力調控矽鍺層120的組成例如是Si_1-x3Ge_x3，其中0<x3<1，且應力調控矽鍺層120中可摻雜例如Ge、As、O原子或前述之組合，摻雜濃度例如為1x10²⁰atom/cm^-3，應力調控矽鍺層120的厚度可以是0.1微米(μm)至10μm，應力傳遞矽層130的厚度可以是0.1μm至10μm，可以使用有機金屬化學氣相沉積法(metal-organic chemical vapor deposition,MOCVD)在同一製程腔室內形成應力調控矽鍺層120和應力傳遞矽層130。其中，為了順利在基底110的表面上磊晶成長應力調控矽鍺層120，可以在基底110和應力調控矽鍺層120之間額外設置具有特定晶面的半導體層，例如矽(111)。FIG. 1 is a schematic cross-sectional view of a composite substrate according to an embodiment of the present disclosure. As shown in FIG. 1, thecomposite substrate 100 includes asubstrate 110, which may be a silicon-on-insulator (SOI) substrate, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a diamond substrate or a sapphire substrate, The material of the single crystal semiconductor substrate or the polycrystalline semiconductor substrate may be silicon, aluminum nitride, silicon carbide, gallium oxide or boron nitride. The silicon material of thesubstrate 110 can be undoped Si<111>, Si<110> or Si<100>, or the silicon material can be doped such as germanium (Ge), arsenic (As), oxygen (O) atoms or For the aforementioned combination, the doping concentration is, for example, 1×10¹³ to 1×10²⁰ atom/cm⁻³ . In addition, thecomposite substrate 100 further includes a stress-regulatingSiGe layer 120 disposed on thesubstrate 110 , and a stress-transmittingSi layer 130 disposed on the stress-modulatingSiGe layer 120 . According to some embodiments of the present disclosure, the composition of the stress-regulating silicon-germanium layer 120 is, for example, Si_1-x3 Ge_x3 , where 0<x3<1, and the stress-regulating silicon-germanium layer 120 can be doped with Ge, As, O atoms or For the aforementioned combination, the doping concentration is, for example, 1×10²⁰ atom/cm⁻³ , the thickness of the stress-regulatingsilicon germanium layer 120 can be 0.1 micrometer (μm) to 10 μm, and the thickness of the stresstransfer silicon layer 130 can be 0.1 μm to 10 μm. The stress-regulatingsilicon germanium layer 120 and the stress-transferringsilicon layer 130 are formed in the same process chamber by metal-organic chemical vapor deposition (MOCVD). Wherein, in order to successfully epitaxially grow the stress-regulatingsilicon germanium layer 120 on the surface of thesubstrate 110 , an additional semiconductor layer with a specific crystal plane, such as silicon (111 ), may be additionally disposed between thesubstrate 110 and the stress-regulatingsilicon germanium layer 120 .

第2圖是根據本揭露一實施例所繪示的複合基板之基底110的製造過程之剖面示意圖。如第2(a)圖所示，首先提供核心層102，例如支撐晶圓(handle wafer)，核心層102可以是矽、碳化矽(SiC)、藍寶石或其他硬度較大的基板，核心層102的厚度例如是300μm至1500μm。接著，經由步驟202，如第2(b)圖所示，在核心層102的表面形成介電層104，以作為後續晶圓鍵合的鍵合層(bonding layer)，及/或用以增強基底整體的抗彎曲性或楊氏係數。其中，介電層104可以是氧化矽(SiO₂)、氧化鋁(Al₂O₃)、氮化矽(SiN)或其他絕緣氧化物，介電層104的厚度可以是0.05μm至5μm，可以利用熱氧化或沉積的方式形成介電層104，並且介電層104可以包裹整個核心層102的正面、背面及側面。之後，經由步驟204，如第2(c)圖所示，提供元件晶圓106，將元件晶圓106鍵合(bonding)至介電層104上，並進行熱處理製程(annealing)。然後，經由步驟206，如第2(d)圖所示，將元件晶圓106減薄，繼以研磨減薄後的表面，得到半導體層108，並完成基底110的製造，其中，可以利用研磨(grinding)及化學機械研磨(chemical-mechanical planarization,CMP)方式進行步驟206，或是利用植入氫氣並膨脹產生微孔隙的分離方式(smart cut)以進行步驟206。同時參考第1圖和第2(d)圖，基底110的半導體層108設置於介電層104與應力調控矽鍺層120之間，半導體層108的厚度可以是0.1μm至10μm。根據本揭露之實施例，核心層102可以增加複合基板100之基底110的硬度，使得複合基板100抗翹曲(bending)效果得以提昇。此外，還可以利用介電層104的厚度調整來降低後續在複合基板100上磊晶成長的氮化鎵層之應力影響，改善基底110的彎曲(bowing)程度。FIG. 2 is a schematic cross-sectional view of the manufacturing process of thebase 110 of the composite substrate according to an embodiment of the present disclosure. As shown in FIG. 2(a), acore layer 102, such as a handle wafer, is provided first. Thecore layer 102 can be silicon, silicon carbide (SiC), sapphire or other hard substrates. Thecore layer 102 The thickness is, for example, 300 μm to 1500 μm. Next, throughstep 202, as shown in FIG. 2(b), adielectric layer 104 is formed on the surface of thecore layer 102 to serve as a bonding layer for subsequent wafer bonding, and/or to strengthen The bending resistance or Young's Modulus of the substrate as a whole. Wherein, thedielectric layer 104 can be silicon oxide (SiO₂ ), aluminum oxide (Al₂ O₃ ), silicon nitride (SiN) or other insulating oxides, and the thickness of thedielectric layer 104 can be 0.05 μm to 5 μm, which can be Thedielectric layer 104 is formed by thermal oxidation or deposition, and thedielectric layer 104 can wrap the entire front, back and sides of thecore layer 102 . Afterwards, throughstep 204 , as shown in FIG. 2( c ), thedevice wafer 106 is provided, thedevice wafer 106 is bonded to thedielectric layer 104 , and annealing is performed. Then, throughstep 206, as shown in FIG. 2(d), theelement wafer 106 is thinned, and then the thinned surface is ground to obtain thesemiconductor layer 108, and the manufacture of thesubstrate 110 is completed, wherein grinding can be used to Step 206 is carried out by means of grinding and chemical-mechanical planarization (CMP), or step 206 is carried out by a separation method (smart cut) by implanting hydrogen gas and expanding to generate micropores. Referring to FIG. 1 and FIG. 2(d) simultaneously, thesemiconductor layer 108 of thesubstrate 110 is disposed between thedielectric layer 104 and the stress-regulatingsilicon germanium layer 120, and the thickness of thesemiconductor layer 108 may be 0.1 μm to 10 μm. According to the embodiment of the present disclosure, thecore layer 102 can increase the hardness of thebase 110 of thecomposite substrate 100 , so that the effect of anti-warping of thecomposite substrate 100 can be improved. In addition, the adjustment of the thickness of thedielectric layer 104 can also be used to reduce the influence of the stress of the GaN layer epitaxially grown on thecomposite substrate 100 and improve the degree of bowing of thesubstrate 110 .

第3圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。第3圖與第2圖的差異在於第3圖的複合基板100之基底110與應力調控矽鍺層120之間額外設置有應力漸變層140，並且應力漸變層140的底部區域的鍺莫爾分率高於頂部區域的鍺莫爾分率。根據一實施例，如第3圖所示，應力漸變層140可包含位於底部區域的第一摻雜漸變矽鍺層112及位於頂部區域的第二摻雜漸變矽鍺層114。根據本揭露一些實施例，第一摻雜漸變矽鍺層112的組成例如是Si_1-x1Ge_x1、第二摻雜漸變矽鍺層114的組成例如是Si_1-x2Ge_x2，其中0<x3<x2<x1<1，且x3為應力調控矽鍺層120的Si_1-x3Gex₃中的鍺莫爾分率。第一摻雜漸變矽鍺層112和第二摻雜漸變矽鍺層114中可摻雜例如Ge、As、O原子或前述之組合，摻雜濃度例如為1x10²⁰atom/cm^-3，第一摻雜漸變矽鍺層112和第二摻雜漸變矽鍺層114的厚度可以各自是0.1μm至20μm。由於第一摻雜漸變矽鍺層112的晶格常數會大於第二摻雜漸變矽鍺層114的晶格常數，因此可以在不影響應力傳遞矽層130和基底110之間的附著性的情況下，進一步提昇施加至應力傳遞矽層130和上方其他半導體層(圖未示)的張應力。FIG. 3 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure. The difference between FIG. 3 and FIG. 2 is that astress gradient layer 140 is additionally provided between thesubstrate 110 and the stress-regulatingsilicon germanium layer 120 of thecomposite substrate 100 in FIG. The rate is higher than the germanium mole fraction in the top region. According to an embodiment, as shown in FIG. 3 , the stress gradedlayer 140 may include a first doped gradedSiGe layer 112 at the bottom region and a second doped gradedSiGe layer 114 at the top region. According to some embodiments of the present disclosure, the composition of the first doped gradedsilicon germanium layer 112 is, for example, Si_1-x1 Ge_x1 , and the composition of the second doped gradedsilicon germanium layer 114 is, for example, Si_1-x2 Ge_x2 , where 0<x3<x2<x1<1, and x3 is the germanium mole fraction in the Si_1-x3 Gex₃ of the stress-regulating silicon-germanium layer 120 . The first doped gradedsilicon germanium layer 112 and the second doped gradedsilicon germanium layer 114 may be doped with Ge, As, O atoms or a combination thereof, the doping concentration is, for example, 1×10²⁰ atom/cm⁻³ , the first The thicknesses of the doped gradedSiGe layer 112 and the second doped gradedSiGe layer 114 may be 0.1 μm to 20 μm respectively. Since the lattice constant of the first doped gradedSiGe layer 112 is greater than the lattice constant of the second doped gradedSiGe layer 114 , it is possible to avoid affecting the adhesion between the stresstransfer Si layer 130 and thesubstrate 110 . Next, the tensile stress applied to the stresstransfer silicon layer 130 and other upper semiconductor layers (not shown) is further increased.

第4圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。第4圖與第3圖的差異在於第4圖的複合基板100之第一摻雜漸變矽鍺層112與第二摻雜漸變矽鍺層114之間額外設置有第一超晶格結構113，此實施例之應力漸變層140包含第一摻雜漸變矽鍺層112、第一超晶格結構113及第二摻雜漸變矽鍺層114由下至上依序設置於基底110與應力調控矽鍺層120之間。第一超晶格結構113包含複數對成對堆疊的矽鍺層，每一對矽鍺層的組成與第一摻雜漸變矽鍺層112和第二摻雜漸變矽鍺層114的組成相同，例如是Si_1-x1Ge_x1和Si_1-x2Ge_x2，其中x1是第一摻雜漸變矽鍺層112的鍺莫爾分率，x2是第二摻雜漸變矽鍺層114的鍺莫爾分率，每一對矽鍺層的厚度小於第一摻雜漸變矽鍺層112和第二摻雜漸變矽鍺層114的厚度，例如可以是0.5nm至15nm，並且第一超晶格結構113可包含20對矽鍺層，第一超晶格結構113中可摻雜例如Ge、As、O原子或前述之組合，摻雜濃度例如為1x10²⁰atom/cm^-3。FIG. 4 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure. The difference between FIG. 4 and FIG. 3 is that afirst superlattice structure 113 is additionally provided between the first doped gradedsilicon germanium layer 112 and the second doped gradedsilicon germanium layer 114 of thecomposite substrate 100 in FIG. 4 , The stress gradedlayer 140 of this embodiment includes a first doped gradedsilicon germanium layer 112, afirst superlattice structure 113, and a second doped gradedsilicon germanium layer 114, which are sequentially arranged on thesubstrate 110 and the stress control silicon germanium layer from bottom to top. between layers 120 . Thefirst superlattice structure 113 includes a plurality of pairs of silicon germanium layers stacked in pairs, and the composition of each pair of silicon germanium layers is the same as that of the first doped gradedsilicon germanium layer 112 and the second doped gradedsilicon germanium layer 114, For example, Si_1-x1 Ge_x1 and Si_1-x2 Ge_x2 , where x1 is the germanium mole fraction of the first doped gradedsilicon germanium layer 112, and x2 is the germanium mole fraction of the second doped gradedsilicon germanium layer 114 The thickness of each pair of silicon germanium layers is less than the thickness of the first doped gradedsilicon germanium layer 112 and the second doped gradedsilicon germanium layer 114, for example, it can be 0.5nm to 15nm, and thefirst superlattice structure 113 It may include 20 pairs of silicon germanium layers, and thefirst superlattice structure 113 may be doped with Ge, As, O atoms or a combination thereof, and the doping concentration is, for example, 1×10²⁰ atom/cm⁻³ .

第5圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。第5圖與第3圖的差異在於第5圖的複合基板100之第二摻雜漸變矽鍺層114與應力調控矽鍺層120之間額外設置有第二超晶格結構115，此實施例之應力漸變層140包含第一摻雜漸變矽鍺層112、第二摻雜漸變矽鍺層114及第二超晶格結構115由下至上依序設置於基底110與應力調控矽鍺層120之間。第二超晶格結構115包含複數對成對堆疊的矽鍺層，每一對矽鍺層的組成與第二摻雜漸變矽鍺層114和應力調控矽鍺層120的組成相同，例如是Si_1-x2Ge_x2和Si_1-x3Ge_x3，其中x2是第二摻雜漸變矽鍺層114的鍺莫爾分率，x3是應力調控矽鍺層120的鍺莫爾分率，每一對矽鍺層的厚度小於第一摻雜漸變矽鍺層112和第二摻雜漸變矽鍺層114的厚度，例如可以是0.5nm至15nm，並且第二超晶格結構115可包含20對矽鍺層，第二超晶格結構115中可摻雜例如是Ge、As、O原子或前述之組合，摻雜濃度例如為1x10²⁰atom/cm^-3。此外，第5圖的複合基板100之應力傳遞矽層130的厚度可以是50nm至100nm。FIG. 5 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure. The difference between FIG. 5 and FIG. 3 is that asecond superlattice structure 115 is additionally provided between the second doped gradedsilicon germanium layer 114 and the stress-regulatingsilicon germanium layer 120 of thecomposite substrate 100 in FIG. 5 , in this embodiment. The stress gradedlayer 140 includes a first doped gradedsilicon germanium layer 112, a second doped gradedsilicon germanium layer 114, and asecond superlattice structure 115, which are sequentially disposed between thesubstrate 110 and the stress controlsilicon germanium layer 120 from bottom to top. between. Thesecond superlattice structure 115 includes a plurality of pairs of silicon germanium layers stacked in pairs, and the composition of each pair of silicon germanium layers is the same as that of the second doped gradedsilicon germanium layer 114 and the stress regulationsilicon germanium layer 120, such as Si_1-x2 Ge_x2 and Si_1-x3 Ge_x3 , where x2 is the germanium mole fraction of the second doped gradedsilicon germanium layer 114, x3 is the germanium mole fraction of the stress-regulatingsilicon germanium layer 120, each pair The thickness of the silicon germanium layer is smaller than the thickness of the first doped gradedsilicon germanium layer 112 and the second doped gradedsilicon germanium layer 114, for example, it can be 0.5nm to 15nm, and thesecond superlattice structure 115 can include 20 pairs of silicon germanium layer, thesecond superlattice structure 115 can be doped with, for example, Ge, As, O atoms or a combination thereof, and the doping concentration is, for example, 1×10²⁰ atom/cm⁻³ . In addition, the thickness of the stresstransfer silicon layer 130 of thecomposite substrate 100 in FIG. 5 may be 50 nm to 100 nm.

第6圖是根據本揭露另一實施例所繪示的複合基板的剖面示意圖。第6圖與第3圖的差異在於第6圖的複合基板100之第一摻雜漸變矽鍺層112和第二摻雜漸變矽鍺層114之間額外設置有第一超晶格結構113，並且第二摻雜漸變矽鍺層114與應力調控矽鍺層120之間設置有第二超晶格結構115，此實施例之應力漸變層140包含第一摻雜漸變矽鍺層112、第一超晶格結構113、第二摻雜漸變矽鍺層114及第二超晶格結構115由下至上依序設置於基底110與應力調控矽鍺層120之間。在第6圖的複合基板100中，第一超晶格結構113和第二超晶格結構115的組成、摻雜元素、摻雜濃度及厚度可以參考前述第5圖和第6圖的複合基板100。FIG. 6 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure. The difference between FIG. 6 and FIG. 3 is that afirst superlattice structure 113 is additionally provided between the first doped gradedsilicon germanium layer 112 and the second doped gradedsilicon germanium layer 114 of thecomposite substrate 100 in FIG. 6 , Moreover, asecond superlattice structure 115 is provided between the second doped gradedsilicon germanium layer 114 and the stress-regulatingsilicon germanium layer 120. The stress gradedlayer 140 in this embodiment includes the first doped gradedsilicon germanium layer 112, the first Thesuperlattice structure 113 , the second doped gradedSiGe layer 114 and thesecond superlattice structure 115 are sequentially disposed between thesubstrate 110 and the stress-regulatingSiGe layer 120 from bottom to top. In thecomposite substrate 100 in Figure 6, the composition, doping elements, doping concentration and thickness of thefirst superlattice structure 113 and thesecond superlattice structure 115 can refer to the composite substrates in the preceding Figures 5 and 6 100.

根據本揭露之實施例，在第一摻雜漸變矽鍺層112、第二摻雜漸變矽鍺層114、應力調控矽鍺層120之間插入第一超晶格結構113、第二超晶格結構115可以強化複合基板100的這些矽鍺層的磊晶品質，避免差排(dislocation)產生，並且可避免因為各矽鍺層之間的應力釋放而造成複合基板100的結構受損。According to an embodiment of the present disclosure, thefirst superlattice structure 113 and the second superlattice structure are inserted between the first doped gradedsilicon germanium layer 112 , the second doped gradedsilicon germanium layer 114 , and the stress controlsilicon germanium layer 120 Thestructure 115 can enhance the epitaxial quality of these SiGe layers of thecomposite substrate 100 , avoid dislocation, and prevent structural damage of thecomposite substrate 100 due to stress release between the SiGe layers.

此外，可以使用有機金屬化學氣相沉積法(MOCVD)在同一製程腔室內形成前述實施例中的第一摻雜漸變矽鍺層112、第二摻雜漸變矽鍺層114、第一超晶格結構113、第二超晶格結構115、應力調控矽鍺層120和應力傳遞矽層130，因此可以改善製程效率，並避免這些層在製造過程受到污染。In addition, the first doped gradedsilicon germanium layer 112 , the second doped gradedsilicon germanium layer 114 , and the first superlattice in the foregoing embodiments can be formed in the same process chamber by metal organic chemical vapor deposition (MOCVD). Thestructure 113 , thesecond superlattice structure 115 , the stress-regulatingSiGe layer 120 and the stress-transferringSi layer 130 can improve process efficiency and avoid contamination of these layers during the manufacturing process.

第7圖是根據本揭露一實施例所繪示的高電子遷移率電晶體的剖面示意圖。如第7圖所示，高電子遷移率電晶體(HEMT)200包含成核層210設置在複合基板100上，複合基板100可以選自前述第1、3、4、5、6圖之複合基板100，為了簡化圖式，第7圖的複合基板100僅以一方塊繪示。成核層210設置在複合基板100的應力傳遞矽層130上，成核層210的材料例如是氮化鋁(AlN)，並且可包含由下層的第一成核層和上層的第二成核層，第一成核層的厚度可以是30nm至80nm，成長溫度介於800至1000℃，第二成核層的厚度可以是30nm至200nm，成長溫度介於900至1100℃。HEMT 200還包含緩衝層220，例如是超晶格層，設置於成核層210上，緩衝層220的材料例如是氮化鋁鎵，並且可包含多層氮化鋁鎵層，例如5層氮化鋁鎵緩衝層，這些氮化鋁鎵緩衝層的鋁莫爾分率從下到上逐漸減少，每一層氮化鋁鎵緩衝層的厚度介於50nm至1000nm，成長溫度介於1000至1300℃。緩衝層220中可摻雜元素例如是碳、鐵、鎂或前述之組合，其中碳的摻雜濃度例如為1x10¹⁶至1x10²¹atom/cm^-3，鐵或鎂的摻雜濃度例如為1x10¹⁶至1x10²⁰atom/cm^-3。HEMT 200還包含高電阻層230設置於緩衝層220上，高電阻層230的電阻率高於緩衝層220的電阻率，高電阻層230的材料例如是氮化鋁鎵，其鋁莫爾分率小於緩衝層220最頂層的鋁莫爾分率，高電阻層230的厚度可以是1600nm至2300nm，成長溫度介於1000至1300℃，高電阻層230中可摻雜元素例如是碳、鐵、鎂或前述之組合，其摻雜濃度範圍與緩衝層220相同。FIG. 7 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure. As shown in FIG. 7, a high electron mobility transistor (HEMT) 200 including anucleation layer 210 is disposed on acomposite substrate 100, and thecomposite substrate 100 can be selected from the composite substrates in the aforementioned FIGS. 1, 3, 4, 5, and 6. 100. In order to simplify the drawing, thecomposite substrate 100 in FIG. 7 is only shown in one block. Thenucleation layer 210 is disposed on the stresstransfer silicon layer 130 of thecomposite substrate 100. The material of thenucleation layer 210 is, for example, aluminum nitride (AlN), and may include a first nucleation layer of the lower layer and a second nucleation layer of the upper layer. layer, the thickness of the first nucleation layer can be 30nm to 80nm, the growth temperature is between 800 to 1000°C, the thickness of the second nucleation layer can be 30nm to 200nm, and the growth temperature is between 900 to 1100°C. The HEMT 200 also includes abuffer layer 220, such as a superlattice layer, disposed on thenucleation layer 210. The material of thebuffer layer 220 is, for example, aluminum gallium nitride, and may include multiple layers of aluminum gallium nitride, such as five layers of nitride The AlGaN buffer layer, the AlGaN buffer layer has a gradually decreasing aluminum mole fraction from bottom to top, the thickness of each AlGaN buffer layer is between 50nm and 1000nm, and the growth temperature is between 1000 and 1300°C. The elements that can be doped in thebuffer layer 220 are, for example, carbon, iron, magnesium, or a combination thereof, wherein the doping concentration of carbon is, for example, 1×10¹⁶ to 1×10²¹ atom/cm⁻³ , and the doping concentration of iron or magnesium is, for example, 1×10¹⁶ to 1x10²⁰ atom/cm^-3 . TheHEMT 200 also includes a high-resistance layer 230 disposed on thebuffer layer 220. The resistivity of the high-resistance layer 230 is higher than the resistivity of thebuffer layer 220. The material of the high-resistance layer 230 is, for example, aluminum gallium nitride, and its aluminum mole fraction is The molar fraction of aluminum in the topmost layer of thebuffer layer 220 is smaller than that of thebuffer layer 220. The thickness of thehigh resistance layer 230 can be 1600nm to 2300nm, and the growth temperature is between 1000 and 1300°C. The elements that can be doped in thehigh resistance layer 230 are carbon, iron, magnesium, etc. Or a combination of the foregoing, the doping concentration range of which is the same as that of thebuffer layer 220 .

HEMT 200還包含通道層(channel layer)240，其設置於高電阻層230上，通道層240的材料例如是氮化鎵(GaN)，厚度可以是0.2nm至1000nm，成長溫度介於1000至1300℃。電子提供層(barrier layer)250設置於通道層240上，電子提供層250的材料例如是氮化鋁鎵，厚度可以是10nm至30nm，成長溫度介於1000至1300℃。覆蓋層(cap layer)260設置於電子提供層250上，覆蓋層260可以是p型氮化鎵(GaN)層或p型氮化鋁鎵(AlGaN)層，其厚度可以分別為10nm至20nm、10nm至150nm，其中p型摻雜元素可以是鎂，摻雜濃度例如為1x10¹⁶至1x10²³atom/cm^-3。HEMT 200的成核層210、緩衝層220、高電阻層230、通道層240、電子提供層250和覆蓋層260都可以經由有機金屬化學氣相沉積法(MOCVD)而磊晶成長形成。TheHEMT 200 also includes achannel layer 240, which is disposed on thehigh resistance layer 230. The material of thechannel layer 240 is, for example, gallium nitride (GaN), the thickness of which can be 0.2 nm to 1000 nm, and the growth temperature is between 1000 and 1300 ℃. An electron supply layer (barrier layer) 250 is disposed on thechannel layer 240. The material of theelectron supply layer 250 is, for example, aluminum gallium nitride, the thickness of which may be 10nm to 30nm, and the growth temperature is between 1000 to 1300°C.A cap layer 260 is disposed on theelectron supply layer 250. Thecap layer 260 may be a p-type gallium nitride (GaN) layer or a p-type aluminum gallium nitride (AlGaN) layer, and its thickness may be 10nm to 20nm, respectively. 10 nm to 150 nm, wherein the p-type dopant element may be magnesium, and the doping concentration is, for example, 1×10¹⁶ to 1×10²³ atom/cm⁻³ . Thenucleation layer 210 , thebuffer layer 220 , thehigh resistance layer 230 , thechannel layer 240 , theelectron supply layer 250 and thecapping layer 260 of theHEMT 200 can all be epitaxially grown by metal organic chemical vapor deposition (MOCVD).

此外，HEMT 200還包含閘極電極270、源極電極280和汲極電極290。閘極電極27設置於覆蓋層260上，而源極電極280和汲極電極290分別設置於閘極電極270的兩側，且位於通道層240上，其中閘極電極270和覆蓋層260可以一起圖案化而形成，源極電極280和汲極電極290可以穿過電子提供層250到達通道層240的頂面，或者到達通道層240的一深度。如第7圖所示，未被覆蓋層260覆蓋的區域會因為通道層240和電子提供層250間所產生的壓電效應而形成二維電子氣(two dimensional electron gas)2DEG。利用閘極電極270向p型覆蓋層260施加偏壓，可以調控位於p型覆蓋層260下方的通道層240中的二維電子氣濃度，進而調控HEMT的開關。In addition, theHEMT 200 further includes agate electrode 270 , asource electrode 280 and adrain electrode 290 .The gate electrode 27 is arranged on thecover layer 260, and thesource electrode 280 and thedrain electrode 290 are respectively arranged on both sides of thegate electrode 270, and are located on thechannel layer 240, wherein thegate electrode 270 and thecover layer 260 can be together Formed by patterning, thesource electrode 280 and thedrain electrode 290 may pass through theelectron supply layer 250 to reach the top surface of thechannel layer 240 , or reach a depth of thechannel layer 240 . As shown in FIG. 7 , the area not covered by thecovering layer 260 will form a two dimensional electron gas (2DEG) due to the piezoelectric effect generated between thechannel layer 240 and theelectron supply layer 250 . Using thegate electrode 270 to apply a bias voltage to the p-type cladding layer 260 can regulate the two-dimensional electron gas concentration in thechannel layer 240 below the p-type cladding layer 260 , and then regulate the switching of the HEMT.

根據本揭露之實施例，複合基板100的基底110之核心層102為硬度較大的基底，可以提昇基底110抗翹曲的效果。此外，可以藉由基底110之介電層104的厚度調控來降低上方的磊晶層例如氮化鎵通道層240之應力影響，可以改善基底110的彎曲，因此複合基板100的基底110可以解決基板翹曲問題。另外，複合基板100的應力調控矽鍺層120的晶格較應力傳遞矽層130的晶格大，因此會對上方的氮化鎵通道層240產生張應力，讓通道層240的2DEG濃度增加，提高元件通道的電流量，進而提昇HEMT的電性效能。According to an embodiment of the present disclosure, thecore layer 102 of thebase 110 of thecomposite substrate 100 is a base with relatively high hardness, which can improve the warping resistance of thebase 110 . In addition, the thickness of thedielectric layer 104 of thesubstrate 110 can be adjusted to reduce the stress effect of the upper epitaxial layer such as the galliumnitride channel layer 240, which can improve the bending of thesubstrate 110, so thesubstrate 110 of thecomposite substrate 100 can solve the substrate problem. warping problem. In addition, compositeThe lattice of the stress-regulatingsilicon germanium layer 120 of thesubstrate 100 is larger than that of the stress-transferringsilicon layer 130, so tensile stress will be generated on the upper galliumnitride channel layer 240, which increases the 2DEG concentration of thechannel layer 240 and improves the device channel. The amount of current, thereby improving the electrical performance of the HEMT.

另外，根據本揭露之實施例，當應力漸變層140的鍺莫爾分率從頂部區域到底部區域逐漸增加時，應力漸變層140的晶格常數也會從頂部區域到底部區域逐漸增加，使得應力漸變層140的晶格從上至下逐漸變大，藉由應力漸變層140的第一摻雜漸變矽鍺層112和第二摻雜漸變矽鍺層114的組成漸變來調整晶格大小，使得上方的氮化鎵通道層240所受張應力增加，可以進一步提高通道層240中的二維電子氣濃度，進而提高元件通道的電流量。相較於氮化鎵磊晶層形成在矽基板上之HEMT，本揭露之實施例可以讓通道層240之2DEG濃度大幅增加約3倍，並且相較於氮化鎵磊晶層形成在SOI基板上之HEMT，本揭露之實施例可以讓通道層240之2DEG濃度大幅增加約26倍。In addition, according to an embodiment of the present disclosure, when the germanium mole fraction of thestress gradient layer 140 gradually increases from the top region to the bottom region, the lattice constant of thestress gradient layer 140 also gradually increases from the top region to the bottom region, so that The lattice of thestress gradient layer 140 gradually becomes larger from top to bottom, and the lattice size is adjusted by the composition gradient of the first doped gradedsilicon germanium layer 112 and the second doped gradedsilicon germanium layer 114 of the stress gradedlayer 140 , Increasing the tensile stress on the upperGaN channel layer 240 can further increase the two-dimensional electron gas concentration in thechannel layer 240 , thereby increasing the current flow of the element channel. Compared with HEMTs in which the GaN epitaxial layer is formed on a silicon substrate, the embodiments of the present disclosure can greatly increase the 2DEG concentration of thechannel layer 240 by about 3 times, and compared with the GaN epitaxial layer formed on an SOI substrate Above the HEMT, the embodiments of the present disclosure can substantially increase the 2DEG concentration of thechannel layer 240 by about 26 times.

此外，根據本揭露之實施例，第一超晶格結構113和第二超晶格結構115的設置可以避免差排(dislocation)產生，而可以強化第一摻雜漸變矽鍺層112、第二摻雜漸變矽鍺層114和應力調控矽鍺層120的磊晶品質，並且避免因為各矽鍺層之間的應力釋放而造成複合基板100的結構受損。另外，本揭露之實施例可以讓HEMT的整體磊晶結構之厚度超過10μm，有效降低元件漏電，改善HEMT在高電壓操作下的效能和可靠度。In addition, according to the embodiment of the present disclosure, the arrangement of thefirst superlattice structure 113 and thesecond superlattice structure 115 can avoid dislocation, and can strengthen the first doped gradedsilicon germanium layer 112, the second The doping of the gradedSiGe layer 114 and the stress control the epitaxial quality of theSiGe layer 120 and prevent the structural damage of thecomposite substrate 100 due to stress release between the SiGe layers. In addition, the embodiments of the present disclosure can make the thickness of the overall epitaxial structure of the HEMT exceed 10 μm, effectively reduce device leakage, and improve the performance and reliability of the HEMT under high-voltage operation.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:複合基板100: composite substrate

110:基底110: base

112:第一摻雜漸變矽鍺層112: the first doped graded silicon germanium layer

114:第二摻雜漸變矽鍺層114: the second doped graded silicon germanium layer

120:應力調控矽鍺層120: Stress control silicon germanium layer

130:應力傳遞矽層130: Stress transfer silicon layer

140:應力漸變層140: Stress gradient layer

Claims (11)

Translated fromChinese

一種高電子遷移率電晶體的複合基板，包括：一基底；一應力調控矽鍺層，設置於該基底上；一應力傳遞矽層，設置於該應力調控矽鍺層上；以及一應力漸變層，介於該基底與該應力調控矽鍺層間，具有一底部區域及一頂部區域，其中該底部區域的鍺莫爾分率高於該頂部區域的鍺莫爾分率。A composite substrate of a high electron mobility transistor, comprising: a substrate; a stress-regulating silicon-germanium layer disposed on the substrate; a stress-transferring silicon layer disposed on the stress-regulating silicon-germanium layer; and a stress gradient layer , between the substrate and the stress-regulating silicon germanium layer, has a bottom region and a top region, wherein the germanium mole fraction of the bottom region is higher than the germanium mole fraction of the top region.如請求項1所述的高電子遷移率電晶體的複合基板，其中該基底包括絕緣層上覆矽(silicon-on-insulator，SOI)基底、單晶半導體基底、多晶半導體基底、鑽石基底或藍寶石基底。The composite substrate of high electron mobility transistor as described in claim 1, wherein the substrate includes a silicon-on-insulator (SOI) substrate, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a diamond substrate or Sapphire base.如請求項2所述的高電子遷移率電晶體的複合基板，其中該單晶半導體基底或該多晶半導體基底包括矽、氮化鋁、碳化矽、氧化鎵或氮化硼。The composite substrate of high electron mobility transistor according to claim 2, wherein the single crystal semiconductor substrate or the polycrystalline semiconductor substrate comprises silicon, aluminum nitride, silicon carbide, gallium oxide or boron nitride.如請求項1所述的高電子遷移率電晶體的複合基板，其中該應力漸變層包括一第一摻雜漸變矽鍺層、一超晶格結構以及一第二摻雜漸變矽鍺層由下至上依序設置於該基底與該應力調控矽鍺層之間，其中該超晶格結構包括複數對矽鍺層，且該每一對矽鍺層的組成與該第一摻雜漸變矽鍺層和該第二摻雜漸變矽鍺層的組成相同。The composite substrate of high electron mobility transistor as claimed in claim 1, wherein the stress gradient layer comprises a first doped graded silicon germanium layer, a superlattice structure and a second doped graded silicon germanium layer consisting of Sequentially disposed between the substrate and the stress-regulating silicon germanium layer, wherein the superlattice structure includes a plurality of pairs of silicon germanium layers, and the composition of each pair of silicon germanium layers is the same as that of the first doped graded silicon germanium layer The composition is the same as that of the second doped graded silicon germanium layer.如請求項1所述的高電子遷移率電晶體的複合基板，其中該應力漸變層包括一第一摻雜漸變矽鍺層、一第二摻雜漸變矽鍺層以及一超晶格結構由下至上依序設置於該基底與該應力調控矽鍺層之間，其中該超晶格結構包括複數對矽鍺層，且該每一對矽鍺層的組成與該第二摻雜漸變矽鍺層和該應力調控矽鍺層的組成相同。The composite substrate of high electron mobility transistor as described in claim 1, wherein the stress graded layer includes a first doped graded silicon germanium layer, a second doped graded silicon germanium layer and a superlattice structure consisting of the following The upper layer is sequentially disposed between the substrate and the stress control silicon germanium layer, wherein the superlattice structure includes complexSeveral pairs of silicon germanium layers, and the composition of each pair of silicon germanium layers is the same as that of the second doped graded silicon germanium layer and the stress regulation silicon germanium layer.如請求項4或5所述的高電子遷移率電晶體的複合基板，其中該應力調控矽鍺層、該應力漸變層或該超晶格結構包含一包括鍺、砷、氧或前述之組合的摻雜元素。The composite substrate of high electron mobility transistors as claimed in claim 4 or 5, wherein the stress-regulating silicon-germanium layer, the stress-gradient layer or the superlattice structure comprises a compound comprising germanium, arsenic, oxygen or a combination thereof doping elements.如請求項1所述的高電子遷移率電晶體的複合基板，其中該應力漸變層包括一第一摻雜漸變矽鍺層、一第一超晶格結構、一第二摻雜漸變矽鍺層以及一第二超晶格結構由下至上依序設置於該基底與該應力調控矽鍺層之間。The composite substrate of high electron mobility transistor as claimed in item 1, wherein the stress gradient layer includes a first doped graded silicon germanium layer, a first superlattice structure, and a second doped graded silicon germanium layer And a second superlattice structure is arranged sequentially from bottom to top between the substrate and the stress-regulating silicon germanium layer.如請求項1所述的高電子遷移率電晶體的複合基板，其中該基底包括：一核心層；一介電層，包裹住該核心層；以及一半導體層，設置於該介電層和該應力調控矽鍺層之間。The composite substrate of high electron mobility transistors as claimed in item 1, wherein the base comprises: a core layer; a dielectric layer wrapping the core layer; and a semiconductor layer disposed between the dielectric layer and the Stress regulation between SiGe layers.一種高電子遷移率電晶體，包括：一基底；一應力調控矽鍺層，設置於該基底上；一應力傳遞矽層，設置於該應力調控矽鍺層上；一成核層，設置於該應力傳遞矽層上；一緩衝層，設置於該成核層上；一高電阻層，設置於該緩衝層上，具有的電阻率高於該緩衝層的電阻率；一通道層，設置於該高電阻層上；一電子提供層，設置於該通道層上；一覆蓋層，設置於該電子提供層上；一閘極電極，設置於該覆蓋層上；以及一源極電極和一汲極電極，分別設置於該閘極電極的兩側，且位於該通道層上。A high electron mobility transistor, comprising: a substrate; a stress-regulating silicon-germanium layer disposed on the substrate; a stress-transferring silicon layer disposed on the stress-regulating silicon-germanium layer; a nucleation layer disposed on the stress-regulating silicon-germanium layer On the stress transfer silicon layer; a buffer layer disposed on the nucleation layer; a high resistance layer disposed on the buffer layer having a resistivity higher than that of the buffer layer;A channel layer, arranged on the high resistance layer; an electron supply layer, arranged on the channel layer; a cover layer, arranged on the electron supply layer; a gate electrode, arranged on the cover layer; and a A source electrode and a drain electrode are respectively arranged on two sides of the gate electrode and located on the channel layer.如請求項9所述的高電子遷移率電晶體，更包括一應力漸變層設置於該基底與該應力調控矽鍺層之間，其中該摻雜漸變矽鍺層的底部區域的鍺莫爾分率高於頂部區域的鍺莫爾分率。The high electron mobility transistor as claimed in claim 9, further comprising a stress graded layer disposed between the substrate and the stress control silicon germanium layer, wherein the germanium mole fraction of the bottom region of the doped graded silicon germanium layer The ratio is higher than the germanium mole fraction in the top region.如請求項9所述的高電子遷移率電晶體，更包括一第一摻雜漸變矽鍺層、一第二摻雜漸變矽鍺層以及一超晶格結構設置於該基底與該應力調控矽鍺層之間，其中該超晶格結構設置於該第一摻雜漸變矽鍺層與該第二摻雜漸變矽鍺層之間，或者設置於該第二摻雜漸變矽鍺層與該應力調控矽鍺層之間，或者前述之組合。The high electron mobility transistor as described in Claim 9, further comprising a first doped graded silicon germanium layer, a second doped graded silicon germanium layer, and a superlattice structure disposed on the substrate and the stress control silicon between the germanium layers, wherein the superlattice structure is disposed between the first doped graded silicon germanium layer and the second doped graded silicon germanium layer, or disposed between the second doped graded silicon germanium layer and the stress Regulate between silicon germanium layers, or a combination of the foregoing.

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