TWI782959B - Semiconductor device - Google Patents

Abstract

Translated fromChinese

本發明的半導體裝置具有：包含多個多晶矽電阻器單元的分壓電阻電路元件、以個別地覆蓋多個多晶矽電阻器單元的各個的方式分割為多個的第一金屬膜、覆蓋分壓電阻電路元件的整體的一體的第二金屬膜、以及形成於第二金屬膜上的氮化矽膜，多個第一金屬膜的各個於多晶矽電阻器單元中包含覆蓋電極部的部分與覆蓋電極部以外的部分，覆蓋電極部以外的第一金屬膜與各自覆蓋的多晶矽電阻器單元進行電性連接。本發明提供一種可防止向分壓電阻電路整體的氫的浸入，且可抑制構成分壓電阻電路的各電阻器單元的電阻值調變的不均的半導體裝置。The semiconductor device of the present invention has: a voltage dividing resistor circuit element including a plurality of polysilicon resistor units; The integral second metal film of the element, and the silicon nitride film formed on the second metal film, each of the plurality of first metal films is in the polysilicon resistor unit including the part covering the electrode part and the part other than the covering electrode part The first metal film other than the covered electrode part is electrically connected to the respective covered polysilicon resistor units. The present invention provides a semiconductor device capable of preventing infiltration of hydrogen into the entire voltage-dividing resistor circuit and suppressing variation in resistance value modulation of each resistor unit constituting the voltage-dividing resistor circuit.

Description

Translated fromChinese

半導體裝置Semiconductor device

本發明是有關於一種半導體裝置。The present invention relates to a semiconductor device.

檢測電壓器等的類比(analog)積體電路(Integrated circuit，IC)以將電晶體與電阻器組合而輸出所需的特性的方式，具備例如包含多晶矽的薄膜電阻器的分壓(bleeder)電阻電路，並調整其電阻分壓比。於該薄膜電阻器上形成有層間絕緣膜及最終保護膜，但已知有如下問題：於其形成過程中因擴散的氫的浸入，導致分壓電阻電路的電阻分壓比於晶圓面內不均，良率下降。一般的半導體裝置於薄膜電阻器上無接縫地配置大面積的金屬配線，避免該氫浸入的問題。An analog integrated circuit (Integrated circuit, IC) such as a voltage detection device is provided with, for example, a voltage divider (bleeder) resistance of a thin film resistor made of polysilicon in such a way that a transistor and a resistor are combined to output the required characteristics. circuit, and adjust its resistor divider ratio. An interlayer insulating film and a final protective film are formed on this thin film resistor, but it is known that there is a problem that the resistance voltage division ratio of the voltage dividing resistor circuit is not within the wafer surface due to the infiltration of diffused hydrogen during the formation process. Uneven, the yield rate drops. In general semiconductor devices, a large-area metal wiring is seamlessly arranged on a thin film resistor to avoid the problem of hydrogen infiltration.

其中，即便於以所述方式配置金屬配線的情況下，根據配線上的情況，將各電阻器的電極部彼此電性連接的金屬配線、即覆蓋電極部的金屬配線亦與覆蓋電極部以外的高電阻部的大面積的金屬配線分離。因此，於經分離的金屬配線間存在間隙，難以避免自所述間隙向電極部周邊的氫的浸入。向電極部周邊的氫的浸入的影響於搭載複雜的電路的多層配線結構的半導體裝置中變得顯著。However, even when the metal wiring is arranged as described above, depending on the situation on the wiring, the metal wiring that electrically connects the electrode parts of each resistor, that is, the metal wiring that covers the electrode part is also separated from the metal wiring that covers the electrode part. The large-area metal wiring of the high-resistance part is separated. Therefore, there is a gap between the separated metal wirings, and it is difficult to prevent hydrogen from infiltrating into the periphery of the electrode part from the gap. The influence of the infiltration of hydrogen into the periphery of the electrode portion becomes remarkable in a semiconductor device having a multilayer wiring structure on which a complicated circuit is mounted.

另一方面，於如所述般配置大面積的金屬配線的情況下，亦產生於構成分壓電阻電路的各電阻器單元，電阻值因不同的比例而調變的問題。其起因於：由電源電壓(V_dd、V_ss)形成的各電阻器單元的電位根據離電源的距離而不同，與接地的金屬配線的電位差於各電阻器單元而不同。例如，處於低電位側(V_ss)的電阻器單元與金屬配線的電位差小，因此電阻值調變小，相對於此，處於高電位側(V_dd)的電阻器單元與金屬配線的電位差大，因此電阻值調變大。各電阻器單元的電阻值調變的不均於使電源電壓變高的情況下變得顯著，要求一種所述情況下的對策。On the other hand, in the case of arranging large-area metal wiring as described above, a problem arises that the resistance value of each resistor unit constituting the voltage dividing resistor circuit is modulated according to a different ratio. This is caused by the fact that the potential of each resistor unit due to the power supply voltage (V_dd , V_ss ) differs depending on the distance from the power supply, and the potential difference between the metal wiring and the ground differs from that of each resistor unit. For example, the potential difference between the resistor unit on the low potential side (V_ss ) and the metal wiring is small, so the modulation of the resistance value is small, whereas the potential difference between the resistor unit on the high potential side (V_dd ) and the metal wiring is large , so the resistance value modulation is large. The variation in the resistance value modulation of each resistor unit becomes conspicuous when the power supply voltage is increased, and a countermeasure in this case is required.

作為電阻值調變的不均的對策之一，於專利文獻1中揭示有一種將金屬配線以與各電阻器單元相對應的方式分割，並將分割的金屬配線的各個與相對應的電阻器單元電性連接的構成。根據該構成，於電阻器單元與金屬配線之間未產生電位差，因此可避免電阻值調變的不均的問題。As one of countermeasures against uneven resistance value modulation, Patent Document 1 discloses a method in which a metal wiring is divided so as to correspond to each resistor unit, and each of the divided metal wiring is divided into a corresponding resistor unit. The composition of the electrical connection of the unit. According to this configuration, since no potential difference is generated between the resistor unit and the metal wiring, the problem of uneven modulation of the resistance value can be avoided.

其中，該構成中，於經分割的金屬配線彼此之間產生間隙，因此有可能通過間隙的氫擾亂分壓電阻電路的電阻分壓比，存在進一步改善的餘地。However, in this configuration, a gap is formed between the divided metal wirings, and therefore hydrogen passing through the gap may disturb the resistance voltage dividing ratio of the voltage dividing resistor circuit, and there is room for further improvement.

[現有技術文獻][Prior art literature][專利文獻][Patent Document]

[專利文獻1]日本專利第3526701號[Patent Document 1] Japanese Patent No. 3526701

本發明是鑒於所述情況而成者，其目的在於提供一種可防止向包含電極部的分壓電阻電路整體的氫的浸入，且可抑制構成分壓電阻電路的各電阻器單元的電阻值調變的不均的半導體裝置。The present invention is made in view of the above circumstances, and its purpose is to provide aA semiconductor device capable of suppressing infiltration of hydrogen into the entire voltage-dividing resistor circuit including electrode portions and suppressing variation in resistance value modulation of each resistor unit constituting the voltage-dividing resistor circuit.

為了解決所述課題，本發明採用以下的手段。In order to solve the above-mentioned problems, the present invention employs the following means.

(1)本發明的一實施方式的半導體裝置具有：基板；分壓電阻電路元件，形成於所述基板的其中一主面側，且包含多個多晶矽電阻器單元；第一金屬膜，以個別地覆蓋所述多個多晶矽電阻器單元的各個的方式分割為多個；一體的第二金屬膜，於所述第一金屬膜上覆蓋所述分壓電阻電路元件的整體；以及氮化矽膜，形成於所述第二金屬膜上；多個所述第一金屬膜的各個於所述多晶矽電阻器單元中包含覆蓋電極部的部分與覆蓋電極部以外的部分，覆蓋所述電極部以外的所述部分與各自覆蓋的所述多晶矽電阻器單元進行電性連接。(1) A semiconductor device according to an embodiment of the present invention includes: a substrate; a voltage dividing resistor circuit element formed on one of the main surfaces of the substrate and including a plurality of polysilicon resistor units; The method of covering each of the plurality of polysilicon resistor units is divided into a plurality; the integral second metal film covers the entirety of the voltage dividing resistor circuit element on the first metal film; and a silicon nitride film , formed on the second metal film; each of the plurality of first metal films includes a portion covering the electrode portion and a portion other than the covering electrode portion in the polysilicon resistor unit, and covers the portion other than the electrode portion The portions are electrically connected to the respective covered polysilicon resistor units.

(2)如所述(1)所述的半導體裝置，較佳為自所述氮化矽膜側的俯視時，所述第2金屬膜的最外周較所述分壓電阻電路元件的最外周處於更外側。(2) In the semiconductor device described in (1), it is preferable that when viewed from the side of the silicon nitride film, the outermost periphery of the second metal film is larger than the outermost periphery of the voltage dividing resistor circuit element. on the outer side.

(3)如所述(1)或(2)所述的半導體裝置，較佳為進而具有側壁部，所述側壁部立設於所述分壓電阻電路元件的周圍，並與所述第二金屬膜連接。(3) The semiconductor device described in (1) or (2) above preferably further has a side wall portion erected around the voltage dividing resistor circuit element and connected to the second Metal film connection.

(4)如所述(1)至(3)中任一項所述的半導體裝置，較佳為具有將所述基板與所述第一金屬膜連結的第一連接孔、以及將所述第一金屬膜與所述第二金屬膜連結的第二連接孔，所述側壁部包括埋入至所述第一連接孔中的金屬膜、以及埋入至所述第二連接孔中的金屬膜。(4) The semiconductor device described in any one of (1) to (3) preferably has a first connection hole that connects the substrate and the first metal film, and connects the first connection hole to the first metal film. A second connection hole connecting the metal film with the second metal film, the side wallThe portion includes a metal film buried in the first connection hole, and a metal film buried in the second connection hole.

(5)如所述(3)或(4)所述的半導體裝置，較佳為俯視時於形成有所述分壓電阻電路元件的區域與形成有所述側壁部的區域之間的區域具有多晶矽罩的構成。(5) In the semiconductor device described in (3) or (4), it is preferable that a region between the region where the voltage-dividing resistance circuit element is formed and the region where the sidewall portion is formed in plan view has The composition of the polysilicon cover.

所述半導體裝置中具有個別連接於多個多晶矽電阻器單元的各個的多個第一金屬膜，進而具有夾持第一金屬膜並覆蓋分壓電阻電路元件的整體的大面積的第二金屬膜。藉由具有第一金屬膜，多晶矽電阻器單元與第一金屬膜的電位差不論佈局如何均成為一定，因此可避免電阻值調變於各多晶矽電阻器單元不均的問題。The semiconductor device has a plurality of first metal films individually connected to each of the plurality of polysilicon resistor units, and further has a large-area second metal film sandwiching the first metal film and covering the entire voltage dividing resistor circuit element. . By having the first metal film, the potential difference between the polysilicon resistor unit and the first metal film becomes constant regardless of the layout, so that the problem of uneven resistance value adjustment among each polysilicon resistor unit can be avoided.

另外，藉由具有第二金屬膜，可避免於製造過程中氫浸入至分壓電阻電路元件中的問題。因此，所述半導體裝置中分壓電阻電路元件中所含有的氫的量較先前而明顯減少。In addition, by having the second metal film, the problem of hydrogen infiltrating into the voltage-dividing resistor circuit element during the manufacturing process can be avoided. Therefore, the amount of hydrogen contained in the voltage dividing resistor circuit element in the semiconductor device is significantly reduced compared to before.

將第二金屬膜設於第一金屬膜的上層側，無需如第一金屬膜般按照相對應的多晶矽電阻器單元的電極部、高電阻部進行分割，可形成無間隙地覆蓋包含電極部周邊在內的分壓電阻電路整體的形狀。因此，所述半導體裝置中，不僅可遮蔽向多晶矽電阻器的中央部的氫浸入路徑，而且亦可遮蔽向設有電極部的多晶矽電阻器的端部的氫浸入路徑，從而可防止伴隨分壓電阻電路元件的電阻分壓比的紊亂的良率下降。The second metal film is provided on the upper layer side of the first metal film, and it is not necessary to divide the electrode part and the high resistance part of the corresponding polysilicon resistor unit like the first metal film, and can form a gap-free covering including the electrode part periphery The overall shape of the voltage dividing resistor circuit inside. Therefore, in the semiconductor device, not only the hydrogen infiltration path to the central portion of the polysilicon resistor but also the hydrogen infiltration path to the end portion of the polysilicon resistor provided with the electrode portion can be shielded, thereby preventing the occurrence of partial pressure. Disturbance of the resistance voltage dividing ratio of the resistive circuit element lowers the yield.

10、10A、10B:多晶矽電阻器單元10, 10A, 10B: polysilicon resistor unit

11、21、31:多晶矽電阻器11, 21, 31: Polysilicon resistors

11A、21A、31A:電極部11A, 21A, 31A: electrode part

11B、21B、31B:高電阻部11B, 21B, 31B: high resistance part

12:保險絲電路元件12: Fuse circuit components

32:多晶矽罩32: Polysilicon cover

100、200、300:半導體裝置100, 200, 300: semiconductor device

101:基板(n型基板)(基材)101: Substrate (n-type substrate) (substrate)

101A、201A、301A:p型阱101A, 201A, 301A: p-type well

102、202、302:分壓電阻電路元件102, 202, 302: Voltage dividing resistor circuit components

102A:分壓電阻電路102A: Divider resistor circuit

103、203、203C、303、303C:第一金屬膜103, 203, 203C, 303, 303C: the first metal film

103A、203A、303A:電極引出層103A, 203A, 303A: electrode lead-out layer

103B、203B、303B:被覆層103B, 203B, 303B: coating layer

104、204、304:第二金屬膜104, 204, 304: the second metal film

105、205、305:氮化矽膜105, 205, 305: silicon nitride film

106、206、306:絕緣膜(場絕緣膜)106, 206, 306: insulating film (field insulating film)

107、207、307:絕緣膜107, 207, 307: insulating film

108、208、308:絕緣膜108, 208, 308: insulating film

109、209、309:絕緣膜109, 209, 309: insulating film

201、301:基板(n型基板)201, 301: substrate (n-type substrate)

207A、307A:第一連接孔207A, 307A: the first connecting hole

207B、307B:金屬膜207B, 307B: metal film

208A、308A:第二連接孔208A, 308A: the second connecting hole

208B、308B:金屬膜208B, 308B: metal film

210、310:p型高濃度擴散層(p⁺擴散層)210, 310: p-type high-concentration diffusion layer (p⁺ diffusion layer)

211、311:側壁部211, 311: side wall part

V_dd、V_ss:電源電壓V_dd , V_ss : power supply voltage

Vout:輸出電壓Vout: output voltage

圖1是本發明的第一實施形態的半導體裝置的平面圖。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

圖2(a)及圖2(b)是圖1的半導體裝置的剖面圖。2( a ) and FIG. 2( b ) are cross-sectional views of the semiconductor device of FIG. 1 .

圖3是構成圖1、圖2(a)及圖2(b)的半導體裝置的分壓電阻電路的圖。FIG. 3 is a diagram of a voltage dividing resistor circuit constituting the semiconductor device shown in FIG. 1 , FIG. 2( a ) and FIG. 2( b ).

圖4是本發明的第二實施形態的半導體裝置的平面圖。4 is a plan view of a semiconductor device according to a second embodiment of the present invention.

圖5是圖4的半導體裝置的剖面圖。FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4 .

圖6是本發明的第三實施形態的半導體裝置的平面圖。6 is a plan view of a semiconductor device according to a third embodiment of the present invention.

圖7(a)及圖7(b)是圖6的半導體裝置的剖面圖。7( a ) and FIG. 7( b ) are cross-sectional views of the semiconductor device of FIG. 6 .

以下，適當參照圖來對本發明進行詳細說明。對於以下的說明中所用的圖式，為了容易理解本發明的特徵，有時會為了方便而將成為特徵的部分放大表示，各構成要素的尺寸比率等有時與實際不同。另外，以下的說明中例示的材料、尺寸等為一例，本發明並不限定於該些，可在發揮本發明的效果的範圍內進行適當變更而實施。Hereinafter, the present invention will be described in detail with appropriate reference to the drawings. In the drawings used in the following description, in order to facilitate understanding of the features of the present invention, the characteristic parts may be enlarged for convenience, and the dimensional ratio of each component may be different from actual ones. In addition, the material, dimension, etc. which were illustrated in the following description are an example, and this invention is not limited to these, It can change suitably within the range which exhibits the effect of this invention, and can implement.

<第一實施形態><First Embodiment>

[半導體裝置的構成][Structure of semiconductor device]

圖1是本發明的第一實施形態的半導體裝置100的平面圖。圖2(a)及圖2(b)分別是於圖1中沿A-A'線、B-B'線切斷半導體裝置100時的剖面圖。FIG. 1 is a plan view of asemiconductor device 100 according to a first embodiment of the present invention. 2( a ) and FIG. 2( b ) are cross-sectional views of thesemiconductor device 100 cut along the lines AA' and BB' in FIG. 1 , respectively.

半導體裝置100具有基板(基材)101、形成於基板的其中一主面側的分壓電阻電路元件102、形成於分壓電阻電路元件102上的兩個金屬膜(第一金屬膜103、第二金屬膜104)、以及設於第二金屬膜104上的氮化矽膜105作為主要的構成要素。Thesemiconductor device 100 has a substrate (substrate) 101, a voltage dividingresistor circuit element 102 formed on one of the principal surfaces of the substrate, and two metal films (first metal film 103, second metal film 103) formed on the voltage dividingresistor circuit element 102. two metal films 104), and thesilicon nitride film 105 provided on thesecond metal film 104 as the main constituent elements.

於基板101與分壓電阻電路元件102之間、分壓電阻電路元件102與第一金屬膜103之間、第一金屬膜103與第二金屬膜104之間分別形成有絕緣膜106、絕緣膜107、絕緣膜108。亦可於第二金屬膜104與氮化矽膜105之間形成有絕緣膜109。再者，圖1中為了使作為主要部分的分壓電阻電路元件102及其周邊的構成明瞭化，省略基板、絕緣膜、氮化矽膜等的圖示。An insulatingfilm 106 and an insulating film are respectively formed between thesubstrate 101 and the voltage dividingresistor circuit element 102, between the voltage dividingresistor circuit element 102 and thefirst metal film 103, and between thefirst metal film 103 and thesecond metal film 104. 107. An insulatingfilm 108. An insulatingfilm 109 may also be formed between thesecond metal film 104 and thesilicon nitride film 105 . Note that, in FIG. 1 , illustration of a substrate, an insulating film, a silicon nitride film, and the like is omitted in order to clarify the configuration of the voltage dividingresistor circuit element 102 as a main part and its surroundings.

圖2(a)及圖2(b)所示的半導體裝置100中是使用於一主面側設有p型阱101A的n型基板101，具有兩層配線結構。分壓電阻電路元件102是設於形成於p型阱101A的表面的絕緣膜(場絕緣膜)106上。Thesemiconductor device 100 shown in FIG. 2( a ) and FIG. 2( b ) is used on an n-type substrate 101 provided with a p-type well 101A on one main surface side, and has a two-layer wiring structure. The voltage dividingresistor circuit element 102 is provided on an insulating film (field insulating film) 106 formed on the surface of the p-type well 101A.

再者，半導體裝置100的構成並不限於圖2(a)及圖2(b)所示者，亦可根據用途而設有分壓電阻電路元件102以外的元件，亦可具有兩層以上的配線結構。另外，亦可自由地設定基板上所摻雜的雜質的導電型。Moreover, the structure of thesemiconductor device 100 is not limited to those shown in FIG. 2(a) and FIG. 2(b), and may also be provided with elements other than the voltage dividingresistor circuit element 102 according to the application, or may have more than two layers. wiring structure. In addition, the conductivity type of impurities doped on the substrate can also be freely set.

分壓電阻電路元件102包含多個多晶矽電阻器單元10。多晶矽電阻器單元10包含摻雜有p型或n型的雜質、且顯示所需的電阻值的單體的多晶矽電阻器11、以顯示所需的電阻值的方式連接的多個多晶矽電阻器11中的一者或兩者。The voltage dividingresistor circuit element 102 includes a plurality ofpolysilicon resistor units 10 . Thepolysilicon resistor unit 10 includes asingle polysilicon resistor 11 doped with p-type or n-type impurities and exhibiting a desired resistance value, and a plurality ofpolysilicon resistors 11 connected so as to exhibit a desired resistance value. one or both of them.

即，分壓電阻電路元件102可僅由包含單體的多晶矽電阻器11的多晶矽電阻器單元10A構成，亦可僅由包含多個多晶矽電阻器11的多晶矽電阻器單元10B構成，抑或可將多晶矽電阻器單元10A、多晶矽電阻器單元10B兩者組合而構成。圖1中例示將多晶矽電阻器單元10A、多晶矽電阻器單元10B兩者組合而構成的情況。That is, the voltage-dividingresistance circuit element 102 may be composed of only apolysilicon resistor unit 10A including asingle polysilicon resistor 11, or may only be composed of apolysilicon resistor unit 10B including a plurality ofpolysilicon resistors 11, or may be made of polysilicon Theresistor unit 10A and thepolysilicon resistor unit 10B are combined. FIG. 1 exemplifies a case in which both thepolysilicon resistor unit 10A and thepolysilicon resistor unit 10B are combined.

作為第一金屬膜103，例如可使用Al-Si-Cu膜、Al-Cu膜等，其厚度較佳為大致3000Å以上且5000Å以下的範圍。As thefirst metal film 103 , for example, an Al—Si—Cu film, an Al—Cu film, or the like can be used, and its thickness is preferably in the range of approximately 3000 Å to 5000 Å.

第一金屬膜103是以個別地覆蓋多個多晶矽電阻器單元10的各個的方式分割為多個。即，於任一多晶矽電阻器單元10上亦設有各至少一片第一金屬膜103。於鄰接的多晶矽電阻器單元10上所設置的第一金屬膜103彼此相互隔開。Thefirst metal film 103 is divided into a plurality so as to individually cover each of the plurality ofpolysilicon resistor units 10 . That is, at least one piece of thefirst metal film 103 is also provided on anypolysilicon resistor unit 10 . Thefirst metal films 103 disposed on adjacentpolysilicon resistor units 10 are separated from each other.

多個第一金屬膜103的各個於多晶矽電阻器單元10中藉由覆蓋電極部11A的部分(電極引出層)103A、以及覆蓋電極部11A以外的高電阻部11B的部分(被覆層)103B而進一步分割。電極部11A位於各多晶矽電阻器11的端部，以較高電阻部11B更高的濃度摻雜有雜質。Each of the plurality offirst metal films 103 is formed in thepolysilicon resistor unit 10 by a portion (electrode lead-out layer) 103A covering theelectrode portion 11A and a portion (coating layer) 103B covering thehigh resistance portion 11B other than theelectrode portion 11A. further split.Electrode portion 11A is located at an end portion of eachpolysilicon resistor 11 , and is doped with impurities at a higher concentration thanresistance portion 11B.

圖3是藉由將電源電壓(V_dd、V_ss)進行分壓並輸出輸出電壓(V_out)使半導體裝置100運作的分壓電阻電路102A及其周邊電路的圖。分壓電阻電路102A中串聯連接有多個多晶矽電阻器單元10，相對於特定的多晶矽電阻器單元10而並列連接有保險絲電路元件12。3 is a diagram of a voltagedividing resistor circuit 102A and its peripheral circuits for operating thesemiconductor device 100 by dividing the power supply voltage (V_dd , V_ss ) and outputting the output voltage (V_out ). In the voltage dividingresistor circuit 102A, a plurality ofpolysilicon resistor units 10 are connected in series, and afuse circuit element 12 is connected in parallel to a specificpolysilicon resistor unit 10 .

被覆層103B與其各自覆蓋的多晶矽電阻器單元10經由金屬配線而連接。即，相對於一個多晶矽電阻器單元10而電性連接有覆蓋其的一個被覆層103B。因此，對串聯連接有多個多晶矽電阻器單元10的分壓電阻電路102A的一端側、另一端側分別施加不同的電源電壓V_dd、V_ss(V_dd>V_ss)並於兩者產生電位差的情況下，被覆層103B與多晶矽電阻器單元10亦成為等電位。Thecovering layer 103B is connected to thepolysilicon resistor cells 10 covered respectively via metal wiring. That is, acovering layer 103B covering apolysilicon resistor unit 10 is electrically connected to it. Therefore, different power supply voltages V_dd and V_ss (V_dd >V_ss ) are applied to one end and the other end of the voltage dividingresistor circuit 102A in which a plurality ofpolysilicon resistor units 10 are connected in series, and a potential difference is generated between them. In the case of , thecovering layer 103B and thepolysilicon resistor unit 10 also have the same potential.

將多晶矽電阻器單元10與被覆層103B連接的金屬配線的材料亦可為與第一金屬膜103相同者，亦可為高熔點金屬的鎢等。The material of the metal wiring connecting thepolysilicon resistor unit 10 and thecovering layer 103B may be the same as that of thefirst metal film 103 , or may be tungsten, which is a high melting point metal, or the like.

作為第二金屬膜104，例如可使用Al-Si-Cu膜、Al-Cu膜等，其厚度較佳為大致3000Å以上且10000Å以下的範圍。As thesecond metal film 104, for example, an Al—Si—Cu film, an Al—Cu film, or the like can be used, and its thickness is preferably in the range of approximately 3000 Å to 10000 Å.

第二金屬膜104為夾持第一金屬膜103且無接縫地覆蓋包含電極部11A的分壓電阻電路元件102的整體的一體的大面積膜。第二金屬膜104的電位以V_ss接地。Thesecond metal film 104 is an integral large-area film that sandwiches thefirst metal film 103 and covers the entire voltage dividingresistor circuit element 102 including theelectrode portion 11A without a joint. The potential of thesecond metal film 104 is grounded at V_ss .

本實施形態的半導體裝置100中具有個別連接於多個多晶矽電阻器單元10的各個的多個第一金屬膜103，進而具有夾持第一金屬膜103並覆蓋分壓電阻電路元件102的整體的大面積的第二金屬膜104。藉由具有第一金屬膜103，多晶矽電阻器單元10與第一金屬膜103的電位差不論佈局如何均成為一定，因此可避免電阻值調變於各多晶矽電阻器單元10不均的問題。Thesemiconductor device 100 of this embodiment has a plurality offirst metal films 103 individually connected to each of the plurality ofpolysilicon resistor units 10 , and further has a structure covering the entirety of the voltage dividingresistor circuit element 102 sandwiching thefirst metal films 103 . Large-areasecond metal film 104 . By having thefirst metal film 103 , the potential difference between thepolysilicon resistor unit 10 and thefirst metal film 103 becomes constant regardless of the layout, thus avoiding the problem of non-uniform resistance adjustment among thepolysilicon resistor units 10 .

另外，藉由具有第二金屬膜104，可避免於製造過程中氫浸入至分壓電阻電路元件102中的問題。因此，本實施形態的半導體裝置100中分壓電阻電路元件102中所含有的氫的量較先前而明顯減少。In addition, by having thesecond metal film 104 , the problem of hydrogen infiltrating into the voltage-dividingresistor circuit element 102 during the manufacturing process can be avoided. Therefore, in this embodimentThe amount of hydrogen contained in the voltage dividingresistor circuit element 102 in thesemiconductor device 100 is significantly reduced compared to before.

將第二金屬膜104設於第一金屬膜103的上層側，無需如第一金屬膜103般按照相對應的多晶矽電阻器單元10的電極部11A、高電阻部11B進行分割，可形成無間隙地覆蓋包含電極部11A周邊在內的分壓電阻電路102A整體的形狀。因此，本實施形態的半導體裝置100中，不僅可遮蔽向多晶矽電阻器11的高電阻部11B的氫浸入路徑，而且亦可遮蔽向多晶矽電阻器11的設有電極部11A的端部的氫浸入路徑，從而可防止伴隨分壓電阻電路元件102的電阻分壓比的紊亂的良率下降。Thesecond metal film 104 is provided on the upper layer side of thefirst metal film 103, without dividing the correspondingelectrode part 11A andhigh resistance part 11B of thepolysilicon resistor unit 10 like thefirst metal film 103, and can form a gapless The shape of the entire voltage-dividingresistor circuit 102A including the periphery of theelectrode portion 11A is completely covered. Therefore, in thesemiconductor device 100 of this embodiment, not only the hydrogen infiltration path to thehigh resistance portion 11B of thepolysilicon resistor 11 can be shielded, but also the hydrogen infiltration path to the end portion of thepolysilicon resistor 11 where theelectrode portion 11A is provided can be shielded. The path can prevent the yield drop caused by the disorder of the resistance voltage dividing ratio of the voltage dividingresistor circuit element 102 .

較佳為自氮化矽膜105側的俯視時，第二金屬膜104的最外周較分壓電阻電路元件102的最外周處於更外側。該情況下，可於第二金屬膜104中阻止相對於分壓電阻電路元件102而欲自上層側垂直地浸入的氫、以及欲傾斜地浸入的氫的一部分，相對應地，可提高相對於氫的分壓電阻電路元件102的保護功能。Preferably, when viewed from the side of thesilicon nitride film 105 , the outermost periphery of thesecond metal film 104 is located further outside than the outermost periphery of the voltage dividingresistor circuit element 102 . In this case, the hydrogen that tends to infiltrate vertically from the upper layer side with respect to the voltage dividingresistor circuit element 102 and part of the hydrogen that infiltrates obliquely with respect to the voltage dividingresistor circuit element 102 can be blocked in thesecond metal film 104, and accordingly, the relative hydrogen density can be improved. The protection function of the voltage dividingresistor circuit element 102.

先前的結構中，需要利用第一金屬膜確實地覆蓋高電阻部，因此第一金屬膜以不僅覆蓋高電阻部而且亦覆蓋低電阻部的一部分的方式大範圍地形成。即，先前結構中，於第一金屬膜存在與低電阻部的重疊(overlap)區域。In the conventional structure, it is necessary to reliably cover the high-resistance portion with the first metal film, and therefore the first metal film is formed over a wide area to cover not only the high-resistance portion but also a part of the low-resistance portion. That is, in the conventional structure, there is an overlap region with the low-resistance portion on the first metal film.

相對於此，本實施形態的半導體裝置100中，第二金屬膜104起到覆蓋高電阻部的作用，因此無需大範圍地形成第一金屬膜103，可削減第一金屬膜103與低電阻部的重疊區域，並可縮小半導體裝置整體的尺寸。In contrast, in thesemiconductor device 100 of the present embodiment, thesecond metal film 104 serves to cover the high-resistance portion, so it is not necessary to form thefirst metal film 103 in a wide area, and the contact between thefirst metal film 103 and the low-resistance portion can be reduced. overlapping area, and can shrinkThe overall size of a small semiconductor device.

另外，於先前結構中，為了於分割的第一金屬膜彼此的間隙處，利用第一金屬膜確實地覆蓋高電阻部，配置有虛設的電阻器，但本實施形態中無需如此，進而可縮小半導體裝置整體的尺寸。In addition, in the conventional structure, a dummy resistor is arranged in order to reliably cover the high resistance portion with the first metal film in the gap between the divided first metal films, but this is not necessary in the present embodiment, and the size can be further reduced. The overall size of the semiconductor device.

[半導體裝置的製造方法][Manufacturing method of semiconductor device]

以形成分壓電阻電路元件102及其周邊部分的步驟為中心來對半導體裝置100的製造方法進行說明。A method of manufacturing thesemiconductor device 100 will be described centering on the steps of forming the voltage dividingresistor circuit element 102 and its peripheral parts.

首先，於n型基板的其中一主面側摻雜p型雜質而形成p型阱。繼而，利用矽局部氧化(Local Oxidation of Silicon，LOCOS)法或淺溝槽隔離(Shallow Trench Isolation，STI)法來形成場絕緣膜。繼而，於p型阱內的規定位置形成p型雜質濃度相對高的區域(p⁺擴散層)。First, p-type impurities are doped on one of the main surfaces of the n-type substrate to form a p-type well. Then, a field insulating film is formed by using a Local Oxidation of Silicon (LOCOS) method or a Shallow Trench Isolation (STI) method. Next, a region (p⁺ diffusion layer) having a relatively high p-type impurity concentration is formed at a predetermined position in the p-type well.

其次，利用化學氣相沈積(Chemical Vapor Deposition，CVD)法等公知的方法，於場絕緣膜上進行構成分壓電阻電路的多晶矽(多矽)的膜形成，進而以成為所需的形狀、配置的方式進行圖案化，從而形成多個多晶矽電阻器。所形成的電阻器的厚度較佳為設為大致500Å以上且5000Å以下。Next, a known method such as chemical vapor deposition (Chemical Vapor Deposition, CVD) is used to form a film of polysilicon (polysilicon) forming a voltage dividing resistor circuit on the field insulating film, and then to obtain a desired shape and arrangement. Patterned in a manner to form a plurality of polysilicon resistors. The thickness of the formed resistor is preferably approximately 500 Å or more and 5000 Å or less.

其次，利用CVD法等公知的方法，於多晶矽電阻器上形成層間絕緣膜。繼而，於與包含單個或多個多晶矽電阻器的多晶矽電阻器單元的至少一部分重合的位置，在層間絕緣膜內形成接觸孔。繼而，將金屬膜埋入至接觸孔內。埋入的金屬膜的材料亦可為與第一金屬膜的材料相同者，亦可為高熔點金屬的鎢。Next, an interlayer insulating film is formed on the polysilicon resistor by a known method such as CVD. Then, a contact hole is formed in the interlayer insulating film at a position overlapping with at least a part of the polysilicon resistor unit including the single or a plurality of polysilicon resistors. Then, the metal film is buried in the contact hole. The material of the embedded metal filmIt may be the same material as that of the first metal film, or may be tungsten which is a high melting point metal.

其次，利用濺鍍法等公知的方法，於形成有接觸孔的層間絕緣膜上形成第一金屬膜。而且，對於所形成的第一金屬膜而言，以1比1對應於各多晶矽電阻器單元的方式進行圖案化並加以分割。藉由該分割，針對各多晶矽電阻器單元而形成有相對應的第一金屬膜的被覆層。即，成為一個第一金屬膜被覆一個多晶矽電阻器單元的狀態。Next, a first metal film is formed on the interlayer insulating film in which the contact hole is formed by a known method such as sputtering. Furthermore, the formed first metal film is patterned and divided so as to correspond to each polysilicon resistor unit on a 1:1 basis. By this division, a corresponding covering layer of the first metal film is formed for each polysilicon resistor unit. That is, one polysilicon resistor cell is covered with one first metal film.

作為第一金屬膜，例如可使用Al-Si-Cu膜、Al-Cu膜。第一金屬膜的厚度較佳為於大致3000Å以上且5000Å以下的範圍內設定。As the first metal film, for example, an Al-Si-Cu film or an Al-Cu film can be used. The thickness of the first metal film is preferably set within a range of approximately 3000 Å to 5000 Å.

其次，利用CVD法等公知的方法，於第一金屬膜上形成層間絕緣膜，並利用濺鍍法等公知的方法，於該層間絕緣膜上形成第二金屬膜。此時，成為至少覆蓋分壓電阻電路元件的整體的、一體的具有大面積的膜。Next, an interlayer insulating film is formed on the first metal film by a known method such as CVD, and a second metal film is formed on the interlayer insulating film by a known method such as sputtering. In this case, it becomes an integral film with a large area covering at least the entire voltage dividing resistor circuit element.

作為第二金屬膜，例如可使用Al-Si-Cu膜、Al-Cu膜。第二金屬膜的厚度較佳為於大致3000Å以上且10000Å以下的範圍內設定。As the second metal film, for example, an Al-Si-Cu film or an Al-Cu film can be used. The thickness of the second metal film is preferably set within a range of approximately 3000Å to 10000Å.

最後，利用電漿CVD法，直接或經由氧化膜而於第二金屬膜上形成氮化矽膜，藉此可獲得本實施形態的半導體裝置100。Finally, a silicon nitride film is formed on the second metal film directly or via an oxide film by plasma CVD, thereby obtaining thesemiconductor device 100 of this embodiment.

<第二實施形態><Second Embodiment>

[半導體裝置的構成][Structure of semiconductor device]

圖4是本發明的第二實施形態的半導體裝置200的平面圖。圖5是於圖4中沿C-C'線切斷半導體裝置200時的剖面圖。再者，圖4中為了使作為主要部分的分壓電阻電路元件及其周邊的構成明瞭化，省略基板、絕緣膜、氮化矽膜等的圖示。FIG. 4 is a plan view of asemiconductor device 200 according to a second embodiment of the present invention. FIG. 5 is a cross-sectional view of thesemiconductor device 200 taken along line CC' in FIG. 4 . In addition, in FIG. 4 , illustration of a substrate, an insulating film, a silicon nitride film, and the like is omitted in order to clarify the structure of the voltage-dividing resistor circuit element and its surroundings as a main part.

半導體裝置200具有立設於分壓電阻電路元件202的周圍(最外周)，頂部與第二金屬膜204連接且底部與基板201連接的側壁部211。於基板201的表面中連接有側壁部211的部分設有p型高濃度擴散層(p⁺擴散層)210。半導體裝置200的側壁部211以外的構成與第一實施形態的半導體裝置100的構成相同，可獲得與半導體裝置100同等的效果。Thesemiconductor device 200 has aside wall portion 211 standing around (the outermost periphery) of the voltage dividingresistor circuit element 202 , having a top connected to thesecond metal film 204 and a bottom connected to thesubstrate 201 . A p-type high-concentration diffusion layer (p⁺ diffusion layer) 210 is provided on a portion of the surface of thesubstrate 201 connected to theside wall portion 211 . The structure of thesemiconductor device 200 other than theside wall portion 211 is the same as that of thesemiconductor device 100 according to the first embodiment, and the same effect as that of thesemiconductor device 100 can be obtained.

側壁部211藉由第一金屬膜203C、分別埋入至第一金屬膜203C的下層側及上層側的絕緣膜207、絕緣膜208中所設置的接觸孔(第一連接孔207A、第二連接孔208A)中的金屬膜207B、金屬膜208B、以及第一連接孔207A之下的p型阱201A內所設置的p型高濃度擴散層(p⁺擴散層)210而構成為堆疊狀。第一連接孔207A將基板201與第一金屬膜203C連結，第二連接孔208A將第一金屬膜203C與第二金屬膜204連結。p型高濃度擴散層210於自半導體裝置200的最表面側的俯視時，包圍分壓電阻電路元件202的周圍。Theside wall portion 211 is formed by contact holes (first connection hole 207A,second connection hole 207A, second connection hole) provided in thefirst metal film 203C, the insulatingfilm 207 buried in the lower layer side and the upper layer side of thefirst metal film 203C, respectively, and the insulatingfilm 208. Themetal film 207B in thehole 208A), themetal film 208B, and the p-type high-concentration diffusion layer (p⁺ diffusion layer) 210 provided in the p-type well 201A under thefirst connection hole 207A are formed in a stacked form. Thefirst connection hole 207A connects thesubstrate 201 and thefirst metal film 203C, and thesecond connection hole 208A connects thefirst metal film 203C and thesecond metal film 204 . The p-type high-concentration diffusion layer 210 surrounds the periphery of the voltage-dividingresistance circuit element 202 in plan view from the outermost side of thesemiconductor device 200 .

較佳為自氮化矽膜205側的俯視時，側壁部211以短間隔並排，若無接縫地包圍分壓電阻電路元件202，則更佳。It is preferable that theside wall portions 211 are arranged at short intervals in a plan view from the side of thesilicon nitride film 205 , and it is more preferable that they surround the voltage dividingresistor circuit element 202 seamlessly.

藉由半導體裝置200中存在側壁部211，不僅可阻止自上方呈直線浸入至分壓電阻電路元件202中的氫，而且亦可阻止自側方迂回而浸入的氫，從而可更有力地保護分壓電阻電路元件202。Due to the presence of thesidewall portion 211 in thesemiconductor device 200, not only the self-The hydrogen infiltrating into the voltage-dividingresistor circuit element 202 in a straight line from the top can also prevent the hydrogen that infiltrates in a detour from the side, so that the voltage-dividingresistor circuit element 202 can be more effectively protected.

另外，側壁部211遮蔽自側方的氫浸入，因此第二金屬膜204只要僅遮蔽自上方呈直線向分壓電阻電路元件202浸入的氫即可。因此，第二金屬膜204的面積可設為與分壓電阻電路元件202相同程度的面積，與無側壁部211的情況相比，可縮小半導體裝置整體的尺寸。In addition, since theside wall portion 211 shields the infiltration of hydrogen from the side, thesecond metal film 204 only needs to shield the hydrogen infiltrating into the voltage dividingresistor circuit element 202 in a straight line from above. Therefore, the area of thesecond metal film 204 can be set to be approximately the same as the area of the voltage dividingresistor circuit element 202, and the overall size of the semiconductor device can be reduced compared to the case without thesidewall portion 211.

<第三實施形態><Third Embodiment>

[半導體裝置的構成][Structure of semiconductor device]

圖6是本發明的第三實施形態的半導體裝置300的平面圖。圖7(a)及圖7(b)分別是於圖6中沿D-D'線、E-E'線切斷半導體裝置300時的剖面圖。再者，圖6中為了使作為主要部分的分壓電阻電路元件及其周邊的構成明瞭化，省略基板、絕緣膜、氮化矽膜等的圖示。FIG. 6 is a plan view of asemiconductor device 300 according to a third embodiment of the present invention. 7( a ) and FIG. 7( b ) are cross-sectional views of thesemiconductor device 300 taken along the DD' line and the EE' line in FIG. 6 , respectively. In addition, in FIG. 6 , illustration of a substrate, an insulating film, a silicon nitride film, and the like is omitted in order to clarify the configuration of the main part of the voltage dividing resistor circuit element and its surroundings.

與第二實施形態同樣地，半導體裝置300具有立設於分壓電阻電路元件302的周圍(最外周)，頂部與第二金屬膜304連接且底部與基板301連接的側壁部311。另外，關於半導體裝置300的形成有側壁部311的區域的內側的分壓電阻電路元件302的構成，與第一實施形態的半導體裝置100的構成相同。Similar to the second embodiment, thesemiconductor device 300 has sidewalls 311 erected around (outermost) the voltage dividingresistor circuit element 302 , connected to thesecond metal film 304 at the top and connected to thesubstrate 301 at the bottom. In addition, the configuration of the voltage dividingresistor circuit element 302 inside the region where theside wall portion 311 is formed in thesemiconductor device 300 is the same as that of thesemiconductor device 100 according to the first embodiment.

如圖7(a)所示，亦與第二實施形態相同的是：側壁部311藉由第一金屬膜303C、分別埋入至第一金屬膜303C的下層側及上層側的絕緣膜307、絕緣膜308中所設置的接觸孔(第一連接孔307A、第二連接孔308A)中的金屬膜307B、金屬膜308B、以及第一連接孔307A之下的p型阱301A內所設置的p型高濃度擴散層(p⁺擴散層)310而構成為堆疊狀。而且，第一連接孔307A將基板301與第一金屬膜303C連結，第二連接孔308A將第一金屬膜303C與第二金屬膜304連結。p型高濃度擴散層310於自半導體裝置300的最表面側的俯視時，包圍分壓電阻電路元件302的周圍。即，可藉由該些構成來獲得與第一實施形態及第二實施形態同等的效果。As shown in FIG. 7( a ), the same as the second embodiment is that theside wall portion 311 is buried in the insulatingfilm 307 on the lower layer side and the upper layer side of thefirst metal film 303C through thefirst metal film 303C, respectively. Themetal film 307B in the contact hole (first connection hole 307A,second connection hole 308A) provided in the insulatingfilm 308, themetal film 308B, and the p-type well 301A provided in thefirst connection hole 307A. Type high-concentration diffusion layer (p⁺ diffusion layer) 310 is formed in a stacked shape. Furthermore, thefirst connection hole 307A connects thesubstrate 301 and thefirst metal film 303C, and thesecond connection hole 308A connects thefirst metal film 303C and thesecond metal film 304 . The p-type high-concentration diffusion layer 310 surrounds the periphery of the voltage-dividingresistance circuit element 302 in plan view from the outermost side of thesemiconductor device 300 . That is, effects equivalent to those of the first embodiment and the second embodiment can be obtained by these configurations.

圖6的E-E'線的附近，為了使連接於電極部31A的電極引出層303A與未圖示的其他電路元件部分連接，於電極引出層303A朝分壓電阻電路元件302的外側延伸設置的部分，側壁部311具有接縫。In the vicinity of the EE' line in FIG. 6 , in order to connect the electrode lead-out layer 303A connected to theelectrode part 31A to other circuit element parts not shown, the electrode lead-out layer 303A is extended toward the outside of the voltage dividingresistor circuit element 302. part, theside wall portion 311 has a seam.

因此，第三實施形態中，半導體裝置300進而於形成有分壓電阻電路元件302的區域、與形成有側壁部311的區域之間的區域具有多晶矽罩32。將多晶矽罩32以於在側壁部311存在接縫的部分，俯視時填補所述側壁部311的接縫的方式，配置於分壓電阻電路元件302的外側的區域。圖6中，多晶矽罩32於分壓電阻電路元件302的外側的區域中，相對於配置有電極部31A的右側與左側的邊而平行且呈直線地設置。Therefore, in the third embodiment, thesemiconductor device 300 further includes thepolysilicon cap 32 in the region between the region where the voltage dividingresistor circuit element 302 is formed and the region where thesidewall portion 311 is formed. Thepolysilicon cap 32 is arranged in an area outside the voltage dividingresistor circuit element 302 so as to fill up the seam of theside wall portion 311 in plan view at the portion where the seam exists in theside wall portion 311 . In FIG. 6 , thepolysilicon cover 32 is provided in parallel and linearly with respect to the right side and the left side where theelectrode portion 31A is arranged in the region outside the voltage dividingresistor circuit element 302 .

如圖7(b)的剖面圖所示，多晶矽罩32是於多晶矽電阻器31的兩側的場絕緣膜306上，由與多晶矽電阻器31相同的多晶矽層形成。於多晶矽罩32上，將電極引出層303A較形成有第二金屬膜304的區域而更進一步朝外側延伸設置，無法於此處形成側壁部311。因此，氫有可能通過該側壁部311的接縫而侵入至多晶矽電阻器31。多晶矽罩32可吸收通過側壁部311的接縫而朝多晶矽電阻器31侵入的氫，從而減少到達多晶矽電阻器31的氫。As shown in the sectional view of Fig. 7 (b), thepolysilicon cover 32 is on thefield insulating film 306 on both sides of thepolysilicon resistor 31, and is made of the same material as thepolysilicon resistor 31.A polysilicon layer is formed. On thepolysilicon cap 32 , the electrode lead-out layer 303A is extended further outward than the region where thesecond metal film 304 is formed, and thesidewall portion 311 cannot be formed there. Therefore, hydrogen may intrude into thepolysilicon resistor 31 through the seam of thesidewall portion 311 . Thepolysilicon cover 32 can absorb the hydrogen intruding toward thepolysilicon resistor 31 through the seam of thesidewall portion 311 , thereby reducing the hydrogen reaching thepolysilicon resistor 31 .

一般而言，多晶矽與單晶矽不同，包括矽原子有規律地鍵結而成的結晶性高的晶粒(grain)部分、以及作為其邊界部分且矽原子的排列不規則的結晶性低的晶粒邊界部分。於晶粒邊界部分存在大量的具有未結合鍵的原子。原子的未結合鍵中容易鍵結有氫，因此根據其鍵結不均而多晶矽電阻器的電阻值不均。圖6中的多晶矽罩32利用該性質，配置於分壓電阻電路元件302的外側的區域，由此吸收自多晶矽罩32的外側浸入的氫，抑制向較形成有多晶矽罩32的區域更靠內側的區域的氫的侵入。In general, polycrystalline silicon is different from single crystal silicon in that it includes a highly crystalline grain part where silicon atoms are regularly bonded, and a low crystallinity part where silicon atoms are arranged irregularly as a boundary part. part of the grain boundary. A large number of atoms having unbonded bonds exist in the grain boundary portion. Hydrogen is easily bonded to the unbonded bonds of atoms, so the resistance value of polysilicon resistors varies according to the uneven bonding. Thepolysilicon cover 32 in FIG. 6 takes advantage of this property and is arranged in the area outside the voltage dividingresistor circuit element 302, thereby absorbing the hydrogen infiltrated from the outside of thepolysilicon cover 32, and suppressing the hydrogen infiltrated from the area where thepolysilicon cover 32 is formed. hydrogen intrusion into the region.

半導體裝置300除第二金屬膜304與側壁部311以外，於側壁部311的接縫附近具備多晶矽罩32，藉此可抑制自外部的氫的浸入，可較第二實施形態更有力地保護分壓電阻電路元件302。In addition to thesecond metal film 304 and thesidewall portion 311, thesemiconductor device 300 is equipped with apolysilicon cap 32 near the joint of thesidewall portion 311, thereby suppressing infiltration of hydrogen from the outside and protecting the components more strongly than in the second embodiment.piezoresistive circuit element 302 .

圖6中，多晶矽罩32於分壓電阻電路元件302的外側的區域中，相對於配置有電極部31A的右側與左側的所有邊而平行且呈直線地設置，但並不限於該構成。即，亦可將多晶矽罩32局部配置於側壁部311的接縫的附近。另外，若俯視時於分壓電阻電路元件302的外側的區域的沿未配置有電極部31A的上側與下側的邊的部分存在側壁部311的接縫，則於該部分配置多晶矽罩32。另一方面，亦可以包圍分壓電阻電路元件302的整個周圍的方式無接縫地配置多晶矽罩32。藉此，可抑制來自任一方向的意外的氫的浸入，從而抑制多晶矽電阻器31的電阻值不均。In FIG. 6 , thepolysilicon cover 32 is provided parallel to and linearly with respect to all the right and left sides where theelectrode portion 31A is arranged in the region outside the voltage dividingresistor circuit element 302 , but the configuration is not limited to this configuration. That is, thepolysilicon cap 32 may be partially disposed near the joint of theside wall portion 311 . In addition, if viewed from above, the divided piezoelectricIn the outer region of theresistance circuit element 302 , there is a joint of theside wall portion 311 along the upper side and the lower side where theelectrode portion 31A is not disposed, and thepolysilicon cap 32 is disposed on this portion. On the other hand, thepolysilicon cover 32 may be seamlessly arranged so as to surround the entire periphery of the voltage dividingresistor circuit element 302 . Thereby, unintentional infiltration of hydrogen from any direction can be suppressed, thereby suppressing the uneven resistance value of thepolysilicon resistor 31 .

另外，多晶矽罩32的厚度較多晶矽電阻器31更厚時可減少氫浸入方向，因此遮蔽氫的效果高。圖7(a)及圖7(b)中，由相同的多晶矽層形成多晶矽電阻器31與多晶矽罩32。因此，無法使兩者的厚度不同，但可藉由以與多晶矽電阻器31不同的多晶矽層形成多晶矽罩32來實現厚度的不同。若多晶矽罩32為與多晶矽電阻器31不同的多晶矽層，厚度較多晶矽電阻器31更厚，則例如亦可利用場效型電晶體的閘極電極中所使用的多晶矽層、或調整電阻值的保險絲中所使用的多晶矽層(未圖示)。In addition, when the thickness of thepolysilicon cap 32 is thicker than that of thepolysilicon resistor 31, the direction of hydrogen infiltration can be reduced, so the effect of shielding hydrogen is high. In FIG. 7( a ) and FIG. 7( b ), thepolysilicon resistor 31 and thepolysilicon cap 32 are formed from the same polysilicon layer. Therefore, the thicknesses of both cannot be made different, but the difference in thickness can be realized by forming thepolysilicon cap 32 with a polysilicon layer different from that of thepolysilicon resistor 31 . If thepolysilicon cover 32 is a polysilicon layer different from thepolysilicon resistor 31, and the thickness is thicker than that of thepolysilicon resistor 31, then for example, the polysilicon layer used in the gate electrode of the field effect transistor, or a device for adjusting the resistance value can also be used. The polysilicon layer (not shown) used in the fuse.

11:多晶矽電阻器11: Polysilicon resistor

11A:電極部11A: electrode part

11B:高電阻部11B: High resistance part

100:半導體裝置100: Semiconductor device

101:基板(n型基板)(基材)101: Substrate (n-type substrate) (substrate)

101A:p型阱101A: p-type well

102:分壓電阻電路元件102: Voltage divider resistor circuit components

103:第一金屬膜103: The first metal film

103A:電極引出層103A: electrode lead-out layer

103B:被覆層103B: Coating layer

104:第二金屬膜104: Second metal film

105:氮化矽膜105: Silicon nitride film

106:絕緣膜(場絕緣膜)106: insulating film (field insulating film)

107:絕緣膜107: insulating film

108:絕緣膜108: insulating film

109:絕緣膜109: insulating film

Claims (5)

Translated fromChinese

一種半導體裝置，其特徵在於具有：基板；分壓電阻電路元件，形成於所述基板的其中一主面側，且包含多個多晶矽電阻器單元；第一金屬膜，以個別地覆蓋多個所述多晶矽電阻器單元的各個的方式分割為多個；一體的第二金屬膜，於所述第一金屬膜上覆蓋所述分壓電阻電路元件的整體；氮化矽膜，形成於所述第二金屬膜上；以及側壁部，所述側壁部立設於所述分壓電阻電路元件的周圍，並與所述第二金屬膜連接；並且多個所述第一金屬膜的各個於所述多晶矽電阻器單元中包含覆蓋電極部的部分與覆蓋所述電極部以外的部分，覆蓋所述電極部以外的部分與各自覆蓋的所述多晶矽電阻器單元進行電性連接，所述第一金屬膜與所述第二金屬膜之間形成有絕緣膜。A semiconductor device, characterized by comprising: a substrate; a voltage dividing resistor circuit element formed on one of the main surfaces of the substrate and including a plurality of polysilicon resistor units; a first metal film individually covering the plurality of resistor units. Each of the polysilicon resistor units is divided into multiple parts; the integral second metal film covers the entirety of the voltage dividing resistor circuit element on the first metal film; a silicon nitride film is formed on the first metal film on the second metal film; and a side wall portion, the side wall portion is erected around the voltage dividing resistor circuit element and connected to the second metal film; and each of the plurality of first metal films is on the The polysilicon resistor unit includes a portion covering the electrode portion and a portion covering the electrode portion, and the portion other than the electrode portion is electrically connected to the respective covered polysilicon resistor unit, and the first metal film An insulating film is formed between the second metal film.如申請專利範圍第1項所述的半導體裝置，其中自所述氮化矽膜側的俯視時，所述第二金屬膜的最外周較所述分壓電阻電路元件的最外周處於更外側。In the semiconductor device according to claim 1, when viewed from the side of the silicon nitride film, the outermost periphery of the second metal film is located outside the outermost periphery of the voltage dividing resistor circuit element.如申請專利範圍第1項或第2項所述的半導體裝置，其具有將所述基板與所述第一金屬膜連結的第一連接孔、以及將所述第一金屬膜與所述第二金屬膜連結的第二連接孔，所述側壁部包括埋入至所述第一連接孔中的金屬膜、以及埋入至所述第二連接孔中的金屬膜。The semiconductor device according to claim 1 or claim 2, which has a first connection hole connecting the substrate and the first metal film, andA second connection hole in which the first metal film is connected to the second metal film, the side wall portion includes a metal film embedded in the first connection hole, and a metal film embedded in the second connection hole. metal film.如申請專利範圍第1項或第2項所述的半導體裝置，其中俯視時於形成有所述分壓電阻電路元件的區域與形成有所述側壁部的區域之間的區域具有多晶矽罩。The semiconductor device according to claim 1 or claim 2, wherein a polysilicon cap is provided in a region between the region where the voltage dividing resistor circuit element is formed and the region where the sidewall portion is formed in plan view.如申請專利範圍第3項所述的半導體裝置，其中俯視時於形成有所述分壓電阻電路元件的區域與形成有所述側壁部的區域之間的區域具有多晶矽罩。The semiconductor device according to claim 3, wherein a polysilicon cap is provided in a region between the region where the voltage dividing resistor circuit element is formed and the region where the sidewall portion is formed in plan view.

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