TWI742256B

Movatterモバイル変換

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Publication number: TWI742256B
Application number: TW107108645A
Authority: TW
Inventors: 陶敏; 亮王; 拉傑許卡特卡爾; 塞普里昂艾米卡烏卓
Original assignee: 美商英帆薩斯公司
Priority date: 2017-03-16
Filing date: 2018-03-14
Publication date: 2021-10-11
Also published as: US12199082B2; US11715730B2; US20250038161A1; US20190088633A1; US20200235085A1; US11329034B2; US20240063199A1; US10629577B2; US20230317703A1; WO2018169968A1; US20210288037A1; US12166024B2; TW201843830A; US20250105234A1

Abstract

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

Description

Translated fromChinese

直接接合的LED陣列及應用 Directly bonded LED array and its application

本發明關於一種直接接合的LED陣列及應用。The invention relates to a directly bonded LED array and its application.

相關申請案Related applications

本專利申請案主張Tao等人於2017年3月16日申請之標題為「直接接合的LED陣列及應用(Direct Bonded LED Arrays and Applications)」的第62/472,363號美國臨時專利申請案之優先權益，且該申請案以全文引用之方式併入本文中。This patent application claims the priority of the U.S. Provisional Patent Application No. 62/472,363 entitled "Direct Bonded LED Arrays and Applications" filed on March 16, 2017 by Tao et al. , And the application is incorporated herein by reference in its entirety.

如本文中所使用，亦稱為微LED(micro-LED)、pLED及「mLED」之微LED(MicroLED)正作為一種新興之平板顯示技術而獲得顯著吸引力。但迄今為止，mLED顯示器尚未廣泛地量產或商品化。mLED顯示器為形成獨立像素元件之微觀LED的陣列。與廣泛之LCD技術相比較，mLED顯示器提供較大對比度及較快回應時間，同時使用較少能量。As used in this article, also known as micro-LED (micro-LED), pLED and "mLED" micro LED (MicroLED) is gaining significant appeal as an emerging flat panel display technology. But so far, mLED displays have not been widely produced or commercialized. The mLED display is an array of microscopic LEDs forming independent pixel elements. Compared with a wide range of LCD technologies, mLED displays provide greater contrast and faster response time, while using less energy.

連同激發有機化合物的膜以發射電致發光之有機發光二極體(organic light-emitting diode；OLED)一起，mLED可用於諸如智慧型電話及智慧型手錶之較小低能量裝置中，其中電池功率非常寶貴。Together with organic light-emitting diodes (OLEDs) that excite films of organic compounds to emit electroluminescence, mLEDs can be used in smaller low-energy devices such as smart phones and smart watches, where battery power Very precious.

mLED及OLED兩者需要比習知LCD系統更少之能量。然而，不同於OLED，mLED技術利用習知III-V無機半導體材料(GaN、InGaN等)以供用作用於照明及顯示之自發光LED，該些自發光LED可在勒克司每瓦特(lux per watt；lux/W)光輸出之較高效率的情況下，提供比OLED產品更高之總體亮度(例如超過OLED之30×)及更高之對比度。mLED技術亦可為容納mLED技術之產品提供較長工作壽命。此mLED陣列技術之版本對於汽車、虛擬實境及增強實境顯示器可為理想的。Both mLED and OLED require less energy than conventional LCD systems. However, unlike OLED, mLED technology uses conventional III-V inorganic semiconductor materials (GaN, InGaN, etc.) for use as self-luminous LEDs for lighting and display. These self-luminous LEDs can be used at lux per watt. Lux/W) In the case of higher light output efficiency, it provides higher overall brightness (for example, more than 30× of OLED) and higher contrast than OLED products. mLED technology can also provide a longer working life for products containing mLED technology. This version of mLED array technology is ideal for automobiles, virtual reality and augmented reality displays.

本發明提供直接接合的LED陣列及應用。實例方法製造LED結構，其包括用於LED結構之平面接合介面表面上之LED結構之p型及n型半導體的共面電接觸點。平面接合介面表面之共面電接觸點直接接合至用於LED結構之驅動器電路之電接觸點。在晶圓級方法中，微LED結構製造於第一晶圓上，該些結構包括用於該晶圓之該些平面接合介面表面上之該些LED結構的p型及n型半導體之共面電接觸點。平面接合介面之至少共面電接觸點直接接合至第二晶圓上之CMOS驅動器電路之電接觸點。該方法提供透明且可撓之微LED陣列顯示器，其中各微LED結構具有近似於在高分辨率視訊顯示器上呈現之圖像之像素或最小可控制元件之大小的照明區域。The present invention provides directly bonded LED arrays and applications. The example method manufactures an LED structure that includes coplanar electrical contacts of p-type and n-type semiconductors for the LED structure on the planar bonding interface surface of the LED structure. The coplanar electrical contact points of the planar bonding interface surface are directly bonded to the electrical contact points of the driver circuit for the LED structure. In the wafer-level method, micro LED structures are fabricated on a first wafer, and the structures include coplanar coplanarity of p-type and n-type semiconductors for the LED structures on the planar bonding interface surfaces of the wafer Electrical contacts. At least the coplanar electrical contact points of the planar bonding interface are directly bonded to the electrical contact points of the CMOS driver circuit on the second wafer. The method provides a transparent and flexible micro LED array display, wherein each micro LED structure has an illumination area similar to the size of the pixels or the smallest controllable element of the image presented on the high-resolution video display.

此發明內容不意欲標識所主張主題之關鍵特徵或基本特性，其亦不意欲用於輔助限制所主張主題之範圍。This summary is not intended to identify key features or basic characteristics of the claimed subject matter, nor is it intended to be used to assist in limiting the scope of the claimed subject matter.

50‧‧‧磊晶層結構/LED結構50‧‧‧Epitaxial layer structure/LED structure

100‧‧‧藍寶石基板100‧‧‧Sapphire substrate

101‧‧‧CTE匹配緩衝材料101‧‧‧CTE matching buffer material

102‧‧‧n-GaN層102‧‧‧n-GaN layer

104‧‧‧p-GaN層104‧‧‧p-GaN layer

106‧‧‧MQW層106‧‧‧MQW layer

108‧‧‧n接觸點108‧‧‧n contact point

110‧‧‧p接觸點110‧‧‧p contact point

200‧‧‧LED結構/LED晶粒200‧‧‧LED structure/LED die

202‧‧‧超平面接合介面202‧‧‧Hyperplane bonding interface

204‧‧‧絕緣體/氧化矽層204‧‧‧Insulator/silicon oxide layer

206‧‧‧佔據面積206‧‧‧Occupied area

208‧‧‧佔據面積208‧‧‧Occupied area

300‧‧‧直接接合方法300‧‧‧Direct bonding method

302‧‧‧驅動器電路302‧‧‧Driver circuit

304‧‧‧晶片/矽基驅動器積體電路/Si晶粒304‧‧‧Chip/Silicon-based driver integrated circuit/Si die

306‧‧‧超平面接合介面306‧‧‧Hyperplane bonding interface

400‧‧‧第一階段400‧‧‧Phase 1

402‧‧‧第二階段402‧‧‧Phase II

404‧‧‧特定位置404‧‧‧Specific location

406‧‧‧第三階段406‧‧‧Phase 3

408‧‧‧第四階段408‧‧‧Phase 4

410‧‧‧腔體410‧‧‧cavity

412‧‧‧第五階段412‧‧‧Fifth stage

414‧‧‧導體414‧‧‧Conductor

416‧‧‧晶種層塗層416‧‧‧Seed layer coating

418‧‧‧第六階段418‧‧‧The sixth stage

420‧‧‧電漿激活420‧‧‧Plasma activation

500‧‧‧mLED陣列顯示器500‧‧‧mLED array display

502‧‧‧晶圓502‧‧‧wafer

504‧‧‧晶圓504‧‧‧wafer

602‧‧‧非金屬介電質表面602‧‧‧Non-metallic dielectric surface

604‧‧‧接合介面604‧‧‧Connecting interface

606‧‧‧分佈式布拉格反射器/介面606‧‧‧Distributed Bragg reflector/interface

702‧‧‧薄化702‧‧‧Thinning

704‧‧‧無電晶體部分704‧‧‧Non-transistor part

802‧‧‧聚醯亞胺層802‧‧‧Polyimide layer

902‧‧‧可撓有機基板902‧‧‧Flexible organic substrate

1002‧‧‧背側堆積層1002‧‧‧Backside accumulation layer

1004‧‧‧光波導1004‧‧‧Optical Waveguide

1006‧‧‧邊緣發射組態1006‧‧‧Edge emission configuration

1008‧‧‧冷卻結構1008‧‧‧Cooling structure

1100‧‧‧方法1100‧‧‧Method

1102‧‧‧區塊Block 1102‧‧‧

1104‧‧‧區塊Block 1104‧‧‧

下文將參考隨附圖式來描述本揭示之某些具體實例，其中相同參考編號表示相同元件。然而，應理解，附圖說明本文中所描述之各種實施方案且並不意謂限制本文中所描述之各種技術之範圍。Hereinafter, some specific examples of the present disclosure will be described with reference to the accompanying drawings, in which the same reference numbers denote the same elements. However, it should be understood that the drawings illustrate the various embodiments described herein and are not meant to limit the scope of the various technologies described herein.

圖1為實例習知氮化物發光二極體(light emitting diode；LED)之圖。FIG. 1 is a diagram of an example of a conventional nitride light emitting diode (LED).

圖2為適用於使得直接接合的微LED結構的晶圓級、晶片陣列級及獨立晶片級建構實現電接觸點之直接接合的實例LED結構的圖。FIG. 2 is a diagram of an example LED structure suitable for direct bonding of electrical contact points in wafer-level, wafer-array-level, and independent wafer-level constructions of directly bonded micro LED structures.

圖3為以與驅動器電路直接接合操作之圖2之實例LED結構的圖。Figure 3 is a diagram of the example LED structure of Figure 2 operating in direct engagement with the driver circuit.

圖4為製造圖2之LED結構之實例方法的圖。Fig. 4 is a diagram of an example method of manufacturing the LED structure of Fig. 2.

圖5為製造實例LED陣列顯示器之第一階段的圖。Fig. 5 is a diagram of the first stage of manufacturing an example LED array display.

圖6為製造實例LED陣列顯示器之第二階段的圖。Fig. 6 is a diagram of the second stage of manufacturing the example LED array display.

圖7為製造實例LED陣列顯示器之第三階段的圖。Fig. 7 is a diagram of the third stage of manufacturing the example LED array display.

圖8為製造實例LED陣列顯示器之第四階段的圖。Fig. 8 is a diagram of the fourth stage of manufacturing the example LED array display.

圖9為製造實例LED陣列顯示器之第五階段的圖。Fig. 9 is a diagram of the fifth stage of manufacturing the example LED array display.

圖10為已完成之LED陣列顯示器及任選組件之圖。Figure 10 is a diagram of the completed LED array display and optional components.

圖11為製造直接接合的LED結構之實例方法的方塊圖。Figure 11 is a block diagram of an example method of manufacturing a directly bonded LED structure.

本揭示描述實例直接接合的發光二極體(light emitting diode；LED)陣列及應用。描述用於形成主動驅動mLED(microLED)結構及顯示單元之新穎方法，該方法包括將III-V化合物半導體mLED陣列接合至矽驅動器晶片以形成主動驅動mLED顯示單元之實例方法。此等方法中之一些可用於量產mLED陣列顯示器。This disclosure describes examples of directly bonded light emitting diode (LED) arrays and applications. A novel method for forming an actively driven mLED (microLED) structure and display unit is described. The method includes an example method of bonding a III-V compound semiconductor mLED array to a silicon driver chip to form an actively driven mLED display unit. Some of these methods can be used for mass production of mLED array displays.

實例方法及結構Example method and structure

圖1展示藍寶石基板100上方之發光二極體(light emitting diode；LED)之習知磊晶層結構50的實例，說明且比較用於本文中所描述之實例結構及方法之一些LED組件。舉例而言，實例習知LED結構50可產生綠光或藍光。半導體材料層化於載體上，諸如藍寶石基板100。GaN與藍寶石100之間的晶格常數及熱膨脹係數之較大失配將造成GaN膜中之較高結晶疵點密度，其引起裝置效能之降低；從而使晶格及CTE匹配緩衝材料101沉積於藍寶石100上以生長GaN。類似於習知LED結構50之光電裝置利用半導體摻雜，例如將少量矽或鍺添加至氮化鎵(gallium nitride；GaN)以使GaN成為用於電子(n型)n-GaN 102之導體，且將少量鎂添加至氮化鎵(gallium nitride；GaN)以使GaN形成於導體中以用於空穴(電子空穴)(p型)p-GaN 104。n-GaN 102之層與p-GaN 104之層之間包夾發光量子井或多量子井(multiple quantum well；MQW)材料(諸如氮化銦鎵InGaN)之超薄層，該超薄層比n-GaN 102及p-GaN 104之任一者具有更小之帶隙(及稍微較小之導電性)，該氮化銦鎵InGaN為由混合氮化鎵(gallium nitride；GaN)與氮化銦(indium nitride；InN)而製成之半導體材料。InGaN為三元第III族/第V族直接帶隙半導體。實例InGaN/GaN或InGaN MQW層106提供量子約束，或分散能量子頻帶，在子頻帶中，載波可僅具有分散能量值，在光學裝置中提供較佳效能。習知LED結構50於所使用之編號或層中可具有許多變型，且材料用於每一層。在圖1中，層，且尤其MQW層106未按相對比例展示。FIG. 1 shows an example of a conventionalepitaxial layer structure 50 of a light emitting diode (LED) above asapphire substrate 100, illustrating and comparing some of the LED components used in the example structures and methods described herein. For example, theconventional LED structure 50 can generate green light or blue light. The semiconductor material is layered on a carrier, such as asapphire substrate 100. The large mismatch in the lattice constant and thermal expansion coefficient between GaN andsapphire 100 will result in a higher density of crystal defects in the GaN film, which will cause a decrease in device performance; thus, the lattice and CTEmatching buffer material 101 will be deposited on thesapphire 100 to grow GaN. Photoelectric devices similar to theconventional LED structure 50 use semiconductor doping, for example, adding a small amount of silicon or germanium to gallium nitride (GaN) to make GaN a conductor for electron (n-type) n-GaN 102, And a small amount of magnesium is added to gallium nitride (GaN) so that GaN is formed in the conductor for holes (electron holes) (p-type) p-GaN 104. An ultra-thin layer of light-emitting quantum well or multiple quantum well (multiple quantum well; MQW) material (such as indium gallium nitride InGaN) is sandwiched between the layer of n-GaN 102 and the layer of p-GaN 104. Either n-GaN 102 and p-GaN 104 has a smaller band gap (and slightly smaller conductivity). The indium gallium nitride InGaN is made of mixed gallium nitride (GaN) and nitride A semiconductor material made of indium (indium nitride; InN). InGaN is a ternary Group III/Group V direct band gap semiconductor. The example InGaN/GaN orInGaN MQW layer 106 provides quantum confinement, or disperses energy sub-bands. In the sub-bands, the carrier can only have dispersed energy values, providing better performance in optical devices. Theconventional LED structure 50 can have many variations in the numbers or layers used, and the materials are used for each layer. In FIG. 1, the layers, and especially theMQW layer 106, are not shown in relative scale.

實例習知LED結構50之特徵在於n接觸點108及p接觸點110位於習知LED結構50之不同表面上之不同垂直水平處。p接觸點110與n接觸點108之間的垂直高度之差藉由電線接合或焊料連接習知地補償。或者，實例習知結構50可具有未暴露之n接觸點108(未展示)。Examples The characteristic of theconventional LED structure 50 is that the n-contact point 108 and the p-contact point 110 are located at different vertical levels on different surfaces of theconventional LED structure 50. The difference in the vertical height between the p-contact point 110 and the n-contact point 108 is conventionally compensated by wire bonding or solder connection. Alternatively, the exampleconventional structure 50 may have unexposed n-contact points 108 (not shown).

圖2至圖3展示用於將含有III-V半導體元件之LED組件直接接合至驅動器電路以用於製造mLED陣列顯示器的實例LED結構200及方法綜覽。實例LED結構200提供超平面接合介面202，該超平面接合介面介面202藉由例如使用由絕緣體204(諸如氧化矽)包圍且暴露於具有超平面接合介面202上之各別共面導電佔據面積206及208的超平面接合介面202上之n接觸點108及p接觸點110兩者之化學機械拋光(chemical-mechanical polishing；CMP)而形成平面。2 to 3 show an overview of anexample LED structure 200 and method for directly bonding LED components containing III-V semiconductor components to a driver circuit for manufacturing mLED array displays. Theexample LED structure 200 provides ahyperplanar bonding interface 202 which is surrounded by an insulator 204 (such as silicon oxide) and exposed to a respective coplanarconductive footprint 206 on thehyperplanar bonding interface 202 by, for example, using The n-contact point 108 and the p-contact point 110 on thehyperplanar junction interface 202 of and 208 are chemical-mechanical polishing (CMP) to form a plane.

n接觸點108及p接觸點110可由金屬或合金金屬之組合或促進直接接合的層壓金屬製成。除金屬組合物以外，超平面接合介面202自身亦促進n 接觸點108與p接觸點110之間的直接接合及各別導電面之接合。超平面接合介面202藉由鑲嵌方法製造，例如亦為超淨，且在幾十奈米內平坦，諸如小於波長為546.1奈米之單色綠光或為632.8奈米之氦氖紅色雷射光之照明源的1/4。在一些具體實例中，平面拋光表面202之粗糙度小於照明源之波長的5%且優選地小於10nm。The n-contact point 108 and the p-contact point 110 may be made of a combination of metals or alloy metals or laminated metals that promote direct bonding. In addition to the metal composition, thehyperplanar bonding interface 202 itself also promotes the direct bonding between the n-contact point 108 and the p-contact point 110 and the bonding of the respective conductive surfaces. Thesuper-planar bonding interface 202 is manufactured by a damascene method. For example, it is also ultra-clean and flat within tens of nanometers, such as a monochromatic green light with a wavelength of 546.1 nanometers or a helium-neon red laser light with a wavelength of 632.8 nanometers. 1/4 of the illumination source. In some specific examples, the roughness of the planarpolished surface 202 is less than 5% of the wavelength of the illumination source and preferably less than 10 nm.

圖3展示圖2之實例LED結構200與晶片304上之驅動器電路302之間、用以形成諸如薄膜電晶體(thin-film transistor；TFT)驅動器之LED電路的實例直接接合方法300。實例直接接合方法300可在獨立晶片之層級上，或在晶片陣列層級下或在晶圓級下執行。對於後續剝離及薄化，晶圓級直接接合可為最佳方式。3 shows an example direct bonding method 300 for forming an LED circuit such as a thin-film transistor (TFT) driver between theexample LED structure 200 of FIG. 2 and thedriver circuit 302 on thechip 304. The example direct bonding method 300 can be performed at the level of individual wafers, or at the wafer array level, or at the wafer level. For subsequent peeling and thinning, wafer-level direct bonding may be the best way.

在實施方案中，可將mLED超平面接合介面202接合至例如矽基驅動器積體電路(integrated circuit；IC)304之各別超平面接合介面306。超平面接合介面306可具有頂部有平面氧化矽層及銅(Cu)襯墊之接觸表面以促進直接接合(例如經由ZiBond®牌方法或DBI®牌方法直接接合)以形成LED電路(Xperi Corporation，San Jose，CA)。在實施方案中，藍寶石基板100可隨後經雷射剝離。若需要，則頂部及底部側兩者可經薄化進一步使得整個疊層可撓。In an embodiment, the mLEDhyperplane bonding interface 202 may be bonded to the respectivehyperplane bonding interface 306 of, for example, a silicon-based driver integrated circuit (IC) 304. Thesuper-planar bonding interface 306 may have a contact surface with a planar silicon oxide layer and a copper (Cu) pad on the top to facilitate direct bonding (for example, direct bonding via ZiBond® brand method or DBI® brand method) to form an LED circuit (Xperi Corporation, San Jose, CA). In an embodiment, thesapphire substrate 100 may be subsequently laser lifted. If necessary, both the top and bottom sides can be thinned to further make the entire laminate flexible.

圖4展示實例結構製造之階段，說明用於製造適用於與例如矽驅動器IC 304直接接合的LED結構200的實例方法流程。FIG. 4 shows the stages of manufacturing an example structure, illustrating an example method flow for manufacturing anLED structure 200 suitable for direct bonding with, for example, asilicon driver IC 304.

在實例方法流程之第一階段400中，諸如藍寶石基板100之實例晶圓與n-GaN 102、InGaN MQW 106及p-GaN 104之起始磊晶層一起累積。In thefirst stage 400 of the example method flow, an example wafer such as thesapphire substrate 100 is accumulated with the initial epitaxial layers of n-GaN 102,InGaN MQW 106, and p-GaN 104.

在實例方法流程之第二階段402中，圖案化且蝕刻頂部磊晶層以在特定位置404處暴露n-GaN層102。雖然在晶粒之邊緣處展示單個暴露位置404，但可存在多於一個位置。舉例而言，一或多個穿孔可暴露n-GaN層102。圖案化光阻可保留於其上。In thesecond stage 402 of the example method flow, the top epitaxial layer is patterned and etched to expose the n-GaN layer 102 at aspecific location 404. Although a singleexposed location 404 is shown at the edge of the die, there may be more than one location. For example, one or more through holes may expose the n-GaN layer 102. The patterned photoresist can remain on it.

在實例方法流程之第三階段406中，沉積諸如氧化矽層204之絕緣體或介電質以至少在接觸襯墊之位置處覆蓋經暴露p-GaN 104及經暴露n-GaN 102兩者。In thethird stage 406 of the example method flow, an insulator or dielectric such assilicon oxide layer 204 is deposited to cover both the exposed p-GaN 104 and the exposed n-GaN 102 at least at the location of the contact pads.

在實例方法流程之第四階段408中，於p-GaN 104及n-GaN 102層上方圖案化且蝕刻氧化矽層204以使得腔體410穿透氧化矽204以用於使導電金屬變為LED結構200之電極。在一實施方案中，p-GaN 104層及MQW 106層之總厚度為近似於2μm，使結構在此階段適用於單步蝕刻及金屬化(MQW層106，未按比例展示)。可形成此類腔體410中之一或多者以形成接觸n-GaN 102層及p-GaN 104層之一或多個電極。In thefourth stage 408 of the example method flow, thesilicon oxide layer 204 is patterned and etched over the p-GaN 104 and n-GaN 102 layers so that thecavity 410 penetrates thesilicon oxide 204 for turning the conductive metal into an LED Electrode ofstructure 200. In one embodiment, the total thickness of the p-GaN 104 layer and theMQW 106 layer is approximately 2 μm, making the structure suitable for single-step etching and metallization at this stage (MQW layer 106, not shown to scale). One or more ofsuch cavities 410 may be formed to form electrodes that contact one or more of the n-GaN 102 layer and the p-GaN 104 layer.

在替代實施方案中，實例方法使平面氧化矽層204如在上述第三階段406中沉積，隨後使用ZiBond®牌直接接合方法或其他直接接合技術直接與驅動晶片304一起接合此氧化物表面。隨後，貫穿矽之通孔(through-silicon-via；TSV)經打孔以建立自n接觸點108及p接觸點110至驅動器晶片304之電連接性。In an alternative embodiment, the example method deposits the planarsilicon oxide layer 204 as in thethird stage 406 described above, and then uses the ZiBond® brand direct bonding method or other direct bonding techniques to directly bond this oxide surface together with thedriver wafer 304. Subsequently, through-silicon-via (TSV) is punched to establish electrical connectivity from the n-contact point 108 and the p-contact point 110 to thedriver chip 304.

在實例方法流程之第五階段412中，腔體410可使用導電材料414金屬化。在一實施方案中，可塗佈且形成障壁及晶種層塗層416，隨後用有導體414填充之腔體，繼之以退火及化學機械平坦化(chemical-mechanical planarization；CMP)。在一實施方案中，可將諸如銦之低熔化溫度金屬塗佈於腔體中。In thefifth stage 412 of the example method flow, thecavity 410 may be metallized with aconductive material 414. In one embodiment, the barrier andseed layer coating 416 may be coated and formed, followed by filling the cavity with theconductor 414, followed by annealing and chemical-mechanical planarization (CMP). In one embodiment, a low melting temperature metal such as indium may be coated in the cavity.

在實例方法之第六階段418中，實例LED結構200之頂部表面經電漿激活420以用於直接接合操作。電漿激活420可視情況用於一些類型之直接接合技術，而在其它直接接合技術中，電漿激活步驟420例如在接觸接合期間促進兩個金屬表面之間的接合強度。電漿激活420亦可應用於待接合於驅動器晶片304上之相對表面。In thesixth stage 418 of the example method, the top surface of theexample LED structure 200 is plasma activated 420 for direct bonding operation.Plasma activation 420 can be used for some types of direct bonding technologies as appropriate, while in other direct bonding technologies, theplasma activation step 420 promotes the bonding strength between two metal surfaces, for example, during contact bonding.Plasma activation 420 can also be applied to the opposite surface to be bonded to thedriver chip 304.

在各種實施方案中，圖4中描繪之實例方法流程可包括挑選且傳送具有高產量之許多小LED晶片，且在極精細間距下直接接合，例如在小於1mm之間距(甚至用於製造微投影儀之更小間距)下，以及在0.05mm間距下，且在各種實施方案中一直降至具有6um凸塊之12μm間距。像素陣列光學件達成LED晶粒200與Si晶粒304之較高平行性。可實現諸如薄化及雷射剝離之後處理，此係由於直接接合塗佈導致平面形貌及較強接合介面達成。In various embodiments, the example method flow depicted in FIG. 4 may include selecting and transferring many small LED chips with high yields, and directly bonding them at very fine pitches, for example, between less than 1mm (even for manufacturing micro-projection It has been reduced to 12μm pitch with 6um bumps in various implementations under the smaller pitch of the instrument), and at the 0.05mm pitch, and in various embodiments. The pixel array optics achieve high parallelism between the LED die 200 and the Si die 304. It can achieve post-processing such as thinning and laser peeling, which is achieved by direct bonding coating resulting in a flat topography and a strong bonding interface.

圖5至9展示用於產生薄、透明且可撓之mLED陣列顯示器500之實例方法，在該方法中，具有藉由圖4之方法形成之LED結構200之晶圓502現接合至(例如)CMOS驅動器晶片晶圓504以形成透明且可撓之陣列顯示器500。FIGS. 5 to 9 show an example method for producing a thin, transparent, and flexiblemLED array display 500, in which method, awafer 502 with anLED structure 200 formed by the method of FIG. 4 is now bonded to (for example) The CMOSdriver chip wafer 504 forms a transparent andflexible array display 500.

在圖5中，在一實施方案中，在LED裝置晶圓502上之平面及經激活表面形成之後，CMOS晶圓504使用CMP或獲得超平面表面及電漿激活420之其他方法平面化。In FIG. 5, in one embodiment, after the planar and activated surfaces on theLED device wafer 502 are formed, theCMOS wafer 504 is planarized using CMP or other methods to obtain a hyperplanar surface andplasma activation 420.

在圖6中，接合兩個晶圓502及504。舉例而言，具有LED結構200且具有n接觸點108與p接觸點110之共面接合表面的第一晶圓502，以及具有CMOS驅動器晶片304之第二晶圓504接合在一起以用於金屬導體之間(且在一實施方案中亦在非金屬介電質表面602之間)的直接接合。與第二晶圓504之經暴露氧化矽相接觸的第一晶圓502之經暴露氧化矽首先經由如同ZiBond®牌直接接合方法之氧化物接合而接合。各別晶圓502及504之金屬接觸襯墊在如同DBI®牌直接接合方法之高於室溫之退火期間形成金屬至金屬接合。接合介面604可在近似於100℃至200℃下退火以形成較強直接接合介面，諸如ZiBond®或DBI®牌直接接合介面。In FIG. 6, twowafers 502 and 504 are joined. For example, thefirst wafer 502 with theLED structure 200 and the coplanar bonding surface of the n-contact 108 and the p-contact 110 and thesecond wafer 504 with theCMOS driver chip 304 are bonded together for metal Direct bonding between conductors (and also between non-metallicdielectric surfaces 602 in one embodiment). The exposed silicon oxide of thefirst wafer 502 that is in contact with the exposed silicon oxide of thesecond wafer 504 is first bonded by oxide bonding like the ZiBond® brand direct bonding method. The metal contact pads of therespective wafers 502 and 504 form a metal-to-metal bond during annealing at higher than room temperature as in the direct bonding method of the DBI® brand. Thebonding interface 604 can be annealed at approximately 100° C. to 200° C. to form a strong direct bonding interface, such as ZiBond® or DBI® brand direct bonding interface.

可沉積諸如分佈式布拉格反射器(distributed Bragg reflector；DBR)606(未按相對比例展示)之光學反射塗層以藉由挑選第一晶圓502與第二晶圓504之間的介面(606)處之晶圓502之頂部上之介電層的不同類型及厚度來增大封裝之光輸出。可替代地，DBR 606亦可在接合之前於第二晶圓504之頂部上形成。在DBR 606之此定向中，光可自裝置之藍寶石側逸出。若DBR 606於第一晶圓502上形成，則薄電介質需要在圖4中展示之方法之第二階段402或第三階段406結束時沉積。DBR 606為由具有變化折射率或藉由例如介電質之厚度之一些特徵的週期性變化以引起有效折射率之週期性變化之交替材料之多個層形成的結構。舉例而言，介電質塗層之此等薄層可為氧化矽、氟化鎂、五氧化鉭、硫化鋅以及二氧化鈦之組合。化合物晶圓502之頂部表面上之氧化矽SiOx層亦可充當隨後使用諸如ZiBond®或DBI®方法之直接接合技術直接接合至晶圓504之塗層的最後一層。Optical reflective coatings such as distributed Bragg reflector (DBR) 606 (not shown to a relative scale) can be deposited by selecting the interface between thefirst wafer 502 and the second wafer 504 (606) The different types and thicknesses of the dielectric layer on the top of thewafer 502 are used to increase the light output of the package. Alternatively, theDBR 606 can also be formed on the top of thesecond wafer 504 before bonding. In this orientation ofDBR 606, light can escape from the sapphire side of the device. If theDBR 606 is formed on thefirst wafer 502, the thin dielectric needs to be deposited at the end of thesecond stage 402 or thethird stage 406 of the method shown in FIG. TheDBR 606 is a structure formed of multiple layers of alternating materials having a varying refractive index or periodic changes in some characteristics, such as the thickness of a dielectric, to cause periodic changes in the effective refractive index. For example, these thin layers of the dielectric coating can be a combination of silicon oxide, magnesium fluoride, tantalum pentoxide, zinc sulfide, and titanium dioxide. The silicon oxide SiOx layer on the top surface of thecompound wafer 502 can also serve as the last layer of the coating that is subsequently directly bonded to thewafer 504 using direct bonding techniques such as ZiBond® or DBI® methods.

在另一具體實例中，DBR可於藍寶石與n-GaN之間處形成。在此定向中，光將朝向CMOS晶圓504反射。然而，歸因於CMOS晶片將阻礙逸出路徑，將逸出較少量的光。In another specific example, the DBR can be formed between sapphire and n-GaN. In this orientation, the light will reflect towards theCMOS wafer 504. However, due to the CMOS wafer will obstruct the escape path, a smaller amount of light will escape.

在圖7中，薄膜電晶體(thin-film transistor；TFT)底板可經薄化702，該薄化702可藉由ZiBond®牌直接接合方法來促進。隨後，經薄化底板之無電晶體部分704亦可經蝕刻掉。在此具體實例中，一或多個n接觸點108及p接觸點110之位置可經設計以使得其可在底板之蝕刻之後自背側暴露；且從而可經接觸以用於與背側之電力傳遞。In FIG. 7, the thin-film transistor (TFT) substrate can be thinned 702, and the thinning 702 can be facilitated by the ZiBond® brand direct bonding method. Subsequently, theelectroless crystal portion 704 of the thinned bottom plate can also be etched away. In this specific example, the position of one or more n-contact points 108 and p-contact points 110 can be designed so that they can be exposed from the back side after etching of the substrate; and thus can be contacted for contact with the back side Power delivery.

在圖8中，經薄化及蝕刻之電晶體表面可使用聚醯亞胺(polyimide；PI)層802或用於保護之任何其他介電材料來塗佈。In FIG. 8, the thinned and etched surface of the transistor can be coated with a polyimide (PI)layer 802 or any other dielectric material for protection.

在圖9中，可對藍寶石基板層100執行雷射剝離，且晶圓502之此經暴露側隨後使用可撓有機基板902來塗佈。In FIG. 9, laser lift-off can be performed on thesapphire substrate layer 100, and the exposed side of thewafer 502 is then coated with a flexibleorganic substrate 902.

在另一具體實例中，用以由電晶體底板藉由PI蝕刻且回填之方法可在藍寶石基板層100之雷射剝離之前省略。在此具體實例中，可能在底板中需要一或多個貫穿電極以用於對電極之電力傳遞。In another specific example, the method for etching and backfilling from the transistor substrate by PI can be omitted before the laser stripping of thesapphire substrate layer 100. In this specific example, one or more through electrodes may be required in the bottom plate for power transmission to the electrodes.

圖10展示於建立有直接接合的實例透明且可撓之mLED陣列顯示器500之所有側上之可用的可操作通路。此變通性至少部分地由於可能使用諸如DBI®及ZiBond®牌接合方法之直接接合的較強接合，該直接接合導致最終結構能夠耐受於結構500之多個側上之其他處理。舉例而言，除剝離透明(例如藍寶石)基板100以使得可撓顯示器500接合至可撓有機基板902以外，可應用後研磨且執行進一步剝離以使得顯示器更薄、更透明且更可撓。Figure 10 shows the operable pathways available on all sides of an example transparent and flexiblemLED array display 500 with direct bonding established. This flexibility is due at least in part to the possible use of stronger bonding such as direct bonding such as DBI® and ZiBond® brand bonding methods, which results in the final structure being able to withstand other processing on multiple sides of thestructure 500. For example, in addition to peeling the transparent (e.g. sapphire)substrate 100 to bond theflexible display 500 to the flexibleorganic substrate 902, post-grinding may be applied and further peeling may be performed to make the display thinner, more transparent, and more flexible.

可將mLED陣列顯示器500之背側添加至具有背側堆積層1002上以用於其他3D整合以附接至記憶體、印刷電路板(printed circuit board；PCB)、觸覺及其他感測器等等。The backside of themLED array display 500 can be added to thebackside stacking layer 1002 for other 3D integration for attachment to memory, printed circuit board (PCB), tactile and other sensors, etc. .

可將一或多個光波導1004整合於透明基板902之頂部上以自LED元件傳輸光信號，且亦可添加用於電信號之線路。在一實施方案中，一或多個光波導1004藉由直接接合技術附接至實例LED陣列顯示器500。One or moreoptical waveguides 1004 can be integrated on the top of thetransparent substrate 902 to transmit optical signals from the LED element, and circuits for electrical signals can also be added. In one implementation, one or moreoptical waveguides 1004 are attached to the exampleLED array display 500 by direct bonding technology.

在實例mLED陣列顯示器500之側上，可添加邊緣發射組態1006，及/或該些側上之類似於頂部上之一或多個光波導1004的光波導。在此具體實例中，可能在LED裝置200之兩側上需要反射器，在層902處，以及在直接接合(例如ZiBond^®)介面604/606處。On the sides of the examplemLED array display 500,edge emission configurations 1006 can be added, and/or optical waveguides on these sides similar to one or moreoptical waveguides 1004 on the top. In this particular example, the LED apparatus may be required on both sides of thereflector 200. Inlayer 902, and the direct bonding (ZiBond^®, for example) at theinterface 604/606.

實例mLED陣列顯示器500之結構實現例如用於太陽能電池及太陽能電池板之化合物半導體之多接面堆疊。The structure of the examplemLED array display 500 realizes, for example, multi-junction stacking of compound semiconductors for solar cells and solar panels.

實例mLED陣列顯示器500之側亦可容納冷卻結構1008。The side of the examplemLED array display 500 can also accommodate acooling structure 1008.

如在圖8中，在移除藍寶石層100之後，表面可變粗糙且添加氧化銦錫(indium tin oxide；ITO)以改良LED之電導率。As in FIG. 8, after thesapphire layer 100 is removed, the surface can be roughened and indium tin oxide (ITO) is added to improve the conductivity of the LED.

剛剛上文所描述且說明之實例步驟提供直接接合的發光二極體(light emitting diode；LED)陣列500，例如mLED之陣列，其中例如在晶圓級方法中，第III至第V族半導體元件直接接合至LED驅動器電路。經由直接接合方法形成之陣列500可為可撓的，且具有光學透明表面。The example steps described and illustrated just above provide a direct-bonded light emitting diode (LED)array 500, such as an array of mLEDs, where, for example, in a wafer-level method, Group III to Group V semiconductor devices Directly connect to the LED driver circuit. Thearray 500 formed by the direct bonding method may be flexible and have an optically transparent surface.

一般而言，基於實例化合物半導體之LED陣列裝置500經形成以具有由共面金屬區域及介電質區域組成之平面表面。共面金屬區域電連接至每一LED元件之化合物半導體之激活區域。Generally speaking, theLED array device 500 based on the example compound semiconductor is formed to have a planar surface composed of coplanar metal regions and dielectric regions. The coplanar metal region is electrically connected to the active region of the compound semiconductor of each LED element.

上文基於化合物半導體之LED陣列結構500可包括與以直接接合方式連接之基於CMOS之裝置的接合。基於化合物半導體之LED陣列裝置500之金屬區域及介電質區域可直接接合至基於CMOS之裝置的各別金屬區域及介電質區域。雖然對晶圓級方法進行描述，但圖5至圖9之實例方法仍不僅可用於晶圓至晶圓(wafer-to-wafer；W2W)方法，且亦可用於晶粒至晶粒(die-to-die；D2D)，或一或多個晶粒至晶圓(dies-to-wafer；D2W)方法。The above compound semiconductor-basedLED array structure 500 may include bonding with CMOS-based devices connected in a direct bonding manner. The metal region and the dielectric region of the compound semiconductor-basedLED array device 500 can be directly bonded to the respective metal region and the dielectric region of the CMOS-based device. Although the wafer-level method is described, the example methods in FIGS. 5-9 can be used not only for wafer-to-wafer (W2W) methods, but also for die-to-die (die-to-wafer) methods. to-die; D2D), or one or more dies-to-wafer (D2W) methods.

所得實例LED陣列結構500亦可具有其他特性及特徵：所得LED陣列結構500可缺少基於第III至第V族之半導體發光裝置生長之基板。此外，基於第III至第V族半導體之發光裝置之微觀結構的表面可有利地粗糙化以用於改良之光提取。The resulting exampleLED array structure 500 may also have other characteristics and features: The resultingLED array structure 500 may lack a substrate based on the growth of semiconductor light-emitting devices of groups III to V. In addition, the surface of the microstructure of light-emitting devices based on Group III to Group V semiconductors can be advantageously roughened for improved light extraction.

用於經由諸如DBI®牌直接接合方法之直接接合方法電連接至n-GaN 102及p-GaN 104激活區域之電極形狀可經專門設計，諸如用於n-GaN 102區域之電極或接觸點108的框追蹤點陣列，及用於p-GaN 104區域之電極或接觸點110的圓形或方形區域中之點陣列。The shape of electrodes used to electrically connect to the active regions of n-GaN 102 and p-GaN 104 via direct bonding methods such as DBI® brand direct bonding methods can be specially designed, such as electrodes orcontact points 108 for n-GaN 102 regions The frame tracking point array is used in the p-GaN 104 area, and the dot array in the circular or square area of the electrode orcontact point 110 is used.

實例方法Instance method

圖11展示製造直接接合LED結構之實例方法1100。在流程圖中，實例方法1100之操作展示於獨立區塊中。Figure 11 shows anexample method 1100 for manufacturing a directly bonded LED structure. In the flowchart, the operations of theexample method 1100 are shown in separate blocks.

在區塊1102處，LED結構經製造以具有在包含LED結構之平面接合介面之第一表面上共面的p型與n型半導體元件之電接觸點。Atblock 1102, the LED structure is manufactured to have electrical contacts of p-type and n-type semiconductor elements that are coplanar on the first surface including the planar bonding interface of the LED structure.

在區塊1104處，第一表面直接接合至包含用於LED結構之驅動器電路之平面接合介面的第二表面。Atblock 1104, the first surface is directly bonded to the second surface including the planar bonding interface of the driver circuit for the LED structure.

用於實例方法1100中之直接接合操作(諸如ZiBond®或DBI®牌直接接合方法)可以晶圓級、單晶片級或晶片陣列級方法塗佈。The direct bonding operations used in the example method 1100 (such as ZiBond® or DBI® brand direct bonding methods) can be applied at the wafer level, single wafer level, or wafer array level methods.

在本說明書及所附申請專利範圍中：術語「連接(connect/connection/connected)」、「與…相連接」及「連接(connecting)」用以意謂「與…直接連接」或「經由一或多個元件與…相連接」。術語「耦接(couple/coupling/coupled)」、「耦接至一起」及「與…耦接」用以意謂「直接地耦接至一起」或「經由一或多個元件耦接至一起」。In the scope of this specification and the attached patent application: the terms "connect/connection/connected", "connected with" and "connecting" are used to mean "directly connected with" or "via a connection". Or multiple components are connected with...". The terms "couple/coupling/coupled", "coupled together" and "coupled with" are used to mean "directly coupled together" or "coupled together via one or more elements" ".

儘管本揭示已對有限數目之具體實例進行揭示，但受益於本發明之熟習此項技術者將瞭解，本說明書所給定之多個修改及變化為可能的。意欲所附申請專利範圍涵蓋如在本揭示之真實精神及範圍內的此類修改及變化。Although the present disclosure has disclosed a limited number of specific examples, those skilled in the art who benefit from the present invention will understand that many modifications and changes given in this specification are possible. It is intended that the scope of the attached patent application covers such modifications and changes as within the true spirit and scope of this disclosure.