TWI700892B - Voltage synchronous control circuit and voltage read control system including the same - Google Patents

Abstract

The invention discloses a voltage synchronization control circuit, it comprising a read start pulse detection module, a first byte reading finish pulse detection module, a second byte reading finish pulse detection module, a reading signal computing module, a flag module, and a updating control module. The read start pulse detection module generates a first output signal. The first byte read finish pulse detection module generates a first byte read finish flag signal. The second byte read finish pulse detection module generates a second byte read finish flag signal. The read signal computing module generates a read start pulse signal and a read finish flag signal. The flag module generates a hold flag signal. The updating control module generates a third output signal and a fourth output signal.

Description

Translated fromChinese

電壓同步控制電路及包含其之電壓讀取控制系統Voltage synchronization control circuit and voltage reading control system containing the same

本發明是有關於一種控制電路及包含其之控制系統，特別是有關於一種電壓同步控制電路及包含其之電壓讀取控制系統。The present invention relates to a control circuit and a control system including it, and more particularly to a voltage synchronization control circuit and a voltage reading control system including it.

在過去各種電子裝置的溝通或連接都需要依照相對應的傳輸線，且在充電或供電上，也需要相對應的線材，所以隨著時間的累積，科技的進步，線材以及供電配件會不斷地更新以及淘汰，造成資源的浪費以及環保的問題，而USB-IF協會推出了一個將資料傳輸以及電力傳輸合為一體的規範，就是USB Type-C規格以及USB Power Delivery規範。為了符合這兩項技術的規格，相對應的硬體規格也產生出來了，此類產品又分為兩類USB-PD Controllers和TCPC。In the past, the communication or connection of various electronic devices required corresponding transmission lines, and corresponding wires were required for charging or power supply. Therefore, with the accumulation of time and technological advancement, the wires and power supply accessories will be constantly updated And elimination, resulting in waste of resources and environmental issues, and the USB-IF Association has launched a specification that integrates data transmission and power transmission, which is the USB Type-C specification and the USB Power Delivery specification. In order to comply with the specifications of these two technologies, corresponding hardware specifications have also been produced. Such products are divided into two types of USB-PD Controllers and TCPC.

以TCPC(Type-C Port Controller)基礎實現含有USB Type-C及USB PD規格的系統上，會含有TCPM(Type-C Port Manager)和TCPC(Type-C Port Controller)兩個區塊，以及TCPCI(Type-C Port Controller Interface)介面。TCPM在系統上屬於Master，PD中屬於應用層，用來判斷PD的資訊及處理所接收到的資訊；TCPC在系統上屬於Slave，PD中屬於實體層，用來傳接PD資料的物理訊號，但除了PD資料的處理，還會控制或判斷Type-C實體端口上的訊號。而TCPCI是使用I2C protocol，來當作兩者之間的橋樑，I2C protocol具有可掛載多個Device的優點。Based on TCPC (Type-C Port Controller) to realize the system with USB Type-C and USB PD specifications, there will be two blocks, TCPM (Type-C Port Manager) and TCPC (Type-C Port Controller), and TCPCI (Type-C Port Controller Interface) interface. TCPM belongs to the Master in the system, and the PD belongs to the application layer, which is used to determine the information of the PD and process the received information; TCPC belongs to the Slave in the system, and the PD belongs to the physical layer, which is used to transmit the physical signal of PD data. But in addition to PD data processing, it also controls or judges the signal on the Type-C physical port. TCPCI uses the I2C protocol as a bridge between the two. The I2C protocol has the advantage of being able to mount multiple devices.

TCPC的硬體規格上會有許多暫存器，有分為狀態、控制、封包傳遞、VBUS電壓等暫存器類別，例如：POWER_STATUS、POWER_CONTROL、TRAMSMIT_BUFFER、RECEIVE_BUFFER、VBUS_VOLTAGE…等，暫存器是透過I2C Protocol做讀取寫入的動作。在TCPC系統應用上，TCPM與TCPC透過I2C做溝通，每次資料的溝通都是一方傳送8位元的資料後，另一方會回傳一個ACK代表傳輸成功，若回傳NACK代表失敗。There are many registers in the hardware specifications of TCPC, which are divided into categories such as status, control, packet transfer, VBUS voltage, etc., such as: POWER_STATUS, POWER_CONTROL, TRANSMIT_BUFFER, RECEIVE_BUFFER, VBUS_VOLTAGE... etc. The register is through I2C Protocol does read and write operations. In the TCPC system application, TCPM and TCPC communicate through I2C. Each time one party transmits 8-bit data, the other party will return an ACK to indicate a successful transmission. If a NACK is returned, it indicates a failure.

VBUS_VOLTAGE的數值代表著Type-C的VBUS電壓大小，這個類比電壓會透過ADC電路轉成數位數值10位元的數值。但因為TCPC硬體的暫存器寬度為8位元，所以整筆資料會分別存放於兩個暫存器，在此將它們分別命名為VBUS_VOL_HBYTE_REG及VBUS_VOL_LBYTE_REG，前面2個位元存放於VBUS_VOL_HBYTE_REG，後面8個位元存放於VBUS_VOL_LBYTE_REG，且隨著VBUS電壓的變化，會更新這兩個暫存器的值。所以當TCPM要讀取VBUS_VOLTAGE資料時，會先讀取VBUS_VOL_LBYTE_REG，後讀取VBUS_VOL_HBYTE_REG，當讀取前面一個暫存器時，後面的暫存器有機會因為VBUS電壓的變化而改變，使得讀取到的數值與理想的數值不同步，使得讀取的資料會有極大的誤差，造成系統的錯誤。The value of VBUS_VOLTAGE represents the VBUS voltage of Type-C. This analog voltage will be converted into a digital value of 10 bits through the ADC circuit. However, because the register width of the TCPC hardware is 8 bits, the entire data will be stored in two registers respectively. Here, they are named VBUS_VOL_HBYTE_REG and VBUS_VOL_LBYTE_REG. The first two bits are stored in VBUS_VOL_HBYTE_REG, and theback 8 bits are stored in VBUS_VOL_LBYTE_REG, and as the VBUS voltage changes, the values of these two registers will be updated. So when TCPM wants to read VBUS_VOLTAGE data, it will read VBUS_VOL_LBYTE_REG first, and then VBUS_VOL_HBYTE_REG. When reading the previous register, the latter register may change due to the change of VBUS voltage, making it read The value of is not synchronized with the ideal value, so that the read data will have a great error, causing system errors.

有鑑於上述習知之問題，本發明的目的在於提供一種電壓同步控制電路及包含其之電壓讀取控制系統，用以解決習知技術中所面臨之問題。In view of the above-mentioned conventional problems, the purpose of the present invention is to provide a voltage synchronization control circuit and a voltage reading control system including the same to solve the problems faced by the conventional technology.

上述目的，本發明係揭露一種電壓同步控制電路，包含讀取起始脈衝偵測模組、第一位元組讀取完成脈衝偵測模組、第二位元組讀取完成脈衝偵測模組、讀取訊號運算模組、旗標模組及更新控制模組。讀取起始脈衝偵測模組接收第一位元組讀取起始脈衝訊號及第二位元組讀取起始脈衝訊號，並且據以產生第一輸出訊號。第一位元組讀取完成脈衝偵測模組接收第一位元組讀取完成脈衝訊號，並且據以產生第一位元組讀取完成旗標訊號。第二位元組讀取完成脈衝偵測模組接收第二位元組讀取完成脈衝訊號，並且據以產生第二位元組讀取完成旗標訊號。讀取訊號運算模組連接讀取起始脈衝偵測模組、第一位元組讀取完成脈衝偵測模組及第二位元組讀取完成脈衝偵測模組，且接收第一輸出訊號、第一位元組讀取完成旗標訊號、第二位元組讀取完成旗標訊號及第一讀取時限訊號，並且據以產生讀取起始脈衝訊號及讀取完成旗標訊號。旗標模組連接讀取訊號運算模組，且接收讀取起始脈衝訊號及讀取完成旗標訊號，並且據以產生保留旗標訊號。更新控制模組連接旗標模組，且接收保留旗標訊號、量測結果訊號、量測完成脈衝訊號、第三輸入訊號及第四輸入訊號，並且產生第三輸出訊號及第四輸出訊號。For the above objective, the present invention discloses a voltage synchronization control circuit, which includes a read start pulse detection module, a first byte read completion pulse detection module, and a second byte read completion pulse detection module Group, read signal operation module, flag module and update control module. The read start pulse detection module receives the first byte read start pulse signal and the second byte read start pulse signal, and generates a first output signal accordingly. The first byte read is completed The pulse detection module receives the first byte readTake the completion pulse signal, and generate the first byte read completion flag signal accordingly. The second byte read completion pulse detection module receives the second byte read completion pulse signal, and generates a second byte read completion flag signal accordingly. The read signal operation module is connected to the read start pulse detection module, the first byte read completed pulse detection module and the second byte read completed pulse detection module, and receive the first output Signal, the first byte read completion flag signal, the second byte read completion flag signal and the first read time limit signal, and the read start pulse signal and read completion flag signal are generated accordingly . The flag module is connected to the read signal operation module, and receives the read start pulse signal and the read complete flag signal, and generates a reserved flag signal accordingly. The update control module is connected to the flag module, and receives the reserved flag signal, the measurement result signal, the measurement completion pulse signal, the third input signal and the fourth input signal, and generates the third output signal and the fourth output signal.

較佳地，讀取起始脈衝偵測模組包含第一或閘，接收第一位元組讀取起始脈衝訊號，以及接收第二位元組讀取起始脈衝訊號，並且據以產生第一輸出訊號。Preferably, the read start pulse detection module includes a first OR gate, receives the first byte read start pulse signal, and receives the second byte read start pulse signal, and generates The first output signal.

較佳地，第一位元組讀取完成脈衝偵測模組包含第一多工器、第二多工器及第一正反器。第一多工器之輸入端接收第一高電位，另一第一多工器之輸入端接收第一位元組讀取完成旗標訊號，以及第一選擇輸入端接收第一位元組讀取完成脈衝訊號，並且據以產生第一多工器輸出訊號。第二多工器連接第一多工器，第二多工器之輸入端接收第二低電位，另一第二多工器之輸入端接收第一多工器輸出訊號，讀取訊號運算模組依據讀取起始脈衝訊號及第一讀取時限訊號產生第二輸出訊號，第二選擇輸入端接收第二輸出訊號，並且據以產生第二多工器輸出訊號。第一正反器連接第二多工器，且第一正反器接收第二多工器輸出訊號，並且據以產生第一位元組讀取完成旗標訊號。Preferably, the first byte read completion pulse detection module includes a first multiplexer, a second multiplexer and a first flip-flop. The input terminal of the first multiplexer receives the first high potential, the input terminal of the other first multiplexer receives the first byte read completion flag signal, and the first selection input terminal receives the first byte read The completion pulse signal is taken, and the first multiplexer output signal is generated accordingly. The second multiplexer is connected to the first multiplexer, the input end of the second multiplexer receives the second low level, the input end of the other second multiplexer receives the output signal of the first multiplexer, and the signal operation mode is read The group generates a second output signal according to the read start pulse signal and the first read time limit signal, and the second select input terminal receives the second output signal and generates the second multiplexer output signal accordingly. The first flip-flop is connected to the second multiplexer, and the first flip-flop receives the output signal of the second multiplexer and generates the first byte read completion flag signal accordingly.

較佳地，第二位元組讀取完成脈衝偵測模組包含第三多工器、第四多工器及第二正反器。第三多工器之輸入端接收第三高電位，另一第三多工器之輸入端接收第二位元組讀取完成旗標訊號，以及第三選擇輸入端接收第二位元組讀取完成脈衝訊號，並且據以產生第三多工器輸出訊號。第四多工器連接第三多工器，第四多工器之輸入端接收第四低電位，另一第四多工器之輸入端接收第三多工器輸出訊號，讀取訊號運算模組依據讀取起始脈衝訊號及第一讀取時限訊號產生第二輸出訊號，第四選擇輸入端接收第二輸出訊號，並且據以產生第四多工器輸出訊號。第二正反器連接第四多工器，第二正反器接收第四多工器輸出訊號，並且據以產生第二位元組讀取完成旗標訊號。Preferably, the second byte read completion pulse detection module includes a third multiplexer, a fourth multiplexer and a second flip-flop. The input terminal of the third multiplexer receives the third high potential, and the other third multiplexerThe input terminal of the device receives the second byte read completion flag signal, and the third selection input terminal receives the second byte read completion pulse signal, and generates a third multiplexer output signal accordingly. The fourth multiplexer is connected to the third multiplexer, the input end of the fourth multiplexer receives the fourth low level, the input end of the other fourth multiplexer receives the output signal of the third multiplexer, and the signal operation mode is read The group generates a second output signal according to the read start pulse signal and the first read time limit signal, and the fourth select input terminal receives the second output signal, and accordingly generates a fourth multiplexer output signal. The second flip-flop is connected to the fourth multiplexer. The second flip-flop receives the output signal of the fourth multiplexer and generates a second byte read completion flag signal accordingly.

較佳地，讀取訊號運算模組包含第一互斥反或閘、第一及閘、第二或閘及第二及閘。第一互斥反或閘之輸入端接收第一位元組讀取完成旗標訊號，另一第一互斥反或閘之輸入端接收第二位元組讀取完成旗標訊號，並且據以產生第一互斥反或閘輸出訊號。第一及閘連接第一互斥反或閘，第一及閘之輸入端接收第一輸出訊號，另一第一及閘之輸入端接收第一互斥反或閘輸出訊號，並且據以產生讀取起始脈衝訊號。第二或閘連接第一及閘，第二或閘之輸入端接收第一讀取時限訊號，另一第二或閘之輸入端接收讀取起始脈衝訊號，並且據以產生第二輸出訊號。第二及閘，其第二及閘之輸入端接收第一位元組讀取完成旗標訊號，另一第二及閘之輸入端接收第二位元讀取完成旗標訊號，並且據以產生讀取完成旗標訊號。Preferably, the read signal operation module includes a first mutually exclusive OR gate, a first AND gate, a second OR gate, and a second AND gate. The input terminal of the first mutually exclusive OR gate receives the first byte read completion flag signal, and the input terminal of the other first mutex OR gate receives the second byte read completion flag signal, and according to To generate the first mutually exclusive inverted OR output signal. The first and gate is connected to the first mutual exclusion or gate, the input of the first and gate receives the first output signal, and the input of the other first and gate receives the first mutual exclusion or gate output signal, and generates accordingly Read the start pulse signal. The second OR gate is connected to the first and gate, the input terminal of the second OR gate receives the first reading time limit signal, and the input terminal of the other second OR gate receives the reading start pulse signal and generates a second output signal accordingly . The second and gate, the input terminal of the second and gate receives the first byte read completion flag signal, and the input of the other second and gate receives the second bit read completion flag signal, and accordingly Generate a read completion flag signal.

較佳地，旗標模組包含第五多工器、第六多工器、第三正反器、第一時限計數器及第三或閘。第五多工器之輸入端接收第五高電位，另一第五多工器之輸入端接收保留旗標訊號，以及第五選擇輸入端接收讀取起始脈衝訊號，並且據以產生第五多工器輸出訊號。第六多工器連接第五多工器，第六多工器之輸入端接收第六低電位，另一第六多工器之輸入端接收第五多工器輸出訊號，以及第六選擇輸入端接收第五輸出訊號，並且據以產生第六多工器輸出訊號。第三正反器連接第六多工器，第三正反器接收第六多工器輸出訊號，並且據以產生保留旗標訊號。第一時限計數器連接第三正反器，第一時限計數器接收保留旗標訊號，並且據以產生第二讀取時限訊號。第三或閘連接第一時限計數器及第六多工器，第三或閘之輸入端接收第二讀取時限訊號，另一第三或閘之輸入端接收讀取完成旗標訊號，並且據以產生第五輸出訊號。Preferably, the flag module includes a fifth multiplexer, a sixth multiplexer, a third flip-flop, a first time limit counter, and a third OR gate. The input terminal of the fifth multiplexer receives the fifth high potential, the input terminal of the other fifth multiplexer receives the reserved flag signal, and the fifth select input terminal receives the read start pulse signal, and accordingly generates the fifth The multiplexer output signal. The sixth multiplexer is connected to the fifth multiplexer, the input of the sixth multiplexer receives the sixth low level, the input of the other sixth multiplexer receives the fifth multiplexer output signal, and the sixth selection input The terminal receives the fifth output signal and generates a sixth multiplexer output signal accordingly. The third flip-flop is connected to the sixth multiplexer, and the third flip-flop receives the output signal of the sixth multiplexer, andAnd based on this, a reserved flag signal is generated. The first time limit counter is connected to the third flip-flop. The first time limit counter receives the reserved flag signal and generates a second read time limit signal accordingly. The third OR gate is connected to the first time limit counter and the sixth multiplexer. The input terminal of the third OR gate receives the second read time limit signal, and the input terminal of the other third OR gate receives the read completion flag signal, and the data To generate the fifth output signal.

較佳地，更新控制模組包含第一蘊含非閘、第七多工器及第八多工器。第一蘊含非閘接之輸入端接收量測完成脈衝訊號，另一第一蘊含非閘接之輸入端接收保留旗標訊號，並且據以產生更新脈衝訊號。第七多工器連接第一蘊含非閘，第七多工器之輸入端接收量測結果訊號，另一第七多工器之輸入端接收第三輸入訊號，以及第七選擇輸入端接收更新脈衝訊號，並且據以產生第三輸出訊號。以及第八多工器連接第一蘊含非閘，第八多工器之輸入端接收量測結果訊號，另一第八多工器之輸入端接收第四輸入訊號，以及第八選擇輸入端接收更新脈衝訊號，並且據以產生第四輸出訊號。Preferably, the update control module includes a first implicit gate, a seventh multiplexer and an eighth multiplexer. The first input terminal with non-gate connection receives the measurement completion pulse signal, and the other input terminal with non-gate connection receives the reserved flag signal, and accordingly generates an update pulse signal. The seventh multiplexer is connected to the first non-gate, the input of the seventh multiplexer receives the measurement result signal, the input of the other seventh multiplexer receives the third input signal, and the seventh selection input receives the update Pulse signal, and generate a third output signal accordingly. And the eighth multiplexer is connected to the first non-gate, the input of the eighth multiplexer receives the measurement result signal, the input of the other eighth multiplexer receives the fourth input signal, and the eighth selection input receives The pulse signal is updated, and the fourth output signal is generated accordingly.

較佳地，本發明也提供一種電壓讀取控制系統，其包含電壓同步控制器、資料解析與傳輸模組、控制器模組、暫存器模組、組態邏輯模組及實體層與應用層模組。其中電壓同步控制器，具有以上提及之電壓同步控制電路，且接收第一位元組讀取起始脈衝訊號、第一位元組讀取完成脈衝訊號、第二位元組讀取起始脈衝訊號、第二位元組讀取完成脈衝訊號、量測結果訊號及量測完成脈衝訊號，並且據以產生第三輸出訊號及第四輸出訊號。資料解析與傳輸模組連接電壓同步控制器，接收至少外部資料需求訊號，據以產生第一位元組讀取起始脈衝訊號、第一位元組讀取完成脈衝訊號、第二位元組讀取起始脈衝訊號及第二位元組讀取完成脈衝訊號。控制器模組連接電壓同步控制器，接收外部類比訊號，且據以產生量測結果訊號及量測完成脈衝訊號。暫存器模組連接電壓同步控制器、資料解析與傳輸模組及控制器模組，且接收第三輸出訊號及第四輸出訊號，暫存器模組儲存第一位元組資料及第二位元組資料，並且據以產生第三輸入訊號及第四輸入訊號。組態邏輯模組連接暫存器模組，且實現使用者命令或偵測外部連結狀態。實體層與應用層模組連接暫存器模組。Preferably, the present invention also provides a voltage reading control system, which includes a voltage synchronization controller, a data analysis and transmission module, a controller module, a register module, a configuration logic module, and a physical layer and application Layer module. The voltage synchronization controller has the voltage synchronization control circuit mentioned above, and receives the first byte read start pulse signal, the first byte read complete pulse signal, and the second byte read start The pulse signal, the second byte read completion pulse signal, the measurement result signal, and the measurement completion pulse signal are used to generate a third output signal and a fourth output signal. The data analysis and transmission module is connected to the voltage synchronization controller to receive at least the external data demand signal, and accordingly generate the first byte read start pulse signal, the first byte read complete pulse signal, and the second byte Read the start pulse signal and the second byte read completion pulse signal. The controller module is connected to the voltage synchronization controller, receives external analog signals, and generates measurement result signals and measurement completion pulse signals accordingly. The register module is connected to the voltage synchronization controller, the data analysis and transmission module and the controller module, and receives the third output signal and the fourth output signal. The register module stores the first byte data and the second Byte data, and according toTo generate the third input signal and the fourth input signal. The configuration logic module is connected to the register module, and realizes user commands or detects external connection status. The physical layer and the application layer module are connected to the register module.

較佳地，暫存器模組之第一位元組資料產生第三輸入訊號。Preferably, the first byte data of the register module generates the third input signal.

較佳地，暫存器模組之第二位元組資料產生第四輸入訊號。Preferably, the second byte data of the register module generates the fourth input signal.

承上所述，本發明之電壓同步控制電路及包含其之電壓讀取控制系統具有以下優點：Based on the above, the voltage synchronization control circuit and the voltage reading control system including it of the present invention have the following advantages:

1.當電壓同步控制器接收到讀取暫存器模組之第一位元組資料時，利用電壓同步控制電路之旗標模組產生保留旗標訊號，且保留旗標訊號之狀態為high狀態，避免第二位元組資料被量測結果訊號更新其資料狀態。1. When the voltage synchronization controller receives the first byte data of the read register module, it uses the flag module of the voltage synchronization control circuit to generate a reserved flag signal, and the state of the reserved flag signal is high State, to prevent the second byte of data from being updated by the measurement result signal.

2.利用電壓同步控制電路之旗標模組內之第一時限計數器，當保留旗標訊號之狀態保持high狀態超過一定時間間隔後，強制將保留旗標訊號之狀態強迫更改成low狀態，讓量測結果訊號可以更新暫存器模組之第一位元組及第二位元組之資料狀態，避免系統之問題。2. Using the first time limit counter in the flag module of the voltage synchronization control circuit, when the state of the reserved flag signal remains high for a certain time interval, the state of the reserved flag signal is forced to change to the low state, so that The measurement result signal can update the data status of the first byte and the second byte of the register module to avoid system problems.

3.利用電壓同步控制電路，暫存器模組之實際值與理想值不會有不同步之問題發生。3. Using the voltage synchronization control circuit, the actual value and ideal value of the register module will not be out of synchronization.

1:第一或閘1: first or gate

1_1:第一位元組讀取起始脈衝訊號1_1: The first byte reads the start pulse signal

1_2:第二位元組讀取起始脈衝訊號1_2: The second byte reads the start pulse signal

2:第一多工器2: The first multiplexer

2_1:第一位元組讀取完成脈衝訊號2_1: The first byte read complete pulse signal

3:第二多工器3: The second multiplexer

4:第一正反器4: The first flip-flop

5:第三多工器5: The third multiplexer

6:第四多工器6: The fourth multiplexer

7:第二正反器7: The second flip-flop

8:第一互斥反或閘8: The first mutually exclusive reverse or gate

9:第一及閘9: First and gate

9_1:讀取起始脈衝訊號9_1: Read the start pulse signal

10:第二或閘10: second or gate

10_1:第一讀取時限訊號10_1: first reading time limit signal

11:第二及閘11: Second and gate

11_1:讀取完成旗標訊號11_1: Reading completed flag signal

12:第五多工器12: Fifth multiplexer

13:第六多工器13: Sixth multiplexer

14:第三正反器14: The third flip-flop

15:第一時限計數器15: The first time limit counter

16:第三或閘16: third or gate

17:第一蘊含非閘17: The first implication is not the gate

18:第七多工器18: Seventh multiplexer

18_1:量測結果訊號18_1: Measurement result signal

19:第八多工器19: Eighth multiplexer

19_1:量測結果訊號19_1: Measurement result signal

100:讀取起始脈衝偵測模組100: Read the start pulse detection module

101:第一位元組讀取完成脈衝偵測模組101: The first byte read completed pulse detection module

102:第二位元組讀取完成脈衝偵測模組102: The second byte read completed pulse detection module

103:讀取訊號運算模組103: Read signal operation module

104:旗標模組104: Flag Module

105:更新控制模組105: Update control module

106:電壓同步控制器106: Voltage Synchronous Controller

107:資料解析與傳輸模組107: Data Analysis and Transmission Module

108:控制器模組108: Controller module

109:暫存器模組109: Register Module

110:組態邏輯模組110: Configuration logic module

111:實體層與應用層模組111: physical layer and application layer modules

200:電壓同步控制電路200: Voltage synchronization control circuit

300:電壓讀取控制系統300: Voltage reading control system

第1圖係為本發明之電壓同步控制電路之方塊圖。Figure 1 is a block diagram of the voltage synchronization control circuit of the present invention.

第2圖係為本發明之電壓同步控制電路之第一電路圖。Figure 2 is the first circuit diagram of the voltage synchronization control circuit of the present invention.

第3圖係為本發明之電壓同步控制電路之第二電路圖。Figure 3 is the second circuit diagram of the voltage synchronization control circuit of the present invention.

第4圖係為本發明之電壓讀取控制系統之方塊圖。Figure 4 is a block diagram of the voltage reading control system of the present invention.

為利瞭解本發明之特徵、內容與優點及其所能達成之功效，茲將本發明配合圖式，並以實施例之表達形式詳細說明如下，而其中所使用之圖式，其主旨僅為示意及輔助說明書之用，未必為本發明實施後之真實比例與精準配置，故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的申請權利範圍。In order to understand the features, content and advantages of the present invention and its achievable effects, the present invention is combined with the drawings and described in detail in the form of an embodiment as follows, and the drawings used therein are:The subject matter is only for the purpose of illustration and auxiliary description, and may not be the true proportions and precise configuration after the implementation of the present invention. Therefore, it should not be interpreted in terms of the proportions and configuration relationships of the attached drawings, and limits the application rights of the present invention in actual implementation. range.

本發明之優點、特徵以及達到之技術方法將參照例示性實施例及所附圖式進行更詳細地描述而更容易理解，且本發明或可以不同形式來實現，故不應被理解僅限於此處所陳述的實施例，相反地，對所屬技術領域具有通常知識者而言，所提供的實施例將使本發明更加透徹與全面且完整地傳達本發明的範疇，且本發明將僅為所附加的申請專利範圍所定義。The advantages, features, and technical methods of the present invention will be described in more detail with reference to the exemplary embodiments and the accompanying drawings to make it easier to understand, and the present invention may be implemented in different forms, so it should not be understood to be limited to these The described embodiments, on the contrary, for those with ordinary knowledge in the technical field, the provided embodiments will make the present invention more thorough and comprehensive and completely convey the scope of the present invention, and the present invention will only be added Is defined by the scope of patent applications.

請參閱第1圖，其係為本發明之電壓同步控制電路200之方塊圖。如圖所示，其以功能劃分本發明之電壓同步控制電路200，且進一步分成六個模組，下述將描述各模組間的連接關係及訊號的輸入與輸出。本發明之同步控制電路包含讀取起始脈衝偵測模組100、第一位元組讀取完成脈衝偵測模組101、第二位元組讀取完成脈衝偵測模組102、讀取訊號運算模組103、旗標模組104及更新控制模組105。其第一位元組對應VBUS_VOLTAGE之低位元組，第二位元組對應VBUS_VOLTAGE之高位元組，讀取起始脈衝偵測模組100接收第一位元組讀取起始脈衝訊號及第二位元組讀取起始脈衝訊號，並且藉由其內部邏輯元件產生第一輸出訊號，其第一輸出訊號對應的訊息為判斷暫存器模組內之第一位元組資料或第二位元組資料之任一資料是否正在讀取，若其任一資料正在讀取，則第一輸出訊號為high狀態(高位準狀態)，否則為low狀態(低位準狀態)。第一位元組讀取完成脈衝偵測模組101接收第一位元組讀取完成脈衝訊號，並且據以產生第一位元組讀取完成旗標訊號，其對應的訊息為，若是第一位元組讀取完成脈衝偵測模組接收到狀態為high(高位準)的第一位元讀取完成脈衝訊號，代表低位元組資料已被讀出，藉由其內部邏輯元件運算，則得到狀態為high之第一位元組讀取完成旗標訊號，否則得到狀態為low(低位準)之第一位元組讀取完成旗標訊號。第二位元組讀取完成脈衝偵測模組102接收第二位元組讀取完成脈衝訊號，並且據以產生第二位元組讀取完成旗標訊號，其對應的訊息為，若是第二位元組讀取完成脈衝偵測模組接收到狀態為high的第二位元讀取完成脈衝訊號，代表高位元組資料已被讀出，藉由其內部邏輯元件運算，則得到狀態為high之第二位元組讀取完成旗標訊號，否則得到狀態為low之第二位元組讀取完成旗標訊號。讀取訊號運算模組103連接讀取起始脈衝偵測模組100、第一位元組讀取完成脈衝偵測模組101及第二位元組讀取完成脈衝偵測模組102，且接收第一輸出訊號、第一位元組讀取完成旗標訊號、第二位元組讀取完成旗標訊號及第一讀取時限訊號，並且據以產生讀取起始脈衝訊號及讀取完成旗標訊號，其對應的訊息為，若是低位元組資料及高位元組資料皆被讀出，藉由內部邏輯元件運算，則得到狀態為high之讀取完成旗標訊號，代表VBUS_VOLTAGE已被完整讀出，否則得到狀態為low之讀取完成旗標訊號。利用第一輸出訊號、第一位元組讀取完成旗標訊號及第二位元組讀取完成旗標訊號，藉由內部邏輯元件運算還能得到另一個訊息，若是低位元組資料與高位元組資料皆被完整讀出或皆未被完整讀出，且第一輸出訊號之狀態代表低位元組資料或高位元組資料之中至少有一資料正在進行讀取動作，則得到狀態為high之讀取起始脈衝訊號，否則得到狀態為low之讀取起始脈衝訊號。旗標模組104連接讀取訊號運算模組103，且接收讀取起始脈衝訊號及讀取完成旗標訊號，並且據以產生保留旗標訊號，其對應的訊息為，若讀取起始脈衝訊號之狀態為high，且讀取完成旗標訊號之狀態為low時，則得到狀態為high之保留旗標訊號，否則得到狀態為low之保留旗標訊號，但是當保留旗標訊號維持high之狀態超過一定時間間隔，內部之邏輯元件將使其訊號改變為low狀態。更新控制模組105連接旗標模組104，且接收保留旗標訊號、量測結果訊號、量測完成脈衝訊號、第三輸入訊號及第四輸入訊號，並且產生第三輸出訊號及第四輸出訊號，其對應的訊息為，若保留旗標訊號之狀態為high，則不論量測結果訊號及量測完成脈衝訊號為何，得到狀態為low之第三輸出訊號及第四輸出訊號，代表低位元組資料及高位元組資料皆不會被量測結果訊號寫入。Please refer to FIG. 1, which is a block diagram of the voltagesynchronization control circuit 200 of the present invention. As shown in the figure, it divides the voltagesynchronization control circuit 200 of the present invention by function, and is further divided into six modules. The connection relationship between the modules and the signal input and output will be described below. The synchronization control circuit of the present invention includes a read start pulse detection module 100, a first byte read completion pulse detection module 101, a second byte read completion pulse detection module 102, and a read Thesignal operation module 103, theflag module 104 and the update control module 105. The first byte corresponds to the low byte of VBUS_VOLTAGE, and the second byte corresponds to the high byte of VBUS_VOLTAGE. The read start pulse detection module 100 receives the first byte to read the start pulse signal and the second The byte reads the initial pulse signal, and generates the first output signal by its internal logic element, and the corresponding message of the first output signal is the first byte data or the second bit in the judgment register module Whether any data of the tuple data is being read, if any of the data is being read, the first output signal is in the high state (high level state), otherwise it is in the low state (low level state). The first byte read completion pulse detection module 101 receives the first byte read completion pulse signal, and generates the first byte read completion flag signal accordingly. The corresponding message is, if the first byte read completion flag signal is The one-byte read completion pulse detection module receives the first-bit read completion pulse signal with the state of high (high level), which means that the low-byte data has been read out. Through its internal logic element operation, Then get the first byte read completion flag signal whose status is high, otherwise get the first byte read completion status of low (low level)Flag signal. The second byte read completion pulse detection module 102 receives the second byte read completion pulse signal, and generates a second byte read completion flag signal accordingly, and the corresponding message is, if it is the first byte The two-byte read completion pulse detection module receives the second-bit read completion pulse signal with the state high, which means that the high-byte data has been read out. Through the operation of its internal logic components, the state is obtained The second byte read completion flag signal of high, otherwise, the second byte read completion flag signal of low state is obtained. The readsignal operation module 103 is connected to the read start pulse detection module 100, the first byte read completed pulse detection module 101, and the second byte read completed pulse detection module 102, and Receive the first output signal, the first byte read completion flag signal, the second byte read completion flag signal and the first read time limit signal, and generate a read start pulse signal and read accordingly The completion flag signal, the corresponding message is, if both the low byte data and the high byte data are read, through the internal logic element operation, the read completion flag signal with high status is obtained, which means that VBUS_VOLTAGE has been Read complete, otherwise get the read completion flag signal with low status. Using the first output signal, the first byte read complete flag signal, and the second byte read complete flag signal, another message can be obtained through the operation of internal logic components, if it is low byte data and high byte The tuple data are all read completely or not completely read, and the state of the first output signal represents that at least one of the low-byte data or the high-byte data is being read, and the status is high. Read the start pulse signal, otherwise get the read start pulse signal with low status. Theflag module 104 is connected to the readsignal operation module 103, and receives the read start pulse signal and the read completion flag signal, and generates a reserved flag signal accordingly. The corresponding message is: When the state of the pulse signal is high and the state of the read completion flag signal is low, the reserved flag signal with high state is obtained, otherwise the reserved flag signal with low state is obtained, but when the reserved flag signal remains high If the state exceeds a certain time interval, the internal logic element will change its signal to the low state. The update control module 105 is connected to theflag module 104, and receives the reserved flag signal, the measurement result signal, the measurement completion pulse signal, the third input signal, and the fourth input signal, and generates the third output signal and the fourth output Signal, the corresponding message is, if the status of the flag signal is retainedIf the state is high, regardless of the measurement result signal and the measurement completion pulse signal, the third output signal and the fourth output signal with the state of low will be obtained, which means that the low byte data and high byte data will not be measured. Signal writing.

請參閱第2圖，其係為電壓同步控制電路200之第一電路圖。如圖所示，讀取起始脈衝偵測模組100內具有邏輯元件第一或閘1，其兩個輸入端其中之一個輸入端接收第一位元組讀取起始脈衝訊號1_1，另一個輸入端接收第二位元組讀取起始脈衝訊號1_2，藉由第一或閘1之運算特性，若是第一位元組讀取起始脈衝訊號1_1或第二位元組讀取起始脈衝訊號1_2之中，至少有一個之狀態為high，則輸出狀態為high之第一輸出訊號，代表低位元組資料或高位元組資料至少有一個正在讀取。Please refer to FIG. 2, which is the first circuit diagram of the voltagesynchronization control circuit 200. As shown in the figure, the read start pulse detection module 100 has a logic element first ORgate 1, one of its two input terminals receives the first byte read start pulse signal 1_1, and the other An input terminal receives the second byte to read the start pulse signal 1_2. With the operation characteristics of the first orgate 1, if the first byte reads the start pulse signal 1_1 or the second byte is read At least one of the initial pulse signals 1_2 has a state of high, and the output state of the first output signal is high, which means that at least one of the low-byte data or the high-byte data is being read.

續請參閱第2圖，第一位元組讀取完成脈衝偵測模組101內，具有以下邏輯元件，第一多工器2、連接第一多工器之第二多工器3及連接第二多工器之第一正反器4。下文提到之多工器，皆為二個輸入端搭配一個選擇輸入端之邏輯元件，第一多工器2其中一個輸入端固定接收高電位(high狀態)，另一個輸入端接收第一正反器4輸出訊號，第一選擇輸入端則接收第一位元組讀取完成脈衝訊號2_1，若是第一位元組讀取完成脈衝訊號2_1為high狀態，則第一多工器2輸出訊號為high狀態。第二多工器3其中一個輸入端固定接收低電位(low狀態)，另一個輸入端接收第一多工器2輸出訊號，第二選擇輸入端接收之訊號，則是由上述讀取訊號運算模組103輸出之讀取起始脈衝訊號9_1及其接收來自外部之第一讀取時限訊號10_1，利用讀取訊號運算模組103內部之邏輯元件產生第二輸出訊號。第二多工器3輸出訊號，若第二選擇輸入端之訊號為狀態high，則輸出狀態low。第一正反器4接收第二多工器3輸出訊號，產生第一位元組讀取完成其標訊號。總結來說，第一位元組讀取完成脈衝偵測模組101整體在運作時，其對應的訊號變化為，當第一位元組讀取完成脈衝訊號2_1接收到狀態為high之訊號，且讀取訊號運算模組103輸出之讀取起始脈衝訊號9_1及其接收來自外部之第一讀取時限訊號10_1兩者皆為狀態low之訊號時，第一位元組讀取完成旗標訊號才會變為high狀態，代表低位元組資料已在時限內被完整讀出，且尚未接收到另一個新的讀取起始脈衝訊號9_1。Please continue to refer to Figure 2. The first byte read completed pulse detection module 101 has the following logic components: afirst multiplexer 2, asecond multiplexer 3 connected to the first multiplexer, and connections The first flip-flop 4 of the second multiplexer. The multiplexers mentioned below are all two input terminals with a logic element that selects the input terminal. One of the input terminals of thefirst multiplexer 2 receives a high voltage (high state), and the other input terminal receives the first positive Theinverter 4 outputs the signal, and the first selection input terminal receives the first byte read completion pulse signal 2_1. If the first byte read completion pulse signal 2_1 is in the high state, thefirst multiplexer 2 outputs the signal High state. One of the input terminals of thesecond multiplexer 3 receives a low level (low state), the other input terminal receives the output signal of thefirst multiplexer 2, and the signal received by the second select input terminal is calculated by the above-mentioned read signal The reading start pulse signal 9_1 output by themodule 103 and the first reading time limit signal 10_1 from the outside are used to generate the second output signal by the logic element inside the readingsignal operation module 103. Thesecond multiplexer 3 outputs a signal, and if the signal of the second selection input terminal is in the state high, the output state is low. The first flip-flop 4 receives the output signal of thesecond multiplexer 3 and generates the first byte read completion signal. In summary, when the first byte read complete pulse detection module 101 is operating as a whole, its corresponding signal changes as follows: when the first byte read complete pulse signal 2_1 receives a signal with a high state,And when the read start pulse signal 9_1 output by the readsignal operation module 103 and the first read time limit signal 10_1 received from the outside are both signals of the state low, the first byte read complete flag The signal will change to the high state, which means that the low-byte data has been completely read within the time limit, and another new read start pulse signal 9_1 has not been received.

第二位元組讀取完成脈衝偵測模組102內，具有以下邏輯元件，第三多工器5、連接第三多工器之第四多工器6及連接第四多工器之第二正反器7。第三多工器5其中一個輸入端固定接收高電位(high狀態)，另一個輸入端接收第二正反器7輸出訊號，第三選擇輸入端則接收第二位元組讀取完成脈衝訊號，若是第二位元組讀取完成脈衝訊號為high狀態，則第三多工器5輸出訊號為high狀態。第四多工器6其中一個輸入端固定接收低電位(low狀態)，另一個輸入端接收第三多工器5輸出訊號，第四選擇輸入端接收之訊號，則是由上述讀取訊號運算模組103輸出之讀取起始脈衝訊號9_1及其接收來自外部之第一讀取時限訊號10_1，利用讀取訊號運算模組103內部之邏輯元件產生第二輸出訊號。第四多工器6輸出訊號，若第四選擇輸入端之訊號為狀態high，則輸出狀態low。第二正反器7接收第四多工器6輸出訊號，產生第二位元組讀取完成其標訊號。總結來說，第二位元組讀取完成脈衝偵測模組102整體在運作時，其對應的訊號變化為，當第二位元組讀取完成脈衝訊號接收到狀態為high之訊號，且讀取訊號運算模組103輸出之讀取起始脈衝訊號9_1及其接收來自外部之第一讀取時限訊號10_1兩者皆為狀態low之訊號時，第二位元組讀取完成旗標訊號才會變為high狀態，代表高位元組資料已在時限內被完整讀出，且尚未接收到另一個讀取起始脈衝訊號9_1。The second byte read completed pulse detection module 102 has the following logic elements, the third multiplexer 5, thefourth multiplexer 6 connected to the third multiplexer, and the fourth multiplexer connected to the fourth multiplexer. Two flip-flop 7. One of the input terminals of the third multiplexer 5 receives the high potential (high state), the other input terminal receives the output signal of the second flip-flop 7, and the third selection input terminal receives the second byte read completion pulse signal If the second byte read completion pulse signal is in the high state, the output signal of the third multiplexer 5 is in the high state. One of the input terminals of thefourth multiplexer 6 receives the low potential (low state), the other input terminal receives the output signal of the third multiplexer 5, and the signal received by the fourth selection input terminal is calculated by the above-mentioned read signal The reading start pulse signal 9_1 output by themodule 103 and the first reading time limit signal 10_1 from the outside are used to generate the second output signal by the logic element inside the readingsignal operation module 103. Thefourth multiplexer 6 outputs a signal, and if the signal of the fourth selection input terminal is in the state high, the output state is low. The second flip-flop 7 receives the output signal of thefourth multiplexer 6, and generates the second byte read completion signal. In summary, when the second byte read complete pulse detection module 102 is operating as a whole, its corresponding signal changes as follows: when the second byte read complete pulse signal receives a high signal, and When the read start pulse signal 9_1 output by the readsignal operation module 103 and the first read time limit signal 10_1 received from the outside are both signals of the state low, the second byte read completion flag signal It will change to the high state, which means that the high byte data has been completely read within the time limit, and another read start pulse signal 9_1 has not been received.

讀取訊號運算模組103內，具有以下邏輯元件，第一互斥反或閘8(NXOR)、連接第一互斥反或閘8(NXOR)之第一及閘9、連接第一及閘9之第二或閘10及第二及閘11。第一互斥反或閘8(NXOR)其中一個輸入端接收來自上述第一位元組讀取完成脈衝偵測模組101之第一位元組讀取完成旗標訊號，第一互斥反或閘8(NXOR)另一個輸入端接收來自上述第二位元組讀取完成脈衝偵測模組102之第二位元組讀取完成旗標訊號，且產生第一互斥反或閘8(NXOR)輸出訊號，若第一位元組讀取完成旗標訊號及第二位元組讀取完成旗標訊號皆為high狀態或皆為low狀態，則產生狀態為high之第一互斥反或閘8(NXOR)輸出訊號，否則產生狀態為low之第一互斥反或閘8(NXOR)輸出訊號，其對應之訊息為，若低位元組資料及高位元組資料皆已被完整讀出或皆未被完整讀出，則產生狀態為high之第一互斥反或閘8(NXOR)輸出訊號，否則產生狀態為low之第一互斥反或閘8(NXOR)輸出訊號。第一及閘9之其中一個輸入端接收第一互斥反或閘8輸出訊號，且第一及閘9之另一個輸入端接收來自上述讀取起始脈衝偵測模組100之第一輸出訊號，且產生讀取起始脈衝訊號9_1，若第一互斥反或閘8輸出訊號及第一輸出訊號皆為high狀態，則產生狀態為high之讀取起始脈衝訊號9_1，否則產生狀態為low之讀取起始脈衝訊號9_1，其對應之訊息為，若低位元組資料及高位元組資料皆已被完整讀出或皆未被完整讀出，且接收到低位元組讀取起始脈衝訊號或高位元組讀取起始脈衝訊號，則第一及閘9輸出狀態為high之讀取起始脈衝訊號9_1，否則第一及閘9輸出狀態為low之讀取起始脈衝訊號9_1。第二或閘10之其中一個輸入端接收讀取起始脈衝訊號9_1，且第二或閘10之另一個輸入端接收來自外部之第一讀取時限訊號10_1，產生上述之第二輸出訊號，其對應的訊息為，若在小於第一讀取時限訊號10_1之週期(10毫秒)內，且未接收到狀態為high之讀取起始脈衝訊號9_1，則第二或閘10產生狀態為low之第二輸出訊號，否則第二或閘10產生狀態為high之第二輸出訊號，上述第一位元組讀取完成脈衝偵測模組101之第二多工器3之第二選擇輸入端，及上述第二位元組讀取完成脈衝偵測模組102之第四多工器6之選擇輸入端，兩者接收其第二輸出訊號。第二及閘11之其中一個輸入端接收第一位元組讀取完成旗標訊號，第二及閘11之另一個輸入端接收第二位元組讀取完成旗標訊號，產生讀取完成旗標訊號11_1，其對應的訊息為，當低位元組資料及高位元組資料皆已被完整讀出或皆未被完整讀出，則輸出狀態為high之讀取完成旗標訊號11_1，否則輸出狀態為low之讀取完成旗標訊號11_1。總結來說，讀取訊號運算模組103整體在運作時，其對應的訊號變化為，當低位元組資料及高位元組資料皆已被完整讀出，則輸出狀態為high之讀取完成旗標訊號11_1至旗標模組104，代表有一個VBUS_VOLTAGE已被完整讀出，否則輸出狀態為low之讀取完成旗標訊號11_1至旗標模組104。若是低位元組資料及高位元組資料皆已被完整讀出或皆未被完整讀出，且再接收到來自上述讀取起始脈衝偵測模組100，狀態為high之第一輸出訊號，則輸出狀態為high之讀取起始脈衝訊號9_1至旗標模組104，代表有一個VBUS_VOLTAGE的讀取正在進行，否則輸出狀態為low之讀取起始脈衝訊號9_1至旗標模組104。The readsignal operation module 103 has the following logic elements: the first mutually exclusive OR gate 8 (NXOR), the first ANDgate 9 connected to the first mutually exclusive OR gate 8 (NXOR), and the first AND gate connected 9 of the second orgate 10 and the second andgate 11. One of the input terminals of the first mutex OR gate 8 (NXOR) receives from the aboveThe first byte read completion flag signal of the first byte read completion of the pulse detection module 101, the other input terminal of the first mutually exclusive or gate 8 (NXOR) receives the second byte from the above Read the second byte of the pulse detection module 102 to read the complete flag signal, and generate the first mutually exclusive or gate 8 (NXOR) output signal, if the first byte is read complete the flag signal And the second byte read completion flag signal is both high state or low state, then the first mutex OR gate 8 (NXOR) output signal with high state is generated, otherwise the first with low state is generated Mutually exclusive reverse OR gate 8 (NXOR) output signal, the corresponding message is, if the low byte data and high byte data have been read out completely or neither of them have been read out completely, then the first state of high will be generated Mutually exclusive or gate 8 (NXOR) output signal, otherwise, the first mutually exclusive or gate 8 (NXOR) output signal with low state will be generated. One of the input terminals of thefirst sum gate 9 receives the first mutually exclusive ORgate 8 output signal, and the other input terminal of thefirst sum gate 9 receives the first output from the read start pulse detection module 100 Signal, and generate the read start pulse signal 9_1, if the first mutually exclusive ORgate 8 output signal and the first output signal are both in the high state, the read start pulse signal 9_1 with the state high is generated, otherwise, the state is generated It is the low read start pulse signal 9_1, and the corresponding message is, if the low byte data and high byte data have been read completely or neither have been read completely, and the low byte data is received Start pulse signal or high byte group read start pulse signal, the first andgate 9 output state is high read start pulse signal 9_1, otherwise the first andgate 9 output state is low read start pulse signal 9_1. One of the input terminals of the second ORgate 10 receives the read start pulse signal 9_1, and the other input terminal of the second ORgate 10 receives the first read timing signal 10_1 from the outside to generate the aforementioned second output signal, The corresponding message is, if within a period (10 milliseconds) less than the first read time limit signal 10_1, and the read start pulse signal 9_1 with a high state is not received, the second ORgate 10 generates a low state The second output signal of the second ORgate 10, otherwise, the second output signal of the state of high is generated by the second ORgate 10, and the second selection input terminal of thesecond multiplexer 3 of the pulse detection module 101 with the first byte read completed , And the selection input terminal of thefourth multiplexer 6 of the second byte read completion pulse detection module 102, both of which receive their second output signal. One of the input terminals of the second andgate 11 receives the first byte read completion flag signal, and the second andgate 11The other input terminal receives the second byte read completion flag signal, and generates the read completion flag signal 11_1, the corresponding message is, when the low byte data and high byte data have been read completely or If none is read completely, the read completion flag signal 11_1 with the high state is output, otherwise the read completion flag signal 11_1 with the low state is output. In summary, when the readsignal operation module 103 is operating as a whole, the corresponding signal change is that when the low byte data and high byte data have been read completely, the output status is the read completion flag of high. The flag signal 11_1 to theflag module 104 indicates that a VBUS_VOLTAGE has been read out completely, otherwise the read completion flag signal 11_1 to theflag module 104 whose output status is low is output. If both the low byte data and the high byte data have been read completely or neither have been read completely, and then the first output signal of the state of high from the read start pulse detection module 100 is received, If the output state is high, the read start pulse signal 9_1 to theflag module 104 means that a VBUS_VOLTAGE reading is in progress, otherwise the output state is low read start pulse signal 9_1 to theflag module 104.

請參閱第3圖，其係為電壓同步控制電路200之第二電路圖。如圖所示，旗標模組104內，具有以下元件，第五多工器12、連接第五多工器12之第六多工器13、連接第六多工器之第三正反器14、連接第三正反器之第一時限計數器15及連接第一時限計數器15與第六多工器13之第三或閘16。第五多工器12其中一個輸入端固定接收第五高電位，第五多工器12另一個輸入端接收由第三正反器14輸出之保留旗標訊號，第五選擇輸入端接收來自讀取訊號運算模組103之讀取起始脈衝訊號9_1。若讀取起始脈衝訊號9_1為狀態high，則第五多工器12產生狀態為high之第五多工器輸出訊號。第六多工器13其中一個輸入端固定第六低電位，第六多工器13另一個輸入端接收來自第五多工器12之第五多工器12輸出訊號，第六選擇輸入端接收來自第三或閘16之第五輸出訊號，若第五輸出訊號為狀態high，則第六多工器13輸出狀態為low之第六多工器13輸出訊號。第三正反器14接收第六多工器13輸出訊號，產生保留旗標訊號。第一時限計數器15接收第三正反器14輸出之保留旗標訊號，產生第二讀取時限訊號，若保留旗標訊號維持狀態high之時間間隔超過預設時間(10毫秒)，則第二讀取時限訊號強制更改為狀態low。第三或閘16其中一個輸入端接收第二讀取時限訊號，第三或閘16另一個輸入端接收來自讀取訊號運算模組103之讀取完成旗標訊號，產生上述之第五輸出訊號。總結來說，旗標模組104整體在運作時，其對應的訊號變化為，若來自讀取訊號運算模組103之讀取起始脈衝訊號9_1為狀態high，且第二讀取時限訊號與讀取完成旗標訊號皆為狀態low，則保留旗標訊號為狀態high，否則為狀態low之訊號。Please refer to FIG. 3, which is the second circuit diagram of the voltagesynchronization control circuit 200. As shown in the figure, theflag module 104 has the following components: afifth multiplexer 12, asixth multiplexer 13 connected to thefifth multiplexer 12, and a third flip-flop connected to thesixth multiplexer 14. The firsttime limit counter 15 connected to the third flip-flop and the third ORgate 16 connected to the firsttime limit counter 15 and thesixth multiplexer 13. One input terminal of thefifth multiplexer 12 fixedly receives the fifth high potential, the other input terminal of thefifth multiplexer 12 receives the reserved flag signal output by the third flip-flop 14, and the fifth selection input terminal receives the signal from the read Take the reading start pulse signal 9_1 of thesignal operation module 103. If the read start pulse signal 9_1 is in the high state, thefifth multiplexer 12 generates the fifth multiplexer output signal in the high state. One input terminal of thesixth multiplexer 13 is fixed at the sixth low level, the other input terminal of thesixth multiplexer 13 receives the output signal from thefifth multiplexer 12 of thefifth multiplexer 12, and the sixth selection input terminal receives The fifth output signal from the third ORgate 16, if the fifth output signal is in the high state, thesixth multiplexer 13 outputs the output signal of thesixth multiplexer 13 in the low state. The third flip-flop 14 receives the output signal of thesixth multiplexer 13 and generates a reserved flag signal. The firsttime limit counter 15Receive the reserved flag signal output by the third flip-flop 14 to generate the second read time limit signal. If the time interval for the reserved flag signal to maintain the state high exceeds the preset time (10 milliseconds), the second read time limit signal is forced Change to status low. One of the input terminals of the third ORgate 16 receives the second read time limit signal, and the other input terminal of the third ORgate 16 receives the read completion flag signal from the readsignal operation module 103 to generate the above-mentioned fifth output signal . In summary, when theflag module 104 is operating as a whole, the corresponding signal change is, if the read start pulse signal 9_1 from the readsignal operation module 103 is in the state high, and the second read time limit signal is If the flag signals of the read completion are all in the state low, the flag signal is kept in the state high, otherwise it is the signal in the state low.

續請參閱第3圖，更新控制模組105內，具有以下元件，第一蘊含非閘17，連接第一蘊含非閘17之第七多工器18，連接第一蘊含非閘17之第八多工器19。第一蘊含非閘17其中一個輸入端接收來自旗標模組104之保留旗標訊號，第一蘊含非閘17另一個輸入端接收來自上述控制器模組108之量測完成脈衝訊號，產生更新脈衝訊號。第七多工器18其中一個輸入端接收來自上述控制器模組108之量測結果訊號18_1，第七多工器18另一個輸入端接收來自上述暫存器模組109之儲存第一位元組資料之暫存器產生之第三輸入訊號，第七選擇輸入端接收來自第一蘊含非閘17產生之更新脈衝訊號，產生第三輸出訊號。第八多工器19其中一個輸入端接收來自上述控制器模組108之量測結果訊號19_1，第八多工器19另一個輸入端接收來自上述暫存器模組109之儲存第二位元組資料之暫存器產生之第四輸入訊號，第八選擇輸入端接收來自第一蘊含非閘17產生之更新脈衝訊號，產生第四輸出訊號。總結來說，更新控制模組105整體在運作時，其對應的訊號變化為，只有當保留旗標訊號之狀態為low，且量測完成脈衝訊號狀態為high時，第七多工器18或第八多工器19會將狀態為high之量測結果訊號輸出為第三輸出訊號，其餘情形第三輸出訊號皆為狀態low。Please continue to refer to Figure 3. The update control module 105 has the following components: the first impliednon-gate 17, theseventh multiplexer 18 connected to the first impliednon-gate 17, and the eighth of the first implied non-gate 17Multiplexer 19. One input terminal of thefirst implication non-gate 17 receives the reserved flag signal from theflag module 104, and the other input terminal of thefirst implication non-gate 17 receives the measurement completion pulse signal from thecontroller module 108 to generate an update Pulse signal. One input of theseventh multiplexer 18 receives the measurement result signal 18_1 from thecontroller module 108, and the other input of theseventh multiplexer 18 receives the stored first bit from theregister module 109 The third input signal generated by the register of the group data, the seventh selection input terminal receives the update pulse signal generated from thefirst implication non-gate 17 to generate the third output signal. One input terminal of theeighth multiplexer 19 receives the measurement result signal 19_1 from thecontroller module 108, and the other input terminal of theeighth multiplexer 19 receives the stored second bit from theregister module 109 The fourth input signal generated by the register of the group data, the eighth selection input terminal receives the update pulse signal generated from thefirst implication non-gate 17 to generate the fourth output signal. In summary, when the update control module 105 is operating as a whole, the corresponding signal changes are: only when the state of the reserved flag signal is low and the state of the measurement completion pulse signal is high, theseventh multiplexer 18 or Theeighth multiplexer 19 outputs the measurement result signal whose state is high as the third output signal, and the third output signal is in the state low in other cases.

請參閱第4圖，其係為電壓讀取控制系統300之方塊圖。如圖所示，本發明提供之電壓讀取控制系統300中的電壓同步控制器106包含上述之電壓同步控制電路200，其電壓同步控制器106接收上述資料解析與傳輸模組107產生之第一位元組讀取起始脈衝訊號、第一位元組讀取完成脈衝訊號、第二位元組讀取起始脈衝訊號、第二位元組讀取完成脈衝訊號、控制器模組108產生之量測結果訊號及量測完成脈衝訊號，並且產生第三輸出訊號及第四輸出訊號至暫存器模組109。資料解析與傳輸模組107接收來自上述TCPM傳送之資料需求訊號，產生第一位元組讀取起始脈衝訊號、第一位元組讀取完成脈衝訊號、第二位元組讀取起始脈衝訊號及第二位元組讀取完成脈衝訊號，並且傳送至電壓同步控制器106。控制器模組108接收來自外部的類比訊號，產生量測結果訊號及量測完成脈衝訊號，並且傳送至電壓同步控制器106。暫存器模組109連接電壓同步控制器106、資料解析與傳輸模組107及控制器模組108，其中暫存器模組109內，儲存第一位元組資料及第二位元組資料，其資料的狀態由上述電壓同步控制器106之更新控制模組105輸出的第三輸出訊號及第四輸出訊號來決定。電壓讀取控制系統300還包含實現使用者命令或偵測外部連結狀態之組態邏輯模組110，其連接暫存器模組109及連接暫存器模組109之實體層與應用層模組111。Please refer to FIG. 4, which is a block diagram of the voltage reading control system 300. As shown in the figure, thevoltage synchronization controller 106 in the voltage reading control system 300 provided by the present invention includes the voltagesynchronization control circuit 200 described above, and thevoltage synchronization controller 106 receives the first data generated by the data analysis and transmission module 107. Byte read start pulse signal, first byte read complete pulse signal, second byte read start pulse signal, second byte read complete pulse signal, generated bycontroller module 108 The measurement result signal and measurement completion pulse signal are generated, and the third output signal and the fourth output signal are generated to theregister module 109. The data analysis and transmission module 107 receives the data demand signal sent from the TCPM, and generates the first byte read start pulse signal, the first byte read complete pulse signal, and the second byte read start signal The pulse signal and the second byte group are read to complete the pulse signal and sent to thevoltage synchronization controller 106. Thecontroller module 108 receives an analog signal from the outside, generates a measurement result signal and a measurement completion pulse signal, and transmits it to thevoltage synchronization controller 106. Theregister module 109 is connected to thevoltage synchronization controller 106, the data analysis and transmission module 107, and thecontroller module 108. Theregister module 109 stores the first byte of data and the second byte of data The state of the data is determined by the third output signal and the fourth output signal output by the update control module 105 of thevoltage synchronization controller 106. The voltage reading control system 300 also includes a configuration logic module 110 for implementing user commands or detecting external connection status, which is connected to theregister module 109 and the physical layer and application layer modules of theregister module 109 111.

復請參閱第3圖及第4圖，更新控制模組105之第七多工器18產生之第三輸出訊號，將決定暫存器模組109內儲存第一位元組資料之狀態，而第一位元組資料又成為第三輸入訊號，傳送至第七多工器18之某一個輸入端。Please refer to Figures 3 and 4 again, the third output signal generated by theseventh multiplexer 18 of the update control module 105 will determine the state of the first byte data stored in theregister module 109, and The data of the first bit group becomes the third input signal again, and is sent to a certain input terminal of theseventh multiplexer 18.

更新控制模組105之第八多工器19產生之第三輸出訊號，將決定暫存器模組109內儲存第二位元組資料之狀態，而第二位元組資料又成為第四輸入訊號，傳送至第八多工器19之某一個輸入端。The third output signal generated by theeighth multiplexer 19 of the update control module 105 will determine the state of storing the second byte of data in theregister module 109, and the second byte of data will become the fourth input The signal is sent to an input terminal of theeighth multiplexer 19.

承上所述，本發明之電壓同步控制電路200及包含其之電壓讀取控制系統300具有以下優點：Based on the above, the voltagesynchronization control circuit 200 and the voltage reading control system 300 including it of the present invention have the following advantages:

1.當電壓同步控制器接收到讀取暫存器模組之第一位元組資料時，利用電壓同步控制電路200之旗標模組產生保留旗標訊號，且保留旗標訊號之狀態為high狀態，避免第二位元組資料被量測結果訊號更新其資料狀態。1. When the voltage synchronization controller receives the first byte data of the read register module, it uses the flag module of the voltagesynchronization control circuit 200 to generate a reserved flag signal, and the state of the reserved flag signal is The high state prevents the second byte of data from being updated by the measurement result signal.

2.利用電壓同步控制電路200之旗標模組內之第一時限計數器，當保留旗標訊號之狀態保持high狀態超過一定時間間隔後，強制將保留旗標訊號之狀態強迫更改成low狀態，讓量測結果訊號可以更新暫存器模組之第一位元組及第二位元組之資料狀態，避免系統之問題。2. Using the first time limit counter in the flag module of the voltagesynchronization control circuit 200, when the state of the reserved flag signal remains high for a certain time interval, the state of the reserved flag signal is forcibly changed to the low state. The measurement result signal can update the data status of the first byte and the second byte of the register module to avoid system problems.

3.利用電壓同步控制電路200，暫存器模組之實際值與理想值不會有不同步之問題發生。3. By using the voltagesynchronization control circuit 200, the actual value and the ideal value of the register module will not be out of synchronization.

以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使所屬技術領域具有通常知識者能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。The above-mentioned embodiments are only to illustrate the technical ideas and features of the present invention, and their purpose is to enable those with ordinary knowledge in the technical field to understand the content of the present invention and implement them accordingly. When they cannot be used to limit the patent scope of the present invention , That is, all equal changes or modifications made in accordance with the spirit of the present invention should still be covered by the patent scope of the present invention.

100:讀取起始脈衝偵測模組100: Read the start pulse detection module

101:第一位元組讀取完成脈衝偵測模組101: The first byte read completed pulse detection module

102:第二位元組讀取完成脈衝偵測模組102: The second byte read completed pulse detection module

103:讀取訊號運算模組103: Read signal operation module

104:旗標模組104: Flag Module

105:更新控制模組105: Update control module

200:電壓同步控制電路200: Voltage synchronization control circuit

Claims (10)

Translated fromChinese

一種電壓同步控制電路，其包含：一讀取起始脈衝偵測模組，係接收一第一位元組讀取起始脈衝訊號及一第二位元組讀取起始脈衝訊號，並且據以產生一第一輸出訊號；一第一位元組讀取完成脈衝偵測模組，係接收一第一位元組讀取完成脈衝訊號，並且據以產生一第一位元組讀取完成旗標訊號；一第二位元組讀取完成脈衝偵測模組，係接收一第二位元組讀取完成脈衝訊號，並且據以產生一第二位元組讀取完成旗標訊號；一讀取訊號運算模組，係連接該讀取起始脈衝偵測模組、該第一位元組讀取完成脈衝偵測模組及該第二位元組讀取完成脈衝偵測模組，且接收該第一輸出訊號、該第一位元組讀取完成旗標訊號、該第二位元組讀取完成旗標訊號及一第一讀取時限訊號，並且據以產生一讀取起始脈衝訊號及一讀取完成旗標訊號；一旗標模組，係連接該讀取訊號運算模組，且接收該讀取起始脈衝訊號及該讀取完成旗標訊號，並且據以產生一保留旗標訊號；以及一更新控制模組，係連接該旗標模組，且接收該保留旗標訊號、一量測結果訊號、一量測完成脈衝訊號、一第三輸入訊號及一第四輸入訊號，並且產生一第三輸出訊號及一第四輸出訊號。A voltage synchronization control circuit includes: a read start pulse detection module, which receives a first byte read start pulse signal and a second byte read start pulse signal, and data To generate a first output signal; a first byte read completion pulse detection module, which receives a first byte read completion pulse signal, and generates a first byte read completion accordingly Flag signal; a second byte read completion pulse detection module, which receives a second byte read completion pulse signal, and generates a second byte read completion flag signal accordingly; A read signal operation module connected to the read start pulse detection module, the first byte read completion pulse detection module, and the second byte read completion pulse detection module , And receive the first output signal, the first byte read completion flag signal, the second byte read completion flag signal and a first read time limit signal, and generate a read accordingly A start pulse signal and a read completion flag signal; a flag module is connected to the read signal operation module, and receives the read start pulse signal and the read completion flag signal, and then Generate a reserved flag signal; and an update control module, which is connected to the flag module and receives the reserved flag signal, a measurement result signal, a measurement completion pulse signal, a third input signal and a The fourth input signal, and a third output signal and a fourth output signal are generated.如請求項1所述之電壓同步控制電路，其中該讀取起始脈衝偵測模組包含：一第一或閘，係接收該第一位元組讀取起始脈衝訊號，以及接收該第二位元組讀取起始脈衝訊號，並且據以產生該第一輸出訊號。The voltage synchronization control circuit according to claim 1, wherein the read start pulse detection module includes: a first OR gate that receives the first byte read start pulse signal, and receives the first byte The two-byte group reads the initial pulse signal, and generates the first output signal accordingly.如請求項1所述之電壓同步控制電路，其中該第一位元組讀取完成脈衝偵測模組包含：一第一多工器，該第一多工器之輸入端係接收一第一高電位，另一該第一多工器之輸入端接收該第一位元組讀取完成旗標訊號，以及一第一選擇輸入端接收該第一位元組讀取完成脈衝訊號，並且據以產生一第一多工器輸出訊號；一第二多工器，係連接該第一多工器，該第二多工器之輸入端接收一第二低電位，另一該第二多工器之輸入端接收該第一多工器輸出訊號，該讀取訊號運算模組依據該讀取起始脈衝訊號及該第一讀取時限訊號產生一第二輸出訊號，一第二選擇輸入端接收該第二輸出訊號，並且據以產生一第二多工器輸出訊號；以及一第一正反器，係連接該第二多工器，該第一正反器接收該第二多工器輸出訊號，並且據以產生該第一位元組讀取完成旗標訊號。The voltage synchronization control circuit according to claim 1, wherein the first byte read completion pulse detection module includes: a first multiplexer, and the input terminal of the first multiplexer receives a first High potential, another input terminal of the first multiplexer receives the first byte read completion flag signal, and a first selection input terminal receives the first byte read completion pulse signal, and according to To generate a first multiplexer output signal; a second multiplexer is connected to the first multiplexer, the input end of the second multiplexer receives a second low level, the other the second multiplexer The input terminal of the device receives the output signal of the first multiplexer, and the read signal operation module generates a second output signal according to the read start pulse signal and the first read time limit signal, and a second select input terminal Receiving the second output signal, and generating a second multiplexer output signal accordingly; and a first flip-flop connected to the second multiplexer, the first flip-flop receiving the second multiplexer A signal is output, and the first byte read completion flag signal is generated accordingly.如請求項1所述之電壓同步控制電路，其中該第二位元組讀取完成脈衝偵測模組包含：一第三多工器，該第三多工器之輸入端係接收一第三高電位，另一該第三多工器之輸入端接收該第二位元組讀取完成旗標訊號，以及一第三選擇輸入端接收該第二位元組讀取完成脈衝訊號，並且據以產生一第三多工器輸出訊號；一第四多工器，係連接該第三多工器，該第四多工器之輸入端接收一第四低電位，另一該第四多工器之輸入端接收該第三多工器輸出訊號，該讀取訊號運算模組依據該讀取起始脈衝訊號及該第一讀取時限訊號產生一第二輸出訊號，一第四選擇輸入端接收該第二輸出訊號，並且據以產生一第四多工器輸出訊號；以及一第二正反器，係連接該第四多工器，該第二正反器接收該第四多工器輸出訊號，並且據以產生該第二位元組讀取完成旗標訊號。The voltage synchronization control circuit according to claim 1, wherein the second byte read completion pulse detection module includes: a third multiplexer, and the input end of the third multiplexer receives a third High potential, the input terminal of the other third multiplexer receives the second byte read completion flagSignal, and a third selection input terminal receives the second byte read completion pulse signal, and generates a third multiplexer output signal accordingly; a fourth multiplexer is connected to the third multiplexer , The input terminal of the fourth multiplexer receives a fourth low level, the input terminal of the other fourth multiplexer receives the output signal of the third multiplexer, and the read signal operation module starts according to the read The initial pulse signal and the first read time limit signal generate a second output signal, a fourth selection input terminal receives the second output signal, and accordingly generates a fourth multiplexer output signal; and a second positive and negative The device is connected to the fourth multiplexer. The second flip-flop receives the output signal of the fourth multiplexer and generates the second byte read completion flag signal accordingly.如請求項1所述之電壓同步控制電路，其中該讀取訊號運算模組包含：一第一互斥反或閘，該第一互斥反或閘之輸入端係接收該第一位元組讀取完成旗標訊號，另一該第一互斥反或閘之輸入端接收該第二位元組讀取完成旗標訊號，並且據以產生一第一互斥反或閘輸出訊號；一第一及閘，係連接該第一互斥反或閘，該第一及閘之輸入端接收該第一輸出訊號，另一該第一及閘之輸入端接收該第一互斥反或閘輸出訊號，並且據以產生該讀取起始脈衝訊號；一第二或閘，係連接該第一及閘，該第二或閘之輸入端接收該第一讀取時限訊號，另一該第二或閘之輸入端接收該讀取起始脈衝訊號，並且據以產生一第二輸出訊號；以及一第二及閘，該第二及閘之輸入端係接收該第一位元組讀取完成旗標訊號，另一該第二及閘之輸入端接收該第二位元組讀取完成旗標訊號，並且據以產生該讀取完成旗標訊號。The voltage synchronization control circuit according to claim 1, wherein the read signal operation module includes: a first mutually exclusive OR gate, and the input terminal of the first mutually exclusive OR gate receives the first byte The read completion flag signal is read, and the input terminal of the other first mutually exclusive inverter receives the second byte read completion flag signal, and accordingly generates a first mutually exclusive inverter output signal; The first and gate is connected to the first mutually exclusive OR gate, the input end of the first and gate receives the first output signal, and the input end of the other first and gate receives the first mutually exclusive OR gate Output signal and generate the read start pulse signal accordingly; a second OR gate is connected to the first and gate, the input of the second or gate receives the first read time limit signal, and the other The input terminal of the second OR gate receives the read start pulse signal and generates a second output signal accordingly; andA second sum gate, the input end of the second sum gate receives the first byte read completion flag signal, and the other input end of the second sum gate receives the second byte read completion flag And generate the read completion flag signal accordingly.如請求項1所述之電壓同步控制電路，其中該旗標模組包含：一第五多工器，該第五多工器之輸入端係接收一第五高電位，另一該第五多工器之輸入端接收該保留旗標訊號，以及一第五選擇輸入端接收該讀取起始脈衝訊號，並且據以產生一第五多工器輸出訊號；一第六多工器，係連接該第五多工器，該第六多工器之輸入端接收一第六低電位，另一該第六多工器之輸入端接收該第五多工器輸出訊號，以及一第六選擇輸入端接收一第五輸出訊號，並且據以產生一第六多工器輸出訊號；一第三正反器，係連接該第六多工器，該第三正反器接收該第六多工器輸出訊號，並且據以產生該保留旗標訊號；一第一時限計數器，係連接該第三正反器，該第一時限計數器接收該保留旗標訊號，並且據以產生一第二讀取時限訊號；以及一第三或閘，係連接該第一時限計數器及該第六多工器，該第三或閘之輸入端接收該第二讀取時限訊號，另一該第三或閘之輸入端接收該讀取完成旗標訊號，並且據以產生該第五輸出訊號。The voltage synchronization control circuit according to claim 1, wherein the flag module includes: a fifth multiplexer, the input terminal of the fifth multiplexer receives a fifth high voltage, and the other fifth multiplexer The input terminal of the multiplexer receives the reserved flag signal, and a fifth select input terminal receives the read start pulse signal, and accordingly generates a fifth multiplexer output signal; a sixth multiplexer is connected The input terminal of the fifth multiplexer and the sixth multiplexer receives a sixth low level, and the input terminal of the sixth multiplexer receives the fifth multiplexer output signal, and a sixth selection input The terminal receives a fifth output signal and generates a sixth multiplexer output signal accordingly; a third flip-flop is connected to the sixth multiplexer, and the third flip-flop receives the sixth multiplexer Output signal, and generate the reserved flag signal accordingly; a first time limit counter connected to the third flip-flop, the first time limit counter receives the reserved flag signal, and generates a second read time limit accordingly Signal; and a third OR gate connected to the first time limit counter and the sixth multiplexer, the input end of the third OR gate receives the second read time limit signal, and another input of the third or gate The terminal receives the read completion flag signal, and generates the fifth output signal accordingly.如請求項1所述之電壓同步控制電路，其中該更新控制模組包含：一第一蘊含非閘，該第一蘊含非閘之輸入端係接收該量測完成脈衝訊號，另一該第一蘊含非閘之輸入端接收該保留旗標訊號，並且據以產生一更新脈衝訊號；一第七多工器，係連接該第一蘊含非閘，該第七多工器之輸入端接收該量測結果訊號，另一該第七多工器之輸入端接收該第三輸入訊號，以及一第七選擇輸入端接收該更新脈衝訊號，並且據以產生一第三輸出訊號；以及一第八多工器，係連接該第一蘊含非閘，該第八多工器之輸入端接收該量測結果訊號，另一該第八多工器之輸入端接收該第四輸入訊號，以及一第八選擇輸入端接收該更新脈衝訊號，並且據以產生一第四輸出訊號。The voltage synchronization control circuit according to claim 1, wherein the update control module includes:A first implicit non-gate, the input terminal of the first implicit non-gate receives the measurement completion pulse signal, and the other input terminal of the first implicit non-gate receives the reserved flag signal, and accordingly generates an update pulse Signal; a seventh multiplexer is connected to the first implication gate, the input of the seventh multiplexer receives the measurement result signal, and the input of the other seventh multiplexer receives the third input Signal, and a seventh selection input terminal to receive the update pulse signal, and generate a third output signal accordingly; and an eighth multiplexer connected to the first implicit non-gate, the input of the eighth multiplexer Terminal receives the measurement result signal, another input terminal of the eighth multiplexer receives the fourth input signal, and an eighth selection input terminal receives the update pulse signal and generates a fourth output signal accordingly.一種電壓讀取控制系統，其包含：一電壓同步控制器，係具有如申請專利範圍第1項至第7項之中任一項所述之電壓同步控制電路，且接收該第一位元組讀取起始脈衝訊號、該第一位元組讀取完成脈衝訊號、該第二位元組讀取起始脈衝訊號、該第二位元組讀取完成脈衝訊號、該量測結果訊號及該量測完成脈衝訊號，並且據以產生一第三輸出訊號及一第四輸出訊號；一資料解析與傳輸模組，係連接該電壓同步控制器，接收至少一外部資料需求訊號，據以產生該第一位元組讀取起始脈衝訊號、該第一位元組讀取完成脈衝訊號、該第二位元組讀取起始脈衝訊號及該第二位元組讀取完成脈衝訊號；一控制器模組，係連接該電壓同步控制器，接收一外部類比訊號，且據以產生該量測結果訊號及該量測完成脈衝訊號；一暫存器模組，係連接該電壓同步控制器、該資料解析與傳輸模組及該控制器模組，且接收該第三輸出訊號及該第四輸出訊號，該暫存器模組儲存一第一位元組資料及一第二位元組資料，並且據以產生一第三輸入訊號及一第四輸入訊號；一組態邏輯模組，係連接該暫存器模組，且實現使用者命令或偵測外部連結狀態；以及一實體層與應用層模組，係連接該暫存器模組。A voltage reading control system, comprising: a voltage synchronization controller having the voltage synchronization control circuit as described in any one of items 1 to 7 of the scope of patent application, and receiving the first byte Read the start pulse signal, the first byte read complete pulse signal, the second byte read start pulse signal, the second byte read complete pulse signal, the measurement result signal, and The measurement completes the pulse signal, and generates a third output signal and a fourth output signal accordingly; a data analysis and transmission module is connected to the voltage synchronization controller, receives at least one external data demand signal, and generates it accordingly The first byte read start pulse signal, the first byte read complete pulse signal, the second byte read start pulse signal, and the second byte read complete pulse signal; A controller module connected to the voltage synchronization controller, receives an external analog signal, and generates the measurement result signal and the measurement completion pulse signal accordingly;A register module is connected to the voltage synchronization controller, the data analysis and transmission module and the controller module, and receives the third output signal and the fourth output signal, and the register module stores A first byte of data and a second byte of data, based on which a third input signal and a fourth input signal are generated; a configuration logic module is connected to the register module and realizes The user commands or detects the external connection status; and a physical layer and an application layer module are connected to the register module.如請求項8所述之電壓讀取控制系統，其中該暫存器模組之該第一位元組資料產生該第三輸入訊號。The voltage reading control system according to claim 8, wherein the first byte data of the register module generates the third input signal.如請求項8所述之電壓讀取控制系統，其中該暫存器模組之該第二位元組資料產生該第四輸入訊號。The voltage reading control system according to claim 8, wherein the second byte data of the register module generates the fourth input signal.

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