TWI684130B - Data storage device - Google Patents

Abstract

A multi-level central processing unit (CPU) of a controller of a data storage device is shown. In the multi-level central processing unit CPU, a transmitting end has a plurality of command queues, so that multiple commands are queued therein to be immediately transmitted to a receiving end. Each command queue is provided for a particular attribute.

Description

Translated fromChinese

資料儲存裝置Data storage

本案係有關於資料儲存裝置的控制器架構。This case is about the controller architecture of the data storage device.

非揮發式記憶體有多種形式─例如，快閃記憶體（flash memory）、磁阻式隨機存取記憶體（Magnetoresistive RAM）、鐵電隨機存取記憶體（Ferroelectric RAM）、電阻式隨機存取記憶體（Resistive  RAM）、自旋轉移力矩隨機存取記憶體（Spin Transfer Torque-RAM， STT-RAM）…等，用於長時間資料保存，可做為儲存媒體實現一資料儲存裝置。There are many forms of non-volatile memory-for example, flash memory (flash memory), magnetoresistive random access memory (Magnetoresistive RAM), ferroelectric random access memory (Ferroelectric RAM), resistive random access Memory (Resistive RAM), Spin Transfer Torque-RAM (STT-RAM), etc. are used for long-term data storage, and can be used as a storage medium to realize a data storage device.

一資料儲存裝置是以一控制器控制一非揮發式記憶體。該控制器之設計為本技術領域一項重要課題。A data storage device uses a controller to control a non-volatile memory. The design of the controller is an important subject in the technical field.

本案一種實施方式以多階層架構設計一中央處理單元(central processing unit)，使之應用於一資料儲存裝置的一控制器。關於該中央處理單元中不同階層之間的指令傳送，本案令發送端具有複數個指令佇列(command queues)，使複數筆指令得以佇列於其中，即時傳送給接收端。一種實施方式中，一第一指令佇列存有一第一指令，一第二指令則由一第二指令佇列儲存；第二指令之佇列不受第一指令延滯。接收端收到該第一指令後會回復發送端一確收反饋。由於發送端早已在該第二指令佇列備妥該第二指令，一旦獲得該第一指令的該確收反饋，即可自該第二指令佇列將該第二指令傳送至接收端。An embodiment of the present invention designs a central processing unit with a multi-level architecture, which is applied to a controller of a data storage device. Regarding the command transmission between different levels in the central processing unit, in this case, the sending end has a plurality of command queues (command queues), so that a plurality of commands can be queued in it and transmitted to the receiving end in real time. In one embodiment, a first instruction queue stores a first instruction, and a second instruction is stored by a second instruction queue; the second instruction queue is not delayed by the first instruction. After receiving the first instruction, the receiving end will reply to the sending end with an acknowledgement feedback. Since the sending end has already prepared the second command in the second command queue, once the acknowledgement feedback of the first command is obtained, the second command can be transmitted from the second command queue to the receiving end.

一種實施方式中，接收端有複數個儲存器。發送端所提供的該等指令佇列分別對應該等儲存器。一種實施方式中，對應一第一儲存器的一第一指令佇列存有以該第一儲存器為目的地的一第一指令，以一第二儲存器為目的地的一第二指令則由對應該第二儲存器的一第二指令佇列儲存；第二指令之佇列不受第一指令延滯。該第一指令存入該第一儲存器後，一確收反饋回傳發送端。由於發送端早已在該第二指令佇列備妥該第二指令，一旦獲得該第一指令的該確收反饋，即可自該第二指令佇列將該第二指令傳送至該第二儲存器。In one embodiment, the receiving end has a plurality of storages. The command queues provided by the sending end respectively correspond to the memories. In one embodiment, a first command queue corresponding to a first storage contains a first command destined for the first storage, and a second command destined for a second storage Stored by a second command queue corresponding to the second storage; the second command queue is not delayed by the first command. After the first command is stored in the first storage, a confirmation feedback is sent back to the sending end. Since the sender has already prepared the second command in the second command queue, once the acknowledgement feedback of the first command is obtained, the second command can be transferred from the second command queue to the second storage Device.

一種實施方式中，接收端為多核設計，具有複數個處理器，各自對應有儲存器。一第一指令佇列對應一第一處理器，用於暫存以該第一處理器中的一第一儲存器為目的地的指令。一第二指令佇列對應一第二處理器，用於暫存以該第二處理器中的一第二儲存器為目的地的指令。一種實施方式中，以該第一儲存器為目的地的一第一指令是填入該第一指令佇列，以該第二儲存器為目的地的一第二指令是填入該第二指令佇列；第二指令之佇列不受第一指令延滯。該第一指令存入該第一處理器上的該第一儲存器後，一確收反饋回傳發送端。由於發送端早已在該第二指令佇列備妥該第二指令，一旦獲得該第一指令的該確收反饋，即可自該第二指令佇列將該第二指令傳送至該第二處理器上的該第二儲存器。In one embodiment, the receiving end is a multi-core design, with a plurality of processors, each corresponding to a memory. A first instruction queue corresponds to a first processor and is used to temporarily store instructions destined for a first memory in the first processor. A second instruction queue corresponds to a second processor and is used to temporarily store instructions destined for a second memory in the second processor. In one embodiment, a first instruction destined to the first storage is filled in the first instruction queue, and a second instruction destined to the second storage is filled in the second instruction Queue; The second command queue is not delayed by the first command. After the first instruction is stored in the first storage on the first processor, a confirmation feedback is sent back to the sending end. Since the sender has already prepared the second command in the second command queue, once the acknowledgement feedback of the first command is obtained, the second command can be transferred from the second command queue to the second process The second storage on the device.

一種實施方式中，複數個指令佇列是採輪詢(round robin)方式輪流使用發送端與接收端之間的傳輸介面。In one embodiment, the plurality of instruction queues is a round robin (round robin) method in turn using the transmission interface between the sending end and the receiving end.

一種實施方式中，各指令佇列採先入先出(FIFO)儲存結構，更顯著增強指令佇列能力。In one embodiment, each instruction queue adopts a first-in first-out (FIFO) storage structure, which significantly enhances the instruction queue capability.

下文特舉實施例，並配合所附圖示，詳細說明本發明內容。The following describes the embodiments in detail and the accompanying drawings to explain the content of the present invention in detail.

以下敘述列舉本發明的多種實施例。以下敘述介紹本發明的基本概念，且並非意圖限制本發明內容。實際發明範圍應依照申請專利範圍界定之。The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention and is not intended to limit the content of the present invention. The actual scope of invention shall be defined in accordance with the scope of patent application.

非揮發式記憶體可以是快閃記憶體（Flash Memory）、磁阻式隨機存取記憶體（Magnetoresistive RAM）、鐵電隨機存取記憶體（Ferroelectric RAM）、電阻式記憶體（Resistive RAM，RRAM）、自旋轉移力矩隨機存取記憶體（Spin Transfer Torque-RAM， STT-RAM）…等，提供長時間資料保存之儲存媒體。以下特別以快閃記憶體為例進行討論。Non-volatile memory can be flash memory (Flash Memory), magnetoresistive random access memory (Magnetoresistive RAM), ferroelectric random access memory (Ferroelectric RAM), resistive memory (Resistive RAM, RRAM ), spin transfer torque random access memory (Spin Transfer Torque-RAM, STT-RAM), etc., provide storage media for long-term data storage. The following uses flash memory as an example for discussion.

現今資料儲存裝置常以快閃記憶體為儲存媒體，實現記憶卡(Memory Card)、通用序列匯流排閃存裝置(USB Flash Device)、固態硬碟(SSD) …等產品。有一種應用是採多晶片封裝、將快閃記憶體與其控制器包裝在一起─稱為嵌入式快閃記憶體模組(如eMMC)，或是將快閃記憶體、控制器以及DRAM包裝在一起。Today's data storage devices often use flash memory as a storage medium to realize products such as memory cards, USB flash devices, solid state drives (SSD), etc. One application is to use a multi-chip package, package the flash memory and its controller together-called an embedded flash memory module (such as eMMC), or package the flash memory, controller, and DRAM in together.

以快閃記憶體為儲存媒體的資料儲存裝置可應用於多種電子裝置中。所述電子裝置包括智慧型手機、穿戴裝置、平板電腦、虛擬實境設備…等。電子裝置的運算模塊可視為主機(Host)，操作所使用的資料儲存裝置，以存取其中快閃記憶體。A data storage device using flash memory as a storage medium can be applied to various electronic devices. The electronic device includes a smart phone, a wearable device, a tablet computer, a virtual reality device, etc. The computing module of the electronic device can be regarded as a host, which operates the data storage device used to access the flash memory.

以快閃記憶體為儲存媒體的資料儲存裝置也可用於建構數據中心。例如，伺服器可操作固態硬碟(SSD)陣列形成數據中心。伺服器即可視為主機，操作所連結之固態硬碟，以存取其中快閃記憶體。A data storage device using flash memory as a storage medium can also be used to construct a data center. For example, a server may operate a solid state drive (SSD) array to form a data center. The server can be regarded as a host, operating the connected solid-state drive to access the flash memory.

資料儲存裝置提供控制器，用以根據主機指令操作快閃記憶體。第1圖圖解根據本案一種實施方式實現的資料儲存裝置100。The data storage device provides a controller for operating the flash memory according to the instructions of the host. FIG. 1 illustrates adata storage device 100 implemented according to an embodiment of the present case.

資料儲存裝置100包括快閃記憶體102以及控制器104，資料儲存裝置100可更包括DRAM，用以暫存資料，其中，DRAM可配置於資料儲存裝置100中，或由主機106所配置的DRAM所虛擬而成。主機106可透過PCIe介面、SATA介面或SAS（Serial Attached SCSI）介面來控制資料儲存裝置100的運作，根據快速非揮發式記憶體(NVMe)或AHCI規範與該控制器104通信。Thedata storage device 100 includes aflash memory 102 and acontroller 104. Thedata storage device 100 may further include a DRAM for temporarily storing data. The DRAM may be configured in thedata storage device 100 or the DRAM configured by thehost 106 It is virtualized. Thehost 106 can control the operation of thedata storage device 100 through a PCIe interface, a SATA interface, or a SAS (Serial Attached SCSI) interface, and communicates with thecontroller 104 according to the Non-Volatile Memory (NVMe) or AHCI specifications.

該控制器104具有中央處理單元(CPU)108以及快閃記憶體控制器(如，NAND flash controller，簡稱NFC)110。根據該主機106下達的主機指令，該中央處理單元108操作該快閃記憶體控制器110對該快閃記憶體102進行讀/寫以及各種管理。Thecontroller 104 has a central processing unit (CPU) 108 and a flash memory controller (eg, NAND flash controller, NFC for short) 110. According to a host command issued by thehost 106, thecentral processing unit 108 operates theflash memory controller 110 to perform read/write and various management on theflash memory 102.

本案採多階層架構實現該中央處理單元108。如圖所示，該中央處理單元108包括前端(Front End，簡稱FE)112以及後端(Back End，簡稱BE)114。前端(FE)112以及後端(BE)114之間存在指令傳輸需求。前端(FE)112主要負責處理來自主機的主機指令，在主機指令完成接收、排序、除錯等處理，或是下載主機指令的使用者資料之後，前端(FE) 112可將主機指令傳送至後端(BE)114。後端(BE)114執行主機指令，例如，將主機指令轉換成操作指令，再由快閃記憶體控制器110依據操作指令以操作快閃記憶體102，其中，操作指令可例如是讀取、寫入、抺除、重置指令、取得參數（Get Features）或設定參數（Set Features）等指令。後端(BE)114再依據快閃記憶體控制器110的執行結果而產生主機指令的執行結果，並將主機指令的執行結果回傳至前端(FE)112。In this case, thecentral processing unit 108 is implemented with a multi-level architecture. As shown in the figure, thecentral processing unit 108 includes a front end (Front End, FE for short) 112 and a back end (Back End, BE for short) 114. There is a command transmission requirement between the front end (FE) 112 and the back end (BE) 114. The front-end (FE) 112 is mainly responsible for processing host commands from the host. After the host commands finish receiving, sorting, debugging, or downloading user data of the host commands, the front-end (FE) 112 can send the host commands to the post端(BE)114. The back-end (BE) 114 executes host commands, for example, converts host commands into operation commands, and then theflash memory controller 110 operates theflash memory 102 according to the operation commands, where the operation commands may be, for example, reading, Write, delete, reset command, get parameters (Get Features) or set parameters (Set Features) and other commands. The back-end (BE) 114 generates the execution result of the host command according to the execution result of theflash memory controller 110, and returns the execution result of the host command to the front-end (FE) 112.

為了加速主機指令的處理，本案設置有複數個指令佇列(Command Queues，詳示於後續圖示)以供前端(FE) 112使用，如此一來，複數筆主機指令得以佇列於複數個指令佇列，即時傳送給後端(BE)114，其中，複數個指令佇列較佳設置在中央處理單元(CPU)108的內部記憶體（較佳為SRAM）中，亦可設置在DRAM中。假如有4筆主機指令以及2個指令佇列，第1-2筆主機指令佇列至第1指令佇列，第3-4筆主機指令佇列至第2指令佇列。當前端(FE) 112傳送主機指令至後端(BE)114時，可以同時或依序傳送第1指令佇列中的第1筆主機指令以及第2指令佇列中的第3筆主機指令。待第1筆主機指令執行完畢（執行結果為成功）之後，再傳送第1指令佇列中的第2筆主機指令至後端(BE)114。待第3筆主機指令執行完畢（執行結果為成功）之後，再傳送第2指令佇列中的第4筆主機指令至後端(BE)114。In order to speed up the processing of host commands, a plurality of command queues (Command Queues, detailed in the subsequent figure) are provided for the front end (FE) 112 to use, so that a plurality of host commands can be queued in a plurality of commands The queue is sent to the back-end (BE) 114 in real time, wherein the plurality of command queues are preferably arranged in the internal memory (preferably SRAM) of the central processing unit (CPU) 108, and may also be arranged in the DRAM. If there are 4 host commands and 2 command queues, the first 1-2 host command queues to the first command queue, and the third 3-4 host command queues to the second command queue. When the front-end (FE) 112 sends host commands to the back-end (BE) 114, it can send the first host command in the first command queue and the third host command in the second command queue simultaneously or sequentially. After the first host command is executed (the execution result is successful), the second host command in the first command queue is sent to the back-end (BE) 114. After the third host command is executed (the execution result is successful), the fourth host command in the second command queue is sent to the back-end (BE) 114.

由上述中可知，指令佇列的數目愈多，前端(FE)112可同時或依序傳送愈多主機指令至後端(BE)114，無需等待一筆主機指令執行完畢後才能傳送下一筆主機指令。另外，每一指令佇列可獨立運作，當其中之一指令佇列中的一筆主機指令執行完畢後，前端(FE)112亦可立即傳送此指令佇列中的下一筆主機指令至後端(BE)114，不會受到其他指令佇列的主機指令的執行結果的影響，因此，中央處理單元(CPU)108可以更高效率的方式來執行主機指令。As can be seen from the above, the greater the number of command queues, the more front-end (FE) 112 can send more host commands to the back-end (BE) 114 simultaneously or sequentially, without waiting for the completion of a host command before the next host command can be sent. . In addition, each command queue can operate independently. When one host command in one of the command queues is executed, the front end (FE) 112 can also immediately send the next host command in the command queue to the back end ( BE) 114 is not affected by the execution results of the host commands of other command queues. Therefore, the central processing unit (CPU) 108 can execute the host commands in a more efficient manner.

一種實施方式中，本案設置有複數個儲存器在後端(BE)114，每一儲存器分別對應其中一個指令佇列。In one embodiment, a plurality of storages are provided in the back-end (BE) 114 in this case, and each storage corresponds to one of the command queues.

第2圖圖解根據本案一種實施方式所實現的中央處理單元200，處理系統202為前端(FE)，處理系統204為後端(BE)。處理系統202以及處理系統204之間以內連206連結。一種實施方式是根據高級可拓展介面(AXI，簡稱Advanced Extensible Interface)實現內連206通信。處理系統202具有處理器208、指令控制器210以及儲存器模組212。處理系統204具有處理器214、指令控制器216以及儲存器模組218。處理器208所填入至指令控制器210中指令佇列的主機指令經由內連206而傳遞至儲存器模組218中的其中之一儲存器。處理器214所填入至指令控制器216中指令佇列的回覆指令經由內連206傳遞至儲存器模組212中的其中之一儲存器。其中，回覆指令可表示執行結果為成功或失敗。處理系統202以及處理系統204都有機會為指令的發送端或接收端。為了簡化說明，以下討論只關於單一傳輸方向(前端FE為發送端，後端BE為接收端)。另一傳輸方向(後端BE為發送端，且前端FE為接收端)則採類似機制實施。FIG. 2 illustrates acentral processing unit 200 implemented according to an embodiment of the present case. Theprocessing system 202 is a front end (FE), and theprocessing system 204 is a back end (BE). Theprocessing system 202 and theprocessing system 204 are connected by aninterconnect 206. One embodiment is to implement theinterconnection 206 communication according to the Advanced Extensible Interface (AXI, Advanced Extensible Interface). Theprocessing system 202 has aprocessor 208, aninstruction controller 210, and astorage module 212. Theprocessing system 204 has aprocessor 214, aninstruction controller 216, and astorage module 218. The host command filled by theprocessor 208 into the command queue in thecommand controller 210 is transferred to one of the storages in thestorage module 218 via theinterconnect 206. The reply command filled by theprocessor 214 to the command queue in thecommand controller 216 is transmitted to one of the storages in thestorage module 212 via theinterconnect 206. Among them, the reply instruction may indicate that the execution result is success or failure. Both theprocessing system 202 and theprocessing system 204 have the opportunity to be the sender or receiver of the instruction. In order to simplify the description, the following discussion only concerns a single transmission direction (front-end FE is the sending end, and back-end BE is the receiving end). The other transmission direction (back-end BE is the sender and front-end FE is the receiver) is implemented by a similar mechanism.

如圖所示，指令控制器210包括複數個指令佇列220_1…220_n，分別對應處理系統204中的儲存器模組218中的複數個儲存器222_1…222_n。各指令佇列可包括多個暫存器，用以儲存主機指令的參數，例如：目的地位址(儲存器222_1…222_n之一為主機指令傳送的目的地)、指令細節(OP Code、指令運算元…等)、有效位元標示(Byte Enable Signals)…等。儲存器222_1…222_n可能是動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、信箱(Mailbox)…等。處理系統202欲發送主機指令(以Cmd_i示意，i為編號)至處理系統204時，處理器208將目的地位址寫入指令佇列220_i之暫存器。目的地位址填寫完後，指令控制器210將指令佇列220_i的內容彙整為傳輸規格(如，AXI規格)，並要求內連206以進行主機指令Cmd_i的傳送。之後，內連206將主機指令Cmd_i傳送到儲存器模組218中的儲存器222_i。儲存器222_i確收後，確收反饋（ACK）回傳至指令控制器210，表示主機指令Cmd_i已傳送完成。由於主機指令Cmd_i已傳送完成，因此，內連206可進入待機或準備狀態以等待下一個要求。指令控制器210可提供結束信號通知處理器208。於收到主機指令之後，接收端的處理器214則開始執行儲存器222_i所接收到的主機指令Cmd_i。As shown, thecommand controller 210 includes a plurality of command queues 220_1...220_n, respectively corresponding to the plurality of storages 222_1...222_n in thestorage module 218 in theprocessing system 204. Each command queue can include multiple registers to store the parameters of the host command, for example: destination address (one of the memories 222_1...222_n is the destination of the host command transmission), command details (OP Code, command operation Yuan... etc.), valid bit sign (Byte Enable Signals)... etc. The memories 222_1...222_n may be dynamic random access memory (DRAM), static random access memory (SRAM), mailbox (Mailbox)...etc. When theprocessing system 202 wants to send a host command (indicated by Cmd_i, i is a number) to theprocessing system 204, theprocessor 208 writes the destination address into the register of the command queue 220_i. After the destination address is filled, thecommand controller 210 aggregates the contents of the command queue 220_i into a transmission specification (eg, AXI specification), and requests theinterconnection 206 to transmit the host command Cmd_i. After that, theinterconnect 206 transmits the host command Cmd_i to the storage 222_i in thestorage module 218. After the memory 222_i is acknowledged, an acknowledgement feedback (ACK) is returned to thecommand controller 210, indicating that the host command Cmd_i has been transmitted. Since the host command Cmd_i has been transferred, theinterconnect 206 can enter a standby or ready state to wait for the next request. Theinstruction controller 210 may provide an end signal to notify theprocessor 208. After receiving the host command, the receivingprocessor 214 starts to execute the host command Cmd_i received by the storage 222_i.

由於處理系統202具有複數個指令佇列220_1…220_n，所以處理器208不需等待對應至主機指令Cmd_i的回覆指令，可直接將下一筆主機指令(以Cmd_j示意，j為編號，以儲存器222_j為目的地)交予指令控制器210。另外，處理器208無須考慮主機指令Cmd_i的傳遞狀況，當內連206進行主機指令Cmd_i的傳送時，即可將主機指令Cmd_j存入對應的指令佇列220_j，完成指令佇列220_j之暫存器填寫。暫存器填寫完後，指令控制器210將指令佇列220_j的內容彙整為傳輸規格(如，AXI規格)，並要求內連206以進行主機指令Cmd_j的傳送。在指令Cmd_i的確收反饋之後，內連206開始傳送主機指令Cmd_j，將主機指令Cmd_j傳送到儲存器模組218中的儲存器222_j。重覆上述步驟，只要內連206閒置，中央處理單元200可不斷地將主機指令從前端FE傳送至後端BE，因此，可大幅度地增加主機指令傳送的效率。Since theprocessing system 202 has a plurality of command queues 220_1...220_n, theprocessor 208 does not need to wait for the reply command corresponding to the host command Cmd_i, and can directly send the next host command (indicated by Cmd_j, j is the number, and the memory 222_j Is the destination) to thecommand controller 210. In addition, theprocessor 208 does not need to consider the transfer status of the host command Cmd_i. When theinterconnection 206 performs the transfer of the host command Cmd_i, the host command Cmd_j can be stored in the corresponding command queue 220_j to complete the register of the command queue 220_j. fill in. After the register is filled, thecommand controller 210 aggregates the contents of the command queue 220_j into transmission specifications (eg, AXI specifications), and requests theinterconnect 206 to transmit the host command Cmd_j. After the feedback of the command Cmd_i is confirmed, theinterconnect 206 starts to send the host command Cmd_j, and sends the host command Cmd_j to the storage 222_j in thestorage module 218. Repeating the above steps, as long as theinterconnect 206 is idle, thecentral processing unit 200 can continuously transmit host commands from the front end FE to the back end BE, therefore, the efficiency of host command transmission can be greatly increased.

由於指令佇列220_1…220_n與儲存器222_1…222_n存在一對一對應關係，指令佇列220_1…220_n可簡化設計，略去目的地位址、有效位元標示…等暫存器。指令佇列的硬體成本因而有效控制。指令佇列的填寫、以及透過內連206之傳輸也更加有效率。Since the instruction queues 220_1...220_n and the memories 222_1...222_n have a one-to-one correspondence, the instruction queues 220_1...220_n can simplify the design, omitting the destination address, valid bit label, etc. registers. The hardware cost of the command queue is therefore effectively controlled. The filling of the command queue and the transmission through theinterconnect 206 are also more efficient.

一種實施方式中，接收端為多核設計，具有複數個處理器，各自有對應的儲存器。發送端所提供的複數個指令佇列分別對應該等儲存器。In one embodiment, the receiving end is a multi-core design, with a plurality of processors, each having a corresponding storage. The plurality of command queues provided by the sending end respectively correspond to the storages.

第3圖圖解根據本案一種實施方式所實現的一中央處理單元300。處理系統302為前端(FE)。處理系統304_1…304_4則組成多核的後端(BE)。處理系統304_1…304_4除了各自具有一處理器，也各自具有一儲存器，對應編號為306_1…306_4。處理系統302上的指令佇列308_1…308_4分別對應該等處理系統304_1…304_4，以所對應處理系統上的儲存器(306_1…306_4)作為主機指令傳送的目的地。處理系統302欲發送指令佇列308_i的主機指令(以Cmd_i示意)至處理系統304_i(i為編號)上儲存器306_i，處理系統302將指令佇列308_i之暫存器內容彙整為傳輸規格(如，AXI規格)，透過內連傳送到儲存器306_i。無須考慮指令Cmd_i的傳遞狀況，處理系統302可將下一筆主機指令Cmd_j存入對應的指令佇列308_j，完成指令佇列308_j之暫存器填寫以及傳輸格式彙整。儲存器306_i確收後，回傳確收反饋。 一旦自處理系統304_i收到主機指令Cmd_i的確收反饋(確定內連可利用)，指令佇列308_j將早已備妥在指令佇列308_j的主機指令Cmd_j經由內連傳送到處理系統304_j的儲存器306_j。FIG. 3 illustrates acentral processing unit 300 implemented according to an embodiment of this case. Theprocessing system 302 is a front end (FE). The processing systems 304_1...304_4 constitute a multi-core backend (BE). The processing systems 304_1...304_4 each have a processor and a memory, and the corresponding numbers are 306_1...306_4. The instruction queues 308_1...308_4 on theprocessing system 302 respectively correspond to the processing systems 304_1...304_4, and the storages (306_1...306_4) on the corresponding processing systems are used as the destinations for the transmission of host commands. Theprocessing system 302 wants to send the host command (indicated by Cmd_i) of the command queue 308_i to the storage 306_i on the processing system 304_i (i is the number), and theprocessing system 302 aggregates the contents of the register of the command queue 308_i into the transmission specifications (such as , AXI specification), sent to the storage 306_i via an internal connection. Without considering the delivery status of the command Cmd_i, theprocessing system 302 can store the next host command Cmd_j in the corresponding command queue 308_j to complete the register filling of the command queue 308_j and the transfer format integration. After the storage 306_i is confirmed, the confirmation feedback is returned. Once the acknowledgement feedback of the host command Cmd_i is received from the processing system 304_i (determined that the interconnection is available), the command queue 308_j will already be prepared and the host command Cmd_j in the command queue 308_j is transferred to the storage 306_j of the processing system 304_j via the interconnection .

處理系統302可對處理系統304_1…304_4發出同樣指令，例如，暫停時脈指令。指令佇列308_1…308_4之填寫不受彼此內容是否成功透過內連傳送到接收端而干擾。指令佇列308_1…308_4一一被填入暫停時脈指令，可一起被觸發使其中內容彙整為傳輸規格(如，AXI規格)，以最佳效率使用內連，近乎不間斷地輪流透過內連寫入各個處理系統的儲存器(306_1…306_4)。處理系統304_1…304_4因而近乎同步地暫停時脈。Theprocessing system 302 may issue the same instruction to the processing systems 304_1...304_4, for example, a pause clock instruction. The filling of the command queues 308_1...308_4 is not disturbed by whether the contents of each other are successfully transmitted to the receiving end through the interconnection. The command queues 308_1...308_4 are filled with pause clock commands one by one, which can be triggered together so that the content is aggregated into transmission specifications (eg, AXI specifications), the interconnection is used with the best efficiency, and the interconnection is alternately passed through almost continuously Write to the storage of each processing system (306_1...306_4). The processing systems 304_1...304_4 thus pause the clock almost synchronously.

一種實施方式中，複數個指令佇列是採輪詢(Round Robin)方式輪流使用發送端與接收端之間的傳輸介面。In one embodiment, the plurality of command queues are in a round robin (Round Robin) manner, and the transmission interface between the sending end and the receiving end is used in turn.

第4圖為根據本案一種實施方式所實現的處理系統400，其中包括處理器402、指令控制器404以及儲存器406 。作為發送端時，處理器402提供主機指令交由指令控制器404發送。作為接收端時，所接收的回覆指令儲存至儲存器406，再由處理器402執行或判斷。指令控制器404採用輪詢(Round Robin)技術。FIG. 4 is aprocessing system 400 implemented according to an embodiment of the present case, which includes aprocessor 402, aninstruction controller 404, and astorage 406. As the sending end, theprocessor 402 provides host commands to be sent by thecommand controller 404. As the receiving end, the received reply command is stored in thestorage 406, and then executed or judged by theprocessor 402. Thecommand controller 404 uses Round Robin technology.

指令控制器404包括複數個指令佇列410_1、410_2、410_3以及410_4、以及輪詢控制器412。指令佇列410_1、410_2、410_3以及410_4分別具有輪詢佇列(Round Robin Queues) 414_1、414_2、414_3以及414_4。處理器402填入各指令佇列410_1、410_2、410_3以及410_4的指令係在該等輪詢佇列414_1、414_2、414_3以及414_4中排隊，在輪到自己時，由輪詢控制器412發送出去。接收端的確收反饋也將由該輪詢控制器412以輪詢確認信號會報指令佇列410_1、410_2、410_3以及410_4，使輪詢佇列414_1、414_2、414_3以及414_4中排隊的下一個指令得以交由輪詢控制器412發送出去。Thecommand controller 404 includes a plurality of command queues 410_1, 410_2, 410_3, and 410_4, and apolling controller 412. The instruction queues 410_1, 410_2, 410_3, and 410_4 have round robin queues (Round Robin Queues) 414_1, 414_2, 414_3, and 414_4, respectively. Theprocessor 402 fills in the instruction queues 410_1, 410_2, 410_3, and 410_4. The instructions are queued in the polling queues 414_1, 414_2, 414_3, and 414_4, and are sent by thepolling controller 412 when it is their turn . The acknowledgement feedback of the receiving end will also be reported by thepolling controller 412 with the polling confirmation signal to the instruction queues 410_1, 410_2, 410_3, and 410_4, so that the next instruction queued in the polling queues 414_1, 414_2, 414_3, and 414_4 can be delivered It is sent by thepolling controller 412.

圖示更顯示本案提供專用指令佇列的技術使得處理器402僅需將待填數據填入指令佇列410_1、410_2、410_3即可。處理器402可在待填數據之後發出觸發信號，使得待填以及既定的指令數據彙整為內連傳輸規格，在所對應的輪詢佇列排隊。各指令佇列也可根據此觸發信號告知該輪詢控制器412有指令排隊待發送。The figure further shows that the technology of providing a dedicated command queue in this case allows theprocessor 402 to fill only the data to be filled into the command queue 410_1, 410_2, 410_3. Theprocessor 402 may issue a trigger signal after the data to be filled, so that the to-be-filled and predetermined command data are aggregated into an interconnect transmission specification and queued in the corresponding polling queue. Each command queue can also inform thepolling controller 412 that there is a command queue to be sent according to the trigger signal.

一種實施方式中，各指令佇列採先入先出(FIFO)儲存結構，更顯著增強指令佇列能力。In one embodiment, each instruction queue adopts a first-in first-out (FIFO) storage structure, which significantly enhances the instruction queue capability.

第5圖根據本案一種實施方式圖解分別包括先入先出(FIFO)緩衝器502_1、502_2、502_3以及502_4的指令佇列504_1、504_2、504_3以及504_4。如此一來，各指令佇列的指令佇列能力更強。關於同一指令佇列，無需考慮前一個主機指令的傳輸狀況，就可以把後續主機指令填入先入先出緩衝器。FIG. 5 illustrates an instruction queue 504_1, 504_2, 504_3, and 504_4 including first-in first-out (FIFO) buffers 502_1, 502_2, 502_3, and 502_4, respectively, according to an embodiment of the present case. In this way, the instruction queue capability of each instruction queue is stronger. Regarding the same command queue, it is possible to fill subsequent host commands into the first-in first-out buffer without considering the transmission status of the previous host command.

在其他實施方式中，指令控制器中的複數個指令佇列可能是對應其他屬性而提供。除了令複數個指令佇列分別對應複數個裝置，複數個指令佇列也可以是相應複數種功能而提供。各指令因而可略去指令屬性之資訊就填入所對應的指令佇列。In other embodiments, the plurality of instruction queues in the instruction controller may be provided corresponding to other attributes. In addition to making a plurality of command queues correspond to a plurality of devices, the plurality of command queues can also be provided for a corresponding plurality of functions. Each command can thus omit the information of the command attribute and fill in the corresponding command queue.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can do some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined in the scope of the attached patent application.

100‧‧‧資料儲存裝置100‧‧‧Data storage device

102‧‧‧快閃記憶體102‧‧‧Flash memory

104‧‧‧控制器104‧‧‧Controller

106‧‧‧主機106‧‧‧Host

108‧‧‧中央處理單元108‧‧‧Central Processing Unit

110‧‧‧快閃記憶體控制器110‧‧‧Flash memory controller

112‧‧‧前端(FE)112‧‧‧Front End (FE)

114‧‧‧後端(BE)114‧‧‧Backend (BE)

200‧‧‧中央處理單元200‧‧‧Central Processing Unit

202、204‧‧‧處理系統202, 204‧‧‧ processing system

206‧‧‧內連206‧‧‧Inline

208、214‧‧‧處理器208, 214‧‧‧ processor

210、216‧‧‧指令控制器210、216‧‧‧Command controller

212、218‧‧‧處理系統202以及204各自具有的一儲存器模組A storage module in each of the 212, 218‧‧‧processing systems 202 and 204

220_1…220_n‧‧‧指令佇列220_1…220_n‧‧‧Command queue

222_1…222_n‧‧‧儲存器222_1…222_n‧‧‧storage

300‧‧‧‧‧‧中央處理單元300‧‧‧‧‧‧Central Processing Unit

302‧‧‧處理系統302‧‧‧ processing system

304_1…304_4‧‧‧處理系統304_1…304_4‧‧‧‧ processing system

306_1…306_4‧‧‧儲存器306_1…306_4‧‧‧storage

308_1…308_4‧‧‧指令佇列308_1…308_4‧‧‧Command queue

400‧‧‧處理系統400‧‧‧ processing system

402‧‧‧處理器402‧‧‧ processor

404‧‧‧指令控制器404‧‧‧Command controller

406‧‧‧儲存器406‧‧‧Storage

410_1…410_4‧‧‧指令佇列410_1…410_4‧‧‧Command queue

412‧‧‧輪詢控制器412‧‧‧ Polling controller

414_1…414_4‧‧‧輪詢佇列414_1…414_4‧‧‧ Polling queue

502_1…502_4‧‧‧先入先出(FIFO)緩衝器502_1…502_4‧‧‧‧First In First Out (FIFO) buffer

504_1…504_4‧‧‧指令佇列。504_1…504_4‧‧‧‧ queue

第1圖圖解根據本案一種實施方式實現的一資料儲存裝置100； 第2圖圖解根據本案一種實施方式所實現的一中央處理單元200； 第3圖圖解根據本案一種實施方式所實現的一中央處理單元300，其中包括多核的後端(BE) ； 第4圖為根據本案一種實施方式所實現的處理系統400，其中指令控制器404採用輪詢(round robin)技術；以及 第5圖根據本案一種實施方式圖解分別包括先入先出(FIFO)緩衝器502_1、502_2、502_3以及502_4的指令佇列504_1、504_2、504_3以及504_4。Figure 1 illustrates adata storage device 100 implemented according to an embodiment of the case; Figure 2 illustrates acentral processing unit 200 implemented according to an embodiment of the case; Figure 3 illustrates a central processing implemented according to an embodiment of thecase Unit 300, which includes a multi-core back-end (BE); Figure 4 is aprocessing system 400 implemented according to an embodiment of the present case, in which theinstruction controller 404 uses round robin technology; and Figure 5 is based on a case of the present case The embodiment diagrams include instruction queues 504_1, 504_2, 504_3, and 504_4 of first-in first-out (FIFO) buffers 502_1, 502_2, 502_3, and 502_4, respectively.

300‧‧‧中央處理單元300‧‧‧Central Processing Unit

302‧‧‧處理系統302‧‧‧ processing system

304_1…304_4‧‧‧處理系統304_1…304_4‧‧‧‧ processing system

306_1…306_4‧‧‧儲存器306_1…306_4‧‧‧storage

308_1...308_4‧‧‧指令佇列308_1...308_4‧‧‧Command queue

Claims (10)

Translated fromChinese

一種資料儲存裝置，包括：一非揮發式記憶體；以及一控制器，操作該非揮發式記憶體，包括一中央處理單元，其中：該中央處理單元採用多階層架構，不同階層之處理系統彼此通訊，其中一第一處理系統上，安裝供實現一發送端的一指令控制器包括複數個指令佇列，其中一第一指令佇列佇列有一第一指令時，該第一處理系統的一第一處理器是將一第二指令填入一第二指令佇列待發送；且該第一處理器是在接收到該第一指令對應的一回覆指令前，將該第二指令填入該第二指令佇列待發送，該回覆指令表示該第一指令在一接收端的執行結果為成功或失敗。A data storage device includes: a non-volatile memory; and a controller operating the non-volatile memory, including a central processing unit, wherein: the central processing unit adopts a multi-level structure, and processing systems of different levels communicate with each other , Where one of the first processing systems, a command controller installed to implement a sending end includes a plurality of command queues, where a first command queue queue has a first command, a first of the first processing system The processor fills a second command into a second command queue to be sent; and the first processor fills the second command into the second command before receiving a reply command corresponding to the first command The command queue is to be sent, and the reply command indicates that the execution result of the first command at the receiving end is success or failure.根據申請專利範圍第1項所述的資料儲存裝置，其中：該指令控制器將該第一指令自該第一指令佇列經一傳輸介面發送至該接收端後，收集該接收端接收該第一指令後回傳的一確收反饋，隨之將該第二指令佇列所佇列的該第二指令自該第一處理系統藉該傳輸介面發送出去。The data storage device according to item 1 of the patent application scope, wherein: the command controller sends the first command from the first command queue to the receiving end through a transmission interface, and then collects the receiving end to receive the first A confirmation feedback is returned after a command, and then the second command queued by the second command queue is sent out from the first processing system through the transmission interface.根據申請專利範圍第2項所述的資料儲存裝置，其中：該第一指令佇列係對應一第一儲存器，且由該第一處理系統自該第一指令佇列發送出去的該第一指令係以該第一儲存器為目的地；且該第二指令佇列係對應一第二儲存器，且由該第一處理系統自該第二指令佇列發送出去的該第二指令係以該第二儲存器為目的地。The data storage device according to item 2 of the patent application scope, wherein: the first command queue corresponds to a first storage, and the first command system sends out the first command queue from the first command queue The command is destined for the first storage; andThe second command queue corresponds to a second storage, and the second command sent from the second command queue by the first processing system takes the second storage as a destination.根據申請專利範圍第3項所述的資料儲存裝置，更包括：一第二處理系統，具有一第二處理器以及該第一儲存器，其中，該第一儲存器接收的該第一指令係由該第二處理器執行；以及一第三處理系統，具有一第三處理器以及該第二儲存器，其中，該第二儲存器接收的該第二指令係由該第三處理器執行。The data storage device according to item 3 of the patent application scope further includes: a second processing system having a second processor and the first storage, wherein the first command received by the first storage is Executed by the second processor; and a third processing system having a third processor and the second storage, wherein the second instruction received by the second storage is executed by the third processor.根據申請專利範圍第4項所述的資料儲存裝置，其中：該傳輸介面為一高級可拓展介面。According to the data storage device described in item 4 of the patent application scope, wherein: the transmission interface is an advanced expandable interface.根據申請專利範圍第2項所述的資料儲存裝置，其中：該指令控制器的該等指令佇列採輪詢(round robin)方式輪流使用該傳輸介面。According to the data storage device described in item 2 of the patent application scope, wherein: the command interface of the command controller adopts a round robin (round robin) method in turn to use the transmission interface.根據申請專利範圍第6項所述的資料儲存裝置，其中：該指令控制器更包括一輪詢控制器；且該指令控制器的該等指令佇列分別具有一輪詢佇列，使指令排隊於其中，由該輪詢控制器發送至該傳輸介面。The data storage device according to item 6 of the patent application scope, wherein: the command controller further includes a polling controller; and the command queues of the command controller each have a polling queue to queue the commands , Sent by the polling controller to the transmission interface.根據申請專利範圍第2項所述的資料儲存裝置，其中：上述複數個指令佇列與複數個指令屬性分別對應，使該等指令屬性的指令係分開佇列。According to the data storage device described in item 2 of the patent application scope, wherein: the plurality of command queues corresponds to the attributes of the plurality of commands, so that the commands areSexual instructions are queued separately.根據申請專利範圍第8項所述的資料儲存裝置，其中：該等指令佇列分別具有一先入先出緩衝器，以佇列同樣指令屬性的複數個指令。According to the data storage device described in item 8 of the patent application scope, wherein the instruction queues each have a first-in first-out buffer to queue a plurality of instructions with the same instruction attributes.根據申請專利範圍第8項所述的資料儲存裝置，其中：各指令係略去指令屬性之資訊而填入所對應的指令佇列。According to the data storage device described in Item 8 of the patent application scope, each command is to omit the information of the command attribute and fill in the corresponding command queue.

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