本案是關於半導體元件領域，特別是一種複合式寬汲極電晶體及其製造方法。This case relates to the field of semiconductor elements, and in particular to a composite wide-drain transistor and a method for manufacturing the same.
隨著半導體工業的進步與發展，現今已進展到奈米等級的技術製程，並且以追求高元件密度、高性能與低成本為目標。為了滿足前述的需求，對於半導體在製造與設計方面的帶來許多的挑戰，也因此電晶體開始採用三維結構做設計及製造。With the progress and development of the semiconductor industry, the technology process has been advanced to the nanometer level, and the goal is to pursue high component density, high performance and low cost. In order to meet the aforementioned requirements, many challenges have been brought to the manufacture and design of semiconductors. Therefore, transistors have begun to use three-dimensional structures for design and manufacturing.
由於電晶體的尺寸逐漸縮小，採用三維多閘極（Multigate）結構的電晶體雖然可以有效增加閘極的控制能力，抑制短通道效應（short-channel effects，SCE）以及減少汲極偏壓導致通道能障降低效應（Drain-Induced Barrier Lowering，DIBL）。並且與傳統平面式結構的電晶體相比，三維多閘極結構的電晶體在改善直流特性上有顯著成效，但是相對的三維多閘極結構的電晶體具有較差的高頻特性表現。As the size of the transistor is gradually shrinking, although a three-dimensional multigate structure transistor can effectively increase the gate control ability, suppress short-channel effects (SCE), and reduce the drain bias caused by the channel Drain-Induced Barrier Lowering (DIBL). And compared with the traditional planar structure of the transistor, the three-dimensional multi-gate structure of the transistor has a significant effect on improving the chilling characteristics, but the relatively three-dimensional multi-gate structure of the transistor has a poor high-frequency performance.
依據一些實施例，一種複合式寬汲極電晶體，其包括一基板、一主動層及一三維閘極區。其中主動層設置於基板上方，主動層包括一源極區、一源極延展區、一通道區、一汲極延展區及一汲極區。通道區包括一奈米線區、一第一平面區及一第二平面區。其中通道區連接奈米線區，奈米線區連接第一平面區，第一平面區連接第二平面區，而第二平面區連接汲極區。源極區、源極延展區、第二平面區及汲極區具有一第一摻雜濃度。奈米線區及第一平面區具有一第二摻雜濃度。汲極延展區沿著一第一方向延伸，三維閘極區沿著一第二方向延伸，第二方向垂直於第一方向。部分的三維閘極區設置於通道區的上方及二側以包覆通道區。According to some embodiments, a composite wide-drain transistor includes a substrate, an active layer, and a three-dimensional gate region. The active layer is disposed above the substrate. The active layer includes a source region, a source extension region, a channel region, a drain extension region, and a drain region. The passage area includes a nanometer area, a first planar area, and a second planar area. The channel region is connected to the nanometer region, the nanometer region is connected to the first plane region, the first plane region is connected to the second plane region, and the second plane region is connected to the drain region. The source region, the source extension region, the second planar region, and the drain region have a first doping concentration. The nanowire region and the first planar region have a second doping concentration. The drain extension area extends along a first direction, the three-dimensional gate area extends along a second direction, and the second direction is perpendicular to the first direction. Part of the three-dimensional gate region is disposed above and on both sides of the channel region to cover the channel region.
依據一些實施例，一種複合式寬汲極電晶體的製造方法，其包括以下步驟：提供一基板、形成沿著第一方向配置的源極區、源極延展區、通道區、汲極延展區及汲極區在基板上，其中汲極延展區包括沿著第一方向從通道區至汲極區之間依序配置的奈米線區、第一平面區及第二平面區、形成沿著第二方向延伸的三維閘極區在通道區上，其中部分的三維閘極區設置於通道區的上方及二側以包覆通道區，並且第二方向垂直於該第一方向、形成第二摻雜濃度於摻雜奈米線區及第一平面區、形成第一摻雜濃度於源極區、源極延展區、第二平面區及汲極區。According to some embodiments, a method for manufacturing a composite wide-drain transistor includes the following steps: providing a substrate, forming a source region, a source extension region, a channel region, and a drain extension region arranged along a first direction; And the drain region are on the substrate, wherein the drain extension region includes a nanowire region, a first planar region, and a second planar region sequentially arranged from the channel region to the drain region along the first direction, The three-dimensional gate region extending in the second direction is on the channel region, and part of the three-dimensional gate region is disposed above and on both sides of the channel region to cover the channel region, and the second direction is perpendicular to the first direction to form a second The doping concentration is in the doped nanowire region and the first planar region, and the first doping concentration is formed in the source region, the source extension region, the second planar region, and the drain region.
綜上，一種複合式寬汲極電晶體及其製造方法，其係具有良好的直流特性、良好的高頻特性、良好的高頻功率特性以及良好的崩潰電壓，並能改善多閘極多重奈米線通道結構造成的高頻特性衰退現象。In summary, a composite wide-drain transistor and a manufacturing method thereof have good DC characteristics, good high-frequency characteristics, good high-frequency power characteristics, and good breakdown voltage, and can improve multi-gate and multi-level Phenomenon channel structure caused by high-frequency characteristics degradation phenomenon.
本案是關於複合式寬汲極電晶體及其製造方法。儘管在說明書中描述了數個被認為是實施本案的較佳模式，但應理解本案仍可以諸多方式來實現，且不應限定於下述之特定實施例或實現下述特徵的特定方式。在其他情況下，公知細節將不再贅述或討論以避免模糊本案重點。This case relates to a composite wide-drain transistor and a method for manufacturing the same. Although several descriptions are considered in the description to be the preferred modes for implementing this case, it should be understood that this case can still be implemented in many ways and should not be limited to the specific embodiments described below or the specific ways to achieve the features described below. In other cases, well-known details will not be repeated or discussed to avoid obscuring the focus of the case.
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地做出解釋。In addition, in order to easily describe the relationship between one component or feature and another component or feature shown in the drawings, for example, "under", "below", "lower", Spatially relative terms of "on", "upper" and similar terms. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the elements when in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein are explained accordingly.
請參照圖1及圖2，在一些實施例，複合式寬汲極電晶體10包括一基板100、一主動層200及一三維閘極區260。主動層200設置於基板100上方。主動層200包括一源極區210、一源極延展區220、一通道區230、一汲極延展區240及一汲極區250。其中，主動層200包括沿著一第一方向D1延伸且依序配置的源極區210、源極延展區220、通道區230、汲極延展區240及汲極區250。而三維閘極區240沿著一第二方向D2延伸在通道區230上。需特別說明的是，第二方向D2垂直於第一方向D1。Please refer to FIGS. 1 and 2. In some embodiments, the composite wide-drain transistor 10 includes a substrate 100, an active layer 200, and a three-dimensional gate region 260. The active layer 200 is disposed above the substrate 100. The active layer 200 includes a source region 210, a source extension region 220, a channel region 230, a drain extension region 240, and a drain region 250. The active layer 200 includes a source region 210, a source extension region 220, a channel region 230, a drain extension region 240, and a drain region 250, which are sequentially arranged along a first direction D1. The three-dimensional gate region 240 extends on the channel region 230 along a second direction D2. It should be noted that the second direction D2 is perpendicular to the first direction D1.
在一些實施例，汲極延展區240包括一奈米線區242、一第一平面區244及一第二平面區246。於此，奈米線區242、第一平面區244及第二平面區246沿著一第一方向D1配置在通道區230與汲極區220之間。奈米線區242的一端連接通道區230。第二平面區246的一端連接汲極區250。換言之，奈米線區242連接於通道區230與第一平面區244之間，第一平面區244連接於奈米線區242與第二平面區246之間，而第二平面區246連接於第一平面區244與汲極區250之間。依據一些實施例，奈米線區242在第一方向D1上的長度是長於第一平面區244在第一方向D1上的長度。In some embodiments, the drain extension region 240 includes a nanowire region 242, a first planar region 244, and a second planar region 246. Here, the nanowire region 242, the first planar region 244, and the second planar region 246 are disposed between the channel region 230 and the drain region 220 along a first direction D1. One end of the nanowire region 242 is connected to the channel region 230. One end of the second planar region 246 is connected to the drain region 250. In other words, the nanowire region 242 is connected between the channel region 230 and the first plane region 244, the first plane region 244 is connected between the nanometer region 242 and the second plane region 246, and the second plane region 246 is connected to Between the first planar region 244 and the drain region 250. According to some embodiments, the length of the nanowire region 242 in the first direction D1 is longer than the length of the first plane region 244 in the first direction D1.
依據一些實施例，源極延展區220設置於源極區210與通道區230之間。並且在一些實施例中，部分的三維閘極區260設置於通道區230的上方及二側以包覆通道區230。According to some embodiments, the source extension region 220 is disposed between the source region 210 and the channel region 230. And in some embodiments, a part of the three-dimensional gate region 260 is disposed above and on both sides of the channel region 230 to cover the channel region 230.
在一些實施例，源極區210、源極延展區220、第二平面區246及汲極區250具有一第一摻雜濃度。奈米線區242及第一平面區244具有一第二摻雜濃度。並且，第一摻雜濃度不同於第二摻雜濃度。在一些實施例，第一摻雜濃度高於第二摻雜濃度。也就是源極區210、源極延展區220、第二平面區246及汲極區250為重摻雜區，而奈米線區242及第一平面區244為淡摻雜區。舉例來說，在一些實施例中，複合式寬汲極電晶體10是以第一摻雜濃度為5*1015每平方公分的磷離子摻雜於源極區210、源極延展區220、第二平面區246及汲極區250，並且以第二摻雜濃度為5*1014每平方公分的磷離子摻雜於奈米線區242及第一平面區244。In some embodiments, the source region 210, the source extension region 220, the second planar region 246, and the drain region 250 have a first doping concentration. The nanowire region 242 and the first planar region 244 have a second doping concentration. And, the first doping concentration is different from the second doping concentration. In some embodiments, the first doping concentration is higher than the second doping concentration. That is, the source region 210, the source extension region 220, the second planar region 246, and the drain region 250 are heavily doped regions, and the nanowire region 242 and the first planar region 244 are lightly doped regions. For example, in some embodiments, the composite wide-drain transistor 10 is doped in the source region 210, the source extension region 220, with a first doping concentration of 5 * 1015 phosphorus ions per square centimeter. The second planar region 246 and the drain region 250 are doped in the nanowire region 242 and the first planar region 244 with phosphorus ions having a second doping concentration of 5 * 1014 per square centimeter.
在一些實施例中，奈米線區242及第一平面區244為未摻雜區，換句話說，第二摻雜濃度可為主動層200仍然是本質半導體(intrinsic semiconductor)時的濃度，也就是主動層200未經摻雜的原始濃度。於此，第二摻雜濃度低於第一摻雜濃度。In some embodiments, the nanowire region 242 and the first planar region 244 are undoped regions. In other words, the second doping concentration may be the concentration when the active layer 200 is still an intrinsic semiconductor, and It is the original concentration of the active layer 200 that is not doped. Here, the second doping concentration is lower than the first doping concentration.
依據一些實施例，通道區230例如但不限於為未摻雜、或摻雜p型摻質（例如，硼離子）。According to some embodiments, the channel region 230 is, for example, without limitation, undoped, or doped with a p-type dopant (eg, boron ions).
請參照圖1及圖2。依據一些實施例，複合式寬汲極電晶體10根據圖1中的延伸線A至延伸線A’為切線，並沿著法線B至法線B’的方向以形成剖面，而圖2的視角為前述剖面從圖1的右下方朝左上方的方向。在一些實施例中，複合式寬汲極電晶體10能形成在塊狀矽（bulk silicon）的基板100上。而在一些實施例，複合式寬汲極電晶體10也能形成在絕緣體上矽（Silicon-on-Insulator，SOI）的基板100上或絕緣體上鍺（Germanium-on-Insulator，GOI）的基板100上，也就是在基板100上形成一層埋入氧化層400（Buried Oxide）以做為絕緣體。另外，根據的一些實施例，基板100可以包括其他導電層或其他導電元件，例如但不限於電晶體、二極體等。在一些實施例中，基板100可包含矽（Si）、鍺（Ge）、 矽鍺（SiGe）、銻化銦（InSb）、碲化鉛（PbTe）、砷化銦（InAs）、磷化銦（InP）、砷化鎵（GaAs）及/或銻化鎵（GaSb）。Please refer to FIG. 1 and FIG. 2. According to some embodiments, the composite wide-drain transistor 10 is a tangent line according to the extension line A to the extension line A ′ in FIG. 1, and forms a cross section along the direction of the normal line B to the normal line B ′, and The angle of view is the direction from the lower right to the upper left in FIG. 1. In some embodiments, the composite wide-drain transistor 10 can be formed on a substrate 100 of bulk silicon. In some embodiments, the composite wide-drain transistor 10 can also be formed on a substrate 100 of silicon-on-insulator (SOI) or a substrate 100 of germanium-on-insulator (GOI). On the substrate 100, a buried oxide layer 400 (Buried Oxide) is formed as an insulator. In addition, according to some embodiments, the substrate 100 may include other conductive layers or other conductive elements, such as, but not limited to, transistors, diodes, and the like. In some embodiments, the substrate 100 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), and / or gallium antimonide (GaSb).
在一些實施例中，基板100包括單晶矽基板（例如，晶圓）。取決於設計需求，基板100可以包括各個摻雜區（例如，p型基板100或n型基板100）。依據一些實施例中，摻雜區可以摻雜有p型摻質或n型摻質。例如，摻雜區可摻雜有諸如硼或二氟化硼（BF2）的p型摻質，或是諸如磷或砷的n型摻質。摻雜區可配置為用於n型複合式寬汲極電晶體10，或者配置為用於P型複合式寬汲極電晶體10。In some embodiments, the substrate 100 includes a single crystal silicon substrate (eg, a wafer). Depending on design requirements, the substrate 100 may include various doped regions (for example, the p-type substrate 100 or the n-type substrate 100). According to some embodiments, the doped region may be doped with a p-type dopant or an n-type dopant. For example, the doped region may be doped with a p-type dopant such as boron or boron difluoride (BF2 ), or an n-type dopant such as phosphorus or arsenic. The doped region may be configured for an n-type composite wide-drain transistor 10 or configured for a P-type composite wide-drain transistor 10.
依據一些實施例，複合式寬汲極電晶體10藉由濕式氧化製程以形成厚度為1微米的埋入氧化層400在基板100上。According to some embodiments, the composite wide-drain transistor 10 is formed on the substrate 100 by a wet oxidation process to form a buried oxide layer 400 having a thickness of 1 micron.
在一些實施例，複合式寬汲極電晶體10藉由低壓化學氣相沉積（Low-pressure CVD，LPCVD）以形成非晶矽結構於基板100上，而後轉變非晶矽結構以形成多晶矽結構的主動層200。其中轉變非晶矽結構以形成多晶矽結構的方法，例如但不限於雷射結晶、準分子雷射結晶、綠光雷射結晶、固相結晶（Solid phase crystallization）、金屬誘發結晶（Metal induced crystallization，MIC）、或金屬誘發側向結晶（Metal induced lateral crystallization，MILC）。依據一些實施例，非晶矽結構形成於埋入氧化層400上，因此多晶矽結構的主動層200同樣形成於埋入氧化層400上。In some embodiments, the composite wide-drain transistor 10 uses low-pressure chemical vapor deposition (LPCVD) to form an amorphous silicon structure on the substrate 100, and then transforms the amorphous silicon structure to form a polycrystalline silicon structure. Active layer 200. Among them, a method of transforming an amorphous silicon structure to form a polycrystalline silicon structure, such as, but not limited to, laser crystallization, excimer laser crystallization, green laser crystallization, solid phase crystallization, and metal induced crystallization. MIC), or Metal induced lateral crystallization (MILC). According to some embodiments, the amorphous silicon structure is formed on the buried oxide layer 400, so the active layer 200 of the polycrystalline silicon structure is also formed on the buried oxide layer 400.
在一些實施例中，複合式寬汲極電晶體10藉由連續波雷射退火（Continuous-wave laser annealing）以轉變非晶矽結構形成多晶矽結構（polycrystalline，poly-Si）的主動層200。依據一些實施例，複合式寬汲極電晶體10以550攝氏溫度的低壓化學氣相沉積以形成100奈米厚的未摻雜的非晶矽（amorphous silicon，α-Si），再藉由功率為5.5瓦並且掃描速率為6公分/每秒的連續波綠光雷射退火以轉變非晶矽結構為多晶矽結構的主動層200。需特別說明的是，在一些實施例中，多晶矽結構的主動層200又稱為多晶矽結構層。In some embodiments, the composite wide-drain transistor 10 uses continuous-wave laser annealing to change the amorphous silicon structure to form a polycrystalline (poly-Si) active layer 200. According to some embodiments, the composite wide-drain transistor 10 is deposited at a low pressure of 550 degrees Celsius by chemical vapor deposition to form 100 nanometers thick undoped amorphous silicon (α-Si). A continuous wave green laser annealing at 5.5 watts and a scan rate of 6 cm / s to transform the amorphous silicon structure into a polycrystalline silicon active layer 200. It should be particularly noted that, in some embodiments, the polycrystalline silicon structure active layer 200 is also referred to as a polycrystalline silicon structure layer.
在一些實施例中，複合式寬汲極電晶體10藉由電子束微影以形成犧牲圖案。其中，電子束微影可包括光阻塗佈（photoresist coating）、軟烘烤（soft baking）、光罩對準（mask aligning）、曝光（exposure）、曝光後烘烤（post-exposure）、光阻顯影（developing photoresist）、潤洗（rising）、硬烘烤（hard baking）等步驟。In some embodiments, the composite wide-drain transistor 10 is lithographed by an electron beam to form a sacrificial pattern. Among them, the electron beam lithography may include photoresist coating, soft baking, mask alignment, exposure, post-exposure, light Development photoresist, washing, hard baking and other steps.
在一些實施例中，複合式寬汲極電晶體10藉由反應式離子刻蝕（Reactive-Ion Etching，RIE）以移除犧牲圖案，並藉此形成源極區210、源極延展區220、通道區230、汲極延展區240及汲極區250。需特別說明的是，汲極延展區240從通道區230沿著第一方向D1延伸至汲極區250，汲極延展區240的各個部件依序排列為奈米線區242、第一平面區244及第二平面區246。In some embodiments, the composite wide-drain transistor 10 is formed by reactive ion etching (Reactive-Ion Etching, RIE) to remove the sacrificial pattern, thereby forming a source region 210, a source extension region 220, The channel region 230, the drain extension region 240, and the drain region 250. It should be noted that the drain extension area 240 extends from the channel area 230 along the first direction D1 to the drain area 250, and the components of the drain extension area 240 are sequentially arranged as a nanowire area 242 and a first planar area. 244 和 第二 平面 区 246.
請參照圖1、圖2及圖3。在一些實施例中，圖3的視角為複合式寬汲極電晶體10根據圖1中的法線B至法線B’從上方朝下方的方向。依據一些實施例，源極延展區220、通道區230及奈米線區242為奈米線結構，並且源極延展區220、通道區230及奈米線區242包括至少一奈米線。奈米線的一端連接源極區210，並且另一端連接第一平面區244。具體而言，每一條奈米線由源極區210延伸至第一平面區244，並且每一條奈米線在連接源極區210的一側（即，奈米線的源極區端）為源極延展區220，而連接第一平面區244的一側（即，奈米線的平面區端）為奈米線區242。換言之，複合式寬汲極電晶體10具有耦接在源極區210與第一平面區244之間的一條或多條奈米線，並且一條或多條奈米線中的每一條奈米線分別是由一條源極延展區220、通道區230及奈米線區242所構成。Please refer to FIGS. 1, 2 and 3. In some embodiments, the viewing angle of FIG. 3 is a direction from the top to the bottom of the composite wide drain transistor 10 according to the normal B to normal B 'in FIG. 1. According to some embodiments, the source extension region 220, the channel region 230, and the nanowire region 242 are nanowire structures, and the source extension region 220, the channel region 230, and the nanowire region 242 include at least one nanowire. One end of the nanowire is connected to the source region 210 and the other end is connected to the first planar region 244. Specifically, each nanowire extends from the source region 210 to the first planar region 244, and each nanowire is on a side connected to the source region 210 (that is, the source region end of the nanowire) is The source extension region 220 and the side connecting the first planar region 244 (ie, the planar region end of the nanowire) is the nanowire region 242. In other words, the composite wide-drain transistor 10 has one or more nanowires coupled between the source region 210 and the first planar region 244, and each of the one or more nanowires They are respectively composed of a source extension area 220, a channel area 230, and a nanowire area 242.
請參照圖3至圖6。在一些實施例，第一平面區244包括至少一第一子平面區245。第一子平面區245的一端（即，奈米線區端）與奈米線以一對一的方式連接，並且第一子平面區245的另一端（即，汲極區端）連接第二平面區246。Please refer to FIGS. 3 to 6. In some embodiments, the first planar region 244 includes at least one first sub-planar region 245. One end of the first sub-plane region 245 (ie, the end of the nanowire region) is connected to the nanowire in a one-to-one manner, and the other end of the first sub-plane region 245 (ie, the end of the drain region) is connected to the second Flat area 246.
依據一些實施例，第一平面區244可包括單一個第一子平面區245，並且第一子平面區245耦接多條奈米線區242。於此，奈米線區242為可彼此不相連接。舉例來說，第一平面區244能具有單一個第一子平面區245，且此第一子平面區245為長矩形（上視圖）。第一子平面區245沿著第一方向D1延伸至奈米線區242，如圖3所示。According to some embodiments, the first plane area 244 may include a single first sub-plane area 245, and the first sub-plane area 245 is coupled to a plurality of nanowire areas 242. Here, the nanowire regions 242 can be disconnected from each other. For example, the first plane area 244 can have a single first sub-plane area 245, and the first sub-plane area 245 is a long rectangle (top view). The first sub-plane area 245 extends to the nano-line area 242 along the first direction D1, as shown in FIG. 3.
依據一些實施例，第一平面區244包括多個第一子平面區245，並且此些第一子平面區245彼此不相連接，如圖4、圖5及圖6所示。在一些實施例中，第一子平面區245於上視圖的形狀例如但不限於四方形、梯形、或類似於四方形或梯形的形狀。舉例來說，第一平面區244能具有多個第一子平面區245，且各第一子平面區245為由汲極區250向奈米線區242漸縮的梯形，如圖5及圖6所示。According to some embodiments, the first plane area 244 includes a plurality of first sub-plane areas 245, and these first sub-plane areas 245 are not connected to each other, as shown in FIG. 4, FIG. 5, and FIG. In some embodiments, the shape of the first sub-plane region 245 in the top view is, for example, but not limited to, a square, trapezoid, or a shape similar to a square or trapezoid. For example, the first planar region 244 can have a plurality of first sub-planar regions 245, and each of the first sub-planar regions 245 is a trapezoid that tapers from the drain region 250 to the nanowire region 242, as shown in FIG. 5 and FIG. 6 shown.
需特別說明的是，各第一子平面區245的奈米線區端的寬度不大於第一子平面區245的汲極區端的寬度。It should be particularly noted that the width of the end of the nanowire region of each first sub-plane region 245 is not greater than the width of the end of the drain region of the first sub-plane region 245.
在一些實施例，第二平面區246依據第一子平面區245的數量而可分為一或多個第二子平面區247，而第二子平面區247在上視圖的形狀例如但不限於四方形、梯形、或類似於四方形或梯形的形狀。在一些實施例，如圖3所示，第二子平面區247與第一子平面區245皆為一四方形，並且第二子平面區247連接第一子平面區245。而在一些實施例，如圖4所示，第二子平面區247與第一子平面區245皆為多個四方形，並且第二子平面區247以一對一的方式連接第一子平面區245。然而，依據一些實施例，如圖5所示，第二子平面區247與第一子平面區245皆為多個梯形，第二子平面區247以一對一的方式連接第一子平面區245，並且第二子平面區247與第一子平面區245可形成一梯形。另外，在一些實施例，如圖6所示，第二子平面區247為多個四方形，第一子平面區245為多個梯形，並且第二子平面區247以一對一的方式連接第一子平面區245。In some embodiments, the second plane area 246 can be divided into one or more second sub-plane areas 247 according to the number of the first sub-plane areas 245, and the shape of the second sub-plane area 247 in the top view is, for example, but not limited to, A square, trapezoid, or shape similar to a square or trapezoid. In some embodiments, as shown in FIG. 3, the second sub-plane area 247 and the first sub-plane area 245 are both square, and the second sub-plane area 247 is connected to the first sub-plane area 245. In some embodiments, as shown in FIG. 4, the second sub-plane area 247 and the first sub-plane area 245 are multiple squares, and the second sub-plane area 247 connects the first sub-plane in a one-to-one manner. Area 245. However, according to some embodiments, as shown in FIG. 5, the second sub-plane area 247 and the first sub-plane area 245 are both trapezoidal, and the second sub-plane area 247 connects the first sub-plane area in a one-to-one manner 245, and the second sub-plane area 247 and the first sub-plane area 245 may form a trapezoid. In addition, in some embodiments, as shown in FIG. 6, the second sub-plane area 247 is a plurality of squares, the first sub-plane area 245 is a plurality of trapezoids, and the second sub-plane area 247 is connected in a one-to-one manner. First sub-plane area 245.
請續參閱圖1及圖2。在一些實施例，複合式寬汲極電晶體10更包括一介電層300，夾設於三維閘極區260與通道區230之間。而複合式寬汲極電晶體10的製造方法更包括：形成一介電層300於三維閘極區260與通道區230之間。Please refer to FIGS. 1 and 2. In some embodiments, the composite wide-drain transistor 10 further includes a dielectric layer 300 sandwiched between the three-dimensional gate region 260 and the channel region 230. The manufacturing method of the composite wide-drain transistor 10 further includes: forming a dielectric layer 300 between the three-dimensional gate region 260 and the channel region 230.
依據一些實施例中，複合式寬汲極電晶體10藉由沉積製程以形成三維閘極區260及介電層300。沉積製程例如低壓化學氣相沉積（Low-pressure CVD，LPCVD）根據一些實施例，複合式寬汲極電晶體10藉由低壓化學氣相沉積以形成50奈米厚的四乙氧基矽烷（Tetraethoxysilane，TEOS）為介電層300，並且形成100奈米厚的臨場摻雜N型多晶矽（in situ n+poly-Si）為三維閘極區260。According to some embodiments, the composite wide-drain transistor 10 is formed by a deposition process to form a three-dimensional gate region 260 and a dielectric layer 300. Deposition process such as Low-pressure CVD (LPCVD) According to some embodiments, the composite wide-drain transistor 10 is formed by low-pressure chemical vapor deposition to form a 50 nanometer thick tetraethoxysilane (Tetraethoxysilane). TEOS) is the dielectric layer 300, and a 100 nm thick in-situ doped N-type polycrystalline silicon (in situ n+ poly-Si) is formed as the three-dimensional gate region 260.
在一些實施例中，介電層300的材料不限於四乙氧基矽烷，也可由二氧化矽（SiO2）、或高介電材料（High Dielectric Constant，HK）所形成。在一些實施例中，三維閘極區260的材料不限於多晶矽，也可由金屬矽化物(Silicide)、或金屬閘極(Metal gate)材料所形成。In some embodiments, the material of the dielectric layer 300 is not limited to tetraethoxysilane, and may be formed of silicon dioxide (SiO2 ), or a high dielectric material (High Dielectric Constant, HK). In some embodiments, the material of the three-dimensional gate region 260 is not limited to polycrystalline silicon, and may also be formed of a metal silicide or a metal gate material.
在一些實施例，複合式寬汲極電晶體10的製造方法更包括：以離子佈植形成源極區210、源極延展區220、汲極延展區240及汲極區250。In some embodiments, the manufacturing method of the composite wide drain transistor 10 further includes: forming a source region 210, a source extension region 220, a drain extension region 240, and a drain region 250 by ion implantation.
在一些實施例，複合式寬汲極電晶體10可藉由離子佈植製程（ion implantation process）、電漿浸沒離子佈植製程（plasma immersion ion implantation process，PIII process）、氣體及/或固體源擴散製程（gas and/or solid source diffusion process）、其他合適的製程或上述的組合達成摻雜。In some embodiments, the composite wide-drain transistor 10 may be processed by an ion implantation process, a plasma immersion ion implantation process (PIII process), a gas, and / or a solid source. Doping is achieved by a gas and / or solid source diffusion process, other suitable processes, or a combination of the above.
在一些實施例，複合式寬汲極電晶體10的製造方法更包括：源極區210、源極延展區220、汲極延展區240及汲極區250以低溫微波退火（Low Temperature Microwave Annealing）以活化離子分佈。在一些實施例，退火方法不限於低溫微波退火，也可用快速熱退火(Rapid thermal annealing，RTA)來活化離子。In some embodiments, the manufacturing method of the composite wide-drain transistor 10 further includes: the source region 210, the source extension region 220, the drain extension region 240, and the drain region 250 by low temperature microwave annealing (Low Temperature Microwave Annealing). To activate ion distribution. In some embodiments, the annealing method is not limited to low-temperature microwave annealing, and rapid thermal annealing (RTA) can also be used to activate the ions.
請參照圖1、圖2、圖7及圖8。在一些實施例，一種複合式寬汲極電晶體10的製造方法，其包括以下步驟：Please refer to FIGS. 1, 2, 7 and 8. In some embodiments, a method for manufacturing a composite wide-drain transistor 10 includes the following steps:
步驟S100：提供基板100。Step S100: Provide a substrate 100.
步驟S110：形成沿著第一方向D1配置的源極區210、源極延展區220、通道區230、汲極延展區240及汲極區250在基板100上，其中汲極延展區240包括：沿著第一方向D1從通道區230至汲極區250之間依序配置的奈米線區242、第一平面區244及第二平面區246。Step S110: forming a source region 210, a source extension region 220, a channel region 230, a drain extension region 240, and a drain region 250 arranged on the substrate 100 along the first direction D1. The drain extension region 240 includes: The nanowire region 242, the first planar region 244, and the second planar region 246 are sequentially arranged from the channel region 230 to the drain region 250 along the first direction D1.
步驟S111：形成埋入氧化層400於基板上。Step S111: forming a buried oxide layer 400 on the substrate.
步驟S112：形成多晶矽結構層於埋入氧化層400上。Step S112: forming a polycrystalline silicon structure layer on the buried oxide layer 400.
步驟S114：形成對應於源極區210、源極延展區220、通道區230、汲極延展區240及汲極區250的犧牲圖案於多晶矽結構層上。Step S114: forming a sacrificial pattern corresponding to the source region 210, the source extension region 220, the channel region 230, the drain extension region 240, and the drain region 250 on the polycrystalline silicon structure layer.
步驟S116：根據犧牲圖案蝕刻多晶矽結構層為源極區210、源極延展區220、通道區230、汲極延展區240及汲極區250。Step S116: etching the polycrystalline silicon structure layer according to the sacrificial pattern into the source region 210, the source extension region 220, the channel region 230, the drain extension region 240, and the drain region 250.
步驟S118：移除犧牲圖案而形成源極區210、源極延展區220、通道區230、汲極延展區240及汲極區250。Step S118: removing the sacrificial pattern to form a source region 210, a source extension region 220, a channel region 230, a drain extension region 240, and a drain region 250.
步驟S120：形成沿著第二方向D2延伸的三維閘極區260在通道區230上，其中部分的三維閘極區260設置於通道區230的上方及二側以包覆通道區230，並且第二方向D2垂直於第一方向D1。Step S120: forming a three-dimensional gate region 260 extending along the second direction D2 on the channel region 230. A part of the three-dimensional gate region 260 is disposed above and on both sides of the channel region 230 to cover the channel region 230, The two directions D2 are perpendicular to the first direction D1.
步驟S130：形成第二摻雜濃度於奈米線區242及第一平面區244。Step S130: forming a second doping concentration in the nanowire region 242 and the first planar region 244.
步驟S140：形成第一摻雜濃度於源極區210、源極延展區220、第二平面區246及汲極區250。Step S140: forming a first doping concentration in the source region 210, the source extension region 220, the second planar region 246, and the drain region 250.
依據一些實施例，複合式寬汲極電晶體10是應用於射頻元件、高頻電路或高頻功率電路。According to some embodiments, the composite wide-drain transistor 10 is applied to a radio frequency element, a high frequency circuit, or a high frequency power circuit.
依據一些實施例中，複合式寬汲極電晶體10例如但不限於傳統金氧半電晶體（Bulk MOSFET）、絕緣體上矽電晶體（SOI MOSFET）、絕緣體上鍺電晶體（GOI MOSFET）、薄膜電晶體（Thin-Film Transistor，TFT）、鰭式薄膜電晶體（Fin-like TFT，FinTFT）。According to some embodiments, the composite wide-drain transistor 10 is, for example, but not limited to, a conventional Bulk MOSFET, a silicon-on-insulator (SOI MOSFET), a germanium-on-insulator (GOI MOSFET), and a thin film. Thin-Film Transistor (TFT), Fin-like TFT (FinTFT).
請參閱圖2及圖3。在一些實施例中，以複合式寬汲極電晶體10為鰭式薄膜電晶體，三維閘極的結構為多晶矽，介電層300為四乙氧基矽烷為例。通道區230的高度（簡稱，通道高T0）為100奈米，通道區230的長度（簡稱，通道長LCH）為0.2微米，奈米線的寬度（簡稱，奈米線寬W0）為135奈米，第一平面區244及第二平面區246在第一方向D1上的總平面延伸長度LEX為0.8微米，第一平面區244及一第二平面區246相連接的等效寬度為4.65微米，介電層300的等效厚度（Equivalent Oxide Thickness，EOT）為50奈米。Please refer to FIG. 2 and FIG. 3. In some embodiments, the composite wide-drain transistor 10 is a fin-type thin-film transistor, the structure of the three-dimensional gate is polycrystalline silicon, and the dielectric layer 300 is tetraethoxysilane. The height of the channel area 230 (for short, the channel height T0 ) is 100 nanometers, the length of the channel area 230 (for short, the channel length LCH ) is 0.2 micrometers, and the width of the nanowires (for short, the nanowire width W0 ) Is 135 nanometers, the total plane extension length LEX of the first planar region 244 and the second planar region 246 in the first direction D1 is 0.8 μm, and the equivalent of the first planar region 244 and a second planar region 246 connected The width is 4.65 micrometers, and the Equivalent Oxide Thickness (EOT) of the dielectric layer 300 is 50 nanometers.
此時，當複合式寬汲極電晶體10的汲源極電壓差（簡稱，VDS）為0.1V，次臨限擺幅（Subthreshold Swing，SS）為198毫伏特/十進位（mV/decade）。當複合式寬汲極電晶體10的閘極電壓（簡稱，VG）比汲極電壓（簡稱，VD）為3V：1V，元件開關比（簡稱，ION/IOFF）大於108，因此可得知複合式寬汲極電晶體10具有良好的直流特性。當複合式寬汲極電晶體10的VDS為1V，截止頻率（簡稱，fT）的峰值為9.55千兆赫茲（GHz），最大震盪頻率fmax的峰值為6.93千兆赫茲，因此可得知複合式寬汲極電晶體10具有良好的高頻特性。當複合式寬汲極電晶體10的頻率為860百萬赫茲，VG為0V，VD為2V時，功率增益為3.39分貝（dB），因此可得知複合式寬汲極電晶體10具有良好的高頻功率特性。當複合式寬汲極電晶體10的VG為0V，總平面延伸長度LEX為0.8微米時，崩潰電壓為6.5V，並且當總平面延伸長度LEX增加時，崩潰電壓也跟著增加，因此可得知複合式寬汲極電晶體10具有良好的崩潰特性。At this time, when the drain-source voltage difference (VDS ) of the composite wide-drain transistor 10 is 0.1V, and the Subthreshold Swing (SS) is 198 millivolts / decade (mV / decade) ). When the gate voltage (abbreviation, VG ) of the composite wide-drain transistor 10 is 3V: 1V compared to the drain voltage (abbreviation, VD ), the element switching ratio (abbreviation, ION / IOFF ) is greater than 108 , Therefore, it can be known that the composite wide-drain transistor 10 has good DC characteristics. When the VDS of the compound wide-drain transistor 10 is 1V, the peak value of the cut-off frequency (abbreviated as fT ) is 9.55 gigahertz (GHz), and the peak value of the maximum oscillation frequency fmax is 6.93 gigahertz. It is known that the composite wide-drain transistor 10 has good high-frequency characteristics. When the frequency of the composite wide-drain transistor 10 is 860 megahertz, VG is 0V, and VD is 2V, the power gain is 3.39 decibels (dB). Therefore, it can be known that the composite wide-drain transistor 10 has Good high-frequency power characteristics. When the composite wide-drain transistor 10 has a VG of 0 V and a total plane extension length LEX of 0.8 μm, the breakdown voltage is 6.5 V. When the total plane extension length LEX increases, the breakdown voltage also increases, so It can be seen that the composite wide-drain transistor 10 has good collapse characteristics.
綜上，根據本案的複合式寬汲極電晶體及其製造方法，其係具有良好的直流特性、良好的高頻特性、良好的高頻功率特性以及良好的崩潰電壓，並能改善多閘極多重奈米線通道結構造成的高頻特性衰退現象。In summary, according to the composite wide-drain transistor and its manufacturing method, the system has good DC characteristics, good high-frequency characteristics, good high-frequency power characteristics, and good breakdown voltage, and can improve multi-gate High-frequency characteristic degradation caused by multiple nanowire channel structures.
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地暸解本案。本技術領域中具有通常知識者應可理解，且可輕易地以本案為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同的優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本案的發明精神與範圍。在不背離本案的發明精神與範圍之前提下，可對本案進行各種改變、置換或修改。The foregoing text summarizes the features of many embodiments so that those having ordinary knowledge in the art can better understand the present case from various aspects. Those with ordinary knowledge in the technical field should understand that other processes and structures can be easily designed or modified based on the present case, so as to achieve the same purpose and / or achieve the same as the embodiments and the like described herein. advantage. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention. Without departing from the spirit and scope of the present invention, various changes, substitutions or modifications can be made to the present case.
10‧‧‧複合式寬汲極電晶體10‧‧‧ Compound Wide Drain Transistor
100‧‧‧基板100‧‧‧ substrate
200‧‧‧主動層200‧‧‧Active layer
210‧‧‧源極區210‧‧‧Source area
220‧‧‧源極延展區220‧‧‧Source extension area
230‧‧‧通道區230‧‧‧passage zone
240‧‧‧汲極延展區240‧‧‧ Drain extension area
242‧‧‧奈米線區242‧‧‧Nanjing District
244‧‧‧第一平面區244‧‧‧First flat area
245‧‧‧第一子平面區245‧‧‧The first sub-plane area
246‧‧‧第二平面區246‧‧‧Second flat area
247‧‧‧第二子平面區247‧‧‧Second Sub-Plane Area
250‧‧‧汲極區250‧‧‧ Drain
260‧‧‧三維閘極區260‧‧‧Three-dimensional gate area
300‧‧‧介電層300‧‧‧ Dielectric layer
400‧‧‧埋入氧化層400‧‧‧Buried oxide layer
D1‧‧‧第一方向D1‧‧‧ first direction
D2‧‧‧第二方向D2‧‧‧ Second direction
W0‧‧‧奈米線寬W0‧‧‧Nano line width
T0‧‧‧通道高T0‧‧‧channel height
LCH‧‧‧通道長LCH ‧‧‧channel length
LEX‧‧‧總平面延伸長度LEX ‧‧‧ Total plane extension
A、A’‧‧‧延伸線A, A’‧‧‧ extension line
S100-S140‧‧‧步驟S100-S140‧‧‧step
B、B’‧‧‧法線B, B’‧‧‧ normal
圖1是根據本案一些實施例之複合式寬汲極電晶體的示意圖。
圖2是根據本案一些實施例之複合式寬汲極電晶體的剖面示意圖。
圖3至圖6是根據本案一些實施例之複合式寬汲極電晶體的上視示意圖。
圖7是根據本案一些實施例之複合式寬汲極電晶體的製造方法的示意圖。
圖8是根據本案一些實施例之複合式寬汲極電晶體的製造方法的示意圖。FIG. 1 is a schematic diagram of a composite wide-drain transistor according to some embodiments of the present invention.
FIG. 2 is a schematic cross-sectional view of a composite wide-drain transistor according to some embodiments of the present invention.
3 to 6 are schematic top views of a composite wide-drain transistor according to some embodiments of the present invention.
FIG. 7 is a schematic diagram of a method for manufacturing a composite wide-drain transistor according to some embodiments of the present invention.
FIG. 8 is a schematic diagram of a method for manufacturing a composite wide-drain transistor according to some embodiments of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108108743ATWI675482B (en) | 2019-03-14 | 2019-03-14 | Hybrid wide drain transistor and method of manufacturing thereof |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108108743ATWI675482B (en) | 2019-03-14 | 2019-03-14 | Hybrid wide drain transistor and method of manufacturing thereof |
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| TWI675482Btrue TWI675482B (en) | 2019-10-21 |
| TW202034528A TW202034528A (en) | 2020-09-16 |
| Application Number | Title | Priority Date | Filing Date |
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| TW108108743ATWI675482B (en) | 2019-03-14 | 2019-03-14 | Hybrid wide drain transistor and method of manufacturing thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8394710B2 (en)* | 2010-06-21 | 2013-03-12 | International Business Machines Corporation | Semiconductor devices fabricated by doped material layer as dopant source |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8394710B2 (en)* | 2010-06-21 | 2013-03-12 | International Business Machines Corporation | Semiconductor devices fabricated by doped material layer as dopant source |
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| TW202034528A (en) | 2020-09-16 |
| Publication | Publication Date | Title |
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