本發明是有關於一種電子電路，且特別是有關於一種通訊裝置、通訊系統及其操作方法。The present invention relates to an electronic circuit, and more particularly to a communication device, a communication system, and a method of operating the same.
微控制單元(microcontroller unit, MCU)電路由於具有高度整合其他元件的能力，可以與許多周邊元件/電路（像是運算功能電路、邏輯電路與/或記憶體等）共同運作，所以被廣泛的使用在車用裝置、手持式裝置等產品。場可編程閘陣列(field programmable gate array，以下稱FPGA)是一種具有可組態(configurable)功能的積體電路，其內部的可組態邏輯區塊(configurable logic block, CLB)可以被編程。具有某一原先功能的習知FPGA在與微控制單元共同運作時，此時編程平台（或編程電路）不可以將新的功能編程至習知FPGA中。在編程平台（或編程電路）將新功能編程至習知FPGA的過程中，習知FPGA無法提供任何功能（包括原先功能與新功能）給微控制單元。所述將新功能編程入習知FPGA的時間往往是漫長的。等到新功能完整編程入習知FPGA中後，習知FPGA才會以新功能與微控制單元共同運作。Microcontroller unit (MCU) circuits are widely used because they have the ability to integrate other components with high integration and can work with many peripheral components/circuits (such as arithmetic functions, logic circuits, and/or memory). In the car equipment, handheld devices and other products. A field programmable gate array (hereinafter referred to as FPGA) is an integrated circuit with a configurable function, and its internal configurable logic block (CLB) can be programmed. A conventional FPGA with some original function can work with the micro-control unit, at which point the programming platform (or programming circuit) cannot program new functions into the conventional FPGA. In the process of programming a new function to a conventional FPGA by a programming platform (or programming circuit), the conventional FPGA cannot provide any function (including the original function and the new function) to the micro control unit. The time to program new functions into a conventional FPGA is often lengthy. After the new function is fully programmed into the familiar FPGA, the conventional FPGA will work with the micro control unit with new functions.
FPGA與微控制單元可以被應用於通訊裝置中。FPGA與微控制單元可以提供底層（例如實體層，即Physical Layer）通訊功能。基於編程，FPGA可以具有通信介面，用來與遠端系統（另一個通訊裝置）進行資料傳輸。這兩個通訊裝置可以透過一個加密通信網路來相互交換資料。習知的通訊裝置是在欲傳輸資料上進行加密，然後使用固定（不變動）的通訊協定而將經加密資料傳輸給對方。這兩個習知的通訊裝置的通信界面之間的通信協定（Communication Protocol）並不會改變。雖然其間傳輸的資料已經被加密了，但是由於其通信協定可能為駭客熟知，尤其是無線電通信網路更無法防止駭客監視（監聽）此通信網路。在通信協定是固定（不變動）的情況下，駭客可以透過此通信協定進行資料攔截及分析來加以破解。The FPGA and micro control unit can be used in a communication device. The FPGA and the micro control unit can provide the underlying (eg, physical layer) communication function. Based on programming, the FPGA can have a communication interface for data transmission with the remote system (another communication device). The two communication devices can exchange data with each other through an encrypted communication network. The conventional communication device encrypts the data to be transmitted, and then transmits the encrypted data to the other party using a fixed (non-changing) communication protocol. The communication protocol between the communication interfaces of the two conventional communication devices does not change. Although the data transmitted between them has been encrypted, its communication protocol may be well known to hackers, especially the radio communication network is more unable to prevent hackers from monitoring (monitoring) the communication network. In the case where the communication agreement is fixed (no change), the hacker can use the communication protocol for data interception and analysis to crack.
本發明提供一種通訊裝置、通訊系統及其操作方法，以提高通信網路的安全性。The invention provides a communication device, a communication system and an operation method thereof to improve the security of a communication network.
本發明的通訊裝置包括微控制單元以及場可編程閘陣列。場可編程閘陣列耦接於微控制單元，經配置以於第一期間中執行第一通訊協定而與微控制單元相互協同工作以便與另一通訊裝置進行通訊，且同時被微控制單元將第二通訊協定編程至該場可編程閘陣列中。場可編程閘陣列受控於微控制單元所輸出切換脈衝而結束第一期間並從第一通訊協定切換至第二通訊協定，且場可編程閘陣列於第二期間中執行第二通訊協定而與微控制單元相互協同工作以便與所述另一通訊裝置進行通訊。The communication device of the present invention includes a micro control unit and a field programmable gate array. The field programmable gate array is coupled to the micro control unit, configured to execute the first communication protocol in the first period and cooperate with the micro control unit to communicate with another communication device, and at the same time, the micro control unit The two communication protocols are programmed into the field programmable gate array. The field programmable gate array is controlled by the switching pulse output by the micro control unit to end the first period and switch from the first protocol to the second protocol, and the field programmable gate array executes the second protocol in the second period Working in conjunction with the micro control unit to communicate with the other communication device.
在本發明的一實施例中，對應上述第一通訊協定的阻態不同於對應上述第二通訊協定的阻態。In an embodiment of the invention, the resistance state corresponding to the first communication protocol is different from the resistance state corresponding to the second communication protocol.
在本發明的一實施例中，上述的場可編程閘陣列包括多個記憶區塊，而這些記憶區塊都分別包括第一開關、第一電阻式非揮發性記憶體元件、第二電阻式非揮發性記憶體元件、閂鎖單元、第二開關。第一開關的第一端耦接至行編程線。第一電阻式非揮發性記憶體元件的下電極耦接至第一開關的第二端，且第一電阻式非揮發性記憶體元件的上電極耦接至第一列線。第二電阻式非揮發性記憶體元件的上電極耦接至第一電阻式非揮發性記憶體元件的下電極，且第二電阻式非揮發性記憶體元件的下電極耦接至第二列線。閂鎖單元的資料輸入端耦接至第一電阻式非揮發性記憶體元件的下電極與第二電阻式非揮發性記憶體元件的上電極。第二開關的控制端耦接至閂鎖單元的資料輸出端，第二開關的第一端耦接至場可編程閘陣列的輸入線，且第二開關的第二端耦接至場可編程閘陣列的輸出線。In an embodiment of the invention, the field programmable gate array includes a plurality of memory blocks, and each of the memory blocks includes a first switch, a first resistive non-volatile memory element, and a second resistive type. Non-volatile memory element, latch unit, second switch. The first end of the first switch is coupled to the row programming line. The lower electrode of the first resistive non-volatile memory component is coupled to the second end of the first switch, and the upper electrode of the first resistive non-volatile memory component is coupled to the first column line. The upper electrode of the second resistive non-volatile memory component is coupled to the lower electrode of the first resistive non-volatile memory component, and the lower electrode of the second resistive non-volatile memory component is coupled to the second column line. The data input end of the latch unit is coupled to the lower electrode of the first resistive non-volatile memory element and the upper electrode of the second resistive non-volatile memory element. The control end of the second switch is coupled to the data output end of the latch unit, the first end of the second switch is coupled to the input line of the field programmable gate array, and the second end of the second switch is coupled to the field programmable The output line of the gate array.
在本發明的一實施例中，上述的於第一期間中，閂鎖單元保持輸出第一功能所對應的第一邏輯準位至第二開關的控制端，同時微控制單元經由第一列線、第二列線、行編程線與第一開關將第二功能所對應的阻態編程至第一電阻式非揮發性記憶體元件或第二電阻式非揮發性記憶體元件。In an embodiment of the invention, in the first period, the latch unit keeps outputting the first logic level corresponding to the first function to the control end of the second switch, and the micro control unit passes the first column line. The second column line, the row programming line and the first switch program the resistance state corresponding to the second function to the first resistive non-volatile memory element or the second resistive non-volatile memory element.
在本發明的一實施例中，上述的場可編程閘陣列更包括一第三開關、一第四開關以及一第五開關。第三開關的第一端耦接至第一列線，且第三開關的第二端經配置以接收第一電壓。第四開關的第一端耦接至該第一列線，且第四開關的第二端經配置以接收讀電壓。第五開關的第一端經配置以接收第二電壓，第五開關的第二端耦接至第二列線。In an embodiment of the invention, the field programmable gate array further includes a third switch, a fourth switch, and a fifth switch. A first end of the third switch is coupled to the first column line, and a second end of the third switch is configured to receive the first voltage. A first end of the fourth switch is coupled to the first column line, and a second end of the fourth switch is configured to receive a read voltage. The first end of the fifth switch is configured to receive the second voltage, and the second end of the fifth switch is coupled to the second column line.
在本發明的一實施例中，上述的於閂鎖單元的取樣期間，第四開關與第五開關導通，第三開關為截止，而閂鎖單元取樣第一電阻式非揮發性記憶體元件與第二電阻式非揮發性記憶體元件的分壓。In an embodiment of the invention, during the sampling of the latch unit, the fourth switch and the fifth switch are turned on, the third switch is turned off, and the latch unit samples the first resistive non-volatile memory element and The partial pressure of the second resistive non-volatile memory element.
在本發明的一實施例中，上述的於第一期間的編程期間中，第一開關、第三開關與第五開關導通，第四開關為截止，而微控制單元經由第一列線、第二列線與行編程線將第二功能所對應的阻態編程至第一電阻式非揮發性記憶體元件或第二電阻式非揮發性記憶體元件。In an embodiment of the invention, in the programming period of the first period, the first switch, the third switch and the fifth switch are turned on, the fourth switch is turned off, and the micro control unit is connected to the first column line The two-column line and the row programming line program the resistance state corresponding to the second function to the first resistive non-volatile memory element or the second resistive non-volatile memory element.
在本發明的一實施例中，上述的場可編程閘陣列更包括第一邏輯閘以及第二邏輯閘。第一邏輯閘的輸入端經配置以接收切換脈衝，且第一邏輯閘的輸出端耦接至第四開關的控制端。第二邏輯閘的輸入端耦接至第一邏輯閘的輸出端，且第二邏輯閘的輸出端耦接至各記憶區塊的閂鎖單元的閘門端。In an embodiment of the invention, the field programmable gate array further includes a first logic gate and a second logic gate. The input of the first logic gate is configured to receive a switching pulse, and the output of the first logic gate is coupled to the control terminal of the fourth switch. The input end of the second logic gate is coupled to the output end of the first logic gate, and the output end of the second logic gate is coupled to the gate end of the latch unit of each memory block.
本發明的通訊裝置的操作方法包括以下步驟。於第一期間中，藉由場可編程閘陣列執行第一通訊協定而與微控制單元相互協同工作以便與另一通訊裝置進行通訊，且同時由微控制單元將第二通訊協定編程至場可編程閘陣列中。由微控制單元輸出切換脈衝而結束第一期間，並使場可編程閘陣列從第一通訊協定切換至第二通訊協定，且於第二期間中執行第二通訊協定而與微控制單元相互協同工作以便與所述另一通訊裝置進行通訊。The method of operation of the communication device of the present invention includes the following steps. During the first period, the first communication protocol is executed by the field programmable gate array to cooperate with the micro control unit to communicate with another communication device, and at the same time, the second communication protocol is programmed to the field by the micro control unit. Program the gate array. Outputting a switching pulse by the micro control unit to end the first period, and switching the field programmable gate array from the first communication protocol to the second communication protocol, and executing the second communication protocol in the second period to cooperate with the micro control unit Working to communicate with the other communication device.
本發明的一種通訊系統包括第一通訊裝置以及第二通訊裝置。第二通訊裝置包括微控制單元以及場可編程閘陣列。場可編程閘陣列耦接於微控制單元。場可編程閘陣列經配置以於第一期間中執行第一通訊協定而與該微控制單元相互協同工作以便與該第一通訊裝置進行通訊，且同時被微控制單元將第二通訊協定編程至場可編程閘陣列中。場可編程閘陣列受控於微控制單元所輸出切換脈衝而結束第一期間，並從第一通訊協定切換至第二通訊協定。場可編程閘陣列於第二期間中執行第二通訊協定而與微控制單元相互協同工作，以便與該第一通訊裝置進行通訊。A communication system of the present invention includes a first communication device and a second communication device. The second communication device includes a micro control unit and a field programmable gate array. The field programmable gate array is coupled to the micro control unit. The field programmable gate array is configured to perform a first communication protocol in a first period to cooperate with the micro control unit to communicate with the first communication device, and at the same time, the second communication protocol is programmed by the micro control unit to Field programmable gate array. The field programmable gate array is controlled by the switching pulse output by the micro control unit to end the first period and switch from the first protocol to the second protocol. The field programmable gate array performs a second communication protocol in the second period and cooperates with the micro control unit to communicate with the first communication device.
基於上述，本發明實施例所述的場可編程閘陣列與微控制單元相互協同工作，以便與另一通訊裝置進行通訊。在微控制單元將新通訊協定（第二通訊協定）編程至場可編程閘陣列的同時，場可編程閘陣列可以執行原先通訊協定（第一通訊協定）而與微控制單元相互協同工作以便與所述另一通訊裝置進行通訊。當場可編程閘陣列接到由微控制單元發出的切換脈衝時，場可編程閘陣列就能即時從第一通訊協定切換至第二通訊協定，而在切換中並不需耗費多餘的編程或轉換時間。因此，本發明實施例所述的通訊裝置可以一直反覆更改通訊協定，來提高通訊網路的資料傳輸的安全性。Based on the above, the field programmable gate array and the micro control unit according to the embodiments of the present invention work in cooperation with each other to communicate with another communication device. While the micro-control unit programs the new protocol (second protocol) to the field programmable gate array, the field programmable gate array can execute the original communication protocol (first protocol) and cooperate with the micro control unit to The other communication device communicates. When the field programmable gate array is connected to the switching pulse sent by the micro control unit, the field programmable gate array can immediately switch from the first protocol to the second protocol, and no unnecessary programming or conversion is required in the switching. time. Therefore, the communication device according to the embodiment of the present invention can repeatedly change the communication protocol to improve the security of data transmission of the communication network.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
在本案說明書全文(包括申請專利範圍)中所使用的「耦接（或連接）」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接（或連接）於第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。The term "coupled (or connected)" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled (or connected) to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be A connection means is indirectly connected to the second device. In addition, wherever possible, the elements and/ Elements/components/steps that use the same reference numbers or use the same terms in different embodiments may refer to the related description.
請參考圖1，圖1繪示本發明一實施例之功能可編程電路100的方塊示意圖。在本實施例中的功能可編程電路100包括微控制單元110以及場可編程閘陣列120，並且微控制單元110耦接於場可編程閘陣列120。微控制單元110可以是微處理器、微控制器、中央處理單元(central processing unit, CPU)或是其他具有多功能整合與處理能力的電路/元件，場可編程閘陣列(field programmable gate array，FPGA)可以是任何具有可編程的邏輯裝置，在此並不加以設限。在本實施例中，場可編程閘陣列120經配置/編程(program)後而具有某一功能（例如第一功能FUNC_1）。場可編程閘陣列120可以於第一期間中執行第一功能FUNC_1而與微控制單元110相互協同工作。Please refer to FIG. 1. FIG. 1 is a block diagram of a functional programmable circuit 100 according to an embodiment of the present invention. The function programmable circuit 100 in this embodiment includes a micro control unit 110 and a field programmable gate array 120, and the micro control unit 110 is coupled to the field programmable gate array 120. The micro control unit 110 can be a microprocessor, a microcontroller, a central processing unit (CPU) or other circuits/components with multi-function integration and processing capabilities, a field programmable gate array (field programmable gate array, The FPGA) can be any programmable logic device and is not limited herein. In the present embodiment, the field programmable gate array 120 has a certain function (for example, the first function FUNC_1) after being configured/programmed. The field programmable gate array 120 can perform the first function FUNC_1 in the first period and cooperate with the micro control unit 110.
接著請一併參考圖1及圖2，圖2是依照本發明一實施例繪示圖1所示功能可編程電路100的操作時序示意圖。於圖2中，橫軸表示時間。於第一期間T1中，場可編程閘陣列120具有第一功能FUNC_1，且微控制單元110進行工作A，以便與場可編程閘陣列120相互協同工作。舉例來說（但不限於此），微控制單元110可以通過互聯匯流排（interconnect bus）Bus2對場可編程閘陣列120進行控制，使場可編程閘陣列120執行第一功能FUNC_1。且值得注意的是，微控制單元110在進行工作A的時候也同時進行工作B，以便通過編程匯流排（programming bus）Bus1將新的功能（例如第二功能FUNC_2）編程到場可編程閘陣列120中。也就是說，場可編程閘陣列120於第一期間T1中除了執行第一功能FUNC_1而與微控制單元110相互協同工作外，並且同時被微控制單元110將第二功能FUNC_2編程至場可編程閘陣列120中。第二功能FUNC_2的編程，並不影響/中斷第一功能FUNC_1的進行。Referring to FIG. 1 and FIG. 2 together, FIG. 2 is a schematic diagram showing the operation sequence of the function programmable circuit 100 shown in FIG. 1 according to an embodiment of the invention. In Fig. 2, the horizontal axis represents time. In the first period T1, the field programmable gate array 120 has a first function FUNC_1, and the micro control unit 110 performs operation A to cooperate with the field programmable gate array 120. For example, but not limited to, the micro control unit 110 can control the field programmable gate array 120 via the interconnect bus Bus2 to cause the field programmable gate array 120 to perform the first function FUNC_1. It is also worth noting that the micro control unit 110 also performs the work B while performing the work A to program a new function (for example, the second function FUNC_2) to the field programmable gate array through the programming bus Bus1. 120. That is, the field programmable gate array 120 cooperates with the micro control unit 110 in addition to the first function FUNC_1 in the first period T1, and is simultaneously programmed by the micro control unit 110 to the field programmable FUNC_2. In the gate array 120. The programming of the second function FUNC_2 does not affect/interrupt the progress of the first function FUNC_1.
接著，在將第二功能FUNC_2完整編程到場可編程閘陣列120中後，微控制單元110可以通過控制信號線SL對場可編程閘陣列120輸出切換脈衝Stri。場可編程閘陣列120在接收到切換脈衝Stri之後即結束第一期間T1，並且從第一功能FUNC_1切換至第二功能FUNC_2。在第一期間T1之後的第二期間T2中，微控制單元110可以進行工作C，以便與場可編程閘陣列120相互協同工作。舉例來說（但不限於此），微控制單元110在進行工作C的時候通過互聯匯流排Bus2對場可編程閘陣列120進行控制，使場可編程閘陣列120在第二期間T2中執行第二功能FUNC_2。Then, after the second function FUNC_2 is completely programmed into the field programmable gate array 120, the micro control unit 110 can output the switching pulse Stri to the field programmable gate array 120 through the control signal line SL. The field programmable gate array 120 ends the first period T1 after receiving the switching pulse Stri, and switches from the first function FUNC_1 to the second function FUNC_2. In the second period T2 after the first period T1, the micro control unit 110 can perform the operation C to cooperate with the field programmable gate array 120. For example, but not limited to, the micro control unit 110 controls the field programmable gate array 120 through the interconnect bus Bus 2 during the operation C, and causes the field programmable gate array 120 to execute in the second period T2. Two functions FUNC_2.
換句話說，場可編程閘陣列120是受控於微控制單元110所輸出的切換脈衝Stri。場可編程閘陣列120接收切換脈衝Stri而結束第一期間T1，並從第一功能FUNC_1切換至第二功能FUNC_2，且於第二期間T2中執行第二功能FUNC_2而與微控制單元110相互協同工作。在本發明的切換信號Stri可以是由使用者端以軟體等方式調整微控制單元110，又或是預先對微控制單元進行110設定，本發明並不加以限制。In other words, the field programmable gate array 120 is controlled by the switching pulse Stri output by the micro control unit 110. The field programmable gate array 120 receives the switching pulse Stri to end the first period T1, and switches from the first function FUNC_1 to the second function FUNC_2, and performs the second function FUNC_2 in the second period T2 to cooperate with the micro control unit 110. jobs. In the switching signal Stri of the present invention, the micro control unit 110 may be adjusted by the user end in a software manner or the like, or the micro control unit may be set 110 in advance, and the present invention is not limited thereto.
具體而言，本實施例利用微控制單元110控制場可編程閘陣列120。在第一期間T1中，微控制單元110能在控制場可編程閘陣列120執行第一功能FUNC_1的同時，將第二功能FUNC_2編程至場可編程閘陣列120。在不停止場可編程閘陣列120所執行的第一功能FUNC_1的情況下，微控制單元110可以編程第二功能FUNC_1到場可編程閘陣列120中。由於在場可編程閘陣列120執行第一功能FUNC_1的期間已經先將第二功能FUNC_2編程到場可編程閘陣列120，因此場可編程閘陣列120可以即時地從第一功能FUNC_1切換到第二功能FUNC_2而不需耗費時間去等待微控制單元110的編程。Specifically, the present embodiment utilizes the micro control unit 110 to control the field programmable gate array 120. In the first period T1, the micro control unit 110 can program the second function FUNC_2 to the field programmable gate array 120 while the control field programmable gate array 120 executes the first function FUNC_1. Without stopping the first function FUNC_1 performed by the field programmable gate array 120, the micro control unit 110 can program the second function FUNC_1 into the field programmable gate array 120. Since the second function FUNC_2 has been programmed to the field programmable gate array 120 during the execution of the first function FUNC_1 by the field programmable gate array 120, the field programmable gate array 120 can be switched from the first function FUNC_1 to the second immediately. The function FUNC_2 does not take time to wait for programming of the micro control unit 110.
請同時參考圖3及圖4，圖3是依照本發明另一實施例繪示圖1所示場可編程閘陣列120的操作情境示意圖，圖4是依照本發明另一實施例繪示圖3所示場可編程閘陣列120的操作時序示意圖。假設本實施例的場可編程閘陣列120具有10K電晶體數目，而功能FUNC_A、功能FUNC_B以及功能FUNC_C所需要的電晶體數目分別為3K、5K及10K。3 and FIG. 4, FIG. 3 is a schematic diagram showing the operation of the field programmable gate array 120 of FIG. 1 according to another embodiment of the present invention, and FIG. 4 is a diagram of FIG. 3 according to another embodiment of the present invention. A timing diagram of the operation of the field programmable gate array 120 is shown. It is assumed that the field programmable gate array 120 of the present embodiment has a number of 10K transistors, and the number of transistors required for the functions FUNC_A, FUNC_B, and FUNC_C is 3K, 5K, and 10K, respectively.
於圖4所示第一期間T1中，場可編程閘陣列120具有功能FUNC_A及功能FUNC_B，且微控制單元110可以進行工作D，以便與場可編程閘陣列120相互協同工作。舉例來說（但不限於此），微控制單元110可以通過互聯匯流排Bus2對場可編程閘陣列120進行控制，使場可編程閘陣列120執行功能FUNC_A及FUNC_B。同時於第一期間T1，微控制單元110在進行工作D的時候亦同時進行工作E，以便通過編程匯流排Bus1將新的功能（例如功能FUNC_C）編程到場可編程閘陣列120中。功能FUNC_C的編程，並不影響/中斷功能FUNC_A及FUNC_B的進行。In the first period T1 shown in FIG. 4, the field programmable gate array 120 has the function FUNC_A and the function FUNC_B, and the micro control unit 110 can perform the operation D to cooperate with the field programmable gate array 120. For example, but not limited to, the micro control unit 110 can control the field programmable gate array 120 via the interconnect bus bus 2, causing the field programmable gate array 120 to perform functions FUNC_A and FUNC_B. At the same time, during the first period T1, the micro control unit 110 simultaneously performs the operation E when the operation D is performed, so that a new function (for example, the function FUNC_C) is programmed into the field programmable gate array 120 through the programming bus Bus1. The programming of the function FUNC_C does not affect the execution of the interrupt functions FUNC_A and FUNC_B.
然後，當場可編程閘陣列120通過控制信號線SL接收到微控制單元110的切換脈衝Stri時，結束第一期間T1，並且功能FUNC_A及功能FUNC_B切換至功能FUNC_C。在第二期間T2中，微控制單元110可以進行工作F，以便與微控制單元110相互協同工作。舉例來說（但不限於此），微控制單元110在進行工作F的時候通過互聯匯流排Bus2對場可編程閘陣列120進行控制，使場可編程閘陣列120在第二期間T2中執行功能FUNC_C。Then, when the field programmable gate array 120 receives the switching pulse Stri of the micro control unit 110 through the control signal line SL, the first period T1 is ended, and the function FUNC_A and the function FUNC_B are switched to the function FUNC_C. In the second period T2, the micro control unit 110 can perform the operation F to cooperate with the micro control unit 110. For example, but not limited to, the micro control unit 110 controls the field programmable gate array 120 through the interconnect bus Bus2 during the operation F, so that the field programmable gate array 120 performs the function in the second period T2. FUNC_C.
由上述操作可以了解到，雖然功能FUNC_A、功能FUNC_B及功能FUNC_C無法同時燒寫至場可編程閘陣列120中（因為FUNC_A、FUNC_B及FUNC_C所需的電晶體數目總和已超過場可編程閘陣列120的電晶體數目），但是藉由功能切換，場可編程閘陣列120的有限的電晶體數目可以實現更多功能。It can be understood from the above operation that although the function FUNC_A, the function FUNC_B and the function FUNC_C cannot be simultaneously programmed into the field programmable gate array 120 (because the sum of the number of transistors required for FUNC_A, FUNC_B and FUNC_C has exceeded the field programmable gate array 120) The number of transistors), but by functional switching, the limited number of transistors of the field programmable gate array 120 can achieve more functionality.
再來請參考圖5，圖5是依照本發明一實施例繪示圖1所示場可編程閘陣列120之電路結構示意圖。本實施例的場可編程閘陣列120包括多個記憶區塊，例如圖5所示記憶區塊501A、501B、501C以及501D。以下將以記憶區塊501A為說明範例，其他記憶區塊可以參照記憶區塊501A的相關說明而類推。記憶區塊501A包括第一開關Q1、第一電阻式非揮發性記憶體元件511、第二電阻式非揮發性記憶體元件512、閂鎖單元513以及第二開關Q2。上述的第一開關Q1以及第二開關Q2可以是金屬氧化物半導體場效電晶體(metal-oxide semi-conductor field-effect transistor, MOSFET)、雙極性接面電晶體(bipolar junction transistor, BJT)或是其他開關電路/元件。例如本實施例的第一開關Q1、第二開關Q2可以是N型金屬氧化物半導體(NMOS)場效電晶體。閂鎖單元513可以包括閂鎖器(latch)、正反器(flip-flop)或是其他可以保存資料的電路/元件，本發明並不加以設限。Referring to FIG. 5, FIG. 5 is a schematic diagram showing the circuit structure of the field programmable gate array 120 of FIG. 1 according to an embodiment of the invention. The field programmable gate array 120 of the present embodiment includes a plurality of memory blocks, such as memory blocks 501A, 501B, 501C, and 501D shown in FIG. The memory block 501A will be exemplified below, and other memory blocks can be analogized with reference to the description of the memory block 501A. The memory block 501A includes a first switch Q1, a first resistive non-volatile memory element 511, a second resistive non-volatile memory element 512, a latch unit 513, and a second switch Q2. The first switch Q1 and the second switch Q2 may be a metal-oxide semi-conductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT) or It is another switch circuit/component. For example, the first switch Q1 and the second switch Q2 of the embodiment may be N-type metal oxide semiconductor (NMOS) field effect transistors. The latch unit 513 may include a latch, a flip-flop or other circuit/component that can hold data, and the invention is not limited thereto.
上述第一電阻式非揮發性記憶體元件511以及第二電阻式非揮發性記憶體元件512可視不同的設計需求而採用不同的實施方式。舉例來說，第一電阻式非揮發性記憶體元件511可以包括上電極(top electrode) TE、可變電阻體以及下電極(bottom electrode) BE，其中可變電阻體配置於上電極TE與下電極BE之間。所述下電極BE材料可以是釔鋇銅氧化物YBa2Cu3O7(YBCO)膜，或是氮化鈦(TiN)，或是包含選自錳、鐵、鎳、鈷、鈦、銅、釩、矽中之元素之氧化物、氮化物、氧氮化物或前述之組合（例如鈦(Ti)、二氧化矽(SiO2)、矽(Si)等）。所述可變電阻體材料可以是鈣鈦礦型氧化物之結晶性鐠鈣錳氧化物Pr1-XCaXMnO3(PCMO)膜，或是ZnSe-Ge異質構造，或者關於Ti、Nb、Hf、Zr、Ta、Ni、V、Zn、Sn、In、Th、Al等金屬之氧化物（例如二氧化鉿(HfO2)薄膜）。所述上電極TE材料可以是濺鍍所沉積的Ag膜，或是氮化鈦(TiN)。隨著上電極TE、可變電阻體與下電極BE的材質及/或製程條件的改變，第一電阻式非揮發性記憶體元件511的電阻值以及閾電壓（clamp voltage）會有所不同。藉由調整第一電阻式非揮發性記憶體元件511的上電極TE與下電極BE之間的電壓方向與電壓大小，可以改變第一電阻式非揮發性記憶體元件511的阻態，進而調整記憶區塊501A~501D的非揮發性邏輯值。第二電阻式非揮發性記憶體元件512可以參照第一電阻式非揮發性記憶體元件511的的相關說明而類推。The first resistive non-volatile memory element 511 and the second resistive non-volatile memory element 512 may adopt different embodiments depending on different design requirements. For example, the first resistive non-volatile memory element 511 may include a top electrode TE, a variable resistor body, and a bottom electrode BE, wherein the variable resistor body is disposed on the upper electrode TE and the lower electrode Between the electrodes BE. The material of the lower electrode BE may be a yttrium copper oxide YBa2 Cu3 O7 (YBCO) film, or titanium nitride (TiN), or may be selected from the group consisting of manganese, iron, nickel, cobalt, titanium, copper, An oxide, a nitride, an oxynitride or a combination of the foregoing (for example, titanium (Ti), cerium oxide (SiO2 ), cerium (Si), etc.). The variable resistor material may be a crystalline strontium calcium manganese oxide Pr1-XCaXMnO3 (PCMO) film of a perovskite type oxide, or a ZnSe-Ge heterostructure, or about Ti, Nb, Hf, Zr, An oxide of a metal such as Ta, Ni, V, Zn, Sn, In, Th, or Al (for example, a hafnium oxide (HfO2 ) film). The upper electrode TE material may be a deposited Ag film or a titanium nitride (TiN). The resistance value and the clamp voltage of the first resistive non-volatile memory element 511 may vary depending on the material of the upper electrode TE, the variable resistor body, and the lower electrode BE and/or the process conditions. By adjusting the voltage direction and the voltage between the upper electrode TE and the lower electrode BE of the first resistive non-volatile memory element 511, the resistance state of the first resistive non-volatile memory element 511 can be changed, thereby adjusting Non-volatile logic values of memory blocks 501A-501D. The second resistive non-volatile memory component 512 can be analogized with reference to the related description of the first resistive non-volatile memory component 511.
於記憶區塊501A中，第一開關Q1的控制端（例如閘極）接收第一控制信號PR1。第一開關Q1的第一端（例如源極）耦接至行（column）編程線520，且其第二端（例如汲極）耦接至第一電阻式非揮發性記憶體元件511的下電極BE。第一電阻式非揮發性記憶體元件511的上電極TE耦接至第一列（row）線531，且其下電極BE耦接至第二電阻式非揮發性記憶體元件512的上電極TE。第二電阻式非揮發性記憶體元件512的下電極BE耦接至第二列線532。閂鎖單元513的資料輸入端D耦接至第一電阻式非揮發性記憶體元件511的下電極BE與第二電阻式非揮發性記憶體元件512的上電極TE。第二開關Q2的控制端（例如閘極）耦接至閂鎖單元513的資料輸出端Q，而第二開關Q2的第一端（例如汲極）耦接至場可編程閘陣列120的輸入線541，並且第二開關Q2的第二端（例如源極）耦接至場可編程閘陣列120的輸出線542。In the memory block 501A, the control terminal (e.g., the gate) of the first switch Q1 receives the first control signal PR1. The first end of the first switch Q1 (eg, the source) is coupled to the column programming line 520, and the second end thereof (eg, the drain) is coupled to the first resistive non-volatile memory element 511. Electrode BE. The upper electrode TE of the first resistive non-volatile memory element 511 is coupled to the first row line 531, and the lower electrode BE is coupled to the upper electrode TE of the second resistive non-volatile memory element 512. . The lower electrode BE of the second resistive non-volatile memory element 512 is coupled to the second column line 532. The data input terminal D of the latch unit 513 is coupled to the lower electrode BE of the first resistive non-volatile memory element 511 and the upper electrode TE of the second resistive non-volatile memory element 512. The control terminal (eg, the gate) of the second switch Q2 is coupled to the data output terminal Q of the latch unit 513, and the first terminal (eg, the drain) of the second switch Q2 is coupled to the input of the field programmable gate array 120. Line 541 and a second end (eg, source) of second switch Q2 is coupled to output line 542 of field programmable gate array 120.
場可編程閘陣列120還包括第三開關Q3、第四開關Q4、第五開關Q5、第一邏輯閘LG1以及第二邏輯閘LG2。上述的第三開關Q3、第四開關Q4、第五開關Q5可以是金屬氧化物半導體場效電晶體、雙極性接面電晶體或是其他開關電路/元件。例如（但不限於此），第三開關Q3以及第五開關Q5可以是NMOS電晶體，而第四電晶體Q4可以是PMOS電晶體。第三開關Q3的控制端（例如閘極）接收第一控制信號PR1。第三開關Q3的第一端（例如源極）耦接至第一列線531，而第三開關Q3的第二端（例如汲極）經配置以接收第一電壓V1。第四開關Q4的第一端（例如汲極）耦接至第一列線531，而第四開關Q4的第二端（例如源極）經配置以接收讀電壓Vr。第五開關Q5的控制端（例如閘極）接收第二控制信號PR2。第五開關Q5的第一端（例如源極）經配置以接收第二電壓V2，而第五開關Q5的第二端（例如汲極）耦接至第二列線532。第一邏輯閘LG1的輸入端耦接至控制信號線SL以接收切換脈衝Stri，且第一邏輯閘LG1的輸出端耦接至第四開關Q4的控制端（例如閘極）。第二邏輯閘LG2的輸入端耦接至第一邏輯閘的輸出端，且第二邏輯閘LG2的輸出端耦接至各記憶區塊501A~501D的閂鎖單元513的閘門端E。The field programmable gate array 120 further includes a third switch Q3, a fourth switch Q4, a fifth switch Q5, a first logic gate LG1, and a second logic gate LG2. The third switch Q3, the fourth switch Q4, and the fifth switch Q5 may be metal oxide semiconductor field effect transistors, bipolar junction transistors or other switching circuits/elements. For example, but not limited to, the third switch Q3 and the fifth switch Q5 may be NMOS transistors, and the fourth transistor Q4 may be a PMOS transistor. The control terminal (eg, the gate) of the third switch Q3 receives the first control signal PR1. A first end (eg, a source) of the third switch Q3 is coupled to the first column line 531, and a second end (eg, a drain) of the third switch Q3 is configured to receive the first voltage V1. A first end (eg, a drain) of the fourth switch Q4 is coupled to the first column line 531, and a second end (eg, a source) of the fourth switch Q4 is configured to receive the read voltage Vr. The control terminal (eg, the gate) of the fifth switch Q5 receives the second control signal PR2. A first end (eg, a source) of the fifth switch Q5 is configured to receive a second voltage V2, and a second end (eg, a drain) of the fifth switch Q5 is coupled to the second column line 532. The input end of the first logic gate LG1 is coupled to the control signal line SL to receive the switching pulse Stri, and the output end of the first logic gate LG1 is coupled to the control end (eg, the gate) of the fourth switch Q4. The input end of the second logic gate LG2 is coupled to the output end of the first logic gate, and the output end of the second logic gate LG2 is coupled to the gate end E of the latch unit 513 of each of the memory blocks 501A-501D.
當場可編程閘陣列120於第一期間T1中，控制信號線SL的邏輯準位為低準位，因此閂鎖單元513保持輸出原先功能（例如第一功能）所對應的第一邏輯準位至第二開關Q2的控制端。也就是說，在控制信號線SL的邏輯準位為低準位的期間，閂鎖單元513的輸出端Q的輸出信號是無關於閂鎖單元513的資料輸入端D的輸入信號。在此同時，微控制單元110可以導通（turn on）第一開關Q1、第三開關Q3與第五開關Q5，以及經由第一列線531、第二列線532與行編程線520將新功能（例如第二功能）所對應的阻態編程至第一電阻式非揮發性記憶體元件511及/或第二電阻式非揮發性記憶體元件512。When the programmable gate array 120 is in the first period T1, the logic level of the control signal line SL is at a low level, so the latch unit 513 keeps outputting the first logic level corresponding to the original function (for example, the first function) to The control terminal of the second switch Q2. That is, while the logic level of the control signal line SL is at a low level, the output signal of the output terminal Q of the latch unit 513 is an input signal irrelevant to the data input terminal D of the latch unit 513. At the same time, the micro control unit 110 can turn on the first switch Q1, the third switch Q3 and the fifth switch Q5, and the new function via the first column line 531, the second column line 532 and the row programming line 520. The resistive state corresponding to (eg, the second function) is programmed to the first resistive non-volatile memory component 511 and/or the second resistive non-volatile memory component 512.
舉例來說，假設第一電壓V1被設定為高位準電壓HV（例如大於第一電阻式非揮發性記憶體元件511的閾電壓，但小於此閾電壓的兩倍），以及第二電壓V2為低位準電壓LV（例如接地電壓或0伏特）。在第一期間T1內，第一電壓V1通過第三開關Q3與第一列線531而被傳輸至第一電阻式非揮發性記憶體元件511的上電極TE，以及第二電壓V2通過第五開關Q5與第二列線532而被傳輸至第二電阻式非揮發性記憶體元件512的下電極BE。此時，若低位準電壓（例如接地電壓或0伏特）通過行編程線520與第一開關Q1而被傳輸至第一電阻式非揮發性記憶體元件511的下電極BE，則第一電阻式非揮發性記憶體元件511會發生「設定（set）」操作，使得第一電阻式非揮發性記憶體元件511的阻態改變為低阻態。所述低阻態的電阻值為大於數百歐姆（例如數KΩ）。由於第二電阻式非揮發性記憶體元件512的上電極TE與下電極BE之電壓差小於其閾電壓，因此第二電阻式非揮發性記憶體元件512的阻態維持於高阻態。所述高阻態的電阻值為大於低阻態阻值的數十倍以上（例如10K~100MΩ）。For example, assume that the first voltage V1 is set to a high level voltage HV (eg, greater than a threshold voltage of the first resistive non-volatile memory element 511, but less than twice the threshold voltage), and the second voltage V2 is Low level voltage LV (eg ground voltage or 0 volts). In the first period T1, the first voltage V1 is transmitted to the upper electrode TE of the first resistive non-volatile memory element 511 through the third switch Q3 and the first column line 531, and the second voltage V2 passes through the fifth The switch Q5 and the second column line 532 are transferred to the lower electrode BE of the second resistive non-volatile memory element 512. At this time, if a low level voltage (for example, ground voltage or 0 volt) is transmitted to the lower electrode BE of the first resistive non-volatile memory element 511 through the row programming line 520 and the first switch Q1, the first resistive type The non-volatile memory element 511 undergoes a "set" operation to change the resistance state of the first resistive non-volatile memory element 511 to a low resistance state. The low resistance state has a resistance value greater than several hundred ohms (eg, several KΩ). Since the voltage difference between the upper electrode TE and the lower electrode BE of the second resistive non-volatile memory element 512 is less than its threshold voltage, the resistance state of the second resistive non-volatile memory element 512 is maintained at a high resistance state. The resistance value of the high resistance state is more than several tens of times higher than the resistance value of the low resistance state (for example, 10K to 100 MΩ).
反之，當高位準電壓HV通過行編程線520與第一開關Q1而被傳輸至第二電阻式非揮發性記憶體元件512的上電極TE，且具有低位準電壓LV的第二電壓V2通過第五開關Q5與第二列線532而被傳輸至第二電阻式非揮發性記憶體元件512的下電極BE，則第二電阻式非揮發性記憶體元件512會發生「設定」操作，使得第二電阻式非揮發性記憶體元件512的阻態改變為低阻態。由於第一電阻式非揮發性記憶體元件511的上電極TE與下電極BE之電壓均為高位準電壓HV，因此第一電阻式非揮發性記憶體元件511的阻態維持於高阻態。On the contrary, when the high level voltage HV is transmitted to the upper electrode TE of the second resistive non-volatile memory element 512 through the row programming line 520 and the first switch Q1, and the second voltage V2 having the low level voltage LV passes through The fifth switch Q5 and the second column line 532 are transmitted to the lower electrode BE of the second resistive non-volatile memory element 512, and the second resistive non-volatile memory element 512 is "set". The resistance state of the two-resistance non-volatile memory element 512 is changed to a low resistance state. Since the voltages of the upper electrode TE and the lower electrode BE of the first resistive non-volatile memory element 511 are both high level voltage HV, the resistance state of the first resistive non-volatile memory element 511 is maintained at a high resistance state.
若要將第一電阻式非揮發性記憶體元件511的阻態從低阻態重置（reset）為高阻態，則第一電壓V1可以被設定為低位準電壓LV；以及第二電壓V2可以被設定為抹除電壓EV（例如大於第一電阻式非揮發性記憶體元件511的閾電壓，但小於此閾電壓的兩倍）。第二電壓V2通過第五開關Q5與第二列線532而被傳輸至第二電阻式非揮發性記憶體元件512的下電極BE，而第一電壓V1將通過第三開關Q3與第一列線531而被傳輸至第一電阻式記憶體元件511的上電極TE。當抹除電壓EV通過行編程線520與第一開關Q1而被傳輸至第一電阻式非揮發性記憶體元件511的下電極BE時，第一電阻式記憶體元件511會發生「重置（reset）」操作，使得第一電阻式記憶體元件511的阻態從低阻態改變為高阻態。由於第二電阻式非揮發性記憶體元件512的上電極TE與下電極BE之電壓均為抹除電壓EV，因此第二電阻式非揮發性記憶體元件512的阻態不會改變。To reset the resistance state of the first resistive non-volatile memory element 511 from a low resistance state to a high resistance state, the first voltage V1 may be set to a low level voltage LV; and the second voltage V2 It may be set to erase voltage EV (eg, greater than the threshold voltage of first resistive non-volatile memory element 511, but less than twice this threshold voltage). The second voltage V2 is transmitted to the lower electrode BE of the second resistive non-volatile memory element 512 through the fifth switch Q5 and the second column line 532, and the first voltage V1 will pass through the third switch Q3 and the first column The line 531 is transferred to the upper electrode TE of the first resistive memory element 511. When the erase voltage EV is transmitted to the lower electrode BE of the first resistive non-volatile memory element 511 through the row programming line 520 and the first switch Q1, the first resistive memory element 511 is "reset" ( The operation "reset" causes the resistance state of the first resistive memory element 511 to change from a low resistance state to a high resistance state. Since the voltages of the upper electrode TE and the lower electrode BE of the second resistive non-volatile memory element 512 are both the erase voltage EV, the resistance state of the second resistive non-volatile memory element 512 does not change.
以此類推，若要將第二電阻式非揮發性記憶體元件512的阻態從低阻態重置（reset）為高阻態，則低位準電壓LV可以通過行編程線520與第一開關Q1而被傳輸至第二電阻式非揮發性記憶體元件512的上電極TE。由於第二電阻式非揮發性記憶體元件512的上電極TE與下電極BE之電壓分別為低位準電壓LV與抹除電壓EV，因此第二電阻式非揮發性記憶體元件512的阻態將從低阻態改變為高阻態。由於第一電阻式記憶體元件511的上電極TE與下電極BE之電壓均為低位準電壓LV，因此第一電阻式記憶體元件511的阻態不會改變。By analogy, if the resistance state of the second resistive non-volatile memory element 512 is reset from the low resistance state to the high resistance state, the low level voltage LV can pass through the row programming line 520 and the first switch. Q1 is transferred to the upper electrode TE of the second resistive non-volatile memory element 512. Since the voltages of the upper electrode TE and the lower electrode BE of the second resistive non-volatile memory element 512 are the low level voltage LV and the erase voltage EV, respectively, the resistance state of the second resistive non-volatile memory element 512 will be Change from low resistance to high resistance. Since the voltages of the upper electrode TE and the lower electrode BE of the first resistive memory element 511 are both the low level voltage LV, the resistance state of the first resistive memory element 511 does not change.
綜上所述，當場可編程閘陣列120在第一期間T1的編程期間中，第一開關Q1、第三開關Q3與第五開關Q5導通，第四開關Q4截止，而微控制單元110可以經由第一列線531、第二列線532與行編程線520將新功能（例如第二功能）所對應的阻態編程至第一電阻式非揮發性記憶體元件511或第二電阻式非揮發性記憶體元件512。編程期間中，由於閂鎖單元513的輸出端Q的輸出信號是無關於閂鎖單元513的資料輸入端D的輸入信號，因此閂鎖單元513可以保持輸出原先功能（例如第一功能）所對應的第一邏輯準位至第二開關Q2的控制端。新功能（例如第二功能）的編程，並不影響/中斷原先功能（例如第一功能）的進行。In summary, during the programming period of the first period T1, the first switch Q1, the third switch Q3 and the fifth switch Q5 are turned on, and the fourth switch Q4 is turned off, and the micro control unit 110 can be turned on. The first column line 531, the second column line 532 and the row programming line 520 program the resistance state corresponding to the new function (for example, the second function) to the first resistive non-volatile memory element 511 or the second resistive non-volatile Sexual memory element 512. During the programming period, since the output signal of the output terminal Q of the latch unit 513 is an input signal irrelevant to the data input terminal D of the latch unit 513, the latch unit 513 can maintain the output corresponding to the original function (for example, the first function). The first logic level is to the control end of the second switch Q2. The programming of new functions (such as the second function) does not affect/interrupt the progress of the original function (such as the first function).
當場可編程閘陣列120的閂鎖單元513在取樣期間時，也就是當控制信號線SL出現切換脈衝Stri時，第四開關Q4與第五開關Q5導通，而第一開關Q1與第三開關Q3為截止。在此取樣期間中，閂鎖單元513受閘門端E的信號的觸發而取樣資料輸入端D的輸入信號，也就是取樣第一電阻式非揮發性記憶體元件511與第二電阻式非揮發性記憶體元件512的分壓。舉例來說（但不限於此），在此取樣期間中，第一電壓V1與讀電壓Vr均被設定為系統電壓Vcc（例如小於第一電阻式非揮發性記憶體元件511的閾電壓），以及第二電壓V2與行編程線520的電壓均被設定為低位準電壓LV（例如接地電壓或0伏特）。當第一電阻式非揮發性記憶體元件511的阻態為高阻態而第二電阻式非揮發性記憶體元件512的阻態為低阻態時，閂鎖單元513在取樣期間通過資料輸入端D所取樣的邏輯值為0。當第一電阻式非揮發性記憶體元件511的阻態為低阻態以及第二電阻式非揮發性記憶體元件512的阻態為高阻態時，閂鎖單元513在取樣期間通過資料輸入端D所取樣的邏輯值為1。因此，場可編程閘陣列120在接收到切換脈衝Stri之後可以結束第一期間T1，並且即時地從原先功能（例如第一功能）切換至新功能（例如第二功能），而不需要額外的等待時間。When the latch unit 513 of the field programmable gate array 120 is in the sampling period, that is, when the switching signal Stri appears in the control signal line SL, the fourth switch Q4 and the fifth switch Q5 are turned on, and the first switch Q1 and the third switch Q3 are turned on. For the deadline. During this sampling period, the latch unit 513 is triggered by the signal of the gate terminal E to sample the input signal of the data input terminal D, that is, the first resistive non-volatile memory component 511 and the second resistive non-volatile sample. The partial pressure of the memory element 512. For example, but not limited to, during the sampling period, the first voltage V1 and the read voltage Vr are both set to the system voltage Vcc (eg, less than the threshold voltage of the first resistive non-volatile memory element 511), And the voltages of the second voltage V2 and the row programming line 520 are both set to a low level voltage LV (eg, ground voltage or 0 volts). When the resistance state of the first resistive non-volatile memory element 511 is a high resistance state and the resistance state of the second resistive non-volatile memory element 512 is a low resistance state, the latch unit 513 passes data input during sampling. The logical value sampled by terminal D is zero. When the resistance state of the first resistive non-volatile memory element 511 is a low resistance state and the resistance state of the second resistive non-volatile memory element 512 is a high resistance state, the latch unit 513 passes data input during sampling. The logical value sampled by terminal D is 1. Therefore, the field programmable gate array 120 may end the first period T1 after receiving the switching pulse Stri, and immediately switch from the original function (eg, the first function) to the new function (eg, the second function) without additional waiting time.
值得注意的是，功能可編程電路100可以在非取樣期間（保持期間）關閉閂鎖單元513的輸入端D，以使閂鎖單元513的輸出端Q維持輸出閂鎖單元513的取樣結果。因此，在非取樣期間中，且在非編程期間中，所有記憶區塊501A~501D的所有電阻式非揮發性記憶體元件的上電極TE與下電極BE可以不需供電，以減少分壓電路的漏電流，而有效降低功耗。It is to be noted that the function programmable circuit 100 can turn off the input terminal D of the latch unit 513 during the non-sampling period (holding period) so that the output terminal Q of the latch unit 513 maintains the sampling result of the output latch unit 513. Therefore, in the non-sampling period, and in the non-programming period, the upper electrode TE and the lower electrode BE of all the resistive non-volatile memory elements of all of the memory blocks 501A to 501D may not need to be supplied with power to reduce the partial piezoelectricity. The leakage current of the circuit effectively reduces power consumption.
請參考圖6，圖6繪示本發明一實施例之功能可編程電路的操作方法。於步驟S610中，於第一期間中，藉由場可編程閘陣列執行第一功能而與微控制單元相互協同工作，且同時由微控制單元將一第二功能編程至場可編程閘陣列中。於步驟S620中，由微控制單元輸出切換脈衝而結束第一期間，並使場可編程閘陣列從第一功能切換至第二功能，且於第二期間中執行第二功能而與微控制單元相互協同工作。有關於本實施例的操作方法可參閱前述實施例的內容，在此不再贅述。Please refer to FIG. 6. FIG. 6 illustrates an operation method of the functional programmable circuit according to an embodiment of the present invention. In step S610, in the first period, the first function is performed by the field programmable gate array to cooperate with the micro control unit, and at the same time, the second function is programmed into the field programmable gate array by the micro control unit. . In step S620, the micro-control unit outputs a switching pulse to end the first period, and switches the field programmable gate array from the first function to the second function, and performs the second function in the second period with the micro control unit. Work together. For the operation method of this embodiment, refer to the content of the foregoing embodiment, and details are not described herein again.
上述諸實施例所述微控制單元110與場可編程閘陣列120可以被應用於通訊裝置中。微控制單元110與場可編程閘陣列120可以提供底層（例如實體層，即Physical Layer）通訊功能。基於編程，場可編程閘陣列120可以具有通信介面，用來與遠端系統（另一個通訊裝置）進行資料傳輸。這兩個通訊裝置可以透過一個加密通信網路來相互交換資料。這兩個通訊裝置可以一直反覆更改通訊協定與/或其他功能，來提高通訊網路的資料傳輸的安全性。The micro control unit 110 and the field programmable gate array 120 described in the above embodiments may be applied to a communication device. The micro control unit 110 and the field programmable gate array 120 can provide an underlying (e.g., physical layer) communication function. Based on programming, the field programmable gate array 120 can have a communication interface for data transfer with a remote system (another communication device). The two communication devices can exchange data with each other through an encrypted communication network. These two communication devices can constantly change the communication protocol and/or other functions to improve the security of the data transmission of the communication network.
圖7是依照本發明一實施例繪示一種通訊系統700的電路方塊（circuit block）示意圖。圖7所示通訊系統700包括第一通訊裝置710以及第二通訊裝置720。第一通訊裝置710可以經由通訊網路730而與第二通訊裝置720建立連接。依照設計需求，通訊網路730可以是有線通訊網路或是無線通訊網路，其中所述有線通訊網路可以是乙太網路（Ethernet）、I2C（inter-integrated circuit）網路或是其他有線網路，而所述無線通訊網路可以是WiFi（Wireless Fidelity）網路、藍芽（bluetooth）或是其他無線網路。為了避免圖式內容過於複雜，圖7並沒有繪示習知的通訊元件，例如天線、調變電路等。FIG. 7 is a schematic diagram of a circuit block of a communication system 700 according to an embodiment of the invention. The communication system 700 shown in FIG. 7 includes a first communication device 710 and a second communication device 720. The first communication device 710 can establish a connection with the second communication device 720 via the communication network 730. According to design requirements, the communication network 730 can be a wired communication network or a wireless communication network, wherein the wired communication network can be an Ethernet, an I2 C (inter-integrated circuit) network, or other wired network. The wireless communication network can be a WiFi (Wireless Fidelity) network, a bluetooth or other wireless network. In order to avoid the complexity of the drawing content, FIG. 7 does not show a conventional communication component such as an antenna, a modulation circuit, or the like.
第一通訊裝置710包括微控制單元711以及場可編程閘陣列712。第二通訊裝置720包括微控制單元721以及場可編程閘陣列722。第一通訊裝置710與第二通訊裝置720可以參照圖1至圖6所述功能可編程電路100的相關說明來類推，微控制單元711與微控制單元721可以參照圖1至圖6所述微控制單元110的相關說明來類推，以及場可編程閘陣列712與場可編程閘陣列722可以參照圖1至圖6所述場可編程閘陣列120的相關說明來類推。基於編程，場可編程閘陣列712與場可編程閘陣列722可以具有通信介面，用來與遠端系統（另一個通訊裝置）進行資料傳輸。場可編程閘陣列712與場可編程閘陣列722可以透過通訊網路730來相互交換資料（例如經加密資料）。場可編程閘陣列712與場可編程閘陣列722可以基於編程而使用特定的通訊協定將資料（例如經加密資料）傳輸給對方。基於微控制單元711與微控制單元721的編程操作與控制，場可編程閘陣列712與場可編程閘陣列722可以一直反覆更改通訊協定，來提高通訊網路730的資料傳輸的安全性。The first communication device 710 includes a micro control unit 711 and a field programmable gate array 712. The second communication device 720 includes a micro control unit 721 and a field programmable gate array 722. The first communication device 710 and the second communication device 720 can be analogized with reference to the related description of the function programmable circuit 100 shown in FIG. 1 to FIG. 6. The micro control unit 711 and the micro control unit 721 can refer to FIG. 1 to FIG. The related description of control unit 110 is analogous, and field programmable gate array 712 and field programmable gate array 722 can be analogized with reference to the description of field programmable gate array 120 of FIGS. 1-6. Based on programming, the field programmable gate array 712 and the field programmable gate array 722 can have a communication interface for data transfer with the remote system (another communication device). The field programmable gate array 712 and the field programmable gate array 722 can exchange data (e.g., encrypted data) with each other via the communication network 730. Field programmable gate array 712 and field programmable gate array 722 can be used to transfer data (e.g., encrypted data) to each other using a particular communication protocol based on programming. Based on the programming operation and control of the micro control unit 711 and the micro control unit 721, the field programmable gate array 712 and the field programmable gate array 722 can repeatedly change the communication protocol to improve the security of the data transmission of the communication network 730.
圖8是依照本發明一實施例說明通訊裝置720的操作方法的流程示意圖。圖7所示第一通訊裝置710可以參照第二通訊裝置720的相關說明來類推，故不再贅述。請參照圖7與圖8。於第一期間中，場可編程閘陣列722執行第一通訊協定而與微控制單元721相互協同工作（步驟S810），以便與第一通訊裝置710進行通訊。在此同時（在相同的第一期間中）微控制單元721可以將第二通訊協定編程至場可編程閘陣列722中（步驟S810）。FIG. 8 is a flow chart showing a method of operating the communication device 720 according to an embodiment of the invention. The first communication device 710 shown in FIG. 7 can be analogized with reference to the related description of the second communication device 720, and therefore will not be described again. Please refer to FIG. 7 and FIG. 8. During the first period, the field programmable gate array 722 executes the first communication protocol and cooperates with the micro control unit 721 (step S810) to communicate with the first communication device 710. At the same time (in the same first period) the micro control unit 721 can program the second communication protocol into the field programmable gate array 722 (step S810).
圖9是依照本發明一實施例繪示圖7所示場可編程閘陣列722的操作時序示意圖。圖9所示橫軸表示時間。請同時參考圖7至圖9。於第一期間T1中，場可編程閘陣列722執行第一通訊協定P1，而微控制單元721可以進行工作J_P1，以便與微控制單元721相互協同工作，進而與第一通訊裝置710進行通訊。在此同時（在相同的第一期間T1中），微控制單元721在進行工作J_P1的時候亦可以同時進行工作P_P2，以便將第二通訊協定P2編程至場可編程閘陣列722中。第二通訊協定P2的編程，並不影響/中斷第一通訊協定P1的進行。FIG. 9 is a timing diagram showing the operation of the field programmable gate array 722 of FIG. 7 according to an embodiment of the invention. The horizontal axis shown in Fig. 9 represents time. Please refer to FIG. 7 to FIG. 9 at the same time. In the first period T1, the field programmable gate array 722 executes the first communication protocol P1, and the micro control unit 721 can perform the operation J_P1 to cooperate with the micro control unit 721 to communicate with the first communication device 710. At the same time (in the same first period T1), the micro control unit 721 can also simultaneously perform the operation P_P2 during the operation J_P1 to program the second communication protocol P2 into the field programmable gate array 722. The programming of the second communication protocol P2 does not affect/interrupt the progress of the first communication protocol P1.
於步驟S820中，場可編程閘陣列722受控於微控制單元721所輸出的切換脈衝Stri而結束所述第一期間T1而進入第二期間T2，並且場可編程閘陣列722從第一通訊協定P1切換至第二通訊協定P2。其中，對應第一通訊協定P1的阻態不同於對應第二通訊協定P2的阻態。於第二期間T2中，場可編程閘陣列722執行第二通訊協定P2，而微控制單元721可以進行工作J_P2，以便與微控制單元722相互協同工作，進而與第一通訊裝置710進行通訊。在此同時（在相同的第二期間T2中），微控制單元721在進行工作J_P2的時候亦可以同時進行工作P_P3，以便將第三通訊協定P3編程至場可編程閘陣列722中。第三通訊協定P3的編程，並不影響/中斷第二通訊協定P2的進行。In step S820, the field programmable gate array 722 is controlled by the switching pulse Stri output by the micro control unit 721 to end the first period T1 and enter the second period T2, and the field programmable gate array 722 is from the first communication. The agreement P1 is switched to the second communication protocol P2. The resistance state corresponding to the first communication protocol P1 is different from the resistance state corresponding to the second communication protocol P2. In the second period T2, the field programmable gate array 722 executes the second communication protocol P2, and the micro control unit 721 can perform the operation J_P2 to cooperate with the micro control unit 722 to communicate with the first communication device 710. At the same time (in the same second period T2), the micro control unit 721 can also simultaneously perform the operation P_P3 during the operation J_P2 to program the third communication protocol P3 into the field programmable gate array 722. The programming of the third communication protocol P3 does not affect/interrupt the progress of the second communication protocol P2.
依此類推，所述第二期間T2結束後進入第三期間T3。於第三期間T3中，場可編程閘陣列722執行第三通訊協定P3，而微控制單元721可以進行工作J_P3，以便與微控制單元722相互協同工作，進而與第一通訊裝置710進行通訊。在此同時（在相同的第三期間T3中），微控制單元721在進行工作J_P3的時候亦可以同時進行工作P_P4，以便將第四通訊協定編程至場可編程閘陣列722中。第四通訊協定的編程（亦即工作P_P4的進行），並不影響/中斷第三通訊協定P3的進行。And so on, after the end of the second period T2, the third period T3 is entered. In the third period T3, the field programmable gate array 722 executes the third communication protocol P3, and the micro control unit 721 can perform the operation J_P3 to cooperate with the micro control unit 722 to communicate with the first communication device 710. At the same time (in the same third period T3), the micro control unit 721 can also simultaneously perform the operation P_P4 when the operation J_P3 is performed in order to program the fourth communication protocol into the field programmable gate array 722. The programming of the fourth communication protocol (that is, the progress of the work P_P4) does not affect/interrupt the progress of the third communication protocol P3.
從圖9所示應用情境的範例可以知道，基於微控制單元721的編程操作與控制，場可編程閘陣列722可以一直反覆更改通訊協定，來提高通訊網路730的資料傳輸的安全性。在通信協定是動態改變的情況下，駭客難以監視（監聽）此通信網路。It can be seen from the example of the application scenario shown in FIG. 9 that based on the programming operation and control of the micro control unit 721, the field programmable gate array 722 can repeatedly change the communication protocol to improve the security of the data transmission of the communication network 730. In the case where the communication protocol is dynamically changed, it is difficult for the hacker to monitor (listen) the communication network.
值得注意的是，在不同的應用情境中，第一通訊裝置710、微控制單元711、場可編程閘陣列712、第二通訊裝置720、微控制單元721及/或場可編程閘陣列722的相關功能可以利用一般的編程語言（programming languages，例如C或C++）、硬體描述語言（hardware description languages，例如Verilog HDL或VHDL）或其他合適的編程語言來實現為軟體、韌體或硬體。可執行所述相關功能的編程語言可以被佈置為任何已知的計算機可存取媒體（computer-accessible medias），例如磁帶（magnetic tapes）、半導體（semiconductors）記憶體、磁盤（magnetic disks）或光盤（compact disks，例如CD-ROM或DVD-ROM），或者可通過互聯網（Internet）、有線通信（wired communication）、無線通信（wireless communication）或其它通信介質傳送所述編程語言。所述編程語言可以被存放在計算機的可存取媒體中，以便於由計算機的處理器來存取/執行所述軟體（或韌體）的編程碼（programming codes）。對於硬體實現，結合本文實施例所揭示的態樣，利用在一或多個控制器、微控制器、微處理器、特殊應用積體電路（Application-specific integrated circuit, ASIC）、數位訊號處理器（digital signal processor, DSP）、場可程式邏輯閘陣列（Field Programmable Gate Array, FPGA）及/或其他處理單元中的的各種示例性的邏輯、邏輯區塊、模組和電路可以被用於實現或執行本文所述功能。另外，本發明的裝置和方法可以通過硬體和軟體的組合來實現。It should be noted that, in different application scenarios, the first communication device 710, the micro control unit 711, the field programmable gate array 712, the second communication device 720, the micro control unit 721, and/or the field programmable gate array 722 Related functions can be implemented as software, firmware or hardware using a general programming language (such as C or C++), a hardware description language (such as Verilog HDL or VHDL), or other suitable programming language. The programming language that can perform the related functions can be arranged as any known computer-accessible media, such as magnetic tapes, semiconductors, magnetic disks, or optical disks. (compact disks, such as CD-ROM or DVD-ROM), or the programming language can be transmitted over the Internet, wired communication, wireless communication, or other communication medium. The programming language can be stored in an accessible medium of the computer such that the software (or firmware) programming codes are accessed/executed by the processor of the computer. For the hardware implementation, combined with the aspects disclosed in the embodiments, one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processing Various exemplary logic, logic blocks, modules, and circuits in a digital signal processor (DSP), Field Programmable Gate Array (FPGA), and/or other processing unit can be used Implement or perform the functions described in this article. Additionally, the apparatus and method of the present invention can be implemented by a combination of hardware and software.
綜上所述，本發明諸實施例所述的場可編程閘陣列可以由微控制單元所控制。於第一期間T1，微控制單元除了控制場可編程閘陣列執行第一通訊協定外，同時還對場可編程閘陣列進行第二通訊協定的編程。因此，當場可編程閘陣列接到由微控制單元的切換脈衝Stri時，場可編程閘陣列就能即時從第一通訊協定切換至第二通訊協定並結束第一期間T1，在切換中並不需耗費多餘的編程時間。因此，本發明諸實施例所述的通訊裝置可以一直反覆更改通訊協定，來提高通訊網路的資料傳輸的安全性。另外，本發明諸實施例所述的場可編程閘陣列的閂鎖單元可有效降低第一電阻式非揮發性記憶體元件與第二電阻式非揮發性記憶體元件的漏電流，以改善場可編程閘陣列的耗電情形。In summary, the field programmable gate array of the embodiments of the present invention can be controlled by a micro control unit. In the first period T1, the micro control unit performs the first communication protocol in addition to the control field programmable gate array, and also performs programming of the second communication protocol on the field programmable gate array. Therefore, when the field programmable gate array is connected to the switching pulse Stri of the micro control unit, the field programmable gate array can immediately switch from the first communication protocol to the second communication protocol and end the first period T1, which is not in the switching. It takes extra programming time. Therefore, the communication device according to the embodiments of the present invention can repeatedly change the communication protocol to improve the security of data transmission in the communication network. In addition, the latch unit of the field programmable gate array according to the embodiments of the present invention can effectively reduce the leakage current of the first resistive non-volatile memory component and the second resistive non-volatile memory component to improve the field. The power consumption of the programmable gate array.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100：功能可編程電路 110：微控制單元 120：場可編程閘陣列 501A、501B、501C、501D：記憶區塊 511：第一電阻式非揮發性記憶體元件 512：第二電阻式非揮發性記憶體元件 513：閂鎖單元 520：行編程線 531：第一列線 532：第二列線 541：輸入線 542：輸出線 700：通訊系統 710：第一通訊裝置 711：微控制單元 712：場可編程閘陣列 720：第二通訊裝置 721：微控制單元 722：場可編程閘陣列 730：通訊網路 A、B、C、D、E、F：工作 Bus1：編程匯流排 Bus2：互聯匯流排 J_P1、J_P2、J_P3：工作 FUNC_1、FUNC_2、FUNC_A、FUNC_B、FUNC_C：功能 LG1、LG2：邏輯閘 P_P2、P_P3、P_P4：工作 P1：第一通訊協定 P2：第二通訊協定 P3：第三通訊協定 PR1：第一控制信號 PR2：第二控制信號 Q1、Q2、Q3、Q4、Q5：開關 S610、S620、S810、S820：步驟 SL：控制信號線 Stri：切換脈衝 T1：第一期間 T2：第二期間 T3：第三期間 V1：第一電壓 V2：第二電壓 Vr：讀電壓100: function programmable circuit 110: micro control unit 120: field programmable gate array 501A, 501B, 501C, 501D: memory block 511: first resistive non-volatile memory element 512: second resistive non-volatile Memory element 513: latch unit 520: row programming line 531: first column line 532: second column line 541: input line 542: output line 700: communication system 710: first communication device 711: micro control unit 712: Field programmable gate array 720: second communication device 721: micro control unit 722: field programmable gate array 730: communication network A, B, C, D, E, F: work Bus1: programming bus Bus2: interconnect bus J_P1, J_P2, J_P3: work FUNC_1, FUNC_2, FUNC_A, FUNC_B, FUNC_C: function LG1, LG2: logic gate P_P2, P_P3, P_P4: work P1: first communication protocol P2: second communication protocol P3: third communication protocol PR1 : First control signal PR2: second control signal Q1, Q2, Q3, Q4, Q5: switch S610, S620, S810, S820: step SL: control signal line Stri: switching pulse T1: first period T2: second period T3: Phase III V1: first voltage V2: second voltage Vr: read voltage
圖1繪示本發明一實施例之功能可編程電路的方塊示意圖。 圖2是依照本發明一實施例繪示圖1所示功能可編程電路的操作時序示意圖。 圖3是依照本發明另一實施例繪示圖1所示場可編程閘陣列的操作情境示意圖。 圖4是依照本發明另一實施例繪示圖3所示之功能可編程電路的操作時序示意圖。 圖5是依照本發明一實施例繪示圖1所示場可編程閘陣列之電路結構示意圖。 圖6繪示本發明一實施例之功能可編程電路的操作方法。 圖7是依照本發明一實施例繪示一種通訊系統的電路方塊（circuit block）示意圖。 圖8是依照本發明一實施例說明一種通訊裝置的操作方法的流程示意圖。 圖9是依照本發明一實施例繪示圖7所示場可編程閘陣列的操作時序示意圖。1 is a block diagram of a functional programmable circuit in accordance with an embodiment of the present invention. FIG. 2 is a timing diagram showing the operation of the functional programmable circuit shown in FIG. 1 according to an embodiment of the invention. FIG. 3 is a schematic diagram showing the operation of the field programmable gate array of FIG. 1 according to another embodiment of the invention. FIG. 4 is a timing diagram showing the operation of the functional programmable circuit shown in FIG. 3 according to another embodiment of the invention. FIG. 5 is a schematic diagram showing the circuit structure of the field programmable gate array of FIG. 1 according to an embodiment of the invention. 6 is a diagram showing an operation method of a functional programmable circuit according to an embodiment of the present invention. FIG. 7 is a schematic diagram of a circuit block of a communication system according to an embodiment of the invention. FIG. 8 is a flow chart showing a method of operating a communication device according to an embodiment of the invention. FIG. 9 is a timing diagram showing the operation of the field programmable gate array of FIG. 7 according to an embodiment of the invention.
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| TW106117517ATWI647551B (en) | 2017-05-26 | 2017-05-26 | Communication device, communication system and operation method thereof |
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| TW106117517ATWI647551B (en) | 2017-05-26 | 2017-05-26 | Communication device, communication system and operation method thereof |
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| TW106117517ATWI647551B (en) | 2017-05-26 | 2017-05-26 | Communication device, communication system and operation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200503491A (en)* | 2003-05-16 | 2005-01-16 | Matsushita Electric Industrial Co Ltd | Transmitting/receiving apparatus, method, program, recording medium, and integrated circuit used in communication network |
| US20050177633A1 (en)* | 2002-12-02 | 2005-08-11 | Plunkett Richard T. | Timeslot arbitration scheme |
| US20090237113A1 (en)* | 2006-07-27 | 2009-09-24 | Panasonic Corporation | Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus |
| US8754670B2 (en)* | 2011-06-27 | 2014-06-17 | Samsung Electronics Co., Ltd. | Real time reconfigurable logic device and semiconductor package having the same |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050177633A1 (en)* | 2002-12-02 | 2005-08-11 | Plunkett Richard T. | Timeslot arbitration scheme |
| US20050213761A1 (en)* | 2002-12-02 | 2005-09-29 | Walmsley Simon R | Storing number and a result of a function on an integrated circuit |
| TW200503491A (en)* | 2003-05-16 | 2005-01-16 | Matsushita Electric Industrial Co Ltd | Transmitting/receiving apparatus, method, program, recording medium, and integrated circuit used in communication network |
| US20090237113A1 (en)* | 2006-07-27 | 2009-09-24 | Panasonic Corporation | Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus |
| US8754670B2 (en)* | 2011-06-27 | 2014-06-17 | Samsung Electronics Co., Ltd. | Real time reconfigurable logic device and semiconductor package having the same |
| Publication number | Publication date |
|---|---|
| TW201901325A (en) | 2019-01-01 |
| Publication | Publication Date | Title |
|---|---|---|
| TWI755218B (en) | Low power ferroelectric based majority logic gate adder | |
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