以下，參照圖式對實施形態進行說明。再者，於以下之說明中，對具有相同功能及構成之構成要素標註共用之參照符號。 1.第1實施形態 對第1實施形態之記憶系統進行說明。以下，列舉具備NAND(Not AND，反及)型快閃記憶體作為半導體記憶裝置之記憶系統為例進行說明。 1.1 關於構成 對本實施形態之NAND型快閃記憶體之構成進行說明。 1.1.1 關於整體構成 首先，使用圖1對本實施形態之NAND型快閃記憶體之大體之整體構成進行說明。 如圖所示，NAND型快閃記憶體1具備記憶胞陣列2、列解碼器3及讀出放大器4。 記憶胞陣列2具備複數個區塊BLK。於圖1中僅示出4個區塊BLK0～BLK3，但其數量並無限定。區塊BLK包含於列及行上建立關聯且三維地積層之複數個記憶胞。又，區塊BLK設置於半導體基板上，於相鄰之區塊間設置有狹縫SLT1。於下文中對記憶胞陣列2之構成之詳細內容進行敍述。 列解碼器3對自外部接收到之行地址進行解碼。然後，列解碼器3基於解碼結果選擇記憶胞陣列2之列方向。更具體而言，對用以選擇列方向之各種配線施加電壓。 讀出放大器4於讀取資料時，將自任一區塊BLK讀取之資料讀出。又，於寫入資料時，將與寫入資料對應之電壓施加至記憶胞陣列2。 1.1.2 關於記憶胞陣列2之構成 繼而，對本實施形態之記憶胞陣列2之構成進行說明。 ＜關於電路構成＞ 首先，使用圖2對記憶胞陣列2之電路構成進行說明。圖2係區塊BLK之等效電路圖。如圖所示，區塊BLK包含複數個記憶體組MG(MG0、MG1、MG2、…)。又，各個記憶體組MG包含複數個NAND串50。以下，將第偶數個記憶體組MGe(MG0、MG2、MG4、…)之NAND串稱為NAND串50e，將第奇數個記憶體組MGo(MG1、MG3、MG5、…)之NAND串稱為NAND串50o。 各個NAND串50例如包含8個記憶胞電晶體MT(MT0～MT7)及選擇電晶體ST1、ST2。記憶胞電晶體MT具備控制閘極與電荷累積層，將資料非揮發性地保存。而且，記憶胞電晶體MT串聯連接於選擇電晶體ST1之源極與選擇電晶體ST2之汲極之間。 各個記憶體組MGe中之選擇電晶體ST1之閘極分別連接於選擇閘極線SGD(SGD0、SGD1、…)。選擇閘極線SGD係由列解碼器3獨立地控制。又，各個第偶數個記憶體組MGe(MG0、MG2、…)中之選擇電晶體ST2之閘極例如共通連接於選擇閘極線SGSe，各個第奇數個記憶體組MGo(MG1、MG3、…)中之選擇電晶體ST2之閘極例如共通連接於選擇閘極線SGSo。選擇閘極線SGSe及SGSo例如可共通地連接，亦可獨立地控制。 又，同一區塊BLK內之記憶體組MGe中所包含之記憶胞電晶體MT(MT0～MT7)之控制閘極分別共通連接於字元線WLe(WLe0～WLe7)。另一方面，記憶體組MGo中所包含之記憶胞電晶體MT(MT0～MT7)之控制閘極分別共通連接於字元線WLo(WLo0～WLo7)。選擇閘極線WLe及WLo由列解碼器3獨立地控制。 區塊BLK例如為資料之刪除單位。即，同一區塊BLK內所包含之記憶胞電晶體MT所保持之資料被一次性刪除。 進而，於記憶胞陣列2內位於同一行之NAND串50之選擇電晶體ST1之汲極共通連接於位元線BL(BL0～BL(L－1)，其中(L－1)為2以上之自然數)。即，位元線BL於複數個記憶體組MG間將NAND串50共通地連接。進而，複數個選擇電晶體ST2之源極共通地連接於源極線SL。 即，記憶體組MG包含複數個連接於不同位元線BL且連接於同一選擇閘極線SGD之NAND串50。又，區塊BLK包含複數個共用字元線WL之複數個記憶體組MG。而且，記憶胞陣列2包含共用位元線BL之複數個區塊BLK。而且，於記憶胞陣列2內，藉由將上述選擇閘極線SGS、字元線WL及選擇閘極線SGD積層於半導體基板上方，而將記憶胞電晶體MT三維地積層。 ＜關於記憶胞陣列之平面佈局＞ 繼而，對記憶胞陣列2之平面構成進行說明。圖3表示某一區塊BLK之半導體基板面內(將其稱為XY平面)之選擇閘極線SGD之平面佈局。於本例中，對1個區塊BLK內包含8條選擇閘極線SGD之情形進行說明。 如圖所示，沿X方向延伸之9個導電層10(10-0～10-7，其中10-0包含10-0a與10-0b)沿著與X方向正交之Y方向排列。各導電層10作為選擇閘極線SGD發揮功能。若是圖3之示例，則區塊BLK內位於沿著Y方向之兩端之2個配線層10-0a及10-0b係作為選擇閘極線SGD0發揮功能。即，位於Y方向上之兩端之2個配線層10相互共通地連接，或者藉由列解碼器3以相同之方式予以控制。而且，位於該等之間之7個配線層10-1～10-7分別作為選擇閘極線SGD1～SGD7發揮功能。因此，於在區塊BLK內以XY平面進行觀察之情形時，記憶體組MG1～MG7沿著Y方向排列，且於其兩側配置有記憶體組MG0。 區塊BLK內於Y方向上相鄰之配線層10係藉由未圖示之絕緣膜隔開。將設置有該絕緣膜之區域稱為狹縫SLT2。於狹縫SLT2中，絕緣膜將例如自半導體基板面至少到設置有配線層10之層為止之區域埋入。又，於記憶胞陣列2內，例如於Y方向上排列有複數個圖3所示之區塊BLK。而且，於Y方向上相鄰之區塊BLK間亦藉由未圖示之絕緣膜隔開。設置有該絕緣膜之區域為圖1中所述之狹縫SLT1。狹縫SLT1亦與SLT2相同。 進而，於在Y方向上相鄰之配線層10間設置有分別沿著Z方向之複數個記憶柱MP(MP0～MP15)。Z方向係與XY方向正交之方向，即與半導體基板面垂直之方向。 具體而言，於配線層10-1與10-2之間設置有記憶柱MP0及MP8，於配線層10-3與10-4之間設置有記憶柱MP1及MP9，於配線層10-5與10-6之間設置有記憶柱MP2及MP10，於配線層10-7與10-0b之間設置有記憶柱MP3及MP11。記憶柱MP係形成選擇電晶體ST1及ST2以及記憶胞電晶體MT之結構體，其詳細內容將於下文中進行敍述。 記憶柱MP0～MP3沿著Y方向排列。又，記憶柱MP8～MP11以於X方向上與記憶柱MP0～MP3相鄰之方式沿著Y方向排列。即，記憶柱MP0～MP3與記憶柱MP8～MP11並排地排列。 而且，位元線BL0係以共通地連接於記憶柱MP0～MP3之方式設置於配線層10之上方。又，位元線BL2係以共通地連接於記憶柱MP8～MP11之方式設置於配線層10之上方。以下，有時將記憶柱MP0～MP3及記憶柱MP8～MP11、以及位元線BL0及BL2稱為組GR1。 又，於配線層10-0a與10-1之間設置有記憶柱MP4及MP12，於配線層10-2與10-3之間設置有記憶柱MP5及MP13，於配線層10-4與10-5之間設置有記憶柱MP6及MP14，於配線層10-6與10-7之間設置有記憶柱MP7及MP15。 記憶柱MP4～MP7沿著Y方向排列，記憶柱MP12～MP15亦沿著Y方向排列。而且，記憶柱MP4～MP7於X方向上位於記憶柱MP0～MP3與記憶柱MP8～MP11之間。又，記憶柱MP12～MP15以於X方向上與記憶柱MP4～MP7一起將記憶柱MP8～MP11夾於其間之方式而設。即，記憶柱MP4～MP7與記憶柱MP12～MP15並排地排列。 而且，位元線BL1係以共通地連接於記憶柱MP4～MP7之方式設置於配線層10之上方。又，位元線BL3係以共通地連接於記憶柱MP12～MP15之方式設置於配線層10之上方。以下，有時將記憶柱MP4～MP7及記憶柱MP12～MP15、以及位元線BL1及BL3稱為組GR2。 即，記憶柱MP係以於Y方向上橫跨2個配線層10且埋入到任一狹縫SLT2之一部分之方式設置，且於Y方向上相鄰之記憶柱MP間存在1個狹縫SLT2。而且，供屬於組GR1之記憶柱MP埋入之狹縫SLT2位於屬於組GR2之2個記憶柱MP間，供屬於組GR2之記憶柱MP埋入之狹縫SLT2位於屬於組GR1之2個記憶柱MP間。 再者，於隔著狹縫SLT1而相鄰之配線層10-0a與10-0b之間並未設置記憶柱MP。 圖4與圖3同樣地，表示XY平面內之字元線WL之平面佈局。圖4與圖3之1區塊大小之區域對應，且係設置於比圖3中所說明之配線層10更靠下層之配線層11之佈局。 如圖所示，沿X方向延伸之9個導電層11(11-0～11-7，其中11-0包含11-0a與11-0b)沿著Y方向排列。各配線層11-0～11-7隔著絕緣膜設置於配線層10-0～10-7之正下方。 各導電層10作為字元線WL7發揮功能。其他字元線WL0～WL6亦相同。若是圖4之示例，則配線層11-0a、11-3、11-5、11-7、及11-0b作為字元線WLo7發揮功能。而且，該等配線層11-0a、11-3、11-5、11-7、及11-0b被引出至沿著X方向之端部(將該端部稱為第1連接部)，且相互共通地連接。而且，於第1連接部，配線層11-0a、11-3、11-5、11-7、及11-0b連接於列解碼器3。 又，配線層11-1、11-3、11-5、及11-7作為字元線WLe7發揮功能。而且，該等配線層11-1、11-3、11-5、及11-7被引出至於X方向上位於與第1連接部為相反側之第2連接部，且相互共通地連接。而且，於第2連接部，配線層11-1、11-3、11-5、及11-7連接於列解碼器3。 而且，於第1連接部與第2連接部之間設置有記憶胞部。於記憶胞部中，於Y方向上相鄰之配線層11係藉由圖3中所說明之狹縫SLT2隔開。又，於Y方向上相鄰之區塊BLK間之配線層11亦同樣地藉由狹縫SLT1隔開。又，於記憶胞部中，以與圖3相同之方式設置有記憶柱MP0～MP15。 上述構成於其他形成字元線WL及選擇閘極線SGS之層中亦相同。 ＜關於記憶胞陣列之剖面結構＞ 繼而，對記憶胞陣列2之剖面結構進行說明。圖5係沿著Y方向之區塊BLK之剖視圖，且示出沿著圖3中之位元線BL0之區域之剖面結構作為一例。 如圖所示，於半導體基板(例如p型井區域)13之上方，設置作為選擇閘極線SGS發揮功能之配線層12。於配線層12之上方，沿著Z方向積層作為字元線WL0～WL7發揮功能之8層配線層11。該等配線11及12之平面佈局為圖4。而且，於配線層11之上方設置作為選擇閘極線SGD發揮功能之配線層10。配線層10之平面佈局如圖3中所說明。 而且，以自配線層10到達至半導體基板13之方式將狹縫SLT2與記憶柱MP沿著Y方向交替地設置。如上所述，狹縫SLT2之實體為絕緣膜。然而，亦可將用以對設置於半導體基板13內之區域施加電壓之接觸插塞等設置於狹縫SLT2內。例如，亦可設置用以將選擇電晶體ST2之源極連接於源極線之接觸插塞。 而且，配線層12將狹縫SLT2或記憶柱MP夾於其間而交替地作為選擇閘極線SGSo或SGSe發揮功能。同樣地，配線層11將狹縫SLT2或記憶柱MP夾於其間而交替地作為字元線WLo或WLe發揮功能。 又，於在Y方向上相鄰之區塊BLK間設置有狹縫SLT1。如上所述，狹縫SLT1之實體亦為絕緣膜。然而，亦可將用以對設置於半導體基板13內之區域施加電壓之接觸插塞等設置於狹縫SLT1內。例如，亦可設置用以將選擇電晶體ST2之源極連接於源極線之接觸插塞或者槽形狀之導體。再者，狹縫SLT1沿著Y方向之寬度大於狹縫SLT2沿著Y方向之寬度。 而且，於記憶柱MP上設置有接觸插塞16，且以共通地連接於該等接觸插塞16之方式將作為位元線BL發揮功能之配線層15沿著Y方向設置。 圖6係沿著X方向之區塊BLK之剖視圖，示出沿著圖3中之選擇閘極線SGD3且通過記憶柱MP5及MP13之區域之剖面結構作為一例。如圖5中說明所述，於半導體基板13上方依次設置有配線層12、11、及10。關於記憶胞部，如使用圖5說明所述。 於第1連接部，配線層10～12例如呈階梯狀被引出。即，當以XY平面進行觀察時，7層配線層10及配線層12之端部上表面於第1連接部露出。而且，於該露出之區域上設置有接觸插塞17，且接觸插塞17連接於金屬配線層18。而且，藉由該金屬配線層18，使作為偶數選擇閘極線SGD0、SGD2、SGD4、及SGD6、偶數字元線WLo及偶數選擇閘極線SGSo發揮功能之配線層10～12電性連接於列解碼器3。 另一方面，於第2連接部，以相同之方式將配線層11及12例如呈階梯狀引出。而且，於配線層11及12所露出之區域上設置有接觸插塞19，且接觸插塞19連接於金屬配線層20。而且，藉由該金屬配線層20，使作為奇數選擇閘極線SGD1、SGD3、SGD5、及SGD7、奇數字元線WLe及奇數選擇閘極線SGSe發揮功能之配線層11及12電性連接於列解碼器3。再者，配線層10可經由第2連接部來代替第1連接部而電性連接於列解碼器3，亦可經由第1連接部及第2連接部兩者而連接。 ＜關於記憶柱及記憶胞電晶體之結構＞ 繼而，對記憶柱MP及記憶胞電晶體MT之結構進行說明。 ・關於第1例 首先，使用圖7及圖8對第1例進行說明。圖7係記憶柱MP之XY平面內之剖視圖，圖8係YZ平面內之剖視圖，尤其示出設置有2個記憶胞電晶體MT之區域。又，第1例係於記憶胞電晶體MT之電荷累積層使用絕緣膜。 如圖所示，記憶柱MP包含沿著Z方向設置之絕緣層30、半導體層31、及絕緣層32至34。絕緣層30例如為氧化矽膜。半導體層31係以包圍絕緣層30之周圍之方式設置，且作為供形成記憶胞電晶體MT之通道之區域發揮功能。半導體層31例如為多晶矽層。絕緣層32係以包圍半導體層31之周圍之方式設置，且作為記憶胞電晶體MT之閘極絕緣膜發揮功能。絕緣層32例如具有氧化矽膜與氮化矽膜之積層結構。絕緣層33係以包圍半導體層31之周圍之方式設置，且作為記憶胞電晶體MT之電荷累積層發揮功能。絕緣層33例如為氮化矽膜。絕緣層34係以包圍絕緣層33之周圍之方式設置，且作為記憶胞電晶體MT之阻擋絕緣膜發揮功能。絕緣層34例如為氧化矽膜。於除記憶柱MP部以外之狹縫SLT2內埋入有絕緣層37。絕緣層37例如為氧化矽膜。 而且，於上述構成之記憶柱MP之周圍設置有例如AlO層35。於AlO層35之周圍形成有例如屏蔽金屬層(TiN膜等)36。於屏蔽金屬層36之周圍設置作為字元線WL發揮功能之導電層11。導電層11例如將鎢設置成材料。 根據上述構成，於1個記憶柱MP內，沿著Y方向設置有2個記憶胞電晶體MT。選擇電晶體ST1及ST2亦具有相同之構成。 ・關於第2例 繼而，使用圖9及圖10對第2例進行說明。圖9係記憶柱MP之XY平面內之剖視圖，圖10係YZ平面內之剖視圖，尤其示出設置有2個記憶胞電晶體MT之區域。第2例係於記憶胞電晶體MT之電荷累積層使用導電膜。 如圖所示，記憶柱MP包含沿著Z方向設置之絕緣層48及43、半導體層40、絕緣層41、導電層42、及絕緣層46a～46c。絕緣層48例如為氧化矽膜。半導體層40係以包圍絕緣層43-1之周圍之方式設置。半導體層40例如為多晶矽層，且作為供形成記憶胞電晶體MT之通道之區域發揮功能，與圖7之示例同樣地，於位於同一記憶柱MP內之記憶胞電晶體MT間未被分離。絕緣層41設置於導電層40之周圍，作為各記憶胞電晶體MT之閘極絕緣膜發揮功能。即，絕緣層41於圖9所示之XY平面內被分離為2個區域，且分別作為同一記憶柱MP內之2個記憶胞電晶體MT之閘極絕緣膜發揮功能。絕緣層41例如具有氧化矽膜與氮化矽膜之積層結構。導電層42設置於絕緣層41之周圍，且沿著Y方向由絕緣層43分離成2個區域。導電層42例如為多晶矽層，被分離而成之2個區域分別作為上述2個記憶胞電晶體MT各自之電荷累積層發揮功能。又，絕緣層43例如為氧化矽膜。於導電層42之周圍依次設置有絕緣層46a、46b、及46c。絕緣層46a及46c例如為氧化矽膜，絕緣層46b例如為氮化矽膜，該等作為記憶胞電晶體MT之阻擋絕緣膜發揮功能。該等絕緣層46a～46b亦沿著Y方向被分離成2個區域，且於該等之間設置有絕緣層43。又，絕緣層43被埋入至狹縫SLT2內。絕緣層43例如為氧化矽膜。 而且，於上述構成之記憶柱MP之周圍設置有例如AlO層45。進而，於AlO層45之周圍形成有例如屏蔽金屬層(TiN膜等)47。而且，於屏蔽金屬層47之周圍設置有作為字元線WL發揮功能之導電層11。 根據上述構成，於1個記憶柱MP內，沿著Y方向設置有2個記憶胞電晶體MT。選擇電晶體ST1及ST2亦具有相同之構成。再者，於在Z方向上相鄰之記憶胞電晶體間設置有未圖示之絕緣層，藉由該絕緣層與絕緣層43及46，而使電荷累積層42與各個記憶胞電晶體之每一個絕緣。 ・關於等效電路 圖11係上述構成之記憶柱MP之等效電路圖。如圖所示，於1根記憶柱MP形成有2個NAND串50o及50e。即，設置於同一記憶柱MP之選擇電晶體ST1連接於互不相同之選擇閘極線SGD，記憶胞電晶體MT連接於互不相同之字元線WLo及WLe，選擇電晶體ST2亦連接於互不相同之選擇閘極線SGSo及SGSe。而且，同一記憶柱MP內之2個NAND串50o及50e連接於同一位元線BL，又，連接於同一源極線SL。但是，電流路徑相互電分離。 1.2 關於讀出動作 繼而，對上述構成之NAND型快閃記憶體中之資料之讀出方法進行說明。 首先，使用圖12及圖13對選擇閘極線SGD被選擇之狀態進行說明。圖12及圖13係上文中所說明之與圖3對應之XY平面內之選擇閘極線SGD之平面佈局圖，且對與所選擇之選擇閘極線SGD對應之配線層10標註斜線而表示。 如圖12所示，當選擇閘極線SGD1～SGD7中之任一個被選擇時，選擇對應之1個配線層10-1～10-7中之任一個。於圖12中示出選擇閘極線SGD1被選擇之情形。藉由選擇配線層10-1，而選擇設置於記憶柱MP0、MP4、MP8、及MP12之4個記憶胞電晶體MT。即，藉由屬於設置於配線層10-1正下方之與任一字元線WL對應之配線層11-1之4個記憶胞電晶體MT形成1頁。該情況於選擇閘極線SGD2～SGD7被選擇之情形時亦同樣。 相對於此，於區塊BLK內位於兩端之配線層10-0a及10-0b兩者同時被選擇。該情況相當於選擇閘極線SGD0被選擇之情況。將該狀態示於圖13。 如圖所示，當選擇閘極線SGD0被選擇時，選擇位於配線層10-0a正下方且設置於記憶柱MP4及MP12之2個記憶胞電晶體MT與位於配線層10-0b正下方且設置於記憶柱MP3及MP11之2個記憶胞電晶體MT。即，藉由該等4個記憶胞電晶體MT形成1頁。 圖14係表示選擇第奇數條選擇閘極線SGDo(即第奇數個記憶體組MG)及字元線WLo0時之各種配線之電壓變化之時序圖。 如圖所示，首先，於時刻t1，對選擇區塊BLK中之所有選擇閘極線SGD施加電壓VSG，將選擇電晶體ST1設為接通狀態。進而，對所有字元線施加電壓VREAD，不論保持資料如何均將記憶胞電晶體MT設為接通狀態。進而，對所有選擇閘極線SGS施加電壓VSG，將選擇電晶體ST2設為接通狀態。藉此，於選擇區塊BLK中，所有NAND串50成為導通狀態，並將VSS(例如0 V)傳輸至通道。 繼而，於時刻t3，讀出放大器4對位元線BL進行預充電。此時，屬於組GR1之偶數位元線BL0及BL2被預充電至電壓VBL2，屬於組GR2之奇數位元線BL1及BL3被預充電至大於電壓VBL2之電壓VBL1。 然後，於時刻t4，對所選擇之選擇閘極線SGD及SGSo施加電壓VSG，對選擇字元線WLo0施加讀出電壓VCGRV，對非選擇字元線WLe0施加電壓VNEG，且施加其他非選擇字元線WL1～WL7。電壓VCGRV係與讀出位準對應之電壓，且係用以判斷所選擇之記憶胞電晶體MT之保持資料為“0”抑或是“1”之電壓。電壓VNEG例如為負電壓或0 V，係用以使記憶胞電晶體MT斷開之電壓。 以上之結果為，若所選擇之記憶胞電晶體MT接通，則電流便會自位元線BL流至源極線SL，若所選擇之記憶胞電晶體MT斷開，則不會流通電流。藉此，可判斷所選擇之記憶胞電晶體MT之保持資料。 1.3 本實施形態之效果 根據本實施形態，可修正記憶體組MG間之記憶胞特性之偏差，從而提高半導體記憶裝置之動作可靠性。以下對本效果進行說明。 若為本實施形態之半導體記憶裝置，則如圖3及圖4說明所述，1根記憶柱MP係以橫跨於XY平面內排列之2條選擇閘極線SGD及2條字元線WL之方式設置。而且，於該記憶柱MP內設置有2個記憶胞電晶體MT，並係由上述2條選擇閘極線SGD及字元線WL控制。 而且，若為本構成，則存在記憶柱MP與對應之2條字元線WL(及選擇閘極線SGD)之位置關係產生偏差之情形。更具體而言，於圖3及圖4中，於著眼於某一記憶柱MP之情形時，較理想為記憶柱MP之Y方向上之中央部位於對應之2條字元線之正中間。其原因在於藉由以此種方式配置記憶柱MP，而由對應之2條字元線WL控制之2個記憶胞電晶體MT之尺寸變得相等。 然而，若記憶柱MP之位置發生偏移，則對應之2個記憶胞電晶體MT之尺寸不同。例如，若為圖3及圖4之示例，則記憶柱MP沿著Y方向朝配線層10-0a側偏移。其結果為，當著眼於配線層10-1及11-1與記憶柱MP0及MP4時，記憶柱MP0與配線層10-1及11-1重疊距離d1，記憶柱MP4與配線層10-1及11-1重疊距離d2，且存在d1＞d2之關係。該情況於記憶柱MP8及MP12之間亦存在相同之關係。 即，於著眼於記憶體組MG1之情形時，連接於偶數位元線BLe之記憶胞電晶體MT之單元尺寸較大，連接於奇數位元線BLo之記憶胞電晶體MT之單元尺寸較小。單元尺寸之大小亦可說成是記憶胞電晶體MT之電流驅動能力之大小。 即，根據圖3可明確，於選擇了第偶數條選擇閘極線SGDe之情形時，連接於位元線BL0及BL2之記憶胞電晶體MT、即屬於組GR1之記憶胞電晶體MT之尺寸較小。另一方面，連接於位元線BL1及BL3之記憶胞電晶體MT、即屬於組GR2之記憶胞電晶體之尺寸較大。 相反，於選擇了第奇數條選擇閘極線SGDo之情形時，連接於位元線BL0及BL2之記憶胞電晶體MT、即屬於組GR1之記憶胞電晶體MT之尺寸較大。另一方面，連接於位元線BL1及BL3之記憶胞電晶體MT、即屬於組GR2之記憶胞電晶體之尺寸較小。 如上所述，當記憶柱MP之位置發生偏移時，於同一頁內，尺寸不同之記憶胞電晶體MT交替地排列。因此，於本實施形態中，讀出放大器4根據所選擇之記憶胞電晶體MT之尺寸而控制讀出動作時之預充電電位。 更具體而言，當選擇第偶數條選擇閘極線SGDe、即第偶數個記憶體組MGe時，讀出放大器4對組GR1之位元線BL施加較大之預充電電位VBL1，對組GR2之位元線BL施加較小之預充電電位VBL2。另一方面，當選擇第奇數條選擇閘極線SGDo、即第奇數個記憶體組MGo時，讀出放大器4對組GR1之位元線BL施加較小之預充電電位VBL2，對組GR2之位元線BL施加較大之預充電電位VBL1。 其結果為，可利用預充電電位抵消因記憶胞電晶體MT之單元尺寸所產生之電流驅動力之差，從而可減小於讀出動作時流至位元線BL之單元電流於位元線間之差量。即，對不易流通單元電流之記憶胞電晶體MT賦予流通足夠大之單元電流之條件，對易於流通單元電流之記憶胞電晶體MT賦予抑制單元電流之條件。藉此，可抑制尤其來自不易流通單元電流之記憶胞電晶體MT之誤讀出之產生，從而可提高半導體記憶裝置之動作可靠性。 又，若為本實施形態之構成，則如圖3所示，位於區塊BLK之兩端部之配線層10-0a及10-0b同時被選擇，且均作為選擇閘極線SGD0發揮功能。其原因在於在其他配線層10-1～10-7分別形成有4個記憶柱MP(記憶胞電晶體MT)，相對於此，於配線層10-0a及10-0b分別僅形成有2個記憶柱MP(記憶胞電晶體MT)。因此，關於區塊BLK之兩端部，使2個配線層10-0a及10-0b作為1條選擇閘極線SGD電性地發揮功能，藉此，即便於選擇了選擇閘極線SGD0時，亦能使1頁之尺寸與選擇了其他選擇閘極線SGD1～SGD7之情形時相同。 而且，以如上方式使頁尺寸一致之結果為，如圖3所示，於1個區塊BLK內作為選擇閘極線SGD發揮功能之配線層10之個數於XY平面內成為奇數個。該情況對於如圖4所示般作為字元線WL發揮功能之配線層11而言亦相同。換言之，當以XY平面進行觀察時，位於狹縫SLT1間之配線層之數量成為奇數個。 再者，記憶柱MP之偏移方式亦可為與圖3及圖4相反之情形。將該情形時之狀態示於圖15。圖15表示本實施形態之變化例之選擇閘極線SGD之平面佈局。如圖所示，本例中，記憶柱MP之位置與圖3之情形相反，係沿著Y方向朝配線層10-0b側偏移。其結果為，當著眼於配線層10-1及11-1與記憶柱MP0及MP4時，記憶柱MP0與配線層10-1及11-1重疊距離d2，記憶柱MP4與配線層10-1及11-1重疊距離d1。於該情況下，於讀出時施加至位元線BL之電壓與上述實施形態之情形相反。 即，當選擇第偶數條選擇閘極線SGDe、即第偶數個記憶體組MGe時，讀出放大器4對組GR1之位元線BL施加較小之預充電電位VBL2，對組GR2之位元線BL施加較大之預充電電位VBL1。另一方面，當選擇第奇數條選擇閘極線SGDo、即第奇數個記憶體組MGo時，讀出放大器4對組GR1之位元線BL施加較大之預充電電位VBL1，對組GR2之位元線BL施加較小之預充電電位VBL2。 2.第2實施形態 繼而，對第2實施形態之半導體記憶裝置進行說明。本實施形態係關於上述第1實施形態中之寫入動作。以下，僅對與第1實施形態不同之方面進行說明。 2.1第1例 首先，對第1例進行說明。資料之寫入動作包含：編程動作，其將電子注入至電荷累積層而使閾值變化；及編程驗證動作，其確認編程動作之結果、即閾值是否達到規定值。第1例係於編程動作中，使施加至位元線BL之電壓於組GR1與GR2中不同。 圖16係表示於資料寫入時選擇第奇數條選擇閘極線SGDo(即第奇數個記憶體組MG)及字元線WLo0時之各種配線之電壓變化之時序圖。 如圖12及圖13所示，於選擇第奇數條選擇閘極線SGDo之情形時，屬於組GR1(BL0、BL2)之記憶胞電晶體MT之尺寸較大，屬於組GR2(BL1、BL3)之記憶胞電晶體MT較小。由於字元線WL與記憶柱MP之重疊面積越大則耦合比越大，故而記憶胞電晶體MT之寫入速度越快。即，組GR1之寫入速度較快，組GR2較慢。 因此，於時刻t2，讀出放大器4對屬於組GR1之位元線BL0及BL2施加相對較高之電壓VCH2，對屬於組GR2之位元線BL1及BL3施加低之電壓VCH1。當然，VCH2＞VCH1。 接下來，於時刻t3，列解碼器3對所有字元線WL0～WL7施加電壓VPASS，進而於時刻t5使選擇字元線WLo0之電壓自VPASS上升到VPGM。電壓VPASS係不論保持資料如何均使記憶胞電晶體MT接通且於非選擇之NAND串50中可藉由耦合使通道電位充分地上升之電壓。又，電壓VPGM係用以藉由FN(Fowler-Nordheim，福勒-諾德海姆)穿遂將電子注入至電荷累積層之高電壓，且VPGM＞VPASS。 根據本方法，藉由增高與寫入速度較高之記憶胞電晶體MT對應之位元線電壓，可降低其寫入速度。藉此，可降低組GR1與GR2之間之寫入速度之差。 2.2第2例 繼而，對第2例進行說明。第2例係於編程動作時，於組GR1與GR2中改變施加至選擇字元線WL之電壓VPGM之值。 圖17係表示本例之選擇字元線WL及位元線BL之電位變化之時序圖，且表示選擇了第偶數個記憶體組MG、即第偶數條選擇閘極線SGDe之情形。 如上所述，寫入動作包含編程動作與編程驗證動作。將該組合稱為編程循環。而且，於寫入動作中，藉由將編程循環反覆進行多次而寫入1頁量之資料。 若為本例，則於編程動作時，對選擇字元線WL施加2種編程電壓VPGM1及VPGM2，且存在VPGM2＞VPGM1之關係。於選擇了第偶數個記憶體組MG之情形時，屬於組GR1(BL0、BL2)之記憶胞電晶體MT之寫入速度較慢，屬於組GR2(BL1、BL3)之記憶胞電晶體MT之寫入速度較快。因此，電壓VPGM1被用作組GR2用之編程電壓，電壓VPGM2被用作組GR1用之編程電壓。 具體而言，於施加電壓VPGM1之期間內，對組GR1之位元線BL0、BL2施加寫入禁止電壓VBL，對組GR2之位元線BL1、BL3施加寫入電壓(例如為0 V，小於VBL之電壓)。其結果為，資料被編程至連接於位元線BL1及BL3之記憶胞電晶體MT。 另一方面，於施加電壓VPGM2之期間內，對組GR2之位元線BL1、BL3施加寫入禁止電壓VBL，對組GR1之位元線BL0、BL2施加寫入電壓。其結果為，資料被編程至連接於位元線BL0及BL2之記憶胞電晶體MT。 根據本方法，對寫入速度較慢之記憶胞電晶體MT使用較高之編程電壓，對寫入速度較快之記憶胞電晶體使用較低之編程電壓。藉此，可降低組GR1與GR2之間之寫入速度之差。再者，亦可於組GR1與GR2中改變編程電壓VPGM之升壓幅度△VPGM。當然，於寫入速度較慢之組中，將 △VPGM設為較大。 2.3第3例 繼而，對第3例進行說明。第3例係於編程驗證動作時，降低對寫入速度較慢之組之預充電電位，藉此使單元電流相對地減少。即，對位元線BL施加電壓之方法與第1實施形態中所說明之圖14相同。 根據本方法，於寫入速度較慢之記憶胞電晶體中，隨著將編程循環反覆進行多次而單元之閾值變高，從而變得不易流通單元電流，因此容易通過編程驗證。其結果為，可降低組GR1與GR2之間之寫入速度之差。 2.4本實施形態之效果 根據本實施形態，即便於寫入速度於屬於同一頁之記憶胞電晶體間不同之情形時，亦可使該等通過編程驗證所需之編程循環數為相同程度。因此，可削減編程循環次數，從而可提高買入速度。又，可抑制寫入速度較快之記憶胞電晶體迅速地通過編程驗證之後長時間地受到向寫入速度較慢之記憶胞電晶體進行寫入動作所產生之干擾等，從而亦可提高寫入動作可靠性。 3.第3實施形態 繼而，對第3實施形態之半導體記憶裝置進行說明。本實施形態係關於與上述第1及第2實施形態不同之平面佈局，作為一例，於1個記憶柱上設置有2條位元線。以下，僅對與第1及第2實施形態不同之方面進行說明。 3.1關於平面佈局 圖18及圖19表示某一區塊BLK之XY平面內之選擇閘極線SGD之平面佈局。圖18與第1實施形態中所說明之圖3對應，亦示出位元線BL之狀態。於圖19中，將記憶胞部之圖示簡化，尤其著眼於第1連接部及第2連接部之構成。又，於本例中，對於1個區塊BLK內包含4條選擇閘極線SGD之情形進行說明。 如圖所示，於本例中亦與圖3中所說明之構成同樣地，包含沿X方向延伸之9個導電層10。惟於本例中，將圖3中所說明之配線層10-1～10-7及10-0b分別改稱為配線層10-1a、10-2a、10-3a、10-0b、10-1b、10-2b、10-3b、及10-0c。於各配線層10之間設置有狹縫SLT2之方面亦與第1實施形態相同。 而且，於區塊BLK內位於沿著Y方向之兩端之2個配線層10-0a及10-0c以及位於中央之配線層10-0b作為選擇閘極線SGD0發揮功能。該等3個配線層10-0如圖19所示，例如於第1連接部中藉由接觸插塞49及金屬配線層51而相互共通地連接，進而連接於列解碼器3。又，配線層10-1a與10-2b於第2連接部中藉由接觸插塞52及金屬配線層53而共通地連接，進而連接於列解碼器3。進而，配線層10-2a與10-2b於第2連接部中藉由接觸插塞52及金屬配線層53而共通地連接，進而連接於列解碼器3。而且，配線層10-3a與10-3b於第1連接部中藉由接觸插塞49及金屬配線層51共通地連接，進而連接於列解碼器3。 又，如圖18所示，2條位元線BL通過1個記憶柱MP上方。其中，該2條位元線BL中連接於記憶柱MP之位元線僅為其中任一條。 即，於記憶柱MP0～MP3之上方設置有2條位元線BL0及BL1。位元線BL0共通地連接於記憶柱MP1及MP2，位元線BL1共通地連接於記憶柱MP0及MP3。又，於記憶柱MP4～MP7之上方設置有2條位元線BL2及BL3。位元線BL2共通地連接於記憶柱MP4及MP5，位元線BL3共通地連接於記憶柱MP6及MP7。進而，於記憶柱MP8～MP11之上方設置2條位元線BL4及BL5。位元線BL4共通地連接於記憶柱MP9及MP10，位元線BL5共通地連接於記憶柱MP8及MP11。而且，於記憶柱MP12～MP15之上方設置有2條位元線BL6及BL7。位元線BL6共通地連接於記憶柱MP12及MP13，位元線BL7共通地連接於記憶柱MP14及MP15。因此，於本例之情形時，位元線BL0、BL1、BL4及BL5以及記憶柱MP0～MP3及MP8～MP11屬於組GR1，位元線BL2、BL3、BL6及BL7以及記憶柱MP4～MP7及MP12～MP15屬於組GR2。 其他構成如第1實施形態中說明所述。 3.2頁選擇方法 繼而，對資料之讀出時及寫入時之頁之選擇方法進行說明。 如上述3.1中說明所述，於本例中，將2個或3個配線層10共通地連接。因此，共通地連接之複數個配線層10被同時選擇。圖20及圖21係上文中所說明之與圖18對應之XY平面內之選擇閘極線SGD之平面佈局圖，對與所選擇之選擇閘極線SGD對應之配線層10標註斜線而表示。 如圖20所示，當選擇閘極線SGD1～SGD3中之任一條被選擇時，選擇對應之2個配線層10。於圖20中，示出選擇閘極線SGD1被選擇之情形。於該情形時，藉由選擇2個配線層10-1a及10-1b，而選擇設置於記憶柱MP0、MP4、MP8、及MP12以及記憶柱MP2、MP6、MP10、及MP14之8個記憶胞電晶體MT。即，藉由屬於設置於配線層10-1a及10-1b正下方之與任一字元線WL對應之配線層11-1a及11-1b之8個記憶胞電晶體MT形成1頁。該情況於選擇閘極線SGD2及SGD3被選擇之情形時亦相同。 相對於此，於選擇閘極線SGD0被選擇之情形時，如圖21所示，同時選擇於區塊BLK內位於兩端之配線層10-0a及10-0c以及位於區塊BLK中央之配線層10-0b之3個配線層10。藉此，選擇位於配線層10-0a正下方且設置於記憶柱MP4及MP12之2個記憶胞電晶體MT、位於配線層10-0c正下方且設置於記憶柱MP3及MP11之2個記憶胞電晶體MT、及位於配線層10-0b正下方且設置於記憶柱MP1、MP6、MP9、及MP14之4個記憶胞電晶體MT。即，藉由這8個記憶胞電晶體MT形成1頁。 資料之讀出方法及寫入方法如第1及第2實施形態中說明所述。 3.3本實施形態之效果 根據本實施形態，藉由使2個以上之配線層10作為1條選擇閘極線SGD發揮功能，可增大1頁之尺寸。又，若為本例之選擇閘極線SGD之接線方法，則於選擇了複數個配線層10時，可使與各配線層建立關聯之記憶胞電晶體MT所受到之單元間之干擾效果(包含電容或電阻之影響)於配線層間幾乎相等。 例如於圖19中，於選擇了選擇閘極線SGD2之情形時，驅動配線層10-2a及10-2b。於Y方向上與配線層10-2a相鄰之配線層10係作為配線層SGD1發揮功能且作為配線層SGD3發揮功能之10-1a及10-3a。而且，於Y方向上與同時被選擇之另一個配線層10-2b相鄰之配線層10亦係作為選擇閘極線SGD1及SGD3發揮功能之配線層10-1b及10-3b。如此，1條選擇閘極線SGD於記憶胞部被分離成2條配線，於Y方向上相鄰之選擇閘極線之組合於分離所得之該2條配線間共通。即，分離所得之2條配線自相鄰之配線受到之影響幾乎相同。該情況於選擇了任一選擇閘極線SGD之情形時均相同。因此，可抑制選擇閘極線SGD間之特性偏差，從而提高動作可靠性。 圖22係本實施形態之變化例之選擇閘極線SGD之XY平面內之俯視圖。如圖所示，本例示出將1區塊BLK內之配線10之數量設為17條之情形。如圖所示，沿著Y方向例如依次排列有配線層10-0a、10-1a、10-2a、10-3a、10-4a、10-5a、10-6a、10-7a、10-0b、10-1b、10-2b、10-3b、10-4b、10-5b、10-6b、10-7b、及10-0c。而且，位於兩端之配線層10-0a及10-0c以及位於中央之配線層10-b作為選擇閘極線SGD0發揮功能。又，配線層10-1a及10-1b作為選擇閘極線SGD1發揮功能，配線層10-2a及10-2b作為選擇閘極線SGD2發揮功能，以下相同。如此，配線層10之條數可適當增加。 若概括化地表達，則可如圖23般進行解釋。圖23亦為選擇閘極線SGD之平面佈局。如圖所示，沿著Y方向排列有(2n＋1)個配線層10-1～10-(2n＋1)。其中，n為2以上之自然數。而且，第1層配線層10-1、位於中央之配線層10-(n＋1)及最後之配線層10-(2n＋1)共通地連接。關於剩餘之配線層10，第i層與第(i＋n)層共通地連接。其中，i為2～n之自然數。 4.第4實施形態 繼而，對第4實施形態之半導體記憶裝置進行說明。本實施形態係關於作為選擇閘極線SGD發揮功能之配線層10之接線方法與上述第3實施形態不同之示例。以下，僅對與第1至第3實施形態不同之方面進行說明。 4.1關於平面佈局 圖24係某一區塊BLK之XY平面內之選擇閘極線SGD之平面佈局，與第3實施形態中所說明之圖19對應。雖省略位元線BL之圖示，但與第3實施形態相同。 如圖所示，若為本例之佈局，則沿著Y方向之2個配線層10-0a及10-0c和隔著1個配線層10而沿著Y方向與兩端之配線層10-0a或10-0c相鄰之1個配線層10-0b被引出至第1連接部並共通連接。而且，這3個配線層10-0a、10-0b及10-0c係作為選擇閘極線SGD0發揮功能。關於剩餘之配線層10，隔著1個配線層10而沿著Y方向相鄰之2個彼此於連接部共通連接。即，如圖24所示，配線層10-1a與10-1b被引出至第2連接部且共通連接，並作為選擇閘極線SGD1發揮功能。又，配線層10-2a與10-2b被引出至第1連接部且共通連接，並作為選擇閘極線SGD2發揮功能。而且，配線層10-3a與10-3b被引出至第2連接部且共通連接，並作為選擇閘極線SGD3發揮功能。 於讀出時及寫入時，於第1連接部或第2連接部中共通地連接之2個或3個配線層10被同時驅動。 4.2本實施形態之效果 如上所述，於第3實施形態中說明之選擇閘極線SGD之接線方法亦可使用如本實施形態般之方法。而且，根據本實施形態，由於不存在複數個配線層10相互交叉之情況，故而可於配線層10之層中將複數個配線層10共通地連接。即，無須如圖19般藉由接觸插塞與金屬配線層而利用其他層。藉此，可使製造方法簡化。 圖25係本實施形態之變化例之選擇閘極線SGD之平面佈局，與圖22同樣地示出將1區塊BLK內之配線層10之數量設為17個之情形之例。如圖所示，沿著Y方向之兩端之2個配線層10與自Y方向上之端部數起為第3層之配線層10被引出至第1連接部，並作為選擇閘極線SGD0發揮功能。其他配線層與圖24相同，隔著某一配線層10而於Y方向上相鄰之2個配線層10於第1連接部或第2連接部被共通地連接。 圖26示出沿著Y方向排列有(2n＋1)個配線層10-1～10-(2n＋1)之狀態。其中，n為2以上之自然數。而且，第1層配線層10-1、第3層配線層10-3及最後之配線層10-(2n＋1)共通地連接。關於剩餘之配線層10，第k層與第(k＋2)層共通地連接。其中，k為2、5、6、7、10、…10-(2n－3)及10-(2n－2)。 5.變化例等 如上所述，上述實施形態之半導體記憶裝置具備：第1區域(於圖3中為BLK)，其包含設置於半導體基板上方且沿著作為半導體基板之面內方向之第1方向(於圖3中為X方向)並排地排列有複數條之第1配線(於圖3中為SGD)、將相鄰之第1配線(於圖3中為SGD)間分離之第1絕緣膜(於圖3中為SLT2)、及以橫跨相鄰之上述第1配線(於圖3中為SGD)間之方式設置之第1柱(於圖3中為MP)；及第2、第3區域(於圖3中為SLT1)，其等以於半導體基板之面內方向且與第1方向不同之第2方向(於圖3中為Y方向)上將第1區域(BLK)夾於其間之方式而設，且包含自半導體基板上設置到第1配線(於圖3中為SGD)之高度為止之第2絕緣膜。第1柱(MP)包含導電層、閘極絕緣膜及電荷累積層(圖7-10)。設置於第1區域(於圖3中為BLK)內之第1配線(SGD)之條數為奇數條(圖3)。 根據本構成，可提高半導體記憶裝置之動作可靠性。再者，上文中所說明之實施形態不過為一例，可進行各種變化。 例如，於上述實施形態中，以通過記憶柱MP上之位元線BL為1條或2條之情形為例進行了說明，但亦可為3條或4條、或者4條以上。又，選擇閘極線SGD之條數亦不限定於9條或17條之情形。進而，於記憶柱MP內設置有2個NAND串之構成並不限定於上述第1實施形態中所說明之結構。關於此種結構，例如記載於名為“半導體記憶裝置及其製造方法(SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME)”之於2015年8月6日提出申請之美國專利申請14/819,706號，該專利申請之整體係藉由參照而援用到本申請之說明書中。 又，於上述實施形態中，使用圖4對字元線WL之平面佈局進行了說明。然而，1區塊BLK中所包含之字元線WL之條數可適當選擇，字元線WL之連接方法亦可適當選擇。又，例如，如圖27所示，亦可為將圖4所示之構成於Y方向上排列2段而成之構成。若為本構成，則狹縫SLT1不僅設置於1區塊BLK之沿著Y方向之兩端，亦設置於區塊BLK中央。而且，若為圖27之示例，則於隔著狹縫SLT1之一側，4條字元線WL於第1連接部被共通地連接，剩餘之3條字元線WL於第2連接部被共通地連接。另一方面，於隔著狹縫SLT1之另一側，4條字元線WL於第2連接部被共通地連接，剩餘之3條字元線WL於第1連接部被共通地連接。而且，隔著狹縫SLT1之2組字元線WL群藉由配線層60及61而連接。若為本構成，則可使自第1連接部側驅動之字元線WL之條數(於圖27中為9條)與自第2連接部側驅動之字元線WL之條數相等。 進而，選擇電晶體ST2亦可包含例如2個電晶體結構。圖28係相當於1個記憶柱MP之等效電路圖。如圖所示，選擇電晶體ST2亦可包含共通連接之2個電晶體ST2-1與ST2-2。圖29係選擇電晶體ST2之剖視圖。如圖所示，選擇電晶體ST2-1形成於記憶柱MP，但選擇電晶體2-2形成於p型井區域13上。即，於井區域13上形成閘極絕緣膜70，於閘極絕緣膜70上設置閘極電極12。進而，於井區域13內設置作為源極區域發揮功能之n型雜質擴散層71。根據本構成，可利用例如擴散層71等對電晶體ST2-2之背閘極施加電位。 再者，於與本發明相關之各實施形態中， (1)例如，記憶胞電晶體MT可保持2位元資料，且其閾值電壓從低到高依次為“Er”、“A”、“B”、“C”位準，於“Er”位準為刪除狀態之情形時，施加至“A”位準之讀出動作中所選擇之字元線之電壓例如為0 V～0.55 V之間。並不限定於此，亦可設為0.1 V～0.24 V、0.21 V～0.31 V、0.31 V～0.4 V、0.4 V～0.5 V、0.5 V～0.55 V中之任一個範圍。 施加至“B”位準之讀出動作中所選擇之字元線之電壓例如為1.5 V～2.3 V之間。並不限定於此，亦可設為1.65 V～1.8 V、1.8 V～1.95 V、1.95 V～2.1 V、2.1 V～2.3 V中之任一個範圍。 施加至“C”位準之讀出動作中所選擇之字元線之電壓例如為3.0 V～4.0 V之間。並不限定於此，亦可設為3.0 V～3.2 V、3.2 V～3.4 V、3.4 V～3.5 V、3.5 V～3.6 V、3.6 V～4.0 V中之任一個範圍。 作為讀出動作之時間(tR)，例如亦可設為25 μs～38 μs、38 μs～70 μs、70 μs～80 μs之間。 (2)寫入動作包含編程動作與驗證動作。於寫入動作中， 最初施加至編程動作時所選擇之字元線之電壓例如為13.7 V～14.3 V之間。並不限定於此，例如亦可設為13.7 V～14.0 V、14.0 V～14.6 V中之任一個範圍。 亦可改變寫入第奇數條字元線時之最初施加至所選擇之字元線之電壓與寫入第偶數條字元線時之最初施加至所選擇之字元線之電壓。 於將編程動作設為ISPP(Incremental Step Pulse Program，增量階躍脈衝編程)方式時，作為升壓之電壓，例如可列舉0.5 V左右。 作為施加至非選擇之字元線之電壓，例如亦可設為6.0 V～7.3 V之間。並不限定於該情形，例如亦可設為7.3 V～8.4 V之間，還可以設為6.0 V以下。 亦可根據非選擇之字元線係第奇數條字元線抑或是第偶數條字元線而改變所要施加之通過電壓。 作為寫入動作之時間(tProg)，例如亦可設為1700 μs～1800 μs、1800 μs～1900 μs、1900 μs～2000 μs之間。 (3)於刪除動作中， 最初施加至形成於半導體基板上部且於上方配置有上述記憶胞之井之電壓例如為12 V～13.6 V之間。並不限定於該情形，例如亦可為13.6 V～14.8 V、14.8 V～19.0 V、19.0～19.8 V、19.8 V～21 V之間。 作為刪除動作之時間(tErase)，例如亦可設為3000 μs～4000 μs、4000 μs～5000 μs、4000 μs～9000 μs之間。 (4)記憶胞之結構係 具有隔著膜厚為4～10 nm之隧穿絕緣膜配置於半導體基板(矽基板)上之電荷累積層。該電荷累積層可設為膜厚為2～3 nm之SiN或SiON等絕緣膜與膜厚為3～8 nm之多晶矽之積層結構。又，亦可於多晶矽中添加Ru等金屬。於電荷累積層之上具有絕緣膜。該絕緣膜例如具有被膜厚為3～10 nm之下層High-k膜與膜厚為3～10 nm之上層High-k膜夾著之膜厚為4～10 nm之氧化矽膜。關於High-k膜，可列舉HfO等。又，氧化矽膜之膜厚可厚於High-k膜之膜厚。於絕緣膜上隔著膜厚為3～10 nm之功函數調整用材料形成有膜厚為30 nm～70 nm之控制電極。此處，功函數調整用材料為TaO等金屬氧化膜、TaN等金屬氮化膜。控制電極可使用W等。 又，可於記憶胞間形成氣隙。 進而，於上述實施形態中，作為半導體記憶裝置，以NAND型快閃記憶體為例進行了說明，但並不限定於NAND型快閃記憶體，可應用於其他所有半導體記憶體，進而，可應用於半導體記憶體以外之各種記憶裝置。 已對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出，並非意圖限定發明之範圍。該等實施形態可以其他各種形態加以實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，同樣包含於申請專利範圍所記載之發明及其均等之範圍內。 [相關申請] 本申請享有以日本專利申請2017-61208號(申請日：2017年3月27日)及日本專利申請2017-168249號(申請日：2017年9月1日)作為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。Hereinafter, embodiments will be described with reference to the drawings. In the following description, constituent elements having the same functions and configurations are denoted by common reference numerals. 1. First Embodiment A memory system according to a first embodiment will be described. Hereinafter, a memory system including a NAND (Not AND) type flash memory as a semiconductor memory device will be described as an example. 1. (Configuration) The configuration of the NAND flash memory of the present embodiment will be described. 1. 1. (1) Overall configuration First, the overall configuration of the NAND flash memory of the present embodiment will be described with reference to Fig. 1 . As shown in the figure, the NAND flash memory 1 includes a memory cell array 2, a column decoder 3, and a sense amplifier 4. The memory cell array 2 has a plurality of blocks BLK. Only four blocks BLK0 to BLK3 are shown in Fig. 1, but the number thereof is not limited. The block BLK includes a plurality of memory cells that are associated in a column and a row and are three-dimensionally layered. Further, the block BLK is provided on the semiconductor substrate, and a slit SLT1 is provided between the adjacent blocks. The details of the constitution of the memory cell array 2 will be described below. The column decoder 3 decodes the row address received from the outside. Then, the column decoder 3 selects the column direction of the memory cell array 2 based on the decoding result. More specifically, a voltage is applied to various wirings for selecting column directions. The sense amplifier 4 reads the data read from any block BLK when reading the data. Further, when data is written, a voltage corresponding to the written data is applied to the memory cell array 2. 1. 1. 2 Configuration of Memory Cell Array 2 Next, the configuration of the memory cell array 2 of the present embodiment will be described. <Circuit Configuration> First, the circuit configuration of the memory cell array 2 will be described using FIG. Figure 2 is an equivalent circuit diagram of the block BLK. As shown, the block BLK contains a plurality of memory banks MG (MG0, MG1, MG2, ...). Also, each memory bank MG includes a plurality of NAND strings 50. Hereinafter, the NAND strings of the even-numbered memory banks MGe (MG0, MG2, MG4, ...) are referred to as NAND strings 50e, and the NAND strings of the odd-numbered memory banks MGo (MG1, MG3, MG5, ...) are referred to as NAND strings. NAND string 50o. Each of the NAND strings 50 includes, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. The memory cell transistor MT has a control gate and a charge accumulation layer to store the data non-volatilely. Further, the memory cell transistor MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. The gates of the selection transistors ST1 in the respective memory groups MGe are respectively connected to the selection gate lines SGD (SGD0, SGD1, ...). The select gate line SGD is independently controlled by the column decoder 3. Further, the gates of the selected transistors ST2 of the even-numbered memory groups MGe (MG0, MG2, ...) are, for example, commonly connected to the selection gate line SGSe, and each odd-numbered memory group MGo (MG1, MG3, ... The gate of the selection transistor ST2 is, for example, commonly connected to the selection gate line SGSo. The gate lines SGSe and SGSo can be connected in common, for example, or independently. Further, the control gates of the memory cell transistors MT (MT0 to MT7) included in the memory group MGe in the same block BLK are commonly connected to the word lines WLe (WLe0 to WLe7), respectively. On the other hand, the control gates of the memory cell transistors MT (MT0 to MT7) included in the memory group MGo are commonly connected to the word lines WLo (WLo0 to WLo7), respectively. The selection gate lines WLe and WLo are independently controlled by the column decoder 3. The block BLK is, for example, a deletion unit of data. That is, the data held by the memory cell transistor MT included in the same block BLK is deleted once. Further, the drains of the selection transistors ST1 of the NAND strings 50 located in the same row in the memory cell array 2 are commonly connected to the bit lines BL (BL0 to BL(L-1), where (L-1) is 2 or more. Natural number). That is, the bit line BL commonly connects the NAND strings 50 between the plurality of memory banks MG. Further, the sources of the plurality of selection transistors ST2 are connected in common to the source line SL. That is, the memory bank MG includes a plurality of NAND strings 50 connected to different bit lines BL and connected to the same selection gate line SGD. Further, the block BLK includes a plurality of memory banks MG of a plurality of common word lines WL. Moreover, the memory cell array 2 includes a plurality of blocks BLK sharing the bit line BL. Further, in the memory cell array 2, the memory cell line MT is three-dimensionally laminated by laminating the selection gate line SGS, the word line WL, and the selection gate line SGD over the semiconductor substrate. <Regarding Planar Layout of Memory Cell Array> Next, the planar configuration of the memory cell array 2 will be described. 3 shows the planar layout of the selection gate line SGD in the plane of the semiconductor substrate of a certain block BLK (referred to as the XY plane). In this example, a case where eight selection gate lines SGD are included in one block BLK will be described. As shown, nine conductive layers 10 (10-0 to 10-7, wherein 10-0 includes 10-0a and 10-0b) extending in the X direction are arranged in the Y direction orthogonal to the X direction. Each of the conductive layers 10 functions as a selection gate line SGD. In the example of FIG. 3, the two wiring layers 10-0a and 10-0b located at both ends in the Y direction in the block BLK function as the selection gate line SGD0. That is, the two wiring layers 10 located at both ends in the Y direction are connected in common to each other, or are controlled in the same manner by the column decoder 3. Further, the seven wiring layers 10-1 to 10-7 located between the functions function as the selection gate lines SGD1 to SGD7, respectively. Therefore, when viewing in the XY plane in the block BLK, the memory groups MG1 to MG7 are arranged in the Y direction, and the memory group MG0 is disposed on both sides thereof. The wiring layers 10 adjacent to each other in the Y direction in the block BLK are separated by an insulating film (not shown). The region in which the insulating film is provided is referred to as a slit SLT2. In the slit SLT2, the insulating film is buried, for example, from at least the semiconductor substrate surface to the region where the wiring layer 10 is provided. Further, in the memory cell array 2, for example, a plurality of blocks BLK shown in FIG. 3 are arranged in the Y direction. Further, the blocks BLK adjacent in the Y direction are also separated by an insulating film (not shown). The region where the insulating film is provided is the slit SLT1 described in FIG. The slit SLT1 is also the same as the SLT2. Further, a plurality of memory strings MP (MP0 to MP15) respectively along the Z direction are provided between the wiring layers 10 adjacent in the Y direction. The Z direction is a direction orthogonal to the XY direction, that is, a direction perpendicular to the surface of the semiconductor substrate. Specifically, memory pillars MP0 and MP8 are provided between wiring layers 10-1 and 10-2, and memory pillars MP1 and MP9 are provided between wiring layers 10-3 and 10-4, and wiring layer 10-5 is provided. A memory cell MP2 and MP10 are provided between 10 and 6-6, and memory cells MP3 and MP11 are provided between the wiring layers 10-7 and 10-0b. The memory cell MP forms a structure in which the selective transistors ST1 and ST2 and the memory cell MT are formed, the details of which will be described later. The memory columns MP0 to MP3 are arranged in the Y direction. Further, the memory columns MP8 to MP11 are arranged in the Y direction so as to be adjacent to the memory cells MP0 to MP3 in the X direction. That is, the memory strings MP0 to MP3 are arranged side by side with the memory columns MP8 to MP11. Further, the bit line BL0 is provided above the wiring layer 10 so as to be commonly connected to the memory strings MP0 to MP3. Further, the bit line BL2 is provided above the wiring layer 10 so as to be commonly connected to the memory strings MP8 to MP11. Hereinafter, the memory columns MP0 to MP3 and the memory columns MP8 to MP11 and the bit lines BL0 and BL2 may be referred to as a group GR1. Further, memory pillars MP4 and MP12 are provided between the wiring layers 10-0a and 10-1, and memory pillars MP5 and MP13 are provided between the wiring layers 10-2 and 10-3, and wiring layers 10-4 and 10 are provided. A memory cell MP6 and MP14 are provided between -5, and memory cells MP7 and MP15 are provided between the wiring layers 10-6 and 10-7. The memory columns MP4 to MP7 are arranged in the Y direction, and the memory columns MP12 to MP15 are also arranged in the Y direction. Further, the memory columns MP4 to MP7 are located between the memory columns MP0 to MP3 and the memory columns MP8 to MP11 in the X direction. Further, the memory columns MP12 to MP15 are provided so as to sandwich the memory columns MP8 to MP11 together with the memory cells MP4 to MP7 in the X direction. That is, the memory columns MP4 to MP7 are arranged side by side with the memory columns MP12 to MP15. Further, the bit line BL1 is provided above the wiring layer 10 so as to be commonly connected to the memory pillars MP4 to MP7. Further, the bit line BL3 is provided above the wiring layer 10 so as to be commonly connected to the memory strings MP12 to MP15. Hereinafter, the memory columns MP4 to MP7 and the memory columns MP12 to MP15 and the bit lines BL1 and BL3 may be referred to as a group GR2. In other words, the memory column MP is provided so as to straddle the two wiring layers 10 in the Y direction and is buried in one of the slits SLT2, and there is one slit between the memory pillars MP adjacent in the Y direction. SLT2. Further, the slit SLT2 for the memory column MP embedded in the group GR1 is located between the two memory columns MP belonging to the group GR2, and the slit SLT2 for the memory column MP belonging to the group GR2 is located in the two memories belonging to the group GR1. Column MP. Further, the memory cell MP is not provided between the adjacent wiring layers 10-0a and 10-0b via the slit SLT1. 4 is a plan layout showing the word line WL in the XY plane, similarly to FIG. 4 corresponds to the area of the block size of FIG. 3, and is disposed in the layout of the wiring layer 11 which is lower than the wiring layer 10 illustrated in FIG. As shown, nine conductive layers 11 (11-0 to 11-7, wherein 11-0 include 11-0a and 11-0b) extending in the X direction are arranged in the Y direction. Each of the wiring layers 11-0 to 11-7 is provided directly under the wiring layers 10-0 to 10-7 via an insulating film. Each of the conductive layers 10 functions as a word line WL7. The other word lines WL0 to WL6 are also the same. In the example of FIG. 4, the wiring layers 11-0a, 11-3, 11-5, 11-7, and 11-0b function as the word line WLo7. Further, the wiring layers 11-0a, 11-3, 11-5, 11-7, and 11-0b are drawn to the end portion along the X direction (this end portion is referred to as a first connection portion), and Connected to each other in common. Further, in the first connection portion, the wiring layers 11-0a, 11-3, 11-5, 11-7, and 11-0b are connected to the column decoder 3. Further, the wiring layers 11-1, 11-3, 11-5, and 11-7 function as the word line WLe7. Further, the wiring layers 11-1, 11-3, 11-5, and 11-7 are drawn to the second connection portion on the opposite side to the first connection portion in the X direction, and are connected to each other in common. Further, in the second connection portion, the wiring layers 11-1, 11-3, 11-5, and 11-7 are connected to the column decoder 3. Further, a memory cell portion is provided between the first connection portion and the second connection portion. In the memory cell portion, the wiring layers 11 adjacent in the Y direction are separated by the slit SLT2 illustrated in FIG. Further, the wiring layers 11 between the adjacent blocks BLK in the Y direction are also separated by the slit SLT1. Further, in the memory cell, memory cells MP0 to MP15 are provided in the same manner as in FIG. The above configuration is also the same in the other layers forming the word line WL and the selection gate line SGS. <Regular Structure of Memory Cell Array> Next, the cross-sectional structure of the memory cell array 2 will be described. 5 is a cross-sectional view of the block BLK along the Y direction, and shows a cross-sectional structure along a region of the bit line BL0 in FIG. 3 as an example. As shown in the figure, a wiring layer 12 functioning as the selection gate line SGS is provided above the semiconductor substrate (for example, the p-type well region) 13. Above the wiring layer 12, eight wiring layers 11 functioning as word lines WL0 to WL7 are laminated in the Z direction. The planar layout of the wirings 11 and 12 is as shown in FIG. Further, a wiring layer 10 functioning as the selection gate line SGD is provided above the wiring layer 11. The planar layout of the wiring layer 10 is as illustrated in FIG. Further, the slit SLT2 and the memory column MP are alternately arranged in the Y direction so as to reach the semiconductor substrate 13 from the wiring layer 10. As described above, the solid of the slit SLT2 is an insulating film. However, a contact plug or the like for applying a voltage to a region provided in the semiconductor substrate 13 may be provided in the slit SLT2. For example, a contact plug for connecting the source of the selection transistor ST2 to the source line may be provided. Further, the wiring layer 12 alternately functions as the selection gate line SGSo or SGSe by sandwiching the slit SLT2 or the memory column MP therebetween. Similarly, the wiring layer 11 alternately functions as the word line WLo or WLe by sandwiching the slit SLT2 or the memory column MP therebetween. Further, a slit SLT1 is provided between the blocks BLK adjacent in the Y direction. As described above, the body of the slit SLT1 is also an insulating film. However, a contact plug or the like for applying a voltage to a region provided in the semiconductor substrate 13 may be provided in the slit SLT1. For example, a contact plug or a slot-shaped conductor for connecting the source of the selection transistor ST2 to the source line may be provided. Further, the width of the slit SLT1 in the Y direction is larger than the width of the slit SLT2 in the Y direction. Further, the memory plug MP is provided with a contact plug 16 and the wiring layer 15 functioning as the bit line BL is disposed in the Y direction so as to be commonly connected to the contact plugs 16. Fig. 6 is a cross-sectional view of the block BLK along the X direction, showing a cross-sectional structure along the selection gate line SGD3 of Fig. 3 and passing through the areas of the memory columns MP5 and MP13 as an example. As described in FIG. 5, the wiring layers 12, 11, and 10 are sequentially disposed above the semiconductor substrate 13. Regarding the memory cell, it is described using FIG. In the first connection portion, the wiring layers 10 to 12 are drawn in a stepped manner, for example. In other words, when viewed in the XY plane, the upper surface of the end portions of the seven wiring layers 10 and the wiring layer 12 is exposed at the first connection portion. Further, a contact plug 17 is provided on the exposed region, and the contact plug 17 is connected to the metal wiring layer 18. Further, the wiring layers 10 to 12 functioning as the even-numbered selection gate lines SGD0, SGD2, SGD4, and SGD6, the even-numbered element lines WLo, and the even-numbered selection gate lines SGSo are electrically connected to each other by the metal wiring layer 18. Column decoder 3. On the other hand, in the second connection portion, the wiring layers 11 and 12 are drawn in a stepwise manner, for example. Further, a contact plug 19 is provided in a region where the wiring layers 11 and 12 are exposed, and the contact plug 19 is connected to the metal wiring layer 20. Further, the wiring layers 11 and 12 functioning as the odd-numbered selection gate lines SGD1, SGD3, SGD5, and SGD7, the odd-numbered digital lines WLe, and the odd-numbered selection gate lines SGSe are electrically connected to each other by the metal wiring layer 20. Column decoder 3. Further, the wiring layer 10 may be electrically connected to the column decoder 3 via the second connection portion instead of the first connection portion, or may be connected via both the first connection portion and the second connection portion. <Regarding Structure of Memory Column and Memory Cell Crystal> Next, the structure of the memory cell MP and the memory cell transistor MT will be described.・First example First, the first example will be described with reference to Figs. 7 and 8 . 7 is a cross-sectional view in the XY plane of the memory cell MP, and FIG. 8 is a cross-sectional view in the YZ plane, particularly showing a region in which two memory cell transistors MT are disposed. Further, in the first example, an insulating film is used for the charge accumulating layer of the memory cell MT. As shown, the memory cell MP includes an insulating layer 30, a semiconductor layer 31, and insulating layers 32 to 34 disposed along the Z direction. The insulating layer 30 is, for example, a hafnium oxide film. The semiconductor layer 31 is provided to surround the periphery of the insulating layer 30, and functions as a region for forming a channel for the memory cell transistor MT. The semiconductor layer 31 is, for example, a polysilicon layer. The insulating layer 32 is provided to surround the periphery of the semiconductor layer 31, and functions as a gate insulating film of the memory cell transistor MT. The insulating layer 32 has, for example, a laminated structure of a hafnium oxide film and a tantalum nitride film. The insulating layer 33 is provided to surround the periphery of the semiconductor layer 31, and functions as a charge accumulating layer of the memory cell transistor MT. The insulating layer 33 is, for example, a tantalum nitride film. The insulating layer 34 is provided to surround the periphery of the insulating layer 33, and functions as a barrier insulating film of the memory cell transistor MT. The insulating layer 34 is, for example, a hafnium oxide film. An insulating layer 37 is buried in the slit SLT2 except the MP portion of the memory cell. The insulating layer 37 is, for example, a hafnium oxide film. Further, for example, an AlO layer 35 is provided around the memory column MP having the above configuration. A shielding metal layer (TiN film or the like) 36 is formed around the AlO layer 35, for example. A conductive layer 11 functioning as a word line WL is provided around the shield metal layer 36. The conductive layer 11 is, for example, made of tungsten as a material. According to the above configuration, two memory cell crystals MT are provided along the Y direction in one memory cell MP. The selective transistors ST1 and ST2 also have the same configuration.・Second example Next, the second example will be described with reference to Figs. 9 and 10 . 9 is a cross-sectional view in the XY plane of the memory cell MP, and FIG. 10 is a cross-sectional view in the YZ plane, particularly showing a region in which two memory cell transistors MT are disposed. In the second example, a conductive film is used for the charge accumulating layer of the memory cell transistor MT. As shown, the memory cell MP includes insulating layers 48 and 43 disposed along the Z direction, a semiconductor layer 40, an insulating layer 41, a conductive layer 42, and insulating layers 46a to 46c. The insulating layer 48 is, for example, a hafnium oxide film. The semiconductor layer 40 is provided to surround the periphery of the insulating layer 43-1. The semiconductor layer 40 is, for example, a polysilicon layer and functions as a region for forming a channel for the memory cell transistor MT. As in the example of FIG. 7, the memory cell MT located in the same memory cell MP is not separated. The insulating layer 41 is provided around the conductive layer 40 and functions as a gate insulating film of each of the memory cell transistors MT. That is, the insulating layer 41 is separated into two regions in the XY plane shown in FIG. 9, and functions as a gate insulating film of two memory cell transistors MT in the same memory cell MP. The insulating layer 41 has, for example, a laminated structure of a hafnium oxide film and a tantalum nitride film. The conductive layer 42 is provided around the insulating layer 41, and is separated into two regions by the insulating layer 43 along the Y direction. The conductive layer 42 is, for example, a polycrystalline germanium layer, and the two separated regions function as charge accumulation layers of the two memory cell crystals MT, respectively. Further, the insulating layer 43 is, for example, a hafnium oxide film. Insulating layers 46a, 46b, and 46c are sequentially disposed around the conductive layer 42. The insulating layers 46a and 46c are, for example, a hafnium oxide film, and the insulating layer 46b is, for example, a tantalum nitride film, which functions as a barrier insulating film of the memory cell transistor MT. The insulating layers 46a to 46b are also separated into two regions along the Y direction, and an insulating layer 43 is provided between the two. Further, the insulating layer 43 is buried in the slit SLT2. The insulating layer 43 is, for example, a hafnium oxide film. Further, for example, an AlO layer 45 is provided around the memory column MP having the above configuration. Further, for example, a barrier metal layer (such as a TiN film) 47 is formed around the AlO layer 45. Further, a conductive layer 11 functioning as a word line WL is provided around the shield metal layer 47. According to the above configuration, two memory cell crystals MT are provided along the Y direction in one memory cell MP. The selective transistors ST1 and ST2 also have the same configuration. Further, an insulating layer (not shown) is provided between the adjacent memory cells in the Z direction, and the charge accumulating layer 42 and the respective memory cell transistors are provided by the insulating layer and the insulating layers 43 and 46. Every insulation.・About equivalent circuit Fig. 11 is an equivalent circuit diagram of the memory column MP having the above configuration. As shown in the figure, two NAND strings 50o and 50e are formed in one memory cell MP. That is, the selection transistor ST1 disposed on the same memory cell MP is connected to the different selection gate lines SGD, the memory cell transistors MT are connected to the word lines WLo and WLe which are different from each other, and the selection transistor ST2 is also connected to The gate lines SGSo and SGSe are different from each other. Further, the two NAND strings 50o and 50e in the same memory column MP are connected to the same bit line BL, and are connected to the same source line SL. However, the current paths are electrically separated from each other. 1. (2) Reading operation Next, a method of reading data in the NAND-type flash memory having the above configuration will be described. First, a state in which the selection gate line SGD is selected will be described with reference to FIGS. 12 and 13. 12 and FIG. 13 are plan layout views of the selection gate line SGD in the XY plane corresponding to FIG. 3 described above, and the wiring layer 10 corresponding to the selected selection gate line SGD is indicated by a diagonal line. . As shown in FIG. 12, when any one of the selection gate lines SGD1 to SGD7 is selected, one of the corresponding ones of the wiring layers 10-1 to 10-7 is selected. The case where the selection gate line SGD1 is selected is shown in FIG. By selecting the wiring layer 10-1, four memory cell transistors MT provided in the memory cells MP0, MP4, MP8, and MP12 are selected. In other words, one page is formed by four memory cell transistors MT belonging to the wiring layer 11-1 corresponding to any word line WL directly under the wiring layer 10-1. This is also the case when the selection gate lines SGD2 to SGD7 are selected. On the other hand, both of the wiring layers 10-0a and 10-0b located at both ends in the block BLK are simultaneously selected. This case is equivalent to the case where the selection gate line SGD0 is selected. This state is shown in FIG. As shown in the figure, when the selection gate line SGD0 is selected, two memory cell transistors MT located directly under the wiring layer 10-0a and disposed on the memory columns MP4 and MP12 are selected and located directly under the wiring layer 10-0b. Two memory cell transistors MT disposed on the memory cells MP3 and MP11. That is, one page is formed by the four memory cell transistors MT. Fig. 14 is a timing chart showing voltage changes of various wirings when the odd-numbered selection gate lines SGDo (i.e., the odd-numbered memory groups MG) and the word line WLo0 are selected. As shown in the figure, first, at time t1, voltage VSG is applied to all of the selected gate lines SGD in the selected block BLK, and the selection transistor ST1 is set to the on state. Further, by applying a voltage VREAD to all the word lines, the memory cell MT is set to the ON state regardless of the data held. Further, a voltage VSG is applied to all of the selection gate lines SGS, and the selection transistor ST2 is turned on. Thereby, in the selection block BLK, all the NAND strings 50 become in an on state, and VSS (for example, 0 V) is transmitted to the channel. Then, at time t3, the sense amplifier 4 precharges the bit line BL. At this time, the even bit lines BL0 and BL2 belonging to the group GR1 are precharged to the voltage VBL2, and the odd bit lines BL1 and BL3 belonging to the group GR2 are precharged to the voltage VBL1 larger than the voltage VBL2. Then, at time t4, a voltage VSG is applied to the selected selection gate lines SGD and SGSo, a read voltage VCGRV is applied to the selected word line WLo0, a voltage VNEG is applied to the non-selected word line WLe0, and other non-selected words are applied. Yuan line WL1 ~ WL7. The voltage VCGRV is a voltage corresponding to the read level, and is used to determine whether the selected data of the selected memory cell MT is “0” or “1”. The voltage VNEG is, for example, a negative voltage or 0 V, which is a voltage for disconnecting the memory cell transistor MT. As a result of the above, if the selected memory cell MT is turned on, the current flows from the bit line BL to the source line SL, and if the selected memory cell MT is turned off, no current flows. . Thereby, the retention data of the selected memory cell MT can be judged. 1. (3) Effects of the present embodiment According to the present embodiment, variations in memory cell characteristics between the memory banks MG can be corrected, and the operational reliability of the semiconductor memory device can be improved. This effect will be described below. According to the semiconductor memory device of the present embodiment, as described with reference to FIGS. 3 and 4, one memory cell MP is formed by two selection gate lines SGD and two word lines WL arranged in the XY plane. The way it is set. Further, two memory cell transistors MT are provided in the memory cell MP, and are controlled by the two selected gate lines SGD and the word line WL. Further, in the case of the present configuration, there is a case where the positional relationship between the memory cell MP and the corresponding two character line lines WL (and the selection gate line SGD) varies. More specifically, in FIGS. 3 and 4, when focusing on a certain memory column MP, it is preferable that the central portion of the memory column MP in the Y direction is located in the middle of the corresponding two word lines. The reason for this is that by arranging the memory cell MP in this manner, the sizes of the two memory cell transistors MT controlled by the corresponding two word lines WL become equal. However, if the position of the memory cell MP is shifted, the size of the corresponding two memory cell MTs is different. For example, in the example of FIGS. 3 and 4, the memory cell MP is shifted toward the wiring layer 10-0a side in the Y direction. As a result, when focusing on the wiring layers 10-1 and 11-1 and the memory pillars MP0 and MP4, the memory pillar MP0 overlaps the wiring layers 10-1 and 11-1 by a distance d1, the memory pillar MP4 and the wiring layer 10-1. And 11-1 overlaps the distance d2, and there is a relationship of d1>d2. This situation also has the same relationship between the memory sticks MP8 and MP12. That is, when focusing on the memory group MG1, the cell size of the memory cell MT connected to the even bit line BLe is large, and the cell size of the memory cell MT connected to the odd bit line BLo is small. . The size of the cell size can also be said to be the magnitude of the current driving capability of the memory cell MT. That is, it can be clarified from Fig. 3 that the size of the memory cell transistor MT connected to the bit lines BL0 and BL2, that is, the memory cell transistor MT belonging to the group GR1, when the even-numbered gate selection gate line SGDe is selected Smaller. On the other hand, the memory cell transistor MT connected to the bit lines BL1 and BL3, that is, the memory cell crystal belonging to the group GR2 has a large size. On the contrary, when the odd-numbered gate selection gate line SGDo is selected, the memory cell transistors MT connected to the bit lines BL0 and BL2, that is, the memory cell transistors MT belonging to the group GR1 are large in size. On the other hand, the memory cell transistors MT connected to the bit lines BL1 and BL3, that is, the memory cell transistors belonging to the group GR2 are small in size. As described above, when the position of the memory cell MP is shifted, the memory cell transistors MT of different sizes are alternately arranged in the same page. Therefore, in the present embodiment, the sense amplifier 4 controls the precharge potential at the time of the read operation in accordance with the size of the selected memory cell MT. More specifically, when the even-numbered selection gate line SGDe, that is, the even-numbered memory group MGe is selected, the sense amplifier 4 applies a larger pre-charge potential VBL1 to the bit line BL of the group GR1, for the group GR2. The bit line BL applies a small precharge potential VBL2. On the other hand, when the odd-numbered gate selection gate line SGDo, that is, the odd-numbered memory group MGo is selected, the sense amplifier 4 applies a smaller precharge potential VBL2 to the bit line BL of the group GR1, for the group GR2. The bit line BL applies a large precharge potential VBL1. As a result, the precharge potential can be used to cancel the difference in current driving force generated by the cell size of the memory cell MT, so that the cell current flowing to the bit line BL during the read operation can be reduced between the bit lines. The difference. In other words, the memory cell MT which is less likely to flow in the cell current is supplied with a condition that a sufficiently large cell current is supplied, and the memory cell current MT which is easy to flow the cell current is given a condition for suppressing the cell current. Thereby, it is possible to suppress the occurrence of erroneous reading of the memory cell MT, which is particularly derived from the current of the cell that is less likely to flow, and to improve the operational reliability of the semiconductor memory device. Further, in the configuration of the present embodiment, as shown in FIG. 3, the wiring layers 10-0a and 10-0b located at both end portions of the block BLK are simultaneously selected, and both function as the selection gate line SGD0. This is because four memory pillars MP (memory cell MT) are formed in each of the other wiring layers 10-1 to 10-7, and only two of the wiring layers 10-0a and 10-0b are formed. Memory column MP (memory cell MT). Therefore, in the both end portions of the block BLK, the two wiring layers 10-0a and 10-0b are electrically operated as one selection gate line SGD, thereby even when the selection gate line SGD0 is selected. It is also possible to make the size of one page the same as when other gate lines SGD1 to SGD7 are selected. Further, as a result of matching the page sizes as described above, as shown in FIG. 3, the number of the wiring layers 10 functioning as the selection gate line SGD in one block BLK is an odd number in the XY plane. This case is also the same for the wiring layer 11 that functions as the word line WL as shown in FIG. In other words, when viewed in the XY plane, the number of wiring layers located between the slits SLT1 becomes an odd number. Furthermore, the offset mode of the memory cell MP may be the opposite of that of FIGS. 3 and 4. The state at the time of this case is shown in FIG. Fig. 15 shows a plan layout of the selection gate line SGD according to a modification of the embodiment. As shown in the figure, in this example, the position of the memory cell MP is opposite to that of the case of FIG. 3, and is shifted toward the wiring layer 10-0b side in the Y direction. As a result, when focusing on the wiring layers 10-1 and 11-1 and the memory pillars MP0 and MP4, the memory pillar MP0 overlaps the wiring layers 10-1 and 11-1 by a distance d2, the memory pillar MP4 and the wiring layer 10-1. And 11-1 overlap distance d1. In this case, the voltage applied to the bit line BL at the time of reading is opposite to that of the above embodiment. That is, when the even-numbered gate selection gate line SGDe, that is, the even-numbered memory group MGe is selected, the sense amplifier 4 applies a small precharge potential VBL2 to the bit line BL of the group GR1, and the bit of the group GR2. The line BL applies a large precharge potential VBL1. On the other hand, when the odd-numbered gate selection gate line SGDo, that is, the odd-numbered memory group MGo is selected, the sense amplifier 4 applies a larger precharge potential VBL1 to the bit line BL of the group GR1, for the group GR2. The bit line BL applies a small precharge potential VBL2. 2. (Second Embodiment) Next, a semiconductor memory device according to a second embodiment will be described. This embodiment relates to the write operation in the first embodiment. Hereinafter, only differences from the first embodiment will be described. 2. 1 First Example First, the first example will be described. The write operation of the data includes a program operation that injects electrons into the charge accumulation layer to cause a threshold change, and a program verify operation that confirms the result of the program operation, that is, whether the threshold value reaches a prescribed value. The first example is in the programming operation such that the voltage applied to the bit line BL is different in the groups GR1 and GR2. Fig. 16 is a timing chart showing voltage changes of various wirings when the odd-numbered selection gate lines SGDo (i.e., the odd-numbered memory groups MG) and the word line WLo0 are selected at the time of data writing. As shown in FIG. 12 and FIG. 13, when the odd-numbered gate selection gate line SGDo is selected, the size of the memory cell transistor MT belonging to the group GR1 (BL0, BL2) is large, belonging to the group GR2 (BL1, BL3). The memory cell transistor MT is small. Since the overlap area of the word line WL and the memory cell MP is larger, the coupling ratio is larger, and thus the writing speed of the memory cell MT is faster. That is, the write speed of the group GR1 is faster, and the group GR2 is slower. Therefore, at time t2, the sense amplifier 4 applies a relatively high voltage VCH2 to the bit lines BL0 and BL2 belonging to the group GR1, and applies a low voltage VCH1 to the bit lines BL1 and BL3 belonging to the group GR2. Of course, VCH2>VCH1. Next, at time t3, the column decoder 3 applies a voltage VPASS to all of the word lines WL0 to WL7, and further increases the voltage of the selected word line WLo0 from VPASS to VPGM at time t5. The voltage VPASS is a voltage that causes the memory cell MT to be turned on regardless of the data to be held, and the channel potential can be sufficiently raised by coupling in the unselected NAND string 50. Further, the voltage VPGM is used to inject electrons into the high voltage of the charge accumulating layer by FN (Fowler-Nordheim, Fowler-Nordheim), and VPGM>VPASS. According to the method, the writing speed can be lowered by increasing the bit line voltage corresponding to the memory cell transistor MT having a higher writing speed. Thereby, the difference in writing speed between the groups GR1 and GR2 can be reduced. 2. 2nd example Next, the 2nd example is demonstrated. The second example is for changing the value of the voltage VPGM applied to the selected word line WL in the groups GR1 and GR2 during the programming operation. Fig. 17 is a timing chart showing the change in potential of the selected word line WL and the bit line BL in this example, and shows the case where the even-numbered memory banks MG, i.e., the even-numbered gate selection gate lines SGDe are selected. As described above, the write action includes a program action and a program verify action. This combination is called a programming loop. Further, in the write operation, the data of one page is written by repeating the program loop a plurality of times. In this case, in the programming operation, two kinds of program voltages VPGM1 and VPGM2 are applied to the selected word line WL, and there is a relationship of VPGM2>VPGM1. When the even number of memory banks MG are selected, the writing speed of the memory cell MT belonging to the group GR1 (BL0, BL2) is slow, and belongs to the memory cell transistor MT of the group GR2 (BL1, BL3). Write speed is faster. Therefore, the voltage VPGM1 is used as the programming voltage for the group GR2, and the voltage VPGM2 is used as the programming voltage for the group GR1. Specifically, during the period in which the voltage VPGM1 is applied, the write inhibit voltage VBL is applied to the bit lines BL0 and BL2 of the group GR1, and the write voltage is applied to the bit lines BL1 and BL3 of the group GR2 (for example, 0 V, which is smaller than VBL voltage). As a result, the data is programmed to the memory cell transistor MT connected to the bit lines BL1 and BL3. On the other hand, during the period in which the voltage VPGM2 is applied, the write inhibit voltage VBL is applied to the bit lines BL1 and BL3 of the group GR2, and the write voltage is applied to the bit lines BL0 and BL2 of the group GR1. As a result, the data is programmed to the memory cell MT connected to the bit lines BL0 and BL2. According to the method, a higher programming voltage is used for the memory cell MT having a slower writing speed, and a lower programming voltage is used for the memory cell having a faster writing speed. Thereby, the difference in writing speed between the groups GR1 and GR2 can be reduced. Furthermore, the boosting amplitude ΔVPGM of the programming voltage VPGM can also be changed in the groups GR1 and GR2. Of course, in the group where the writing speed is slow, ΔVPGM is set to be large. 2. 3rd example Next, the third example will be explained. The third example is to reduce the precharge potential of the group having a slower writing speed in the case of the program verifying operation, thereby relatively reducing the cell current. That is, the method of applying a voltage to the bit line BL is the same as that of FIG. 14 described in the first embodiment. According to the method, in the memory cell having a slow writing speed, the threshold of the cell is increased as the programming cycle is repeated a plurality of times, and the cell current is less likely to flow, so that it is easy to verify by programming. As a result, the difference in writing speed between the groups GR1 and GR2 can be reduced. 2. (Effect of the present embodiment) According to the present embodiment, even when the writing speed is different between the memory cells belonging to the same page, the number of programming cycles required for the program verification can be made the same. Therefore, the number of programming cycles can be reduced, thereby increasing the buying speed. Moreover, it is possible to suppress the memory cell which has a fast writing speed from being quickly subjected to the writing operation after the program verification, and the interference caused by the writing operation to the memory cell having a slow writing speed for a long time, thereby improving the writing. Into the action reliability. 3. Third Embodiment Next, a semiconductor memory device according to a third embodiment will be described. This embodiment relates to a planar layout different from the above-described first and second embodiments. As an example, two bit lines are provided on one memory column. Hereinafter, only differences from the first and second embodiments will be described. 3. 1 Regarding Planar Layout FIG. 18 and FIG. 19 show the planar layout of the selected gate line SGD in the XY plane of a certain block BLK. Fig. 18 corresponds to Fig. 3 described in the first embodiment, and also shows the state of the bit line BL. In Fig. 19, the illustration of the memory cell portion is simplified, and in particular, the configuration of the first connection portion and the second connection portion is focused. Moreover, in this example, a case where four selection gate lines SGD are included in one block BLK will be described. As shown in the figure, in the present example, as in the configuration illustrated in FIG. 3, nine conductive layers 10 extending in the X direction are included. However, in this example, the wiring layers 10-1 to 10-7 and 10-0b illustrated in FIG. 3 are respectively referred to as wiring layers 10-1a, 10-2a, 10-3a, 10-0b, 10- 1b, 10-2b, 10-3b, and 10-0c. The slit SLT2 is provided between the wiring layers 10 as in the first embodiment. Further, the two wiring layers 10-0a and 10-0c located at both ends in the Y direction in the block BLK and the wiring layer 10-0b located at the center function as the selection gate line SGD0. As shown in FIG. 19, for example, the three wiring layers 10-0 are commonly connected to each other by the contact plug 49 and the metal wiring layer 51 in the first connection portion, and are further connected to the column decoder 3. Further, the wiring layers 10-1a and 10-2b are connected in common to the second connection portion via the contact plug 52 and the metal wiring layer 53, and are further connected to the column decoder 3. Further, the wiring layers 10-2a and 10-2b are connected in common to the second connection portion via the contact plug 52 and the metal wiring layer 53, and are further connected to the column decoder 3. Further, the wiring layers 10-3a and 10-3b are connected in common to the first connection portion via the contact plug 49 and the metal wiring layer 51, and are further connected to the column decoder 3. Further, as shown in FIG. 18, two bit lines BL pass over one memory column MP. The bit line connected to the memory column MP of the two bit lines BL is only one of them. That is, two bit lines BL0 and BL1 are provided above the memory columns MP0 to MP3. The bit line BL0 is commonly connected to the memory columns MP1 and MP2, and the bit line BL1 is commonly connected to the memory columns MP0 and MP3. Further, two bit lines BL2 and BL3 are provided above the memory columns MP4 to MP7. The bit line BL2 is commonly connected to the memory columns MP4 and MP5, and the bit line BL3 is commonly connected to the memory columns MP6 and MP7. Further, two bit lines BL4 and BL5 are provided above the memory columns MP8 to MP11. The bit line BL4 is commonly connected to the memory cells MP9 and MP10, and the bit line BL5 is commonly connected to the memory cells MP8 and MP11. Further, two bit lines BL6 and BL7 are provided above the memory columns MP12 to MP15. The bit line BL6 is commonly connected to the memory columns MP12 and MP13, and the bit line BL7 is commonly connected to the memory columns MP14 and MP15. Therefore, in the case of this example, the bit lines BL0, BL1, BL4, and BL5 and the memory columns MP0 to MP3 and MP8 to MP11 belong to the group GR1, the bit lines BL2, BL3, BL6, and BL7 and the memory columns MP4 to MP7 and MP12 to MP15 belong to group GR2. Other configurations are as described in the first embodiment. 3. 2-page selection method Next, the method of selecting the page at the time of reading and writing is described. As above 3. As described in the first description, in the present example, two or three wiring layers 10 are connected in common. Therefore, a plurality of wiring layers 10 that are commonly connected are simultaneously selected. 20 and FIG. 21 are plan layout views of the selection gate line SGD in the XY plane corresponding to FIG. 18 described above, and the wiring layer 10 corresponding to the selected selection gate line SGD is indicated by oblique lines. As shown in FIG. 20, when any one of the selection gate lines SGD1 to SGD3 is selected, the corresponding two wiring layers 10 are selected. In Fig. 20, the case where the selection gate line SGD1 is selected is shown. In this case, eight memory cells provided in the memory cells MP0, MP4, MP8, and MP12 and the memory cells MP2, MP6, MP10, and MP14 are selected by selecting the two wiring layers 10-1a and 10-1b. Transistor MT. In other words, one page is formed by eight memory cell transistors MT belonging to the wiring layers 11-1a and 11-1b corresponding to any of the word lines WL directly under the wiring layers 10-1a and 10-1b. This is also the case when the selection gate lines SGD2 and SGD3 are selected. On the other hand, when the selection gate line SGD0 is selected, as shown in FIG. 21, the wiring layers 10-0a and 10-0c located at both ends in the block BLK and the wiring at the center of the block BLK are simultaneously selected. Three wiring layers 10 of layer 10-0b. Thereby, two memory cell electrodes MT disposed directly under the wiring layer 10-0a and disposed on the memory cells MP4 and MP12, and two memory cells located directly under the wiring layer 10-0c and disposed on the memory columns MP3 and MP11 are selected. The transistor MT and the four memory cell transistors MT disposed directly under the wiring layer 10-0b and disposed on the memory columns MP1, MP6, MP9, and MP14. That is, one page is formed by the eight memory cell transistors MT. The data reading method and writing method are as described in the first and second embodiments. 3. (3) Effects of the present embodiment According to the present embodiment, by making two or more wiring layers 10 function as one selection gate line SGD, the size of one page can be increased. Moreover, if the wiring method of the gate line SGD is selected in this example, when a plurality of wiring layers 10 are selected, the interference effect between the cells received by the memory cell transistor MT associated with each wiring layer can be obtained ( The effect of including the capacitor or resistor is almost equal between the wiring layers. For example, in FIG. 19, when the gate line SGD2 is selected, the wiring layers 10-2a and 10-2b are driven. The wiring layer 10 adjacent to the wiring layer 10-2a in the Y direction functions as the wiring layer SGD1 and functions as the wiring layer SGD3 10-1a and 10-3a. Further, the wiring layer 10 adjacent to the other selected wiring layer 10-2b in the Y direction is also used as the wiring layers 10-1b and 10-3b which function as the selection gate lines SGD1 and SGD3. In this manner, one of the selection gate lines SGD is separated into two wirings in the memory cell portion, and the combination of the selected gate lines adjacent in the Y direction is common between the two wirings obtained by the separation. That is, the two wirings obtained by the separation are almost the same as those affected by the adjacent wiring. This case is the same when any of the selected gate lines SGD is selected. Therefore, variations in characteristics between the selected gate lines SGD can be suppressed, thereby improving operational reliability. Fig. 22 is a plan view showing the selection gate line SGD in the XY plane of the variation of the embodiment. As shown in the figure, this example shows a case where the number of wirings 10 in the 1-block BLK is set to 17. As shown in the figure, wiring layers 10-0a, 10-1a, 10-2a, 10-3a, 10-4a, 10-5a, 10-6a, 10-7a, 10-0b are sequentially arranged in the Y direction, for example. , 10-1b, 10-2b, 10-3b, 10-4b, 10-5b, 10-6b, 10-7b, and 10-0c. Further, the wiring layers 10-0a and 10-0c located at both ends and the wiring layer 10-b located at the center function as the selection gate line SGD0. Further, the wiring layers 10-1a and 10-1b function as the selection gate line SGD1, and the wiring layers 10-2a and 10-2b function as the selection gate line SGD2, and the same applies hereinafter. Thus, the number of the wiring layers 10 can be appropriately increased. If it is expressed in a generalized manner, it can be explained as shown in FIG. Figure 23 is also a plan layout of the selection gate line SGD. As shown in the figure, (2n+1) wiring layers 10-1 to 10-(2n+1) are arranged along the Y direction. Where n is a natural number of 2 or more. Further, the first wiring layer 10-1, the wiring layer 10-(n+1) located at the center, and the last wiring layer 10-(2n+1) are connected in common. Regarding the remaining wiring layer 10, the i-th layer and the (i+n)th layer are connected in common. Where i is a natural number from 2 to n. 4. Fourth Embodiment Next, a semiconductor memory device according to a fourth embodiment will be described. In the present embodiment, the wiring method of the wiring layer 10 functioning as the selection gate line SGD is different from the above-described third embodiment. Hereinafter, only differences from the first to third embodiments will be described. 4. 1. Planar layout Fig. 24 is a plan layout of the selection gate line SGD in the XY plane of a certain block BLK, corresponding to Fig. 19 described in the third embodiment. Although the illustration of the bit line BL is omitted, it is the same as that of the third embodiment. As shown in the figure, in the layout of this example, two wiring layers 10-0a and 10-0c along the Y direction and a wiring layer 10 along the Y direction and both ends via one wiring layer 10 are provided. One wiring layer 10-0b adjacent to 0a or 10-0c is led out to the first connection portion and connected in common. Further, the three wiring layers 10-0a, 10-0b, and 10-0c function as the selection gate line SGD0. In the remaining wiring layer 10, two adjacent to each other in the Y direction via the one wiring layer 10 are connected to each other in common at the connection portion. That is, as shown in FIG. 24, the wiring layers 10-1a and 10-1b are drawn to the second connection portion and connected in common, and function as the selection gate line SGD1. Further, the wiring layers 10-2a and 10-2b are led out to the first connection portion and connected in common, and function as the selection gate line SGD2. Further, the wiring layers 10-3a and 10-3b are led out to the second connection portion and connected in common, and function as the selection gate line SGD3. At the time of reading and writing, two or three wiring layers 10 that are commonly connected to each other in the first connection portion or the second connection portion are simultaneously driven. 4. (2) Effects of the present embodiment As described above, the method of wiring the selective gate line SGD described in the third embodiment can also be carried out by the method as in the present embodiment. Moreover, according to the present embodiment, since a plurality of wiring layers 10 do not intersect each other, a plurality of wiring layers 10 can be connected in common in the layer of the wiring layer 10. That is, it is not necessary to use other layers by contacting the plug and the metal wiring layer as shown in FIG. Thereby, the manufacturing method can be simplified. 25 is a plan layout of the selection gate line SGD according to the modification of the embodiment, and shows an example in which the number of the wiring layers 10 in the one block BLK is set to 17 as in FIG. 22 . As shown in the figure, the wiring layer 10 which is the third layer from the two ends in the Y direction and the third layer from the end in the Y direction is led out to the first connection portion and serves as a selection gate line. SGD0 functions. Similarly to FIG. 24, the other wiring layers are connected in common to the first connection portion or the second connection portion of the two wiring layers 10 adjacent to each other in the Y direction via the wiring layer 10. FIG. 26 shows a state in which (2n+1) wiring layers 10-1 to 10-(2n+1) are arranged along the Y direction. Where n is a natural number of 2 or more. Further, the first wiring layer 10-1, the third wiring layer 10-3, and the last wiring layer 10-(2n+1) are connected in common. Regarding the remaining wiring layer 10, the kth layer is connected in common to the (k+2)th layer. Wherein k is 2, 5, 6, 7, 10, ... 10-(2n-3) and 10-(2n-2). 5. As described above, the semiconductor memory device of the above-described embodiment includes the first region (BLK in FIG. 3) including the first direction disposed above the semiconductor substrate and along the in-plane direction of the semiconductor substrate ( In FIG. 3, the first wiring (the SGD in FIG. 3) and the first insulating wiring (the SGD in FIG. 3) are arranged side by side in a plurality of rows (the X direction). In FIG. 3, SLT2) and a first column (MP in FIG. 3) disposed between the adjacent first wirings (SGD in FIG. 3); and 2nd and 3rd a region (SLT1 in FIG. 3) that sandwiches the first region (BLK) in a second direction (in the Y direction in FIG. 3) different from the first direction in the in-plane direction of the semiconductor substrate In addition, the second insulating film is provided from the semiconductor substrate to the height of the first wiring (SGD in FIG. 3). The first pillar (MP) includes a conductive layer, a gate insulating film, and a charge accumulating layer (Fig. 7-10). The number of the first wirings (SGD) provided in the first region (BLK in FIG. 3) is an odd number (FIG. 3). According to this configuration, the operational reliability of the semiconductor memory device can be improved. Furthermore, the embodiments described above are merely examples, and various changes can be made. For example, in the above embodiment, the case where the bit line BL on the memory column MP is one or two is described as an example, but three or four or four or more may be used. Further, the number of the gate lines SGD is not limited to 9 or 17. Further, the configuration in which two NAND strings are provided in the memory column MP is not limited to the configuration described in the first embodiment. For example, U.S. Patent Application Serial No. 14/819,706, filed on Aug. 6, 2015, which is incorporated herein by reference in its entirety in its entirety, The entire patent application is hereby incorporated by reference in its entirety in its entirety in its entirety herein in Further, in the above embodiment, the planar layout of the word line WL has been described using FIG. However, the number of word lines WL included in the 1-block BLK can be appropriately selected, and the connection method of the word line WL can be appropriately selected. Further, for example, as shown in FIG. 27, a configuration in which the configuration shown in FIG. 4 is arranged in two stages in the Y direction may be employed. In the present configuration, the slit SLT1 is provided not only at both ends of the 1-block BLK in the Y direction but also at the center of the block BLK. Further, in the example of FIG. 27, the four word lines WL are connected in common to the first connection portion via one side of the slit SLT1, and the remaining three word lines WL are connected to the second connection portion. Commonly connected. On the other hand, on the other side of the slit SLT1, the four word lines WL are connected in common to the second connection portion, and the remaining three word lines WL are connected in common to the first connection portion. Further, the two groups of word lines WL across the slit SLT1 are connected by the wiring layers 60 and 61. According to this configuration, the number of character lines WL (9 in FIG. 27) driven from the first connection portion side can be made equal to the number of word lines WL driven from the second connection portion side. Further, the selection transistor ST2 may also include, for example, two transistor structures. Fig. 28 is an equivalent circuit diagram corresponding to one memory column MP. As shown in the figure, the selection transistor ST2 may also include two transistors ST2-1 and ST2-2 connected in common. Figure 29 is a cross-sectional view of the selective transistor ST2. As shown, the selection transistor ST2-1 is formed on the memory column MP, but the selection transistor 2-2 is formed on the p-type well region 13. That is, the gate insulating film 70 is formed on the well region 13, and the gate electrode 12 is provided on the gate insulating film 70. Further, an n-type impurity diffusion layer 71 functioning as a source region is provided in the well region 13. According to this configuration, a potential can be applied to the back gate of the transistor ST2-2 by, for example, the diffusion layer 71. Furthermore, in the embodiments related to the present invention, (1) for example, the memory cell transistor MT can hold 2-bit data, and the threshold voltages thereof are "Er", "A", and "from low to high." B", "C" level, when the "Er" level is in the deleted state, the voltage of the word line selected in the read operation applied to the "A" level is, for example, 0 V to 0. Between 55 V. It is not limited to this and can also be set to 0. 1 V ~ 0. 24 V, 0. 21 V to 0. 31 V, 0. 31 V to 0. 4 V, 0. 4 V ~ 0. 5 V, 0. 5 V to 0. Any of the 55 V ranges. The voltage of the word line selected in the read operation applied to the "B" level is, for example, 1. 5 V~2. Between 3 V. It is not limited to this, and may be set to 1. 65 V~1. 8 V, 1. 8 V~1. 95 V, 1. 95 V~2. 1 V, 2. 1 V ~ 2. Any of the 3 V ranges. The voltage of the word line selected in the read operation applied to the "C" level is, for example, 3. 0 V~4. Between 0 V. It is not limited to this, and may be set to 3. 0 V~3. 2 V, 3. 2 V ~ 3. 4 V, 3. 4 V~3. 5 V, 3. 5 V~3. 6 V, 3. 6 V to 4. Any range of 0 V. The time (tR) of the read operation may be, for example, between 25 μs and 38 μs, between 38 μs and 70 μs, and between 70 μs and 80 μs. (2) The write action includes a program action and a verify action. In the write operation, the voltage of the word line selected when initially applied to the programming operation is, for example, 13. 7 V~14. Between 3 V. It is not limited to this, and for example, it may be set to 13. 7 V~14. 0 V, 14. 0 V~14. Any of the 6 V ranges. The voltage initially applied to the selected word line when writing the odd number of word lines and the voltage initially applied to the selected word line when writing the even number of word lines may also be changed. When the programming operation is set to the ISPP (Incremental Step Pulse Program) mode, as the voltage for boosting, for example, 0. Around 5 V. As the voltage applied to the unselected word line, for example, it can also be set to 6. 0 V to 7. Between 3 V. It is not limited to this case, for example, it can also be set to 7. 3 V~8. Between 4 V, it can also be set to 6. Below 0 V. The pass voltage to be applied may also be changed according to the odd-numbered word line of the unselected character line or the even-numbered word line. The time (tProg) of the writing operation may be, for example, 1700 μs to 1800 μs, 1800 μs to 1900 μs, or 1900 μs to 2000 μs. (3) In the erasing operation, the voltage applied to the well formed on the upper portion of the semiconductor substrate and disposed above the memory cell is, for example, 12 V to 13. Between 6 V. It is not limited to this case, and may be, for example, 13. 6 V~14. 8 V, 14. 8 V to 19. 0 V, 19. 0 to 19. 8 V, 19. Between 8 V and 21 V. The time (tErase) as the erasing operation may be, for example, between 3000 μs and 4000 μs, between 4000 μs and 5000 μs, and between 4000 μs and 9000 μs. (4) Structure of memory cell A charge accumulating layer which is disposed on a semiconductor substrate (tantalum substrate) via a tunneling insulating film having a thickness of 4 to 10 nm. The charge accumulating layer can be a laminated structure of an insulating film such as SiN or SiON having a film thickness of 2 to 3 nm and a polycrystalline silicon having a film thickness of 3 to 8 nm. Further, a metal such as Ru may be added to the polycrystalline silicon. An insulating film is provided over the charge accumulating layer. The insulating film has, for example, a hafnium oxide film having a film thickness of 3 to 10 nm and a layer of a high-k film and a film thickness of 3 to 10 nm, and a film thickness of 4 to 10 nm. Examples of the High-k film include HfO and the like. Further, the film thickness of the ruthenium oxide film may be thicker than the film thickness of the High-k film. A control electrode having a film thickness of 30 nm to 70 nm is formed on the insulating film via a work function adjusting material having a film thickness of 3 to 10 nm. Here, the material for adjusting the work function is a metal oxide film such as TaO or a metal nitride film such as TaN. The control electrode can use W or the like. Moreover, an air gap can be formed between the memory cells. Further, in the above-described embodiment, the NAND flash memory has been described as an example of the semiconductor memory device. However, the present invention is not limited to the NAND flash memory, and can be applied to all other semiconductor memories. It is applied to various memory devices other than semiconductor memory. The embodiments of the present invention have been described, but are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions and changes may be made without departing from the scope of the invention. The scope of the invention and the scope of the invention are also included in the scope of the invention and the scope of the invention as set forth in the appended claims. [Related application] This application has priority as a basic application in Japanese Patent Application No. 2017-61208 (application date: March 27, 2017) and Japanese Patent Application No. 2017-168249 (application date: September 1, 2017). right. This application incorporates the entire contents of the basic application by reference to the basic application.