本發明係有關一種顯示裝置及顯示裝置基板。The present invention relates to a display device and a display device substrate.
以往，在用於顯示裝置的功能元件、顯示元件、用於靜電電容感測器或光感測器等的輸入元件、記憶元件、RFID(Radio Frequency Identification；無線射頻識別)元件、薄膜電晶體(TFT：Thin Film Transistor)或二極體等之主動元件中，使用導電配線。為了解消電氣信號的延遲，要求低電阻的導電配線。Conventionally, a functional element for a display device, a display element, an input element for a capacitance sensor or a photo sensor, a memory element, an RFID (Radio Frequency Identification) element, a thin film transistor ( Conductive wiring is used in an active element such as a TFT (Thin Film Transistor) or a diode. In order to understand the delay of the eraser signal, a low-resistance conductive wiring is required.
作為此種導電配線，大多採用鋁配線。鋁配線係低電阻配線，且藉由鋁鈍化可獲得實用的可靠性。As such a conductive wiring, aluminum wiring is often used. The aluminum wiring is low-resistance wiring, and practical reliability can be obtained by aluminum passivation.
然而，關於高純度且高導電性的鋁配線，起因於備有鋁配線的功能裝置在製造過程中的熱履歷、長期的使用或保存等，在鋁配線表面容易產生凸丘(半球狀等之突起物)，容易引起絕緣不良等之可靠性降低。However, the high-purity and high-conductivity aluminum wiring is caused by the heat history of the functional device provided with the aluminum wiring during the manufacturing process, long-term use or storage, and the like, and it is easy to generate a dome on the surface of the aluminum wiring (hemispherical shape, etc.) The protrusions are likely to cause a decrease in reliability such as insulation failure.
高純度的鋁具有2.7μΩcm的電阻係數。為解消上述的凸丘產生的問題，以往，使用被少量添加有Nd(釹)或Ta(鉭)等之金屬的鋁合金。High purity aluminum has a resistivity of 2.7 μΩcm. In order to solve the problem of the above-mentioned ridges, an aluminum alloy to which a metal such as Nd (yttrium) or Ta (yttrium) is added in a small amount has been used.
因Nd或Ta之添加所致鋁合金的電阻係數之增加率各自為3.7μΩcm/原子%、8.6μΩcm/原子%。換言之，因添加1原子%的Nd至鋁而獲得之鋁合金的電阻係數，經計算是6.4μΩcm，會惡化。一般，鋁合金配線的目標電阻係數設為6μΩcm以下。The increase rate of the electrical resistivity of the aluminum alloy due to the addition of Nd or Ta was 3.7 μΩcm/atomic and 8.6 μΩcm/atomic, respectively. In other words, the electrical resistivity of the aluminum alloy obtained by adding 1 atom% of Nd to aluminum is calculated to be 6.4 μΩcm, which is deteriorated. Generally, the target resistivity of the aluminum alloy wiring is set to 6 μΩcm or less.
一方面，作為上述的導電配線，已知有銅合金配線。銅合金配線在耐鹼性的觀點上優於鋁合金配線，又，在耐藥品性的觀點，具有優異的特性。作為用於功能裝置的導電配線，銅合金配線的要求高。On the other hand, as the above-described conductive wiring, a copper alloy wiring is known. The copper alloy wiring is superior to the aluminum alloy wiring in terms of alkali resistance, and has excellent characteristics from the viewpoint of chemical resistance. As a conductive wiring for a functional device, copper alloy wiring is required to be high.
與鋁相較下，高純度的銅具有1.7μΩcm的電阻係數，被期待作為取代鋁合金配線之導電配線。然而，銅配線相對於連接於銅配線的構件或材料容易擴散，招致可靠性降低，銅配線的表面在未進行鋁鈍化下存在著銅氧化物的形成量經時增加的缺點。Compared with aluminum, high-purity copper has a resistivity of 1.7 μΩcm, and is expected to be used as a conductive wiring instead of aluminum alloy wiring. However, the copper wiring is easily diffused with respect to the member or material connected to the copper wiring, resulting in a decrease in reliability, and the surface of the copper wiring has a drawback that the amount of formation of copper oxide increases over time without aluminum passivation.
當形成於銅配線表面的銅氧化物的膜厚變厚，表面電阻變高而在電氣封裝上發生問題。銅氧化物的形成係表面電阻增加，再加上亦會對依接觸電阻的偏差所導致薄膜電晶體之閾值電壓(Vth)的偏差造成影響，故而並不佳。就銅配線或銅合金配線與各種配線或各種層膜之電氣封裝而言，因為要除去被形成在配線的表面之銅氧化物，所以無需像螯合洗淨那樣的前處理。When the film thickness of the copper oxide formed on the surface of the copper wiring is increased, the surface resistance becomes high and a problem occurs in electrical packaging. The formation of copper oxide increases the surface resistance, and it is also unfavorable because the deviation of the threshold voltage (Vth) of the thin film transistor is caused by the deviation of the contact resistance. Copper wiring or copper alloy wiring and various wiring or various layers of electricityIn the gas encapsulation, since the copper oxide formed on the surface of the wiring is removed, pretreatment such as chelation cleaning is not required.
近年提供一種具有被含有銦和鋅之氧化物層所夾持的銅層之金屬配線(例如，參照專利文獻1)。專利文獻1中，氧化鋅的含量設為10重量%以上且小於35重量%。於專利文獻1的[0050]段落，列記有氧化鋅(ZnO)、銦氧化物(InO)等。In recent years, a metal wiring having a copper layer sandwiched between oxide layers containing indium and zinc has been provided (for example, refer to Patent Document 1). In Patent Document 1, the content of zinc oxide is 10% by weight or more and less than 35% by weight. In the paragraph [0050] of Patent Document 1, zinc oxide (ZnO), indium oxide (InO), or the like is listed.
然而，專利文獻1的請求項1中，氧化物中的作為金屬元素的銦，且未定義金屬元素。因此，金屬元素的原子比(原子%)不明確。若假設換算銦氧化物(InO)中的金屬元素的原子比時，則在氧化鋅的下限值10重量%中，氧化物層中的原子比大約為15原子%。當鋅元素的量相對於銦元素與鋅元素的合計是超過10原子%時，耐鹼性會持續降低。However, in the claim 1 of Patent Document 1, indium in the oxide is a metal element, and a metal element is not defined. Therefore, the atomic ratio (atomic %) of the metal element is not clear. When the atomic ratio of the metal element in the indium oxide (InO) is assumed to be converted, the atomic ratio in the oxide layer is about 15 atom% in the lower limit of 10% by weight of the zinc oxide. When the amount of the zinc element is more than 10 atom% with respect to the total of the indium element and the zinc element, the alkali resistance is continuously lowered.
特別是，鋅元素的量越多，上述的耐鹼性之降低越顯著發生。又，當鋅元素的量超過10原子%時，氧化鋅與氧化銦之複合氧化物的表面電阻增大，成為電氣封裝之障礙。專利文獻1未揭示此種課題。再者，專利文獻1未針對銅的遷移或擴散的問題有任何揭示。In particular, the more the amount of the zinc element, the more significant the above-mentioned reduction in alkali resistance occurs. Further, when the amount of the zinc element exceeds 10 atom%, the surface resistance of the composite oxide of zinc oxide and indium oxide increases, which is an obstacle to electrical packaging. Patent Document 1 does not disclose such a problem. Further, Patent Document 1 does not disclose any problem concerning the migration or diffusion of copper.
又，在針對於玻璃基板或矽基板改善銅的密接性之技術方面，揭示一種將鋅(Zn)、鈣(Ca)、鎂(Mg)、錳(Mn)等作為合金元素添加於銅的技術(例如，參照專利文獻2及專利文獻3)。Further, in the technique for improving the adhesion of copper to a glass substrate or a tantalum substrate, zinc (Zn), calcium (Ca), magnesium (Mg), and manganese (Mn) are disclosed.A technique of adding copper as an alloying element (for example, refer to Patent Document 2 and Patent Document 3).
然而，就專利文獻2及專利文獻3而言，採用銅合金直接接觸於玻璃基板或薄膜電晶體的半導體層之構成，具有完全無法抑制銅相對於銅的基底層(玻璃基板、半導體層)擴散的問題。專利文獻2及專利文獻3當然没有揭示藉由銅合金層被導電性金屬氧化物所夾持的3層構成來解決課題。However, in Patent Document 2 and Patent Document 3, the copper alloy is directly in contact with the semiconductor layer of the glass substrate or the thin film transistor, and it is impossible to suppress the diffusion of copper to the underlying layer (glass substrate, semiconductor layer) of copper. The problem. Patent Document 2 and Patent Document 3 of course solve the problem by providing a three-layer structure in which a copper alloy layer is sandwiched by a conductive metal oxide.
又，在以銅合金形成的導電配線被直接形成於基板的構成中，例如，在配線寬度是10μm寬度以下的細線時，會有於製造工程中導電配線從基板剝離之情況。藉濕式蝕刻工程形成的導電配線係在其工程以後的工程，例如，洗淨工程、半導體圖案化工程及顯影工程等中，有時會發生起因於靜電破壞而部分剝離(導電配線缺陷或斷線)。導電配線的線寬越細，發生導電配線剝離的情況會越顯著。此種製造工程中的課題未揭示於專利文獻1及專利文獻2。又，專利文獻1、專利文獻2及專利文獻3任一者都未揭示利用靜電電容方式的接觸感測之技術。In the configuration in which the conductive wiring formed of the copper alloy is directly formed on the substrate, for example, when the wiring width is 10 μm or less, the conductive wiring may be peeled off from the substrate during the manufacturing process. The conductive wiring formed by the wet etching process is partially peeled off due to electrostatic breakdown in the post-engineering engineering, for example, cleaning engineering, semiconductor patterning engineering, and development engineering (conductive wiring defects or breaks) line). The thinner the line width of the conductive wiring, the more significant the peeling of the conductive wiring occurs. Problems in such a manufacturing process are not disclosed in Patent Document 1 and Patent Document 2. Further, none of Patent Document 1, Patent Document 2, and Patent Document 3 discloses a technique of contact sensing using a capacitive method.
專利文獻1 日本國特開2014-78700號公報Patent Document 1 Japanese Patent Laid-Open Publication No. 2014-78700
專利文獻2 日本國特開2011-91364號公報Patent Document 2 Japanese Patent Laid-Open Publication No. 2011-91364
專利文獻3 日本國專利第5099504號公報Patent Document 3 Japanese Patent No. 5099504
本發明係有鑒於上述課題而完成者，提供一種可防止銅的擴散或銅的遷移之發生，且可提升電氣封裝的可靠性之顯示裝置。The present invention has been made in view of the above problems, and provides a display device capable of preventing the occurrence of copper diffusion or copper migration and improving the reliability of an electrical package.
又，本發明提供一種可進行穩定的接觸感測、接觸感測感度高且能獲得良好的響應性之顯示裝置及顯示裝置基板。Further, the present invention provides a display device and a display device substrate which are capable of performing stable contact sensing, high sensitivity to contact sensing, and excellent responsiveness.
本發明第1態樣的顯示裝置，具備：第1基板；功能裝置；及第2基板，具有導電配線和因應施加於前述導電配線之電氣信號而驅動前述功能裝置的驅動裝置，且和前述第1基板對向配置，前述導電配線，係以藉第1導電性金屬氧化物層與第2導電性金屬氧化物層夾持銅合金層而成的3層所構成，前述銅合金層包含固溶於銅的第1元素、和負電性小於銅及前述第1元素的第2元素，前述第1元素及前述第2元素為，在添加於銅時的電阻係數上升率是1μΩcm/原子%以下的元素，前述銅合金層的電阻係數係在1.9μΩcm至6μΩcm的範圍內。A display device according to a first aspect of the present invention includes: a first substrate; a functional device; and a second substrate having a conductive wiring and a driving device for driving the functional device in response to an electrical signal applied to the conductive wiring, and the The substrate is disposed opposite to each other, and the conductive wiring is formed of three layers in which a copper alloy layer is sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer, and the copper alloy layer contains solid solution. The first element of copper and the second element having lower electronegativity than copper and the first element, the first element and the second element are such that the rate of increase in resistivity when added to copper is 1 μΩcm/ato% or less. The element, the aforementioned copper alloy layer has a resistivity in the range of 1.9 μΩcm to 6 μΩcm.
本發明第2態樣的顯示裝置，具備：具有第1導電配線之第1基板；功能裝置；及第2基板，具有第2導電配線和因應施加於前述第2導電配線之電氣信號而驅動前述功能裝置的驅動裝置，且和前述第1基板對向配置，前述第1導電配線及前述第2導電配線的每一者，係以藉第1導電性金屬氧化物層與第2導電性金屬氧化物層夾持銅合金層而成的3層所構成，前述銅合金層包含固溶於銅的第1元素、和負電性小於銅及前述第1元素的第2元素，前述第1元素及前述第2元素為，在添加於銅時的電阻係數上升率是1μΩcm/原子%以下的元素，前述銅合金層的電阻係數係在1.9μΩcm至6μΩcm的範圍內。A display device according to a second aspect of the present invention includes: a first substrate having a first conductive wiring; a functional device; and a second substrate having a second conductive wiring and an electric signal applied to the second conductive wiring to drive the The driving device of the functional device is disposed to face the first substrate, and each of the first conductive wiring and the second conductive wiring is oxidized by the first conductive metal oxide layer and the second conductive metal The material layer is composed of three layers in which a copper alloy layer is sandwiched, and the copper alloy layer includes a first element that is solid-solubilized in copper, and a second element that is less negative in charge than copper and the first element, and the first element and the first element. The second element is an element having a resistivity increase rate of 1 μΩcm/atomic or less when added to copper, and the resistivity of the copper alloy layer is in the range of 1.9 μΩcm to 6 μΩcm.
關於本發明第2態樣的顯示裝置，亦可為：具備：第3導電配線，設於前述第1基板或前述第2基板，且在平面視圖中，在相對於前述第1導電配線延伸的方向正交的方向延伸；及控制部，檢測前述第1導電配線與前述第3導電配線之間的靜電電容之變化而進行接觸感測，前述第3導電配線，係以藉第1導電性金屬氧化物層與第2導電性金屬氧化物層夾持銅合金層而成的3層所構成，前述銅合金層包含固溶於銅的第1元素、和負電性小於銅及前述第1元素的第2元素，前述第1元素及前述第2元素為，在添加於銅時的電阻係數上升率是1μΩcm/原子%以下的元素，前述銅合金層的電阻係數係在1.9μΩcm至6μΩcm的範圍內。In the display device according to the second aspect of the present invention, the third conductive wiring may be provided on the first substrate or the second substrate, and may extend in the plan view with respect to the first conductive wiring. And a control unit that detects a change in electrostatic capacitance between the first conductive wiring and the third conductive wiring to perform contact sensing, and the third conductive wiring is made of a first conductive metal The oxide layer and the second conductive metal oxide layer are composed of three layers in which a copper alloy layer is sandwiched, and the copper alloy layer contains a first element which is solid-solubilized in copper and a negatively chargeable property lower than copper and the first element. In the second element, the first element and the second element are elements having a resistivity increase rate of 1 μΩcm/nm or less when added to copper, and the resistivity of the copper alloy layer is in a range of 1.9 μΩcm to 6 μΩcm. .
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述第1元素係鋅，前述第2元素係鈣。In the display device according to the first aspect or the second aspect of the present invention, the first element may be zinc and the second element may be calcium.
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述第1導電性金屬氧化物層及前述第2導電性金屬氧化物層為，含有作為主要導電性金屬氧化物的氧化銦，並含有1種以上選自氧化銻、氧化鋅及氧化鎵所構成的群之導電性金屬氧化物。In the display device according to the first aspect or the second aspect of the present invention, the first conductive metal oxide layer and the second conductive metal oxide layer may contain a main conductive metal oxide. Indium oxide and one or more conductive metal oxides selected from the group consisting of cerium oxide, zinc oxide, and gallium oxide.
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述驅動裝置係為具有和閘極絕緣層接觸且以氧化物半導體構成之通道層，並驅動前述功能裝置之薄膜電晶體，前述驅動裝置係設於和前述第1基板對向的前述第2基板的面。In the display device according to the first aspect or the second aspect of the present invention, the driving device may be a thin film device having a channel layer which is in contact with the gate insulating layer and is formed of an oxide semiconductor, and drives the functional device. In the crystal, the driving device is provided on a surface of the second substrate that faces the first substrate.
關於本發明第1態樣，亦可為：前述驅動裝置係具備設於閘極絕緣層上之閘極電極，前述閘極電極係構成前述導電配線的一部分。In the first aspect of the invention, the driving device may include a gate electrode provided on the gate insulating layer, and the gate electrode may constitute a part of the conductive wiring.
關於本發明第2態樣，亦可為：前述驅動裝置係具備設於閘極絕緣層上之閘極電極，前述閘極電極係構成前述第2導電配線的一部分。According to a second aspect of the present invention, the driving device may include a gate electrode provided on the gate insulating layer, and the gate electrode may constitute a part of the second conductive wiring.
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述氧化物半導體係含有1種以上選自氧化銦(In2O3)、氧化鎵(Ga2O3)、氧化鋅(ZnO)所構成的群，且至少包含氧化銻(Sb2O3)、氧化鉍(Bi2O3)中任一者。In the display device according to the first aspect or the second aspect of the invention, the oxide semiconductor system may contain one or more kinds selected from the group consisting of indium oxide (In2 O3 ), gallium oxide (Ga2 O3 ), and oxidation. A group consisting of zinc (ZnO) and containing at least one of cerium oxide (Sb2 O3 ) and cerium oxide (Bi2 O3 ).
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述閘極絕緣層係含有氧化鈰的氧化物，或含有氧化鈰的氧氮化物。In the display device according to the first aspect or the second aspect of the present invention, the gate insulating layer may contain an oxide of cerium oxide or an oxynitride containing cerium oxide.
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述功能裝置係有機電致發光層，前述有機電致發光層係設在與前述第1基板對向之前述第2基板的面。In the display device according to the first aspect or the second aspect of the present invention, the functional device may be an organic electroluminescence layer, and the organic electroluminescence layer may be provided on the second substrate opposite to the first substrate. The face of the substrate.
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述功能裝置係發光二極體層，前述發光二極體層係設在與前述第1基板對向之前述第2基板的面。In the display device according to the first aspect or the second aspect of the present invention, the functional device may be a light emitting diode layer, and the light emitting diode layer may be provided on the second substrate facing the first substrate. surface.
關於本發明第1態樣或第2態樣的顯示裝置，亦可為：前述功能裝置係液晶層，前述液晶層係配設在前述第1基板與前述第2基板之間。In the display device according to the first aspect or the second aspect of the present invention, the functional device may be a liquid crystal layer, and the liquid crystal layer may be disposed between the first substrate and the second substrate.
本發明第3態樣的顯示裝置基板具備：基板本體；黑色矩陣，設在前述基板本體上；及第1接觸感測配線，在平面視圖中，設在與前述黑色矩陣對應之位置，前述第1接觸感測配線，係以藉第1導電性金屬氧化物層與第2導電性金屬氧化物層夾持銅合金層而成的3層所構成，前述銅合金層係包含固溶於銅的第1元素、和負電性小於銅及前述第1元素的第2元素，前述第1元素及前述第2元素為，在添加於銅時的電阻係數上升率是1μΩcm/原子%以下的元素，前述銅合金層的電阻係數係在1.9μΩcm至6μΩcm的範圍內。A display device substrate according to a third aspect of the present invention includes: a substrate body; a black matrix provided on the substrate body; and a first contact sensing wiring provided at a position corresponding to the black matrix in plan view, 1 contact sensing wiring is based on the first conductive metal oxide layerThe second conductive metal oxide layer is composed of three layers in which a copper alloy layer is sandwiched, and the copper alloy layer contains a first element which is solid-solubilized in copper and a second element which is less negative in electric power than copper and the first element. The first element and the second element are elements having a resistivity increase rate of 1 μΩcm/nm or less when added to copper, and the resistivity of the copper alloy layer is in a range of 1.9 μΩcm to 6 μΩcm.
關於本發明第3態樣的顯示裝置基板，亦可為：具備：絕緣層，覆蓋前述第1接觸感測配線；及第2接觸感測配線，於平面視圖中，在相對於前述第1接觸感測配線延伸的方向正交的方向延伸，且於對應前述黑色矩陣的位置設置在前述絕緣層上，前述第2接觸感測配線，係以藉第1導電性金屬氧化物層與第2導電性金屬氧化物層夾持銅合金層而成的3層所構成，前述銅合金層係包含固溶於銅的第1元素、和負電性小於銅及前述第1元素的第2元素，前述第1元素及前述第2元素為，在添加於銅時的電阻係數上升率是1μΩcm/原子%以下的元素，前述銅合金層的電阻係數係在1.9μΩcm至6μΩcm的範圍內。The display device substrate according to the third aspect of the present invention may further include: an insulating layer covering the first contact sensing wiring; and a second contact sensing wiring that is in contact with the first contact in plan view The sensing wiring extends in a direction orthogonal to the direction of the wiring, and is disposed on the insulating layer at a position corresponding to the black matrix. The second contact sensing wiring is formed by the first conductive metal oxide layer and the second conductive layer. The metal alloy layer is composed of three layers in which a copper alloy layer is sandwiched, and the copper alloy layer includes a first element that is solid-solubilized in copper and a second element that is less negatively-charged than copper and the first element, and the first The first element and the second element are elements having a resistivity increase rate of 1 μΩcm/atomic or less when added to copper, and the resistivity of the copper alloy layer is in the range of 1.9 μΩcm to 6 μΩcm.
依據本發明的態樣，能提供即便將使用了銅合金的導電配線用於顯示裝置，也可防止銅的擴散或銅的遷移之發生，且可提升電氣封裝的可靠性之顯示裝置。依據本發明的態樣，可提供一種藉由使用銅合金作為導電配線或接觸感測配線之構成材料，可進行穩定的接觸感測、接觸感測感度高且能獲得良好的響應性之顯示裝置及顯示裝置基板。According to the aspect of the invention, it is possible to provide a display device which can prevent the diffusion of copper or the migration of copper even when a conductive wiring using a copper alloy is used for a display device, and which can improve the reliability of the electrical package. According to an aspect of the present invention, a copper alloy can be provided as a conductive compoundA constituent device of a line or a contact sensing wiring, which can perform stable contact sensing, high sensitivity of contact sensing, and good responsiveness, and a display device substrate.
2、774‧‧‧第2接觸感測配線(導電配線、第3導電配線)2. 774‧‧‧2nd contact sensing wiring (conductive wiring, 3rd conductive wiring)
3、611‧‧‧第1接觸感測配線(導電配線、第1導電配線)3, 611‧‧‧1st contact sensing wiring (conductive wiring, first conductive wiring)
4‧‧‧第2導電性金屬氧化物層4‧‧‧2nd conductive metal oxide layer
5‧‧‧銅合金層5‧‧‧copper alloy layer
6‧‧‧第1導電性金屬氧化物層6‧‧‧1st conductive metal oxide layer
8‧‧‧黑色層8‧‧‧Black layer
9‧‧‧側面9‧‧‧ side
10、75‧‧‧閘極配線10, 75‧‧‧ gate wiring
11‧‧‧第1絕緣層(絕緣層)11‧‧‧1st insulation layer (insulation layer)
12‧‧‧第2絕緣層(絕緣層)12‧‧‧2nd insulation layer (insulation layer)
13‧‧‧第3絕緣層(絕緣層)13‧‧‧3rd insulation layer (insulation layer)
14‧‧‧第4絕緣層(絕緣層)14‧‧‧4th insulation layer (insulation layer)
16‧‧‧透明樹脂層16‧‧‧Transparent resin layer
17、72‧‧‧共通電極17, 72‧‧‧ common electrode
17A‧‧‧電極部17A‧‧‧Electrode
17B‧‧‧導電連接部17B‧‧‧Electrical connection
17K‧‧‧壁部17K‧‧‧ wall
20‧‧‧畫素電極20‧‧‧pixel electrodes
20K‧‧‧內壁20K‧‧‧ inner wall
20S‧‧‧通孔20S‧‧‧through hole
21、22、44、62、65‧‧‧透明基板21, 22, 44, 62, 65‧‧‧ transparent substrate
24、77‧‧‧源極電極24, 77‧‧‧ source electrode
25、76、95‧‧‧閘極電極25, 76, 95‧‧ ‧ gate electrode
26、56、78‧‧‧汲極電極26, 56, 78‧‧‧汲electrode
27‧‧‧通道層27‧‧‧Channel layer
28、68‧‧‧主動元件28, 68‧‧‧ active components
30‧‧‧共同配線30‧‧‧Common wiring
31、66‧‧‧源極配線31, 66‧‧‧ source wiring
45‧‧‧基板45‧‧‧Substrate
51‧‧‧濾光片51‧‧‧ Filters
58‧‧‧通道層58‧‧‧Channel layer
71‧‧‧畫素電極71‧‧‧ pixel electrodes
73‧‧‧薄膜電晶體73‧‧‧film transistor
79‧‧‧通道層79‧‧‧Channel layer
87‧‧‧上部電極87‧‧‧Upper electrode
88‧‧‧下部電極88‧‧‧lower electrode
91‧‧‧電洞注入層91‧‧‧ hole injection layer
92‧‧‧發光層92‧‧‧Lighting layer
93‧‧‧接觸孔93‧‧‧Contact hole
94‧‧‧觸排94‧‧‧Touch
96‧‧‧平坦化層96‧‧‧flattening layer
100、400、600‧‧‧顯示裝置基板100, 400, 600‧‧‧ display device substrate
105‧‧‧第2透明樹脂層105‧‧‧2nd transparent resin layer
108‧‧‧第1透明樹脂層108‧‧‧1st transparent resin layer
109‧‧‧密封層109‧‧‧ Sealing layer
110‧‧‧顯示部110‧‧‧Display Department
120‧‧‧控制部120‧‧‧Control Department
121‧‧‧映像信號控制部121‧‧‧Image Signal Control Department
122‧‧‧接觸感測控制部122‧‧‧Contact Sensing Control Department
123‧‧‧系統控制部123‧‧‧System Control Department
200、500、700‧‧‧陣列基板200, 500, 700‧‧‧ array substrates
300、800‧‧‧液晶層300, 800‧‧‧ liquid crystal layer
604‧‧‧第1光吸收層604‧‧‧1st light absorbing layer
605‧‧‧第2光吸收層605‧‧‧2nd light absorbing layer
721‧‧‧絕緣層721‧‧‧Insulation
723‧‧‧絕緣層723‧‧‧Insulation
圖1係顯示構成本發明第1實施形態的顯示裝置之控制部(映像信號控制部、系統控制部及接觸感測控制部)及顯示部的方塊圖。1 is a block diagram showing a control unit (a video signal control unit, a system control unit, and a contact sensing control unit) and a display unit constituting the display device according to the first embodiment of the present invention.
圖2係將構成本發明第1實施形態的顯示裝置之陣列基板作一部分顯示的平面圖，為從觀察者側所見的平面圖。Fig. 2 is a plan view showing a part of an array substrate constituting the display device according to the first embodiment of the present invention, which is a plan view seen from the observer side.
圖3A係將本發明第1實施形態的顯示裝置作一部分顯示的剖面圖，為沿著圖2所示的B-B’線之剖面圖。Fig. 3A is a cross-sectional view showing a part of the display device according to the first embodiment of the present invention, taken along line B-B' shown in Fig. 2;
圖3B係將本發明第1實施形態的顯示裝置作一部分顯示的剖面圖，為放大顯示共通電極之放大剖面圖。3B is a cross-sectional view showing a part of the display device according to the first embodiment of the present invention, and is an enlarged cross-sectional view showing the common electrode in an enlarged manner.
圖4係將本發明第1實施形態的顯示裝置作一部分顯示的剖面圖，為沿著圖2所示之C-C’線的剖面圖。Fig. 4 is a cross-sectional view showing a part of the display device according to the first embodiment of the present invention, taken along line C-C' shown in Fig. 2;
圖5係將構成本發明第1實施形態的顯示裝置之顯示裝置基板作一部分顯示的剖面圖，為放大顯示圖3A所示之接觸感測配線(第1導電配線)的放大剖面圖。5 is a cross-sectional view showing a part of a display device substrate constituting the display device according to the first embodiment of the present invention, and is an enlarged cross-sectional view showing the contact sensing wiring (first conductive wiring) shown in FIG. 3A in an enlarged manner.
圖6係顯示本發明第1實施形態的顯示裝置中接觸感測配線作為接觸驅動電極發揮功能，且共通電極作為接觸檢測電極發揮功能的情況下，接觸感測配線與共通電極之間產生電場的狀態之示意剖面圖。In the display device according to the first embodiment of the present invention, when the contact sense line functions as a contact drive electrode and the common electrode functions as a contact detection electrode, an electric field is generated between the contact sense line and the common electrode. A schematic cross-sectional view of the state.
圖7係顯示本發明第1實施形態的顯示裝置之示意剖面圖，為顯示手指等之指標接觸或接近於顯示裝置基板的觀察者側的表面時的電場之生成狀態的變化之剖面圖。7 is a schematic cross-sectional view showing a display device according to the first embodiment of the present invention, and is a cross-sectional view showing a change in a state in which an electric field is generated when an index of a finger or the like is in contact with or close to a surface on the observer side of the display device substrate.
圖8係將本發明第2實施形態的顯示裝置作一部分顯示的剖面圖。Fig. 8 is a cross-sectional view showing a part of a display device according to a second embodiment of the present invention.
圖9係將構成本發明第2實施形態的顯示裝置之陣列基板作一部分顯示的部分剖面圖。Fig. 9 is a partial cross-sectional view showing a part of an array substrate constituting a display device according to a second embodiment of the present invention.
圖10係將本發明第3實施形態的顯示裝置作一部分顯示的剖面圖。Fig. 10 is a cross-sectional view showing a part of a display device according to a third embodiment of the present invention.
圖11係將構成本發明第3實施形態的顯示裝置之顯示裝置基板作一部分顯示的剖面圖，為放大顯示圖10的符號P所示之接觸感測配線(第1導電配線)的放大剖面圖。11 is a cross-sectional view showing a part of a display device substrate constituting the display device according to the third embodiment of the present invention, and is an enlarged cross-sectional view showing the contact sensing wiring (first conductive wiring) indicated by the symbol P in FIG. .
圖12係將構成本發明第3實施形態的顯示裝置之陣列基板作一部分顯示的平面圖，為沿著圖10所示之D-D’線的圖。Fig. 12 is a plan view showing a part of the array substrate constituting the display device of the third embodiment of the present invention, taken along the line D-D' shown in Fig. 10.
圖13係將本發明第3實施形態的顯示裝置作一部分顯示的剖面圖，為沿著圖12所示之E-E’線的圖。Fig. 13 is a cross-sectional view showing a portion of the display device according to the third embodiment of the present invention, taken along the line E-E' shown in Fig. 12.
以下，一邊參照圖面一邊針對本發明實施形態作說明。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
在以下說明中，對於相同或實質相同的功能及構成要素，賦予相同符號，省略或簡化其說明，或僅於必要情況進行說明。在各圖中，為將各構成要素設成可在圖面上辨識程度的大小，所以適宜地使各構成要素的尺寸及比率與實際者相異。又，因應需要，省略難以圖示的要素，例如構成顯示裝置的絕緣層、緩衝層、形成半導體的通道層之複數層的構成，及形成導電層的複數層構成等之圖示。In the following description, the same or substantially the same functions and components are denoted by the same reference numerals, and the description thereof is omitted or simplified, or only necessary.The situation is explained. In each of the drawings, in order to set each component as a size that can be recognized on the drawing, the size and ratio of each component are appropriately different from those of the actual one. Further, if necessary, elements that are difficult to be illustrated, such as a structure constituting an insulating layer of a display device, a buffer layer, a plurality of layers forming a channel layer of a semiconductor, and a plurality of layers forming a conductive layer, are exemplified.
本發明實施形態的顯示裝置係具備：功能裝置；及因應施加於導電配線的電氣信號以驅動功能裝置的驅動裝置。A display device according to an embodiment of the present invention includes a functional device and a driving device that drives the functional device in response to an electrical signal applied to the conductive wiring.
作為本發明實施形態涉及的功能裝置，可例舉控制接觸感測的控制部、顯示裝置中進行顯示功能之顯示元件、機械要素零件、靜電電容感測器或光感測器等之輸入元件、致動器、記憶元件等。具體言之，可例舉液晶(Liquid Crystal)、發光二極體(LED：Light Emitting Diode)、有機EL(OLED：Organic Light Emitting Diode)、EMS(Electro Mechanical System；機電系統)元件、MEMS(Micro Electro Mechanical System；微機電系統)元件、IMOD(Interferometric Modulation；干涉調變顯示器)元件、RFID(Radio Frequency Identification；無線射頻識別)元件等。The functional device according to the embodiment of the present invention may, for example, be a control unit that controls contact sensing, a display element that performs a display function in a display device, an input component of a mechanical element component, a capacitance sensor, or a photo sensor, Actuators, memory components, etc. Specifically, a liquid crystal (Liquid Crystal), a light emitting diode (LED), an organic EL (OLED: Organic Light Emitting Diode), an EMS (Electro Mechanical System) element, and a MEMS (Micro) can be exemplified. Electro Mechanical System; MEMS (Interferometric Modulation) component, RFID (Radio Frequency Identification) component, and the like.
作為驅動裝置，可例舉薄膜電晶體或薄膜二極體等之主動元件等。薄膜電晶體或二極體因為係藉由來自含有導電配線的控制系電路之電氣信號而具有可驅動上述功能裝置的功能，故而稱為驅動裝置。作為一例，驅動裝置係具有和閘極絕緣層接觸且以氧化物半導體構成的通道層並將功能裝置驅動之薄膜電晶體。此外，本發明中，未限定以驅動裝置驅動功能裝置。在以下記載中，有時將薄膜電晶體記載成主動元件。The driving device may, for example, be an active device such as a thin film transistor or a thin film diode. The thin film transistor or diode is driven by the electrical signal from the control system circuit containing the conductive wiringThe function of the functional device is called a driving device. As an example, the driving device is a thin film transistor having a channel layer which is in contact with the gate insulating layer and is formed of an oxide semiconductor and drives the functional device. Further, in the present invention, it is not limited to drive the functional device with the driving device. In the following description, a thin film transistor may be described as an active element.
作為可用於本發明實施形態的第1基板或第2基板等之基板，可適用玻璃基板、石英基板、藍寶石基板、陶瓷基板、矽、碳化矽、矽鍺等之半導體基板或塑膠基板等。As a substrate which can be used for the first substrate or the second substrate of the embodiment of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a semiconductor substrate such as tantalum, niobium carbide or tantalum, or a plastic substrate can be applied.
例如，使用玻璃基板等之可見區域透明的基板作為第1基板，使用矽基板等作為第2基板，可構成反射型顯示裝置。For example, a transparent display substrate such as a glass substrate can be used as the first substrate, and a tantalum substrate or the like can be used as the second substrate to form a reflective display device.
將微發光二極體(Micro LED)等之發光元件排列成矩陣狀而成的大型顯示裝置、投影機或穿戴顯示器用的小型顯示裝置也可適用本發明。The present invention can also be applied to a large-sized display device in which a light-emitting elements such as a micro-light-emitting diode (Micro LED) are arranged in a matrix, a projector, or a small-sized display device for wearing a display.
第1基板、第2基板且使用於第1導電配線、第2導電配線、第3導電配線等之「第1」、「第2」等之序數詞係為避免構成要素的混淆而附上的，未限定數量。第1導電配線、第2導電配線、第3導電配線在以下記載中有時僅稱為導電配線。The ordinal numbers of "first" and "second" used for the first and second substrates, such as the first conductive wiring, the second conductive wiring, and the third conductive wiring, are attached to avoid confusion of constituent elements. , unlimited number. The first conductive wiring, the second conductive wiring, and the third conductive wiring may be simply referred to as conductive wirings in the following description.
第1導電性金屬氧化物層及第2導電性金屬氧化物層，於以下說明中，有時僅略稱為導電性金屬氧化物層。本發明實施形態的顯示裝置能具有依據靜電電容方式的接觸感測功能。如後述般，第1導電配線或第3導電配線等之導電配線係可用作為接觸感測之檢測配線或驅動配線。在以下記載中，關於接觸感測的導電配線、電極及信號，有時僅稱為接觸配線、接觸驅動配線、接觸檢測配線、接觸電極及接觸驅動信號。將為了驅動接觸感測而被施加至接觸感測配線的電壓稱為接觸驅動電壓，將為了驅動顯示功能層、即液晶層而被施加於共通電極與畫素電極間之電壓稱為液晶驅動電壓。將驅動有機EL層的電壓稱為有機EL驅動電壓。連接於共通電極的導電配線有時稱為共同配線。The first conductive metal oxide layer and the second conductive metal oxide layer may be simply referred to as a conductive metal oxide layer in the following description.The display device according to the embodiment of the present invention can have a contact sensing function in accordance with an electrostatic capacitance method. As will be described later, the conductive wiring such as the first conductive wiring or the third conductive wiring can be used as the detection wiring or the driving wiring for contact sensing. In the following description, the conductive wiring, the electrode, and the signal for contact sensing may be simply referred to as a contact wiring, a contact driving wiring, a contact detecting wiring, a contact electrode, and a contact driving signal. The voltage applied to the contact sensing wiring for driving the contact sensing is referred to as a contact driving voltage, and a voltage applied between the common electrode and the pixel electrode for driving the display function layer, that is, the liquid crystal layer is referred to as a liquid crystal driving voltage. . The voltage that drives the organic EL layer is referred to as an organic EL driving voltage. The conductive wiring connected to the common electrode is sometimes referred to as a common wiring.
以下，就本發明第1實施形態的顯示裝置DSP1，一邊參照圖1至圖7一邊作說明。Hereinafter, the display device DSP1 according to the first embodiment of the present invention will be described with reference to Figs. 1 to 7 .
在以下所述的各實施形態中，針對特徵的部分作說明，例如，針對一般液晶顯示裝置所用的構成要素與本實施形態的顯示裝置没有差異的部分省略說明。In each of the embodiments described below, the description will be omitted. For example, the components used in the general liquid crystal display device and the display device of the present embodiment are not described.
本發明實施形態的顯示裝置DSP1中，功能裝置為液晶層，驅動裝置為薄膜電晶體(主動元件)。In the display device DSP1 according to the embodiment of the present invention, the functional device is a liquid crystal layer, and the driving device is a thin film transistor (active device).
又，本發明實施形態的顯示裝置DSP1係使用內嵌型。此處，所謂「內嵌型(in-cell)」係意味著接觸感測功能內建於液晶顯示裝置而成的液晶顯示裝置，或者，將接觸感測功能與液晶顯示裝置一體化而成的液晶顯示裝置。通常，在隔著液晶層將顯示裝置基板和陣列基板(TFT基板)貼合的液晶顯示裝置中，在顯示裝置基板及陣列基板各自外側的面貼附偏光膜。換言之，本發明實施形態涉及的內嵌型(in-cell)的液晶顯示裝置係指：位在相互對向的2個偏光膜之間並於厚度方向構成液晶顯示裝置的任一部位，具備接觸感測功能之液晶顯示裝置。Further, the display device DSP1 according to the embodiment of the present invention uses an in-line type. Here, the term "in-cell" means a liquid crystal display device in which a touch sensing function is built in a liquid crystal display device, orA liquid crystal display device in which a touch sensing function is integrated with a liquid crystal display device. In general, in a liquid crystal display device in which a display device substrate and an array substrate (TFT substrate) are bonded via a liquid crystal layer, a polarizing film is attached to a surface of each of the display device substrate and the array substrate. In other words, the in-cell liquid crystal display device according to the embodiment of the present invention refers to any portion of the liquid crystal display device which is disposed between the two polarizing films facing each other and has a thickness direction. A liquid crystal display device that senses the function.
圖1係顯示本發明第1實施形態的顯示裝置DSP1之方塊圖。如圖1所示，本實施形態的顯示裝置DSP1具備顯示部110、及用以控制顯示部110及接觸感測功能之控制部120。Fig. 1 is a block diagram showing a display device DSP1 according to the first embodiment of the present invention. As shown in FIG. 1, the display device DSP1 of the present embodiment includes a display unit 110 and a control unit 120 for controlling the display unit 110 and the touch sensing function.
控制部120具有公知的構成，備有映像信號控制部121(第一控制部)、接觸感測控制部122(第二控制部)、及系統控制部123(第三控制部)。The control unit 120 has a known configuration and includes a video signal control unit 121 (first control unit), a contact sensing control unit 122 (second control unit), and a system control unit 123 (third control unit).
映像信號控制部121係將設於陣列基板200的共通電極17(後述)設為定電位，並對設於陣列基板200的閘極配線10(後述的掃描線)及源極配線31(後述的信號線)傳送信號。藉由映像信號控制部121對共通電極17與畫素電極20(後述)之間施加顯示用的液晶驅動電壓，在陣列基板200上產生邊緣電場，液晶分子沿著邊緣電場旋轉使液晶層300被驅動。藉此，在陣列基板200上顯示畫像。複數個畫素電極20的每一者，經由源極配線(信號線)被個別地施加例如矩形波的映像信號。又，作為矩形波，亦可為正或負的直流矩形波或交流矩形波。映像信號控制部121將此種映像信號送至源極配線。The image signal control unit 121 sets the common electrode 17 (described later) provided in the array substrate 200 to a constant potential, and the gate wiring 10 (scanning line to be described later) and the source wiring 31 provided on the array substrate 200 (described later) Signal line) transmits signals. The display signal control unit 121 applies a liquid crystal driving voltage for display between the common electrode 17 and the pixel electrode 20 (described later), generates a fringe electric field on the array substrate 200, and rotates the liquid crystal molecules along the fringe electric field to cause the liquid crystal layer 300 to be drive. Thereby, an image is displayed on the array substrate 200. Each of the plurality of pixel electrodes 20 is individually applied with a signal signal of, for example, a rectangular wave via a source wiring (signal line). Again, as a momentThe shape wave can also be a positive or negative DC rectangular wave or an AC rectangular wave. The video signal control unit 121 sends such a video signal to the source wiring.
接觸感測控制部122係向接觸感測配線3(第1導電配線)施加接觸感測驅動電壓，檢測在接觸感測配線3與共通電極17(第2導電配線)之間產生的靜電電容之變化，以進行接觸感測。The contact sensing control unit 122 applies a contact sensing driving voltage to the contact sensing wiring 3 (first conductive wiring), and detects an electrostatic capacitance generated between the contact sensing wiring 3 and the common electrode 17 (second conductive wiring). Change for contact sensing.
系統控制部123係可控制映像信號控制部121及接觸感測控制部122，將液晶驅動與靜電電容之變化的檢測交互地、亦即分時地進行。又，系統控制部123亦可具有以與液晶驅動頻率和接觸感測驅動頻率相異的頻率，或相異的電壓來驅動液晶之功能。The system control unit 123 controls the video signal control unit 121 and the contact sensing control unit 122 to perform the liquid crystal drive and the detection of the change in the electrostatic capacitance, that is, in a time-sharing manner. Further, the system control unit 123 may have a function of driving the liquid crystal at a frequency different from the liquid crystal driving frequency and the contact sensing driving frequency, or a different voltage.
關於具有此種功能的系統控制部123，例如，檢測顯示裝置DSP1所撿拾來自外部環境的雜訊之頻率，選擇與雜訊頻率相異的接觸感測驅動頻率。藉此，可減輕雜訊的影響。又，關於此種系統控制部123，亦可選定配合手指或筆等之指標(pointer)的掃描速度之接觸感測驅動頻率。The system control unit 123 having such a function detects, for example, the frequency at which the display device DSP1 picks up noise from the external environment, and selects a contact sensing drive frequency that is different from the noise frequency. This can reduce the impact of noise. Further, the system control unit 123 may select a contact sensing drive frequency that matches the scanning speed of a pointer such as a finger or a pen.
在具有圖1所示之構成的顯示裝置DSP1中，共通電極17係同時具有向共通電極17與畫素電極20之間施加顯示用的液晶驅動電壓以驅動液晶之功能、及檢測在接觸感測配線3與共通電極17之間產生的靜電電容之變化的接觸感測功能。本發明實施形態涉及的接觸感測配線係以導電係數良好的金屬層形成，故能降低接觸感測配線的電阻值而使接觸感度提升(後述)。In the display device DSP1 having the configuration shown in FIG. 1, the common electrode 17 has a function of applying a liquid crystal driving voltage for display between the common electrode 17 and the pixel electrode 20 to drive the liquid crystal, and detecting contact sensing. A contact sensing function of a change in electrostatic capacitance generated between the wiring 3 and the common electrode 17. Contact sensing configuration according to an embodiment of the present inventionSince the wire is formed of a metal layer having a good electrical conductivity, the resistance value of the contact sensing wiring can be lowered to improve the contact sensitivity (described later).
控制部120如後述，係以具有在映像顯示的穩定期間及映像顯示後的黑顯示穩定期間當中至少一穩定期間，進行基於接觸感測配線3及共通電極17的接觸感測驅動之功能者較佳。As will be described later, the control unit 120 has a function of performing contact sensing driving by the contact sensing wiring 3 and the common electrode 17 at least one stable period during the stable period of the image display and the black display stabilization period after the image display. good.
本實施形態的液晶顯示裝置係可具備後述之實施形態的顯示裝置基板。又，以下記載的「平面視圖中」，係意味著觀察者從觀察液晶顯示裝置的顯示面(顯示裝置用基板的平面)的方向所見之平面。本發明實施形態的液晶顯示裝置之顯示部的形狀、或規定畫素的畫素開口部之形狀、構成液晶顯示裝置之畫素數係不受限定。其中，在以下詳述的實施形態中，平面視圖中，將畫素開口部的短邊方向規定為X方向，長邊的方向(長度方向)規定為Y方向，且將透明基板的厚度方向規定為Z方向以說明液晶顯示裝置。以下的實施形態中，亦可將上述所規定的X方向與Y方向替換來構成液晶顯示裝置。The liquid crystal display device of the present embodiment can include a display device substrate of an embodiment to be described later. In the "plan view" described below, it means the plane seen by the observer from the direction in which the display surface (plane of the display device substrate) of the liquid crystal display device is observed. The shape of the display unit of the liquid crystal display device of the embodiment of the present invention, or the shape of the pixel opening portion of the predetermined pixel, and the number of pixels constituting the liquid crystal display device are not limited. In the embodiment described in detail below, in the plan view, the short side direction of the pixel opening portion is defined as the X direction, and the long side direction (longitudinal direction) is defined as the Y direction, and the thickness direction of the transparent substrate is defined. The Z direction is used to explain the liquid crystal display device. In the following embodiments, the liquid crystal display device may be configured by replacing the above-described predetermined X direction and Y direction.
又，圖2~圖7中，賦予液晶層300初期配向的配向膜、偏光膜、位相差膜等之光學膜、保護用的蓋玻璃等係被省略。在顯示裝置DSP1的表面及背面各自上以光軸成為正交偏光(Crossed Nicol)的方式貼附偏光膜。In addition, in FIG. 2 to FIG. 7 , an alignment film, a polarizing film, an optical film such as a retardation film, and a cover glass for protection which are initially aligned in the liquid crystal layer 300 are omitted. A polarizing film is attached to each of the front surface and the back surface of the display device DSP1 such that the optical axis is crossed polarized.
本實施形態的顯示裝置DSP1中，採用FFS液晶驅動方式(Fringe Field Switching；邊緣電場切換)。就此液晶驅動方式而言，藉由在共通電極17與畫素電極20之間產生的電場，特別是藉由在稱為邊緣的電極端部產生的電場，使構成液晶層300的液晶分子驅動。此外，本發明未限定FFS液晶驅動方式。作為液晶層，亦可採用垂直配向的液晶層。In the display device DSP1 of the present embodiment, an FFS liquid crystal driving method (Fringe Field Switching) is employed. In the liquid crystal driving method, the liquid crystal molecules constituting the liquid crystal layer 300 are driven by an electric field generated between the common electrode 17 and the pixel electrode 20, particularly by an electric field generated at an end portion of the electrode called an edge. Further, the present invention does not limit the FFS liquid crystal driving method. As the liquid crystal layer, a vertically aligned liquid crystal layer can also be used.
圖2係將構成本發明第1實施形態的顯示裝置DSP1之陣列基板200作一部分顯示的平面圖，從觀察者側所見的平面圖。圖2中，為了容易清楚地說明陣列基板的構造，省略與陣列基板對向的顯示裝置基板之圖示。Fig. 2 is a plan view showing a part of the array substrate 200 constituting the display device DSP1 according to the first embodiment of the present invention, as seen from the observer side. In FIG. 2, in order to clearly explain the structure of the array substrate, the illustration of the display device substrate facing the array substrate is omitted.
顯示裝置DSP1在陣列基板200上具備：複數個源極配線31；複數個閘極配線10；及複數個共同配線30(導電配線、第2導電配線)。源極配線31分別以具有在Y方向(第1方向)延伸的線狀圖案之方式形成。閘極配線10各自及共同配線30各自係以具有在X方向(第2方向)延伸的線狀圖案之方式形成。亦即，源極配線31係與閘極配線10及共同配線30正交。共同配線30係以橫越複數個畫素開口部的方式延伸於X方向。所謂複數個畫素開口部係在透明基板22上所定義的區域。The display device DSP1 includes a plurality of source wirings 31, a plurality of gate wirings 10, and a plurality of common wirings 30 (conductive wirings and second conductive wirings) on the array substrate 200. The source wirings 31 are each formed to have a linear pattern extending in the Y direction (first direction). Each of the gate wirings 10 and the common wiring 30 is formed to have a linear pattern extending in the X direction (second direction). That is, the source wiring 31 is orthogonal to the gate wiring 10 and the common wiring 30. The common wiring 30 extends in the X direction so as to traverse the plurality of pixel openings. The plurality of pixel openings are defined in a region defined on the transparent substrate 22.
圖2中，複數個畫素開口部係以複數個源極配線31和複數個閘極配線10區劃成矩陣狀。此外，第1方向和第2方向係大致正交即可，第1方向和第2方向可調換。In FIG. 2, a plurality of pixel openings are divided into a matrix by a plurality of source wirings 31 and a plurality of gate wirings 10. Further, the first direction and the second direction may be substantially orthogonal, and the first direction and the second direction may be interchanged.
又，在第1方向「延伸線」係意味著各個的畫素形狀，例如可為彎曲成ㄑ字(dog leg pattern)的形狀，或亦可為平行四邊形狀，意味著畫素排列是排列於第1方向的矩陣。在第2方向「延伸線」的意思亦相同。以畫素排列的整體而言，第1方向與第2方向係正交。Further, the "extension line" in the first direction means that each pixel shape may be, for example, a shape that is curved into a dog leg pattern, or may be a parallelogram shape, meaning that the pixel arrangement is arranged in The matrix of the first direction. The meaning of "extension line" in the second direction is also the same. The first direction and the second direction are orthogonal to each other in the pixel arrangement.
再者，顯示裝置DSP1具備呈矩陣狀配置的複數個畫素電極20及以與畫素電極20對應的方式設置且連接於畫素電極20的複數個主動元件28(薄膜電晶體)。畫素電極20設於複數個畫素開口部每一者。具體言之，於複數個畫素電極20的每一者連接有主動元件28。在圖2所示的例子中，畫素電極20的右上端的位置設有主動元件28。Further, the display device DSP1 includes a plurality of pixel electrodes 20 arranged in a matrix, and a plurality of active elements 28 (thin film transistors) provided in correspondence with the pixel electrodes 20 and connected to the pixel electrodes 20. The pixel electrode 20 is provided in each of a plurality of pixel openings. Specifically, the active element 28 is connected to each of the plurality of pixel electrodes 20. In the example shown in FIG. 2, the active element 28 is provided at the position of the upper right end of the pixel electrode 20.
主動元件28係具備：連接於源極配線31的源極電極24(後述)；通道層27(後述)；汲極電極26(後述)；及隔著絕緣層13(後述)與通道層27對向配置的閘極電極25。主動元件28的閘極電極25係構成閘極配線10(導電配線、第2導電配線)的一部分，連接於閘極配線10。The active device 28 includes a source electrode 24 (described later) connected to the source wiring 31, a channel layer 27 (described later), a drain electrode 26 (described later), and a channel layer 27 via an insulating layer 13 (described later). The gate electrode 25 is arranged. The gate electrode 25 of the active device 28 constitutes a part of the gate wiring 10 (conductive wiring and second conductive wiring), and is connected to the gate wiring 10.
本實施形態中，顯示裝置DSP1具備複數個畫素，一個畫素電極20形成一個畫素。藉由主動元件28的切換驅動，對複數個畫素電極20的每一者賦予電壓(正負的電壓)，使液晶被驅動。以下說明中，有時將藉畫素電極20進行液晶驅動的區域稱為畫素、畫素開口部或畫素區域之情況。此畫素係在平面視圖中以源極配線31和閘極配線10所區劃的區域。In the present embodiment, the display device DSP1 includes a plurality of pixels, and one pixel electrode 20 forms a single pixel. By cutting the active component 28The drive is changed, and a voltage (positive and negative voltage) is applied to each of the plurality of pixel electrodes 20 to drive the liquid crystal. In the following description, a region in which the liquid crystal driving is performed by the pixel element 20 may be referred to as a pixel, a pixel opening, or a pixel region. This pixel is a region partitioned by the source wiring 31 and the gate wiring 10 in plan view.
再者，顯示裝置DSP1係在Z方向中與畫素電極20對向的位置具備共通電極17。特別是對一個畫素電極20設置具有2個條紋圖案的共通電極17。共通電極17係設於複數個畫素開口部的每一者。共通電極17係在Y方向延伸，和畫素電極20的長邊方向平行。Y方向的共通電極17的長度EL係大於Y方向的畫素電極20的長度。共通電極17係經由後述的通孔20S、接觸孔H和共同配線30電連接。接觸孔H如圖2所示，係位在共通電極17的導電圖案(電極部17A、條紋圖案)的長邊方向之中央。Further, the display device DSP1 includes the common electrode 17 at a position facing the pixel electrode 20 in the Z direction. In particular, a common electrode 17 having two stripe patterns is provided for one pixel electrode 20. The common electrode 17 is provided in each of a plurality of pixel openings. The common electrode 17 extends in the Y direction and is parallel to the longitudinal direction of the pixel electrode 20. The length EL of the common electrode 17 in the Y direction is larger than the length of the pixel electrode 20 in the Y direction. The common electrode 17 is electrically connected to the through hole 20S, the contact hole H, and the common wiring 30 which will be described later. As shown in FIG. 2, the contact hole H is centered on the longitudinal direction of the conductive pattern (electrode portion 17A, stripe pattern) of the common electrode 17.
在一畫素內之共通電極17的條數及接觸孔的數量，例如可藉由畫素寬度(畫素尺寸)來調整。The number of the common electrodes 17 and the number of contact holes in one pixel can be adjusted, for example, by the pixel width (pixel size).
在X方向，共通電極17的寬度W17A例如約3μm。相互鄰接的共通電極17之間的間距P17A(距離)例如約4μm。具體言之，不僅是一個畫素上，在相互鄰接的畫素間亦是，共通電極17在X方向以間距P17A相互疏離。In the X direction, the width W17A of the common electrode 17 is, for example, about 3 μm. The pitch P17 (distance) between the mutually adjacent common electrodes 17 is, for example, about 4 μm. Specifically, not only one pixel but also between mutually adjacent pixels, the common electrodes 17 are spaced apart from each other by the pitch P17A in the X direction.
在圖2所示的例子中，對一個畫素電極20設置具有2個條紋圖案的共通電極17，但本發明未限定此構成。因應畫素電極20的大小，共通電極17的條數亦可為1條以上、甚至3條以上。這時，共通電極17的寬度W17A及間距P17A係可因應畫素尺寸等或設計而適宜地變更。In the example shown in FIG. 2, the common electrode 17 having two stripe patterns is provided for one pixel electrode 20, but the present invention is not limited to this configuration.The number of the common electrodes 17 may be one or more or even three or more depending on the size of the pixel electrodes 20. In this case, the width W17A and the pitch P17A of the common electrode 17 can be appropriately changed depending on the size of the pixel or the like.
圖3A係將本發明第1實施形態的顯示裝置DSP1作一部分顯示的剖面圖，為沿著圖2所示的B-B’線之剖面圖。圖3B係將本發明第1實施形態的顯示裝置DSP1作一部分顯示的剖面圖，為將共通電極放大的放大剖面圖。Fig. 3A is a cross-sectional view showing a part of the display device DSP1 according to the first embodiment of the present invention, taken along the line B-B' shown in Fig. 2 . 3B is a cross-sectional view showing a portion of the display device DSP1 according to the first embodiment of the present invention, which is an enlarged cross-sectional view showing the common electrode.
圖4係將本發明第1實施形態的顯示裝置DSP1作一部分顯示的剖面圖，為沿著圖2所示的C-C’線的剖面圖。Fig. 4 is a cross-sectional view showing a part of the display device DSP1 according to the first embodiment of the present invention, taken along line C-C' shown in Fig. 2 .
圖3A係顯示接觸感測配線3與共通電極17之距離W1。換言之，此距離W1係在含有透明樹脂層16、濾光片51(RGB)、未圖示的配向膜及液晶層300的空間中之Z方向的距離。此空間未含有主動元件、源極配線及畫素電極。本實施形態中，將以距離W1所示的此空間稱為接觸感測空間。從主動元件或源極配線等之雜訊源所產生的雜訊，一般是呈3次元的放射狀放出。因此，雜訊的大小成為距離W1的3次方分之1(距離越大，雜訊的影響變小)。因此，如圖3A所示，接觸感測空間未含有主動元件或源極配線等之雜訊源，故而能使接觸感測精度提升。FIG. 3A shows the distance W1 between the contact sensing wiring 3 and the common electrode 17. In other words, this distance W1 is a distance in the Z direction in the space including the transparent resin layer 16, the filter 51 (RGB), the alignment film (not shown), and the liquid crystal layer 300. This space does not contain active components, source wiring, and pixel electrodes. In the present embodiment, this space indicated by the distance W1 is referred to as a contact sensing space. The noise generated from the noise source such as the active device or the source wiring is generally a radial discharge of 3 dimensions. Therefore, the size of the noise becomes one of the third power of the distance W1 (the larger the distance, the smaller the influence of the noise). Therefore, as shown in FIG. 3A, the contact sensing space does not contain a noise source such as an active device or a source wiring, so that the contact sensing accuracy can be improved.
圖3A係顯示接觸感測配線3與源極配線31之距離W2。如距離W2所示，接觸感測配線3與源極配線31係離得遠。再加上，如圖2所示，共通電極17與源極配線31在平面視圖中未重疊，故起因於源極配線31的寄生電容極小。再者，設於最接近接觸感測空間的位置之共通電極17係在畫素的長邊方向具有以畫素單位細切的形狀。因此，與設有以跨複數個畫素的方式呈直線形狀延伸的共通電極之情況相比，本實施形態的共通電極17係可將寄生電容變小。FIG. 3A shows the distance W2 between the contact sensing wiring 3 and the source wiring 31. As shown by the distance W2, the contact sensing wiring 3 and the source wiring 31 are far apart. Further, as shown in FIG. 2, the common electrode 17 and the source wiring 31 do not overlap in plan view, and the parasitic capacitance due to the source wiring 31 is extremely small. Further, the common electrode 17 provided at the position closest to the contact sensing space has a shape that is finely cut in units of pixels in the longitudinal direction of the pixel. Therefore, the common electrode 17 of the present embodiment can reduce the parasitic capacitance as compared with the case where the common electrode extending in a straight line shape across a plurality of pixels is provided.
依據圖3A所示的構造，可抑制起因於被供給至源極配線31的映像信號之雜訊帶給接觸感測配線3(第1導電配線)的影響，可減少在接觸感測配線3與源極配線31之間產生的寄生電容。According to the configuration shown in FIG. 3A, the influence of the noise band caused by the image signal supplied to the source wiring 31 on the contact sensing wiring 3 (first conductive wiring) can be suppressed, and the contact sensing wiring 3 can be reduced. The parasitic capacitance generated between the source wirings 31.
顯示裝置DSP1係具備：顯示裝置基板100(第1基板、對向基板)；以與顯示裝置基板100對向的方式貼合的陣列基板200(第2基板)；及被顯示裝置基板100及陣列基板200所夾持之液晶層300(功能裝置)。The display device DSP1 includes a display device substrate 100 (a first substrate and a counter substrate), an array substrate 200 (second substrate) that is bonded to the display device substrate 100, and a display device substrate 100 and an array. The liquid crystal layer 300 (functional device) sandwiched by the substrate 200.
在顯示裝置DSP1向內部供給光L的背光單元BU，係設於構成顯示裝置DSP1的陣列基板200之背面(供配置液晶層300的陣列基板200的透明基板的面之相反面)。此外，背光單元BU亦可設於顯示裝置DSP1的側面。這時，例如，使從背光單元BU射出的光在顯示裝置DSP1朝內部反射的反射板、導光板、或光擴散板等是設於陣列基板200的透明基板22的背面。背光單元BU的光源可使用LED。The backlight unit BU that supplies the light L to the inside of the display device DSP1 is disposed on the back surface of the array substrate 200 constituting the display device DSP1 (opposite to the surface of the transparent substrate on which the array substrate 200 of the liquid crystal layer 300 is disposed). Further, the backlight unit BU may be provided on the side of the display device DSP1. At this time, for example, a reflector, a light guide plate, a light diffusing plate, or the like that reflects the light emitted from the backlight unit BU toward the inside of the display device DSP1.It is provided on the back surface of the transparent substrate 22 of the array substrate 200. The light source of the backlight unit BU can use an LED.
顯示裝置基板100係具備：透明基板21(基板本體)；設於透明基板21上的接觸感測配線3；以覆蓋接觸感測配線3般地形成的濾光片51(RGB)；及以覆蓋濾光片51般地形成的透明樹脂層16(絕緣層)。The display device substrate 100 includes a transparent substrate 21 (substrate body), a contact sensing wiring 3 provided on the transparent substrate 21, a filter 51 (RGB) formed to cover the contact sensing wiring 3, and a cover The transparent resin layer 16 (insulating layer) formed in the form of the filter 51.
接觸感測配線3係作為接觸驅動電極(接觸驅動配線)發揮供能。顯示裝置DSP1中，藉由檢測在接觸感測配線3與共通電極17間之靜電電容的變化以進行接觸感測的檢測。The contact sensing wiring 3 serves as a contact driving electrode (contact driving wiring) to supply energy. In the display device DSP1, detection of contact sensing is performed by detecting a change in electrostatic capacitance between the contact sensing wiring 3 and the common electrode 17.
接觸感測配線3係具有黑色層8、及設於黑色層8的上方之金屬積層構造。平面視圖中，在與設於透明基板21上之黑色矩陣(黑色層)對應的位置設有接觸感測配線3。接觸感測配線3具有3層積層構造。又，第1導電性金屬氧化物層6的表面(液晶層側)亦可再積層黑色層或光吸收層。平面視圖中，亦可具有接觸感測配線3和黑色層8的線寬相等的部分。The contact sensing wiring 3 has a black layer 8 and a metal laminated structure provided above the black layer 8. In the plan view, the contact sensing wiring 3 is provided at a position corresponding to the black matrix (black layer) provided on the transparent substrate 21. The contact sensing wiring 3 has a three-layer laminated structure. Further, a black layer or a light absorbing layer may be further laminated on the surface (liquid crystal layer side) of the first conductive metal oxide layer 6. In the plan view, it is also possible to have portions in which the line widths of the contact sensing wiring 3 and the black layer 8 are equal.
如圖5所示，接觸感測配線3具有藉第1導電性金屬氧化物層6和第2導電性金屬氧化物層4夾持銅合金層5的構成。As shown in FIG. 5, the contact sensing wiring 3 has a configuration in which the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4.
此種配線構造不僅是接觸感測配線3，也適用於形成在陣列基板200上的各種配線。具體言之，在與本發明的導電配線或第2導電配線對應之閘極配線10、源極配線31、共同配線30等亦是，也能適用利用第1導電性金屬氧化物層6與第2導電性金屬氧化物層4夾持有銅合金層5的配線構造。Such a wiring structure is not only the contact sensing wiring 3 but also various wirings formed on the array substrate 200. Specifically, the gate wiring 10, the source wiring 31, the common wiring 30, and the like corresponding to the conductive wiring or the second conductive wiring of the present invention are also applicable to the first conductive metal oxide layer 6 and the first conductive layer. 2 The conductive metal oxide layer 4 has a wiring structure in which the copper alloy layer 5 is sandwiched.
以下，針對銅合金層5作具體說明。Hereinafter, the copper alloy layer 5 will be specifically described.
銅合金層5含有固溶於銅的第1元素及負電性小於銅及第1元素的第2元素。第1元素及前述第2元素為，添加於銅時的電阻係數上升率是1μΩcm/原子%以下的元素。銅合金層的電阻係數係在1.9μΩcm至6μΩcm的範圍內。第1元素係鋅，第2元素係鈣。The copper alloy layer 5 contains a first element which is dissolved in copper and a second element having a lower electronegativity than copper and a first element. The first element and the second element are elements having a resistivity increase rate of 1 μΩcm/atomic or less when added to copper. The resistivity of the copper alloy layer is in the range of 1.9 μΩcm to 6 μΩcm. The first element is zinc and the second element is calcium.
具體言之，關於銅合金層5的組成，銅合金層5係使用鈣2原子%、鋅0.5原子%及剩餘部份是銅的銅合金。銅合金層5的電阻係數係2.6μΩcm。Specifically, regarding the composition of the copper alloy layer 5, the copper alloy layer 5 is a copper alloy in which copper is 2 atom%, zinc is 0.5 atom%, and the remainder is copper. The resistivity of the copper alloy layer 5 was 2.6 μΩcm.
銅合金層5的電阻係數係可能因為銅合金層5之成膜方法或退火條件而有±30%左右之變化。例如，就銅合金層被直接形成於玻璃基板等之構成而言，因為成膜時之熱處理及進一步的成膜後之熱處理，使得銅合金層被氧化(形成CuO、氧化銅)，故電阻值會惡化。又，在構成銅合金層的合金元素是以低濃度添加的銅合金，亦即，稀釋合金中，會形成氧化銅且銅合金的晶粒變太大。因此，形成具有間隙的粗大粒界(結晶粒界)，有銅合金層的表面變粗，使電阻值惡化的情況。The resistivity of the copper alloy layer 5 may vary by about ±30% due to the film formation method or annealing condition of the copper alloy layer 5. For example, in the case where the copper alloy layer is directly formed on a glass substrate or the like, the copper alloy layer is oxidized (formation of CuO, copper oxide) due to heat treatment at the time of film formation and further heat treatment after film formation, so the resistance value Will deteriorate. Further, the alloy element constituting the copper alloy layer is a copper alloy added at a low concentration, that is, in the diluted alloy, copper oxide is formed and the crystal grains of the copper alloy become too large. Therefore, a coarse grain boundary (crystal grain boundary) having a gap is formed, and the surface of the copper alloy layer is thickened to deteriorate the resistance value.
本發明實施形態中，採用銅合金層5是被第1導電性金屬氧化物層6與第2導電性金屬氧化物層4所夾持的構成。就此構成而言，藉由熱處理(退火)改善電阻係數的情形很多。換言之，本發明實施形態中，藉由銅合金層5被導電性金屬氧化物所覆蓋，以抑制銅合金層5的表面氧化。又，藉由形成於銅合金層5的表面及背面的導電性金屬氧化物層所產生之限制(錨定)，銅合金層5的晶粒並無極端地粗大化，銅合金層5的表面沒變粗。即便是構成銅合金層5的合金元素以低的濃度(例如，0.2原子%左右)添加的銅合金層5，結晶粒(晶粒)仍不易變大，可抑制粒界所致載體散亂(電阻係數的惡化)。In the embodiment of the present invention, the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4. In this regard, there are many cases in which the resistivity is improved by heat treatment (annealing). In other words, in the embodiment of the present invention, the copper alloy layer 5 is covered with the conductive metal oxide to suppress surface oxidation of the copper alloy layer 5. Further, by the restriction (anchoring) of the conductive metal oxide layer formed on the front and back surfaces of the copper alloy layer 5, the crystal grains of the copper alloy layer 5 are not extremely coarsened, and the surface of the copper alloy layer 5 is formed. Not getting thicker. Even in the copper alloy layer 5 in which the alloying elements constituting the copper alloy layer 5 are added at a low concentration (for example, about 0.2 atom%), the crystal grains (grains) are not easily enlarged, and the carrier scattering due to the grain boundaries can be suppressed ( Deterioration of the resistivity).
關於抑制電阻係數的惡化之效果，特別是，添加於銅的合金元素的電阻係數上升率是1μΩcm/原子%的元素的情況，且銅合金層5是被第1導電性金屬氧化物層6和第2導電性金屬氧化物層4所夾持的構成之情況，容易獲得顯著的效果。本實施形態係與銅合金層被暴露於大氣環境、氮氣環境、氧氣環境及氫氣環境等之情況完全不同，藉由形成於銅合金層的表面及背面之導電性金屬氧化物層的限制(Anchoring；錨定)，銅合金層中緻密的晶粒的再結晶化進展，銅合金層容易低電阻化。The effect of suppressing the deterioration of the resistivity is particularly the case where the coefficient of increase of the resistivity of the alloy element added to copper is 1 μΩcm/atomic element, and the copper alloy layer 5 is the first conductive metal oxide layer 6 and When the structure of the second conductive metal oxide layer 4 is sandwiched, it is easy to obtain a remarkable effect. This embodiment is completely different from the case where the copper alloy layer is exposed to the atmosphere, the nitrogen atmosphere, the oxygen atmosphere, and the hydrogen atmosphere, and is limited by the conductive metal oxide layer formed on the surface and the back surface of the copper alloy layer (Anchoring) Anchoring) The recrystallization of dense crystal grains in the copper alloy layer progresses, and the copper alloy layer is easily reduced in resistance.
關於本發明實施形態涉及的接觸感測配線3，在銅合金層5和第1導電性金屬氧化物層6之界面，及銅合金層5和第2導電性金屬氧化物層4之界面，特別是在銅合金層5的側面9(濾光片51的著色層R和銅合金層5之界面、濾光片51的著色層G和銅合金層5之界面)形成有鈣氧化物。因為鈣氧化物形成於銅合金層5的表面，故抑制銅的擴散，有助於可靠性的提升。The contact sensing wiring 3 according to the embodiment of the present invention has an interface between the copper alloy layer 5 and the first conductive metal oxide layer 6 and copper bonding.The interface between the gold layer 5 and the second conductive metal oxide layer 4, particularly on the side surface 9 of the copper alloy layer 5 (the interface between the coloring layer R of the filter 51 and the copper alloy layer 5, and the coloring layer G of the filter 51) An interface with the copper alloy layer 5 is formed with calcium oxide. Since calcium oxide is formed on the surface of the copper alloy layer 5, the diffusion of copper is suppressed, contributing to an improvement in reliability.
又，關於本發明實施形態涉及的銅合金層，無需有意地使之含有氧(O)。含氧多的銅合金層，例如會因為水或鹼的存在而在銅合金層t產生孔隙，擔心會降低銅合金層的可靠性。Further, the copper alloy layer according to the embodiment of the present invention does not need to intentionally contain oxygen (O). The copper alloy layer containing a large amount of oxygen, for example, may cause voids in the copper alloy layer t due to the presence of water or alkali, and it is feared that the reliability of the copper alloy layer may be lowered.
於是，將第1導電性金屬氧化物層和銅合金層及第2導電性金屬氧化物層3層，例如，在從室溫(25℃)到小於200℃的基板溫度進行連續成膜。然後，於形成有通道層之圖案後的後工程，例如，施以200℃~350℃的低溫退火。藉此，可改善包含電阻係數在內的電氣特性。Then, the first conductive metal oxide layer, the copper alloy layer, and the second conductive metal oxide layer 3 are continuously formed into a film at a substrate temperature of from room temperature (25 ° C) to less than 200 ° C, for example. Then, after the formation of the pattern of the channel layer, for example, a low temperature annealing at 200 ° C to 350 ° C is applied. Thereby, electrical characteristics including the resistivity can be improved.
氧化物半導體，例如含有1種以上選自氧化銦、氧化鎵、氧化鋅所構成的群組。再者，氧化物半導體係含有氧化銻、氧化鉍中任一者。此種氧化物半導體係藉由與上述同樣的200℃~350℃之低溫退火促進結晶化，可使半導體特性穩定化。此種低溫處理係提升對以有機樹脂或有機顏料為基底的濾光片、或聚醯亞胺樹脂或醯胺樹脂等之樹脂基板之適合性。The oxide semiconductor contains, for example, one or more selected from the group consisting of indium oxide, gallium oxide, and zinc oxide. Further, the oxide semiconductor system contains any one of cerium oxide and cerium oxide. Such an oxide semiconductor is accelerated by low-temperature annealing at 200 ° C to 350 ° C in the same manner as described above, and the semiconductor characteristics can be stabilized. Such low-temperature treatment improves the suitability of a filter based on an organic resin or an organic pigment, or a resin substrate such as a polyimide resin or a guanamine resin.
在銅合金層5是被第1導電性金屬氧化物層6和第2導電性金屬氧化物層4所夾持的構成中，能獲得包含上述的效果之相乘效果。此外，為了更提升本發明實施形態涉及的導電配線的可靠性，除了用於電氣封裝的端子部、接觸孔以外者，以利用由氮氧化矽等之絕緣性無機膜、丙烯酸樹脂、聚醯亞胺樹脂等之有機樹脂所構成的保護層來覆蓋接觸感測配線3者較理想。亦可採用例如隔有丙烯酸樹脂、聚醯亞胺樹脂、醯胺樹脂等之絕緣層而積層2層的導電配線構造。在此種導電配線構造中，上配線及下配線的各個導電配線係例如可經由接觸孔電連接。In the configuration in which the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4, a multiplication effect including the above-described effects can be obtained. In addition, in order to improve the reliability of the conductive wiring according to the embodiment of the present invention, an insulating inorganic film made of yttrium oxynitride or the like, acrylic resin, or polyyttrium is used in addition to the terminal portion and the contact hole for electrical packaging. It is preferable that a protective layer made of an organic resin such as an amine resin covers the contact sensing wiring 3 . For example, a conductive wiring structure in which two layers are laminated with an insulating layer such as an acrylic resin, a polyimide resin, or a guanamine resin may be used. In such a conductive wiring structure, each of the conductive wirings of the upper wiring and the lower wiring can be electrically connected via, for example, a contact hole.
本發明實施形態涉及的銅合金層係Cu-Ca合金系的合金。Cu-Ca合金系中，鈣不易固溶於銅。例如，銅合金層的起始材料、即濺鍍靶材容易以Cu5Ca等之析出物分散於濺鍍靶材中。Cu-Ca-Zn合金中亦相同，鈣不易固溶於銅。A copper alloy layer-based Cu-Ca alloy-based alloy according to an embodiment of the present invention. In the Cu-Ca alloy system, calcium is not easily dissolved in copper. For example, the starting material of the copper alloy layer, that is, the sputtering target, is easily dispersed in the sputtering target with precipitates such as Cu5 Ca. The same is true in the Cu-Ca-Zn alloy, and calcium is not easily dissolved in copper.
Cu5Ca、熱處理時形成在銅合金的表面或導電性金屬氧化物與銅合金之界面的CaO，係抑制銅的擴散，有助於提升銅配線之可靠性。Cu5 Ca and CaO formed on the surface of the copper alloy or the interface between the conductive metal oxide and the copper alloy during heat treatment suppress the diffusion of copper and contribute to the improvement of the reliability of the copper wiring.
本發明實施形態中，添加於銅合金的添加元素、即鈣及鋅未被使用在使銅合金薄膜對透明基板或濾光片之密接性的提升上。In the embodiment of the present invention, calcium and zinc, which are added elements added to the copper alloy, are not used to improve the adhesion of the copper alloy film to the transparent substrate or the filter.
藉由將鋅添加於銅合金，鋅固溶於銅，使鋅置換銅在晶粒中之晶格位置以抑制銅的移動，主要可防止銅的遷移。By adding zinc to the copper alloy, zinc is solid-solubilized in copper, so that zinc replaces the lattice position of copper in the crystal grains to suppress the movement of copper, and mainly prevents migration of copper.
藉由將鈣添加於銅合金，主要可防止因CaO或Cu5Ca等之析出物形成所致銅的擴散。By adding calcium to the copper alloy, it is possible to mainly prevent the diffusion of copper due to the formation of precipitates such as CaO or Cu5 Ca.
本發明實施形態中，夾持銅合金層的導電性金屬氧化物層具有：提升對銅合金薄膜之密接性；改善電氣封裝中之歐姆接觸；提升耐擦傷性，防止銅遷移；提升銅合金層及導電性金屬氧化物層之積層構造的可靠性等之功能。In the embodiment of the present invention, the conductive metal oxide layer sandwiching the copper alloy layer has: improving adhesion to the copper alloy film; improving ohmic contact in the electrical package; improving scratch resistance and preventing copper migration; and improving the copper alloy layer And the function of the reliability of the laminated structure of the conductive metal oxide layer.
將本發明實施形態涉及之具有以導電性金屬氧化物層夾持銅合金層而成的3層構成之導電配線使用於薄膜電晶體或薄膜二極體等之半導體元件的導電配線，特別有效。具體言之，在經由接觸孔與半導體元件和導電配線之電連接中，大致可獲得實用的接觸。而且，藉由形成添加有鈣或鋅等之合金元素的銅合金，防止銅相對於氧化物半導體或矽半導體之擴散，能獲得高的可靠性。The conductive wiring having a three-layer structure in which a copper alloy layer is sandwiched between conductive metal oxide layers according to the embodiment of the present invention is particularly effective for use in a conductive wiring of a semiconductor element such as a thin film transistor or a thin film diode. In particular, in the electrical connection to the semiconductor element and the conductive wiring via the contact hole, practical contact is substantially obtained. Further, by forming a copper alloy to which an alloying element such as calcium or zinc is added, diffusion of copper with respect to an oxide semiconductor or a germanium semiconductor can be prevented, and high reliability can be obtained.
本發明實施形態中的詞語「元素」係以包含「金屬元素」及「半金屬」的廣義的意味來使用。金屬元素彼此的成為固體之固溶度係可從其等的原子半徑、價電子的總數e與總原子數a的比e/a(電子濃度)或化學的親和力等來推定。簡單來說，從元素彼此的2元狀態圖能判斷固溶的可能性。The word "element" in the embodiment of the present invention is used in a broad sense including "metal element" and "semimetal". The solid solubility of the metal elements as a solid can be estimated from the atomic radius thereof, the ratio e/a (electron concentration) of the total number e of valence electrons to the total number of atoms a, chemical affinity, and the like. In short, the possibility of solid solution can be judged from the 2-ary state diagram of the elements.
本發明實施形態涉及之所謂和銅固溶的元素，例如，可換言之係在針對車載電子機器的使用範圍、即一(負)40℃至+(正)80℃的溫度區域中，穩定地和銅取得取代型固溶的元素。又，元素(複數種亦可)朝銅的添加量只要是銅合金的電阻係數(與比電阻同義)不超過6μΩcm的範圍即可。在矩陣母材是銅的情況，相對於銅具有廣固溶域的金屬係可例示(Au)、鎳(Ni)、鋅(Zn)、鎵(Ga)、鈀(Pd)、錳(Mn)。鋁(Al)雖不廣，但相對於銅具有固溶域。The so-called copper solid solution element according to the embodiment of the present invention, for example, can be stably obtained with copper in a temperature range of one (negative) 40 ° C to + (positive) 80 ° C for a range of use of an in-vehicle electronic device. Substituted solid solution elements. Moreover, the amount of addition of the element (a plurality of types) to copper may be in a range of not more than 6 μΩcm in terms of the resistivity (synonymous with specific resistance) of the copper alloy. In the case where the matrix base material is copper, the metal system having a wide solid solution range with respect to copper can be exemplified by (Au), nickel (Ni), zinc (Zn), gallium (Ga), palladium (Pd), and manganese (Mn). . Although aluminum (Al) is not wide, it has a solid solution domain with respect to copper.
作為具有耐凸丘性的合金，例如已知添加有1原子%的Nd的鋁合金。此種鋁合金的比電阻係6.4μΩcm。本發明實施形態涉及之銅合金層係具有可代替以鋁合金構成的導電配線之程度的電氣特性(小的比電阻)。亦即，本發明實施形態涉及之銅合金層的電阻係數的上限係6μΩcm。但是，若為容許起因於含有銅合金層之導電配線的電阻之信號延遲或衰減，則能使用含有具有大於6μΩcm的電阻係數之銅合金的導電配線。As the alloy having the scrim resistance, for example, an aluminum alloy to which 1 atom% of Nd is added is known. The specific resistance of such an aluminum alloy is 6.4 μΩcm. The copper alloy layer according to the embodiment of the present invention has electrical characteristics (small specific resistance) which can be substituted for the conductive wiring made of an aluminum alloy. That is, the upper limit of the electrical resistivity of the copper alloy layer according to the embodiment of the present invention is 6 μΩcm. However, if the signal due to the resistance of the conductive wiring containing the copper alloy layer is delayed or attenuated, a conductive wiring containing a copper alloy having a resistivity of more than 6 μΩcm can be used.
具有與銀同等之高導電係數的添加於銅之元素係藉合金化而增加電阻係數。純銅之電阻係數係約1.7μΩcm。此外，在本發明實施形態說明的純銅係含有微量的不可避免雜質。An element added to copper having a high conductivity equal to that of silver is alloyed to increase the resistivity. The resistivity of pure copper is about 1.7 μΩcm. Further, the pure copper system described in the embodiment of the present invention contains a trace amount of unavoidable impurities.
電阻係數小的元素(銅的合金元素)，可例舉：鈀(Pd)、鎂(Mg)、鈹(Be)、金(Au)、鈣(Ca)、鎘(Cd)、鋅(Zn)、銀(Ag)。此等元素對純銅添加1原子%時增加的電阻係數是大致1μΩcm以下。鈣(Ca)、鎘(Cd)、鋅(Zn)、銀(Ag)的電阻係數之增加係0.3μΩcm/原子%以下，故以用作為合金元素者較佳。當考慮經濟性及環境負荷時，將鋅及鈣用作為合金元素者較佳。鋅及鈣分別可作為合金元素朝銅添加到4原子%。An element having a small resistivity (alloying element of copper) may, for example, be palladium (Pd), magnesium (Mg), beryllium (Be), gold (Au), calcium (Ca), cadmium (Cd) or zinc (Zn). ,Silver (Ag). When these elements add 1 atom% to pure copper, the resistivity increased is approximately 1 μΩcm or less. The increase in the electrical resistivity of calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag) is preferably 0.3 μΩcm/atomic or less, so that it is preferably used as an alloying element. When considering economic and environmental loads, it is preferred to use zinc and calcium as alloying elements. Zinc and calcium can be added as an alloying element to copper at 4 atom%, respectively.
亦可依據上述添加量的範圍，增加鈣的添加量、減少鋅的添加量、或增減鋅及鈣的添加量。關於起因於對銅添加鋅及鈣之效果，在各自0.2原子%以上的添加量下可獲得顯著的效果。It is also possible to increase the amount of calcium added, reduce the amount of zinc added, or increase or decrease the amount of zinc and calcium added depending on the range of the above added amount. Regarding the effect of adding zinc and calcium to copper, a remarkable effect can be obtained at an addition amount of 0.2 atom% or more.
對純銅添加合計0.4原子%的鋅及鈣後之銅合金的電阻係數係約1.9μΩcm。因此，本發明實施形態涉及之銅合金層的電阻係數的下限係1.9μΩcm。此外，在將鈣(Ca)、鎘(Cd)、鋅(Zn)、銀(Ag)用作合金元素的情況，當對銅的添加量超過5原子%時，銅合金的電阻係數會顯著增加，故以至少小於5原子%的添加量者較佳。The resistivity of the copper alloy in which 0.4 atom% of zinc and calcium were added to pure copper was about 1.9 μΩcm. Therefore, the lower limit of the resistivity of the copper alloy layer according to the embodiment of the present invention is 1.9 μΩcm. In addition, in the case where calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag) are used as the alloying elements, when the amount of copper added exceeds 5 atom%, the resistivity of the copper alloy is remarkably increased. Therefore, it is preferred to add at least less than 5 atom%.
鋅在100℃以下的溫度，對銅具有至少30原子%的固溶區域。鋅係和銅取代固溶，在銅的晶粒(結晶粒)之中抑制銅的移動，具有抑制銅的擴散之效果。Zinc has a solid solution zone of at least 30 atomic % for copper at temperatures below 100 °C. The zinc-based and copper-substituted solid solution suppresses the movement of copper among the crystal grains (crystal grains) of copper, and has an effect of suppressing the diffusion of copper.
負電性係為原子(元素)吸引電子附近的強度之相對尺度。此值越小的元素越容易成為陽離子。銅的負電性為1.9。氧的負電性為3.5。負電性小的元素可例舉鹼土類元素、鈦族元素、鉻族元素等。鹼元素的負電性亦小，但當在銅的近處存在有鹼元素或水分時，銅的擴散增長。因此，鈉或鉀等之鹼元素無法作為銅的合金元素使用。Negative electricity is the relative measure of the strength of an atom (element) that attracts electrons. The smaller the value, the easier the element becomes a cation. The electronegativity of copper is 1.9. The electronegativity is 3.5. An alkaline earth can be exemplified as an element having a small electronegativityClass elements, titanium elements, chromium elements, etc. The alkalinity of the alkali element is also small, but when there is an alkali element or moisture in the vicinity of copper, the diffusion of copper increases. Therefore, an alkali element such as sodium or potassium cannot be used as an alloying element of copper.
鈣的負電性係1.0的小值。在將鈣作為銅的合金元素使用的情況，鈣於熱處理時等中，比銅還先被氧化而成為氧化鈣，可抑制銅的擴散。就本發明實施形態涉及的導電配線而言，可使未被導電性金屬氧化物層覆蓋的銅合金層之露出面、銅合金層和導電性金屬氧化物層之界面選擇性地形成鈣氧化物。特別是，在未被導電性金屬氧化物層覆蓋的銅合金層之露出面形成鈣氧化物有助於抑制銅之擴散、及可靠性的提升。本發明實施形態的導電配線或銅合金層的導電係數係透過熱處理等退火來進行提升。上述的負電性係以鮑林(Pauling)之負電性的值表示。關於本發明實施形態涉及的導電配線，以藉由導電配線的熱處理工程等，使第2元素係比銅及第1元素還先被氧化而形成氧化物者較佳。又以防止氫、氧對銅或銅合金混入者較佳。The negative charge of calcium is a small value of 1.0. In the case where calcium is used as an alloying element of copper, calcium is oxidized earlier than copper to form calcium oxide during heat treatment, and the diffusion of copper can be suppressed. In the conductive wiring according to the embodiment of the present invention, the interface between the exposed surface of the copper alloy layer not covered by the conductive metal oxide layer and the interface between the copper alloy layer and the conductive metal oxide layer can selectively form calcium oxide. . In particular, the formation of calcium oxide on the exposed surface of the copper alloy layer not covered by the conductive metal oxide layer contributes to suppressing the diffusion of copper and improving the reliability. The conductivity of the conductive wiring or the copper alloy layer according to the embodiment of the present invention is improved by annealing by heat treatment or the like. The above negative electric properties are expressed by the value of Pauling's electronegativity. In the conductive wiring according to the embodiment of the present invention, it is preferable that the second element is oxidized to form an oxide before the copper element and the first element by heat treatment of the conductive wiring. Further, it is preferable to prevent hydrogen or oxygen from being mixed with copper or a copper alloy.
此外，本發明實施形態中，「第1元素」的負電性可小於銅的負電性。「第2元素」可在銅具有固溶域。在使用具有負電性小於銅且在銅中具有固溶域這2個性質之2種以上的元素之情況，可將2種以上的元素中之負電性小的元素設為「第2元素」。Further, in the embodiment of the present invention, the "first element" may have a lower electronegativity than that of copper. The "second element" can have a solid solution domain in copper. When two or more elements having two properties of less than copper and having a solid solution domain in copper are used, an element having a low electronegativity among two or more elements may be referred to as a "second element".
在銅的晶粒內藉由產生利用鋅取代銅及形成鈣氧化物，以提升本發明實施形態涉及的導電配線之可靠性。再加上，因為本發明實施形態涉及的導電配線係具有藉第1導電性金屬氧化物層和第2導電性金屬氧化物層夾持銅合金層所成的3層構成，所以可獲得藉導電性金屬氧化物抑制銅對顯示裝置的構成材料之擴散的效果，使導電配線的可靠性提升。再者，導電性金屬氧化物係形成導電配線的表面層。因此，藉電連接(封裝)能獲得歐姆接觸。The use of zinc in place of copper and formation of calcium oxide in the crystal grains of copper enhances the reliability of the conductive wiring according to the embodiment of the present invention. In addition, since the conductive wiring according to the embodiment of the present invention has a three-layer structure in which a copper alloy layer is sandwiched between the first conductive metal oxide layer and the second conductive metal oxide layer, conductivity can be obtained. The metal oxide suppresses the effect of copper on the diffusion of constituent materials of the display device, and improves the reliability of the conductive wiring. Further, the conductive metal oxide forms a surface layer of the conductive wiring. Therefore, an ohmic contact can be obtained by means of an electrical connection (package).
於本發明實施形態所述的構成中亦可適用銀合金，而非銅合金。但從材料價格面考量，以使用銅合金者較佳。A silver alloy, not a copper alloy, may be applied to the configuration described in the embodiment of the present invention. However, considering the material price, it is better to use copper alloy.
本發明實施形態中，銅合金層含有在銅具有固溶域且於銅的晶粒中可和銅取代之第1元素及負電性小於銅的第2元素。藉此，可防止使驅動裝置的電氣特性降低之銅的擴散或遷移。再者，本發明實施形態具有上述銅合金層被導電性金屬氧化物層所夾持的構成。藉此構成，可提供實用性高且具高可靠性之銅配線。In the embodiment of the present invention, the copper alloy layer contains a first element in which copper has a solid solution domain and is replaceable with copper in crystal grains of copper, and a second element having less electronegativity than copper. Thereby, it is possible to prevent the diffusion or migration of copper which lowers the electrical characteristics of the driving device. Furthermore, in the embodiment of the present invention, the copper alloy layer is sandwiched by the conductive metal oxide layer. According to this configuration, it is possible to provide a copper wiring having high practicability and high reliability.
第1導電性金屬氧化物層6及第2導電性金屬氧化物層4係夾持銅合金層5。The first conductive metal oxide layer 6 and the second conductive metal oxide layer 4 sandwich the copper alloy layer 5.
第1導電性金屬氧化物層6及第2導電性金屬氧化物層4係含有作為主要導電性金屬氧化物的氧化銦，並含有1種以上選自氧化銻、氧化鋅及氧化鎵所構成的群組之導電性金屬氧化物。The first conductive metal oxide layer 6 and the second conductive metal oxide layer 4 contain indium oxide as a main conductive metal oxide, and one or more types selected from the group consisting of cerium oxide, zinc oxide, and gallium oxide. Group of conductive metal oxides.
例如，關於第1導電性金屬氧化物層6及第2導電性金屬氧化物層4各個的組成，在未計數氧之元素的比例係銻4原子%、鎵4原子%、剩餘部份是銦。For example, regarding the composition of each of the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4, the ratio of the element which does not count oxygen is 原子4 atom%, gallium 4 atom%, and the remainder is indium. .
銻氧化物作為將銅或銅合金層夾持的導電性金屬氧化物層之金屬氧化物是重要的。銻與作為金屬元素的銅之固溶域小，抑制銅朝導電性金屬氧化物中擴散。第1導電性金屬氧化物層6及第2導電性金屬氧化物層4每一者，除了銦氧化物以外，以至少含有銻氧化物者較佳。It is important that the cerium oxide is a metal oxide of a conductive metal oxide layer sandwiching a copper or copper alloy layer. The solid solution domain of bismuth and copper as a metal element is small, and the diffusion of copper into the conductive metal oxide is suppressed. It is preferable that each of the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4 contains at least an antimony oxide in addition to indium oxide.
構成本發明實施形態涉及的導電配線之第1導電性金屬氧化物層、銅合金層及第2導電性金屬氧化物層，係可使用濺鍍等之真空成膜法簡便地成膜。The first conductive metal oxide layer, the copper alloy layer, and the second conductive metal oxide layer constituting the conductive wiring according to the embodiment of the present invention can be easily formed by a vacuum film formation method such as sputtering.
第1導電性金屬氧化物層、銅合金層、第2導電性金屬氧化物層係以維持真空環境而連續成膜者較佳。第1導電性金屬氧化物層與第2導電性金屬氧化物層的膜厚相異亦可。例如，亦可將形成於接近顯示裝置基板100(第1基板)的透明基板21之位置的第2導電性金屬氧化物層4的膜厚設為25nm，將形成於偏離透明基板21的位置之第1導電性金屬氧化物層6的膜厚設為45nm。銅合金層的膜厚的膜厚範圍可設為200nm至400nm。但是，本發明未規定構成上述的導電配線之層的各個膜厚。The first conductive metal oxide layer, the copper alloy layer, and the second conductive metal oxide layer are preferably formed by continuously forming a film while maintaining a vacuum atmosphere. The thickness of the first conductive metal oxide layer and the second conductive metal oxide layer may be different. For example, the thickness of the second conductive metal oxide layer 4 formed on the transparent substrate 21 close to the display device substrate 100 (first substrate) may be 25 nm, and may be formed at a position deviated from the transparent substrate 21. The film thickness of the first conductive metal oxide layer 6 was set to 45 nm. The film thickness of the copper alloy layer may range from 200 nm to 400 nm. However, the present invention does not specify the respective film thicknesses of the layers constituting the above-described conductive wiring.
作為本發明實施形態涉及的導電性金屬氧化物層之形成方法，可例舉上述的濺鍍成膜法，能將導電性金屬氧化物層簡便地成膜。這時，使用濺鍍靶材作為成膜材料。此外，此濺鍍靶材為提升高密度化、靶材母材的結晶之緻密化、靶材之導電性，可少量添加氧化鈦(TiO2)、氧化鋯(ZrO2)、氧化錫(SnO2)等。As a method of forming the conductive metal oxide layer according to the embodiment of the present invention, the above-described sputtering film formation method can be used, and the conductive metal oxide layer can be easily formed into a film. At this time, a sputtering target is used as a film forming material. In addition, the sputtering target is used to increase the density, the densification of the target base material, and the conductivity of the target. A small amount of titanium oxide (TiO2 ), zirconium oxide (ZrO2 ), or tin oxide (SnO) may be added.2 ) Wait.
此外，關於將本發明實施形態涉及的導電配線圖案化之方法，具有將第1導電性金屬氧化物層/銅合金層/第2導電性金屬氧化物層3層，以周知的光刻法的手法使用1液的蝕刻液匯總地形成任意配線狀的圖案之益處。亦可於導電配線形成用於電氣封裝之端子部或迂迴部、接觸孔等。亦可視需要形成電性浮動的浮動圖案。複數個第1導電配線及複數個第2導電配線係可於接觸感測時分別使之疏化地驅動、檢測。藉由疏化驅動條數，可縮短接觸響應時間，或可減低有關接觸驅動之消耗電力。In addition, the method of patterning the conductive wiring according to the embodiment of the present invention includes three layers of the first conductive metal oxide layer/copper alloy layer/second conductive metal oxide layer by a well-known photolithography method. The technique uses a single liquid etching solution to collectively form the benefit of any wiring pattern. A terminal portion or a turn-around portion, a contact hole, or the like for electrical packaging may be formed on the conductive wiring. An electrically floating floating pattern can also be formed as needed. The plurality of first conductive wirings and the plurality of second conductive wirings can be driven and detected in a sparse manner during contact sensing. By thinning the number of driving strips, the contact response time can be shortened, or the power consumption related to the contact driving can be reduced.
黑色層8係作為顯示裝置DSP1的黑色矩陣發揮功能。黑色層係例如以使黑色的色材分散的著色樹脂所構成。銅的氧化物或銅合金的氧化物雖無法獲得充分的黑色或低的反射率，本實施形態涉及的在黑色層與玻璃等之基板之間的界面中之可見光的反射率係大致被抑制成3%以下，可獲得高的視認性。The black layer 8 functions as a black matrix of the display device DSP1. The black layer is composed of, for example, a colored resin in which a black color material is dispersed. The oxide of copper or the oxide of the copper alloy cannot obtain sufficient black or low reflectance, and the reflectance of visible light at the interface between the black layer and the substrate such as glass is substantially suppressed to Below 3%, high visibility can be obtained.
作為黑色的色材，可適用碳、碳奈米管或複數個有機顏料之混合物。例如，對色材整體的量以51質量%以上的比例，亦即，使用碳作為主要的色材。為了調整反射色，可將藍或紅等之有機顏料添加於黑色的色材作使用。例如，藉由調整起始材料、即感光性黑色塗布液所含碳的濃度(降低碳濃度)，可使黑色層的再現性提升。As the black color material, a mixture of carbon, carbon nanotubes or a plurality of organic pigments can be applied. For example, the amount of the entire color material is 51% by mass or more, that is, carbon is used as the main color material. In order to adjust the reflection color, an organic pigment such as blue or red may be added to the black color material for use. For example, by adjusting the concentration of the carbon contained in the starting material, that is, the photosensitive black coating liquid (reducing the carbon concentration), the reproducibility of the black layer can be improved.
即便是使用液晶顯示裝置的製造裝置、即大型曝光裝置之情況，例如，亦可形成具有1~6μm寬度(細線)的圖案之黑色層(圖案化)。此外，本實施形態中之碳濃度的範圍係相對於含有樹脂或硬化劑和顏料之整體的固形分，設定在4以上且50以下之質量%的範圍內。此處，碳量方面，碳濃度雖可超過50質量%，但當碳濃度相對於整體的固形分超過50質量%時會有塗膜適性降低的傾向。又，在將碳濃度設定小於4質量%的情況，無法獲得充分的黑色，而有在位於黑色層下之基底的金屬層產生的反射光被清楚辨視而降低視認性的情況。Even in the case of using a manufacturing apparatus of a liquid crystal display device, that is, a large-sized exposure apparatus, for example, a black layer (patterning) having a pattern having a width (thin line) of 1 to 6 μm can be formed. In addition, the range of the carbon concentration in the present embodiment is set to be in the range of 4 or more and 50% by mass or less based on the solid content of the resin, the curing agent, and the pigment. Here, the carbon content may exceed 50% by mass, but when the carbon concentration exceeds 50% by mass based on the total solid content, the coating film tends to be lowered. Moreover, when the carbon concentration is set to less than 4% by mass, sufficient black cannot be obtained, and the reflected light generated by the metal layer on the base under the black layer is clearly observed to reduce the visibility.
於後工程的光刻法中進行曝光處理的情況，進行曝光對象的基板與遮罩之對位(對準)。此時，優先對準，例如，可將利用透過測定的黑色層之光學濃度設為2以下。除了碳以外，亦可使用作為黑色的色調整之複數個有機顏料的混合物來形成黑色層。以考量玻璃或透明樹脂等之基材的折射率(約1.5)，使在黑色層與其等基材之間的界面中之反射率成為3%以下的方式設定黑色層的反射率。在此情況，以調整黑色色材的含量、種類、用於色材的樹脂，膜厚為宜。藉由將此等條件最佳化，可將在折射率是大約1.5的玻璃等之基材與黑色層之間的界面中之反射率，在可見光的波長區域內設為3%以下，可實現低反射率。考慮防止起因於從背光單元BU射出的光之反射光再度反射之必要性、觀察者視認性的提升，黑色層的反射率宜設成3%以下。此外，通常，濾光片所用的丙烯酸樹脂且液晶材料的折射率大約是1.5以上且1.7以下的範圍。In the case where exposure processing is performed in the photolithography method of the subsequent process, alignment (alignment) of the substrate to be exposed and the mask is performed. At this time, the alignment is preferentially performed. For example, the optical density of the black layer by the transmission measurement can be set to 2 or less. In addition to carbon, a black layer may be formed using a mixture of a plurality of organic pigments adjusted in black color. Considering the refractive index (about 1.5) of a substrate such as glass or transparent resin, in the black layer and its likeThe reflectance of the black layer is set such that the reflectance in the interface between the two is 3% or less. In this case, it is preferable to adjust the content and type of the black color material, and the resin used for the color material. By optimizing these conditions, the reflectance at the interface between the substrate such as glass having a refractive index of about 1.5 and the black layer can be set to 3% or less in the wavelength region of visible light, thereby realizing Low reflectivity. It is considered that the necessity of preventing reflection of light reflected from the backlight unit BU to be reflected again and the visibility of the observer are improved, and the reflectance of the black layer is preferably set to 3% or less. Further, in general, the acrylic resin used for the filter and the refractive index of the liquid crystal material are approximately in the range of 1.5 or more and 1.7 or less.
又，透過在接觸感測配線3上形成具有光吸收性的金屬氧化物，可抑制用於接觸感測配線3的銅合金層5所致光反射。Moreover, by forming a light-absorbing metal oxide on the contact sensing wiring 3, light reflection by the copper alloy layer 5 for contacting the sensing wiring 3 can be suppressed.
圖3A所示的顯示裝置基板100中，雖使用設有濾光片51的構造，但亦可使用省略了濾光片51的構造，例如，亦可使用備有設於透明基板21上的接觸感測配線3及以覆蓋接觸感測配線3的方式形成的透明樹脂層16之構造。In the display device substrate 100 shown in FIG. 3A, a structure in which the filter 51 is provided is used, but a structure in which the filter 51 is omitted may be used. For example, a contact provided on the transparent substrate 21 may be used. The configuration of the sensing wiring 3 and the transparent resin layer 16 formed to cover the contact sensing wiring 3 is formed.
使用未含有濾光片51的顯示裝置基板之液晶顯示裝置中，將紅色發光、綠色發光及藍色發光各個LED設於背光單元，以場序(field sequential)的手法進行彩色顯示。設於圖3A所示的透明基板21上的接觸感測配線3之層構成，可設成和後述之形成於陣列基板200的共同配線30(導電配線)之層構成、閘極電極25(閘極配線10)之層構成相同。In a liquid crystal display device using a display device substrate that does not include the filter 51, LEDs of red light emission, green light emission, and blue light emission are provided in a backlight unit, and color display is performed in a field sequential manner. The layer structure of the contact sensing wiring 3 provided on the transparent substrate 21 shown in FIG. 3A can be formed as a layer of a common wiring 30 (conductive wiring) formed on the array substrate 200 to be described later, and a gate electrode 25 (gate) The layers of the pole wiring 10) have the same structure.
如圖3A及圖3B所示，陣列基板200具備：透明基板22(第2透明基板)；以覆蓋透明基板22表面的方式形成的第4絕緣層14；形成於第4絕緣層14上的源極配線31；以覆蓋源極配線31的方式形成於第4絕緣層14上的第3絕緣層13；形成於第3絕緣層13上的閘極配線10；形成於第3絕緣層13上的共同配線30；以覆蓋閘極配線10及共同配線30的方式形成於第3絕緣層13上的第2絕緣層12；形成於第2絕緣層12上的畫素電極20；以覆蓋畫素電極20的方式形成於第2絕緣層12上的第1絕緣層11；及共通電極17。As shown in FIGS. 3A and 3B, the array substrate 200 includes a transparent substrate 22 (second transparent substrate), a fourth insulating layer 14 formed to cover the surface of the transparent substrate 22, and a source formed on the fourth insulating layer 14. a pole wiring 31; a third insulating layer 13 formed on the fourth insulating layer 14 so as to cover the source wiring 31; a gate wiring 10 formed on the third insulating layer 13; and a third insulating layer 13 formed on the third insulating layer 13. The common wiring 30; the second insulating layer 12 formed on the third insulating layer 13 so as to cover the gate wiring 10 and the common wiring 30; the pixel electrode 20 formed on the second insulating layer 12; to cover the pixel electrode The first insulating layer 11 formed on the second insulating layer 12 and the common electrode 17 are formed in a manner of 20.
作為形成第1絕緣層11、第2絕緣層12、第3絕緣層13及第4絕緣層14的材料，採用氧化矽、氮氧化矽、氧化鋁、氮氧化鋁、氧化鈰、氧化鉿或含有此種材料的混合材料。或，此等絕緣層的一部分亦可使用聚醯亞胺樹脂、丙烯酸樹脂，苯環丁烯樹脂或低介電常數材料(low-k材料)。又，作為此種絕緣層11、12、13、14的構成，亦可採用由單一層所構成的層構成，亦可採用積層有複數個層的多層構成。此種絕緣層11、12、13、14係可使用電漿CVD或濺鍍等之成膜裝置來形成。As the material for forming the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14, yttrium oxide, lanthanum oxynitride, aluminum oxide, aluminum oxynitride, cerium oxide, cerium oxide or the like is used. a mixed material of this material. Alternatively, a part of the insulating layers may be a polyimide resin, an acrylic resin, a benzocyclobutene resin or a low dielectric constant material (low-k material). Further, the configuration of the insulating layers 11, 12, 13, and 14 may be a layer composed of a single layer, or a multilayer structure in which a plurality of layers are laminated. Such insulating layers 11, 12, 13, and 14 can be formed using a film forming apparatus such as plasma CVD or sputtering.
源極配線31配設在第3絕緣層13與第4絕緣層14之間。作為源極配線31的構造，可採用多層的導電層。第1實施形態中，作為源極電極24與汲極電極26之構造，採用鈦/鋁合金/鈦、或鉬/鋁合金/鉬等之3層構成。此處，鋁合金係鋁-釹的合金。此外，源極電極24和汲極電極26及源極配線31亦可採用將銅合金層以導電性金屬氧化物層夾持的導電配線。The source wiring 31 is disposed between the third insulating layer 13 and the fourth insulating layer 14. As the configuration of the source wiring 31, a plurality of conductive layers may be employed.In the first embodiment, the structure of the source electrode 24 and the drain electrode 26 is made of three layers of titanium/aluminum alloy/titanium or molybdenum/aluminum alloy/molybdenum. Here, the aluminum alloy is an alloy of aluminum-niobium. Further, as the source electrode 24, the drain electrode 26, and the source wiring 31, a conductive wiring in which a copper alloy layer is sandwiched by a conductive metal oxide layer may be used.
作為共同配線30的形成材料，採用與上述的銅合金層5相同材料。又，同樣地，作為共同配線30的構造，採用與上述的銅合金層5相同構造。As the material for forming the common wiring 30, the same material as the above-described copper alloy layer 5 is used. Further, similarly, the structure of the common wiring 30 is the same as that of the above-described copper alloy layer 5.
畫素電極20設於複數個畫素開口部各自上，連接於係TFT的主動元件(後述)。陣列基板200中，由於主動元件被配置成矩陣狀，所以畫素電極20亦同樣地，在陣列基板200上呈矩陣狀配置。畫素電極20係以ITO(Indium Tin Oxide；氧化銦)等之透明導電膜形成。The pixel electrode 20 is provided on each of the plurality of pixel openings, and is connected to an active element (described later) of the TFT. In the array substrate 200, since the active elements are arranged in a matrix, the pixel electrodes 20 are similarly arranged in a matrix on the array substrate 200. The pixel electrode 20 is formed of a transparent conductive film such as ITO (Indium Tin Oxide).
構成主動元件的通道層或半導體層係能以多晶矽半導體來形成，亦能以氧化物半導體來形成。構成主動元件的通道層或半導體層的層構成係亦可為積層有多晶矽半導體與氧化物半導體的積層構成。亦可為在陣列基板上的同一面上形成由2種半導體形成的元件，例如形成備有是多晶矽半導體的通道層之主動元件及備有是氧化物半導體的通道層之主動元件的構成。再者，亦可採用在多晶矽半導體的TFT陣列上隔著絕緣層而積層2層以氧化物半導體形成的TFT陣列之構成。在顯示功能層是有機EL(Organic Electroluminescence)層的情況，以氧化物半導體形成的TFT係具有向以多晶矽半導體形成的TFT供給信號(選擇TFT元件)的功能，以多晶矽半導體形成的TFT係具有驅動顯示功能層之功能。藉此構成，可實現採用有機EL層作為顯示功能層的顯示裝置。備有載體遷移率高的多晶矽半導體且具有多晶矽半導體作為通道層之TFT，係適合於進行朝有機EL元件進行電流注入(有機EL元件的驅動)。The channel layer or the semiconductor layer constituting the active device can be formed of a polycrystalline germanium semiconductor or an oxide semiconductor. The layer structure of the channel layer or the semiconductor layer constituting the active device may be a laminated structure in which a polycrystalline germanium semiconductor and an oxide semiconductor are laminated. It is also possible to form an element formed of two kinds of semiconductors on the same surface on the array substrate, for example, an active element provided with a channel layer which is a polysilicon semiconductor and an active element provided with a channel layer which is an oxide semiconductor. Further, a TFT array formed of an oxide semiconductor may be laminated on the TFT array of the polycrystalline silicon semiconductor via an insulating layer. In the case where the display functional layer is an organic EL (Organic Electroluminescence) layer, to oxidizeThe TFT formed of the material semiconductor has a function of supplying a signal (selecting a TFT element) to a TFT formed of a polycrystalline germanium semiconductor, and a TFT formed of a polycrystalline germanium semiconductor has a function of driving a display function layer. With this configuration, a display device using the organic EL layer as a display function layer can be realized. A TFT having a polycrystalline germanium semiconductor having a high carrier mobility and a polycrystalline germanium semiconductor as a channel layer is suitable for current injection into an organic EL element (driving of an organic EL element).
參照圖3B來說明共通電極17的構造及位在共通電極17周邊之陣列基板200的構成構件。特別針對以共同配線30、共通電極17、畫素電極20、第1絕緣層11及第2絕緣層12所構成的積層構造作具體說明。圖3B係顯示構成陣列基板200的畫素之要部，顯示在一個畫素中的一個共通電極17的構造。圖3B所示的共通電極17之構造係亦適用於陣列基板200中所有的畫素。The structure of the common electrode 17 and the constituent members of the array substrate 200 positioned around the common electrode 17 will be described with reference to FIG. 3B. In particular, the laminated structure including the common wiring 30, the common electrode 17, the pixel electrode 20, the first insulating layer 11, and the second insulating layer 12 will be specifically described. Fig. 3B shows the configuration of a common electrode 17 in one pixel, which is the main part of the pixel constituting the array substrate 200. The configuration of the common electrode 17 shown in FIG. 3B is also applicable to all the pixels in the array substrate 200.
第2絕緣層12係設於第1絕緣層11之下，形成於共同配線30上，具有形成後述的接觸孔H的一部分之貫通孔12H。第1絕緣層11係設於共通電極17的上部(電極部17A)之下，形成於畫素電極20上，具有後述之形成接觸孔H的一部分之貫通孔11H。貫通孔12H的位置(中心位置)與貫通孔11H的位置(中心位置)一致。貫通孔11H的直徑(X方向的寬度)係在從第1絕緣層11的上面11T朝向共同配線30的方向(Z方向)緩慢變小。同樣地，貫通孔12H的直徑(X方向的寬度)係在從第2絕緣層12的上面12T朝向共同配線30的方向(Z方向)緩慢變小。貫通孔11H及貫通孔12H具有連續的內壁，形成接觸孔H。接觸孔H具有錐形。The second insulating layer 12 is formed under the first insulating layer 11 and formed on the common wiring 30, and has a through hole 12H that forms a part of the contact hole H to be described later. The first insulating layer 11 is formed under the upper portion (electrode portion 17A) of the common electrode 17, and is formed on the pixel electrode 20, and has a through hole 11H which forms a part of the contact hole H to be described later. The position (center position) of the through hole 12H coincides with the position (center position) of the through hole 11H. The diameter (width in the X direction) of the through hole 11H gradually decreases in the direction (Z direction) from the upper surface 11T of the first insulating layer 11 toward the common wiring 30. Similarly,The diameter (width in the X direction) of the through hole 12H gradually decreases in the direction (Z direction) from the upper surface 12T of the second insulating layer 12 toward the common wiring 30. The through hole 11H and the through hole 12H have continuous inner walls and form a contact hole H. The contact hole H has a taper shape.
畫素電極20係形成在第1絕緣層11之下，具有通孔20S。通孔20S係不存在透明導電膜之開口部。通孔20S設於與接觸孔H對應的位置。The pixel electrode 20 is formed under the first insulating layer 11 and has a through hole 20S. The through hole 20S is not provided with an opening portion of the transparent conductive film. The through hole 20S is provided at a position corresponding to the contact hole H.
圖2所示的例子中，在各畫素設有2個接觸孔H，亦即，左側接觸孔LH(H，第1接觸孔)及右側接觸孔RH(H，第2接觸孔)，在與2個接觸孔H各自對應的位置設有通孔20S。In the example shown in FIG. 2, two contact holes H, that is, the left contact hole LH (H, the first contact hole) and the right contact hole RH (H, the second contact hole) are provided in each pixel. A through hole 20S is provided at a position corresponding to each of the two contact holes H.
以下的說明中，有時將左側接觸孔LH及右側接觸孔RH僅成為接觸孔H。In the following description, the left contact hole LH and the right contact hole RH may be only the contact hole H.
通孔20S相當於設在畫素電極20的內壁20K之內側區域。通孔20S的直徑D20S大於接觸孔H的直徑。貫通孔11H(接觸孔H的一部分)設於通孔20S的內部。通孔20S的內部充填有第1絕緣層11，以將埋住通孔20S的內壁之第1絕緣層11的充填部11F貫通的方式形成貫通孔11H。進一步在通孔20S的下方位置亦是，以與貫通孔11H連續的方式形成貫通孔12H(接觸孔H的一部分)。此外，形成於畫素電極20的通孔20S的數量係與接觸孔H的數量相同，形成在平面視圖中相同位置。通孔20S的直徑D20S，例如為3μm至6μm。通孔20S的直徑亦可設成大於共通電極17的寬度W17A。The through hole 20S corresponds to an inner region of the inner wall 20K of the pixel electrode 20. The diameter D20S of the through hole 20S is larger than the diameter of the contact hole H. The through hole 11H (a part of the contact hole H) is provided inside the through hole 20S. The inside of the through hole 20S is filled with the first insulating layer 11, and the through hole 11H is formed so as to penetrate the filling portion 11F of the first insulating layer 11 which is buried in the inner wall of the through hole 20S. Further, a through hole 12H (a part of the contact hole H) is formed in a position below the through hole 20S so as to be continuous with the through hole 11H. Further, the number of the through holes 20S formed in the pixel electrode 20 is the same as the number of the contact holes H, and is formed at the same position in plan view. The diameter D20S of the through hole 20S is, for example, 3 μm to 6 μm. The diameter of the through hole 20S may also be set larger than the width W17A of the common electrode 17.
共通電極17具備電極部17A(導電部)、導電連接部17B。The common electrode 17 includes an electrode portion 17A (conductive portion) and a conductive connecting portion 17B.
電極部17A形成在第1絕緣層11的上面11T，從Z方向觀之，配置成與畫素電極20的通孔20S重疊。電極部17A設於最接近於液晶層300的陣列基板200的面。具體言之，在液晶層300與陣列基板200之間形成有配向膜，在此配向膜之下設有第1絕緣層11。The electrode portion 17A is formed on the upper surface 11T of the first insulating layer 11, and is disposed to overlap the through hole 20S of the pixel electrode 20 as viewed in the Z direction. The electrode portion 17A is provided on the surface of the array substrate 200 closest to the liquid crystal layer 300. Specifically, an alignment film is formed between the liquid crystal layer 300 and the array substrate 200, and the first insulating layer 11 is provided under the alignment film.
電極部17A的寬度W17A，例如約為3μm，比導電連接部17B的上端(電極部17A與導電連接部17B之連接部)還大，亦可形成比通孔20S的直徑D20S(例如，2μm)大。或者，亦可通孔20S的直徑D20S比電極部17A的寬度W17A還大。通孔20S的直徑D20S，例如亦可設為4μm。在從電極部17A的中心(與Z方向平行的電極部17A的中心線)朝向電極部17A的外側的方向(X方向)，電極部17A的壁部17K係從畫素電極20的內壁20K的位置突出。The width W17A of the electrode portion 17A is, for example, about 3 μm, which is larger than the upper end of the conductive connecting portion 17B (the connecting portion between the electrode portion 17A and the conductive connecting portion 17B), and may be formed to have a diameter D20S (for example, 2 μm) than the through hole 20S. Big. Alternatively, the diameter D20S of the through hole 20S may be larger than the width W17A of the electrode portion 17A. The diameter D20S of the through hole 20S may be, for example, 4 μm. The wall portion 17K of the electrode portion 17A is from the inner wall 20K of the pixel electrode 20 in the direction (X direction) from the center of the electrode portion 17A (the center line of the electrode portion 17A parallel to the Z direction) toward the outside of the electrode portion 17A (X direction). The position is outstanding.
導電連接部17B設於接觸孔H(貫通孔11H、12H)的內部，通過接觸孔H電連接於共同配線30。The conductive connecting portion 17B is provided inside the contact hole H (through holes 11H, 12H), and is electrically connected to the common wiring 30 through the contact hole H.
藉由在第1絕緣層11及第2絕緣層12形成上述的接觸孔之狀態下於第1絕緣層11上施行成膜工程及圖案化工程，電極部17A及導電連接部17B係一體形成。共通電極17係與畫素電極20同樣，以ITO等之透明導電膜形成。The electrode portion 17A and the conductive connecting portion 17B are integrally formed by performing a film forming process and a patterning process on the first insulating layer 11 in a state where the above-described contact holes are formed in the first insulating layer 11 and the second insulating layer 12. Similarly to the pixel electrode 20, the common electrode 17 is formed of a transparent conductive film such as ITO.
於上述的積層構造中，在電極部17A與畫素電極20之間配置有第1絕緣層11，且共同配線30與畫素電極20之間配置第2絕緣層12之狀態下，共通電極17及共同配線30相互導通，共同配線30的電位與共通電極17的電位成為相同。In the laminated structure described above, the first insulating layer 11 is disposed between the electrode portion 17A and the pixel electrode 20, and the common insulating layer 12 is disposed between the common wiring 30 and the pixel electrode 20, and the common electrode 17 is provided. The common wiring 30 is electrically connected to each other, and the potential of the common wiring 30 is the same as the potential of the common electrode 17.
共同配線30(或共通電極17)的電位係可在交互進行液晶驅動和接觸感測驅動(靜電電容的變化之檢測)之際、亦即分時作改變。且向共同配線30(或共通電極17)賦予之信號的頻率係可在交互進行液晶驅動和接觸感測驅動(靜電電容的變化之檢測)之際、亦即分時作改變。又，在液晶驅動時且圖框反轉驅動時，將共同配線30(或共通電極17)的電位之極性，按每圖框調換正極性與負極性，例如，能以±2.5V的液晶驅動電壓驅動液晶。The potential of the common wiring 30 (or the common electrode 17) can be changed when the liquid crystal driving and the contact sensing driving (detection of the change in electrostatic capacitance) are alternately performed, that is, time division. The frequency of the signal given to the common wiring 30 (or the common electrode 17) can be changed when the liquid crystal driving and the contact sensing driving (detection of the change in electrostatic capacitance) are alternately performed, that is, time-divisionally changed. Further, when the liquid crystal is driven and the frame is driven in the reverse direction, the polarity of the potential of the common wiring 30 (or the common electrode 17) is changed to the positive polarity and the negative polarity for each frame, and for example, it can be driven by a liquid crystal of ±2.5 V. The voltage drives the liquid crystal.
在液晶驅動設為行反轉(Column Inversion)驅動或點反轉驅動之情況，共通電極17的電位亦可設為固定(定電位)。在此情況的「定電位」係指例如經由高電阻接地於液晶顯示裝置之框體等的共通電極17的電位，並非意味用於前述圖框反轉驅動的±2.5V等之定電位。係在液晶的閾值Vth以下的電壓以下的範圍且被固定在大致0V(零伏)的定電位。換言之，若為Vth的範圍內，則「定電位」亦可為從液晶驅動電壓的中間值偏移的定電位。此外，上述的「高電阻」係可自500mega歐姆至50tera歐姆的範圍內作選擇的電阻值。作為此種電阻值，例如可採用代表性的500giga歐姆至5tera歐姆。在液晶驅動方式是採用行反轉驅動或點反轉驅動之情況，共同配線30係例如經由1tera歐姆的高電阻而接地，可設成大致0V(零伏)的定電位。這時，連接於共同配線30的共通電極17亦大致成為0V(零伏)的定電位，可進行被蓄積的靜電電容之重置。在將共通電極17的電位設為定電位的情況，接觸感測時接觸驅動電壓被施加於接觸感測配線。將共通電極17的電位設為「定電位」的情況，液晶驅動和接觸驅動亦可不分時驅動。When the liquid crystal drive is driven by a column inversion drive or a dot inversion drive, the potential of the common electrode 17 may be fixed (fixed potential). The "fixed potential" in this case is, for example, the potential of the common electrode 17 that is grounded to the casing of the liquid crystal display device via a high resistance, and does not mean a constant potential of ±2.5 V or the like used for the reverse rotation of the frame. It is fixed to a constant potential of approximately 0 V (zero volts) in a range of a voltage equal to or lower than a threshold value Vth of the liquid crystal. In other words, in the range of Vth, the "fixed potential" may be a constant potential that is shifted from the intermediate value of the liquid crystal driving voltage. In addition, the above "high resistance" can be selected from the range of 500 mega ohms to 50 tera ohms. As such a resistance value, for exampleA representative 500 giga ohm to 5 tera ohm can be used. In the case where the liquid crystal driving method is a row inversion driving or a dot inversion driving, the common wiring 30 is grounded, for example, via a high resistance of 1 tera ohm, and can be set to a constant potential of substantially 0 V (zero volt). At this time, the common electrode 17 connected to the common wiring 30 is also substantially at a constant potential of 0 V (zero volt), and the accumulated capacitance can be reset. In the case where the potential of the common electrode 17 is set to a constant potential, the contact driving voltage at the time of contact sensing is applied to the contact sensing wiring. When the potential of the common electrode 17 is set to "fixed potential", the liquid crystal drive and the contact drive can be driven without division.
此外，作為形成液晶顯示裝置的主動元件(薄膜電晶體)的通道層之材料，在使用IGZO(Indium Gallium Zinc Oxide、氧化銦鎵鋅)等之氧化物半導體的情況，為了緩和液晶顯示裝置的畫素容易產生殘影的狀態，亦可使用低於1tera歐姆的電阻作為上述的高電阻。In addition, in the case of using an oxide semiconductor such as IGZO (Indium Gallium Zinc Oxide) as a material for forming a channel layer of an active device (thin film transistor) of a liquid crystal display device, in order to alleviate the drawing of the liquid crystal display device It is easy to produce a residual image, and a resistance lower than 1 tera ohm can be used as the high resistance described above.
在後述的黑顯示時，亦可經由上述高電阻將閘極配線或源極配線接地。這時，可防止畫素的殘影。In the black display to be described later, the gate wiring or the source wiring may be grounded via the high resistance. At this time, the residual image of the pixel can be prevented.
又，基於調整與接觸感測有關的時間常數之目的，可調整上述高電阻。在將IGZO等之氧化物半導體用於主動元件的通道層的顯示裝置中，於接觸感測控制中之上述各種的工夫成為可能。在以下記載中有時將氧化物半導體僅稱IGZO。Further, the above high resistance can be adjusted for the purpose of adjusting the time constant related to the contact sensing. In the display device using an oxide semiconductor such as IGZO for the channel layer of the active device, the above various kinds of work in the contact sensing control are possible. In the following description, the oxide semiconductor may be referred to simply as IGZO.
在使用多晶矽半導體作為薄膜電晶體的通道層之電晶體中，漏電流大，有必要朝薄膜電晶體重寫煩雜的映像信號。擔心此重寫煩雜的信號，例如從源極配線產生的雜訊會對接觸感測造成不良影響。將稱為IGZO等之氧化物半導體使用於通道層的薄膜電晶體係漏電流極少而具備記憶性。換言之，具備以氧化物半導體形成的通道層之薄膜電晶體可保持映像信號，因而無需重寫煩雜的信號。備有以氧化物半導體形成的通道層之薄膜電晶體與接觸感測之兼容性極為良好。In a transistor using a polycrystalline germanium semiconductor as a channel layer of a thin film transistor, the leakage current is large, and it is necessary to rewrite a complicated image signal toward the thin film transistor. Worried about this confusing signal, such as from source wiringThe noise will have an adverse effect on contact sensing. An oxide semiconductor such as IGZO or the like is used in a thin film transistor system of a channel layer, and has a small amount of leakage current and has memory. In other words, the thin film transistor having the channel layer formed of the oxide semiconductor can hold the image signal, and thus it is not necessary to rewrite the troublesome signal. The thin film transistor provided with the channel layer formed of an oxide semiconductor is extremely compatible with contact sensing.
具體言之，使用氧化物半導體作為通道層之薄膜電晶體係能以驅動液晶的低頻驅動來活用。例如，即便是將液晶驅動頻率設為0.1Hz到30Hz的低頻率驅動，亦可進行無閃爍(flicker)的顯示。功能裝置的低頻率驅動有助於大減消耗電力。再者，藉由進行利用液晶層的低頻率之點反轉驅動及與此低頻率相異的接觸感測驅動，高精度的接觸感測成為可能。In particular, a thin film electro-crystalline system using an oxide semiconductor as a channel layer can be utilized for driving a low frequency drive of a liquid crystal. For example, even if the liquid crystal driving frequency is set to a low frequency drive of 0.1 Hz to 30 Hz, a flicker-free display can be performed. The low frequency drive of the functional device helps to greatly reduce power consumption. Further, by performing low-frequency dot inversion driving using the liquid crystal layer and contact sensing driving at a low frequency, high-accuracy contact sensing is possible.
此外，為將驅動裝置、即薄膜電晶體以第2導電配線來驅動，第2導電配線至少設成向薄膜電晶體傳送映像信號的源極配線或傳送閘極信號的閘極配線即可。以下的記載中，有時將薄膜電晶體記載成主動元件。Further, in order to drive the driving device, that is, the thin film transistor, by the second conductive wiring, the second conductive wiring may be provided with at least a source wiring for transmitting a video signal to the thin film transistor or a gate wiring for transmitting a gate signal. In the following description, a thin film transistor may be described as an active element.
其次，參照圖4，針對連接於畫素電極20的主動元件28之構造作說明。Next, the configuration of the active element 28 connected to the pixel electrode 20 will be described with reference to FIG.
圖4係顯示具有頂閘極構造之薄膜電晶體(TFT)的一例。Fig. 4 shows an example of a thin film transistor (TFT) having a top gate structure.
主動元件28具備：通道層27；連接於通道層27的一端(第一端，圖4中之通道層27的左端)之汲極電極26；連接於通道層27的另一端(第二端，圖4中之通道層27的右端)之源極電極24；及隔著第3絕緣層13與通道層27對向配置的閘極電極25。圖4係顯示構成主動元件28的通道層27、汲極電極26及源極電極24被形成於第4絕緣層14上的構造，但本發明不受此種構造所限定。亦可未設置第4絕緣層14而在透明基板22上直接形成主動元件28。The active component 28 is provided with: a channel layer 27; a drain electrode 26 connected to one end of the channel layer 27 (the first end, the left end of the channel layer 27 in FIG. 4); and the other end connected to the channel layer 27 (the second end, The source electrode 24 of the right end of the channel layer 27 in FIG. 4; and the gate electrode 25 disposed opposite to the channel layer 27 via the third insulating layer 13. 4 shows a structure in which the channel layer 27, the drain electrode 26, and the source electrode 24 constituting the active device 28 are formed on the fourth insulating layer 14, but the present invention is not limited to such a configuration. The active element 28 may be formed directly on the transparent substrate 22 without providing the fourth insulating layer 14.
源極配線31被以高的頻度供給映像信號，容易從源極配線31產生雜訊。關於頂閘極構造，具有能使亦是雜訊發生源的源極配線31從前述的接觸感測空間疏離的益處。The source wiring 31 is supplied with a video signal at a high frequency, and it is easy to generate noise from the source wiring 31. Regarding the top gate structure, there is a benefit of being able to alienate the source wiring 31 which is also a source of noise generation from the aforementioned contact sensing space.
又，本發明未限定具有頂閘極構造的薄膜電晶體，亦可適用具有底閘極構造的薄膜電晶體。Further, the present invention is not limited to a thin film transistor having a top gate structure, and a thin film transistor having a bottom gate structure can also be applied.
圖4所示之源極電極24和汲極電極26係於相同工程中以相同構成的導電層形成。在第1實施形態中，作為源極電極24和汲極電極26的構造，採用鈦/鋁合金/鈦的3層構成。此處，鋁合金係鋁-釹的合金。The source electrode 24 and the drain electrode 26 shown in FIG. 4 are formed in the same process as a conductive layer having the same structure. In the first embodiment, the structure of the source electrode 24 and the drain electrode 26 is a three-layer structure of titanium/aluminum alloy/titanium. Here, the aluminum alloy is an alloy of aluminum-niobium.
位在閘極電極25的下部之第3絕緣層13係亦可為具有與閘極電極25相同寬度之絕緣層。這時，例如，進行將閘極電極25用作遮罩的乾式蝕刻，除去閘極電極25周圍的第3絕緣層13。藉此，可形成具有和閘極電極25相同寬度之絕緣層。將閘極電極25用作遮罩且以乾式蝕刻加工絕緣層的技術，一般稱為自我整合。The third insulating layer 13 located at the lower portion of the gate electrode 25 may be an insulating layer having the same width as the gate electrode 25. At this time, for example, dry etching using the gate electrode 25 as a mask is performed, and the third insulating layer 13 around the gate electrode 25 is removed. Thereby, an insulating layer having the same width as the gate electrode 25 can be formed. A technique in which the gate electrode 25 is used as a mask and the insulating layer is processed by dry etching is generally referred to as self-integration.
藉由閘極電極25及第3絕緣層13形成具有相同寬度，可減低寄生電容。閘極電極25係以和閘極配線10相同工程，利用第1導電性金屬氧化物層/銅合金層/第2導電性金屬氧化物層的3層構成(導電配線)形成。By forming the same width by the gate electrode 25 and the third insulating layer 13, the parasitic capacitance can be reduced. The gate electrode 25 is formed in the same manner as the gate wiring 10, and is formed by a three-layer structure (conductive wiring) of the first conductive metal oxide layer/copper alloy layer/second conductive metal oxide layer.
通道層27的材料方面，例如，可使用稱為IGZO的氧化物半導體。通道層27的材料方面，可使用含有鎵、銦、鋅、錫、鋁、鍺、銻、鉍、鈰當中2種以上的金屬氧化物之氧化物半導體。本實施形態中，使用含有氧化銦、氧化鎵及氧化鋅的氧化物半導體。以氧化物半導體形成的通道層27之材料係亦可為單結晶、多結晶、微結晶、微結晶與非結晶之混合體或非結晶任一者。氧化物半導體的膜厚方面，可設為2nm~50nm的範圍內的膜厚。此外，通道層27亦可使用多晶矽半導體形成。As the material of the channel layer 27, for example, an oxide semiconductor called IGZO can be used. As the material of the channel layer 27, an oxide semiconductor containing two or more kinds of metal oxides of gallium, indium, zinc, tin, aluminum, lanthanum, cerium, lanthanum, and cerium can be used. In the present embodiment, an oxide semiconductor containing indium oxide, gallium oxide, and zinc oxide is used. The material of the channel layer 27 formed of an oxide semiconductor may be a single crystal, a polycrystal, a microcrystal, a mixture of microcrystals and non-crystals, or a non-crystal. The film thickness of the oxide semiconductor can be set to be in the range of 2 nm to 50 nm. Further, the channel layer 27 may also be formed using a polysilicon semiconductor.
氧化物半導體或多晶矽半導體例如可使用於具有p/n接合的互補型電晶體的構成，或僅具有n型接合的單通道型電晶體的構成。作為氧化物半導體的積層構成，例如，亦可採用積層有n型氧化物半導體及與此n型氧化物半導體之電氣特性相異的n型氧化物半導體之積層構造。積層的n型氧化物半導體亦可用複數層來構成。在積層的n型氧化物半導體中，可使基底的n型半導體之帶隙與位在上層的n型半導體之帶隙相異。The oxide semiconductor or the polysilicon semiconductor can be used, for example, for a configuration of a complementary transistor having p/n junction or a configuration of a single channel transistor having only n-type bonding. As a laminated structure of the oxide semiconductor, for example, a laminated structure in which an n-type oxide semiconductor and an n-type oxide semiconductor having electrical characteristics different from those of the n-type oxide semiconductor are laminated may be employed. The laminated n-type oxide semiconductor can also be formed by a plurality of layers. In the laminated n-type oxide semiconductor, the band gap of the n-type semiconductor of the substrate can be made different from the band gap of the n-type semiconductor located in the upper layer.
亦可採用通道層的上面例如以相異的氧化物半導體覆蓋的構成。或者，亦可採用例如在結晶性的n型氧化物半導體上積層有微結晶(接近非晶質)的氧化物半導體之積層構成。此處所謂的微結晶係指，例如，將以濺鍍裝置成膜的非晶質氧化物半導體在180℃以上且450℃以下的範圍熱處理後的微結晶狀的氧化物半導體膜。或是將成膜時的基板溫度設定在200℃左右的狀態下所成膜之微結晶狀的氧化物半導體膜。微結晶狀的氧化物半導體膜係為可藉由TEM等之觀察方法觀察到至少1nm至3nm左右，或大於3nm的結晶粒之氧化物半導體膜。It is also possible to adopt a configuration in which the upper surface of the channel layer is covered with a different oxide semiconductor, for example. Alternatively, for example, a laminated structure of an oxide semiconductor in which a microcrystalline (near amorphous) layer is laminated on a crystalline n-type oxide semiconductor may be employed. The microcrystalline crystal film is a microcrystalline oxide semiconductor film obtained by heat-treating an amorphous oxide semiconductor formed by a sputtering apparatus in a range of 180° C. or higher and 450° C. or lower. Or a microcrystalline oxide semiconductor film formed by setting the substrate temperature at the time of film formation to about 200 °C. The microcrystalline oxide semiconductor film is an oxide semiconductor film which can be observed as a crystal grain of at least 1 nm to 3 nm or more than 3 nm by an observation method such as TEM.
氧化物半導體由藉由從非晶質變化成結晶質，可實現改善載體遷移率、提升可靠性。作為氧化銦、氧化鎵的氧化物之融點高。氧化銻、氧化鉍的融點均為1000℃以下且氧化物的融點低。例如，在採用氧化銦與氧化鎵以及氧化銻的3元系複合氧化物之情況，因為融點低的氧化銻之效果，可降低此複合氧化物的結晶化溫度。換言之，可提供從非晶質狀態容易結晶化成微結晶狀態等之氧化物半導體。The oxide semiconductor can be improved in carrier mobility and improved in reliability by changing from amorphous to crystalline. The melting point of the oxide of indium oxide or gallium oxide is high. The melting point of cerium oxide and cerium oxide is 1000 ° C or less and the melting point of the oxide is low. For example, in the case of using a ternary composite oxide of indium oxide and gallium oxide and cerium oxide, the crystallization temperature of the composite oxide can be lowered because of the effect of cerium oxide having a low melting point. In other words, an oxide semiconductor which is easily crystallized from an amorphous state to a microcrystalline state or the like can be provided.
作為半導體的積層構成，亦可在n型多晶矽半導體上積層n型氧化物半導體。關於獲得將此多晶矽半導體用作基底層的積層構造之方法，以在利用雷射退火進行多晶矽結晶化工程之後，在維持著真空狀態下藉由濺鍍等對氧化物半導體進行成膜者較佳。作為適用於此方法的氧化物半導體，由於在後工程的濕式蝕刻中被要求易溶性，故可使用富氧化鋅的複合氧化物。例如，在用於濺鍍的靶材之金屬元素的原子比方面，可例示In：Ga：Zn=1：2：2。此積層構成中，亦可採用僅多晶矽的通道層上未積層氧化物半導體(例如，藉濕式蝕刻除去的)構成。此處，Zn(鋅)可取代成Sb(銻)或Bi(鉍)。As the laminated structure of the semiconductor, an n-type oxide semiconductor may be laminated on the n-type polysilicon semiconductor. In order to obtain a laminated structure using the polycrystalline germanium semiconductor as a base layer, it is preferable to form an oxide semiconductor by sputtering or the like after maintaining a vacuum state by polycrystalline germanium crystallization. . As applicable to this methodAs the oxide semiconductor, since it is required to be easily soluble in wet etching of a post-engineering, a zinc oxide-rich composite oxide can be used. For example, in the atomic ratio of the metal element of the target for sputtering, In:Ga:Zn=1:2:2 can be exemplified. In the laminated structure, it is also possible to adopt a structure in which only an oxide semiconductor (for example, removed by wet etching) is formed on the channel layer of the polycrystalline germanium. Here, Zn (zinc) may be substituted with Sb (锑) or Bi (铋).
再者，亦能以於同一畫素上各配設一個具有n型氧化物半導體的通道層之薄膜電晶體(主動元件)及具有n型矽半導體的通道層之薄膜電晶體(主動元件)，活用薄膜電晶體的各個通道層之特性的方式，驅動液晶層或OLED這樣的顯示功能層。在使用液晶層或OLED作為顯示功能層之情況，可採用n型多晶矽薄膜電晶體作為向顯示功能層施加電壓(電流)的驅動電晶體，可採用n型氧化物半導體的薄膜電晶體作為向此多晶矽薄膜電晶體傳送信號的切換電晶體(switching transistor)。Furthermore, it is also possible to provide a thin film transistor (active device) having a channel layer of an n-type oxide semiconductor and a thin film transistor (active device) having a channel layer of an n-type germanium semiconductor on the same pixel. The display functional layer such as a liquid crystal layer or an OLED is driven in such a manner as to utilize the characteristics of the respective channel layers of the thin film transistor. In the case where a liquid crystal layer or an OLED is used as the display function layer, an n-type polycrystalline germanium film transistor can be used as a driving transistor for applying a voltage (current) to the display function layer, and a thin film transistor of an n-type oxide semiconductor can be used as the driving film. A switching transistor of a polycrystalline germanium film transistor that transmits a signal.
作為汲極電極26及源極電極24(源極配線31)的每一者，可採用相同構造。例如，可將多層的導電層使用於汲極電極26及源極電極24。例如，可採用將鋁、銅或此等的合金層以鉬、鈦、鉭、鎢、導電性金屬氧化物層等予以夾持的電極構造。亦可在第4絕緣層14上先形成汲極電極26及源極電極24，再以於此等2個電極上積層的方式形成通道層27。電晶體的構造亦可為雙閘極構造等之多閘極構造。或者，作為陣列基板內的電晶體的構造，亦可為在通道層的上下配置有電極之雙重閘極構造。The same structure can be adopted as each of the drain electrode 26 and the source electrode 24 (source wiring 31). For example, a plurality of conductive layers can be used for the drain electrode 26 and the source electrode 24. For example, an electrode structure in which aluminum, copper or the like alloy layer is sandwiched by molybdenum, titanium, tantalum, tungsten, a conductive metal oxide layer or the like can be used. The drain electrode 26 and the source electrode 24 may be formed on the fourth insulating layer 14, and the channel layer 27 may be formed by laminating the two electrodes. The structure of the transistor can also be a multi-gate structure such as a double gate structure. Or as a transistor in the array substrateThe structure may also be a double gate structure in which electrodes are disposed above and below the channel layer.
半導體層或通道層亦可於其厚度方向調整遷移率或電子濃度。半導體層或通道層亦可為積層有相異的氧化物半導體之積層構造。由源極電極與汲極電極之最小間隔所決定之電晶體的通道長係10nm以上且10μm以下，例如，可設為20nm至0.5μm。The semiconductor layer or the channel layer can also adjust the mobility or electron concentration in the thickness direction thereof. The semiconductor layer or the channel layer may also have a laminated structure in which different oxide semiconductors are laminated. The channel length of the transistor determined by the minimum interval between the source electrode and the drain electrode is 10 nm or more and 10 μm or less, and may be, for example, 20 nm to 0.5 μm.
第3絕緣層13係作為閘極絕緣層發揮功能。作為此種絕緣層材料，採用氧化鉿矽(HfSiOx)、氧化矽、氧化鋁、氮化矽、氮氧化矽、氮氧化鋁、氧化鋯、氧化鎵、氧化鋅、氧化鉿、氧化鈰、氧化鑭、或混合此等材料所獲得之絕緣層等。氧化鈰係介電常數高且鈰與氧原子相結合強固。因此，將閘極絕緣層設為含有氧化鈰的複合氧化物較佳。在採用氧化鈰作為構成複合氧化物的氧化物之一的情況亦是，即便是非晶質狀態亦容易保持高的介電常數。氧化鈰具備氧化力。閘極絕緣層，例如，閘極絕緣層係含有氧化鈰的氧化物或是含有氧化鈰的氧氮化物。The third insulating layer 13 functions as a gate insulating layer. As such an insulating layer material, cerium oxide (HfSiOx), cerium oxide, aluminum oxide, cerium nitride, cerium oxynitride, aluminum oxynitride, zirconia, gallium oxide, zinc oxide, cerium oxide, cerium oxide, cerium oxide are used. Or an insulating layer obtained by mixing such materials. The lanthanum oxide system has a high dielectric constant and is strongly bonded to the oxygen atom. Therefore, it is preferable to make the gate insulating layer a composite oxide containing cerium oxide. In the case where cerium oxide is used as one of the oxides constituting the composite oxide, it is easy to maintain a high dielectric constant even in an amorphous state. Cerium oxide has an oxidizing power. The gate insulating layer, for example, the gate insulating layer contains an oxide of cerium oxide or an oxynitride containing cerium oxide.
氧化鈰係可進行氧的儲藏和放出。因此，藉由氧化物半導體與氧化鈰接觸的構造，從氧化鈰朝氧化物半導體供氧，可避免氧化物半導體的氧欠缺，可實現穩定的氧化物半導體(通道層)。在將SiN等的氮化物用於閘極絕緣層的構成中未發現上述那樣的作用。又，閘極絕緣層的材料亦可含有以氧化鈰矽(CeSiOx)為代表的鑭系金屬矽酸鹽。或者，亦可含有鑭鈰複合氧化物、鑭鈰矽酸鹽、及鈰氮氧化物。The lanthanum oxide system can store and release oxygen. Therefore, by the structure in which the oxide semiconductor is in contact with the ruthenium oxide, oxygen is supplied from the ruthenium oxide to the oxide semiconductor, oxygen deficiency of the oxide semiconductor can be avoided, and a stable oxide semiconductor (channel layer) can be realized. Using a nitride such as SiN for the gateThe above-described effects were not found in the structure of the insulating layer. Further, the material of the gate insulating layer may also contain a lanthanide metal silicate represented by cerium oxide (CeSiOx). Alternatively, it may contain a cerium composite oxide, a ceric acid salt, and a cerium oxynitride.
因此，藉由氧化物半導體與氧化鈰接觸的構造，可避免氧化物半導體的氧欠缺，可實現穩定的氧化物。在將氮化物用於閘極絕緣層的構成中未發現上述那樣的作用。又，閘極絕緣層的材料亦可含有以氧化鈰矽(CeSiOx)為代表之鑭系金屬矽酸鹽。Therefore, by the structure in which the oxide semiconductor is in contact with the cerium oxide, oxygen deficiency of the oxide semiconductor can be avoided, and a stable oxide can be realized. The above-described effects were not found in the structure in which the nitride was used for the gate insulating layer. Further, the material of the gate insulating layer may contain a lanthanide metal silicate represented by cerium oxide (CeSiOx).
作為第3絕緣層13的構造，亦可為單層膜、混合膜或多層膜。在混合膜、多層膜的情況，藉由選自上述絕緣膜材料的材料可形成混合膜、多層膜。第3絕緣層13的膜厚，例如係可從2nm以上300nm以下的範圍內作選擇的膜厚。在將通道層27以氧化物半導體形成的情況，於含有多氧的狀態(成膜環境)下可形成和通道層27接觸的第3絕緣層13之界面。The structure of the third insulating layer 13 may be a single layer film, a mixed film or a multilayer film. In the case of a mixed film or a multilayer film, a mixed film or a multilayer film can be formed by a material selected from the above-mentioned insulating film materials. The film thickness of the third insulating layer 13 can be, for example, a film thickness selected from the range of 2 nm to 300 nm. In the case where the channel layer 27 is formed of an oxide semiconductor, the interface of the third insulating layer 13 in contact with the channel layer 27 can be formed in a state containing a polyoxygen (film formation environment).
於薄膜電晶體的製造工程中，就具有頂閘極構造的薄膜電晶體而言，係在形成氧化物半導體後，在含有氧的導入氣體之中，可形成含氧化鈰的閘極絕緣層。此時，能使位在閘極絕緣層之下的氧化物半導體的表面氧化，且能調整其表面的氧化程度。在具有底閘極構造的薄膜電晶體中，由於閘極絕緣層的形成工程是比氧化物半導體的工程還先進行，故調整氧化物半導體表面的氧化程度稍有難度。具有頂閘極構造的薄膜電晶體係比底閘極構造的情況還能促進氧化物半導體表面的氧化，氧化物半導體不易發生氧欠缺。In the manufacturing process of a thin film transistor, in the case of a thin film transistor having a top gate structure, after forming an oxide semiconductor, a gate insulating layer containing ruthenium oxide can be formed in an introduction gas containing oxygen. At this time, the surface of the oxide semiconductor positioned under the gate insulating layer can be oxidized, and the degree of oxidation of the surface can be adjusted. In a thin film transistor having a bottom gate structure, since the formation of the gate insulating layer is a semiconductor semiconductingThe work of the body is also carried out first, so it is somewhat difficult to adjust the degree of oxidation of the surface of the oxide semiconductor. The thin film electro-crystal system having the top gate structure can also promote the oxidation of the surface of the oxide semiconductor than the bottom gate structure, and the oxide semiconductor is less likely to be deficient in oxygen.
含有第1絕緣層11、第2絕緣層12、第3絕緣層13及氧化物半導體的基底的絕緣層(第4絕緣層14)之複數個絕緣層，係可使用無機絕緣材料或有機絕緣材料來形成。作為絕緣層的材料，可使用氧化矽、氮氧化矽、氧化鋁，作為絕緣層的構造，可使用含有上述材料的單層或複數層。亦可為積層有以相異的絕緣材料形成的複數個層之構成。為獲得將絕緣層的上面平坦化的效果，亦可將丙烯酸樹脂、聚醯亞胺樹脂、苯環丁烯樹脂、聚醯胺樹脂等使用在一部分的絕緣層上。也可使用低介電常數材料(low-k材料)。The insulating layer (the fourth insulating layer 14) including the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the base of the oxide semiconductor may be an inorganic insulating material or an organic insulating material. To form. As the material of the insulating layer, cerium oxide, cerium oxynitride, or aluminum oxide can be used as the structure of the insulating layer, and a single layer or a plurality of layers containing the above materials can be used. It may also be a laminate of a plurality of layers formed of different insulating materials. In order to obtain an effect of flattening the upper surface of the insulating layer, an acrylic resin, a polyimide resin, a benzene cyclobutene resin, a polyamide resin, or the like may be used on a part of the insulating layer. Low dielectric constant materials (low-k materials) can also be used.
通道層27之上隔著第3絕緣層13配設閘極電極25。閘極電極25(閘極配線10)係能以使用和共通電極17或共同配線30相同材料且具有相同層構成的方式以相同工程形成。又，閘極電極25係亦能以使用和上述的汲極電極26及源極電極24相同材料且具有相同層構造的方式形成。作為閘極電極25的構造，可採用銅層或銅合金層是被導電性金屬氧化物所夾持的構成。A gate electrode 25 is disposed on the channel layer 27 via the third insulating layer 13. The gate electrode 25 (the gate wiring 10) can be formed in the same manner by using the same material as the common electrode 17 or the common wiring 30 and having the same layer configuration. Further, the gate electrode 25 can also be formed using the same material as the above-described drain electrode 26 and source electrode 24 and having the same layer structure. As the structure of the gate electrode 25, a structure in which a copper layer or a copper alloy layer is sandwiched by a conductive metal oxide can be employed.
亦能將露出於閘極電極25的端部之金屬層的表面以含有銦的複合氧化物覆蓋。或用氮化矽或氮化鉬等之氮化物以包含閘極電極25的端部(剖面)之方式覆蓋閘極電極25整體亦可。或，將具有與上述的閘極絕緣層相同組成之絕緣膜以比50nm還厚的膜厚積層亦可。It is also possible to cover the surface of the metal layer exposed at the end of the gate electrode 25 with a composite oxide containing indium. Alternatively, the gate electrode 25 may be entirely covered with a nitride such as tantalum nitride or molybdenum nitride so as to cover the end portion (cross section) of the gate electrode 25. Alternatively, an insulating film having the same composition as that of the above-described gate insulating layer may be laminated with a film thickness thicker than 50 nm.
在閘極電極25的形成方法方面，亦可在閘極電極25形成前，先僅對位在主動元件28的通道層27的正上之第3絕緣層13施以乾式蝕刻等，將第3絕緣層13的厚度薄化。In the method of forming the gate electrode 25, the third insulating layer 13 located directly above the channel layer 27 of the active device 28 may be subjected to dry etching or the like before the formation of the gate electrode 25, and the third layer may be applied. The thickness of the insulating layer 13 is thinned.
亦可在和第3絕緣層13接觸的閘極電極25之界面再插入電氣性質相異之氧化物半導體。或將第3絕緣層13以至少含有氧化鈰或氧化鎵的絕緣性金屬氧化物層來形成亦可。An oxide semiconductor having a different electrical property may be further inserted at the interface of the gate electrode 25 in contact with the third insulating layer 13. Alternatively, the third insulating layer 13 may be formed of an insulating metal oxide layer containing at least cerium oxide or gallium oxide.
又，在通道層27下部亦可形成遮光膜。作為遮光膜的材料，可使用鉬、鎢、鈦、鉻等之高融點金屬。Further, a light shielding film may be formed on the lower portion of the channel layer 27. As a material of the light shielding film, a high melting point metal such as molybdenum, tungsten, titanium, or chromium can be used.
閘極配線10和主動元件28就電性而言有協作關係。具體言之，連接於閘極配線10的閘極電極25與主動元件28的通道層27係隔著第3絕緣層13對向。因應從映像信號控制部121供給至閘極電極25的掃描信號而在主動元件28進行切換驅動。The gate wiring 10 and the active component 28 have a cooperative relationship in terms of electrical properties. Specifically, the gate electrode 25 connected to the gate wiring 10 and the channel layer 27 of the active device 28 are opposed to each other via the third insulating layer 13. The active element 28 is switched and driven in response to a scan signal supplied from the image signal control unit 121 to the gate electrode 25.
為了抑制起因於供給至源極配線31的映像信號之雜訊附於共同配線30，有必要將第3絕緣層13增厚。另一方面，第3絕緣層13具有作為位在閘極電極25與通道層27之間的閘極絕緣層之功能，被要求經考量主動元件28的切換特性後之適切的膜厚。為了實現這樣相反的2個功能，藉由將在共同配線30與源極配線31之間的第3絕緣層13的膜厚維持大的狀態下而將位在通道層27正上方的第3絕緣層13之厚度減薄，可抑制起因於被供給至源極配線的映像信號之雜訊附於共同配線30，同時主動元件28可實現所期望的切換特性。In order to suppress the noise due to the image signal supplied to the source wiring 31 from being attached to the common wiring 30, it is necessary to thicken the third insulating layer 13.On the other hand, the third insulating layer 13 has a function as a gate insulating layer between the gate electrode 25 and the channel layer 27, and is required to have a suitable film thickness after considering the switching characteristics of the active device 28. In order to achieve such two opposite functions, the third insulating layer positioned directly above the channel layer 27 is maintained in a state where the film thickness of the third insulating layer 13 between the common wiring 30 and the source wiring 31 is maintained large. The thickness of the layer 13 is reduced, and the noise due to the image signal supplied to the source wiring can be suppressed from being attached to the common wiring 30, and the active element 28 can achieve desired switching characteristics.
又，在通道層27的下部亦可形成遮光膜。遮光膜的材料方面，可使用鉬、鎢、鈦、鉻等之高融點金屬。Further, a light shielding film may be formed on the lower portion of the channel layer 27. As the material of the light shielding film, a high melting point metal such as molybdenum, tungsten, titanium or chromium can be used.
閘極配線10和主動元件28就電性而言有協作關係。具體言之，連接於閘極配線10的閘極電極25與主動元件28的通道層27係隔著第3絕緣層13對向。因應從映像信號控制部121供給至閘極電極25的掃描信號而在主動元件28進行切換驅動。The gate wiring 10 and the active component 28 have a cooperative relationship in terms of electrical properties. Specifically, the gate electrode 25 connected to the gate wiring 10 and the channel layer 27 of the active device 28 are opposed to each other via the third insulating layer 13. The active element 28 is switched and driven in response to a scan signal supplied from the image signal control unit 121 to the gate electrode 25.
源極配線31被賦予來自映像信號控制部121之作為映像信號的電壓。源極配線31，例如，被賦予±2.5V至±5V之正或負的電壓的映像信號。作為施加於共通電極17的電壓，例如，可設為按圖框反轉變化的±2.5V的範圍。又，共通電極17的電位亦可設為從液晶驅動的閾值Vth以下至0V的範圍之定電位。在將此共通電極適用於後述的定電位驅動之情況，以於通道層27使用氧化物半導體為宜。以氧化物半導體構成的通道層之電氣的耐電壓高，藉由使用了氧化物半導體的電晶體，將超過±5V的幅度(range)之高的驅動電壓施加於電極部17A，可使液晶的響應高速化。液晶驅動可適用圖框反轉驅動、行反轉(垂直線反轉)驅動、水平線反轉驅動、點反轉驅動等各種驅動方法。The source wiring 31 is supplied with a voltage as a video signal from the video signal control unit 121. The source wiring 31 is, for example, a picture signal given a positive or negative voltage of ±2.5V to ±5V. The voltage applied to the common electrode 17 can be, for example, a range of ±2.5 V which is reversely changed in the frame. Further, the potential of the common electrode 17 may be a constant potential ranging from a threshold value Vth of the liquid crystal drive to a range of 0 V. In the case where the common electrode is applied to a constant potential driving to be described later, it is preferable to use an oxide semiconductor for the channel layer 27. Electrical withstand voltage of a channel layer composed of an oxide semiconductorWhen a transistor having an oxide semiconductor is used, a driving voltage higher than a range of ±5 V is applied to the electrode portion 17A, and the response of the liquid crystal can be increased. The liquid crystal driver can be applied to various driving methods such as frame inversion driving, line inversion (vertical line inversion) driving, horizontal line inversion driving, and dot inversion driving.
閘極電極25的構成的一部分採用銅合金之情況，對銅可添加0.1原子%以上且4原子%以下的範圍內之金屬元素或半金屬元素。如此藉由將元素對銅添加，可獲得能抑制銅的遷移之效果。特別是，以將在銅層的結晶(晶粒)內藉由和銅原子的一部分取代而能配置於銅的晶格位置之元素及在銅層的結晶粒界析出而抑制銅的結晶粒界附近之銅原子的移動之元素一起添加於銅者較佳。或，以為了抑制銅原子的移動而將比銅原子還重的(原子量大的)元素添加於銅者較佳。而且，以選擇相對於銅在0.1原子%至4原子%的範圍內之添加量且銅的導電係數不易降低的添加元素者較佳。再者，當考慮濺鍍等之真空成膜時，以濺鍍等之成膜率接近銅的元素較佳。如上述將元素添加於銅的技術，亦可適用於在假設將銅取代成銀或鋁的情況。換言之，亦可使用銀合金或鋁合金來取代銅合金。In the case where a part of the gate electrode 25 is made of a copper alloy, a metal element or a semimetal element in a range of 0.1 at% or more and 4 at% or less may be added to the copper. Thus, by adding an element to copper, an effect of suppressing migration of copper can be obtained. In particular, an element which can be disposed in a crystal lattice position of copper in a crystal (crystal) of a copper layer and which can be disposed at a lattice position of copper and precipitates at a crystal grain boundary of the copper layer suppresses the vicinity of the crystal grain boundary of copper. It is preferable that the element of the movement of the copper atom is added to the copper together. Alternatively, it is preferable to add an element (large atomic weight) which is heavier than the copper atom to the copper in order to suppress the movement of the copper atom. Further, it is preferable to select an additive element which is added in an amount of from 0.1 atom% to 4 atom% with respect to copper and that the conductivity of copper is not easily lowered. Further, in consideration of vacuum film formation such as sputtering, an element which is close to copper at a film formation rate such as sputtering is preferable. The technique of adding an element to copper as described above can also be applied to the case where it is assumed that copper is substituted with silver or aluminum. In other words, a silver alloy or an aluminum alloy may be used instead of the copper alloy.
將在銅層的結晶(晶粒)內藉由和銅原子的一部分取代而能配置於銅的晶格位置之元素添加於銅，換言之，係將在常溫附近和銅形成固溶體的金屬或半金屬添加於銅。易於和銅形成固溶體的金屬，可例舉錳、鎳、鋅、鈀、鎵、金(Au)等。將在銅層的結晶粒界析出而抑制銅的結晶粒界附近之銅原子的移動之元素添加於銅，換言之，係添加在常溫附近不和銅形成固溶體的金屬或半金屬。不和銅形成固溶體或不易和銅形成固溶體的金屬或半金屬可例舉各種材料。例如，可例舉鈦、鋯、鉬、鎢等之高融點金屬、矽、鍺、銻、鉍等之稱為半金屬的元素等。An element which can be disposed at a lattice position of copper in a crystal (crystal) of a copper layer by substitution with a part of a copper atom is added to copper, in other words, a metal or a semimetal which forms a solid solution with copper at a normal temperature. Added to copper. a metal which is easy to form a solid solution with copper, and may be exemplified by manganese, nickel, zinc,Palladium, gallium, gold (Au), etc. An element which precipitates at the crystal grain boundary of the copper layer and suppresses the movement of copper atoms in the vicinity of the crystal grain boundary of copper is added to copper, in other words, a metal or a semimetal which does not form a solid solution with copper at a normal temperature is added. A metal or a semimetal which does not form a solid solution with copper or which is difficult to form a solid solution with copper may be exemplified by various materials. For example, a high melting point metal such as titanium, zirconium, molybdenum or tungsten, an element called a semimetal such as lanthanum, cerium, lanthanum or cerium may be mentioned.
銅在遷移的觀點上有可靠性的問題。藉由將上述的金屬或半金屬添加於銅中能補償可靠性。對銅添加0.1原子%以上的上述金屬或半金屬能獲得抑制遷移之效果。但是，在對銅添加上述金屬或半金屬超過4原子%的情況，銅的導電係數的惡化變顯著，無法獲得選定銅或銅合金之益處。Copper has a problem of reliability in terms of migration. Reliability can be compensated by adding the above metal or semimetal to copper. Addition of 0.1 atom% or more of the above metal or semimetal to copper can obtain an effect of suppressing migration. However, when the above metal or semimetal is added to copper in excess of 4 atom%, the deterioration of the conductivity of copper becomes remarkable, and the benefit of the selected copper or copper alloy cannot be obtained.
作為上述導電性金屬氧化物，例如可採用從氧化銦、氧化錫、氧化鋅及氧化銻選擇2個以上的複合氧化物(混合氧化物)。亦可於此複合氧化物再少量添加氧化鈦、氧化鋯、氧化鋁、氧化鎂、氧化鍺。氧化銦與氧化錫之複合氧化物通常當作稱為ITO之低電阻的透明導電膜。在使用氧化銦、氧化鋅及氧化錫的三元系複合氧化物之情況，藉由調整氧化鋅及氧化錫之混合比例，可調整濕式蝕刻中之蝕刻率。在藉由氧化銦、氧化鋅及氧化錫的三元系複合氧化物夾持有合金層而成的3層構成中，可調整複合氧化物的蝕刻率及銅合金層的蝕刻率，可將此等3層的圖案寬度設為大致相等。As the conductive metal oxide, for example, two or more composite oxides (mixed oxides) selected from indium oxide, tin oxide, zinc oxide, and cerium oxide can be used. Further, a small amount of titanium oxide, zirconium oxide, aluminum oxide, magnesium oxide or cerium oxide may be added to the composite oxide. A composite oxide of indium oxide and tin oxide is generally referred to as a low-resistance transparent conductive film called ITO. In the case of using a ternary composite oxide of indium oxide, zinc oxide, and tin oxide, the etching rate in wet etching can be adjusted by adjusting the mixing ratio of zinc oxide and tin oxide. In the three-layer structure in which the alloy layer is sandwiched between the ternary composite oxides of indium oxide, zinc oxide, and tin oxide, the etching rate of the composite oxide and the etching rate of the copper alloy layer can be adjusted. The pattern widths of the three layers are set to be substantially equal.
一般，為了進行灰階顯示，因應灰階顯示的各種電壓被施加於源極配線，且映像信號在各種時序被賦予至源極配線。起因於此種映像信號的雜訊係容易附在共通電極17而有降低接觸感測的檢測精度之虞。於是，如圖4所示，藉由採用將源極配線31與接觸感測配線3之距離W2加大的構造，可獲得能減低雜訊的效果。Generally, in order to perform gray scale display, various voltages corresponding to the gray scale display are applied to the source wiring, and the image signal is given to the source wiring at various timings. The noise system resulting from such a video signal is easily attached to the common electrode 17 and has the advantage of reducing the detection accuracy of the contact sensing. Then, as shown in FIG. 4, by using a structure in which the distance W2 between the source wiring 31 and the contact sensing wiring 3 is increased, an effect of reducing noise can be obtained.
本實施形態中，作為主動元件28，採用具有頂閘極構造之電晶體。亦可採用具有底閘極構造的電晶體來取代頂閘極構造，在採用頂閘極構造的電晶體之情況中，可使在Z方向之源極配線31的位置從接觸感測配線3疏離。換言之，在具有頂閘極構造之電晶體的情況，可使源極配線從在接觸感測配線3與共通電極17之間產生靜電電容的空間疏離。藉由使源極配線從如此產生靜電電容的空間疏離，可減低雜訊對在接觸感測配線3與共通電極17之間所檢測之接觸信號的影響，亦即，起因於從源極配線產生的各種映像信號之雜訊所帶給接觸信號之影響。In the present embodiment, as the active element 28, a transistor having a top gate structure is used. Instead of the top gate structure, a transistor having a bottom gate structure may be used. In the case of a transistor having a top gate structure, the position of the source wiring 31 in the Z direction may be separated from the contact sensing wiring 3. . In other words, in the case of the transistor having the top gate structure, the source wiring can be separated from the space where the electrostatic capacitance is generated between the contact sensing wiring 3 and the common electrode 17. By alienating the source wiring from the space in which the electrostatic capacitance is generated, the influence of the noise on the contact signal detected between the contact sensing wiring 3 and the common electrode 17 can be reduced, that is, due to generation from the source wiring. The noise of various image signals is brought to the influence of the contact signal.
本實施形態中，在接觸感測配線3與共通電極17間之物理的空間未含有源極配線31或畫素電極20是重要的。以下說明中，有時將接觸感測配線3與共通電極17間之物理的空間稱為接觸感測空間。又，以形成將閘極配線10與共同配線30(導電配線)之距離及上述的距離W2一併考慮後的接觸感測空間較理想。這時，可緩和起因於供給至閘極配線10的閘極信號之雜訊所帶給共同配線30的影響。In the present embodiment, it is important that the physical space between the contact sensing wiring 3 and the common electrode 17 does not include the source wiring 31 or the pixel electrode 20. In the following description, the physical space between the contact sensing wiring 3 and the common electrode 17 may be referred to as a contact sensing space. Further, the distance between the gate wiring 10 and the common wiring 30 (conductive wiring) and the above-described distance are formed.The contact sensing space after W2 is considered together is ideal. At this time, the influence of the noise caused by the gate signal supplied to the gate wiring 10 to the common wiring 30 can be alleviated.
圖6及圖7係顯示在本發明第1實施形態的顯示裝置DSP1中，接觸感測配線3作為接觸驅動電極發揮功能，且共通電極17作為接觸檢測電極發揮功能之情況的構造。In the display device DSP1 according to the first embodiment of the present invention, the contact sense wiring 3 functions as a contact drive electrode, and the common electrode 17 functions as a contact detection electrode.
依據圖6及圖7所示的構造，進行以下的說明。The following description will be made based on the structures shown in FIGS. 6 and 7.
此外，如上述般，接觸驅動電極與接觸檢測電極之角色可調換。Further, as described above, the roles of the contact driving electrodes and the contact detecting electrodes can be changed.
圖6係顯示在接觸感測配線與共通電極之間產生電場的狀態之示意剖面圖，圖7係顯示在手指等之指標接觸或接近於顯示裝置基板100的觀察者側之表面時的電場之產生狀態的變化之剖面圖。6 is a schematic cross-sectional view showing a state in which an electric field is generated between the contact sensing wiring and the common electrode, and FIG. 7 is an electric field when the index of the finger or the like is in contact with or close to the surface of the viewer side of the display device substrate 100. A profile that produces a change in state.
圖6及圖7中，說明使用了接觸感測配線3與共通電極17之接觸感測技術。圖6及圖7為了容易清楚地說明接觸感測驅動，顯示構成陣列基板200的第1絕緣層11及共通電極17以及顯示裝置基板100，其他構成省略。In FIGS. 6 and 7, the contact sensing technique using the contact sensing wiring 3 and the common electrode 17 will be described. 6 and FIG. 7 show the first insulating layer 11 and the common electrode 17 and the display device substrate 100 constituting the array substrate 200 in order to clearly explain the contact sensing drive, and other configurations are omitted.
如圖6及圖7所示，在相對於液晶層300的厚度方向傾斜之斜方向，接觸感測配線3與共通電極17相互對向。因此，對於產生斜方向電場的狀態之變化，可容易地提升檢測信號之對比，能獲得可提高接觸感測的S/N比之效果(S/N比的改善效果)。再者，關於如此的接觸感測配線3與共通電極17在斜方向相互對向的配置，由於平面視圖中沒有形成接觸感測配線3與共通電極17重疊的重疊部，故可大大減少寄生電容。又，以接觸檢測電極與接觸驅動電極是於厚度的上下方向彼此重疊之構成而言，由於在接觸檢測電極及接觸驅動電極相互重疊的部分之靜電電容難以變化，故難以對接觸感測之S/N比賦予對比。例如，接觸檢測電極與接觸驅動電極是處在同一面上之平行的位置關係之情況為，靜電電容依手指等之指標的位置而變得容易不均一地變化，會有誤檢測及解像度降低之虞。As shown in FIGS. 6 and 7, the contact sense wiring 3 and the common electrode 17 oppose each other in an oblique direction inclined with respect to the thickness direction of the liquid crystal layer 300. Therefore, it is easy to change the state of the electric field in the oblique direction.By comparing the detection signals of the ground, it is possible to obtain an effect of improving the S/N ratio of the contact sensing (the improvement effect of the S/N ratio). Further, in the arrangement in which the contact sensing wiring 3 and the common electrode 17 are opposed to each other in the oblique direction, since the overlapping portion where the contact sensing wiring 3 and the common electrode 17 overlap is not formed in the plan view, the parasitic capacitance can be greatly reduced. . Further, in the configuration in which the contact detecting electrode and the contact driving electrode are overlapped in the vertical direction of the thickness, the electrostatic capacitance in the portion where the contact detecting electrode and the contact driving electrode overlap each other is hard to change, so that it is difficult to sense the contact S. /N ratio gives contrast. For example, when the contact detecting electrode and the contact driving electrode are in a parallel positional relationship on the same surface, the electrostatic capacitance is likely to be unevenly changed depending on the position of the index such as a finger, and the erroneous detection and the resolution are lowered. Hey.
本發明實施形態的顯示裝置DSP1中，如圖2、圖3A及圖3B所示，共通電極17作為檢測電極發揮功能且具有長度EL。此共通電極17與作為驅動電極發揮功能的接觸感測配線3在平面視圖中平行，藉由具有長度EL的共通電極17而能充分且均一地確保靜電電容。In the display device DSP1 according to the embodiment of the present invention, as shown in FIGS. 2, 3A, and 3B, the common electrode 17 functions as a detecting electrode and has a length EL. The common electrode 17 is parallel to the contact sense wiring 3 functioning as a drive electrode in plan view, and the electrostatic capacitance can be sufficiently and uniformly ensured by the common electrode 17 having the length EL.
圖6係示意地顯示使接觸感測配線3作為接觸驅動電極發揮功能且使共通電極17作為接觸檢測電極發揮功能之情況下之靜電電容之產生狀況。接觸感測配線3被供給既定頻率且脈衝狀的寫入信號。此寫入信號的供給亦能以液晶驅動與接觸驅動之分時來進行。藉由寫入信號，使得以電力線33(箭頭)表示的靜電電容被維持在接地之共通電極17與接觸感測配線3之間。FIG. 6 is a view schematically showing a state in which the electrostatic capacitance is generated when the contact sensing wiring 3 functions as a contact driving electrode and the common electrode 17 functions as a contact detecting electrode. The contact sensing wiring 3 is supplied with a pulse signal of a predetermined frequency. The supply of the write signal can also be performed in the time division of the liquid crystal driving and the contact driving. By writing the signal, the electrostatic capacitance indicated by the power line 33 (arrow) is maintained between the ground common electrode 17 and the contact sensing wiring 3.
如圖7所示，當手指等之指標接觸或接近於顯示裝置基板100的觀察者側之表面時，共通電極17與接觸感測配線3之間的靜電電容變化，藉此靜電電容的變化，檢測有無手指等之指標的接觸。As shown in FIG. 7, when the index of the finger or the like contacts or approaches the surface of the viewer side of the display device substrate 100, the electrostatic capacitance between the common electrode 17 and the contact sensing wiring 3 changes, whereby the electrostatic capacitance changes, Check for contact with indicators such as fingers.
如圖6及圖7所示，在接觸感測配線3與共通電極17之間未設置與液晶驅動相關的電極或配線。再者，如圖4所示，源極配線31自接觸感測配線3及共通電極17(接觸驅動配線及接觸檢測配線)偏離。因此，實現難以拾取與液晶驅動相關的雜訊。As shown in FIGS. 6 and 7, electrodes or wirings related to liquid crystal driving are not provided between the contact sensing wiring 3 and the common electrode 17. Further, as shown in FIG. 4, the source wiring 31 is deviated from the contact sensing wiring 3 and the common electrode 17 (contact driving wiring and contact detecting wiring). Therefore, it is difficult to pick up noise related to the liquid crystal driving.
例如，平面視圖中，複數個接觸感測配線3係於第1方向(例如，Y方向)延伸並在第2方向(例如，X方向)排列地配設。複數個共同配線30(導電配線)於Z方向中位在陣列基板200內部之畫素電極20的下方，於第2方向(例如，X方向)延伸，在第1方向(例如，Y方向)排列。共通電極17與共同配線30電連接，將共通電極17與接觸感測配線3之間的靜電電容之變化使用在有無接觸之檢測上。For example, in the plan view, the plurality of contact sensing wires 3 extend in the first direction (for example, the Y direction) and are arranged in the second direction (for example, the X direction). The plurality of common wirings 30 (conductive wirings) are positioned below the pixel electrodes 20 inside the array substrate 200 in the Z direction, and extend in the second direction (for example, the X direction), and are arranged in the first direction (for example, the Y direction). . The common electrode 17 is electrically connected to the common wiring 30, and the change in electrostatic capacitance between the common electrode 17 and the contact sensing wiring 3 is used for detecting the presence or absence of contact.
關於本實施形態的顯示裝置DSP1，在接觸感測配線3與共通電極17之間，例如，以500Hz以上且500KHz以下的頻率施加矩形波狀的脈衝信號。通常，藉由此脈衝信號之施加，檢測電極、即共通電極17係維持固定的輸出波形。當手指等之指標接觸或接近於顯示裝置基板100之觀察者側的表面時，在其部位的共通電極17之輸出波形出現變化，判斷有無接觸。手指等之指標的迄至顯示面為止的距離，係能以指標的從接近到接觸為止的時間(通常是數百μsec以上且數msec以下)或在其時間內計數之輸出脈衝數等來測定。藉由取接觸檢測信號的積分值可進行穩定的接觸檢測。In the display device DSP1 of the present embodiment, a rectangular wave-shaped pulse signal is applied between the contact sense line 3 and the common electrode 17, for example, at a frequency of 500 Hz or more and 500 kHz or less. Generally, the detection electrode, that is, the common electrode 17, maintains a fixed output waveform by the application of the pulse signal. When the index of the finger or the like is in contact with or close to the display device substrateWhen the surface of the observer side of 100 is changed, the output waveform of the common electrode 17 at the portion thereof changes, and it is judged whether or not there is contact. The distance from the index of the finger to the display surface can be measured from the time from the approach to the contact (usually several hundred μsec or more and several msec or less) or the number of output pulses counted in the time. . Stable contact detection can be performed by taking the integrated value of the contact detection signal.
接觸感測配線3及共同配線30(或連接於導電配線之共通電極)亦可全不用在接觸感測。也可進行疏化驅動。其次，針對使接觸感測配線3疏化驅動的情況作說明。首先，將所有的接觸感測配線3區分成複數個群。群的數量係少於所有的接觸感測配線3的數量。構成一個群的配線數，例如設為6條。此處，選擇所有配線(配線數為6條)中例如2條配線(少於所有配線條數的條數，2條<6條)。於一個群，使用所選擇的2條配線進行接觸感測，剩餘的4條配線的電位被設成浮動電位。顯示裝置DSP1由於具有複數個群，所以可如上述按各被定義有配線功能的群進行接觸感測。同樣地，在共同配線30亦可進行疏化驅動。The contact sensing wiring 3 and the common wiring 30 (or a common electrode connected to the conductive wiring) may not be used for contact sensing at all. It can also be driven by thinning. Next, a case where the contact sensing wiring 3 is driven to be thinned and driven will be described. First, all the contact sensing wires 3 are divided into a plurality of groups. The number of groups is less than the number of all contact sensing wires 3. The number of wirings constituting one group is set to, for example, six. Here, for example, two wirings (less than the number of all wiring strips and two <6 strips) are selected among all the wirings (the number of wiring lines is six). In one group, contact sensing is performed using the selected two wires, and the potentials of the remaining four wires are set to a floating potential. Since the display device DSP1 has a plurality of groups, contact sensing can be performed for each group in which the wiring function is defined as described above. Similarly, the common wiring 30 can also be driven by thinning.
用於接觸的指標是手指和是筆的情況，接觸或接近之指標的面積或電容會不同。透過如此的指標之大小，可調整要疏化之配線的條數。就筆或針尖等前端細的指標而言，可使用減少配線的疏化條數之高密度的接觸感測配線之矩陣。指紋認證時也可使用高密度的接觸感測配線之矩陣。The indicators used for contact are the case of the finger and the pen, and the area or capacitance of the indicator of contact or proximity will be different. Through the size of such indicators, the number of wires to be thinned can be adjusted. For a fine index of a tip such as a pen or a needle tip, a matrix of high-density contact sensing wirings that reduce the number of strips of wiring can be used. A matrix of high-density contact sensing wiring can also be used for fingerprint authentication.
如此藉由按每群進行接觸感測驅動，因為用於掃描或檢測的配線數會減少，故可提升接觸感測速度。而且，就上述的例子而言，雖然構成一個群的配線數是6條，但亦可例如以10以上的配線數形成一個群，使用一個群中所選擇的2條配線進行接觸感測。亦即，增加被疏化的配線數(成為浮動電位之配線數)，藉此讓用於接觸感測的選擇配線之密度(相對於全配線數之選擇配線的密度)降低，透過利用選擇配線進行掃描或檢測，有助於減少消耗電力及提升接觸檢測精度。反之，減少被疏化的配線之數量且提高用於接觸感測的選擇配線之密度，利用選擇配線進行掃描或檢測，藉此可活用於例如基於指紋認證或觸控筆之輸入。在這樣的接觸感測的期間，使源極配線31或閘極配線10接地或開路(open)(浮動)，可減少起因於此等配線之寄生電容。Thus, by performing contact sensing driving for each group, since the number of wirings for scanning or detecting is reduced, the contact sensing speed can be improved. Further, in the above-described example, the number of wirings constituting one group is six, but one group may be formed by, for example, 10 or more wirings, and contact sensing may be performed using two wirings selected in one group. In other words, the number of wirings to be thinned (the number of wirings that become the floating potential) is increased, whereby the density of the selection wiring for contact sensing (the density of the selection wiring with respect to the total number of wirings) is lowered, and the selection wiring is used. Scanning or testing helps reduce power consumption and improve contact detection accuracy. Conversely, the number of thinned wirings is reduced and the density of the selected wiring for contact sensing is increased, and scanning or detection is performed using the selected wiring, whereby it can be used for input based on, for example, fingerprint authentication or stylus. During such contact sensing, the source wiring 31 or the gate wiring 10 is grounded or opened (floating), and the parasitic capacitance of the wiring due to the wiring can be reduced.
接觸感測驅動與液晶驅動亦能分時進行。亦可配合所要求之接觸輸入的速度來調整接觸驅動的頻率。接觸驅動頻率係可採用比液晶驅動頻率還高的頻率。手指等之指標接觸或接近於顯示裝置基板100的觀察者側之表面的時序係不定期，且為短時間，故以接觸驅動頻率高者為宜。The contact sensing drive and the liquid crystal drive can also be performed in a time-sharing manner. The frequency of the contact drive can also be adjusted to match the speed of the required contact input. The contact drive frequency can be a frequency higher than the liquid crystal drive frequency. The timing at which the index of the finger or the like is in contact with or close to the surface of the viewer side of the display device substrate 100 is irregular, and is short, so that the contact driving frequency is high.
使接觸驅動頻率與液晶驅動頻率相異的方法係可例舉幾個。例如，以常關型的液晶驅動，在黑顯示(關)時背光亦設為關(off)，於此黑顯示的期間(不影響液晶顯示的期間)進行接觸感測亦可。這時，可選擇各種接觸驅動的頻率。A method of making the contact drive frequency different from the liquid crystal drive frequency can be exemplified. For example, it is driven by a normally-off liquid crystal, when it is black (off)The backlight is also set to off, and the contact sensing may be performed during the black display period (the period during which the liquid crystal display is not affected). At this time, the frequency of various contact drives can be selected.
又，即使是使用具有負的介電常數各向異性之液晶的情況，亦容易選擇與液晶驅動頻率相異之接觸驅動頻率。換言之，如圖6及圖7所示，從接觸感測配線3朝向共通電極17產生的電力線33係作用於液晶層300的斜方向或厚度方向，但若使用具有負的介電常數各向異性之液晶，則因液晶分子未在此電力線33方向立起，故對顯示品質的影響變少。Further, even in the case of using a liquid crystal having a negative dielectric anisotropy, it is easy to select a contact driving frequency which is different from the liquid crystal driving frequency. In other words, as shown in FIGS. 6 and 7, the power line 33 generated from the contact sensing wiring 3 toward the common electrode 17 acts on the oblique direction or the thickness direction of the liquid crystal layer 300, but if it has a negative dielectric anisotropy. In the liquid crystal, since the liquid crystal molecules are not raised in the direction of the power line 33, the influence on the display quality is small.
再者，於降低接觸感測配線3或共同配線30的配線電阻，且隨著電阻之降低而降低接觸驅動電壓的情況，亦可容易設定與液晶驅動頻率不同的接觸驅動頻率。透過在構成接觸感測配線3或共同配線30的金屬層使用銅或銀等之導電係數良好的金屬、合金，可獲得低的配線電阻。Further, when the wiring resistance of the contact sensing wiring 3 or the common wiring 30 is lowered and the contact driving voltage is lowered as the resistance is lowered, the contact driving frequency different from the liquid crystal driving frequency can be easily set. A low wiring resistance can be obtained by using a metal or an alloy having a good electrical conductivity such as copper or silver in the metal layer constituting the contact sensing wiring 3 or the common wiring 30.
在進行3D(立體映像)顯示之顯示裝置的情況，不僅是通常的二維畫像的顯示，為將近前的畫像或處在深處的畫像作三維顯示，複數個映像信號(例如，右眼用的映像信號與左眼用的映像信號)是必要的。因此，關於液晶驅動的頻率，例如，240Hz或480Hz等之高速驅動及多的映像信號是必要的。此時，藉由使接觸驅動的頻率與液晶驅動的頻率相異所能獲得之益處大。例如，依據本實施形態，在進行3D顯示的遊戲機器，高速及高精度的接觸感測成為可能。以本實施形態而言，在遊戲機器或現金自動提款機等之手指等之接觸輸入頻度高的顯示器中亦特別有用。In the case of a display device that performs 3D (stereoscopic image) display, not only the display of a normal two-dimensional image but also a three-dimensional display of a recent image or a deep image, a plurality of image signals (for example, for the right eye) The image signal and the image signal for the left eye are necessary. Therefore, regarding the frequency of the liquid crystal driving, for example, a high-speed driving of 240 Hz or 480 Hz or the like and a plurality of image signals are necessary. At this time, the benefit that can be obtained by making the frequency of the contact drive different from the frequency of the liquid crystal driving is large. For example, according to the present embodiment, a game machine that performs 3D display is high speed and high precision.Contact sensing is possible. In the present embodiment, it is particularly useful in a display having a high frequency of contact with a finger such as a game machine or a cash dispenser.
典型的動畫顯示，基於畫素的映像信號的覆寫動作係被頻繁地進行。由於附隨於此等映像信號之雜訊係從源極配線衍生，所以如本發明實施形態以使源極配線31在厚度方向(Z方向)的位置疏離接觸感測配線3者較佳。依據本發明實施形態，由於接觸驅動信號被施加於位在偏離源極配線31之位置的接觸感測配線3，所以相較於揭示於陣列基板設置有供施加接觸驅動信號的配線之構造之專利文獻6，雜訊的影響變少。A typical animation shows that the overwriting action of the pixel-based image signal is frequently performed. Since the noise accompanying the image signals is derived from the source wiring, it is preferable that the source wiring 31 is separated from the contact wiring 3 in the thickness direction (Z direction) in the embodiment of the present invention. According to the embodiment of the present invention, since the contact driving signal is applied to the contact sensing wiring 3 located at a position deviated from the source wiring 31, the patent relating to the configuration in which the wiring for applying the contact driving signal is provided on the array substrate is disclosed. In Document 6, the influence of noise is less.
一般，液晶驅動的頻率為60Hz，或為此頻率之整數倍的驅動頻率。通常，接觸感測部位會受到伴隨於液晶驅動的頻率之雜訊的影響。而且，通常的家庭電源係50Hz或60Hz的交流電源，接觸感測部位容易拾取從以這樣的外部電源動作的電氣機器產生的雜訊。因此，作為接觸驅動的頻率，藉由採用和50Hz或60Hz的頻率相異的頻率或由此等頻率的整數倍稍偏移的頻率，可大幅減低從液晶驅動或外部電子機器所產生的雜訊之影響。或者在時間軸使接觸感測驅動信號的施加時序從液晶驅動信號的施加時序偏移亦可。偏移量係若干量即可，例如，從雜訊頻率偏移±3%~±17%的偏移量即可。這時，可減低對雜訊頻率之干涉。例如，接觸驅動的頻率，例如，可從500Hz~500KHz的範圍選擇不與上述液晶驅動頻率或電源頻率干涉之相異的頻率。藉由將不與液晶驅動頻率或電源頻率干涉之相異的頻率選作接觸驅動的頻率，例如，可減輕在行反轉驅動之耦合雜訊等之雜訊的影響。Typically, the frequency of the liquid crystal drive is 60 Hz, or a drive frequency that is an integer multiple of this frequency. Usually, the contact sensing portion is affected by noise accompanying the frequency of the liquid crystal driving. Further, the normal household power source is an AC power source of 50 Hz or 60 Hz, and the contact sensing portion can easily pick up noise generated from an electric device that operates with such an external power source. Therefore, as the frequency of the contact drive, the noise generated from the liquid crystal drive or the external electronic device can be greatly reduced by using a frequency different from the frequency of 50 Hz or 60 Hz or a frequency slightly offset by an integral multiple of the same frequency. The impact. Alternatively, the timing of applying the contact sensing drive signal from the time axis may be shifted from the application timing of the liquid crystal driving signal. The offset may be a certain amount, for example, an offset of ±3% to ±17% from the noise frequency. At this time, interference with the noise frequency can be reduced. For example, the frequency of the contact drive, for exampleFor example, a frequency different from the above-mentioned liquid crystal driving frequency or power supply frequency interference can be selected from the range of 500 Hz to 500 kHz. By selecting a frequency that does not interfere with the liquid crystal driving frequency or the power supply frequency as the frequency of the contact driving, for example, the influence of noise such as coupling noise driven by the line inversion driving can be alleviated.
又，關於接觸感測驅動，並非將驅動電壓對所有接觸感測配線3供給，而是如上述般利用疏化驅動進行接觸位置檢測，藉此可減低在接觸感測上的消耗電力。Further, regarding the contact sensing drive, the driving voltage is not supplied to all of the contact sensing wires 3, but the contact position detection is performed by the thinning drive as described above, whereby the power consumption in the contact sensing can be reduced.
關於疏化驅動中未用於接觸感測的配線，亦即具有浮動圖案的配線，亦可藉由切換元件切換成檢測電極或驅動電極以進行高精細的接觸感測。或者具有浮動圖案的配線亦能以和地面(於框體接地)電連接的方式作切換。為改善接觸感測的S/N比，亦可在接觸感測的信號檢測時將TFT等之主動元件的信號配線暫時接地於地面(框體等)。Regarding the wiring that is not used for contact sensing in the thinning drive, that is, the wiring having the floating pattern, it is also possible to switch to the detecting electrode or the driving electrode by the switching element to perform high-definition contact sensing. Or the wiring with the floating pattern can be switched in such a way as to be electrically connected to the ground (grounded at the frame). In order to improve the S/N ratio of the contact sensing, the signal wiring of the active element such as a TFT may be temporarily grounded to the ground (frame or the like) at the time of detecting the signal of the contact sensing.
又，在藉接觸感測控制所檢測的靜電電容之重置需要時間之接觸感測配線，亦即在接觸感測之時間常數(電容與電阻值之積)大的接觸感測配線而言，例如，亦可將奇數行的接觸感測配線和偶數行的接觸感測配線交互利用於感測，進行調整時間常數的大小之驅動。亦可將複數個接觸感測配線群組化並進行驅動或檢測。複數個接觸感測配線的群組化係亦可不按線順序而以其群單位採取亦稱為自我檢測方式的匯總檢測的手法。亦可進行以群單位的並列驅動。或為了消除寄生電容等之雜訊，亦可採用取相互接近或鄰接的接觸感測配線之檢測信號的差的差分檢測方式。Further, in the contact sensing wiring which requires a time by the reset of the electrostatic capacitance detected by the contact sensing control, that is, the contact sensing wiring having a large time constant of the contact sensing (the product of the capacitance and the resistance value), For example, the contact sense wiring of the odd rows and the contact sensing wiring of the even rows may be used interchangeably for sensing, and the magnitude of the adjustment time constant may be driven. A plurality of contact sensing wires can also be grouped and driven or detected. The grouping of a plurality of contact sensing wirings may also adopt a method of collective detection, also referred to as self-detection, in a group unit without line order. Can also be carried outThe parallel drive of group units. Alternatively, in order to eliminate noise such as parasitic capacitance, a differential detection method of taking a difference between detection signals of contact sensing wirings that are close to each other or adjacent to each other may be employed.
依據上述的第1實施形態，可防止發生銅的擴散或銅的遷移，可提升電氣封裝之可靠性。又，藉由使用上述的銅合金作為導電配線或接觸感測配線的構成材料，可穩定地接觸感測，可獲得接觸感測感度高、良好的響應性。特別是可提供一S/N比高、高解像度且能反應高速的接觸輸入之顯示裝置DSP1。再者，藉由採用使用了氧化物半導體的薄膜電晶體作為通道層，可實現低消耗電力、閃爍少，且具備接觸感測功能之顯示裝置DSP1。According to the first embodiment described above, the diffusion of copper or the migration of copper can be prevented, and the reliability of the electrical package can be improved. Further, by using the copper alloy described above as a constituent material of the conductive wiring or the contact sensing wiring, the sensing can be stably contacted, and the contact sensitivity can be improved and the responsiveness can be improved. In particular, it is possible to provide a display device DSP1 having a high S/N ratio, high resolution, and high-speed contact input. Further, by using a thin film transistor using an oxide semiconductor as a channel layer, it is possible to realize a display device DSP1 having low power consumption and low flicker and having a contact sensing function.
圖3A所示的顯示裝置DSP1中，使用設有濾光片51的構造。本實施形態中亦可省略濾光片。在省略濾光片51的構造中，例如，亦可作成備有設於透明基板21上的接觸感測配線3及以覆蓋接觸感測配線3般形成的透明樹脂層16之構造。In the display device DSP1 shown in FIG. 3A, a configuration in which the filter 51 is provided is used. In the present embodiment, the filter may be omitted. In the structure in which the filter 51 is omitted, for example, a contact sensing wiring 3 provided on the transparent substrate 21 and a transparent resin layer 16 formed to cover the contact sensing wiring 3 may be provided.
未含有濾光片51的顯示裝置中，將紅色發光、綠色發光及藍色發光各自的LED設於背光單元，以場序的手法進行彩色顯示。設於圖3A所示之透明基板21上的接觸感測配線3之層構成，可採用形成於陣列基板200的共同配線30(導電配線)之層構成、閘極電極25(閘極配線10)之層構成。In the display device not including the color filter 51, LEDs of each of red light emission, green light emission, and blue light emission are provided in the backlight unit, and color display is performed by field sequential method. The layer structure of the contact sensing wiring 3 provided on the transparent substrate 21 shown in FIG. 3A can be formed by a layer of a common wiring 30 (conductive wiring) formed on the array substrate 200, and a gate electrode 25 (gate wiring 10). The composition of the layers.
關於圖3A所示的顯示裝置DSP1，在顯示裝置基板100(第1基板)的透明基板21和接觸感測配線3的界面，可形成黑色層8或反射防止膜。黑色層8係例如可將碳、碳奈米管、碳奈米角或複數個有機顏料的混合物分散於樹脂而形成。這時亦可獲得和上述的實施形態同樣的效果。With respect to the display device DSP1 shown in FIG. 3A, a black layer 8 or an anti-reflection film can be formed on the interface between the transparent substrate 21 of the display device substrate 100 (first substrate) and the contact sensing wiring 3. The black layer 8 can be formed, for example, by dispersing a mixture of carbon, carbon nanotubes, carbon nanohorns or a plurality of organic pigments in a resin. Also in this case, the same effects as those of the above embodiment can be obtained.
又，本發明亦可適用於未具有接觸感測功能的顯示裝置。這時，採用從圖3A所示的顯示裝置DSP1除去了接觸感測配線3後的構造。換言之，採用第1基板未設置導電配線而在第2基板、即陣列基板200上設有導電配線之構造。Moreover, the present invention is also applicable to a display device that does not have a touch sensing function. At this time, the configuration in which the contact sense wiring 3 is removed from the display device DSP1 shown in FIG. 3A is employed. In other words, the first substrate is not provided with conductive wiring, and the conductive substrate is provided on the second substrate, that is, the array substrate 200.
以下，一邊參照圖面一邊針對本發明第2實施形態作說明。Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
第2實施形態中，對和第1實施形態相同構件賦予同一符號，且省略或簡化其說明。In the second embodiment, the same members as those in the first embodiment are denoted by the same reference numerals, and their description will be omitted or simplified.
圖8係將本發明第2實施形態的顯示裝置DSP2作一部分顯示的剖面圖。圖9係將構成本發明第2實施形態涉及的陣列基板500作一部分顯示的剖面圖。Fig. 8 is a cross-sectional view showing a part of the display device DSP2 according to the second embodiment of the present invention. Fig. 9 is a cross-sectional view showing a part of the array substrate 500 according to the second embodiment of the present invention.
顯示裝置DSP2中，採用有機EL層作為功能裝置，採用薄膜電晶體(主動元件)作為驅動裝置。薄膜電晶體具有以氧化物半導體所構成的通道層58。In the display device DSP2, an organic EL layer is used as a functional device, and a thin film transistor (active device) is used as a driving device. The thin film transistor has a channel layer 58 composed of an oxide semiconductor.
構成第2實施形態的顯示裝置DSP2的顯示裝置基板400(第1基板)，係備有具有第1面MF及與第1面MF相反側的第2面MS之透明基板44(基板本體)。於第1面MF，在觀察方向OB，依序形成有第1接觸感測配線3(導電配線、第1導電配線)、第2接觸感測配線2(導電配線、第3導電配線)。亦即，第2接觸感測配線2位在第1接觸感測配線3與陣列基板500(第2基板)之間。第2接觸感測配線2及第1面MF係被第2透明樹脂層105所覆蓋。The display device substrate 400 (first substrate) constituting the display device DSP2 of the second embodiment is provided with a transparent substrate 44 (substrate body) having a first surface MF and a second surface MS opposite to the first surface MF. In the first surface MF, the first contact sensing wiring 3 (conductive wiring, first conductive wiring) and the second contact sensing wiring 2 (conductive wiring, third conductive wiring) are sequentially formed in the observation direction OB. In other words, the second contact sensing wiring 2 is located between the first contact sensing wiring 3 and the array substrate 500 (second substrate). The second contact sensing wiring 2 and the first surface MF are covered by the second transparent resin layer 105.
在第1接觸感測配線3和第2接觸感測配線2之間，以覆蓋第1接觸感測配線3的方式設有絕緣層I(接觸配線絕緣層)，第1接觸感測配線3與第2接觸感測配線2藉由絕緣層I而相互電性絕緣。An insulating layer I (contact wiring insulating layer) is provided between the first contact sensing wiring 3 and the second contact sensing wiring 2 so as to cover the first contact sensing wiring 3, and the first contact sensing wiring 3 and the first contact sensing wiring 3 are provided. The second contact sensing wirings 2 are electrically insulated from each other by the insulating layer 1.
在圖8所示的構造中，第1透明樹脂層108與第2透明樹脂層105是被貼合。具體言之，隔著透濕性低的第1透明樹脂層108，使具備是有機EL的發光層92的陣列基板500和具備第1接觸感測配線3及第2接觸感測配線2的顯示裝置基板400被貼合。亦即，發光層92(功能裝置)係設於和顯示裝置基板400對向的前述陣列基板500的面。In the structure shown in FIG. 8, the first transparent resin layer 108 and the second transparent resin layer 105 are bonded together. Specifically, the array substrate 500 including the light-emitting layer 92 which is the organic EL and the display including the first contact-sensing wiring 3 and the second contact-sensing wiring 2 are provided via the first transparent resin layer 108 having low moisture permeability. The device substrate 400 is bonded. That is, the light-emitting layer 92 (functional device) is provided on the surface of the array substrate 500 that faces the display device substrate 400.
第2實施形態的第1接觸感測配線3係對應於第1實施形態的接觸感測配線3，具有和第1實施形態同樣的構成，亦即，具有黑色層和設在黑色層上的金屬積層構造。平面視圖中，在與設置於透明基板44上的黑色矩陣(黑色層)相對應的位置上設有第1接觸感測配線3。第1接觸感測配線3係具有藉第1導電性金屬氧化物層6與第2導電性金屬氧化物層4夾持銅合金層5的構成。The first contact-sensing wiring 3 of the second embodiment corresponds to the contact-sensing wiring 3 of the first embodiment, and has the same configuration as that of the first embodiment, that is, has a black layer and a metal provided on the black layer. Laminationstructure. In the plan view, the first contact sensing wiring 3 is provided at a position corresponding to a black matrix (black layer) provided on the transparent substrate 44. The first contact sensing wiring 3 has a configuration in which the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4 .
平面視圖(從觀察方向OB所見)中，第2接觸感測配線2係在對第1接觸感測配線3延伸的方向正交的方向延伸。第2接觸感測配線2係設於絕緣層I上。第2接觸感測配線2具有和第1實施形態的接觸感測配線3同樣的構成，亦即，具有黑色層及設於黑色層上的金屬積層構造。平面視圖中，在和設於絕緣層I上的黑色矩陣(黑色層)對應之位置設有第2接觸感測配線2。第2接觸感測配線2具有藉第1導電性金屬氧化物層6和第2導電性金屬氧化物層4夾持銅合金層5的構成。In the plan view (as seen from the observation direction OB), the second contact sensing wiring 2 extends in a direction orthogonal to the direction in which the first contact sensing wires 3 extend. The second contact sensing wiring 2 is provided on the insulating layer 1. The second contact sensing wiring 2 has the same configuration as the contact sensing wiring 3 of the first embodiment, that is, has a black layer and a metal laminated structure provided on the black layer. In the plan view, the second contact sensing wiring 2 is provided at a position corresponding to the black matrix (black layer) provided on the insulating layer 1. The second contact sensing wiring 2 has a configuration in which the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4 .
第1接觸感測配線3及第2接觸感測配線2連接於接觸感測控制部122，接觸感測控制部122係檢測在第1接觸感測配線3與第2接觸感測配線2之間產生的靜電電容之變化，進行接觸感測。The first contact sensing wiring 3 and the second contact sensing wiring 2 are connected to the contact sensing control unit 122 , and the contact sensing control unit 122 detects between the first contact sensing wiring 3 and the second contact sensing wiring 2 . The resulting electrostatic capacitance changes to make contact sensing.
在X方向延伸的複數個第1接觸感測配線3及在Y方向延伸的複數個第2接觸感測配線2的每一者係電性獨立。第1接觸感測配線3與第2接觸感測配線2在平面視圖中正交。例如，可將第1接觸感測配線3用作為接觸檢測電極，將第2接觸感測配線2用作為接觸驅動電極。接觸感測控制部122係檢測在第1接觸感測配線3與第2接觸感測配線2之交點的第1接觸感測配線3與第2接觸感測配線2之間的靜電電容C2之變化作為接觸信號。Each of the plurality of first contact sensing wires 3 extending in the X direction and the plurality of second contact sensing wires 2 extending in the Y direction are electrically independent. The first contact sensing wiring 3 and the second contact sensing wiring 2 are orthogonal to each other in plan view. For example, the first contact sensing wiring 3 can be used as a contact detecting electrode, and the second contact sensing wiring 2 can be used as a contact driving electrode. The contact sensing control unit 122 detects the first contact sensing wiringThe change in the capacitance C2 between the first contact sense line 3 and the second contact sense line 2 at the intersection of the second contact sense line 2 serves as a contact signal.
又，第1接觸感測配線3的角色與第2接觸感測配線2的角色亦可調換。具體言之，亦可將第1接觸感測配線3作為接觸驅動電極使用，將第2接觸感測配線2作為接觸檢測電極使用。Further, the role of the first contact sensing wiring 3 and the role of the second contact sensing wiring 2 can be reversed. Specifically, the first contact sensing wiring 3 can be used as a contact driving electrode, and the second contact sensing wiring 2 can be used as a contact detecting electrode.
作為第1接觸感測配線3及第2接觸感測配線2每一者的構造，可採用和在第1實施形態說明之圖5所示的剖面構造相同的構造。呈格子狀正交之第1接觸感測配線3與第2接觸感測配線2亦兼具用以提升顯示對比的黑色矩陣之角色。The structure of each of the first contact sensing wires 3 and the second contact sensing wires 2 can be the same as the cross-sectional structure shown in FIG. 5 described in the first embodiment. The first contact sensing wiring 3 and the second contact sensing wiring 2 which are orthogonal to each other in the grid shape also have a role of a black matrix for enhancing display contrast.
其次，針對構成顯示裝置DSP2之陣列基板500的構造作說明。Next, the configuration of the array substrate 500 constituting the display device DSP2 will be described.
作為陣列基板500的基板45，没必要使用透明基板，例如，作為可適用於陣列基板500之基板，可例舉玻璃基板、陶瓷基板、石英基板、藍寶石基板、矽、碳化矽或矽鍺等之半導體基板，或塑膠基板等。As the substrate 45 of the array substrate 500, it is not necessary to use a transparent substrate. For example, as a substrate applicable to the array substrate 500, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, tantalum, niobium carbide or tantalum may be mentioned. A semiconductor substrate, or a plastic substrate.
關於陣列基板500，在基板45上依序積層第4絕緣層14、形成於第4絕緣層14上的主動元件68、以覆蓋第4絕緣層14及主動元件68的方式形成的第3絕緣層13、以與主動元件68的通道層58對向的方式形成於第3絕緣層13上的閘極電極95、以覆蓋第3絕緣層13及閘極電極95的方式形成的第2絕緣層12、及形成在第2絕緣層12上的平坦化層96。In the array substrate 500, the fourth insulating layer 14 is formed on the substrate 45, the active device 68 formed on the fourth insulating layer 14, and the third insulating layer formed to cover the fourth insulating layer 14 and the active device 68. 13. Formed in a manner opposite to the channel layer 58 of the active component 68.The gate electrode 95 on the insulating layer 13 , the second insulating layer 12 formed to cover the third insulating layer 13 and the gate electrode 95 , and the planarization layer 96 formed on the second insulating layer 12 .
於平坦化層96，在對應主動元件68的汲極電極56之位置形成有接觸孔93。又，於平坦化層96上，在與通道層58對應的位置形成有觸排(bank)94。在剖面視圖彼此相鄰的觸排94間之區域中，亦即，平面視圖中被觸排94包圍的區域中，以覆蓋平坦化層96的上面、接觸孔93的內部及汲極電極56的方式形成下部電極88(畫素電極)。此外，下部電極88亦可不被形成在觸排94的上面。In the planarization layer 96, a contact hole 93 is formed at a position corresponding to the gate electrode 56 of the active device 68. Further, on the planarization layer 96, a bank 94 is formed at a position corresponding to the channel layer 58. In the region between the rows 94 adjacent to each other in the cross-sectional view, that is, in the region surrounded by the bank 94 in plan view, to cover the upper surface of the planarization layer 96, the inside of the contact hole 93, and the drain electrode 56. The lower electrode 88 (pixel electrode) is formed in a manner. Further, the lower electrode 88 may not be formed on the upper side of the bank 94.
再者，以覆蓋下部電極88、觸排94及平坦化層96的方式形成電洞注入層91。在電洞注入層91上依序積層發光層92、上部電極87及密封層109。Further, the hole injection layer 91 is formed to cover the lower electrode 88, the bank 94, and the planarization layer 96. The light-emitting layer 92, the upper electrode 87, and the sealing layer 109 are sequentially laminated on the hole injection layer 91.
如後述，下部電極88具有銀或銀合金層被導電性金屬氧化物層所夾持之構成。As will be described later, the lower electrode 88 has a structure in which a silver or silver alloy layer is sandwiched by a conductive metal oxide layer.
作為觸排94的材料，可使用丙烯酸樹脂、聚醯亞胺樹脂、酚醛清漆樹脂等之有機樹脂。在觸排94亦可再積層氧化矽、氮氧化矽等之無機材料。As the material of the bank 94, an organic resin such as an acrylic resin, a polyimide resin, or a novolak resin can be used. In the bank 94, an inorganic material such as cerium oxide or cerium oxynitride may be further laminated.
作為平坦化層96的材料，亦可使用丙烯酸樹脂、聚醯亞胺樹脂、苯環丁烯樹脂、聚醯胺樹脂等。亦可使用低介電常數材料(low-k材料)。As the material of the planarization layer 96, an acrylic resin, a polyimide resin, a benzene cyclobutene resin, a polyamide resin, or the like can also be used. Low dielectric constant materials (low-k materials) can also be used.
此外，為了提升視認性，平坦化層96、密封層109或基板45任一者亦可具有光散射的功能。或者，亦可在基板45的上方形成光散射層。Further, in order to improve visibility, either of the planarization layer 96, the sealing layer 109, or the substrate 45 may have a function of light scattering. Alternatively, a light scattering layer may be formed over the substrate 45.
此外，圖8中，符號290表示以下部電極88、電洞注入層91、發光層92及上部電極87所構成的發光區域。In addition, in FIG. 8, reference numeral 290 denotes a light-emitting region composed of the lower electrode 88, the hole injection layer 91, the light-emitting layer 92, and the upper electrode 87.
如圖9所示，陣列基板500包含功能裝置、即發光層92(有機EL層)。發光層92係為在一對的電極間被賦予電場時，藉由從陽極(例如，下部電極)注入的電洞與從陰極(例如，上部電極、畫素電極)注入的電子再結合而被激發而發光的顯示功能層。As shown in FIG. 9, the array substrate 500 includes a functional device, that is, a light-emitting layer 92 (organic EL layer). The light-emitting layer 92 is recombined with electrons injected from a cathode (for example, an upper electrode or a pixel electrode) by an electric field injected from an anode (for example, a lower electrode) when an electric field is applied between a pair of electrodes. A display function layer that excites and emits light.
發光層92係至少包含具有發光性質的材料(發光材料)，且較佳為包含具有電子輸送性的材料。發光層92係形成在陽極與陰極之間的層，下部電極88(陽極)之上形成有電洞注入層91的情況為，在電洞注入層91和上部電極87(陰極)之間形成發光層92。又，於陽極之上形成有電洞輸送層的情況為，在電洞輸送層和陰極之間形成發光層92。上部電極87與下部電極88之角色可調換。The light-emitting layer 92 is at least composed of a material (light-emitting material) having light-emitting properties, and preferably contains a material having electron transport properties. The light-emitting layer 92 is formed in a layer between the anode and the cathode, and the hole injection layer 91 is formed on the lower electrode 88 (anode) in such a manner that light is formed between the hole injection layer 91 and the upper electrode 87 (cathode). Layer 92. Further, in the case where the hole transport layer is formed on the anode, the light-emitting layer 92 is formed between the hole transport layer and the cathode. The roles of the upper electrode 87 and the lower electrode 88 are interchangeable.
發光層92的膜厚只要是無明顯損及本發明的效果則可為任意，但考量在膜不易產生缺陷這點，以膜厚大者較佳。一方面，在膜厚小的情況，驅動電壓變低，故而較佳。因此，發光層92的膜厚以3nm以上較佳，5nm以上更佳，又，一方面，通常以200nm以下較佳，100nm以下更佳。The film thickness of the light-emitting layer 92 may be any as long as it does not significantly impair the effects of the present invention, but it is preferable that the film thickness is large in the case where the film is less likely to be defective. On the other hand, in the case where the film thickness is small, the driving voltage is lowered, which is preferable. Therefore, the thickness of the light-emitting layer 92 is preferably 3 nm or more, more preferably 5 nm or more, and further preferably 200 nm or less, more preferably 100 nm or less.
發光層92的材料只要以所期望的發光波長發光且無損本發明的效果則並無特別限制，可適用公知的發光材料。發光材料雖可為螢光發光材料或磷光發光材料，但以發光效率良好的材料較佳，從內部量子效率的觀點考量以磷光發光材料較佳。The material of the light-emitting layer 92 is not particularly limited as long as it emits light at a desired light-emitting wavelength and does not impair the effects of the present invention, and a known light-emitting material can be applied. Although the luminescent material may be a fluorescent luminescent material or a phosphorescent luminescent material, a material having good luminescence efficiency is preferable, and a phosphorescent luminescent material is preferable from the viewpoint of internal quantum efficiency.
作為賦予藍色發光的發光材料，例如，可例舉萘、苝、芘、蒽、香豆素、對雙(2-苯基乙烯基)苯及該等之衍生物等。作為賦予綠色發光的發光材料，例如，可例舉喹吖酮衍生物、香豆素衍生物、Al(C9H6NO)3等鋁錯合物等。Examples of the light-emitting material that imparts blue light emission include naphthalene, anthracene, anthracene, anthracene, coumarin, p-bis(2-phenylvinyl)benzene, and the like. Examples of the light-emitting material that imparts green light emission include a quinophthalone derivative, a coumarin derivative, and an aluminum complex such as Al(C9 H6 NO)3 .
作為賦予紅色發光的發光材料，例如，可例舉DCM(4-(二氰基亞甲基)-2-甲基-6-(對二甲胺基苯乙烯)-4H-吡喃)系化合物、苯并吡喃衍生物、玫瑰紅衍生物、苯并硫衍生物、氮雜苯并硫等。As the luminescent material that imparts red light emission, for example, DCM (4-(dicyanomethylidene)-2-methyl-6-(p-dimethylaminostyrene)-4H-pyran) compound can be exemplified. a benzopyran derivative, a rose red derivative, a benzothiazepine derivative, an azabenzo sulfur, and the like.
構成上述的發光層92之有機EL層的構成或發光材料等係不受限於上述材料。The configuration of the organic EL layer constituting the above-described light-emitting layer 92, the light-emitting material, and the like are not limited to the above materials.
如圖9所示，發光層92被形成在電洞注入層91上，藉由施加在上部電極87與下部電極88之間的驅動電壓而被驅動。As shown in FIG. 9, the light-emitting layer 92 is formed on the hole injection layer 91, and is driven by a driving voltage applied between the upper electrode 87 and the lower electrode 88.
下部電極88係具有將反射層以導電性金屬氧化物層夾持的3層構造。此外，在上部電極87與下部電極88之間，除了發光層92以外，亦可插入電子注入層、電子輸送層、電洞輸送層等。The lower electrode 88 has a three-layer structure in which the reflective layer is sandwiched by a conductive metal oxide layer. Further, an electron injection layer, an electron transport layer, a hole transport layer, or the like may be inserted between the upper electrode 87 and the lower electrode 88 in addition to the light-emitting layer 92.
電洞注入層91可使用氧化鎢或氧化鉬等之高融點金屬氧化物。反射層可適用光反射率高的銀合金、鋁合金等。此外，ITO等之導電性金屬氧化物和鋁之密接性不佳。電極或接觸孔等之界面是例如ITO和鋁合金之情況容易發生電連接不良。銀或銀合金係與ITO等之導電性金屬氧化物之密接性良好，且ITO等之導電性金屬氧化物容易獲得歐姆接觸。The hole injection layer 91 can use a high melting point metal oxide such as tungsten oxide or molybdenum oxide. The reflective layer can be applied to a silver alloy or an aluminum alloy having a high light reflectance. Further, the adhesion between the conductive metal oxide such as ITO and aluminum is not good. When the interface of the electrode or the contact hole or the like is, for example, ITO and an aluminum alloy, electrical connection failure is likely to occur. The silver or silver alloy is excellent in adhesion to a conductive metal oxide such as ITO, and the conductive metal oxide such as ITO is easily ohmic-contacted.
其次，參照圖9，針對顯示裝置DSP2中連接於下部電極88(畫素電極)的主動元件68之構造作說明。Next, a configuration of the active element 68 connected to the lower electrode 88 (pixel electrode) in the display device DSP2 will be described with reference to FIG.
圖9係顯示採用有頂閘極構造的薄膜電晶體(TFT)的構造，作為主動元件68的一例。此外，圖9中，為簡化說明，省略顯示裝置基板400及密封層109。Fig. 9 shows a configuration of a thin film transistor (TFT) using a top gate structure as an example of the active element 68. In FIG. 9, the display device substrate 400 and the sealing layer 109 are omitted for simplification of description.
閘極電極95和閘極配線(導電配線、第2導電配線)就電性而言有協作關係，驅動主動元件68。第2實施形態中，第1接觸感測配線3(導電配線、第1導電配線)、第2接觸感測配線2(導電配線、第3導電配線)，及閘極配線(導電配線、第2導電配線)係具有藉第1導電性金屬氧化物層6和第2導電性金屬氧化物層4夾持銅合金層5之構成。又，針對導電配線中的材料組成亦是，第2實施形態和第1實施形態相同。The gate electrode 95 and the gate wiring (the conductive wiring and the second conductive wiring) have a cooperative relationship in terms of electrical properties, and drive the active device 68. In the second embodiment, the first contact sensing wiring 3 (conductive wiring, first conductive wiring), second contact sensing wiring 2 (conductive wiring, third conductive wiring), and gate wiring (conductive wiring, second The conductive wiring) has a configuration in which the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4. Further, the material composition in the conductive wiring is also the same as that in the first embodiment.
通道層58係以和第1實施形態相同的氧化銦、氧化銻、氧化鎵的氧化物半導體所構成。具體言之，關於形成第2實施形態的薄膜電晶體所具備的通道層之氧化物半導體，金屬元素的原子比(未計數氧之原子比)設為In：Ga：Sb=1：1：1。氧化物半導體中的氧化銻可取代成氧化鋅。The channel layer 58 is made of an oxide semiconductor of indium oxide, antimony oxide or gallium oxide which is the same as that of the first embodiment. Specifically, in the oxide semiconductor in which the channel layer included in the thin film transistor of the second embodiment is formed, the atomic ratio of the metal element (atomic ratio of uncounted oxygen) is set to In:Ga:Sb=1:1:1 . Cerium oxide in an oxide semiconductor can be substituted into zinc oxide.
本實施形態中，針對使用有機EL發光層作為功能裝置的情況作說明，但也可使用微發光二極體取代有機EL發光層。在以薄膜電晶體驅動有機EL發光層或微發光二極體的情況，薄膜電晶體的Vth(閾值電壓)均一是必要的。使用多晶矽半導體作為薄膜電晶體的通道層之電晶體由於電晶體的Vth之偏差大，所以在被要求驅動電壓高且均一性的有機EL發光層或微發光二極體的驅動上並不適合。具備以氧化物半導體形成的通道層之薄膜電晶體係Vth的偏差小，適合於有機EL發光層或微發光二極體之驅動。In the present embodiment, a case where an organic EL light-emitting layer is used as a functional device will be described, but a micro light-emitting diode may be used instead of the organic EL light-emitting layer. In the case where the organic EL light-emitting layer or the micro-light-emitting diode is driven by a thin film transistor, uniformity of Vth (threshold voltage) of the thin film transistor is necessary. A transistor using a polycrystalline germanium semiconductor as a channel layer of a thin film transistor is not suitable for driving of an organic EL light-emitting layer or a micro-light-emitting diode which is required to have a high driving voltage and uniformity because of a large variation in Vth of the transistor. The thin film electrowinning system Vth having a channel layer formed of an oxide semiconductor has a small variation and is suitable for driving an organic EL light-emitting layer or a micro-light-emitting diode.
利用備有以氧化物半導體形成的通道層之薄膜電晶體所進行的有機EL或LED之驅動，係比利用備有以多晶矽半導體形成的通道層之薄膜電晶體所進行的驅動還好。The driving of the organic EL or the LED by the thin film transistor provided with the channel layer formed of the oxide semiconductor is better than the driving using the thin film transistor provided with the channel layer formed of the polycrystalline semiconductor.
例如，稱為IGZO的氧化物半導體係以濺鍍等之真空成膜一次形成。於氧化物半導體被成膜後，TFT等之圖案形成後的熱處理亦匯總地進行。因此，有關通道層的電氣的特性(例如，Vth)的偏差極少。有機EL或LED之驅動係抑制其亮度的偏差，故有必要將前述薄膜電晶體之Vth的偏差抑制在小範圍。For example, an oxide semiconductor called IGZO is formed by vacuum deposition at a time such as sputtering. After the oxide semiconductor is formed into a film, heat treatment after pattern formation of a TFT or the like is also performed collectively. Therefore, the relevant channel layerThe electrical characteristics (eg, Vth) are extremely small. Since the driving of the organic EL or the LED suppresses variations in luminance, it is necessary to suppress the variation in Vth of the thin film transistor to a small range.
一方面，關於備有以多晶矽半導體形成的通道層之薄膜電晶體，需將薄膜電晶體的前驅物、即非結晶矽於電晶體各個上施以雷射退火，各個的雷射退火會招致薄膜電晶體的Vth的偏差。就此觀點，被使用於具備有機EL或LED的顯示裝置之薄膜電晶體，係以具備以氧化物半導體形成的通道層之薄膜電晶體較佳。On the one hand, regarding a thin film transistor provided with a channel layer formed of a polycrystalline germanium semiconductor, a precursor of the thin film transistor, that is, an amorphous crystal, is required to be subjected to laser annealing on each of the transistors, and each of the laser annealing causes a film. The deviation of the Vth of the transistor. From this point of view, a thin film transistor used for a display device including an organic EL or an LED is preferably a thin film transistor having a channel layer formed of an oxide semiconductor.
又，備有以氧化物半導體形成的通道層之薄膜電晶體，由於漏電流極少，所以在掃描信號或映像信號輸入後之穩定性高。備有以多晶矽半導體形成的通道層之薄膜電晶體與氧化物半導體的電晶體相較下，漏電流大了2位數以上。該漏電流少係與高精度的接觸感測相關連，是好的。Further, a thin film transistor having a channel layer formed of an oxide semiconductor has high leakage current, and therefore has high stability after input of a scanning signal or a video signal. A thin film transistor having a channel layer formed of a polycrystalline germanium semiconductor has a larger leakage current than a transistor of an oxide semiconductor. This small leakage current is associated with high-accuracy contact sensing and is good.
通道層58的材料方面，例如，可使用稱為IGZO的氧化物半導體。在構成通道層58的氧化物半導體的材料方面，可使用包含含有一種以上選自鎵、銦、鋅、錫、鋁、鍺及鈰所構成的群之金屬氧化物及含有銻及鉍中至少任一種的金屬氧化物之材料。As the material aspect of the channel layer 58, for example, an oxide semiconductor called IGZO can be used. In the material of the oxide semiconductor constituting the channel layer 58, a metal oxide containing a group of one or more selected from the group consisting of gallium, indium, zinc, tin, aluminum, antimony and bismuth, and at least any of cerium and lanthanum may be used. A material of a metal oxide.
本實施形態中，將含有氧化銦、氧化鎵、氧化銻等之氧化物半導體使用於通道層。以氧化物半導體形成的通道層58之材料亦可為單結晶、多結晶、微結晶、微結晶與非結晶之混合體、或非結晶中任一者。關於形成通道層的氧化物半導體，亦可於通道層的厚度方向形成載體遷移率相異的複數層的氧化物半導體。作為氧化物半導體的膜厚，可設為2nm~50nm的範圍內的膜厚。通道層58亦可以多晶矽半導體形成。In the present embodiment, an oxide semiconductor containing indium oxide, gallium oxide, or antimony oxide is used for the channel layer. The material of the channel layer 58 formed of an oxide semiconductor may be any of a single crystal, a polycrystal, a microcrystal, a mixture of microcrystals and non-crystals, or a non-crystal. Regarding the oxide semiconductor forming the channel layer, a plurality of oxide semiconductors having different carrier mobilitys may be formed in the thickness direction of the channel layer. The film thickness of the oxide semiconductor can be set to be in the range of 2 nm to 50 nm. Channel layer 58 can also be formed of a polysilicon semiconductor.
再者，亦可採用積層了2個薄膜電晶體的構造。作為一例，亦可使用具備以多晶矽半導體形成的通道層之薄膜電晶體作為位於下層的薄膜電晶體。使用具備以氧化物半導體形成的通道層之薄膜電晶體作為位於上層的薄膜電晶體。在積層有此種2個薄膜電晶體的構造中，平面視圖中，薄膜電晶體被配置成矩陣狀。關於此構造，藉多晶矽半導體可獲得高的遷移率，藉氧化物半導體可實現低漏電流。亦即，可同時活用多晶矽半導體和氧化物半導體雙方的益處。Further, a structure in which two thin film transistors are laminated may be employed. As an example, a thin film transistor having a channel layer formed of a polycrystalline germanium semiconductor may be used as the thin film transistor located under the layer. A thin film transistor having a channel layer formed of an oxide semiconductor is used as the thin film transistor located in the upper layer. In the structure in which such two thin film transistors are laminated, the thin film transistors are arranged in a matrix shape in plan view. With regard to this configuration, high mobility can be obtained by the polysilicon semiconductor, and low leakage current can be realized by the oxide semiconductor. That is, the benefits of both the polycrystalline germanium semiconductor and the oxide semiconductor can be utilized at the same time.
作為另一例，亦可在顯示裝置基板400與陣列基板500對向的面，於顯示裝置基板400及陣列基板500各自上形成薄膜電晶體。這時，各薄膜電晶體可具備以氧化物半導體形成的通道層。As another example, a thin film transistor may be formed on each of the display device substrate 400 and the array substrate 500 on the surface of the display device substrate 400 facing the array substrate 500. At this time, each of the thin film transistors may be provided with a channel layer formed of an oxide semiconductor.
氧化物半導體或多晶矽半導體可使用於例如，具有p/n接合的互補型電晶體的構成，或僅具有n型接合的單通道型電晶體的構成。作為氧化物半導體的積層構造，例如，亦可採用積層有n型氧化物半導體及與此n型氧化物半導體之電氣特性相異的n型氧化物半導體之積層構造。積層的n型氧化物半導體亦可用複數層來構成。在積層的n型氧化物半導體中，可使基底的n型半導體之帶隙與位在上層的n型半導體之帶隙相異。An oxide semiconductor or a polycrystalline germanium semiconductor can be used for, for example, a configuration of a complementary transistor having p/n junction, or a single having only n-type bondingThe composition of the channel type transistor. As the laminated structure of the oxide semiconductor, for example, a laminated structure in which an n-type oxide semiconductor and an n-type oxide semiconductor having electrical characteristics different from those of the n-type oxide semiconductor are laminated may be employed. The laminated n-type oxide semiconductor can also be formed by a plurality of layers. In the laminated n-type oxide semiconductor, the band gap of the n-type semiconductor of the substrate can be made different from the band gap of the n-type semiconductor located in the upper layer.
亦可採用通道層的上面例如以相異的氧化物半導體覆蓋的構成。亦可採用積層有載體遷移率、載體濃度互異的複數個氧化物半導體之多層構成。或，亦可採用例如在結晶性的n型氧化物半導體上積層有微結晶(接近非晶質)的氧化物半導體之積層構成。此處所謂的微結晶係指，例如，將以濺鍍裝置成膜的非晶質氧化物半導體在200℃以上且450℃以下的範圍熱處理後的微結晶狀的氧化物半導體膜。或是將成膜時的基板溫度設定在200℃左右的狀態下所成膜之微結晶狀的氧化物半導體膜。微結晶狀的氧化物半導體膜係為可藉由TEM等之觀察方法觀察至少1nm至3nm左右，或大於3nm的結晶粒之氧化物半導體膜。It is also possible to adopt a configuration in which the upper surface of the channel layer is covered with a different oxide semiconductor, for example. It is also possible to use a multilayer of a plurality of oxide semiconductors having a carrier mobility and a different carrier concentration. Alternatively, for example, a laminated structure of an oxide semiconductor in which a microcrystalline (near amorphous) layer is laminated on a crystalline n-type oxide semiconductor may be employed. The microcrystalline crystal film is a microcrystalline oxide semiconductor film obtained by heat-treating an amorphous oxide semiconductor formed by a sputtering apparatus in a range of 200° C. or higher and 450° C. or lower. Or a microcrystalline oxide semiconductor film formed by setting the substrate temperature at the time of film formation to about 200 °C. The microcrystalline oxide semiconductor film is an oxide semiconductor film which can observe crystal grains of at least about 1 nm to 3 nm or more than 3 nm by an observation method such as TEM.
氧化物半導體藉由從非晶質變化成結晶質，可實現改善載體遷移率、提升可靠性。作為氧化銦、氧化鎵的氧化物之融點高。氧化銻(Sb2O3)、氧化鉍(Bi2O3)的融點均為1000℃以下且氧化物的融點低。例如，在採用氧化銦(In2O3)與氧化鎵(Ga2O3)以及氧化銻的3元系複合氧化物之情況，因為融點低的氧化銻之效果，可降低此複合氧化物的結晶化溫度。換言之，可提供從非晶質狀態容易結晶化成微結晶狀態等之氧化物半導體。氧化物半導體藉由提高其結晶性，可使載體遷移率提升。The oxide semiconductor can be improved in carrier mobility and improved in reliability by changing from amorphous to crystalline. The melting point of the oxide of indium oxide or gallium oxide is high. The melting point of bismuth oxide (Sb2 O3 ) and bismuth oxide (Bi2 O3 ) is 1000 ° C or less and the melting point of the oxide is low. For example, in the case of using a ternary composite oxide of indium oxide (In2 O3 ) and gallium oxide (Ga2 O3 ) and cerium oxide, the composite oxide can be lowered because of the effect of low melting point of cerium oxide. Crystallization temperature. In other words, an oxide semiconductor which is easily crystallized from an amorphous state to a microcrystalline state or the like can be provided. The oxide semiconductor can increase the carrier mobility by increasing its crystallinity.
本發明實施形態涉及之上述的氧化物半導體，係在從室溫(例如，25℃)到小於200℃的基板溫度進行成膜，在通道層的圖案形成後之後工程，例如藉由250℃~350℃的低溫退火也可改善電氣特性。於薄膜電晶體形成後，連同第2導電配線一起退火，在省略工程的觀點是簡便的。又，本發明實施形態涉及的氧化物半導體或導電配線係相對於基底層(氧化矽等之絕緣層)或玻璃基板具有極強固的密接性。The above-described oxide semiconductor according to the embodiment of the present invention is formed by forming a film from a room temperature (for example, 25 ° C) to a substrate temperature of less than 200 ° C, and after the formation of the pattern of the channel layer, for example, by 250 ° C. Low temperature annealing at 350 °C also improves electrical characteristics. After the formation of the thin film transistor, annealing together with the second conductive wiring is simple in terms of omitting engineering. Moreover, the oxide semiconductor or the conductive wiring according to the embodiment of the present invention has extremely strong adhesion to the underlying layer (insulating layer such as yttrium oxide) or the glass substrate.
由於在後工程的濕式蝕刻中，氧化物半導體被要求易溶性，故可使用富氧化鋅、氧化鎵或氧化銻的複合氧化物。例如，在使用於濺鍍的金屬氧化物靶材之金屬元素的原子比(未計數氧之原子比)方面，可例示In：Ga：Sb=1：2：2，In：Ga：Sb=1：3：3，In：Ga：Sb=2：1：1，或In：Ga：Sb=1：1：1。此處Sb可取代成例如Zn(鋅)或Bi(鉍)。以下，有時將氧化銦、氧化銻及氧化鎵的複合氧化物稱為IAGO。Since the oxide semiconductor is required to be easily soluble in the wet etching of the post-engineering, a composite oxide rich in zinc oxide, gallium oxide or cerium oxide can be used. For example, in the atomic ratio of the metal element used for the sputtered metal oxide target (the atomic ratio of uncounted oxygen), In:Ga:Sb=1:2:2, In:Ga:Sb=1 can be exemplified :3:3, In:Ga:Sb=2:1:1, or In:Ga:Sb=1:1:1. Here, Sb may be substituted with, for example, Zn (zinc) or Bi (ruthenium). Hereinafter, a composite oxide of indium oxide, cerium oxide, and gallium oxide is sometimes referred to as IAGO.
又，以In：Sb=1：1的原子比設為氧化銦及氧化銻的2元系複合氧化物亦可。例如，以In：Bi=1：1的原子比設為氧化銦及氧化鉍的2元系複合氧化物亦可。又，亦可於上述原子比中，進一步增加In的含量。Further, an atomic ratio of In:Sb=1:1 may be used as a ternary composite oxide of indium oxide and cerium oxide. For example, the original with In:Bi=1:1The sub-ratio can also be a ternary composite oxide of indium oxide and antimony oxide. Further, the content of In may be further increased in the above atomic ratio.
例如，亦可於上述的複合氧化物再添加Sn。這時，能獲得包含含有In2O3、Ga2O3、Sb2O3及SnO2的4元系的組成之複合氧化物，或能獲得包含含有In2O3、Sb2O3及SnO2的3元系的組成之複合氧化物，成為可調整載體濃度。與In2O3、Ga2O3、Sb2O3、Bi2O3不同價數的SnO2係實現載體摻雜物的角色。For example, Sn may be further added to the above composite oxide. In this case, a composite oxide containing a composition of a quaternary system containing In2 O3 , Ga2 O3 , Sb2 O3 , and SnO2 can be obtained, or a composition containing In2 O3 , Sb2 O3 , and SnO can be obtained. The composite oxide of the composition of the ternary system of2 is an adjustable carrier concentration. The SnO2 system having a different valence from In2 O3 , Ga2 O3 , Sb2 O3 , and Bi2 O3 realizes the role of the carrier dopant.
此外，複合氧化物的組成未受上述組成所限定。Further, the composition of the composite oxide is not limited by the above composition.
例如，使用於含有氧化銦、氧化鎵及氧化銻的3元系金屬氧化物添加氧化錫所獲得之靶材來進行濺鍍成膜。藉此，可成膜載體濃度提升的複合氧化物。同樣地，例如，藉由使用於含有氧化銦、氧化鎵、氧化鉍的3元系金屬氧化物添加氧化錫所獲得之靶材來進行濺鍍成膜，可成膜載體濃度提升的複合氧化物。For example, a target obtained by adding tin oxide to a ternary metal oxide containing indium oxide, gallium oxide or cerium oxide is used for sputtering to form a film. Thereby, a composite oxide having an increased carrier concentration can be formed. Similarly, for example, by sputtering a film using a target obtained by adding tin oxide to a ternary metal oxide containing indium oxide, gallium oxide or cerium oxide, a composite oxide having a increased carrier concentration can be formed. .
但是，當載體濃度過高時，具有以複合氧化物形成的通道層之電晶體的閾值Vth容易變負(容易變常開)。因此，以調整氧化錫添加量使載體濃度成為小於1×1018cm-3較理想。又，針對載體濃度或載體遷移率，藉由調整上述複合氧化物之成膜條件(用於導入氣體的氧氣、基板溫度、成膜率等)、成膜後之退火條件及複合氧化物的組成等，可獲得所期望的載體濃度或載體遷移率。例如，提高氧化銦的組成比係容易提升載體遷移率。例如，藉由在200℃到700℃的溫度條件下進行熱處理之退火工程，促進上述複合氧化物的結晶化，可使複合氧化物的載體遷移率提升。However, when the carrier concentration is too high, the threshold Vth of the transistor having the channel layer formed of the composite oxide tends to become negative (easy to become normally open). Therefore, it is preferable to adjust the amount of the tin oxide added so that the carrier concentration becomes less than 1 × 1018 cm-3 . Further, the film formation conditions (oxygen used for introducing the gas, substrate temperature, film formation rate, etc.), annealing conditions after film formation, and composition of the composite oxide are adjusted for the carrier concentration or the carrier mobility. Etc., the desired carrier concentration or carrier mobility can be obtained. For example, increasing the composition ratio of indium oxide tends to increase the carrier mobility. For example, by annealing the above-mentioned composite oxide by annealing at a temperature of 200 ° C to 700 ° C, the carrier mobility of the composite oxide can be improved.
再者，亦能以於同一畫素上各配設一個具有以n型氧化物半導體形成的通道層之薄膜電晶體(主動元件)及具有以n型矽半導體形成的通道層之薄膜電晶體(主動元件)，活用薄膜電晶體的各個通道層之特性的方式，驅動LED或有機EL(OLED)這樣的發光層。在使用液晶層或有機EL(OLED)作為顯示功能層的情況，可採用n型多晶矽薄膜電晶體作為向發光層施加電壓(電流)的驅動電晶體，可採用n型氧化物半導體的薄膜電晶體作為向此多晶矽薄膜電晶體傳送信號的切換電晶體。Furthermore, a thin film transistor (active device) having a channel layer formed of an n-type oxide semiconductor and a thin film transistor having a channel layer formed of an n-type germanium semiconductor can be disposed on the same pixel ( The active element) drives a light-emitting layer such as an LED or an organic EL (OLED) in a manner that utilizes the characteristics of each channel layer of the thin film transistor. In the case where a liquid crystal layer or an organic EL (OLED) is used as the display functional layer, an n-type polycrystalline germanium thin film transistor can be employed as a driving transistor for applying a voltage (current) to the light emitting layer, and a thin film transistor of an n-type oxide semiconductor can be employed. As a switching transistor that transmits a signal to the polysilicon thin film transistor.
依據上述的第2實施形態，可獲得和第1實施形態同樣的效果並能實現備有以有機EL元件構成的發光層之顯示裝置DSP2。According to the second embodiment described above, the display device DSP2 provided with the light-emitting layer composed of the organic EL element can be obtained by the same effects as those of the first embodiment.
上述第2實施形態中，針對作為驅動裝置，發光層92是被形成於陣列基板500(第2基板)的構成作了說明。驅動裝置不僅形成於陣列基板500，亦可形成於顯示裝置基板400(第1基板)。這時，亦可於顯示裝置基板400及陣列基板500每一者形成驅動裝置，以形成有驅動裝置的面成為對向的方式將顯示裝置基板400及陣列基板500貼合。如此用以供給施加於形成於2個基板上的驅動裝置的電氣信號之第2導電配線，係可形成於2個基板每一者。藉由形成於顯示裝置基板400上的驅動裝置，可對導電配線、即接觸配線施加接觸驅動電壓。驅動裝置可設為具備以氧化物半導體形成的通道層之薄膜電晶體。這時亦可獲得和上述的實施形態同樣的效果。In the second embodiment, the configuration in which the light-emitting layer 92 is formed on the array substrate 500 (second substrate) as the driving device will be described. The driving device is formed not only on the array substrate 500 but also on the display device substrate 400 (first substrate). At this time, a driving device may be formed on each of the display device substrate 400 and the array substrate 500, and the display device substrate 400 and the array may be formed such that the surface on which the driving device is formed is opposed.The substrate 500 is attached. The second conductive wiring for supplying an electric signal applied to the driving devices formed on the two substrates can be formed on each of the two substrates. The contact driving voltage can be applied to the conductive wiring, that is, the contact wiring, by the driving device formed on the display device substrate 400. The driving device can be a thin film transistor including a channel layer formed of an oxide semiconductor. Also in this case, the same effects as those of the above embodiment can be obtained.
此外，上述實施形態中說明了採用有機電致發光層(有機EL)作為發光層92的構造。發光層92亦可為無機的發光二極體層。又，發光層92亦可為具有無機的LED晶片被排列成矩陣狀的構造。這時，亦可將紅色發光、綠色發光、藍色發光各個微小的LED晶片安裝於陣列基板500上。關於LED晶片封裝於陣列基板500的方法，亦可進行倒裝(face-down)封裝。亦即，發光二極體層(功能裝置)係設於和顯示裝置基板400對向之前述陣列基板500的面。Further, in the above embodiment, the structure in which the organic electroluminescent layer (organic EL) is used as the light-emitting layer 92 has been described. The luminescent layer 92 can also be an inorganic luminescent diode layer. Further, the light-emitting layer 92 may have a structure in which inorganic LED chips are arranged in a matrix. At this time, each of the minute LED chips of red light emission, green light emission, and blue light emission may be mounted on the array substrate 500. Regarding the method of packaging the LED chip on the array substrate 500, a face-down package can also be performed. That is, the light-emitting diode layer (functional device) is provided on the surface of the array substrate 500 facing the display device substrate 400.
在發光層92是以無機LED所構成的情況，將作為發光層92的藍色發光二極體或藍紫色發光二極體配設於陣列基板500(基板45)。形成氮化物半導體層和上部電極之後，於綠色畫素積層綠色螢光體，於紅色發光的畫素積層紅色螢光體。藉此，可於陣列基板500簡便地形成無機LED。在使用此種螢光體的情況，藉由從藍紫色發光二極體產生的藍色光之激發，從綠色螢光體及紅色螢光體分別可獲得綠色發光及紅色發光。When the light-emitting layer 92 is composed of an inorganic LED, a blue light-emitting diode or a blue-violet light-emitting diode as the light-emitting layer 92 is disposed on the array substrate 500 (substrate 45). After the formation of the nitride semiconductor layer and the upper electrode, a green phosphor is laminated on the green pixel, and a red phosphor is laminated on the red-emitting pixel. Thereby, the inorganic LED can be easily formed on the array substrate 500. In the case of using such a phosphor, green light emission and red light emission can be obtained from the green phosphor and the red phosphor, respectively, by excitation of blue light generated from the blue-violet light-emitting diode.
或者，亦可將作為發光層92的紫外發光二極體配設於陣列基板500(基板45)。這時，形成氮化物半導體層和上部電極之後，於藍色畫素積層藍色螢光體，於綠色畫素積層綠色螢光體，於紅色畫素積層紅色螢光體。藉此，可於陣列基板500簡便地形成無機LED。在使用此種螢光體的情況，例如，可以印刷法等之簡便手法，形成綠色畫素、紅色畫素或藍色畫素。此等畫素，從各色的發光效率或色平衡的觀點考量，以調整畫素的大小者較理想。Alternatively, the ultraviolet light emitting diode as the light emitting layer 92 may be disposed on the array substrate 500 (substrate 45). At this time, after the nitride semiconductor layer and the upper electrode are formed, a blue phosphor is laminated on the blue pixel, a green phosphor is laminated on the green pixel, and a red phosphor is laminated on the red pixel. Thereby, the inorganic LED can be easily formed on the array substrate 500. In the case of using such a phosphor, for example, a green pixel, a red pixel or a blue pixel can be formed by a simple method such as a printing method. These pixels are considered from the viewpoint of luminous efficiency or color balance of each color, and it is preferable to adjust the size of the pixels.
上述的實施形態中，檢測在第1接觸感測配線3(第1導電配線)與第2接觸感測配線2(第3導電配線)之間產生的靜電電容之變化，進行接觸感測。例如，也可將第1接觸感測配線3及第2接觸感測配線2當中之一導電配線用於RFID(IC卡等)的讀取器。In the above-described embodiment, the change in electrostatic capacitance generated between the first contact sense line 3 (first conductive line) and the second contact sense line 2 (third conductive line) is detected, and contact sensing is performed. For example, one of the first contact sensing wires 3 and the second contact sensing wires 2 may be used for a reader of an RFID (such as an IC card).
接觸驅動的頻率為數KHz，用於RFID的頻率為13.56MHz，頻率不同。例如，亦可將從接觸驅動的頻率朝RFID的頻率切換之切換開關設於顯示裝置DSP2。或藉由以分時切換導電配線的驅動頻率等，可將顯示裝置DSP2作為RFID的讀取器使用。再者，電子支付系統或近距離通信系統能適用本發明實施形態的顯示裝置DSP2。切換開關亦可為顯示於顯示裝置DSP2的顯示畫面之畫像的一部分。The frequency of the contact drive is several KHz, and the frequency for the RFID is 13.56 MHz, and the frequency is different. For example, a switch that switches the frequency of the contact drive toward the frequency of the RFID may be provided to the display device DSP2. Alternatively, the display device DSP2 can be used as a reader of the RFID by switching the driving frequency of the conductive wiring or the like in a time division manner. Furthermore, the electronic payment system or the short-range communication system can be applied to the display device DSP2 of the embodiment of the present invention. The changeover switch may also be part of an image displayed on the display screen of the display device DSP2.
藉由調整導電配線的膜厚、線寬、圖案形狀等，可將RFID的讀取器的功能安裝於顯示裝置DSP2。此處，所謂圖案形狀係意味著對應所使用的頻率而調整例如單極、雙極、迴圈等之天線形狀。例如，為使RFID的讀取器的接收感度提升，亦可設成在剖面視圖中，於導電配線的下部隔有高介電常數的絕緣層之第4導電配線、第5導電配線等之積層構成。再者，亦可於陣列基板500上形成藉驅動裝置驅動的阻抗匹配電路(共振頻率的調整)，然後與設於顯示裝置基板400的天線進行電連接。此外，用於RFID的頻率亦可使用VHF或UHF等更高的頻率。The function of the RFID reader can be attached to the display device DSP2 by adjusting the film thickness, line width, pattern shape, and the like of the conductive wiring. Here, the pattern shape means that the antenna shape such as a monopole, a bipolar, or a loop is adjusted in accordance with the frequency to be used. For example, in order to improve the reception sensitivity of the reader of the RFID, it is also possible to provide a laminate of the fourth conductive wiring and the fifth conductive wiring having a high dielectric constant insulating layer in the lower portion of the conductive wiring in the cross-sectional view. Composition. Further, an impedance matching circuit (adjustment of resonance frequency) driven by the driving device may be formed on the array substrate 500, and then electrically connected to an antenna provided on the display device substrate 400. In addition, frequencies used for RFID can also use higher frequencies such as VHF or UHF.
依據上述的變形例，可獲得與第2實施形態同樣的效果，能於顯示裝置DSP2實現RFID的讀取器之功能。According to the above-described modification, the same effects as those of the second embodiment can be obtained, and the function of the RFID reader can be realized in the display device DSP2.
以下，一邊參照圖面一邊針對本發明第3實施形態作說明。Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
第3實施形態中，對和第1實施形態及第2實施形態相同構件賦予同一符號，且省略或簡化其說明。In the third embodiment, the same members as those in the first embodiment and the second embodiment are denoted by the same reference numerals, and their description will be omitted or simplified.
圖10係將本發明第3實施形態的顯示裝置DSP3作一部分顯示的剖面圖。圖11係將構成本發明第3實施形態的顯示裝置DSP3之顯示裝置基板600作一部分顯示的剖面圖，為放大顯示符號P所示之接觸感測配線(第1導電配線)的放大剖面圖。圖12係將構成本發明第3實施形態的顯示裝置之陣列基板700作一部分顯示的平面圖，為沿著圖10所示之D-D’線的圖。圖13係將本發明第3實施形態的顯示裝置作一部分顯示的剖面圖，為沿著圖12所示之E-E’線的圖。Fig. 10 is a cross-sectional view showing a portion of the display device DSP3 according to the third embodiment of the present invention. 11 is a cross-sectional view showing a part of the display device substrate 600 constituting the display device DSP3 according to the third embodiment of the present invention, and is a display of the contact sensing wiring shown by the symbol P (first).An enlarged cross-sectional view of the conductive wiring). Fig. 12 is a plan view showing a part of the array substrate 700 constituting the display device of the third embodiment of the present invention, taken along the line D-D' shown in Fig. 10. Fig. 13 is a cross-sectional view showing a portion of the display device according to the third embodiment of the present invention, taken along the line E-E' shown in Fig. 12.
第3實施形態中，功能裝置係液晶層，驅動裝置係薄膜電晶體(主動元件)。In the third embodiment, the functional device is a liquid crystal layer, and the driving device is a thin film transistor (active device).
如圖10~圖12所示，第3實施形態的顯示裝置DSP3具有：顯示裝置基板600(第1基板)；陣列基板700(第2基板)；及配置在顯示裝置基板600與陣列基板700之間的液晶層800。As shown in FIG. 10 to FIG. 12, the display device DSP3 of the third embodiment includes a display device substrate 600 (first substrate), an array substrate 700 (second substrate), and a display device substrate 600 and an array substrate 700. A liquid crystal layer 800 between.
顯示裝置基板600備有透明基板65(基板本體)、及配置在透明基板65上的第1接觸感測配線611。陣列基板700備有透明基板62、第2接觸感測配線774(導電配線、第3導電配線)、及源極配線66(導電配線、第2導電配線)。顯示裝置基板600及陣列基板700係隔著液晶層800被貼合。The display device substrate 600 includes a transparent substrate 65 (substrate body) and a first contact sensing wiring 611 disposed on the transparent substrate 65. The array substrate 700 includes a transparent substrate 62, a second contact sensing wiring 774 (conductive wiring, third conductive wiring), and a source wiring 66 (conductive wiring, second conductive wiring). The display device substrate 600 and the array substrate 700 are bonded together via the liquid crystal layer 800.
如圖10及圖11所示，顯示裝置基板600具備夾持第1接觸感測配線611(導電配線、第1導電配線)的第1光吸收層604及第2光吸收層605。第1光吸收層604係為提升觀察者觀察顯示裝置DSP3的顯示面之際的視認性而設。第2光吸收層605係為了抑制從背光單元(未圖示)產生之再反射光或在顯示部110內部傳遞的反射光射入薄膜電晶體的開口部、減低與映像顯示有關的雜訊而形成。此外，濾光片51(RGB)亦可從顯示裝置基板600省略。As shown in FIG. 10 and FIG. 11 , the display device substrate 600 includes a first light absorbing layer 604 and a second light absorbing layer 605 that sandwich the first contact sensing wires 611 (conductive wires and first conductive wires). The first light absorbing layer 604 is provided to enhance the visibility of the viewer when viewing the display surface of the display device DSP3. The second light absorbing layer 605 is for suppressing re-reflected light generated from a backlight unit (not shown) or reflected light transmitted inside the display unit 110.It is formed by injecting into the opening of the thin film transistor and reducing noise associated with the image display. Further, the filter 51 (RGB) may be omitted from the display device substrate 600.
第3實施形態的第1接觸感測配線611與第2接觸感測配線774在平面視圖中正交，可用作為接觸感測中的檢測配線或驅動配線。第2接觸感測配線774在平面視圖中和閘極配線75平行，源極配線66擔任映像信號線、即源極配線的角色。The first contact sensing wiring 611 and the second contact sensing wiring 774 of the third embodiment are orthogonal to each other in plan view, and can be used as detection wiring or driving wiring in contact sensing. The second contact sensing wiring 774 is parallel to the gate wiring 75 in plan view, and the source wiring 66 functions as a signal signal line, that is, a source wiring.
液晶層800係水平配向的液晶，被在陣列基板700上的畫素電極71與共通電極72之間產生的邊緣電場所驅動。圖10中，省略配向膜、偏光板等光學膜之圖示。The liquid crystal layer 800 is a horizontally aligned liquid crystal that is driven by an edge electric field generated between the pixel electrode 71 on the array substrate 700 and the common electrode 72. In Fig. 10, illustration of an optical film such as an alignment film or a polarizing plate is omitted.
圖13中，藉由檢測在位於紙面深處的第1接觸感測配線611(以虛線表示)與配設在陣列基板700的絕緣層723上之第2接觸感測配線774之間的靜電電容C3之變化以進行接觸感測。第1接觸感測配線611與第2接觸感測配線774係在從觀察者所見的平面視圖中正交。In FIG. 13, the electrostatic capacitance between the first contact sensing wiring 611 (shown by a broken line) located deep in the paper surface and the second contact sensing wiring 774 disposed on the insulating layer 723 of the array substrate 700 is detected. The change in C3 is for contact sensing. The first contact sensing wiring 611 and the second contact sensing wiring 774 are orthogonal to each other in a plan view seen from an observer.
如圖12所示，畫素電極71係延伸於X軸方向且按各畫素作配設。如圖13所示，畫素電極71係設於絕緣層723上，配設在與液晶層800對向的陣列基板700的面。As shown in FIG. 12, the pixel electrode 71 extends in the X-axis direction and is arranged for each pixel. As shown in FIG. 13, the pixel electrode 71 is provided on the insulating layer 723, and is disposed on the surface of the array substrate 700 opposed to the liquid crystal layer 800.
於陣列基板700上，隔著絕緣層721配設對畫素電極71施加液晶驅動電壓的薄膜電晶體73(主動元件)。薄膜電晶體73具備閘極電極76、源極電極77、汲極電極78及通道層79。閘極電極76和閘極配線75就電性而言有協作關係。源極電極77和源極配線66就電性而言有協作關係。A thin film transistor 73 (active device) that applies a liquid crystal driving voltage to the pixel electrode 71 is disposed on the array substrate 700 via the insulating layer 721. thinThe membrane transistor 73 includes a gate electrode 76, a source electrode 77, a drain electrode 78, and a channel layer 79. The gate electrode 76 and the gate wiring 75 have a cooperative relationship in terms of electrical properties. The source electrode 77 and the source wiring 66 have a cooperative relationship in terms of electrical properties.
在Y方向延伸線的第2接觸感測配線774係與閘極配線75平行，配設於平面視圖中重疊的位置。在與Y方向正交的X方向延伸線之第1接觸感測配線611係和第2導電配線、即源極配線66平行，配設於平面視圖中重疊的位置。The second contact sensing wiring 774 extending in the Y direction is parallel to the gate wiring 75, and is disposed at a position overlapping in plan view. The first contact sensing wiring 611 in the X-direction extending line orthogonal to the Y direction is parallel to the second conductive wiring, that is, the source wiring 66, and is disposed at a position overlapping in plan view.
第1接觸感測配線611、源極配線66及第2接觸感測配線774分別具有銅合金層5被第1導電性金屬氧化物層6與第2導電性金屬氧化物層4夾持的構成。Each of the first contact-sensing wiring 611, the source wiring 66, and the second contact-sensing wiring 774 has a configuration in which the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4 .
第3實施形態中，銅合金層5係使用鈣3原子%、鋅0.6原子%及剩餘部份是銅的銅合金。銅合金層5的電阻係數係約3μΩcm。此外，銅合金層5的電阻係數係可因為銅合金層5的成膜方法或退火條件而有±30%左右之變化。就銅合金層5是被第1導電性金屬氧化物層6與第2導電性金屬氧化物層4夾持的構成而言，很多會因為熱處理(退火)而改善電阻係數。In the third embodiment, the copper alloy layer 5 is a copper alloy in which 3 atom% of calcium, 0.6 atom% of zinc, and the remainder are copper. The resistivity of the copper alloy layer 5 is about 3 μΩcm. Further, the electrical resistivity of the copper alloy layer 5 may vary by about ±30% due to the film formation method or annealing condition of the copper alloy layer 5. In the configuration in which the copper alloy layer 5 is sandwiched between the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4, the resistivity is often improved by heat treatment (annealing).
關於第3實施形態中第1導電性金屬氧化物層6及第2導電性金屬氧化物層4各個的組成，在未計數氧之元素的比例為鋅4原子%、銻4原子%、剩餘部份是銦。如上述，當鋅的添加量超過10原子%時，導電性金屬氧化物層的耐鹼性降低，故鋅的添加量以小於10原子%者較佳。In the composition of each of the first conductive metal oxide layer 6 and the second conductive metal oxide layer 4 in the third embodiment, the ratio of the element which does not count oxygen is 4 atom% of zinc, 4 atom% of 锑, and the remaining part. The part is indium.As described above, when the amount of zinc added exceeds 10 atom%, the alkali resistance of the conductive metal oxide layer is lowered, so that the amount of zinc added is preferably less than 10 atom%.
鋅和鎵及銻合計之添加量的上限係15原子%。雖然亦受電氣封裝之條件所左右，但是例如，當鋅和鎵及銻合計的添加量超過16原子%時，會有表面電阻變大，難以取得歐姆接觸之虞。The upper limit of the addition amount of zinc and gallium and lanthanum is 15 atom%. Although it is also subject to the conditions of electrical packaging, for example, when the addition amount of zinc, gallium, and antimony exceeds 16 atom%, the surface resistance becomes large, and it is difficult to obtain an ohmic contact.
鋅和鎵及銻合計之添加量的下限係0.2原子%。在此添加量小於0.2原子%的情況，在對導電性金屬氧化物層作退火處理等之熱處理中，氧化銦複合氧化物的晶粒容易異常成長，容易成為不穩定的導電性金屬氧化物層。The lower limit of the addition amount of zinc and gallium and bismuth is 0.2 atom%. When the amount of addition is less than 0.2 atomic%, in the heat treatment for annealing the conductive metal oxide layer, the crystal grains of the indium oxide composite oxide are likely to grow abnormally, and it is likely to become an unstable conductive metal oxide layer. .
關於形成第3實施形態的薄膜電晶體所具備的通道層之氧化物半導體，金屬元素的原子比(未計數氧之原子比)設為In：Ga：Sb=1：1：1。氧化物半導體中的氧化銻可取代成氧化鋅。閘極絕緣層係以氧化鈰形成。In the oxide semiconductor in which the channel layer included in the thin film transistor of the third embodiment is formed, the atomic ratio of the metal element (atomic ratio of uncounted oxygen) is set to In:Ga:Sb=1:1:1. Cerium oxide in an oxide semiconductor can be substituted into zinc oxide. The gate insulating layer is formed of yttrium oxide.
第3實施形態中，源極配線66是第2導電配線。第2導電配線係和第1實施形態或第2實施形態相同，為藉第1導電性金屬氧化物層和第2導電性金屬氧化物層夾持銅合金層的構成。源極電極77、汲極電極78係在形成源極配線66之相同的工程以和上述導電配線相同構成、材料形成。在該實施形態之導電配線係擔任將映像信號送至前述薄膜電晶體的角色。In the third embodiment, the source wiring 66 is a second conductive wiring. In the same manner as in the first embodiment or the second embodiment, the second conductive wiring has a configuration in which a copper alloy layer is sandwiched between the first conductive metal oxide layer and the second conductive metal oxide layer. The source electrode 77 and the drain electrode 78 are formed of the same material and material as the above-described conductive wiring in the same process of forming the source wiring 66. In the conductive wiring system of this embodiment, the image signal is sent to the thin film transistor.
在第1實施形態及第3實施形態的顯示裝置之主動矩陣驅動中，關於掃描信號線(閘極配線)，亦可每一畫素使用2條閘極配線。這時，例如，奇數行的掃描信號線與偶數行的掃描信號線被寫入相反極性的資料。亦可於某顯示期間，對鄰接之畫素的奇數列和偶數列分別寫入相反極性的資料，於下一顯示期間分別寫入和之前的顯示期間相反極性的資料(例如，特開平7-181927號公報所記載)。藉由採用此種配線構造、驅動方法，減少顯示裝置的消耗電力，且可減輕影響接觸感測的雜訊。In the active matrix driving of the display device according to the first embodiment and the third embodiment, two gate wirings may be used for each pixel in the scanning signal line (gate wiring). At this time, for example, the scanning signal lines of the odd rows and the scanning signal lines of the even rows are written with data of opposite polarities. It is also possible to write data of opposite polarity to the odd-numbered columns and the even-numbered columns of adjacent pixels during a certain display period, and to write data of opposite polarity to the previous display period in the next display period (for example, special open 7- Documented in 181927). By adopting such a wiring structure and a driving method, power consumption of the display device can be reduced, and noise that affects contact sensing can be reduced.
在將上述的液晶驅動方法適用於本發明的情況，關於任一方法，每一畫素的主動元件(TFT)的個數係1個以上、複數亦可。本發明可適用上述的液晶驅動技術。In the case where the liquid crystal driving method described above is applied to the present invention, the number of active elements (TFTs) per pixel may be one or more and plural in any of the methods. The present invention is applicable to the liquid crystal driving technique described above.
例如，上述實施形態的顯示裝置可進行各種應用。關於上述實施形態的顯示裝置可適用的電子機器，可例舉行動電話、行動式遊戲設備、行動資訊終端、個人電腦、電子書、錄影機、數位相機、頭戴式顯示器、導航系統、音響再生裝置(車載聲頻、數位聲頻播放器等)、複印機、傳真機、印表機、複合式印表機、自動販賣機、現金自動存提款機(ATM)、個人認證設備、光通信機器等。上述的各實施形態可自由組合使用。For example, the display device of the above embodiment can be used in various applications. The electronic device to which the display device according to the above embodiment can be applied can be, for example, a mobile phone, a mobile game device, a mobile information terminal, a personal computer, an electronic book, a video recorder, a digital camera, a head mounted display, a navigation system, and an audio reproduction. Devices (car audio, digital audio players, etc.), copiers, fax machines, printers, composite printers, vending machines, cash deposit and withdrawal machines (ATM), personal authentication devices, optical communication devices, etc. Each of the above embodiments can be used in combination.
說明本發明較佳實施形態，上述雖已作說明，但當應理解此等乃係本發明的例示，不應以限定者來作考量。追加、省略、置換及其他變更係可在不悖離本發明的範圍下進行。所以，本發明並不為前述說明所限定，而係受申請專利範圍所限。The preferred embodiments of the present invention have been described above, and the foregoing description of the present invention is intended to be construed as illustrative. Additions, omissions, substitutions, and other changes may be made without departing from the invention.Under the scope of the. Therefore, the invention is not limited by the foregoing description, but is limited by the scope of the claims.
| Application Number | Priority Date | Filing Date | Title |
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| TW106102318ATWI630534B (en) | 2017-01-23 | 2017-01-23 | Display device and display device substrate |
| Application Number | Priority Date | Filing Date | Title |
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| TW106102318ATWI630534B (en) | 2017-01-23 | 2017-01-23 | Display device and display device substrate |
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| TWI630534Btrue TWI630534B (en) | 2018-07-21 |
| TW201828009A TW201828009A (en) | 2018-08-01 |
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| TW106102318ATWI630534B (en) | 2017-01-23 | 2017-01-23 | Display device and display device substrate |
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