本發明是有關於一種記憶體裝置，且特別是有關於一種具有埋入式字元線的動態隨機存取記憶體。The present invention relates to a memory device, and more particularly to a dynamic random access memory having embedded word lines.
動態隨機存取記憶體屬於一種揮發性記憶體，其是由多個記憶胞構成。每一個記憶胞主要是由一個電晶體與一個由電晶體所操控的電容器所構成，且每一個記憶胞藉由字元線與位元線彼此電性連接。Dynamic random access memory is a kind of volatile memory, which is composed of a plurality of memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by a transistor, and each of the memory cells is electrically connected to each other by a word line and a bit line.
為提高動態隨機存取記憶體的積集度以加快元件的操作速度，以及符合消費者對於小型化電子裝置的需求，近年來發展出埋入式字元線動態隨機存取記憶體（buried word line DRAM），以滿足上述種種需求。In order to improve the accumulative degree of dynamic random access memory to speed up the operation speed of components and meet the needs of consumers for miniaturized electronic devices, buried word line dynamic random access memory (buried word) has been developed in recent years. Line DRAM) to meet the above needs.
目前採用的動態隨機存取記憶體的主流佈局為兩個記憶胞共用一個位元線接觸窗，而兩個記憶胞分別由兩條字元線控制。當其中一個記憶胞字元線開啟/關閉(on/off)以控制其中一個記憶胞時，與上述記憶胞共用同一個位元線接觸窗的另一個記憶胞容易被干擾。此一情況在記憶胞特徵尺寸微縮時(即當記憶胞與記憶胞之間的距離變得更近)，則干擾會更為嚴重。The mainstream layout of the currently used dynamic random access memory is that two memory cells share one bit line contact window, and two memory cells are controlled by two word lines. When one of the memory cell word lines is turned on/off to control one of the memory cells, another memory cell sharing the same bit line contact window with the above memory cells is susceptible to interference. In this case, when the memory cell feature size is reduced (i.e., when the distance between the memory cell and the memory cell becomes closer), the interference is more serious.
而且，由於字元線與字元線之間的間距僅有1特徵尺寸(Feature size)，因此將字元線要拉線到記憶胞陣列邊緣製作字元線拉出接觸窗時，容易在製程中發生字元線拉出接觸窗至字元線短路的問題。習知的一種作法會將兩相鄰字元線的距離於末端拉開，而呈現類似於Y形的結構，以增加接觸窗的製程裕度(process window)。然而此種作法必須額外佔用記憶胞陣列邊緣的面積導致晶片尺寸增加，且無法應用於字元線的兩端在記憶胞陣列邊緣均有拉出接觸窗的設計，而無法減少字元線斷線時的損失。Moreover, since the spacing between the word line and the word line has only one feature size, the word line is pulled to the edge of the memory cell array to make the word line pull out of the contact window, which is easy to process. The problem occurs when the word line pulls out the contact window to the word line short circuit. One conventional practice would pull the distance of two adjacent word lines apart at the end and present a structure similar to a Y shape to increase the process window of the contact window. However, this method must additionally occupy the area of the edge of the memory cell array, resulting in an increase in the size of the wafer, and cannot be applied to both ends of the word line at the edge of the memory cell array to pull out the contact window, and the word line disconnection cannot be reduced. Time loss.
此外，由於記憶胞佈局的兩端還分別設置有電容器接觸窗，且電容器接觸窗的橋接裕度(bridge window)會取決於相鄰的兩個電容器接觸窗之間的間距。現行的佈局中，相鄰的兩個電容器接觸窗之間的間距僅有1特徵尺寸(1F)。受限於佈局設計，當製程微縮時，電容器接觸窗的橋接裕度將變得更小。In addition, since both ends of the memory cell layout are respectively provided with capacitor contact windows, the bridge window of the capacitor contact window may depend on the spacing between adjacent two capacitor contact windows. In the current layout, the spacing between adjacent two capacitor contact windows is only 1 feature size (1F). Limited by the layout design, when the process is miniature, the bridge margin of the capacitor contact window will become smaller.
本發明提供一種動態隨機存取記憶體，可有效減少記憶單元間的干擾問題，並增加製程裕度。The invention provides a dynamic random access memory, which can effectively reduce the interference problem between memory cells and increase the process margin.
本發明的動態隨機存取記憶體，包括基底、多個隔離結構、多條埋入式字元線、多條位元線以及多個電容器。基底包括多個主動區，主動區被配置成帶狀且排列成一陣列。多個隔離結構，設置於所述基底的溝渠中，每一所述隔離結構設置於兩個相鄰的所述主動區之間；多條埋入式字元線沿第一方向平行設置於基底的溝渠中，每一埋入式字元線將排列成同一列的主動區分為第一接觸區與第二接觸區。多條位元線沿第二方向平行設置於基底上，且橫跨埋入式字元線。主動區的長邊方向與第二方向呈現非正交，每一位元線連接排列成同一行的主動區的第一接觸區。多個電容器分別電性連接所述主動區的所述第二接觸區。The dynamic random access memory of the present invention comprises a substrate, a plurality of isolation structures, a plurality of buried word lines, a plurality of bit lines, and a plurality of capacitors. The substrate includes a plurality of active regions that are arranged in a strip shape and arranged in an array. a plurality of isolation structures disposed in the trenches of the substrate, each of the isolation structures being disposed between two adjacent active regions; the plurality of buried word lines being disposed in parallel with the substrate along the first direction In the trench, each buried word line is arranged in the same column and is actively divided into a first contact area and a second contact area. A plurality of bit lines are disposed in parallel along the second direction on the substrate and across the buried word line. The long side direction of the active area is non-orthogonal with the second direction, and each bit line is connected to form a first contact area of the active area of the same row. A plurality of capacitors are electrically connected to the second contact regions of the active region, respectively.
在本發明的一實施例中，上述的主動區的長邊方向與第二方向之夾角為15º~50º。In an embodiment of the invention, the angle between the longitudinal direction of the active region and the second direction is 15o~50o.
在本發明的一實施例中，上述的第一方向上，相鄰的主動區之間具有一個特徵尺寸間距。In an embodiment of the invention, in the first direction, the adjacent active regions have a feature size spacing therebetween.
在本發明的一實施例中，上述的相鄰兩列的主動區成鏡像配置。In an embodiment of the invention, the active regions of the adjacent two columns are mirrored.
在本發明的一實施例中，在相鄰的字元線之間設置有兩個第一接觸區或兩個第二接觸區。In an embodiment of the invention, two first contact regions or two second contact regions are disposed between adjacent word lines.
在本發明的一實施例中，相鄰的埋入式字元線之間的間距大於一個特徵尺寸，且在第一方向上，相鄰的主動區之間具有一個特徵尺寸間距。In an embodiment of the invention, the spacing between adjacent buried word lines is greater than one feature size, and in the first direction, there is a feature size spacing between adjacent active regions.
在本發明的一實施例中，上述的第一方向上，主動區的兩端部分別與相鄰的主動區的兩端部並列配置。In an embodiment of the invention, in the first direction, both end portions of the active region are arranged in parallel with both end portions of the adjacent active regions.
在本發明的一實施例中，一列的主動區的第二接觸區與相鄰的另一列的主動區的所述第一接觸區成交錯配置。In an embodiment of the invention, the second contact regions of the active regions of one column are staggered with the first contact regions of the active regions of another adjacent column.
在本發明的一實施例中，上述的動態隨機存取記憶體，更包括多個電容器接觸窗。多個電容器接觸窗位於電容器與第二接觸區之間，以電性連接所述位元線與所述第二接觸區。In an embodiment of the invention, the dynamic random access memory further includes a plurality of capacitor contact windows. A plurality of capacitor contact windows are located between the capacitor and the second contact region to electrically connect the bit line and the second contact region.
在本發明的一實施例中，上述的動態隨機存取記憶體，更包括多個位元線接觸窗。多個位元線接觸窗位於所述位元線與所述第一接觸區之間以電性連接所述電容器與所述第一接觸區。In an embodiment of the invention, the dynamic random access memory further includes a plurality of bit line contact windows. A plurality of bit line contact windows are located between the bit line and the first contact region to electrically connect the capacitor and the first contact region.
基於上述，本發明的動態隨機存取記憶體，一個主動區上只形成有一個記憶單元，且各記憶單元之間由元件隔離結構分離，因此可有效減少記憶單元之間的干擾問題。而且，相鄰的埋入式字元線之間的間距較大，因此可以於記憶胞陣列邊緣，對應於埋入式字元線的兩端均設置字元線拉出接觸窗，而可以減少埋入式字元線斷線時的損失，並能夠增加字元線拉出接觸窗的製程裕度。此外，若一列的主動區的第二接觸區會與相鄰的另一列的主動區的第一接觸區成交錯配置，則可以縮小記憶體的尺寸。Based on the above, in the dynamic random access memory of the present invention, only one memory cell is formed on one active region, and each memory cell is separated by an element isolation structure, so that interference between memory cells can be effectively reduced. Moreover, the spacing between adjacent buried word lines is relatively large, so that the word line can be pulled out of the contact window at both ends of the memory cell array corresponding to the buried word line, and the contact window can be reduced. The loss of the buried word line when the line is broken, and can increase the process margin of the word line pulling out of the contact window. In addition, if the second contact area of the active area of one column is staggered with the first contact area of the active area of another adjacent column, the size of the memory can be reduced.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
本文中請參照圖式，以便更加充分地體會本發明的概念，隨附圖式中顯示本發明的實施例。但是，本發明還可採用許多不同形式來實踐，且不應將其解釋為限於底下所述之實施例。實際上，提供實施例僅為使本發明更將詳盡且完整，並將本發明之範疇完全傳達至所屬技術領域中具有通常知識者。The embodiments of the present invention are shown in the accompanying drawings. However, the invention may be practiced in many different forms and should not be construed as being limited to the embodiments described. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed to those of ordinary skill in the art.
在圖式中，為明確起見可能將各層以及區域的尺寸以及相對尺寸作誇張的描繪。In the drawings, the dimensions and relative dimensions of the various layers and regions may be exaggerated for clarity.
圖1A是依照本發明的第一實施例的一種動態隨機存取記憶體的佈局示意圖；圖1B是圖1A的A-A'線段的剖面示意圖。在圖1B中繪示了單一記憶單元的結構。1A is a schematic diagram showing the layout of a dynamic random access memory according to a first embodiment of the present invention; and FIG. 1B is a schematic cross-sectional view of the line AA' of FIG. 1A. The structure of a single memory cell is illustrated in Figure 1B.
請參照圖1A及圖1B，本實施例的動態隨機存取記憶體包括基底100、多條埋入式字元線102、多條位元線106與多個電容器108。Referring to FIG. 1A and FIG. 1B, the DRAM of the present embodiment includes a substrate 100, a plurality of buried word lines 102, a plurality of bit lines 106, and a plurality of capacitors 108.
多條埋入式字元線102沿Y方向(列方向)平行設置於基底100的溝渠中，埋入式字元線102的材料例如是鎢、矽化鎢、氮化鈦…等金屬導體，形成方法例如是物理氣相沈積法、化學氣相沈積法或原子層氣相沈積法。在埋入式字元線102與基底100之間，如圖1B所示，更可設置有絕緣層112作為閘介電層。絕緣層112的材料例如是氧化矽，其形成方法包括在爐管中進行熱氧化製程等的製程。A plurality of buried word lines 102 are arranged in parallel in the Y direction (column direction) in the trenches of the substrate 100, and the material of the buried word lines 102 is, for example, a metal conductor such as tungsten, tungsten telluride or titanium nitride. The method is, for example, physical vapor deposition, chemical vapor deposition or atomic layer vapor deposition. Between the buried word line 102 and the substrate 100, as shown in FIG. 1B, an insulating layer 112 may be further disposed as a gate dielectric layer. The material of the insulating layer 112 is, for example, cerium oxide, and the forming method thereof includes a process of performing a thermal oxidation process or the like in the furnace tube.
多條位元線106沿X方向(行方向)平行設置於基底100上，且橫跨埋入式字元線102。位元線106的材料例如是鎢、矽化鎢、氮化鈦…等過渡金屬導體，形成方法例如是物理氣相沈積法、化學氣相沈積法或原子層氣相沈積法。埋入式字元線102與位元線106例如互相垂直。A plurality of bit lines 106 are disposed in parallel on the substrate 100 in the X direction (row direction) and across the buried word line 102. The material of the bit line 106 is, for example, a transition metal conductor such as tungsten, tungsten telluride, titanium nitride, etc., and the formation method is, for example, physical vapor deposition, chemical vapor deposition, or atomic layer vapor deposition. The buried word line 102 and the bit line 106 are, for example, perpendicular to each other.
基底100包括多個主動區104。主動區104被配置為帶狀且排列成一陣列。主動區104的長邊方向與X方向呈現非正交而具有夾角θ。每一埋入式字元線102將排列成同一列的主動區104分為第一接觸區110a與第二接觸區110b。在多個主動區104之間例如設置有多個隔離結構118。Substrate 100 includes a plurality of active regions 104. The active regions 104 are configured in a strip shape and arranged in an array. The longitudinal direction of the active region 104 and the X direction are non-orthogonal and have an included angle θ. Each buried word line 102 divides the active area 104 arranged in the same column into a first contact area 110a and a second contact area 110b. A plurality of isolation structures 118 are disposed between the plurality of active regions 104, for example.
每一位元線106電性連接排列成同一行的主動區104的第一接觸區110a。亦即，基底100上的每一條位元線106在橫跨埋入式字元線102的同時，還能分別利用如位元線接觸窗116(如圖1B所示)來電性連接位於埋入式字元線102一側的第一接觸區110a。Each of the bit lines 106 is electrically connected to the first contact area 110a of the active area 104 of the same row. That is, each bit line 106 on the substrate 100 can be electrically connected to the buried word line 102 at the same time as the bit line contact window 116 (shown in FIG. 1B). The first contact area 110a on one side of the word line 102.
主動區104的長邊方向與X方向之夾角θ可為15º~50º，但本發明並不限於此。根據主動區104的面積、位元線106的線寬及埋入式字元線102的線寬等參數都會影響夾角θ的範圍。另外，位元線接觸窗116在圖1A中雖顯示為矩形，但實際上可略呈圓形，且其大小可依製程變大或變小。The angle θ between the longitudinal direction of the active region 104 and the X direction may be 15o to 50o, but the present invention is not limited thereto. Parameters such as the area of the active area 104, the line width of the bit line 106, and the line width of the buried word line 102 all affect the range of the included angle θ. In addition, the bit line contact window 116 is shown as a rectangle in FIG. 1A, but may actually be slightly circular, and its size may become larger or smaller depending on the process.
多個電容器108分別電性連接主動區104的第二接觸區110b。而電容器108通常設置在基底100上的絕緣層130內。電容器108例如是堆疊電容器，包括導體層120、介電層122以及導體層124。導體層120、導體層124例如為TiN(或TiN/SiGe)、介電層122可為ZAZ(即ZrO2/Al2O3/ZrO2)之類的介電材料，且可適用於60nm以下的DRAM。The plurality of capacitors 108 are electrically connected to the second contact regions 110b of the active region 104, respectively. Capacitor 108 is typically disposed within insulating layer 130 on substrate 100. The capacitor 108 is, for example, a stacked capacitor including a conductor layer 120, a dielectric layer 122, and a conductor layer 124. The conductor layer 120 and the conductor layer 124 are, for example, TiN (or TiN/SiGe), and the dielectric layer 122 may be a dielectric material such as ZAZ (ie, ZrO2 /Al2 O3 /ZrO2 ), and is applicable to 60 nm or less. DRAM.
每一個電容器108可使用電容器接觸窗114來電性連接至位於埋入式字元線102另一側的第二接觸區110b。此外，電容器接觸窗114在圖1A中雖顯示為矩形，但實際上可略呈圓形，且其大小可依製程變大或變小。Each capacitor 108 can be electrically connected to the second contact region 110b on the other side of the buried word line 102 using a capacitor contact window 114. Further, although the capacitor contact window 114 is shown as a rectangle in FIG. 1A, it may be slightly circular in shape, and its size may become larger or smaller depending on the process.
除了圖1A中有顯示的結構外，從圖1B可知，埋入式字元線102是設置於基底100的溝渠中。在基底100上的電容器108、電容器接觸窗114、位元線106、位元線接觸窗116等，通常藉由各絕緣層126、128、130來分開。絕緣層126、128、130可包括二氧化矽(SiO2)、氮化矽(SiN)或硼磷矽玻璃(BPSG)等絕緣材料。在每一個主動區104中分別設置一個記憶單元。記憶單元包括埋入式字元線102、絕緣層112、位元線106、位元線接觸窗116、電容器108以及電容器接觸窗114。In addition to the structure shown in FIG. 1A, it can be seen from FIG. 1B that the buried word line 102 is disposed in the trench of the substrate 100. Capacitor 108, capacitor contact window 114, bit line 106, bit line contact window 116, etc. on substrate 100 are typically separated by insulating layers 126, 128, 130. The insulating layers 126, 128, 130 may include an insulating material such as cerium oxide (SiO2 ), cerium nitride (SiN), or borophosphorus bismuth glass (BPSG). A memory unit is provided in each of the active areas 104. The memory cell includes a buried word line 102, an insulating layer 112, a bit line 106, a bit line contact window 116, a capacitor 108, and a capacitor contact window 114.
本實施例的每一個主動區104中，第一接觸區110a電性連接一條位元線106，第二接觸區110b電性連接一個電容器108。如圖1A所示，埋入式字元線102的線寬W1約為1個特徵尺寸(1F)間距；埋入式字元線102之間的間距W2約為3個特徵尺寸(3F)間距。在X方向上，主動區104之間的間距W3約為1個特徵尺寸(1F)間距。在Y方向上，主動區104之間的間距W4約為1個特徵尺寸(1F)間距。此外，在記憶胞陣列邊緣，設置有電性連接埋入式字元線102的字元線拉出接觸窗134以及電性連接位元線106的位元線拉出接觸窗132。其中，字元線拉出接觸窗134是對應埋入式字元線102的兩端而設置。In each active area 104 of the embodiment, the first contact area 110a is electrically connected to one bit line 106, and the second contact area 110b is electrically connected to a capacitor 108. As shown in FIG. 1A, the line width W1 of the buried word line 102 is about 1 feature size (1F) pitch; the pitch W2 between the buried word lines 102 is about 3 feature size (3F) pitch. . In the X direction, the spacing W3 between the active regions 104 is about 1 feature size (1F) pitch. In the Y direction, the spacing W4 between the active regions 104 is about 1 feature size (1F) pitch. In addition, at the edge of the memory cell array, a word line that is electrically connected to the buried word line 102 is pulled out of the contact window 134 and a bit line that electrically connects the bit line 106 is pulled out of the contact window 132. The word line pull-out contact window 134 is disposed corresponding to both ends of the buried word line 102.
在上述實施例中，一個主動區104上只形成有一個記憶單元，且各記憶單元之間由元件隔離結構118分離，因此可有效減少記憶單元之間的干擾問題。而且，相鄰的兩個埋入式字元線102之間的間距W2有3個特徵尺寸(3F)間距，因此可以於記憶胞陣列邊緣，對應於埋入式字元線102的兩端均設置字元線拉出接觸窗134，而可以減少埋入式字元線102斷線時的損失，並能夠增加字元線拉出接觸窗134的製程裕度。In the above embodiment, only one memory cell is formed on one active region 104, and the memory cells are separated by the element isolation structure 118, so that the interference problem between the memory cells can be effectively reduced. Moreover, the spacing W2 between two adjacent buried word lines 102 has three feature size (3F) pitches, and thus can be at the edge of the memory cell array, corresponding to both ends of the buried word line 102. The set word line pulls out the contact window 134, which can reduce the loss when the buried word line 102 is broken, and can increase the process margin of the word line pulling out of the contact window 134.
圖2是依照本發明的第二實施例的一種動態隨機存取記憶體的佈局示意圖。在第二實施例中，構件與第一實施例相同者，給予相同的符號，並省略其說明。以下只針對不同點做說明。2 is a schematic diagram showing the layout of a dynamic random access memory in accordance with a second embodiment of the present invention. In the second embodiment, the same members as those in the first embodiment are given the same reference numerals, and the description thereof will be omitted. The following only explains the different points.
如圖2所示，基底100包括多個主動區104。主動區104成帶狀且排列成一陣列，於本實施例中，這些主動區104排列成5個主動區列R1~R5，且相鄰兩個主動區列呈鏡像配置。舉例來說，主動區列R1、R3、R5的長邊方向與X方向呈現非正交而具有夾角θ，主動區列R2、R4的長邊方向與X方向呈現非正交而具有夾角(180º-θ)。在相鄰的兩個埋入式字元線102之間設置有兩個第一接觸區110a或兩個第二接觸區110b。As shown in FIG. 2, substrate 100 includes a plurality of active regions 104. The active areas 104 are arranged in a strip shape and arranged in an array. In this embodiment, the active areas 104 are arranged in five active area columns R1 R R5, and the adjacent two active area columns are mirrored. For example, the longitudinal direction of the active region columns R1, R3, and R5 is non-orthogonal and has an included angle θ, and the longitudinal direction of the active region columns R2 and R4 is non-orthogonal with the X direction and has an angle (180o). -θ). Two first contact regions 110a or two second contact regions 110b are disposed between adjacent two buried word lines 102.
在上述實施例中，一個主動區104上只形成有一個記憶單元，且各記憶單元之間由元件隔離結構118分離，因此可有效減少記憶單元之間的干擾問題。而且，相鄰的兩個埋入式字元線102之間的間距有3個特徵尺寸(3F)間距，因此可以於記憶胞陣列邊緣，對應於埋入式字元線102的兩端均設置字元線拉出接觸窗134，而可以減少字元線斷線時的損失，並能夠增加字元線拉出接觸窗134的製程裕度。In the above embodiment, only one memory cell is formed on one active region 104, and the memory cells are separated by the element isolation structure 118, so that the interference problem between the memory cells can be effectively reduced. Moreover, the spacing between adjacent two buried word lines 102 has three feature size (3F) pitches, and thus can be set at the edges of the memory cell array corresponding to both ends of the buried word line 102. The word line pulls out the contact window 134, which can reduce the loss of the word line when the line is broken, and can increase the process margin of the word line pulling out of the contact window 134.
圖3是依照本發明的第三實施例的一種動態隨機存取記憶體的佈局示意圖。在第三實施例中，構件與第一實施例相同者，給予相同的符號，並省略其說明。以下只針對不同點做說明。3 is a schematic diagram showing the layout of a dynamic random access memory in accordance with a third embodiment of the present invention. In the third embodiment, the same members as those of the first embodiment are given the same reference numerals, and the description thereof will be omitted. The following only explains the different points.
如圖3所示，基底100包括多個主動區104。這些主動區104成帶狀且排列成一陣列。舉例來說，這些主動區104排列成5個主動區列R1~R5。在X方向上，主動區104的兩端部分別與相鄰的主動區104的兩端部並列配置。在兩相鄰的埋入式字元線102之間，排成一列的主動區104的第二接觸區110b會與相鄰的排成另一列的主動區104的第一接觸區110a於Y方向上呈交錯配置。舉例來說，在主動區列R1與主動區列R2之間，主動區列R1中的主動區104的第二接觸區110b會與主動區列R2中的主動區104的第一接觸區110a於Y方向上呈交錯配置；而在主動區列R2與主動區列R3之間，主動區列R2中的主動區104的第二接觸區110b會與主動區列R3中的主動區104的第一接觸區110a於Y方向上呈交錯配置。在上述實施例中，一個主動區104上只形成有一個記憶單元，且各記憶單元之間由元件隔離結構分離，因此可有效減少記憶單元間的干擾問題。而且，在兩相鄰的埋入式字元線102之間，排成一列的主動區104的第二接觸區110b會與相鄰的排成另一列的主動區104的第一接觸區110a呈交錯配置，可以縮小記憶體的尺寸。As shown in FIG. 3, substrate 100 includes a plurality of active regions 104. These active regions 104 are strip-shaped and arranged in an array. For example, the active regions 104 are arranged in five active region columns R1 R R5. In the X direction, both end portions of the active region 104 are arranged in parallel with both end portions of the adjacent active regions 104. Between two adjacent buried word lines 102, the second contact regions 110b of the active regions 104 arranged in a row will be in the Y direction with the first contact regions 110a of the adjacent active regions 104 arranged in another column. The top is staggered. For example, between the active region column R1 and the active region column R2, the second contact region 110b of the active region 104 in the active region column R1 and the first contact region 110a of the active region 104 in the active region column R2 In the Y direction, there is a staggered configuration; and between the active region column R2 and the active region column R3, the second contact region 110b of the active region 104 in the active region column R2 and the first region of the active region 104 in the active region column R3 The contact regions 110a are arranged in a staggered manner in the Y direction. In the above embodiment, only one memory cell is formed on one active region 104, and each memory cell is separated by an element isolation structure, so that interference between memory cells can be effectively reduced. Moreover, between two adjacent buried word lines 102, the second contact regions 110b of the active regions 104 arranged in a row are adjacent to the first contact regions 110a of the adjacent active regions 104 arranged in another column. Interleaved configuration can reduce the size of the memory.
綜上所述，本發明的動態隨機存取記憶體，一個主動區上只形成有一個記憶單元，且各記憶單元之間由元件隔離結構分離，因此可有效減少記憶元件間的干擾問題。於一些實施例中，相鄰的兩個埋入式字元線之間的間距較大，因此可以於記憶胞陣列邊緣，對應於埋入式字元線的兩端均設置字元線拉出接觸窗，而可以減少埋入式字元線斷線時的損失，並能夠增加字元線拉出接觸窗的製程裕度。此外，於另一些實施例中，將一列的主動區的第二接觸區與相鄰的另一列的主動區的第一接觸區成交錯配置，則可以縮小記憶體的尺寸。In summary, in the dynamic random access memory of the present invention, only one memory cell is formed on one active region, and each memory cell is separated by an element isolation structure, thereby effectively reducing interference between memory elements. In some embodiments, the spacing between adjacent two buried word lines is relatively large, so that the word line can be pulled out at the edges of the memory cell array corresponding to both ends of the buried word line. The contact window can reduce the loss when the buried word line is broken, and can increase the process margin of the word line pulling out of the contact window. In addition, in other embodiments, the size of the memory can be reduced by arranging the second contact regions of the active regions of one column in a staggered configuration with the first contact regions of the active regions of the adjacent other columns.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧基底
102‧‧‧埋入式字元線
104‧‧‧主動區
106‧‧‧位元線
108‧‧‧電容器
110a‧‧‧第一接觸區
110b‧‧‧第二接觸區
112‧‧‧絕緣層
114‧‧‧電容器接觸窗
116‧‧‧位元線接觸窗
118‧‧‧隔離結構
120、124‧‧‧導體層
122‧‧‧介電層
126、128、130‧‧‧絕緣層
132‧‧‧位元線拉出接觸窗
134‧‧‧字元線拉出接觸窗
θ‧‧‧夾角
W1‧‧‧線寬
W2、W3、W4‧‧‧間距
R1~R5‧‧‧主動區列100‧‧‧Base
102‧‧‧Blinded word line
104‧‧‧Active Area
106‧‧‧ bit line
108‧‧‧ capacitor
110a‧‧‧First contact area
110b‧‧‧Second contact area
112‧‧‧Insulation
114‧‧‧ capacitor contact window
116‧‧‧ bit line contact window
118‧‧‧Isolation structure
120, 124‧‧‧ conductor layer
122‧‧‧ dielectric layer
126, 128, 130‧‧‧ insulation
132‧‧‧ bit line pull out the contact window
134‧‧‧ character line pull out the contact window θ‧‧‧ angle
W1‧‧‧ line width
W2, W3, W4‧‧‧ spacing
R1~R5‧‧‧active zone
圖1A是依照本發明的第一實施例的一種動態隨機存取記憶體的佈局示意圖。 圖1B是圖1A的A-A'線段的剖面示意圖。 圖2是依照本發明的第二實施例的一種動態隨機存取記憶體的佈局示意圖。 圖3是依照本發明的第三實施例的一種動態隨機存取記憶體的佈局示意圖。1A is a schematic diagram showing the layout of a dynamic random access memory according to a first embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line AA' of Fig. 1A. 2 is a schematic diagram showing the layout of a dynamic random access memory in accordance with a second embodiment of the present invention. 3 is a schematic diagram showing the layout of a dynamic random access memory in accordance with a third embodiment of the present invention.
100‧‧‧基底100‧‧‧Base
102‧‧‧埋入式字元線102‧‧‧Blinded word line
104‧‧‧主動區104‧‧‧Active Area
106‧‧‧位元線106‧‧‧ bit line
108‧‧‧電容器108‧‧‧ capacitor
110a‧‧‧第一接觸區110a‧‧‧First contact area
110b‧‧‧第二接觸區110b‧‧‧Second contact area
114‧‧‧電容器接觸窗114‧‧‧ capacitor contact window
116‧‧‧位元線接觸窗116‧‧‧ bit line contact window
118‧‧‧隔離結構118‧‧‧Isolation structure
132‧‧‧位元線拉出接觸窗132‧‧‧ bit line pull out the contact window
134‧‧‧字元線拉出接觸窗134‧‧‧ character line pull out the contact window
θ‧‧‧夾角Θ‧‧‧ angle
W1‧‧‧線寬W1‧‧‧ line width
W2、W3、W4‧‧‧間距W2, W3, W4‧‧‧ spacing
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104136113ATWI595544B (en) | 2015-11-03 | 2015-11-03 | Dynamic random access memory |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104136113ATWI595544B (en) | 2015-11-03 | 2015-11-03 | Dynamic random access memory |
| Publication Number | Publication Date |
|---|---|
| TW201717265A TW201717265A (en) | 2017-05-16 |
| TWI595544Btrue TWI595544B (en) | 2017-08-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104136113ATWI595544B (en) | 2015-11-03 | 2015-11-03 | Dynamic random access memory |
| Country | Link |
|---|---|
| TW (1) | TWI595544B (en) |
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|---|---|---|---|---|
| TWI702711B (en)* | 2019-07-04 | 2020-08-21 | 華邦電子股份有限公司 | Dyanmic random access memory and method of manufacturing the same |
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