本發明實施例係屬半導體製造領域，尤指，半導體元件製造。Embodiments of the invention are in the field of semiconductor fabrication, and in particular, semiconductor component fabrication.
本申請案係2008年8月25日所提申之共同申請之美國申請案序號12/197,466之部分接續案，美國申請案序號12/197,466係2008年5月21日所提申之美國申請案序號12/124,855之接續案，美國申請案序號12/124,855基於35 U.S.C.119(e)條款主張2007年5月25日所提申之美國臨時專利申請案序號60/940,139和2007年11月9日所提申之美國臨時專利申請案序號60/986,637之優先權利益，在此將其全體一併整合參考之。This application is a continuation of the US application Serial No. 12/197,466, filed on August 25, 2008, which is incorporated herein by reference. Serial No. 12/124,855, U.S. Serial No. 12/124,855, based on 35 USC 119(e), claims US Provisional Patent Application Serial No. 60/940,139, filed May 25, 2007, and November 9, 2007 The priority benefits of the U.S. Provisional Patent Application Serial No. 60/986,637, the entire disclosure of which is incorporated herein by reference.
過去數個十年中，積體電路之特徵尺寸縮放已成為支持半導體工業持續成長之驅動力。特徵尺寸越縮越小可增加半導體晶片之有限晶片面積上之功能單位密度。例如，縮小電晶體大小可在一晶片上整合更多記憶體元件，導致生產力增加之產品製造。然而，驅動持續不斷更多之生產力並不是毫無問題。對最佳化每一個元件之執行效率需求變得越來越明顯。In the past few decades, the feature size scaling of integrated circuits has become the driving force behind the continued growth of the semiconductor industry. The smaller the feature size, the smaller the functional unit density over the limited wafer area of the semiconductor wafer. For example, shrinking the size of the transistor allows more memory components to be integrated on a wafer, resulting in increased productivity of the product. However, the drive continues to be more livelyProductivity is not without problems. The need to optimize the efficiency of execution of each component is becoming increasingly apparent.
非揮發性半導體記憶體典型地使用堆疊式浮閘型場效電晶體。在這類電晶體中，電子係藉由施偏壓於一控制閘極並接地將該記憶體單元形成於其上之基板本體區域來射入至欲程式化之記憶體單元之浮接閘極。一氧化物-氮化物-氧化物(ONO)堆疊不是充當例如一半導體-氧化物-氮化物-氧化物-半導體(SONOS)電晶體內之電荷儲存層就是充當例如一分離式閘極快閃電晶體內之浮接閘極與控制閘極間的絕緣層。圖1說明一傳統非揮發性電荷捕獲記憶體元件之剖面圖。Non-volatile semiconductor memory typically uses stacked floating gate field effect transistors. In such a transistor, electrons are incident on the floating gate of the memory cell to be programmed by biasing a control gate and grounding the substrate body region on which the memory cell is formed. . A single oxide-nitride-oxide (ONO) stack does not act as, for example, a charge storage layer within a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor or acts as, for example, a split gate flash crystal An insulating layer between the floating gate and the control gate in the body. Figure 1 illustrates a cross-sectional view of a conventional non-volatile charge trapping memory component.
參考至圖1，半導體元件100包含一半導體-氧化物-氮化物-氧化物-半導體閘極堆疊104，包含形成於一矽基板102上方之傳統氧化物-氮化物-氧化物部分106。半導體元件100進一步包含分別位於半導體-氧化物-氮化物-氧化物-半導體閘極堆疊104一側上之源極及汲極區域110。半導體-氧化物-氮化物-氧化物-半導體閘極堆疊104包含形成於上方並接觸到氧化物-氮化物-氧化物部分106之多晶矽閘極層108。多晶矽閘極層108係經由氧化物-氮化物-氧化物部分106而與矽基板102電性隔離。氧化物-氮化物-氧化物部分106典型地包含一穿隧氧化物層106A、一氮化物或氮氧化物電荷捕獲層106B及在氮化物或氮氧化物電荷捕獲層106B上方之一頂部氧化物層106C。Referring to FIG. 1, semiconductor component 100 includes a semiconductor-oxide-nitride-oxide-semiconductor gate stack 104 comprising a conventional oxide-nitride-oxide portion 106 formed over a germanium substrate 102. Semiconductor component 100 further includes source and drain regions 110 on one side of semiconductor-oxide-nitride-oxide-semiconductor gate stack 104, respectively. The semiconductor-oxide-nitride-oxide-semiconductor gate stack 104 includes a polysilicon gate layer 108 formed over and in contact with the oxide-nitride-oxide portion 106. The polysilicon gate layer 108 is electrically isolated from the germanium substrate 102 via the oxide-nitride-oxide portion 106. The oxide-nitride-oxide portion 106 typically includes a tunneling oxide layer 106A, a nitride or oxynitride charge trap layer 106B, and a top oxide over the nitride or oxynitride charge trap layer 106B. Layer 106C.
一傳統半導體-氧化物-氮化物-氧化物-半導體電晶體之問題係在該氮化物或氮氧化物電荷捕獲層106B內之不良資料保持限制半導體元件100之壽命並因該層之漏電而限制它在一些應用上之使用。A problem with a conventional semiconductor-oxide-nitride-oxide-semiconductor transistor is that the poor data in the nitride or oxynitride charge trap layer 106B remains limiting the lifetime of the semiconductor device 100 and is limited by the leakage of the layer. It is used in some applications.
根據本發明一觀點，一種製造記憶體元件之方法包括：使一基板承受一第一氧化製程以在連接形成於該基板內之記憶體元件之源極和汲極的通道上方形成一穿隧氧化物層，其中，該通道包括多晶矽；在該穿隧氧化物層上方形成一多層電荷儲存層，該多層電荷儲存層包括含在該穿隧氧化物層上之氮化物之一含氧之第一層，其中，該第一層之化學計量組成成分致使它實質上無捕獲，並包括含該第一層上之氮化物之一缺氧之第二層，其中，該第二層之化學計量組成成分致使它為密集捕獲；以及使該基板承受一第二氧化製程以耗用一部分第二層並在該多層電荷儲存層上方形成一高溫氧化物(HTO)層。According to one aspect of the invention, a method of fabricating a memory device includes subjecting a substrate to a first oxidation process to form a tunneling oxide over a channel connecting a source and a drain of a memory device formed in the substrate. a layer, wherein the channel comprises a polysilicon; a plurality of charge storage layers are formed over the tunnel oxide layer, the multilayer charge storage layer comprising an oxygen containing one of the nitrides on the tunnel oxide layer a layer, wherein the stoichiometric composition of the first layer renders it substantially non-captured and includes a second layer comprising one of the nitrides on the first layer, wherein the second layer is stoichiometric The composition causes it to be densely trapped; and subjecting the substrate to a second oxidation process to consume a portion of the second layer and forming a high temperature oxide (HTO) layer over the plurality of charge storage layers.
根據本發明另一觀點，一種製造記憶體元件之方法包括：在一基板表面上形成包含至少一第一介電層、一閘極層和一第二介電層之多層堆疊，其中，該閘極層係經由該第一介電層而與該基板表面分開，且該第二介電層係經由該閘極層而與該第一介電層分開；形成延伸經過該多層堆疊至形成於該基板表面上之第一摻雜擴散區域之開口；在該開口側壁上形成一高溫氧化物(HTO)層；在該高溫氧化物層之內部側壁上形成一多層電荷儲存層，該多層電荷儲存層包括在該高溫氧化物層上之缺氧第一氮氧化物層，其中，該第一氮氧化物層之化學計量組成成分致使它為密集捕獲，並包括在該第一氮氧化物層上之含氧第二氮氧化物層，其中，該第二氮氧化物層之化學計量組成成分致使它實質上無捕獲；在該多層電荷儲存層一內部側壁上形成一穿隧氧化物層；以及在該穿隧氧化物層一內部側壁上形成一包括多晶矽之垂直通道，其中，該垂直通道電性耦接第一摻雜擴散區域至接著形成於該多層堆疊和該開口上方之半導體材料層內之一第二摻雜擴散區域。According to another aspect of the present invention, a method of fabricating a memory device includes: forming a multilayer stack including at least a first dielectric layer, a gate layer, and a second dielectric layer on a surface of a substrate, wherein the gate The pole layer is separated from the surface of the substrate via the first dielectric layer, and the second dielectric layer is separated from the first dielectric layer via the gate layer; forming an extension through the multilayer stack to be formed thereon An opening of the first doped diffusion region on the surface of the substrate; forming a high temperature oxide (HTO) layer on the sidewall of the opening; forming a plurality of charge storage layers on the inner sidewall of the high temperature oxide layer, the multilayer charge storage The layer includes an oxygen-deficient first oxynitride layer on the high temperature oxide layer, wherein the stoichiometric composition of the first oxynitride layer causes it to be densely trapped and included on the first oxynitride layer An oxygen-containing second oxynitride layer, wherein the stoichiometric composition of the second oxynitride layer renders it substantially free of capture; forming a tunneling oxide layer on an inner sidewall of the multilayer charge storage layer; In the Tunnel oxide layer formed on an inner sidewallForming a vertical channel comprising a polysilicon, wherein the vertical channel is electrically coupled to the first doped diffusion region to a second doped diffusion region formed in the layer of semiconductor material over the multilayer stack and the opening.
100‧‧‧半導體元件100‧‧‧Semiconductor components
102‧‧‧矽基板102‧‧‧矽 substrate
104、1402‧‧‧閘極堆疊104, 1402‧‧ ‧ gate stacking
106‧‧‧氧化物-氮化物-氧化物部分106‧‧‧Oxide-nitride-oxide fraction
108‧‧‧多晶矽閘極層108‧‧‧Polysilicon gate layer
110、612、1012、1212‧‧‧源極和汲極區域110, 612, 1012, 1212‧‧‧ source and bungee regions
112、614、1014、1214、1412‧‧‧通道區域112, 614, 1014, 1214, 1412‧‧‧ channel areas
106A、1616、1714、1808‧‧‧穿隧氧化物層106A, 1616, 1714, 1808‧‧‧ tunnel oxide layer
106B‧‧‧氮化物或氮氧化物層106B‧‧‧Nitride or oxynitride layer
106C‧‧‧頂部氧化物層106C‧‧‧Top oxide layer
200‧‧‧批次處理腔室200‧‧‧ batch processing chamber
202‧‧‧半導體晶圓202‧‧‧Semiconductor wafer
204‧‧‧載子設備204‧‧‧Machine equipment
300、500、900、1100‧‧‧流程圖300, 500, 900, 1100‧‧‧ flow chart
302-306、502-512、902-910、1102-1114、1500-1508‧‧‧操作302-306, 502-512, 902-910, 1102-1114, 1500-1508‧‧‧ operations
400、600、700、1000、1200、1300、1408、1500、1606、1706、1906、2006‧‧‧基板400, 600, 700, 1000, 1200, 1300, 1408, 1500, 1606, 1706, 1906, 2006‧‧‧ substrates
402、602、606、708、1002、1006、1202、1206、1308、1902、1910、2002‧‧‧介電層402, 602, 606, 708, 1002, 1006, 1202, 1206, 1308, 1902, 1910, 2002‧‧‧ dielectric layer
404、604、1004、1204、1624、1626、1720、1722、1810、1816、1818、1916、2016、2016a、2016b‧‧‧電荷捕獲層404, 604, 1004, 1204, 1624, 1626, 1720, 1722, 1810, 1816, 1818, 1916, 2016, 2016a, 2016b‧‧‧ charge trapping layer
404A、604A、708A、1004A、1204B‧‧‧第一區域404A, 604A, 708A, 1004A, 1204B‧‧‧ first area
404B、604B、708B、1004B、1204C‧‧‧第二區域404B, 604B, 708B, 1004B, 1204C‧‧‧ second area
406、1618、1716、1812、1918、2018‧‧‧阻擋介電層406, 1618, 1716, 1812, 1918, 2018‧ ‧ blocking dielectric layer
608、1008、1208、1414、1620、1718、1814、1908、2022‧‧‧閘極層608, 1008, 1208, 1414, 1620, 1718, 1814, 1908, 2022‧‧ ‧ gate layer
610、1010、1210‧‧‧介電間隔側壁610, 1010, 1210‧‧‧ dielectric spacer sidewall
702、1302‧‧‧隔離區域702, 1302‧‧‧Isolated area
704、706、1304、1306‧‧‧露出結晶平面704, 706, 1304, 1306‧‧‧ exposed crystal plane
800‧‧‧叢集工具800‧‧‧ cluster tools
802‧‧‧轉移腔室802‧‧‧Transfer chamber
804、806、808‧‧‧製程腔室804, 806, 808‧‧ ‧ process chamber
1204A‧‧‧含氧氮氧化矽部分1204A‧‧‧Oxygen oxynitride fraction
1308A‧‧‧第一部分1308A‧‧‧Part 1
1308B‧‧‧第二部分1308B‧‧‧Part II
1400、1600、1800、2026‧‧‧記憶體元件1400, 1600, 1800, 2026‧‧‧ memory components
1404‧‧‧氧化物-氮化物-氧化物-氮化物-氧化物結構1404‧‧‧Oxide-nitride-oxide-nitride-oxide structure
1406、1604‧‧‧表面1406, 1604‧‧‧ surface
1410、1904、1930‧‧‧擴散區域1410, 1904, 1930‧‧‧Diffusion area
1416、1502、1914、2014‧‧‧穿隧氧化物層1416, 1502, 1914, 2014‧‧‧ tunnel oxide layer
1418、1419、1504‧‧‧氮化物層1418, 1419, 1504‧‧‧ nitride layer
1420‧‧‧阻擋氧化物層1420‧‧‧Block oxide layer
1421、1506、1628、1724、1820、2020‧‧‧抗穿隧層1421, 1506, 1628, 1724, 1820, 2020‧‧‧ anti-through tunneling
1508、1614‧‧‧多層電荷儲存層1508, 1614‧‧‧Multilayer charge storage layer
1602‧‧‧通道1602‧‧‧ channel
1608、1708、1804‧‧‧源極1608, 1708, 1804‧‧‧ source
1610、1710、1806‧‧‧汲極1610, 1710, 1806‧‧‧ bungee
1612、1712‧‧‧閘極1612, 1712‧‧ ‧ gate
1622‧‧‧絕緣層1622‧‧‧Insulation
1700‧‧‧非平面式多閘極記憶體元件1700‧‧‧ Non-planar multi-gate memory components
1702、1802‧‧‧奈米線通道1702, 1802‧‧ nm line
1726‧‧‧位元成本可調架構1726‧‧‧ bit cost adjustable architecture
1924、2008‧‧‧垂直通道1924, 2008‧‧‧ vertical channel
1912、1920、2012、2024‧‧‧開口1912, 1920, 2012, 2024‧‧
1922、1928、2010‧‧‧半導體材料1922, 1928, 2010‧‧‧ semiconductor materials
1926‧‧‧介電填充材料1926‧‧‧ dielectric filling material
2004‧‧‧犧牲層2004‧‧‧ Sacrifice layer
T1、T2‧‧‧厚度T1, T2‧‧‧ thickness
本發明實施例係舉例說明附圖之圖形，並非限制，其中：圖1說明一傳統非揮發性電荷捕獲記憶體元件之剖面圖。The embodiments of the present invention are illustrative of the drawings, and are not limiting. FIG. 1 illustrates a cross-sectional view of a conventional non-volatile charge trapping memory component.
圖2根據本發明一實施例說明一批次處理工具之氧化腔室之剖面圖。2 is a cross-sectional view showing an oxidation chamber of a batch processing tool in accordance with an embodiment of the present invention.
圖3根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作流程圖。3 illustrates a series of operational flow diagrams in a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention.
圖4A根據本發明一實施例說明對應至圖3流程圖中之操作302之具有一電荷捕獲層形成於其上之基板剖面圖。4A illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon corresponding to operation 302 of the flow chart of FIG. 3, in accordance with an embodiment of the present invention.
圖4B根據本發明一實施例說明對應至圖3流程圖之操作304之具有包含一阻擋介電層形成於其上之電荷捕獲層之基板剖面圖。4B illustrates a cross-sectional view of a substrate having a charge trapping layer having a blocking dielectric layer formed thereon corresponding to operation 304 of the flow chart of FIG. 3, in accordance with an embodiment of the present invention.
圖5根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作流程圖。FIG. 5 illustrates a series of operational flow diagrams in a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention.
圖6A根據本發明一實施例說明對應至圖5流程圖中之操作502之基板剖面圖。Figure 6A illustrates a cross-sectional view of a substrate corresponding to operation 502 of the flow chart of Figure 5, in accordance with an embodiment of the present invention.
圖6B根據本發明一實施例說明對應至圖5流程圖中之操作504之具有一第一介電層形成於其上之基板剖面圖。6B illustrates a cross-sectional view of a substrate having a first dielectric layer formed thereon corresponding to operation 504 of the flow chart of FIG. 5, in accordance with an embodiment of the present invention.
圖6C根據本發明一實施例說明對應至圖5流程圖中之操作508之具有一電荷捕獲層形成於其上之基板剖面圖。6C illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon corresponding to operation 508 of the flow chart of FIG. 5, in accordance with an embodiment of the present invention.
圖6D根據本發明一實施例說明對應至圖5流程圖之操作510之具有包含一阻擋介電層形成於其上之電荷捕獲層之基板剖面圖。6D illustrates a cross-sectional view of a substrate having a charge trapping layer having a blocking dielectric layer formed thereon corresponding to operation 510 of the flow chart of FIG. 5, in accordance with an embodiment of the present invention.
圖6E根據本發明一實施例說明一非揮發性電荷捕獲記憶體元件之剖面圖。6E illustrates a cross-sectional view of a non-volatile charge trapping memory component in accordance with an embodiment of the present invention.
圖7A根據本發明一實施例說明包含第一和第二露出結晶平面之基板剖面圖。7A illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention.
圖7B根據本發明一實施例說明包含第一和第二露出結晶平面並具有一介電層形成於其上之基板剖面圖。7B illustrates a cross-sectional view of a substrate including first and second exposed crystalline planes and having a dielectric layer formed thereon, in accordance with an embodiment of the present invention.
圖8根據本發明一實施例說明一叢集工具內之製程腔室配置。Figure 8 illustrates a process chamber configuration within a cluster tool in accordance with an embodiment of the present invention.
圖9根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作流程圖。Figure 9 illustrates a series of operational flow diagrams in a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention.
圖10A根據本發明一實施例說明一基板之剖面圖。Figure 10A illustrates a cross-sectional view of a substrate in accordance with an embodiment of the present invention.
圖10B根據本發明一實施例說明對應至圖4流程圖中之操作402之具有一穿隧介電層形成於其上之基板剖面圖。Figure 10B illustrates a cross-sectional view of a substrate having a tunneling dielectric layer formed thereon corresponding to operation 402 of the flow chart of Figure 4, in accordance with an embodiment of the present invention.
圖10C根據本發明一實施例說明對應至圖4流程圖中之操作406之具有一電荷捕獲層形成於其上之基板剖面圖。Figure 10C illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon corresponding to operation 406 of the flow chart of Figure 4, in accordance with an embodiment of the present invention.
圖10D根據本發明一實施例說明對應至圖4流程圖之操作408之具有一頂部介電層形成於其上之基板剖面圖。Figure 10D illustrates a cross-sectional view of a substrate having a top dielectric layer formed thereon corresponding to operation 408 of the flow chart of Figure 4, in accordance with an embodiment of the present invention.
圖10E根據本發明一實施例說明一非揮發性電荷捕獲記憶體元件之剖面圖。Figure 10E illustrates a cross-sectional view of a non-volatile charge trapping memory component in accordance with an embodiment of the present invention.
圖11根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作流程圖。Figure 11 illustrates a series of operational flow diagrams in a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention.
圖12A根據本發明一實施例說明對應至圖6流程圖中之操作602之具有一穿隧介電層形成於其上之基板剖面圖。Figure 12A illustrates a cross-sectional view of a substrate having a tunneling dielectric layer formed thereon corresponding to operation 602 of the flow chart of Figure 6, in accordance with an embodiment of the present invention.
圖12B根據本發明一實施例說明對應至圖6流程圖中之操作606之具有一電荷捕獲層中含氧之氮氧化矽部分形成於其上之基板剖面圖。Figure 12B illustrates a cross-sectional view of a substrate having an oxygen-containing oxynitride oxide portion of a charge trapping layer formed thereon corresponding to operation 606 of the flow chart of Figure 6 in accordance with an embodiment of the present invention.
圖12C根據本發明一實施例說明對應至圖6流程圖中之操作610之具有一電荷捕獲層中含矽之氮氧化矽部分形成於其上之基板剖面圖。Figure 12C illustrates a cross-sectional view of a substrate having a portion of yttria containing a ruthenium in a charge trap layer formed thereon corresponding to operation 610 of the flow chart of Figure 6 in accordance with an embodiment of the present invention.
圖12D根據本發明一實施例說明對應至圖6流程圖之操作612之具有一頂部介電層形成於其上之基板剖面圖。Figure 12D illustrates a cross-sectional view of a substrate having a top dielectric layer formed thereon corresponding to operation 612 of the flow chart of Figure 6 in accordance with an embodiment of the present invention.
圖12E根據本發明一實施例說明一非揮發性電荷捕獲記憶體元件之剖面圖。Figure 12E illustrates a cross-sectional view of a non-volatile charge trapping memory component in accordance with an embodiment of the present invention.
圖13A根據本發明一實施例說明包含第一和第二露出結晶平面之基板剖面圖。Figure 13A illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention.
圖13B根據本發明一實施例說明包含第一和第二露出結晶平面並具有一介電層形成於其上之基板剖面圖。Figure 13B illustrates a cross-sectional view of a substrate including first and second exposed crystalline planes and having a dielectric layer formed thereon, in accordance with an embodiment of the present invention.
圖14說明包含一氧化物-氮化物-氧化物-氮化物-氧化物堆疊之非揮發性電荷捕獲記憶體元件之剖面圖。Figure 14 illustrates a cross-sectional view of a non-volatile charge trapping memory device comprising an oxide-nitride-oxide-nitride-oxide stack.
圖15根據本發明一實施例說明代表包含一氧化物-氮化物-氧化物-氮化物-氧化物堆疊之非揮發性電荷捕獲記憶體元件製造方法中之一系列操作剖面圖。Figure 15 illustrates a series of operational cross-sectional views of a method of fabricating a non-volatile charge trapping memory device comprising an oxide-nitride-oxide-nitride-oxide stack, in accordance with an embodiment of the present invention.
圖16A說明包含一分離式電荷捕獲區域之非平面式多閘極元件。Figure 16A illustrates a non-planar multi-gate element comprising a separate charge trapping region.
圖16B說明圖16A之非平面式多閘極元件之剖面圖。Figure 16B illustrates a cross-sectional view of the non-planar multi-gate element of Figure 16A.
圖17A及17B說明包含一分離式電荷捕獲區域及一水平奈米線通道之非平面式多閘極元件。17A and 17B illustrate the inclusion of a separate charge trapping region and a horizontal nanowire channel.Non-planar multi-gate components.
圖17C說明圖17A之非平面式多閘極元件垂直串之剖面圖。Figure 17C illustrates a cross-sectional view of the vertical string of the non-planar multi-gate element of Figure 17A.
圖18A及18B說明包含一分離式電荷捕獲區域及一垂直奈米線通道之非平面式多閘極元件。18A and 18B illustrate a non-planar multi-gate element comprising a separate charge trapping region and a vertical nanowire channel.
圖19A至圖19F說明用於製造圖18A之非平面式多閘極元件之閘極優先方案。19A-19F illustrate a gate priority scheme for fabricating the non-planar multi-gate element of FIG. 18A.
圖20A至圖20F說明用於製造圖18A之非平面式多閘極元件之閘極後製方案。20A through 20F illustrate a gate post-production scheme for fabricating the non-planar multi-gate element of FIG. 18A.
一種與邏輯元件整合之非揮發性電荷捕獲記憶體元件之實施例在此參考圖形進行描述。然而，特定實施例可在沒有這些特定細節之一或更多下或結合已知方法、材料及設備來實施。在下列說明中，例如特定材料、尺寸及製程參數等等眾多特定細節被提出，以提供本發明之徹底了解。在其它範例中，熟知半導體設計及製造技術未特別詳加說明以避免不必要地模糊本發明。整份說明書對“一實施例”之參考表示結合該實施例所述之特定特性、結構、材料或特徵係包含於本發明至少一實施例內。因此，在整份說明書之不同地方中之用語“一實施例中”之出現並不一定參考至本發明之相同實施例。更進一步，該些特定特性、結構、材料或特徵可以任何合適方式結合至一或更多實施例中。An embodiment of a non-volatile charge trapping memory component integrated with logic elements is described herein with reference to the figures. However, specific embodiments may be practiced without one or more of these specific details or in combination with known methods, materials, and devices. Numerous specific details are set forth in the following description, such as the specific materials, dimensions, and process parameters, to provide a thorough understanding of the invention. In other instances, well-known semiconductor design and fabrication techniques are not specifically described in order to avoid unnecessarily obscuring the invention. Reference to the "an embodiment" in this specification means that the specific features, structures, materials or characteristics described in connection with the embodiments are included in at least one embodiment of the invention. Thus, appearances of the phrase "in an embodiment" Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner into one or more embodiments.
用以製造一非揮發性電荷捕獲記憶體元件之方法在此被描述。在下列說明中，例如特定尺寸之眾多特定細節被提出，用以提供本發明之徹底了解。本發明可被實施而沒有這些特定細節對於一熟知此項技術之人士會是顯而易見的。在其它範例中，例如圖案步驟或濕式化學清潔之熟知處理步驟未被詳細描述，用以不混淆本發明。更進一步，要了解到圖式中所示之各種實施例係說明代表，未必按比例繪製。Methods for fabricating a non-volatile charge trapping memory component are described herein. In the following description, for example, a number of specific details of a particular size are presented to provide the present invention.Clear understanding of the Ming. The invention may be practiced without these specific details being apparent to those skilled in the art. In other examples, well-known processing steps such as patterning steps or wet chemical cleaning are not described in detail to avoid obscuring the invention. Further, it is to be understood that the various embodiments shown in the drawings
在此所揭示者係一非揮發性電荷捕獲記憶體元件之製造方法。先提供具有一電荷捕獲層置於其上之基板。在一實施例中，該電荷捕獲層之一部分接著被氧化，以藉由將該電荷捕獲層曝露至一基氧化製程而於該電荷捕獲層上方形成一阻擋介電層。The disclosed herein is a method of making a non-volatile charge trapping memory element. A substrate having a charge trapping layer disposed thereon is first provided. In one embodiment, a portion of the charge trap layer is then oxidized to form a blocking dielectric layer over the charge trap layer by exposing the charge trap layer to a base oxidation process.
藉由一基氧化製程形成一介電層可較所涉及之蒸汽增長製程，也就是濕式增長製程提供更高品質之薄膜。更進一步，一批次處理腔室內所實施之基氧化製程可提供高品質薄膜而不影響一製造設備所要之產量(晶圓/小時)需求。藉由在例如大約600-900攝氏度範圍內之溫度之這類腔室容限溫度下實施該基氧化製程，該基板所容忍之熱預算及該基板上之任何其它特性直到超過1000攝氏度之典型範圍前並未受到影響。根據本發明一實施例，涉及將氫氣(H2)及氧氣(O2)流入一批次處理腔室中之基氧化製程被實施以經由一露出基板或薄膜之氧化耗用而造成一介電層之增長。在一實施例中，多個基氧化製程被實施以供給一非揮發性電荷捕獲記憶體元件一穿隧介電層及一阻擋介電層。這些介電層可以是非常高品質，甚至在厚度減少下亦然。在一實施例中，該穿隧介電層及該阻擋介電層兩者係較密且相較於濕式氧化技術所形成之穿隧介電層及阻擋介電層，實質上每立方公分由更少之氫原子所構成。根據本發明另一實施例，藉由實施一基氧化製程所形成之介電層係較不會受到它成長所在基板內之結晶平面方位差所影響。在一實施例中，不同結晶平面氧化速率所引起之銳角效應係藉由透過一基氧化製程所形成之介電層而顯著地減少。Forming a dielectric layer by a base oxidation process provides a higher quality film than the steam growth process involved, that is, the wet growth process. Furthermore, the base oxidation process performed in a batch of processing chambers provides high quality films without affecting the throughput (wafer/hour) requirements of a manufacturing facility. By performing the radical oxidation process at such chamber tolerance temperatures, for example, at temperatures in the range of about 600-900 degrees Celsius, the thermal budget tolerated by the substrate and any other characteristics on the substrate up to a typical range of more than 1000 degrees Celsius Not affected before. According to an embodiment of the invention, a base oxidation process involving the flow of hydrogen (H2) and oxygen (O2) into a batch of processing chambers is performed to cause a dielectric layer via an oxidizing dissipation of an exposed substrate or film. increase. In one embodiment, a plurality of base oxidation processes are implemented to supply a non-volatile charge trapping memory component, a tunneling dielectric layer, and a blocking dielectric layer. These dielectric layers can be of very high quality, even with reduced thickness. In one embodiment, both the tunneling dielectric layer and the blocking dielectric layer are denser than the tunneling dielectric layer and the blocking dielectric layer formed by the wet oxidation technique, substantially per cubic centimeter It consists of fewer hydrogen atoms. According to another embodiment of the present invention, the dielectric layer formed by performing a base oxidation process is less affected by the crystal plane orientation difference in the substrate in which it grows.influences. In one embodiment, the acute angle effect caused by the different crystal plane oxidation rates is significantly reduced by the dielectric layer formed by a radical oxidation process.
一非揮發性電荷捕獲記憶體元件之一部分可藉由在一製程腔室內實施一基氧化製程而被製造。在根據本發明一實施例中，該製程腔室係一批次處理腔室。圖2根據那個實施例說明一批次處理工具之氧化腔室剖面圖。參考至圖2，一批次處理腔室200包含持有複數個半導體晶圓202之載子設備204。在一實施例中，該批次處理腔室係一氧化腔室。在一特定實施例中，該製程腔室係一低壓化學氣相沉積腔室。該複數個半導體晶圓202可以在能夠納入的合理晶圓數量(例如25個晶圓)的同時，極大化每一個晶圓對一基氧化製程之曝露以進行一次操作處理之這類方式來安排之。然而，應了解到本發明並未限定至一批次處理腔室。A portion of a non-volatile charge trapping memory component can be fabricated by performing a base oxidation process in a process chamber. In an embodiment in accordance with the invention, the process chamber is a batch of processing chambers. Figure 2 illustrates a cross-sectional view of an oxidation chamber of a batch processing tool in accordance with that embodiment. Referring to FIG. 2, a batch of processing chamber 200 includes a carrier device 204 holding a plurality of semiconductor wafers 202. In one embodiment, the batch processing chamber is an oxidation chamber. In a particular embodiment, the process chamber is a low pressure chemical vapor deposition chamber. The plurality of semiconductor wafers 202 can be arranged in such a manner as to maximize the number of wafers that can be incorporated (for example, 25 wafers) while maximizing the exposure of each wafer to a base oxidation process for one operation. It. However, it should be understood that the invention is not limited to a batch of processing chambers.
在本發明一觀點中，一非揮發性電荷捕獲記憶體元件之一部分係藉由一基氧化製程來製造。圖3根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作流程圖。圖4A-4B根據本發明一實施例說明代表製造一非揮發性電荷捕獲記憶體元件之操作。In one aspect of the invention, a portion of a non-volatile charge trapping memory component is fabricated by a base oxidation process. 3 illustrates a series of operational flow diagrams in a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention. 4A-4B illustrate an operation representative of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention.
圖4A根據本發明一實施例說明對應至圖3流程圖中之操作302之具有一電荷捕獲層形成於其上之基板剖面圖。參考至流程圖300之操作302及相對應圖4A，提供具有一電荷捕獲層置於其上之基板400。在一實施例中，該電荷捕獲層具有一第一區域404A及一第二區域404B置於基板400上方。在一實施例中，一介電層402係如圖4A所述地置於基板400及該電荷捕獲層之間。該電荷捕獲層可由一材料所構成且具有適合儲存電荷之厚度，並因此改變接著形成閘極堆疊之臨界電壓。在一實施例中，該電荷捕獲層之區域404A會保留成為接著後續製程操作之完整無缺電荷捕獲層。然而，在那個實施例中，該增加形成之電荷捕獲層之區域404B會被耗用以在區域404A上方形成一第二介電層。4A illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon corresponding to operation 302 of the flow chart of FIG. 3, in accordance with an embodiment of the present invention. Referring to operation 302 of flowchart 300 and corresponding FIG. 4A, a substrate 400 having a charge trapping layer disposed thereon is provided. In one embodiment, the charge trap layer has a first region 404A and a second region 404B disposed above the substrate 400. In one embodiment, a dielectric layer 402 is placed between the substrate 400 and the charge trapping layer as described in FIG. 4A. The charge trap layer can be composed of a material and has a thickness suitable for storing charge and thus a threshold voltage that subsequently forms a gate stack. In an embodiment, theRegion 404A of the charge trapping layer will remain intact as a complete charge trapping layer for subsequent processing operations. However, in that embodiment, the region 404B of the increased charge trapping layer is consumed to form a second dielectric layer over region 404A.
圖4B根據本發明一實施例說明對應至圖3流程圖之操作304之具有包含一阻擋介電層形成於其上之電荷捕獲層之基板剖面圖。參考至流程圖300之操作304及相對應圖4B，一阻擋介電層406係形成於電荷捕獲層404上。根據本發明一實施例，阻擋介電層406係藉由曝露該電荷捕獲層至一基氧化製程而由該電荷捕獲層之氧化區域404B所形成。在那個實施例中，該原始電荷捕獲層之區域404A現在被標示為電荷捕獲層404。4B illustrates a cross-sectional view of a substrate having a charge trapping layer having a blocking dielectric layer formed thereon corresponding to operation 304 of the flow chart of FIG. 3, in accordance with an embodiment of the present invention. Referring to operation 304 of flowchart 300 and corresponding FIG. 4B, a blocking dielectric layer 406 is formed over charge trap layer 404. According to an embodiment of the invention, the blocking dielectric layer 406 is formed by the oxidized region 404B of the charge trapping layer by exposing the charge trapping layer to a radical oxidation process. In that embodiment, the region 404A of the original charge trap layer is now labeled as charge trap layer 404.
阻擋介電層406可由一材料所構成且具有適合對漏電維持一障礙卻不顯著地降低在接著形成於一非揮發性電荷捕獲記憶體元件內之閘極堆疊電容之厚度。在一特定實施例中，區域404B係具有大約在2-3奈米範圍厚度之含矽之氮氧化矽區域並被氧化以形成具有大約在3.5-4.5奈米範圍之厚度之阻擋介電層。在那個實施例中，阻擋介電層406係由二氧化矽所構成。The blocking dielectric layer 406 can be comprised of a material and has a thickness suitable for maintaining a barrier to leakage without significantly reducing the gate stack capacitance subsequently formed in a non-volatile charge trapping memory component. In a particular embodiment, region 404B is a germanium containing niobium oxide region having a thickness in the range of about 2-3 nanometers and is oxidized to form a barrier dielectric layer having a thickness in the range of about 3.5-4.5 nanometers. In that embodiment, the blocking dielectric layer 406 is comprised of cerium oxide.
阻擋介電層406可藉由一基氧化製程來形成。在根據本發明一實施例中，該基氧化製程涉及將氫氣及氧氣流入例如連結圖2所述批次處理腔室200之熔爐中。在一實施例中，氫氣及氧氣分壓彼此間具有大約1：1的比值。然而，在一實施例中，一燃燒事件並未實現，其在其它方面典型地會被使用以熱分解氫氣及氧氣來形成蒸汽。替代性地，允許氫氣及氧氣作用以在區域404B表面處形成自由基。在一實施例中，該些自由基被使用以耗用區域404B以提供阻擋介電層406。在一特定實施例中，該基氧化製程包含在大約600-900攝氏度範圍溫度下利用例如一氫氧基、一氫過氧基或一氧二基之自由基來進行氧化，但不限於此。在一具體實施例中，該基氧化製程係實施於大約700-800攝氏度範圍之溫度及大約0.5-5托耳範圍之壓力下。在一實施例中，該第二基氧化製程係實施大約100-150分鐘範圍之持續時間。The blocking dielectric layer 406 can be formed by a base oxidation process. In an embodiment in accordance with the invention, the base oxidation process involves flowing hydrogen and oxygen into a furnace, such as the batch processing chamber 200 of FIG. In one embodiment, the hydrogen and oxygen partial pressures have a ratio of about 1:1 to each other. However, in one embodiment, a combustion event is not achieved, which is otherwise typically used to thermally decompose hydrogen and oxygen to form steam. Alternatively, hydrogen and oxygen are allowed to act to form free radicals at the surface of region 404B. In one embodiment, the free radicals are used to consume region 404B to provide a blocking dielectric layer 406. In a particular embodiment, the base oxidationThe process comprises oxidizing using a radical such as monohydric oxy, monohydroperoxy or monooxydiyl at a temperature in the range of about 600-900 degrees Celsius, but is not limited thereto. In one embodiment, the base oxidation process is carried out at a temperature in the range of about 700-800 degrees Celsius and a pressure in the range of about 0.5-5 Torr. In one embodiment, the second base oxidation process is carried out for a duration ranging from about 100 to 150 minutes.
參考至流程圖300之操作306，阻擋介電層406可進一步在該第一製程腔室內承受一氮化製程。根據本發明一實施例，該氮化製程包含在大約700-800攝氏度範圍溫度下及大約5分鐘-60分鐘範圍持續時間內，於一含氮大氣中回火阻擋介電層406。在一實施例中，該含氮大氣係由例如氮氣(N2)、氧化亞氮(N2O)、二氧化氮(NO2)、氧化氮(NO)或氨(NH3)之氣體所構成，但不限於此。替代性地，本氮化步驟，也就是來自流程圖300之操作306，可被略過。Referring to operation 306 of flowchart 300, blocking dielectric layer 406 can be further subjected to a nitridation process within the first process chamber. In accordance with an embodiment of the invention, the nitridation process comprises temper blocking the dielectric layer 406 in a nitrogen-containing atmosphere at a temperature in the range of about 700-800 degrees Celsius and for a duration of between about 5 minutes and 60 minutes. In one embodiment, the nitrogen-containing atmosphere is composed of, but not limited to, a gas such as nitrogen (N 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), nitrogen oxide (NO), or ammonia (NH 3 ). this. Alternatively, the nitriding step, that is, operation 306 from flowchart 300, may be skipped.
在本發明一觀點中，一穿隧介電層及一阻擋介電層兩者可藉由一基氧化製程來形成。圖5根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作流程圖500。圖6A-6E根據本發明一實施例說明代表製造一非揮發性電荷捕獲記憶體元件之操作。In one aspect of the invention, both a tunneling dielectric layer and a blocking dielectric layer can be formed by a base oxidation process. FIG. 5 illustrates a series of operational flowcharts 500 representative of a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention. 6A-6E illustrate an operation representative of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention.
圖6A根據本發明一實施例說明對應至圖5流程圖中之操作502之基板剖面圖。參考至流程圖500之操作502及相對應圖6A，一基板600被提供於一製程腔室內。Figure 6A illustrates a cross-sectional view of a substrate corresponding to operation 502 of the flow chart of Figure 5, in accordance with an embodiment of the present invention. Referring to operation 502 of flowchart 500 and corresponding FIG. 6A, a substrate 600 is provided in a process chamber.
基板600可由適合用於半導體元件製造之材料所構成。在一實施例中，基板600係一本體基板，由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料之單一結晶材料所構成，但不限於此。在另一實施例中，基板600包含具有一頂部磊晶層之本體層。在一特定實施例中，該本體層係由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料或石英之單一結晶材料所構成，但不限於此，而該頂部磊晶層係由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料之單一結晶層所構成，但不限於此。在另一實施例中，基板600包含位於一下方本體層之上之中間絕緣體層上的頂部磊晶層。該頂部磊晶層係由可包含矽(也就是，用以形成絕緣體上矽(SOI)半導體基板)、鍺、矽-鍺或一III-V族化合物半導體材料之單一結晶層所構成，但不限於此。該絕緣體層係由可包含二氧化矽、氮化矽或氮氧化矽之材料所構成，但不限於此。該下方本體層係由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料或石英之單一結晶材料所構成，但不限於此。基板600可進一步包含摻雜物之雜質原子。The substrate 600 may be composed of a material suitable for the manufacture of semiconductor elements. In one embodiment, the substrate 600 is a body substrate composed of a single crystalline material that may comprise yttrium, lanthanum, ytterbium, or a group III-V compound semiconductor material, but is not limited thereto. In another embodiment,Substrate 600 includes a body layer having a top epitaxial layer. In a specific embodiment, the body layer is composed of a single crystalline material that may comprise yttrium, lanthanum, ytterbium, or a group III-V compound semiconductor material or quartz, but is not limited thereto, and the top epitaxial layer It is composed of a single crystal layer which may contain yttrium, lanthanum, ytterbium-tellurium or a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 600 includes a top epitaxial layer on an intermediate insulator layer over a lower body layer. The top epitaxial layer is composed of a single crystal layer which may comprise germanium (that is, a germanium-on-insulator (SOI) semiconductor substrate), germanium, germanium-tellurium or a group III-V compound semiconductor material, but not Limited to this. The insulator layer is composed of a material which may include cerium oxide, cerium nitride or cerium oxynitride, but is not limited thereto. The lower body layer is composed of a single crystalline material which may comprise yttrium, lanthanum, ytterbium or a group III-V compound semiconductor material or quartz, but is not limited thereto. The substrate 600 may further include impurity atoms of the dopant.
圖6B根據本發明一實施例說明對應至圖5流程圖中之操作504之具有一第一介電層形成於其上之基板剖面圖。參考至流程圖500之操作504及相對應圖6B，基板600係承受一第一基氧化製程以形成一第一介電層602。6B illustrates a cross-sectional view of a substrate having a first dielectric layer formed thereon corresponding to operation 504 of the flow chart of FIG. 5, in accordance with an embodiment of the present invention. Referring to operation 504 of flowchart 500 and corresponding FIG. 6B, substrate 600 is subjected to a first radical oxidation process to form a first dielectric layer 602.
第一介電層602可由一材料所構成且具有一適合厚度以在一施加閘極偏壓下，讓電荷載子穿隧至接著形成之電荷捕獲層，而在未施加偏壓於接著形成之非揮發性電荷捕獲記憶體元件時，對漏電維持一合適障礙。第一介電層602在習知技術中可稱之為穿隧介電層。根據本發明一實施例，第一介電層602係由一氧化製程所形成，其中，該基板600之頂部表面被耗用。因此，在一實施例中，介電層602係由基板600之材料之氧化物所構成。例如，在一實施例中，基板600係由矽所構成且第一介電層602係由二氧化矽所構成。在一特定實施例中，所形成第一介電層602之厚度係大約在1-10奈米範圍內。在一具體實施例中，所形成第一介電層602之厚度係大約在1.5-2.5奈米範圍內。The first dielectric layer 602 can be formed of a material and has a suitable thickness to allow the charge carriers to tunnel to the subsequently formed charge trapping layer under an applied gate bias, without being biased to form subsequently. Non-volatile charge trapping memory components maintains a suitable barrier to leakage. The first dielectric layer 602 may be referred to as a tunneling dielectric layer in the prior art. According to an embodiment of the invention, the first dielectric layer 602 is formed by an oxidation process in which the top surface of the substrate 600 is consumed. Thus, in one embodiment, the dielectric layer 602 is comprised of an oxide of material of the substrate 600. For example, in one embodiment, substrate 600 is comprised of germanium and first dielectric layer 602It is composed of cerium oxide. In a particular embodiment, the thickness of the first dielectric layer 602 formed is in the range of about 1-10 nanometers. In one embodiment, the thickness of the first dielectric layer 602 formed is in the range of about 1.5-2.5 nanometers.
第一介電層602可藉由一基氧化製程來形成。在根據本發明一實施例中，該基氧化製程涉及將氫氣(H2)及氧氣(O2)流入例如連結圖2所述批次處理腔室200之熔爐中。在一實施例中，氫氣及氧氣分壓彼此間具有大約1：1的比值。然而，在一實施例中，一燃燒事件並未實現，其在其它方面典型地會被使用以熱分解氫氣及氧氣來形成蒸汽。替代性地，氫氣及氧氣係可起反應以在基板600表面處形成自由基。在一實施例中，該些自由基被使用以耗用基板600之頂部以提供第一介電層602。在一特定實施例中，該基氧化製程包含在大約600-900攝氏度範圍溫度下利用例如一氫氧基、一氫過氧基或一氧二基之自由基來進行氧化，但不限於此。在一具體實施例中，該基氧化製程係實施於大約700-800攝氏度範圍溫度及大約0.5-5托耳範圍壓力下。在一實施例中，該基氧化製程係實施大約100-150分鐘範圍之持續時間。根據本發明一實施例，第一介電層602係形成為一高密度、低氫含量之薄膜。The first dielectric layer 602 can be formed by a base oxidation process. In an embodiment in accordance with the invention, the base oxidation process involves flowing hydrogen (H2) and oxygen (O2) into a furnace, such as the batch processing chamber 200 of FIG. In one embodiment, the hydrogen and oxygen partial pressures have a ratio of about 1:1 to each other. However, in one embodiment, a combustion event is not achieved, which is otherwise typically used to thermally decompose hydrogen and oxygen to form steam. Alternatively, hydrogen and oxygen may react to form free radicals at the surface of the substrate 600. In one embodiment, the free radicals are used to consume the top of the substrate 600 to provide the first dielectric layer 602. In a particular embodiment, the base oxidation process comprises oxidizing using a radical such as monohydric oxy, monohydroperoxy or monooxydiyl at a temperature in the range of about 600-900 degrees Celsius, but is not limited thereto. In one embodiment, the base oxidation process is carried out at a temperature in the range of about 700-800 degrees Celsius and at a pressure in the range of about 0.5-5 Torr. In one embodiment, the base oxidation process is carried out for a duration ranging from about 100 to 150 minutes. According to an embodiment of the invention, the first dielectric layer 602 is formed as a high density, low hydrogen content film.
參考至流程圖500之操作506，形成第一介電層602之後，且在任何進一步處理之前，第一介電層602可承受一氮化製程。在一實施例中，該氮化製程係實施於與形成第一介電層502所使用之相同製程腔室內，在製程步驟間並未將基板600自該製程腔室中移除。在一實施例中，該回火包含在大約700-800攝氏度範圍溫度下及大約5分鐘-60分鐘範圍持續時間內，於一含氮大氣中加熱基板600。在一實施例中，該含氮大氣係由例如氮氣(N2)、氧化亞氮(N2O)、二氧化氮(NO2)、氧化氮(NO)或氨(NH3)之氣體所構成，但不限於此。在一實施例中，該氮化作用發生於該第一基氧化製程後之製程腔室之氮或氬清除後。替代性地，上述氮化步驟可被略過。Referring to operation 506 of flowchart 500, after forming first dielectric layer 602, and prior to any further processing, first dielectric layer 602 can be subjected to a nitridation process. In one embodiment, the nitridation process is performed in the same process chamber as used to form the first dielectric layer 502, and the substrate 600 is not removed from the process chamber between process steps. In one embodiment, the tempering comprises heating the substrate 600 in a nitrogen-containing atmosphere at a temperature in the range of about 700-800 degrees Celsius and for a duration of between about 5 minutes and 60 minutes. In one embodiment, the nitrogen-containing atmosphere is made of a gas such as nitrogen (N2 ), nitrous oxide (N2 O), nitrogen dioxide (NO2 ), nitrogen oxides (NO), or ammonia (NH3 ). Composition, but not limited to this. In one embodiment, the nitriding occurs after nitrogen or argon removal of the process chamber after the first base oxidation process. Alternatively, the above nitridation step can be skipped.
圖6C根據本發明一實施例說明對應至圖5流程圖中之操作508之具有一電荷捕獲層形成於其上之基板剖面圖。參考至流程圖500之操作508及相對應圖6C，具有一第一區域604A及一第二區域604B之電荷捕獲層係形成於第一介電層602上。在一實施例中，該電荷捕獲層之形成係實施於與形成第一介電層602所使用之相同製程腔室內，在製程步驟間並未將基板600自該製程腔室中移除。6C illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon corresponding to operation 508 of the flow chart of FIG. 5, in accordance with an embodiment of the present invention. Referring to operation 508 of flowchart 500 and corresponding FIG. 6C, a charge trapping layer having a first region 604A and a second region 604B is formed on first dielectric layer 602. In one embodiment, the formation of the charge trapping layer is performed in the same process chamber as used to form the first dielectric layer 602, and the substrate 600 is not removed from the process chamber between process steps.
該電荷捕獲層可由一材料所構成且具有適合儲存電荷並因此改變接著形成之閘極堆疊臨界電壓之厚度。根據本發明一實施例，該電荷捕獲層係由如圖6C所述之二區域604A及604B所構成。在一實施例中，該電荷捕獲層之區域604A會保留做為後續製程操作之完整無缺電荷捕獲層。然而，在那個實施例中，該增加形成之電荷捕獲層之區域604B會被耗用以在區域604A上方形成一第二介電層。The charge trap layer can be composed of a material and has a thickness suitable for storing charge and thus changing the threshold voltage of the subsequently formed gate stack. According to an embodiment of the invention, the charge trapping layer is formed by two regions 604A and 604B as described in FIG. 6C. In one embodiment, the region 604A of the charge trapping layer remains as a complete, uncharged charge trapping layer for subsequent processing operations. However, in that embodiment, the region 604B of the increased charge trapping layer is consumed to form a second dielectric layer over region 604A.
具有區域604A及604B之電荷捕獲層可藉由一化學氣相沉積製程來形成。根據本發明一實施例，該電荷捕獲層係由例如氮化矽、氮氧化矽、含氧之氮氧化矽或含氮之氮氧化矽所構成，但不限於此。在一實施例中，該電荷捕獲層之604A及604B係形成於大約600-800攝氏度範圍溫度下。在一特定實施例中，該電荷捕獲層係使用例如二氯矽烷、雙三級丁氨基矽烷(BTBAS)、氨(NH3)或氧化亞氮(N2O)之氣體來形成，但不限於此。在一實施例中，該電荷捕獲層係形成大約5-15奈米範圍之總厚度，區域604B佔有大約該電荷捕獲層總厚度之2-3奈米範圍厚度。在那個實施例中，區域604A佔有該電荷捕獲層之其餘總厚度，也就是，區域604A佔有該電荷捕獲層中，未被接著耗用以形成一頂部或阻擋介電層的部分。The charge trapping layer having regions 604A and 604B can be formed by a chemical vapor deposition process. According to an embodiment of the invention, the charge trapping layer is composed of, for example, tantalum nitride, lanthanum oxynitride, cerium oxide containing oxygen or cerium oxynitride containing nitrogen, but is not limited thereto. In one embodiment, the charge trapping layers 604A and 604B are formed at a temperature in the range of about 600-800 degrees Celsius. In a particular embodiment, the charge trapping layer is formed using, but not limited to, a gas such as dichlorodecane, di-tertiary butylaminodecane (BTBAS), ammonia (NH3 ), or nitrous oxide (N2 O). this. In one embodiment, the charge trapping layer forms a total thickness in the range of about 5-15 nm, and the region 604B occupies a thickness in the range of about 2-3 nm of the total thickness of the charge trapping layer. In that embodiment, region 604A occupies the remaining total thickness of the charge trap layer, that is, region 604A occupies a portion of the charge trap layer that is not subsequently consumed to form a top or barrier dielectric layer.
在本發明另一觀點中，該電荷捕獲層可包含多個組成成分區域。例如，根據本發明一實施例，該電荷捕獲層包含一含氧部分及一含矽部分並藉由一第一氣體組成成分來沉積一含氧之氮氧化物薄膜和接著藉由一第二氣體組成成分來沉積一含矽之氮氧化物薄膜而形成。在一實施例中，該電荷捕獲層係藉由改變氨(NH3)氣體流速並引進氧化亞氮(N2O)和二氯矽烷來提供該些要求氣體比值，以先產生一含氧之氮氧化物薄膜，再接著產生一含矽之氮氧化物薄膜而形成。在一特定實施例中，該含氧之氮氧化物薄膜係藉由引進包含氧化亞氮、氨及二氯矽烷之製程氣體混合物，同時將該製程腔室維持在大約5-500毫托耳範圍壓力下，並將基板600維持在大約700-850攝氏度範圍溫度下，持續一段大約2.5-20分鐘範圍之時間而形成。在一進一步實施例中，該製程氣體混合物包含具有約從8：1至1：8比值之氧化亞氮和氨，及具有約從1：7至7：1比值之二氯矽烷和氨，且可以大約每分鐘5-200標準立方公分(sccm)範圍之流速來引進。在另一特定實施例中，該含矽氮氧化物薄膜係藉由引進包含氧化亞氮、氨及二氯矽烷之製程氣體混合物，同時將該腔室維持在大約5-500毫托耳範圍壓力下，並將基板600維持在大約700-850攝氏度範圍溫度下，持續一段大約2.5-20分鐘範圍之時間而形成。在一進一步實施例中，該製程氣體混合物包含具有約從8：1至1：8比值之氧化亞氮和氨，及以約從1：7至7：1比值混合之二氯矽烷和氨，以大約每分鐘5至20標準立方公分之流速來引進。根據本發明一實施例，該電荷捕獲層包括具有大約2.5-3.5奈米範圍厚度之底部含氧氮氧化矽部分及具有大約9-10奈米範圍厚度之頂部含矽氮氧化矽部分。在一實施例中，電荷捕獲層之區域504B佔有該電荷捕獲層之頂部含矽氮氧化矽部分之總厚度大約2-3奈米範圍厚度。因此，針對接著耗用以形成一第二介電層所預定之區域604B可完全由含矽氮氧化矽來構成之。In another aspect of the invention, the charge trap layer may comprise a plurality of constituent regions. For example, in accordance with an embodiment of the present invention, the charge trapping layer includes an oxygen-containing portion and a germanium-containing portion and deposits an oxygen-containing oxynitride film by a first gas component and then a second gas The composition is formed by depositing a film of ruthenium-containing oxynitride. In one embodiment, the charge trapping layer provides the desired gas ratio by varying the ammonia (NH3) gas flow rate and introducing nitrous oxide (N2O) and dichlorosilane to produce an oxygenated nitrogen oxide. The film is then formed by the formation of a film of ruthenium oxide containing ruthenium. In a specific embodiment, the oxygen-containing oxynitride film is maintained at a process temperature of about 5 to 500 mTorr by introducing a process gas mixture comprising nitrous oxide, ammonia, and methylene chloride. The substrate 600 is formed under pressure and maintained at a temperature in the range of about 700-850 degrees Celsius for a period of about 2.5-20 minutes. In a further embodiment, the process gas mixture comprises nitrous oxide and ammonia having a ratio of from about 8:1 to 1:8, and dichloromethane and ammonia having a ratio of from about 1:7 to 7:1, and It can be introduced at a flow rate in the range of about 5 to 200 standard cubic centimeters (sccm) per minute. In another specific embodiment, the ruthenium-containing oxynitride film is maintained at a pressure in the range of about 5 to 500 mTorr by introducing a process gas mixture comprising nitrous oxide, ammonia, and methylene chloride. Next, the substrate 600 is maintained at a temperature in the range of about 700-850 degrees Celsius for a period of time ranging from about 2.5-20 minutes. In a further embodiment, the process gas mixture comprises nitrous oxide and ammonia having a ratio of from about 8:1 to 1:8, and dichloromethane and ammonia mixed at a ratio of from about 1:7 to 7:1, Introduced at a flow rate of approximately 5 to 20 standard cubic centimeters per minute. According to this issueIn a preferred embodiment, the charge trapping layer comprises a bottom oxynitride oxide moiety having a thickness in the range of about 2.5-3.5 nm and a top germanium containing niobium oxynitride moiety having a thickness in the range of about 9-10 nm. In one embodiment, the region 504B of the charge trapping layer occupies a thickness in the range of about 2-3 nm of the total thickness of the niobium oxynitride portion at the top of the charge trap layer. Therefore, the region 604B predetermined for the subsequent formation of a second dielectric layer can be completely composed of yttrium oxide containing lanthanum oxynitride.
圖6D根據本發明一實施例說明對應至圖5流程圖之操作510之具有一第二介電層形成於其上之基板剖面圖。參考至流程圖500之操作510及相對應圖6D，一第二介電層606係形成於電荷捕獲層604上。在一實施例中，該第二介電層606之形成係實施於與形成第一介電層602和該電荷捕獲層604所使用之相同製程腔室內，在製程步驟間並未將基板600自該製程腔室中移除。在一實施例中，該第二基氧化製程係實施於該電荷捕獲層沉積後之製程腔室之氮或氬清除後。6D illustrates a cross-sectional view of a substrate having a second dielectric layer formed thereon corresponding to operation 510 of the flow chart of FIG. 5, in accordance with an embodiment of the present invention. Referring to operation 510 of flowchart 500 and corresponding FIG. 6D, a second dielectric layer 606 is formed over charge trap layer 604. In one embodiment, the second dielectric layer 606 is formed in the same process chamber as that used to form the first dielectric layer 602 and the charge trap layer 604. The substrate 600 is not used in the process step. The process chamber is removed. In one embodiment, the second base oxidation process is performed after nitrogen or argon removal of the process chamber after deposition of the charge trap layer.
第二介電層606可一材料所構成且具有對漏電維持一合適障礙卻不顯著地降低接著形成於一非揮發性電荷捕獲記憶體元件內之閘極堆疊電容之厚度。第二介電層606於習知技術中可稱之為一阻擋介電層或一頂部介電層。根據本發明一實施例，第二介電層606係藉由耗用連結圖6C所述操作508所形成之電荷捕獲層之區域604B而形成。因此，在一實施例中，區域604B被耗用以提供第二介電層606，而區域604A保留一電荷捕獲層。在一特定實施例中，區域604B係具有大約2-3奈米範圍厚度之含矽氮氧化矽，並被氧化以形成具有大約3.5-4.5奈米範圍厚度之第二介電層606。在一那個實施例中，第二介電層606係由二氧化矽所構成。根據本發明一實施例，第二介電層606係由一第二基氧化製程所形成，類似於連結圖4B所述之實施該基氧化製程以形成阻擋介電層406。在一實施例中，參考至流程圖500之操作512，形成第二介電層606後，接著第二介電層606係進一步承受一氮化製程，類似於連結流程圖500之操作506所述之氮化製程。在一特定實施例中，該氮化作用發生於該第二基氧化製程後之製程腔室之氮或氬清除後。替代性地，本氮化步驟可被略過。根據本發明一實施例，沒有額外沉積製程被使用於第二介電層606之形成。The second dielectric layer 606 can be constructed of a material and has a suitable barrier to leakage while not significantly reducing the thickness of the gate stack capacitance that is subsequently formed in a non-volatile charge trapping memory component. The second dielectric layer 606 can be referred to as a blocking dielectric layer or a top dielectric layer in the prior art. In accordance with an embodiment of the invention, the second dielectric layer 606 is formed by consuming a region 604B of the charge trapping layer formed by operation 508 of FIG. 6C. Thus, in one embodiment, region 604B is consumed to provide a second dielectric layer 606 while region 604A retains a charge trapping layer. In a particular embodiment, region 604B is tantalum oxynitride having a thickness in the range of about 2-3 nanometers and is oxidized to form a second dielectric layer 606 having a thickness in the range of about 3.5-4.5 nanometers. In one embodiment, the second dielectric layer 606 is comprised of hafnium oxide. According to an embodiment of the invention, the second dielectric layer 606 is formed by a second base oxidation process, similar to the link.The base oxidation process is performed as described in FIG. 4B to form a blocking dielectric layer 406. In one embodiment, referring to operation 512 of flowchart 500, after forming second dielectric layer 606, second dielectric layer 606 is further subjected to a nitridation process, similar to operation 506 of connection flow diagram 500. Nitriding process. In a particular embodiment, the nitriding occurs after nitrogen or argon removal of the process chamber after the second base oxidation process. Alternatively, the present nitridation step can be skipped. According to an embodiment of the invention, no additional deposition process is used for the formation of the second dielectric layer 606.
因此，根據本發明一實施例，包含第一介電層602、電荷捕獲層604及第二介電層606之氧化物-氮化物-氧化物堆疊係以一次操作形成於一製程腔室內。藉由一次操作該製程腔室內之多個晶圓來製造這些層，高產量要求可被滿足而仍能確保非常高品質薄膜之形成。依據包含第一介電層602、電荷捕獲層604及第二介電層606之氧化物-氮化物-氧化物堆疊製造，一非揮發性電荷捕獲記憶體元件可被製造以包含該氧化物-氮化物-氧化物堆疊之圖案化部分。圖6E根據本發明一實施例說明一非揮發性電荷捕獲記憶體元件之剖面圖。Thus, in accordance with an embodiment of the invention, an oxide-nitride-oxide stack comprising a first dielectric layer 602, a charge trap layer 604, and a second dielectric layer 606 is formed in a process chamber in a single operation. By fabricating these layers in a single operation of multiple wafers within the process chamber, high throughput requirements can be met while still ensuring the formation of very high quality films. Manufactured from an oxide-nitride-oxide stack comprising a first dielectric layer 602, a charge trap layer 604, and a second dielectric layer 606, a non-volatile charge trapping memory element can be fabricated to include the oxide- A patterned portion of a nitride-oxide stack. 6E illustrates a cross-sectional view of a non-volatile charge trapping memory component in accordance with an embodiment of the present invention.
參考至圖6E，一非揮發性電荷捕獲記憶體元件包含形成於基板600上方之氧化物-氮化物-氧化物堆疊之圖案化部分。該氧化物-氮化物-氧化物堆疊包含第一介電層602、電荷捕獲層604及第二介電層606。一閘極層608係置於第二介電層606上。該非揮發性電荷捕獲記憶體元件進一步包含基板600內分別位於該氧化物-氮化物-氧化物堆疊一側上之源極和汲極區域612，以定義該氧化物-氮化物-氧化物堆疊下之基板600內之通道區域614。一對介電間隔側壁610隔離第一介電層602、電荷捕獲層604、第二介電層606及閘極層608之側壁。在一特定實施例中，通道區域614係為P型摻雜，而在一替代性實施例中，通道區域614係N型摻雜。Referring to FIG. 6E, a non-volatile charge trapping memory component includes a patterned portion of an oxide-nitride-oxide stack formed over substrate 600. The oxide-nitride-oxide stack includes a first dielectric layer 602, a charge trap layer 604, and a second dielectric layer 606. A gate layer 608 is placed over the second dielectric layer 606. The non-volatile charge trapping memory component further includes source and drain regions 612 on the side of the oxide-nitride-oxide stack in the substrate 600 to define the oxide-nitride-oxide stack Channel region 614 within substrate 600. A pair of dielectric spacer sidewalls 610 isolate sidewalls of the first dielectric layer 602, the charge trapping layer 604, the second dielectric layer 606, and the gate layer 608. In a particular embodiment, channel region 614 is P-typeDoping, while in an alternative embodiment, channel region 614 is N-doped.
根據本發明一實施例，連結圖6E所述之非揮發性電荷捕獲記憶體元件係一半導體-氧化物-氮化物-氧化物-半導體型元件。按照慣例，SONOS代表“半導體-氧化物-氮化物-氧化物-半導體”，其中，該第一個“半導體”參考至該通道區域材料，該第一個“氧化物”參考至該穿隧介電層，“氮化物”參考至該電荷捕獲介電層，該第二個“氧化物”參考至該頂部介電層(也是已知之阻擋介電層)，以及該第二個“半導體”參考至該閘極層。因此，根據本發明一實施例，第一介電層602係一穿隧介電層，且第二介電層606係一阻擋介電層。According to an embodiment of the invention, the non-volatile charge trapping memory component described in connection with FIG. 6E is a semiconductor-oxide-nitride-oxide-semiconductor type component. Conventionally, SONOS stands for "semiconductor-oxide-nitride-oxide-semiconductor", wherein the first "semiconductor" is referenced to the channel region material, and the first "oxide" is referenced to the tunneling dielectric An electrical layer, "nitride" is referenced to the charge trapping dielectric layer, the second "oxide" is referenced to the top dielectric layer (also known as a blocking dielectric layer), and the second "semiconductor" reference To the gate layer. Therefore, according to an embodiment of the invention, the first dielectric layer 602 is a tunneling dielectric layer, and the second dielectric layer 606 is a blocking dielectric layer.
閘極層608可由適合在一半導體-氧化物-氮化物-氧化物-半導體型電晶體操作期間提供一偏壓之任何導體或半導體材料所構成。根據本發明一實施例，閘極層608係經由一化學氣相沉積製程所形成且由摻雜多晶矽所構成。在另一實施例中，閘極層608係經由物理氣相沉積製程所形成且由可包含金屬氮化物、金屬碳化物、金屬矽化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷或鎳之含金屬材料所構成，但不限於此。Gate layer 608 can be constructed of any conductor or semiconductor material suitable for providing a bias during operation of a semiconductor-oxide-nitride-oxide-semiconductor type of transistor. In accordance with an embodiment of the invention, the gate layer 608 is formed via a chemical vapor deposition process and is comprised of doped polysilicon. In another embodiment, the gate layer 608 is formed by a physical vapor deposition process and may include metal nitrides, metal carbides, metal tellurides, hafnium, zirconium, titanium, hafnium, aluminum, hafnium, palladium, It is composed of a metal-containing material of platinum, cobalt or nickel, but is not limited thereto.
基板600內之源極和汲極區域612可為具有與通道區域614相反導電性之任何區域。例如，根據本發明一實施例，源極及汲極區域612係N型摻雜區域，而通道區域614係一P型摻雜區域。在一實施例中，基板600及因此所形成之通道區域614係由具有1x1015-1x1019原子/立方公分範圍硼濃度之硼摻雜單結晶矽所構成。在那個實施例中，源極及汲極區域612係由具有5x1016-5x1019原子/立方公分範圍之N型摻雜物濃度之磷或砷摻雜區域所構成。在一特定實施例中，源極及汲極區域612在基板600內具有80-200奈米範圍之深度。根據本發明一替代性實施例，源極及汲極區域612係P型摻雜區域，而通道區域614係一N型摻雜區域。The source and drain regions 612 within the substrate 600 can be any region having opposite conductivity to the channel region 614. For example, in accordance with an embodiment of the invention, the source and drain regions 612 are N-type doped regions and the channel region 614 is a P-type doped region. In one embodiment, substrate 600 and thus channel region 614 are formed of boron doped monocrystalline germanium having a boron concentration in the range of 1 x 1015 -1 x 1019 atoms per cubic centimeter. In that embodiment, the source and drain regions 612 are comprised of phosphorous or arsenic doped regions having an N-type dopant concentration in the range of 5 x10 16 - 5 x1019 atoms per cubic centimeter. In a particular embodiment, the source and drain regions 612 have a depth in the range of 80-200 nm within the substrate 600. In accordance with an alternative embodiment of the present invention, the source and drain regions 612 are P-type doped regions and the channel region 614 is an N-type doped region.
在本發明另一觀點中，經由一氧化腔室內之基板頂部表面之基氧化作用所形成之介電層在它生長於該基板上時，較不容易受到該基板內之結晶平面方位差的影響。例如，在一實施例中，不同結晶平面氧化速率所引起之銳角效應係藉由一基氧化製程所形成之介電層而顯著地降低。圖7A根據本發明一實施例說明包含第一和第二露出結晶平面之基板剖面圖。In another aspect of the present invention, the dielectric layer formed by the base oxidation of the top surface of the substrate in the oxidation chamber is less susceptible to the difference in crystal plane orientation in the substrate when it is grown on the substrate. . For example, in one embodiment, the acute angle effect caused by different crystal plane oxidation rates is significantly reduced by the dielectric layer formed by a base oxidation process. 7A illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention.
參考至圖7A，一基板700具有形成於其上之隔離區域702。基板700可由連結自圖6A基板600所述之材料所構成。隔離區域702可由適合黏接至基板700之絕緣材料所構成。基板700之一露出部分延伸超過隔離區域702之頂部表面。根據本發明一實施例，該基板700之露出部分具有一第一露出結晶平面704及一第二露出結晶平面706。在一實施例中，該第一露出結晶平面704之結晶方位係不同於該第二露出結晶平面706之結晶方位。在一特定實施例中，基板700係由矽所構成，第一露出結晶平面704具有<100>方位，且第二露出結晶平面706具有<110>方位。Referring to FIG. 7A, a substrate 700 has an isolation region 702 formed thereon. Substrate 700 can be constructed of materials described in connection with substrate 600 of FIG. 6A. The isolation region 702 can be constructed of an insulating material suitable for bonding to the substrate 700. One exposed portion of the substrate 700 extends beyond the top surface of the isolation region 702. According to an embodiment of the invention, the exposed portion of the substrate 700 has a first exposed crystal plane 704 and a second exposed crystal plane 706. In one embodiment, the crystal orientation of the first exposed crystal plane 704 is different from the crystal orientation of the second exposed crystal plane 706. In a particular embodiment, substrate 700 is constructed of tantalum, with first exposed crystalline plane 704 having a <100> orientation and second exposed crystalline plane 706 having a <110> orientation.
基板700可承受一基氧化製程以藉由耗用(氧化)該基板700之頂部表面來形成一介電層。在一實施例中，經由一基氧化製程來氧化基板700包含利用由一氫氧基、一氫過氧基或一氧二基所構成的族群中所選之自由基來進行氧化。圖7B根據本發明一實施例說明分別包含第一和第二結晶平面704和706並具有一介電層708形成於其上之基板700之剖面圖。在一實施例中，如圖7B所示地，介電層708之第一部分708A係形成於第一露出結晶平面704上，且介電層708之第二部分708B係形成於第二露出結晶平面706上。在一實施例中，介電層708之第一部分708A之厚度T1係大約等於介電層708之第二部分708B之厚度T2，即使第一露出結晶平面704和第二露出結晶平面706之結晶平面方位不同亦然。在一特定實施例中，該基板700之基氧化作用係實施於大約600-900攝氏度範圍溫度下。在一特定實施例中，該基板700之基氧化作用係實施於大約700-800攝氏度範圍溫度及大約0.5-5托耳範圍壓力下。The substrate 700 can be subjected to a base oxidation process to form a dielectric layer by consuming (oxidizing) the top surface of the substrate 700. In one embodiment, oxidizing substrate 700 via a basal oxidation process comprises oxidizing using a radical selected from the group consisting of monohydric oxy, monohydroperoxy or oxydiyl groups. 7B illustrates a cross-sectional view of a substrate 700 having first and second crystal planes 704 and 706, respectively, and having a dielectric layer 708 formed thereon, in accordance with an embodiment of the present invention. In one embodiment, as shown in FIG. 7B, the first portion 708A of the dielectric layer 708 is formed in the firstA portion of the dielectric plane 704 is exposed and a second portion 708B of the dielectric layer 708 is formed on the second exposed crystalline plane 706. In one embodiment, the thickness T1 of the first portion 708A of the dielectric layer 708 is approximately equal to the thickness T2 of the second portion 708B of the dielectric layer 708, even though the crystalline plane of the first exposed crystalline plane 704 and the second exposed crystalline plane 706 The same is true for the orientation. In a particular embodiment, the base oxidation of the substrate 700 is carried out at a temperature in the range of about 600-900 degrees Celsius. In a particular embodiment, the base oxidation of the substrate 700 is carried out at a temperature in the range of about 700-800 degrees Celsius and a pressure in the range of about 0.5-5 Torr.
因此，一種非揮發性電荷捕獲記憶體元件之製造方法已被揭示。根據本發明一實施例，提供具有一電荷捕獲層沉積於其上之基板。該電荷捕獲層之一部分接著被氧化以藉由將該電荷捕獲層曝露至一基氧化製程中而於該電荷捕獲層上方形成一阻擋介電層。Therefore, a method of fabricating a non-volatile charge trapping memory element has been disclosed. According to an embodiment of the invention, a substrate having a charge trapping layer deposited thereon is provided. A portion of the charge trap layer is then oxidized to form a blocking dielectric layer over the charge trap layer by exposing the charge trap layer to a base oxidation process.
在本發明另一觀點中，可期待使用一叢集工具以實施一基氧化製程。因此，在此所揭示者係一種非揮發性電荷捕獲記憶體元件之製造方法。一基板可先承受一第一基氧化製程以於一叢集工具之第一製程腔室內形成一第一介電層。在一實施例中，一電荷捕獲層接著係在該叢集工具之第二製程腔室內沉積於該第一介電層上方。該電荷捕獲層接著可承受一第二基氧化製程以在該電荷捕獲層上方形成一第二介電層。在一實施例中，該第二介電層係藉由氧化該叢集工具之第一製程腔室內之一部分電荷捕獲層而形成。在一特定實施例中，該叢集工具係一單晶圓叢集工具。In another aspect of the invention, it is contemplated to use a cluster tool to perform a base oxidation process. Accordingly, what is disclosed herein is a method of making a non-volatile charge trapping memory element. A substrate may be subjected to a first base oxidation process to form a first dielectric layer in the first process chamber of a cluster tool. In one embodiment, a charge trapping layer is then deposited over the first dielectric layer in a second process chamber of the cluster tool. The charge trap layer can then be subjected to a second base oxidation process to form a second dielectric layer over the charge trap layer. In one embodiment, the second dielectric layer is formed by oxidizing a portion of the charge trapping layer within the first process chamber of the cluster tool. In a particular embodiment, the cluster tool is a single wafer cluster tool.
一叢集工具腔室內之介電層形成允許該介電層生長於較批次處理腔室內一般可得之更高溫度。更進一步，一基氧化製程可被實施於該叢集工具腔室內，以做為該介電層生長之主要路徑。根據本發明一實施例，涉及將氫氣(H2)及氧氣(O2)流入一叢集工具之氧化腔室中之基氧化製程被實施以經由一露出基板或薄膜之氧化耗用來造成一介電層之增長。在一實施例中，多個基氧化製程被實施於一叢集工具之氧化腔室以供給一非揮發性電荷捕獲記憶體元件一穿隧介電層及一阻擋介電層。這些介電層可以是非常高品質，甚至在厚度減少下亦然。在一實施例中，該穿隧介電層及該阻擋介電層兩者係較密且由實質上每立方公分較一批次製程腔室內所形成之穿隧介電層及阻擋介電層更少之氫原子所構成。更進一步，相較於一批次製程腔室，在一叢集工具之氧化腔室內，一穿隧介電層及一阻擋介電層係形成於其上之基板可被曝露於一較短促溫度上升速率和穩定時間。因此，根據本發明另一實施例，對該基板熱預算之影響係藉由在一叢集工具之氧化腔室運用一基氧化製程而減少。根據本發明另一實施例，在一叢集工具之氧化腔室內實施一基氧化製程所形成之介電層係較不會受到它成長所在基板內之結晶平面方位差所影響。在一實施例中，不同結晶平面氧化速率所引起之銳角效應係藉由透過在一叢集工具之氧化腔室內所實施之基氧化製造所形成之介電層而顯著地減少。The formation of a dielectric layer within a cluster tool cavity allows the dielectric layer to grow at a higher temperature generally available in the batch processing chamber. Further, a base oxidation process can be implemented in the cluster tool chamber as the main path for the growth of the dielectric layer. According to an embodiment of the present inventionFor example, a base oxidation process involving the flow of hydrogen (H2) and oxygen (O2) into an oxidation chamber of a cluster tool is performed to cause an increase in dielectric layer via an exposed substrate or film oxidation. In one embodiment, a plurality of base oxidation processes are implemented in an oxidation chamber of a cluster tool to supply a non-volatile charge trapping memory component, a tunneling dielectric layer, and a blocking dielectric layer. These dielectric layers can be of very high quality, even with reduced thickness. In one embodiment, the tunneling dielectric layer and the blocking dielectric layer are both dense and have a tunneling dielectric layer and a blocking dielectric layer formed substantially per cubic centimeter of the batch process chamber. It consists of fewer hydrogen atoms. Further, compared to a batch of processing chambers, a substrate through which a tunneling dielectric layer and a blocking dielectric layer are formed can be exposed to a short temperature rise in an oxidation chamber of a cluster tool. Rate and settling time. Thus, in accordance with another embodiment of the present invention, the effect on the thermal budget of the substrate is reduced by applying a base oxidation process in the oxidation chamber of a cluster tool. According to another embodiment of the present invention, a dielectric layer formed by performing a base oxidation process in an oxidation chamber of a cluster tool is less affected by the difference in crystal plane orientation in the substrate in which it grows. In one embodiment, the acute angle effects caused by different crystal plane oxidation rates are significantly reduced by the formation of a dielectric layer formed by the base oxidation performed in an oxidization chamber of a cluster tool.
一非揮發性電荷捕獲記憶體元件之一部分可被製造於一叢集工具中。圖8根據本發明一實施例說明在一叢集工具內之製程腔室配置。參考至圖8，一叢集工具800之製程腔室配置包含一轉移腔室802、一第一製程腔室804、一第二製程腔室806及一第三製程腔室808。在一實施例中，轉移腔室802係用於接收來自一外部環境之晶圓以引入叢集工具800中。在一實施例中，該些製程腔室802、804及806中之每一個係以使得一晶圓可如圖8之雙箭頭所示地前後穿梭於這些腔室和轉移腔室802之間之方式來安排之。根據本發明一實施例，雖未顯示，叢集工具800可被架構以使得一晶圓可被直接轉移於製程腔室802、804及806中之任一對之間。A portion of a non-volatile charge trapping memory component can be fabricated in a cluster tool. Figure 8 illustrates a process chamber configuration within a cluster tool in accordance with an embodiment of the present invention. Referring to FIG. 8, the process chamber configuration of a cluster tool 800 includes a transfer chamber 802, a first process chamber 804, a second process chamber 806, and a third process chamber 808. In one embodiment, the transfer chamber 802 is for receiving wafers from an external environment for introduction into the cluster tool 800. In one embodiment, each of the process chambers 802, 804, and 806 is such that a wafer can be shuttled back and forth between the chambers and the transfer chamber 802 as indicated by the double arrows of FIG. Way to comeRanked. In accordance with an embodiment of the invention, although not shown, cluster tool 800 can be structured such that a wafer can be transferred directly between any of process chambers 802, 804, and 806.
叢集工具800可為將一外部環境隔絕於製程腔室804、804及806和轉移腔室802之外或之間之任何叢集工具。因此，根據本發明一實施例，一旦一晶圓已進入製程腔室802，則在它被移動至製程腔室804、804及806和轉移腔室802之內或之間時，它係隔離於一外部環境。這類叢集工具範例係由位於美國加州聖克拉拉市之應用材料公司於市場銷售之Centura®平台。在一實施例中，一旦轉移腔室802已接收一晶圓，在叢集工具800內維持大約小於100毫托耳之真空。根據本發明一實施例，叢集工具800整合一墊塊(或多個墊塊，也就是，每一個腔室一個墊塊)，其中，相對於該邊緣表面之晶圓平坦表面依靠在該墊塊上用以處理並轉移事件。在一實施例中，藉由將一晶圓平坦表面依靠在該墊塊上，用於加熱該晶圓之更快速上升速率可藉由透過該墊塊來加熱該晶圓而得。在一特定實施例中，叢集工具800係一單晶圓叢集工具。The cluster tool 800 can be any cluster tool that isolates an external environment from outside or between the process chambers 804, 804, and 806 and the transfer chamber 802. Thus, in accordance with an embodiment of the present invention, once a wafer has entered process chamber 802, it is isolated when it is moved into or between process chambers 804, 804 and 806 and transfer chamber 802. An external environment. An example of such a clustering tool is the Centura® platform marketed by Applied Materials, Inc. of Santa Clara, California. In one embodiment, once the transfer chamber 802 has received a wafer, a vacuum of less than about 100 mTorr is maintained within the cluster tool 800. According to an embodiment of the invention, the cluster tool 800 integrates a spacer (or a plurality of spacers, that is, one spacer per chamber), wherein the wafer flat surface relative to the edge surface depends on the spacer Used to process and transfer events. In one embodiment, by relying on a wafer flat surface on the spacer, a faster rate of rise for heating the wafer can be obtained by heating the wafer through the spacer. In a particular embodiment, cluster tool 800 is a single wafer cluster tool.
製程腔室802、804及806可包含氧化腔室、低壓化學氣相沉積腔室或其結合，但不限於此。例如，根據本發明一實施例，第一製程腔室804係一第一氧化腔室，第二製程腔室806係一低壓化學氣相沉積腔室，且第三製程腔室808係一第二氧化腔室。一氧化腔室範例係來自應用材料公司之現場蒸汽產生(ISSG)腔室。低壓化學氣相沉積腔室範例包含來自應用材料公司之SiNgenTM腔室及OXYgenTM腔室。取代典型批次處理腔室例之加熱整個製程腔室以加熱一晶圓者為用於攜帶單一晶圓所使用之墊塊可被加熱以加熱該晶圓。根據本發明一實施例，一墊塊被使用以加熱一晶圓至該要求製程溫度。因此，可得到相當短促之溫度上升時間及穩定時間。Process chambers 802, 804, and 806 can include, but are not limited to, an oxidation chamber, a low pressure chemical vapor deposition chamber, or a combination thereof. For example, in accordance with an embodiment of the invention, the first process chamber 804 is a first oxidation chamber, the second process chamber 806 is a low pressure chemical vapor deposition chamber, and the third process chamber 808 is a second Oxidation chamber. An example of an oxidation chamber is from Applied Materials' on-site steam generation (ISSG) chamber. A low pressure chemical vapor deposition chamber comprising a sample chamber SiNgenTM from Applied Materials Company and OXYgenTM chamber. Instead of a typical batch processing chamber, the entire process chamber is heated to heat a wafer. The pads used to carry a single wafer can be heated to heat the wafer. In accordance with an embodiment of the invention, a spacer is used to heat a wafer to the desired process temperature. Therefore, a relatively short temperature rise time and settling time can be obtained.
一非揮發性電荷捕獲記憶體元件之一部分可被製造於一叢集工具中。圖9根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作流程圖。圖10A-10E根據本發明一實施例說明代表製造一非揮發性電荷捕獲記憶體元件之操作剖面圖。A portion of a non-volatile charge trapping memory component can be fabricated in a cluster tool. Figure 9 illustrates a series of operational flow diagrams in a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention. 10A-10E illustrate operational cross-sectional views representative of the fabrication of a non-volatile charge trapping memory device, in accordance with an embodiment of the present invention.
參考至圖10A，一基板1000被提供於一叢集工具中。在一實施例中，基板1000被提供於一轉移腔室中，例如，連結圖8所述之轉移腔室802。Referring to Figure 10A, a substrate 1000 is provided in a cluster tool. In one embodiment, the substrate 1000 is provided in a transfer chamber, for example, coupled to the transfer chamber 802 illustrated in FIG.
基板1000可由適合用於半導體元件製造之材料所構成。在一實施例中，基板1000係一本體基板，由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料之單一結晶材料所構成，但不限於此。在另一實施例中，基板1000包含具有一頂部磊晶層之本體層。在一特定實施例中，該本體層係由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料或石英之單一結晶材料所構成，但不限於此，而該頂部磊晶層係由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料之單一結晶層所構成，但不限於此。在另一實施例中，基板1000包含位於一下方本體層之上之中間絕緣體層上的頂部磊晶層。該頂部磊晶層係由可包含矽(也就是，用以形成絕緣體上矽(SOI)半導體基板)、鍺、矽-鍺或一III-V族化合物半導體材料之單一結晶層所構成，但不限於此。該絕緣體層係由可包含二氧化矽、氮化矽或氮氧化矽之材料所構成，但不限於此。該下方本體層係由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料或石英之單一結晶材料所構成，但不限於此。基板1000可進一步包含摻雜物之雜質原子。The substrate 1000 can be constructed of materials suitable for use in the fabrication of semiconductor components. In one embodiment, the substrate 1000 is a body substrate composed of a single crystalline material that may comprise yttrium, lanthanum, ytterbium, or a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 1000 includes a body layer having a top epitaxial layer. In a specific embodiment, the body layer is composed of a single crystalline material that may comprise yttrium, lanthanum, ytterbium, or a group III-V compound semiconductor material or quartz, but is not limited thereto, and the top epitaxial layer It is composed of a single crystal layer which may contain yttrium, lanthanum, ytterbium-tellurium or a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 1000 includes a top epitaxial layer on an intermediate insulator layer over a lower body layer. The top epitaxial layer is composed of a single crystal layer which may comprise germanium (that is, a germanium-on-insulator (SOI) semiconductor substrate), germanium, germanium-tellurium or a group III-V compound semiconductor material, but not Limited to this. The insulator layer is composed of a material which may include cerium oxide, cerium nitride or cerium oxynitride, but is not limited thereto. The lower body layer is composed of a single crystalline material which may comprise yttrium, lanthanum, ytterbium or a group III-V compound semiconductor material or quartz, but is not limited thereto. The substrate 1000 may further include impurity atoms of the dopant.
圖10B根據本發明一實施例說明對應至圖9流程圖中之操作902之具有一穿隧介電層形成於其上之基板剖面圖。參考至流程圖900之操作902及相對應圖10B，基板1000係於該叢集工具之第一製程腔室內承受一第一基氧化製程以形成一第一介電層1002。Figure 10B illustrates a cross-sectional view of a substrate having a tunneling dielectric layer formed thereon corresponding to operation 902 of the flow chart of Figure 9, in accordance with an embodiment of the present invention. Referring to operation 902 of flowchart 900 and corresponding FIG. 10B, substrate 1000 is subjected to a first base oxidation process in a first process chamber of the cluster tool to form a first dielectric layer 1002.
第一介電層1002可由一材料所構成且具有一合適厚度以在一施加閘極偏壓下，讓電荷載子穿隧至一接著形成之電荷捕獲層中，而在未施加偏壓於接著形成之非揮發性電荷捕獲記憶體元件時，對漏電維持一合適障礙。第一介電層1002在習知技術中可稱之為穿隧介電層。根據本發明一實施例，第一介電層602係由一氧化製程所形成，其中，基板1000之頂部表面被耗用。因此，在一實施例中，第一介電層1002係由基板1000之材料之氧化物所構成。例如，在一實施例中，基板1000係由矽所構成且第一介電層1002係由二氧化矽所構成。在一特定實施例中，所形成第一介電層1002之厚度係大約在1-10奈米範圍內。在一具體實施例中，所形成第一介電層1002之厚度係大約在1.5-2.5奈米範圍內。The first dielectric layer 1002 can be formed of a material and having a suitable thickness to allow charge carriers to tunnel into a subsequently formed charge trap layer under an applied gate bias without biasing When a non-volatile charge trapping memory element is formed, an appropriate obstacle to leakage is maintained. The first dielectric layer 1002 may be referred to as a tunneling dielectric layer in the prior art. According to an embodiment of the invention, the first dielectric layer 602 is formed by an oxidation process in which the top surface of the substrate 1000 is consumed. Thus, in one embodiment, the first dielectric layer 1002 is comprised of an oxide of material of the substrate 1000. For example, in one embodiment, substrate 1000 is comprised of tantalum and first dielectric layer 1002 is comprised of hafnium oxide. In a particular embodiment, the thickness of the first dielectric layer 1002 formed is in the range of about 1-10 nanometers. In one embodiment, the thickness of the first dielectric layer 1002 formed is in the range of about 1.5-2.5 nanometers.
第一介電層1002可由一基氧化製程來形成之。在根據本發明一實施例中，該基氧化製程涉及將氫氣及氧氣流入例如連結圖8所述氧化腔室804或808之氧化腔室中。在一實施例中，氫氣及氧氣分壓彼此間具有大約1：50-1：5範圍比值。然而，在一實施例中，一燃燒事件並未實現，其在其它方面典型地會被使用以熱分解氫氣及氧氣來形成蒸汽。替代性地，氫氣及氧氣係可起反應以在基板1000表面處形成自由基。在一實施例中，該些自由基被使用以耗用基板1000之頂部以提供第一介電層1002。在一特定實施例中，該基氧化製程包含利用例如一氫氧基、一氫過氧基或一氧二基之自由基來進行氧化，但不限於此。在一具體實施例中，該基氧化製程係實施於大約950-1100攝氏度範圍溫度及大約5-15托耳範圍壓力下。在一實施例中，該基氧化製程係實施大約1-3分鐘範圍之持續時間。根據本發明一實施例，第一介電層1002係形成為一高密度、低氫含量之薄膜。The first dielectric layer 1002 can be formed by a base oxidation process. In an embodiment in accordance with the invention, the base oxidation process involves flowing hydrogen and oxygen into an oxidation chamber, such as the oxidation chamber 804 or 808 of FIG. In one embodiment, the hydrogen and oxygen partial pressures have a ratio ranging from about 1:50 to 1:5. However, in one embodiment, a combustion event is not achieved, which is otherwise typically used to thermally decompose hydrogen and oxygen to form steam. Alternatively, hydrogen and oxygen may react to form free radicals at the surface of the substrate 1000. In one embodiment, the free radicals are used to consume the top of the substrate 1000 to provide the first dielectric layer 1002. In a particular embodiment, the radical oxidation process comprises the use of, for example, monohydric oxy, monohydroperoxy or monooxyThe radical is oxidized, but is not limited thereto. In one embodiment, the base oxidation process is carried out at a temperature in the range of about 950 to 1100 degrees Celsius and a pressure in the range of about 5 to 15 Torr. In one embodiment, the base oxidation process is carried out for a duration ranging from about 1-3 minutes. According to an embodiment of the invention, the first dielectric layer 1002 is formed as a high density, low hydrogen content film.
參考至流程圖900之操作904，形成第一介電層1002之後，且在任何進一步處理之前，第一介電層1002可承受一氮化製程。在一實施例中，該氮化製程係實施於與形成第一介電層1002所使用之相同製程腔室內，在一實施例中，第一介電層1002係回火於該第一製程腔室內，其中，該回火包含在大約900-1100攝氏度範圍溫度下，大約30秒-60秒範圍持續時間內，於一含氮大氣中加熱基板1000。在一實施例中，該含氮大氣係由例如氮氣(N2)、氧化亞氮(N2O)、二氧化氮(NO2)、氧化氮(NO)或氨(NH3)之氣體所構成，但不限於此。在一實施例中，該氮化作用發生於一獨立製程腔室。替代性地，本氮化步驟可被略過。Referring to operation 904 of flowchart 900, after forming first dielectric layer 1002, and prior to any further processing, first dielectric layer 1002 can undergo a nitridation process. In one embodiment, the nitridation process is performed in the same process chamber as used to form the first dielectric layer 1002. In one embodiment, the first dielectric layer 1002 is tempered in the first process cavity. Indoor, wherein the tempering comprises heating the substrate 1000 in a nitrogen-containing atmosphere at a temperature in the range of about 900-1100 degrees Celsius for a duration of about 30 seconds to 60 seconds. In one embodiment, the nitrogen-containing atmosphere is composed of, but not limited to, a gas such as nitrogen (N 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), nitrogen oxide (NO), or ammonia (NH 3 ). this. In one embodiment, the nitriding occurs in a separate process chamber. Alternatively, the present nitridation step can be skipped.
圖10C根據本發明一實施例說明對應至圖9流程圖中之操作906之具有一電荷捕獲層形成於其上之基板剖面圖。參考至流程圖900之操作906及相對應圖10C，具有一第一區域1004A及一第二區域1004B之電荷捕獲層係在一叢集工具之第二製程腔室內形成於第一介電層1002上。Figure 10C illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon corresponding to operation 906 of the flow chart of Figure 9, in accordance with an embodiment of the present invention. Referring to operation 906 of flowchart 900 and corresponding FIG. 10C, a charge trapping layer having a first region 1004A and a second region 1004B is formed on the first dielectric layer 1002 in a second processing chamber of the cluster tool. .
該電荷捕獲層可由一材料所構成且具有適合儲存電荷並因此改變接著形成之閘極堆疊臨界電壓之厚度。根據本發明一實施例，該電荷捕獲層係由如圖10C所述之二區域1004A及1004B所構成。在一實施例中，該電荷捕獲層之區域1004A會保留做為後續製程操作之完整無缺電荷捕獲層。然而，在那個實施例中，該增加形成之電荷捕獲層之區域1004B會被耗用以在區域1004A上方形成一第二介電層。在一實施例中，該電荷捕獲層之區域1004A及1004B係以相同製程步驟來形成且由相同材料所構成。The charge trap layer can be composed of a material and has a thickness suitable for storing charge and thus changing the threshold voltage of the subsequently formed gate stack. According to an embodiment of the invention, the charge trapping layer is formed by two regions 1004A and 1004B as described in FIG. 10C. In one embodiment, the region 1004A of the charge trapping layer remains as a complete, uncharged charge trapping layer for subsequent processing operations. However, in that embodiment, the region 1004B of the charge trapping layer formed is increased.It will be consumed to form a second dielectric layer over region 1004A. In one embodiment, regions 1004A and 1004B of the charge trapping layer are formed in the same process steps and are comprised of the same material.
具有區域1004A及1004B之電荷捕獲層可經由一化學氣相沉積製程來形成之。根據本發明一實施例，該電荷捕獲層係由例如氮化矽、氮氧化矽、含氧之氮氧化矽或含氮之氮氧化矽所構成，但不限於此。在一實施例中，該電荷捕獲層係在例如連結自圖8之製程腔室806所述之SiNgen TM低壓化學氣相沉積腔室般之低壓化學氣相沉積腔室內形成於第一介電層1002上。在一實施例中，該第二製程腔室係一低壓化學氣相沉積腔室，且該電荷捕獲層之區域1004A及1004B係在相較於形成第一介電層1002所使用之溫度更低之溫度下形成之。在一特定實施例中，該電荷捕獲層之區域1004A及1004B係在大約700-850攝氏度範圍溫度下形成之。在一實施例中，該第二製程腔室係一低壓化學氣相沉積腔室，且該電荷捕獲層係使用例如二氯矽烷、雙三級丁氨基矽烷(BTBAS)、氨(NH3)或氧化亞氮(N2O)之氣體來形成，但不限於此。根據本發明一實施例，該電荷捕獲層係形成為大約5-15奈米範圍之總厚度，區域1004B佔有大約該電荷捕獲層總厚度中之2-3奈米範圍厚度。在那個實施例中，區域1004A佔有該電荷捕獲層之其餘總厚度，也就是，區域1004A佔有該電荷捕獲層中，未被接著耗用以形成一頂部或阻擋介電層的部分。The charge trapping layer having regions 1004A and 1004B can be formed via a chemical vapor deposition process. According to an embodiment of the invention, the charge trapping layer is composed of, for example, tantalum nitride, lanthanum oxynitride, cerium oxide containing oxygen or cerium oxynitride containing nitrogen, but is not limited thereto. In one embodiment, the charge trapping layer is formed in the first dielectric layer in a low pressure chemical vapor deposition chamber, such as the SiNgenTM low pressure chemical vapor deposition chamber coupled to the process chamber 806 of FIG. On the 1002. In one embodiment, the second process chamber is a low pressure chemical vapor deposition chamber, and the regions 1004A and 1004B of the charge trap layer are at a lower temperature than those used to form the first dielectric layer 1002. It is formed at a temperature. In a particular embodiment, regions 1004A and 1004B of the charge trapping layer are formed at a temperature in the range of about 700-850 degrees Celsius. In one embodiment, the second processing chamber is a low pressure chemical vapor deposition chamber, and the charge trapping layer uses, for example, dichlorosilane, double tertiary butylaminodecane (BTBAS), ammonia (NH3 ) or A gas of nitrous oxide (N2 O) is formed, but is not limited thereto. In accordance with an embodiment of the invention, the charge trapping layer is formed to a total thickness in the range of about 5-15 nm, and the region 1004B occupies about 2-3 nm of the total thickness of the charge trapping layer. In that embodiment, region 1004A occupies the remaining total thickness of the charge trap layer, that is, region 1004A occupies a portion of the charge trap layer that is not subsequently consumed to form a top or barrier dielectric layer.
在本發明另一觀點中，該電荷捕獲層可包含多個組成成分區域。例如，根據本發明一實施例，該電荷捕獲層包含一含氧部分及一含矽部分並於該第二製程腔室內經由一第一氣體組成成分來沉積一含氧之氮氧化物薄膜並經由一第二氣體組成成分來沉積一含矽之氮氧化物薄膜而形成。在一實施例中，該電荷捕獲層係藉由改變氨(NH3)氣之流速並引進氧化亞氮(N2O)和二氯矽烷來提供該些要求氣體比值，以先產生一含氧之氮氧化物薄膜，再接著產生一含矽之氮氧化物薄膜而形成。在一特定實施例中，該含氧之氮氧化物薄膜係藉由引進包含氧化亞氮、氨及二氯矽烷之製程氣體混合物，同時將該腔室維持在大約0.5-500托耳範圍壓力下，並將基板1000維持在大約700-850攝氏度範圍溫度下，持續一段大約2.5-20分鐘範圍之時間而形成。在一進一步實施例中，該製程氣體混合物包含具有約從8：1至1：8比值之氧化亞氮和氨，及具有約從1：7至7：1比值之二氯矽烷和氨，且可以大約每分鐘5-200標準立方公分範圍之流速來引進。在另一特定實施例中，該含矽之氮氧化物薄膜係藉由引進包含氧化亞氮、氨及二氯矽烷之製程氣體混合物，同時將該腔室維持在大約0.5-500托耳範圍壓力下，並將基板1000維持在大約700-850攝氏度範圍溫度下，持續一段大約2.5-20分鐘範圍之時間而形成。在一進一步實施例中，該製程氣體混合物包含具有約從8：1至1：8比值之氧化亞氮和氨，及以約從1：7至7：1比值混合之二氯矽烷和氨，以大約每分鐘5至20標準立方公分之流速來引進。根據本發明一實施例，該電荷捕獲層包括具有大約2.5-3.5奈米範圍厚度之底部含氧氮氧化矽部分及具有大約9-10奈米範圍厚度之頂部含矽氮氧化矽部分。在一實施例中，電荷捕獲層之區域1004B佔有該電荷捕獲層之頂部含矽氮氧化矽部分之總厚度中大約2-3奈米範圍厚度。因此，針對接著耗用以形成一第二介電層所預定之區域1004B可完全地由含矽氮氧化矽來構成之。In another aspect of the invention, the charge trap layer may comprise a plurality of constituent regions. For example, in accordance with an embodiment of the invention, the charge trapping layer includes an oxygen-containing portion and a germanium-containing portion and deposits an oxygen-containing nitrogen oxide in the second processing chamber via a first gas component.The film is formed by depositing a film of ruthenium-containing oxynitride via a second gas composition. In one embodiment, the charge trapping layer provides the desired gas ratio by changing the flow rate of ammonia (NH3) gas and introducing nitrous oxide (N2O) and dichlorosilane to generate an oxygen-containing nitrogen oxide. The film is then formed by the formation of a ruthenium-containing oxynitride film. In a particular embodiment, the oxygen-containing oxynitride film is maintained at a pressure in the range of about 0.5-500 Torr by introducing a process gas mixture comprising nitrous oxide, ammonia, and methylene chloride. The substrate 1000 is maintained at a temperature in the range of about 700-850 degrees Celsius for a period of about 2.5-20 minutes. In a further embodiment, the process gas mixture comprises nitrous oxide and ammonia having a ratio of from about 8:1 to 1:8, and dichloromethane and ammonia having a ratio of from about 1:7 to 7:1, and It can be introduced at a flow rate of approximately 5-200 standard cubic centimeters per minute. In another specific embodiment, the ruthenium-containing oxynitride film is maintained at a pressure in the range of about 0.5-500 Torr by introducing a process gas mixture comprising nitrous oxide, ammonia, and methylene chloride. The substrate 1000 is maintained at a temperature in the range of about 700-850 degrees Celsius for a period of about 2.5-20 minutes. In a further embodiment, the process gas mixture comprises nitrous oxide and ammonia having a ratio of from about 8:1 to 1:8, and dichloromethane and ammonia mixed at a ratio of from about 1:7 to 7:1, Introduced at a flow rate of approximately 5 to 20 standard cubic centimeters per minute. In accordance with an embodiment of the invention, the charge trapping layer comprises a bottom oxynitride layer having a thickness in the range of about 2.5 to 3.5 nanometers and a top ytterbium oxynitride portion having a thickness in the range of about 9-10 nanometers. In one embodiment, the region 1004B of the charge trapping layer occupies a thickness in the range of about 2-3 nm in the total thickness of the niobium oxynitride portion of the charge trapping layer. Therefore, the region 1004B predetermined for the subsequent formation of a second dielectric layer can be completely composed of niobium-containing niobium oxide.
圖10D根據本發明一實施例說明對應至圖9流程圖之操作908之具有一第二介電層形成於其上之基板剖面圖。參考至流程圖900之操作908及相對應圖10D，一第二介電層1006係在該叢集工具之第一製程腔室內形成於電荷捕獲層1004上。FIG. 10D illustrates the operation corresponding to the flowchart of FIG. 9 according to an embodiment of the invention.908 has a cross-sectional view of a substrate having a second dielectric layer formed thereon. Referring to operation 908 of flowchart 900 and corresponding FIG. 10D, a second dielectric layer 1006 is formed on the charge trap layer 1004 in the first process chamber of the cluster tool.
第二介電層1006可一材料所構成且具有對漏電維持一障礙卻不顯著地降低接著形成於一非揮發性電荷捕獲記憶體元件內之閘極堆疊電容之厚度。根據本發明一實施例，第二介電層1006係藉由耗用連結圖10C所述操作906所形成之電荷捕獲層之區域1004B而形成。因此，在一實施例中，區域1004B被耗用以提供第二介電層1006，而區域1004A保留一電荷捕獲層1004。在一特定實施例中，區域1004B係具有大約2-3奈米範圍厚度之含矽氮氧化矽，並被氧化以形成具有大約3.5-4.5奈米範圍厚度之第二介電層1006。在一那個實施例中，第二介電層1006係由二氧化矽所構成。The second dielectric layer 1006 can be constructed of a material and has a barrier to leakage that does not significantly reduce the thickness of the gate stack capacitance that is subsequently formed in a non-volatile charge trapping memory component. In accordance with an embodiment of the invention, the second dielectric layer 1006 is formed by consuming a region 1004B of the charge trapping layer formed by the operation 906 described in connection with FIG. 10C. Thus, in one embodiment, region 1004B is consumed to provide second dielectric layer 1006 while region 1004A retains a charge trap layer 1004. In a particular embodiment, region 1004B is tantalum oxynitride having a thickness in the range of about 2-3 nanometers and is oxidized to form a second dielectric layer 1006 having a thickness in the range of about 3.5-4.5 nanometers. In one embodiment, the second dielectric layer 1006 is comprised of ruthenium dioxide.
第二介電層1006可經由一第二基氧化製程來形成之。根據本發明一實施例，該第二基氧化製程涉及將氫氣及氧氣流入例如連結圖8所述氧化腔室804或808之氧化腔室中。在一實施例中，氫氣及氧氣分壓彼此間具有大約1：50-1：5範圍比值。然而，在一實施例中，一燃燒事件並未實現，其在其它方面典型地會被使用以熱分解氫氣及氧氣來形成蒸汽。替代性地，氫氣及氧氣係可起反應以在區域1004B表面處形成自由基。在一實施例中，該些自由基被使用以耗用區域1004B以提供第二介電層1006。在一特定實施例中，該第二基氧化製程包含利用例如一氫氧基、一氫過氧基或一氧二基之自由基來進行氧化，但不限於此。在一具體實施例中，該第二基氧化製程係實施於大約950-1100攝氏度範圍溫度及大約5-15托耳範圍壓力下。在一實施例中，該第二基氧化製程係實施大約1-3分鐘範圍之持續時間。根據本發明一實施例，第一介電層1002係形成為一高密度、低氫含量之薄膜。在一實施例中，沒有額外沉積步驟被需要以如圖10D所述及流程圖900所示地形成一完整第二介電層1006。依據該叢集工具內之晶圓傳送邏輯，該第二基氧化製程可實施於與用以形成第一介電層1002所使用之第一基氧化製程相同腔室，也就是第一腔室，或實施於該叢集工具之一不同製程腔室，也就是第三製程腔室。因此，根據本發明一實施例，對一第一製程腔室之參考可被使用以代表重新引入至該第一製程腔室中或代表引入至不同於該第一製程腔室之製程腔室中。The second dielectric layer 1006 can be formed via a second radical oxidation process. According to an embodiment of the invention, the second base oxidation process involves flowing hydrogen and oxygen into an oxidation chamber, such as the oxidation chamber 804 or 808 of FIG. In one embodiment, the hydrogen and oxygen partial pressures have a ratio ranging from about 1:50 to 1:5. However, in one embodiment, a combustion event is not achieved, which is otherwise typically used to thermally decompose hydrogen and oxygen to form steam. Alternatively, hydrogen and oxygen can react to form free radicals at the surface of region 1004B. In one embodiment, the free radicals are used to consume region 1004B to provide a second dielectric layer 1006. In a particular embodiment, the second radical oxidation process comprises oxidation using a free radical such as monohydric oxy, monohydroperoxy or monooxydiyl, but is not limited thereto. In one embodiment, the second base oxidation process is carried out at a temperature in the range of about 950 to 1100 degrees Celsius and a pressure in the range of about 5 to 15 Torr. In one embodiment, the second base oxidation process is carried out for a duration of about 1-3 minutes.time. According to an embodiment of the invention, the first dielectric layer 1002 is formed as a high density, low hydrogen content film. In an embodiment, no additional deposition steps are required to form a complete second dielectric layer 1006 as illustrated in FIG. 10D and as shown in flowchart 900. According to the wafer transfer logic in the cluster tool, the second base oxidation process can be implemented in the same chamber as the first base oxidation process used to form the first dielectric layer 1002, that is, the first chamber, or Implemented in one of the cluster tools, the different process chambers, that is, the third process chamber. Thus, in accordance with an embodiment of the present invention, a reference to a first process chamber can be used to represent reintroduction into the first process chamber or to introduce into a process chamber different from the first process chamber. .
參考至流程圖900之操作910，形成第二介電層1006後，且自該叢集工具中移除基板1000之前，第二介電層1006可進一步在該第一製程腔室內承受一氮化製程。根據本發明一實施例，該氮化製程包含在大約900-1100攝氏度範圍溫度下，大約30秒-60秒範圍持續時間內，於一含氮大氣中回火第二介電層1006。在一實施例中，該含氮大氣係由例如氮氣(N2)、氧化亞氮(N2O)、二氧化氮(NO2)、氧化氮(NO)或氨(NH3)之氣體所構成，但不限於此。替代性地，本氮化步驟，也就是來自流程圖900之操作910，可被略過，並自該叢集工具中卸除該晶圓。Referring to operation 910 of flowchart 900, after forming the second dielectric layer 1006, and before removing the substrate 1000 from the cluster tool, the second dielectric layer 1006 may further undergo a nitridation process in the first process chamber. . In accordance with an embodiment of the invention, the nitridation process comprises tempering the second dielectric layer 1006 in a nitrogen-containing atmosphere at a temperature in the range of about 900-1100 degrees Celsius for a duration of between about 30 seconds and 60 seconds. In one embodiment, the nitrogen-containing atmosphere is composed of, but not limited to, a gas such as nitrogen (N 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), nitrogen oxide (NO), or ammonia (NH 3 ). this. Alternatively, the present nitridation step, that is, operation 910 from flowchart 900, can be skipped and the wafer removed from the cluster tool.
因此，根據本發明一實施例，包含第一介電層1002、電荷捕獲層1004及第二介電層1006之氧化物-氮化物-氧化物堆疊係以一次操作來形成於一叢集工具內。藉由在該製程腔室內以一次操作來製造這些層，在第一介電層1002和電荷捕獲層1004之間及在電荷捕獲層1004和第二介電層1006之間之原始介面可被保存。在一實施例中，第一介電層1002、電荷捕獲層1004及第二介電層1006被形成而未損毀該叢集工具內之真空。在一實施例中，每一層係形成於一不同溫度下，以量身定做薄膜特性而不招惹顯著的上升時間損失。更進一步，相對於在批次處理工具內進行製造，藉由在一叢集工具內製造這些層，該層堆疊之整體均勻性可被最佳化。例如，根據本發明一實施例，藉由在一叢集工具內製造層1002、1004及1006，橫跨單一晶圓各層1002、1004及1006之堆疊厚度變異性可降低多達約30%。在一示範性實施例中，1cr係大約為第一介電層1002厚度之1-2%範圍內。在一特定實施例中，該叢集工具係一單晶圓叢集工具。Thus, in accordance with an embodiment of the invention, an oxide-nitride-oxide stack comprising a first dielectric layer 1002, a charge trap layer 1004, and a second dielectric layer 1006 is formed in a cluster tool in a single operation. By fabricating the layers in a single operation within the process chamber, the original interface between the first dielectric layer 1002 and the charge trap layer 1004 and between the charge trap layer 1004 and the second dielectric layer 1006 can be saved. . In one embodiment, the first dielectric layer 1002, the charge trap layer 1004, and the second dielectric layer 1006 are formed without damaging the vacuum within the cluster tool. inIn one embodiment, each layer is formed at a different temperature to tailor film properties without incurring significant rise time loss. Still further, the overall uniformity of the layer stack can be optimized by fabricating the layers within a cluster tool relative to manufacturing in a batch processing tool. For example, stack thickness variability across layers 1002, 1004, and 1006 across a single wafer can be reduced by up to about 30% by fabricating layers 1002, 1004, and 1006 in a cluster tool, in accordance with an embodiment of the present invention. In an exemplary embodiment, the 1cr is approximately 1-2% of the thickness of the first dielectric layer 1002. In a particular embodiment, the cluster tool is a single wafer cluster tool.
依據包含第一介電層1002、電荷捕獲層1004及第二介電層1006之氧化物-氮化物-氧化物堆疊製造，一非揮發性電荷捕獲記憶體元件可被製造以包含該氧化物-氮化物-氧化物堆疊之圖案化部分。圖10E根據本發明一實施例說明一非揮發性電荷捕獲記憶體元件之剖面圖。Manufactured from an oxide-nitride-oxide stack comprising a first dielectric layer 1002, a charge trap layer 1004, and a second dielectric layer 1006, a non-volatile charge trapping memory element can be fabricated to include the oxide- A patterned portion of a nitride-oxide stack. Figure 10E illustrates a cross-sectional view of a non-volatile charge trapping memory component in accordance with an embodiment of the present invention.
參考至第6E圖，一非揮發性電荷捕獲記憶體元件包含形成於基板1000上方之氧化物-氮化物-氧化物堆疊之圖案化部分。該氧化物-氮化物-氧化物堆疊包含第一介電層1002、電荷捕獲層1004及第二介電層1006。一閘極層1008係置於第二介電層1006上。該非揮發性電荷捕獲記憶體元件進一步包含在基板1000內分別位於該氧化物-氮化物-氧化物堆疊一側上之源極和汲極區域1012，以定義該氧化物-氮化物-氧化物堆疊下面基板1000內之通道區域1014。一對介電間隔側壁1010隔離第一介電層1002、電荷捕獲層1004、第二介電層1006及閘極層1008之側壁。在一特定實施例中，通道區域1014係為P型摻雜，而在一替代性實施例中，通道區域1014係N型摻雜。Referring to FIG. 6E, a non-volatile charge trapping memory component includes a patterned portion of an oxide-nitride-oxide stack formed over substrate 1000. The oxide-nitride-oxide stack includes a first dielectric layer 1002, a charge trap layer 1004, and a second dielectric layer 1006. A gate layer 1008 is placed over the second dielectric layer 1006. The non-volatile charge trapping memory component further includes source and drain regions 1012 on the oxide-nitride-oxide stack side within the substrate 1000 to define the oxide-nitride-oxide stack The channel region 1014 in the lower substrate 1000. A pair of dielectric spacer sidewalls 1010 isolate sidewalls of the first dielectric layer 1002, the charge trap layer 1004, the second dielectric layer 1006, and the gate layer 1008. In a particular embodiment, channel region 1014 is P-type doped, while in an alternative embodiment, channel region 1014 is N-doped.
根據本發明一實施例，連結圖10E所述之非揮發性電荷捕獲記憶體元件係一半導體-氧化物-氮化物-氧化物-半導體型元件。按照慣例，SONOS代表“半導體-氧化物-氮化物-氧化物-半導體”，其中，該第一個“半導體”參考至該通道區域材料，該第一個“氧化物”參考至該穿隧介電層，“氮化物”參考至該電荷捕獲介電層，該第二個“氧化物”參考至該頂部介電層(也是已知之阻擋介電層)，以及該第二個“半導體”參考至該閘極層。因此，根據本發明一實施例，第一介電層1002係一穿隧介電層，且第二介電層1006係一阻擋介電層。Non-volatile charge trapping as described in connection with FIG. 10E, in accordance with an embodiment of the present inventionThe memory element is a semiconductor-oxide-nitride-oxide-semiconductor type element. Conventionally, SONOS stands for "semiconductor-oxide-nitride-oxide-semiconductor", wherein the first "semiconductor" is referenced to the channel region material, and the first "oxide" is referenced to the tunneling dielectric An electrical layer, "nitride" is referenced to the charge trapping dielectric layer, the second "oxide" is referenced to the top dielectric layer (also known as a blocking dielectric layer), and the second "semiconductor" reference To the gate layer. Therefore, according to an embodiment of the invention, the first dielectric layer 1002 is a tunneling dielectric layer, and the second dielectric layer 1006 is a blocking dielectric layer.
閘極層1008可由適合在一半導體-氧化物-氮化物-氧化物-半導體型電晶體操作期間提供一偏壓之任何導體或半導體材料所構成。根據本發明一實施例，閘極層1008係經由一化學氣相沉積製程所形成且由摻雜多晶矽所構成。在另一實施例中，閘極層1008係經由物理氣相沉積製程所形成且由可包含金屬氮化物、金屬碳化物、金屬矽化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷或鎳之含金屬材料所構成，但不限於此。The gate layer 1008 can be comprised of any conductor or semiconductor material suitable for providing a bias during operation of a semiconductor-oxide-nitride-oxide-semiconductor type of transistor. According to an embodiment of the invention, the gate layer 1008 is formed via a chemical vapor deposition process and is composed of doped polysilicon. In another embodiment, the gate layer 1008 is formed by a physical vapor deposition process and may include metal nitrides, metal carbides, metal tellurides, hafnium, zirconium, titanium, hafnium, aluminum, hafnium, palladium, It is composed of a metal-containing material of platinum, cobalt or nickel, but is not limited thereto.
基板1000內之源極和汲極區域1012可為具有與通道區域1014相反導電性之任何區域。例如，根據本發明一實施例，源極及汲極區域1012係N型摻雜區域，而通道區域1014係一P型摻雜區域。在一實施例中，基板1000及因此所形成之通道區域1014係由具有1x1015-1x1019原子/立方公分範圍硼濃度之硼摻雜單結晶矽所構成。在那個實施例中，源極及汲極區域1012係由具有5x1016-5x1019原子/立方公分範圍之N型摻雜物濃度之磷或砷摻雜區域所構成。在一特定實施例中，源極及汲極區域1012在基板1000內具有80-200奈米範圍之深度。根據本發明一替代性實施例，源極及汲極區域1012係P型摻雜區域，而通道區域1014係一N型摻雜區域。The source and drain regions 1012 within the substrate 1000 can be any region having opposite conductivity to the channel region 1014. For example, in accordance with an embodiment of the invention, the source and drain regions 1012 are N-type doped regions and the channel region 1014 is a P-type doped region. In one embodiment, the substrate 1000 and thus the channel region 1014 is formed of a boron-doped monocrystalline germanium having a boron concentration in the range of 1 x 1015 -1 x 1019 atoms per cubic centimeter. In that embodiment, the source and drain regions 1012 are comprised of phosphorus or arsenic doped regions having an N-type dopant concentration in the range of 5 x10 16 - 5 x1019 atoms per cubic centimeter. In a particular embodiment, the source and drain regions 1012 have a depth in the range of 80-200 nm within the substrate 1000. In accordance with an alternative embodiment of the present invention, the source and drain regions 1012 are P-type doped regions and the channel region 1014 is an N-type doped region.
在本發明另一觀點中，一電荷捕獲層可包含多個組成成分區域，其中，最接近一穿隧介電層之組成成分區域係承受一基氧化製程。圖11根據本發明一實施例說明代表一非揮發性電荷捕獲記憶體元件之製造方法中之一系列操作之流程圖1100。圖12A-12E根據本發明一實施例說明代表製造一非揮發性電荷捕獲記憶體元件之操作剖面圖。In another aspect of the invention, a charge trap layer can comprise a plurality of constituent regions, wherein the constituent regions closest to a tunneling dielectric layer are subjected to a base oxidation process. Figure 11 illustrates a flow diagram 1100 of a series of operations in a method of fabricating a non-volatile charge trapping memory component, in accordance with an embodiment of the present invention. 12A-12E are cross-sectional views showing the operation of fabricating a non-volatile charge trapping memory element, in accordance with an embodiment of the present invention.
圖12A根據本發明一實施例說明對應至圖11流程圖中之操作1102之具有一第一介電層形成於其上之基板剖面圖。參考至流程圖1100之操作1102及相對應圖12A，基板1200係於一叢集工具之第一製程腔室內承受一第一基氧化製程以形成一第一介電層1202。基板1200及第一介電層1202可分別由連結自圖10A及10B之基板1000及第一介電層1002所述之材料所構成。用以形成第一介電層1202之基氧化製程可類似於連結圖10B所述之用以形成第一介電層1002之基氧化製程。Figure 12A illustrates a cross-sectional view of a substrate having a first dielectric layer formed thereon corresponding to operation 1102 of the flow chart of Figure 11 in accordance with an embodiment of the present invention. Referring to operation 1102 of flowchart 1100 and corresponding FIG. 12A, substrate 1200 is subjected to a first base oxidation process in a first process chamber of a cluster tool to form a first dielectric layer 1202. The substrate 1200 and the first dielectric layer 1202 are respectively formed of materials described in connection with the substrate 1000 and the first dielectric layer 1002 of FIGS. 10A and 10B. The base oxidation process for forming the first dielectric layer 1202 can be similar to the base oxidation process for forming the first dielectric layer 1002 as described in connection with FIG. 10B.
參考至流程圖1100之操作1104，形成第一介電層1202之後，且在任何進一步處理之前，第一介電層1202可承受一氮化製程。該氮化製程可類似於連結流程圖900之操作904所述之氮化製程。在一實施例中，該氮化製程係實施於與形成第一介電層1202所使用之相同製程腔室內。在另一實施例中，該氮化製程發生於一獨立製程腔室內。替代性地，本氮化步驟可被略過。Referring to operation 1104 of flowchart 1100, after forming first dielectric layer 1202, and prior to any further processing, first dielectric layer 1202 can be subjected to a nitridation process. The nitridation process can be similar to the nitridation process described in connection with operation 904 of flowchart 900. In one embodiment, the nitridation process is performed in the same process chamber as used to form the first dielectric layer 1202. In another embodiment, the nitridation process occurs in a separate process chamber. Alternatively, the present nitridation step can be skipped.
圖12B根據本發明一實施例說明對應至圖11流程圖中之操作1106之具有一電荷捕獲層之含氧氮氧化矽部分形成於其上之基板剖面圖。參考至流程圖1100之操作1106及相對應圖12B，一含氧氮氧化矽部分1204A係形成於該叢集工具之第二製程腔室內之第一介電層1202上。含氧氮氧化矽部分1204A可由一含氧氮氧化矽材料所構成且由連結自圖10C之第一區域1004A所述之技術所形成。Figure 12B is a cross-sectional view showing a substrate on which a portion of the oxynitride containing oxynitride having a charge trapping layer, corresponding to operation 1106 of the flow chart of Figure 11, is formed, in accordance with an embodiment of the present invention. Referring to operation 1106 of flowchart 1100 and corresponding FIG. 12B, an oxynitride oxynitride portion 1204A is formed on first dielectric layer 1202 in the second process chamber of the cluster tool. OxygenThe bismuth oxynitride portion 1204A may be comprised of a oxynitride oxynitride material and formed by the techniques described in connection with the first region 1004A of Figure 10C.
根據本發明一實施例參考至流程圖1100中之操作1108，含氧氮氧化矽部分1204A係於該叢集工具之第一製程腔室內承受一第二基氧化製程。該第二基氧化製程可類似於分別連結圖10B及10D所述之用以形成第一介電層1002或第二介電層1006之基氧化製程中之一。在一實施例中，因為含氧氮氧化矽部分1204A係維持於該工具內部環境中，因而保留一原始表面，故實施該第二基氧化製程係可行的依據。在一實施例中，該第二基氧化製程密集含氧氮氧化矽部分1204A。依據該叢集工具內之晶圓傳送邏輯，該第二基氧化製程可實施於與用以形成第一介電層1202所使用之第一基氧化製程相同腔室，也就是第一腔室，或實施於一不同製程腔室，也就是第三製程腔室。因此，根據本發明一實施例，對一第一製程腔室之參考可被使用以代表重新引入至該第一製程腔室中或代表引入至不同於該第一製程腔室之製程腔室中。Referring to operation 1108 of flowchart 1100, the oxynitride oxynitride portion 1204A is subjected to a second base oxidation process in the first process chamber of the cluster tool in accordance with an embodiment of the present invention. The second base oxidation process can be similar to one of the base oxidation processes used to form the first dielectric layer 1002 or the second dielectric layer 1006 as described in connection with FIGS. 10B and 10D, respectively. In one embodiment, since the oxynitride oxide portion 1204A is maintained in the internal environment of the tool, an original surface is retained, so that the second base oxidation process is feasible. In one embodiment, the second base oxidation process is densely packed with the oxynitride oxyhydroxide moiety 1204A. According to the wafer transfer logic in the cluster tool, the second base oxidation process can be implemented in the same chamber as the first base oxidation process used to form the first dielectric layer 1202, that is, the first chamber, or Implemented in a different process chamber, that is, a third process chamber. Thus, in accordance with an embodiment of the present invention, a reference to a first process chamber can be used to represent reintroduction into the first process chamber or to introduce into a process chamber different from the first process chamber. .
圖12C根據本發明一實施例說明對應至圖11流程圖中之操作1110之具有一電荷捕獲層中之含矽氮氧化矽部分形成於其上之基板剖面圖。參考至流程圖1100之操作1110及相對應圖12C，具有一第一區域1204B及一第二區域1204C之含矽氮氧化矽部分係形成於該叢集工具之第二製程腔室內之含氧氮氧化矽部分1204A上。含矽氮氧化矽部分可由一含矽氮氧化矽材料所構成且由連結自圖10C之第二區域1004B所述之技術所形成。依據該叢集工具內之晶圓傳送邏輯，該電荷捕獲層之含矽氮氧化矽部分沉積可實施於與該電荷捕獲層之含氧氮氧化矽部分1204A沉積相同之腔室，也就是第二腔室，或一不同製程腔室。因此，根據本發明一實施例，對一第二製程腔室之參考可被使用以代表重新引入至該第二製程腔室中或代表引入至不同於該第二製程腔室之一製程腔室中。Figure 12C is a cross-sectional view showing a substrate having a portion containing bismuth oxynitride contained in a charge trap layer corresponding to operation 1110 of the flow chart of Figure 11, in accordance with an embodiment of the present invention. Referring to operation 1110 of flowchart 1100 and corresponding FIG. 12C, the bismuth oxynitride containing portion having a first region 1204B and a second region 1204C is formed in the second process chamber of the cluster tool for oxidation of oxygen and nitrogen oxides.矽 Part 1204A. The niobium oxynitride containing molybdenum oxide moiety can be formed from a niobium oxynitride containing material and formed by the techniques described in connection with the second region 1004B of Figure 10C. According to the wafer transfer logic in the cluster tool, a portion of the charge trap layer containing germanium oxynitride may be deposited in the same chamber as the oxynitride oxide portion 1204A of the charge trap layer.That is, the second chamber, or a different process chamber. Thus, in accordance with an embodiment of the present invention, a reference to a second process chamber can be used to represent reintroduction into the second process chamber or to represent a process chamber that is different from one of the second process chambers. in.
圖12D根據本發明一實施例說明對應至圖11流程圖之操作1112之具有一頂部介電層形成於其上之基板剖面圖。參考至流程圖1100之操作1112及相對應圖12D，一第二基板1206係形成於該叢集工具之第一製程腔室內之電荷捕獲層1204上。根據本發明一實施例，第二基板1206係經由一第三基氧化製程來耗用該含矽氮氧化矽部分之第二區域1204C而形成。因此，在一實施例中，在第一介電層1202及第二介電層1206之間所留存之電荷捕獲層1204係如圖12D所述地由含氧氮氧化矽部分1204A及該含矽氮氧化矽部分1204之第一區域1204B所構成。用以耗用該含矽氮氧化矽部分之第二區域1204C以提供第二介電層1206之第三基氧化製程可類似於連結圖10D所述之用以形成第二介電層1006之基氧化製程。依據該叢集工具內之晶圓傳送邏輯，該第三基氧化製程可實施於與形成第一介電層1202所使用之基氧化製程相同之腔室，也就是第一腔室，或例如第三製程腔室之一不同製程腔室。因此，根據本發明一實施例，對一第一製程腔室之參考可被使用以代表重新引入至該第一製程腔室中或代表引入至不同於該第一製程腔室之一製程腔室中。Figure 12D illustrates a cross-sectional view of a substrate having a top dielectric layer formed thereon corresponding to operation 1112 of the flow chart of Figure 11 in accordance with an embodiment of the present invention. Referring to operation 1112 of flowchart 1100 and corresponding FIG. 12D, a second substrate 1206 is formed on charge trap layer 1204 within the first process chamber of the cluster tool. According to an embodiment of the invention, the second substrate 1206 is formed by consuming the second region 1204C containing the niobium oxynitride portion via a third base oxidation process. Therefore, in one embodiment, the charge trapping layer 1204 remaining between the first dielectric layer 1202 and the second dielectric layer 1206 is composed of the oxynitride oxide portion 1204A and the germanium containing ruthenium as described in FIG. 12D. The first region 1204B of the yttrium oxynitride portion 1204 is formed. The third base oxidation process for consuming the second region 1204C of the germanium oxynitride containing portion to provide the second dielectric layer 1206 can be similar to that used to form the second dielectric layer 1006 as described in connection with FIG. 10D. Oxidation process. According to the wafer transfer logic in the cluster tool, the third base oxidation process can be implemented in the same chamber as the base oxidation process used to form the first dielectric layer 1202, that is, the first chamber, or for example, the third One of the process chambers has a different process chamber. Thus, in accordance with an embodiment of the present invention, a reference to a first process chamber can be used to represent reintroduction into the first process chamber or to represent a process chamber that is different from one of the first process chambers. in.
參考至流程圖1100之操作1114，形成第二介電層1206之後，且自該叢集工具中移除基板1200之前，第二介電層1206可進一步在該第一製程腔室內承受一氮化製程。該氮化製程可類似於連結流程圖900之操作910所述之氮化製程。在一實施例中，該氮化製程係實施於與形成第二介電層1206所使用之相同製程腔室內。在另一實施例中，該氮化作用發生於一獨立製程腔室內。替代性地，本氮化步驟可被略過。Referring to operation 1114 of flowchart 1100, after forming second dielectric layer 1206, and before removing substrate 1200 from the cluster tool, second dielectric layer 1206 can further undergo a nitridation process in the first process chamber . The nitridation process can be similar to the nitridation process described in connection with operation 910 of flowchart 900. In one embodiment, the nitridation process is implemented and formedThe same process chamber used by the two dielectric layers 1206. In another embodiment, the nitriding occurs in a separate process chamber. Alternatively, the present nitridation step can be skipped.
依據包含第一介電層1202、電荷捕獲層1204及第二介電層1206之氧化物-氮化物-氧化物堆疊製造，一非揮發性電荷捕獲記憶體元件可被製造以包含該氧化物-氮化物-氧化物堆疊之圖案化部分。圖12E根據本發明一實施例說明一非揮發性電荷捕獲記憶體元件之剖面圖。Manufactured from an oxide-nitride-oxide stack comprising a first dielectric layer 1202, a charge trap layer 1204, and a second dielectric layer 1206, a non-volatile charge trapping memory element can be fabricated to include the oxide- A patterned portion of a nitride-oxide stack. Figure 12E illustrates a cross-sectional view of a non-volatile charge trapping memory component in accordance with an embodiment of the present invention.
參考至圖12E，一非揮發性電荷捕獲記憶體元件包含形成於基板1200上方之氧化物-氮化物-氧化物堆疊之圖案化部分。該氧化物-氮化物-氧化物堆疊包含第一介電層1202、電荷捕獲層1204及第二介電層1206。一閘極層1208係置於第二介電層1206上。該非揮發性電荷捕獲記憶體元件進一步包含基板1200內，分別位於該氧化物-氮化物-氧化物堆疊一側上之源極和汲極區域1212，以定義該氧化物-氮化物-氧化物堆疊下之基板1200內之通道區域1214。一對介電間隔側壁1210隔離第一介電層1202、電荷捕獲層1204、第二介電層1206及閘極層1208之側壁。根據本發明一實施例，電荷捕獲層1204係如圖12E所述地由一含氧氮氧化矽部分1204A及一含矽氮氧化矽部分1204B所構成。在一實施例中，該非揮發性電荷捕獲記憶體元件係一半導體-氧化物-氮化物-氧化物-半導體型元件。閘極層1208、源極和汲極區域1212及通道區域1214可由來自連結自圖10E之閘極層1008、源極和汲極區域1012及通道區域1014所述之材料來構成之。Referring to FIG. 12E, a non-volatile charge trapping memory component includes a patterned portion of an oxide-nitride-oxide stack formed over substrate 1200. The oxide-nitride-oxide stack includes a first dielectric layer 1202, a charge trap layer 1204, and a second dielectric layer 1206. A gate layer 1208 is placed over the second dielectric layer 1206. The non-volatile charge trapping memory component further includes source and drain regions 1212 on the oxide-nitride-oxide stack side within the substrate 1200 to define the oxide-nitride-oxide stack The channel region 1214 in the lower substrate 1200. A pair of dielectric spacer sidewalls 1210 isolate sidewalls of the first dielectric layer 1202, the charge trap layer 1204, the second dielectric layer 1206, and the gate layer 1208. According to an embodiment of the invention, the charge trapping layer 1204 is comprised of an oxynitride oxyhydroxide moiety 1204A and a bismuth oxynitride containing moiety 1204B as described in FIG. 12E. In one embodiment, the non-volatile charge trapping memory component is a semiconductor-oxide-nitride-oxide-semiconductor type component. Gate layer 1208, source and drain regions 1212, and channel region 1214 can be formed from materials described in connection with gate layer 1008, source and drain regions 1012, and channel region 1014 of FIG. 10E.
在本發明另一觀點中，經由一氧化腔室內之基板頂部表面之基氧化作用所形成之介電層在它生長於該基板上時，較不容易受到該基板內之結晶平面方位差的影響。例如，在一實施例中，不同結晶平面氧化速率所引起之銳角效應係藉由形成於一叢集工具之氧化腔室內之介電層而顯著地降低。圖13A根據本發明一實施例說明包含第一和第二露出結晶平面之基板剖面圖。In another aspect of the present invention, the dielectric layer formed by the base oxidation of the top surface of the substrate in the oxidation chamber is less susceptible to the difference in crystal plane orientation in the substrate when it is grown on the substrate. . For example, in one embodiment, different crystal plane oxidation ratesThe acute angle effect caused by the rate is significantly reduced by the dielectric layer formed in the oxidization chamber of a cluster tool. Figure 13A illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention.
參考至圖13A，一基板1300具有形成於其上之隔離區域1302。基板1300可由連結自圖10A之基板1000所述材料來構成之。隔離區域1302可由適合黏接至基板1300之絕緣材料所構成。基板1300之一露出部分延伸超過隔離區域1302之頂部表面。根據本發明一實施例，該基板1300之露出部分具有一第一露出結晶平面1304及一第二露出結晶平面1306。在一實施例中，該第一露出結晶平面1304之結晶方位係不同於該第二露出結晶平面1306之結晶方位。在一特定實施例中，基板1300係由矽所構成，第一露出結晶平面1304具有<100>方位，且第二露出結晶平面1306具有<110>方位。Referring to FIG. 13A, a substrate 1300 has an isolation region 1302 formed thereon. The substrate 1300 can be constructed from the materials described in connection with the substrate 1000 of FIG. 10A. The isolation region 1302 may be composed of an insulating material suitable for bonding to the substrate 1300. An exposed portion of the substrate 1300 extends beyond the top surface of the isolation region 1302. According to an embodiment of the invention, the exposed portion of the substrate 1300 has a first exposed crystal plane 1304 and a second exposed crystal plane 1306. In one embodiment, the crystal orientation of the first exposed crystal plane 1304 is different from the crystal orientation of the second exposed crystal plane 1306. In a particular embodiment, the substrate 1300 is comprised of tantalum, the first exposed crystalline plane 1304 has a <100> orientation, and the second exposed crystalline plane 1306 has a <110> orientation.
基板1300可於一叢集工具內承受一基氧化製程以藉由耗用(氧化)該基板1300之頂部表面來形成一介電層。在一實施例中，經由一基氧化製程來氧化基板1300包含利用由一氫氧基、一氫過氧基或一氧二基所構成的族群中所選之自由基來進行氧化。圖13B根據本發明一實施例說明分別包含第一和第二結晶平面1304和1306並具有一介電層1308形成於其上之基板1300之剖面圖。在一實施例中，如圖13B所示地，介電層1308之第一部分1308A係形成於第一露出結晶平面1304上，且介電層1308之第二部分1308B係形成於第二露出結晶平面1306上。在一實施例中，介電層1308之第一部分1308A之厚度T1係大約等於介電層1308之第二部分1308B之厚度T2，即使第一露出結晶平面1304和第二露出結晶平面1306之結晶平面方位不同亦然。在一特定實施例中，該基板1300之基氧化作用係實施於大約950-1100攝氏度範圍溫度及大約5-15托耳範圍壓力下。在一實施例中，形成介電層1308之後，基板1300係在大約900-1100攝氏度範圍溫度下，於一含氮大氣之氧化腔室內，回火大約30秒-60秒範圍之持續時間。The substrate 1300 can be subjected to a base oxidation process in a cluster tool to form a dielectric layer by consuming (oxidizing) the top surface of the substrate 1300. In one embodiment, oxidizing substrate 1300 via a base oxidation process comprises oxidizing using a radical selected from the group consisting of monohydric oxy, monohydroperoxy or monooxydiyl. Figure 13B illustrates a cross-sectional view of a substrate 1300 having first and second crystallographic planes 1304 and 1306 and having a dielectric layer 1308 formed thereon, in accordance with an embodiment of the present invention. In one embodiment, as shown in FIG. 13B, a first portion 1308A of the dielectric layer 1308 is formed on the first exposed crystal plane 1304, and a second portion 1308B of the dielectric layer 1308 is formed on the second exposed crystal plane. On 1306. In one embodiment, the thickness T1 of the first portion 1308A of the dielectric layer 1308 is approximately equal to the thickness T2 of the second portion 1308B of the dielectric layer 1308, even if the first exposed crystalline plane 1304 and the second exposed crystalline plane 1306 are crystallized.The same is true for the plane orientation. In a particular embodiment, the basal oxidation of the substrate 1300 is carried out at a temperature in the range of about 950 to 1100 degrees Celsius and a pressure in the range of about 5 to 15 Torr. In one embodiment, after forming the dielectric layer 1308, the substrate 1300 is tempered in a oxidizing chamber containing a nitrogen atmosphere at a temperature in the range of about 900-1100 degrees Celsius for a duration of about 30 seconds to 60 seconds.
在一觀點中，本揭示係指向包含一氧化物分離式多層電荷儲存結構之記憶體元件。圖14係說明一這類半導體記憶體元件1400之實施例剖面側視圖。該記憶體元件1400包含內含形成於一基板1408之表面1406上方之氧化物-氮化物-氧化物-氮化物-氧化物結構1404之半導體-氧化物-氮化物-氧化物-氮化物-氧化物-半導體堆疊1402。基板1408包含對準該閘極堆疊1402並由一通道區域1412分開之一或更多擴散區域1410，例如，源極和汲極區域。大體上，該半導體-氧化物-氮化物-氧化物-氮化物-氧化物-半導體結構1402包含形成於其上並接觸該氧化物-氮化物-氧化物-氮化物-氧化物結構1404之多晶矽或金屬閘極層1414。該閘極1414與該基板1408係由該氧化物-氮化物-氧化物-氮化物-氧化物結構1404所分開或電性隔離。該氧化物-氮化物-氧化物-氮化物-氧化物結構1404包含一下方氧化物薄層或穿隧氧化物薄層1416，其將該堆疊1402與該通道區域1412、一頂部或阻擋氧化物層1420和一多層電荷儲存層1404分開或電性隔離。該多層電荷儲存層大體上包含具有不同之矽、氧和氮組成成分之至少二氮化物層，包含一含矽、含氮又缺氧頂部氮化物層1418、一含矽又含氧底部氮化物層1419及一氧化物抗穿隧層1421。In one aspect, the present disclosure is directed to a memory component comprising an oxide-separated multilayer charge storage structure. Figure 14 is a cross-sectional side view showing an embodiment of such a semiconductor memory device 1400. The memory device 1400 includes a semiconductor-oxide-nitride-oxide-nitride-oxidation containing an oxide-nitride-oxide-nitride-oxide structure 1404 formed over a surface 1406 of a substrate 1408. Object-semiconductor stack 1402. Substrate 1408 includes one or more diffusion regions 1410, such as source and drain regions, that are aligned with the gate stack 1402 and separated by a channel region 1412. In general, the semiconductor-oxide-nitride-oxide-nitride-oxide-semiconductor structure 1402 includes polysilicon formed thereon and contacting the oxide-nitride-oxide-nitride-oxide structure 1404. Or metal gate layer 1414. The gate 1414 and the substrate 1408 are separated or electrically isolated from the oxide-nitride-oxide-nitride-oxide structure 1404. The oxide-nitride-oxide-nitride-oxide structure 1404 includes a thin underlying oxide layer or tunneling oxide layer 1416 that overlaps the stack 1402 with the channel region 1412, a top or barrier oxide Layer 1420 and a plurality of charge storage layers 1404 are separated or electrically isolated. The multilayer charge storage layer generally comprises at least a dinitride layer having different compositions of germanium, oxygen and nitrogen, comprising a germanium-containing, nitrogen-containing and anoxic top nitride layer 1418, a germanium-containing and oxygen-containing bottom nitride. Layer 1419 and an oxide anti-tunneling layer 1421.
已發現到一含矽又含氧底部氮化物層1419降低程式化及抹除後之電荷損失率，其在該保留模式中係顯現一小電壓偏移，同時，一含矽、含氮又缺氧頂部氮化物層1418改善該速度並增加程式化和抹除電壓間之初始差異，未危及使用該矽-氧化物-氮氧化物-氧化物-矽結構實施例所製造記憶體元件之電荷損失率，由此延伸該元件操作壽命。It has been found that a niobium-containing and oxygen-containing bottom nitride layer 1419 reduces stylization and wipingIn addition to the charge loss rate, which exhibits a small voltage shift in the retention mode, while a niobium-containing, nitrogen-containing and anoxic top nitride layer 1418 improves the velocity and increases the stylization and erase voltage. The initial difference does not jeopardize the charge loss rate of the memory element fabricated using the bismuth-oxide-oxynitride-oxide-germanium structure embodiment, thereby extending the operational life of the element.
已進一步發現到該抗穿隧層1421實質上降低在程式化期間所累積於該上方氮化物層1418界面處之電子電荷穿隧至該底部氮化物層1419之可能性，因而相較於圖1所示結構，產生較低漏電結果。It has been further discovered that the anti-tunneling layer 1421 substantially reduces the likelihood of electron charge accumulated at the interface of the upper nitride layer 1418 during the stylization tunneling to the bottom nitride layer 1419, thus compared to FIG. The structure shown produces a lower leakage result.
該多層電荷儲存層可具有約自50埃至150埃之整體厚度且在一些實施例中約少於100埃，同時，該抗穿隧層1421之厚度係約自5埃至20埃，且該些氮化物層1418、1419之厚度實質上係相等。The multilayer charge storage layer can have an overall thickness of from about 50 angstroms to 150 angstroms and, in some embodiments, less than about 100 angstroms, while the thickness of the tunneling resistant layer 1421 is from about 5 angstroms to about 20 angstroms, and The thickness of the nitride layers 1418, 1419 are substantially equal.
現在要參考圖15流程圖來說明根據一實施例之形成或製造一分離式多層電荷儲存結構之方法。A method of forming or fabricating a separate multilayer charge storage structure in accordance with an embodiment will now be described with reference to the flow chart of FIG.
參考圖15，該方法始於在一基板(1500)表面上之含矽層上方形成例如一穿隧氧化物層之第一氧化物層。如上所述地，該穿隧氧化物層可經由包含一電漿氧化製程、現場蒸汽產生技術(ISSG)或一基氧化製程之任何合適手段來形成或沉積之。在一實施例中，該基氧化製程涉及將氫氣(H2)及氧氣(O2)流入一處理腔室或熔爐中，以經由氧化耗用一部分基板來造成該穿隧氧化物層生長。Referring to Figure 15, the method begins with forming a first oxide layer, such as a tunneling oxide layer, over a germanium containing layer on a substrate (1500) surface. As noted above, the tunneling oxide layer can be formed or deposited via any suitable means including a plasma oxidation process, an on-site vapor generation process (ISSG), or a base oxidation process. In one embodiment, the base oxidation process involves flowing hydrogen (H2 ) and oxygen (O2 ) into a processing chamber or furnace to consume a portion of the substrate via oxidation to cause the tunneling oxide layer to grow.
接著，該多層電荷儲存層之第一或底部氮化物或含氮化物層係形成於該穿隧氧化物層(1502)一表面上。在一實施例中，該些氮化物層係以一低壓化學氣相沉積製程，使用例如矽烷(SiH4)、氯矽烷(SiH3Cl)、二氯矽烷或DCS(SiH2Cl2)、四氯矽烷(SiCl4)或雙三級丁氨基矽烷(BTBAS)類之矽來源，例如氮氣(H2)、氨(NH3)、三氧化氮(NO3)或氧化亞氮(N2O)類之氮來源，及例如氧氣(O2)或氧化亞氮(N2O)類之含氧氣體來形成或沉積之。替代性地，已由氘取代氫之氣體可被使用，例如包含以氘化氨(ND3)取代氨。以氣取代氫有利於鈍化該矽-氧化物界面處之矽懸空鍵，由此增加該些元件之NBTI(負偏壓溫度不穩定性)壽命。Next, a first or bottom nitride or nitride-containing layer of the multilayer charge storage layer is formed on a surface of the tunnel oxide layer (1502). In one embodiment, the nitride layers are processed in a low pressure chemical vapor deposition process using, for example, decane (SiH4 ), chlorodecane (SiH3 Cl), dichloromethane or DCS (SiH2 Cl2 ), Sources of chlorocyclohexane (SiCl4 ) or double tertiary butylamino decane (BTBAS), such as nitrogen (H2 ), ammonia (NH3 ), nitrogen trioxide (NO3 ) or nitrous oxide (N2 O) A source of nitrogen, and an oxygen-containing gas such as oxygen (O2 ) or nitrous oxide (N2 O), is formed or deposited. Alternatively, the hydrogen gas is substituted by the deuterium may be used, for example, contains deuterated ammonia (ND3) substituted amino. Substituting hydrogen with gas facilitates passivation of the 矽 dangling bonds at the 矽-oxide interface, thereby increasing the NBTI (negative bias temperature instability) lifetime of the components.
例如，該下方或底部氮化物層可藉由將該基板放置於一沉積腔室並引進包含氧化亞氮、氨及二氯矽烷之製程氣體，同時，維持該腔室在大約自5毫托耳(mT)至500毫托耳壓力下並維持該基板在大約700攝氏度至850攝氏度，且在一些實施例中至少約為760攝氏度之溫度下，持續一段大約自2.5分鐘至20分鐘的時間，而被沉積於該穿隧氧化物層上方。尤其，該製程氣體可包含以約從8：1至1：8比值混合氧化亞氮和氨之第一氣體混合物及約從1：7至7：1比值混合二氯矽烷和氨之第二氣體混合物，且可以大約每分鐘5至200標準立方公分(sccm)之流速來引進。已發現到在這些條件下所產生或沉積之氮氧化物層產生一含矽又含氧之底部氮化物層。For example, the lower or bottom nitride layer can be maintained by placing the substrate in a deposition chamber and introducing a process gas comprising nitrous oxide, ammonia, and methylene chloride, while maintaining the chamber at about 5 mTorr. (mT) to a pressure of 500 mTorr and maintaining the substrate at a temperature of between about 700 degrees Celsius and 850 degrees Celsius, and in some embodiments at least about 760 degrees Celsius, for a period of time ranging from about 2.5 minutes to 20 minutes, and It is deposited over the tunneling oxide layer. In particular, the process gas may comprise a first gas mixture of nitrous oxide and ammonia mixed at a ratio of from about 8:1 to 1:8 and a second gas of dichloromethane and ammonia at a ratio of from about 1:7 to about 7:1. The mixture can be introduced at a flow rate of about 5 to 200 standard cubic centimeters (sccm) per minute. It has been discovered that the oxynitride layer produced or deposited under these conditions produces a ruthenium-containing and oxygen-containing bottom nitride layer.
接著，該抗穿隧層係形成或沉積於該底部氮化物層(1504)之表面上。如同具有該穿隧氧化物層般地，該抗穿隧層可經由包含一電漿氧化製程、現場蒸汽產生技術(ISSG)或一基氧化製程之任何合適手段來形成或沉積之。在一實施例中，該基氧化製程涉及將氫氣(H2)及氧氣(O2)流入一批次處理腔室或熔爐中，以經由氧化耗用一部分底部氮化物層來造成該抗穿隧層之生長。Next, the anti-tunneling layer is formed or deposited on the surface of the bottom nitride layer (1504). As with the tunneling oxide layer, the anti-tunneling layer can be formed or deposited via any suitable means including a plasma oxidation process, an on-site vapor generation process (ISSG) or a base oxidation process. In one embodiment, the base oxidation process involves flowing hydrogen (H2 ) and oxygen (O2 ) into a batch of processing chambers or furnaces to consume a portion of the bottom nitride layer via oxidation to cause the tunneling resistance. The growth of the layer.
該多層電荷儲存層之第二或頂部氮化物層係接著形成於該抗穿隧層(1506)之表面上。該頂部氮化物層可以一化學氣相沉積製程，使用包含氧化亞氮、氨及二氯矽烷之製程氣體，於大約自5毫托耳至500毫托耳腔室壓力下，並於大約700攝氏度至850攝氏度，且在一些實施例中至少約為760攝氏度之基板溫度下，持續一段大約自2.5分鐘至20分鐘時間，而被沉積於該抗穿隧層1421上方。尤其，該製程氣體可包含以約從8：1至1：8比值混合氧化亞氮和氨之第一氣體混合物及約從1：7至7：1比值混合二氯矽烷和氨之第二氣體混合物，且可以大約每分鐘5至20標準立方公分之流速來引進。已發現到在這些條件下所產生或沉積之氮氧化物層產生一含矽、含氮又缺氧之頂部氮化物層1418，其改善該速度並增加在程式化和抹除電壓間之初始差異，未危及使用該矽-氧化物-氮氧化物-氧化物-矽結構實施例所製造記憶體元件之電荷損失率，由此延伸該元件操作壽命。A second or top nitride layer of the multilayer charge storage layer is then formed on the surface of the anti-tunneling layer (1506). The top nitride layer can be used in a chemical vapor deposition process.Process gas comprising nitrous oxide, ammonia, and dichloromethane, at a pressure of from about 5 millitorr to 500 millitorr chamber pressure, and at about 700 degrees Celsius to 850 degrees Celsius, and in some embodiments at least about 760 At a substrate temperature of Celsius, it lasts for a period of about 2.5 minutes to 20 minutes and is deposited over the anti-tunneling layer 1421. In particular, the process gas may comprise a first gas mixture of nitrous oxide and ammonia mixed at a ratio of from about 8:1 to 1:8 and a second gas of dichloromethane and ammonia at a ratio of from about 1:7 to about 7:1. The mixture can be introduced at a flow rate of about 5 to 20 standard cubic centimeters per minute. It has been discovered that the oxynitride layer produced or deposited under these conditions produces a niobium-containing, nitrogen-containing, and oxygen-deficient top nitride layer 1418 which improves the velocity and increases the initial difference between stylized and erase voltages. The charge loss rate of the memory device fabricated using the ruthenium-oxide-oxynitride-oxide-ruthenium structure embodiment is not compromised, thereby extending the operational life of the device.
在一些實施例中，該含矽、含氮又缺氧頂部氮化物層可以一化學氣相沉積製程，使用包含以約從1：7至7：1比值混合雙三級丁氨基矽烷和氨(NH3)之製程氣體，來沉積於該抗穿隧層上方，以進一步包含一所選碳濃度而增加其中之捕獲數量。在該第二氮氧化物層中之所選碳濃度可包含大約從5%至15%之碳濃度。In some embodiments, the ruthenium-containing, nitrogen-containing, and oxygen-deficient top nitride layer can be subjected to a chemical vapor deposition process using a mixture comprising two third-stage butylaminodecane and ammonia at a ratio of from about 1:7 to about 7:1 ( A process gas of NH3 ) is deposited over the anti-tunneling layer to further include a selected carbon concentration to increase the amount of capture therein. The selected carbon concentration in the second oxynitride layer can comprise a carbon concentration of from about 5% to 15%.
最後，一頂部阻擋氧化物層或高溫氧化物層係形成於該多層電荷儲存層(1508)之第二層表面上。如同具有該穿隧氧化物層及該抗穿隧層般地，該高溫氧化物層可經由包含一電漿氧化製程、現場蒸汽產生技術(ISSG)或一基氧化製程之任何合適手段來形成或沉積之。在一實施例中，該高溫氧化物層係使用執行於一電漿製程腔室內之電漿氧化作用來形成。本製程所使用之典型沉積條件係在1500瓦至10000瓦範圍之射頻功率，佔有氫氣量百分比在0%至90%之間之氫氣和氧氣混合物，基板溫度介於300C至400C之間，沉積時間係20至60秒。Finally, a top barrier oxide layer or a high temperature oxide layer is formed on the surface of the second layer of the multilayer charge storage layer (1508). As with the tunneling oxide layer and the anti-tunneling layer, the high temperature oxide layer may be formed by any suitable means including a plasma oxidation process, an on-site steam generation technique (ISSG) or a base oxidation process or Deposition. In one embodiment, the high temperature oxide layer is formed using plasma oxidation performed in a plasma processing chamber. The typical deposition conditions used in this process are RF power in the range of 1500 watts to 10,000 watts, hydrogen and oxygen mixtures with a percentage of hydrogen between 0% and 90%, and substrate temperatures between 300C and 400.Between C, the deposition time is 20 to 60 seconds.
替代性地，該高溫氧化物層係使用一現場蒸氣產生氧化製程來形成之。在一實施例中，該現場蒸氣產生技術係在大約從8至12托耳壓力及大約1050℃溫度下，利用已添加大約從0.5%至33%之氫之含氧氣混合物於例如來自上述應用材料公司之現場蒸氣產生腔室之RTP腔室內執行之。該沉積時間係在20至60秒範圍內。Alternatively, the high temperature oxide layer is formed using an in situ vapor generation oxidation process. In one embodiment, the in situ vapor generation technique utilizes an oxygen-containing mixture having from about 0.5% to 33% hydrogen added at a temperature of from about 8 to 12 Torr and about 1050 ° C, for example, from the above-mentioned application materials. The company's on-site vapor generation chamber is executed in the RTP chamber. The deposition time is in the range of 20 to 60 seconds.
會理解到在任一實施例中，該頂部氮化物層之厚度可隨著在形成該高溫氧化物層之製程期間，多少該頂部氮化物層會被有效地耗用或氧化而做調整或增加。It will be appreciated that in any embodiment, the thickness of the top nitride layer can be adjusted or increased as the top nitride layer is effectively consumed or oxidized during the process of forming the high temperature oxide layer.
選擇性地，該方法可進一步包含在該高溫氧化物層一表面上形成或沉積一含金屬或多晶矽層，以形成該電晶體或元件(1508)之閘極層。該閘極層可為例如由一化學氣相沉積製程所沉積之多晶矽層，以形成一矽-氧化物-氮化物-氧化物-氮化物-氧化物-矽(SONOS)結構。Optionally, the method may further comprise forming or depositing a metal- or polysilicon-containing layer on a surface of the high temperature oxide layer to form a gate layer of the transistor or element (1508). The gate layer can be, for example, a polysilicon layer deposited by a chemical vapor deposition process to form a germanium-oxide-nitride-oxide-nitride-oxide-germanium (SONOS) structure.
在另一觀點中，本揭示也指向包含在一基板表面上或上方所形成通道之二或更多側上方之電荷捕獲區域之多閘極或多閘極表面記憶體元件，及其製造方法。多閘極元件包含平面式及非平面式元件兩者。一平面式多閘極元件(未顯示)大體上包含一雙閘極平面式元件，其中，一些第一層被沉積以在接著形成之通道下面形成一第一閘極，且一些第二層被沉積於其上方以形成一第二閘極。一非平面式多閘極元件大體上包含形成於一基板表面上或上方並由一閘極環繞於三或更多側上之水平或垂直通道。In another aspect, the present disclosure also refers to a multi-gate or multi-gate surface memory element comprising a charge trapping region above two or more sides of a channel formed on or above a substrate surface, and a method of fabricating the same. Multiple gate elements include both planar and non-planar components. A planar multi-gate element (not shown) generally comprises a dual gate planar element, wherein some of the first layer is deposited to form a first gate under the subsequently formed via, and some of the second layer is Deposited thereon to form a second gate. A non-planar multi-gate element generally comprises horizontal or vertical channels formed on or above a substrate surface and surrounded by a gate on three or more sides.
圖16A說明包含一電荷捕獲區域之非平面式多閘極元件實施例。參考至圖16A，該記憶體元件1600，通常稱之為鰭狀物場效電晶體，包含由位於連接該記憶體元件之源極1608和汲極1610之基板1606上之一表面1604上方之半導體材料薄膜或薄層所形成之通道1602。該通道1602之三邊側係由形成該元件之閘極1612之鰭狀物所封閉。該閘極1612(自源極至汲極方向進行估測)之厚度決定該元件之有效通道長度。Figure 16A illustrates an embodiment of a non-planar multi-gate element comprising a charge trapping region. Referring to FIG. 16A, the memory element 1600, commonly referred to as a fin field effect transistor,A channel 1602 is formed comprising a thin film or thin layer of semiconductor material over a surface 1604 of the substrate 1606 that connects the source 1608 and the drain 1610 of the memory device. The three sides of the channel 1602 are enclosed by fins that form the gate 1612 of the component. The thickness of the gate 1612 (estimated from the source to the drain) determines the effective channel length of the component.
根據本揭示，圖16A之非平面式多閘極記憶體元件1600可包含一分離式電荷捕獲區域。圖16B係圖16A之非平面式多閘極元件之一部分剖面圖，包含一部分基板1606、通道1602及說明一多層電荷儲存層1614之閘極1612。該閘極1612進一步包含位在一凸起通道1602上方之穿隧氧化物層1616、一阻擋介電層1618及位在該阻擋層上方以形成該記憶體元件1600之控制閘極之金屬閘極層1620。在一些實施例中，可以一摻雜多晶矽代替金屬來進行沉積，以提供一多晶矽閘極層。該通道1602及閘極1612可直接形成於基板1606上或在該基板上或上方所形成之例如一埋入式氧化物層之絕緣或介電層1622上。In accordance with the present disclosure, the non-planar multi-gate memory device 1600 of FIG. 16A can include a separate charge trapping region. 16B is a partial cross-sectional view of a non-planar multi-gate device of FIG. 16A, including a portion of substrate 1606, channel 1602, and gate 1612 illustrating a plurality of charge storage layers 1614. The gate 1612 further includes a tunnel oxide layer 1616 over the bump via 1602, a blocking dielectric layer 1618, and a metal gate positioned above the barrier layer to form a control gate of the memory device 1600. Layer 1620. In some embodiments, a doped polysilicon can be deposited instead of a metal to provide a polysilicon gate layer. The channel 1602 and the gate 1612 can be formed directly on the substrate 1606 or on an insulating or dielectric layer 1622 such as a buried oxide layer formed on or over the substrate.
參考至圖16B，該多層電荷儲存層1614包含較接近該穿隧氧化物層1616之至少一含氮下方或底部電荷捕獲層1624及位在該底部電荷捕獲層上面之一上方或頂部電荷捕獲層1626。大體上，該頂部電荷捕獲層1626包含一含矽又缺氧氮化物層並包含散佈於多個電荷捕獲層之多數電荷捕獲，而該底部電荷捕獲層1624包含一含氧氮化物或氮氧化矽層且相對於該頂部電荷捕獲層係含氧的，以減少其中之電荷捕獲數量。含氧係意謂著在該底部電荷捕獲層1624中之氧濃度係大約從15至40%，然而在頂部電荷捕獲層1626中之氧濃度係大約小於5%。Referring to FIG. 16B, the multi-layer charge storage layer 1614 includes at least one nitrogen-containing underlying or bottom charge trap layer 1624 that is closer to the tunnel oxide layer 1616 and a charge trap layer above or above the bottom charge trap layer. 1626. In general, the top charge trap layer 1626 comprises a germanium-containing and oxygen-deficient nitride layer and comprises a plurality of charge traps interspersed among a plurality of charge trap layers, and the bottom charge trap layer 1624 comprises an oxynitride or bismuth oxynitride. The layer is oxygen-containing relative to the top charge trap layer to reduce the amount of charge trapped therein. Oxygen means that the oxygen concentration in the bottom charge trap layer 1624 is from about 15 to 40%, whereas the oxygen concentration in the top charge trap layer 1626 is about less than 5%.
在一實施例中，該阻擋介電層1618也包含例如一高溫氧化物之氧化物層，以提供一ONNO結構。該通道1602及該上方ONNO結構可直接形成於一矽基板1606上並位在一摻雜多晶矽閘極層1620上方以提供一SONNOS結構。In an embodiment, the blocking dielectric layer 1618 also includes, for example, a high temperature oxidation.An oxide layer of the material to provide an ONNO structure. The channel 1602 and the upper ONNO structure can be formed directly on a germanium substrate 1606 and over a doped polysilicon gate layer 1620 to provide a SONNOS structure.
在一些實施例中，例如圖16B所示那個，該多層電荷儲存層1614進一步包含至少一中間或抗穿隧薄層1628，包含例如一氧化物之介電層以將該頂部電荷捕獲層1626與該底部電荷捕獲層1624分開。如上所述地，該抗穿隧層1628實質上降低在程式化期間所累積於該上方氮化物層1626界面處之電子電荷穿隧至該底部氮化物層1624之可能性。In some embodiments, such as that shown in FIG. 16B, the multi-layer charge storage layer 1614 further includes at least one intermediate or anti-tunneling layer 1628 comprising a dielectric layer such as an oxide to dispose the top charge trap layer 1626 with The bottom charge trap layer 1624 is separated. As described above, the anti-tunneling layer 1628 substantially reduces the likelihood of electron charge trapped at the interface of the upper nitride layer 1626 during tunneling to the bottom nitride layer 1624.
如同上述實施例，該底部電荷捕獲層1624及該頂部電荷捕獲層1626中任一者或兩者可包含氮化矽或氮氧化矽，並可例如經由包含氧化亞氮/氨及二氯矽烷/氨氣體混合物之化學氣相沉積製程，以量身定做之比值和流速來提供一含矽又含氧之氮氧化物層而形成之。該多層電荷儲存結構之第二氮化物層係接著形成於該中間氧化物層上。該頂部電荷捕獲層1626具有不同於該底部電荷捕獲層1624那個之氧、氮及/或矽化學計量組成成分，也可經由一化學氣相沉積製程，使用包含二氯矽烷/氨及氧化亞氮/氨氣體混合物之製程氣體，以量身定做之比值和流速來提供一含矽又含氧之氮氧化物層而形成或沉積之。As with the above embodiments, either or both of the bottom charge trap layer 1624 and the top charge trap layer 1626 may comprise tantalum nitride or hafnium oxynitride and may, for example, comprise nitrous oxide/ammonia and dichloromethane/ The chemical vapor deposition process of the ammonia gas mixture is formed by providing a niobium-containing and oxygen-containing oxynitride layer at a tailored ratio and flow rate. A second nitride layer of the multilayer charge storage structure is then formed over the intermediate oxide layer. The top charge trap layer 1626 has a different stoichiometric composition of oxygen, nitrogen, and/or helium than the bottom charge trap layer 1624, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and nitrous oxide. The process gas of the ammonia/gas mixture is formed or deposited by providing a layer of ruthenium-containing and oxygen-containing oxynitride at a tailored ratio and flow rate.
在包含一含氧化物之中間或抗穿隧層1628之那些實施例中，該抗穿隧層可使用基氧化作用來氧化該底部氮氧化物層至一所選深度而形成之。基氧化作用可在例如1000-1100攝氏度溫度下使用一單晶圓工具或在800-900攝氏度溫度下使用一批次反應器工具來執行之。一氫氣和氧氣混合物可在300-500托耳壓力下運用於一批次製程或在10-15托耳壓力下使用一單一氣相工具，使用一單晶圓工具則持續1-2分鐘時間，或者，使用一批次製程則持續30分鐘-1小時時間。In those embodiments comprising an intermediate or anti-tunneling layer 1628, the anti-tunneling layer can be formed using a base oxidation to oxidize the bottom oxynitride layer to a selected depth. The base oxidation can be carried out using, for example, a single wafer tool at a temperature of 1000-1100 degrees Celsius or using a batch of reactor tools at a temperature of 800-900 degrees Celsius. A hydrogen and oxygen mixture can be used in a batch process at 300-500 Torr or at 10-15 Torr.With a single gas phase tool, a single wafer tool can be used for 1-2 minutes, or a batch process can last for 30 minutes to 1 hour.
最後，在包含一含氧化物之阻擋介電層1618之那些實施例中，該氧化物可經由任何合適手段來形成或沉積之。在一實施例中，該阻擋介電層1618之氧化物係以一高溫氧化物化學氣相沉積製程來沉積之高溫氧化物。替代性地，該阻擋介電層1618或阻擋氧化物層可為熱生長，然而會理解到，在本實施例中，該頂部氮化物厚度可隨著在熱生長該阻擋氧化物層之製程期間，多少該頂部氮化物層會被有效地耗用或氧化而做調整或增加。一第三選項係使用基氧化作用來氧化該頂部氮化物層至一所選深度。Finally, in those embodiments comprising an oxide-containing barrier dielectric layer 1618, the oxide can be formed or deposited via any suitable means. In one embodiment, the oxide of the barrier dielectric layer 1618 is a high temperature oxide deposited by a high temperature oxide chemical vapor deposition process. Alternatively, the blocking dielectric layer 1618 or the barrier oxide layer may be thermally grown, however it will be appreciated that in the present embodiment, the top nitride thickness may be during the process of thermally growing the barrier oxide layer. How much of this top nitride layer is effectively utilised or oxidized to adjust or increase. A third option uses base oxidation to oxidize the top nitride layer to a selected depth.
該底部電荷捕獲層1624之合適厚度可從大約30埃至大約160埃(具有一些變異值，例如，±10埃)，其中，大約5-20埃厚度可經由基氧化作用來耗用，以形成該抗穿隧層1628。該頂部電荷捕獲層1626之合適厚度可至少為30埃。在一些實施例中，該頂部電荷捕獲層1626可形成高達130埃厚，其中，30-70埃厚度可經由基氧化作用來耗用，以形成該阻擋介電層1618。在一些實施例中，在該底部電荷捕獲層1624及頂部電荷捕獲層1626間之厚度比值係大約1：1，然而其它比值也是可行的。A suitable thickness of the bottom charge trap layer 1624 can range from about 30 angstroms to about 160 angstroms (with some variation, for example, ±10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to form The anti-through tunnel layer 1628. A suitable thickness of the top charge trap layer 1626 can be at least 30 angstroms. In some embodiments, the top charge trap layer 1626 can be formed up to 130 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via basal oxidation to form the blocking dielectric layer 1618. In some embodiments, the thickness ratio between the bottom charge trap layer 1624 and the top charge trap layer 1626 is about 1:1, although other ratios are also possible.
在其它實施例中，該頂部電荷捕獲層1626及該阻擋介電層1618中任一者或兩者可包含一高介電係數介電質。合適高介電係數介電質包含例如矽氧氮化鉿、矽氧化鉿或氧化鉿類之含鉿材料，例如矽氧氮化鋯、矽氧化鋯或氧化鋯類之含鋯材料，及例如三氧化二釔類之含釔材料。In other embodiments, either or both of the top charge trapping layer 1626 and the blocking dielectric layer 1618 can comprise a high dielectric constant dielectric. Suitable high-k dielectrics include cerium-containing materials such as cerium lanthanum oxynitride, cerium lanthanum oxide or cerium oxide, such as zirconium-containing materials such as zirconium oxynitride, hafnium oxynitride or zirconia, and for example three A bismuth-containing material containing cerium oxide.
在圖17A及17B所示之另一實施例中，該記憶體元件可包含由位在連接該記憶體元件之源極和汲極之基板上之一表面上方之半導體材料薄膜所形成之奈米線通道。奈米線通道係意謂著在一結晶矽材料薄條帶內所形成之傳導通道，具有最大剖面尺寸約為10奈米(nm)或更小，且較佳地，大約小於6奈米。選擇性地，該通道可被形成以相對於該通道一長軸具有<100>表面結晶方位。In another embodiment shown in FIGS. 17A and 17B, the memory device can include a semiconductor disposed over a surface of a substrate connected to a source and a drain of the memory device.The nanowire channel formed by the material film. The nanowire channel means a conductive channel formed in a thin strip of crystalline germanium material having a maximum cross-sectional dimension of about 10 nanometers (nm) or less, and preferably less than about 6 nanometers. Optionally, the channel can be formed to have a <100> surface crystalline orientation relative to a long axis of the channel.
參考至圖17A，該記憶體元件1700包含形成自一基板1706上之表面上或上方之半導體材料薄膜或薄層並連接該記憶體元件之源極1708和汲極1710之水平奈米線通道1702。在所示實施例中，該元件具有繞式閘極(GAA)結構，其中，該奈米通道1702之所有邊側係由該元件之閘極1712所封閉。該閘極1712(自源極至汲極方向進行估測)之厚度決定該元件之有效通道長度。Referring to FIG. 17A, the memory device 1700 includes a thin film or thin layer of semiconductor material formed on or over a surface of a substrate 1706 and connected to a source 1708 and a drain 1710 of the memory device. . In the illustrated embodiment, the component has a wound gate (GAA) configuration in which all sides of the nanochannel 1702 are enclosed by a gate 1712 of the component. The thickness of the gate 1712 (estimated from the source to the drain) determines the effective channel length of the component.
根據本揭示，圖17A之非平面式多閘極記憶體元件1700可包含一分離式電荷捕獲區域。圖17B係圖17A之非平面式多閘極元件之一部分剖面圖，包含一部分基板1706、通道1702及說明一分離式電荷儲存區域之閘極1612。參考至圖17B，該閘極1712包含位在該奈米線通道1702上方之穿隧氧化物層1714、一分離式電荷捕獲區域、一阻擋介電層1716及位在該阻擋層上方以形成該記憶體元件1600之控制閘極之閘極層1718。該閘極層1718可包括一沉積金屬或一摻雜多晶矽。該分離式電荷捕獲區域包含較接近該穿隧氧化物層1714之至少一含氮化物之內部電荷捕獲層1720及位在該內部電荷捕獲層上方之一外部電荷捕獲層1722。大體上，該外部電荷捕獲層1722包括一含矽又缺氧氮化物層並包括散佈於多個電荷捕獲層之多數電荷捕獲，而該內部電荷捕獲層1720包括一含氧氮化物或氮氧化矽層且相對於該外部電荷捕獲層係含氧的，以減少其中之電荷捕獲數量。In accordance with the present disclosure, the non-planar multi-gate memory device 1700 of FIG. 17A can include a separate charge trapping region. 17B is a partial cross-sectional view of a non-planar multi-gate device of FIG. 17A, including a portion of substrate 1706, channel 1702, and gate 1612 illustrating a separate charge storage region. Referring to FIG. 17B, the gate 1712 includes a tunneling oxide layer 1714 over the nanowire channel 1702, a separate charge trapping region, a blocking dielectric layer 1716, and over the barrier layer to form the gate. The gate layer 1718 of the control gate of the memory element 1600. The gate layer 1718 can include a deposited metal or a doped polysilicon. The separate charge trapping region includes at least one nitride-containing internal charge trapping layer 1720 proximate to the tunneling oxide layer 1714 and an external charge trapping layer 1722 positioned above the internal charge trapping layer. In general, the external charge trap layer 1722 includes a germanium-containing and oxygen-deficient nitride layer and includes a majority of charge traps dispersed across a plurality of charge trap layers, and the internal charge trap layer 1720 includes an oxynitride or bismuth oxynitride. The layer is oxygen-containing relative to the external charge trapping layer to reduce the amount of charge trapped therein.
在一些實施例中，如同所示那個，該分離式電荷捕獲區域進一步包含至少一中間或抗穿隧薄層1724，包括例如一氧化物介電層，以將外部電荷捕獲層1722與內部電荷捕獲層1720分開。該抗穿隧層1724實質上降低在程式化期間所累積於外部電荷捕獲層1722界面處之電子電荷穿隧至該內部氮化物層1720之可能性，因而導致較低漏電。In some embodiments, as shown, the split charge trapping region further includes at least one intermediate or anti-tunneling thin layer 1724, including, for example, an oxide dielectric layer to trap the external charge trapping layer 1722 with internal charge. Layer 1720 is separated. The anti-piercing layer 1724 substantially reduces the likelihood of electrons trapped at the interface of the external charge trapping layer 1722 during the stylization tunneling to the internal nitride layer 1720, thereby resulting in lower leakage.
如同上述實施例，該內部電荷捕獲層1720及該外部電荷捕獲層1722中任一者或兩者可包括氮化矽或氮氧化矽，並可例如經由包含氧化亞氮/氨及二氯矽烷/氨氣體混合物之化學氣相沉積製程以量身定做之比值和流速來提供一含矽又含氧之氮氧化物層而形成之。該多層電荷儲存結構之第二氮化物層接著被形成於該中間氧化物層上。該外部電荷捕獲層1722具有不同於該內部電荷捕獲層1720那個之氧、氮及/或矽化學計量組成成分，也可經由一化學氣相沉積製程，使用包含二氯矽烷/氨及氧化亞氮/氨氣體混合物之製程氣體，以量身定做之比值和流速來提供一含矽又缺氧之頂部氮化物層而形成或沉積之。As with the above embodiments, either or both of the inner charge trap layer 1720 and the outer charge trap layer 1722 may comprise tantalum nitride or hafnium oxynitride and may, for example, comprise nitrous oxide/ammonia and dichloromethane/ The chemical vapor deposition process of the ammonia gas mixture is formed by providing a niobium-containing and oxygen-containing oxynitride layer at a tailored ratio and flow rate. A second nitride layer of the multilayer charge storage structure is then formed over the intermediate oxide layer. The external charge trap layer 1722 has a different stoichiometric composition of oxygen, nitrogen and/or helium than the inner charge trap layer 1720, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and nitrous oxide. The process gas of the / ammonia gas mixture is formed or deposited by providing a niobium- and oxygen-deficient top nitride layer at a tailored ratio and flow rate.
在包含一含氧化物之中間或抗穿隧層1724之那些實施例中，該抗穿隧層可使用基氧化作用來氧化該內部電荷捕獲層1720至一所選深度而形成之。基氧化作用可在例如1000-1100攝氏度溫度下使用一單晶圓工具或在800-900攝氏度溫度下使用一批次反應器工具來執行之。一氫氣和氧氣混合物可在300-500托耳壓力下運用於一批次製程或在10-15托耳壓力下使用一單一氣相工具，使用一單晶圓工具則持續1-2分鐘時間，或者，使用一批次製程則持續30分鐘-1小時時間。In those embodiments including an oxide-containing intermediate or anti-tunneling layer 1724, the anti-tunneling layer can be formed using base oxidation to oxidize the internal charge trapping layer 1720 to a selected depth. The base oxidation can be carried out using, for example, a single wafer tool at a temperature of 1000-1100 degrees Celsius or using a batch of reactor tools at a temperature of 800-900 degrees Celsius. A hydrogen and oxygen mixture can be used in a batch process at 300-500 Torr or a single gas phase tool at 10-15 Torr, using a single wafer tool for 1-2 minutes. Alternatively, use a batch process for a period of 30 minutes to 1 hour.
最後，在包括氧化物之阻擋介電層1716之那些實施例中，該氧化物可經由任何合適手段來形成或沉積之。在一實施例中，該阻擋介電層1716之氧化物係以一高溫氧化物化學氣相沉積製程來沉積之高溫氧化物。替代性地，該阻擋介電層1716或阻擋氧化物層可為熱生長，然而會理解到，在本實施例中，該外部電荷捕獲層1722之厚度也許需要隨著在熱生長該阻擋氧化物層之製程期間，多少該頂部氮化物層被有效地耗用或氧化而做調整或增加。Finally, in those embodiments including the barrier dielectric layer 1716 of oxide,The oxide can be formed or deposited by any suitable means. In one embodiment, the oxide of the barrier dielectric layer 1716 is a high temperature oxide deposited by a high temperature oxide chemical vapor deposition process. Alternatively, the blocking dielectric layer 1716 or the blocking oxide layer may be thermally grown, however it will be appreciated that in the present embodiment, the thickness of the external charge trapping layer 1722 may need to be grown with thermal growth of the blocking oxide. During the processing of the layer, how much of the top nitride layer is effectively consumed or oxidized to adjust or increase.
該內部電荷捕獲層1720之合適厚度可從大約30埃至大約80埃(具有一些變異值，例如，±10埃)，其中，大約5-20埃厚度可經由基氧化作用來耗用，以形成該抗穿隧層1724。該外部電荷捕獲層1722之合適厚度至少為30埃。在一些實施例中，該外部電荷捕獲層1722可形成高達170埃厚，其中，30-70埃厚度可經由基氧化作用來耗用，以形成該阻擋介電層1716。在一些實施例中，在該內部電荷捕獲層1720及該外部電荷捕獲層1722間之厚度比值係大約1：1，然而其它比值也是可行的。A suitable thickness of the internal charge trap layer 1720 can range from about 30 angstroms to about 80 angstroms (with some variation, for example, ±10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to form The anti-through tunnel layer 1724. The outer charge trap layer 1722 has a suitable thickness of at least 30 angstroms. In some embodiments, the outer charge trap layer 1722 can be formed up to 170 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via basal oxidation to form the blocking dielectric layer 1716. In some embodiments, the thickness ratio between the inner charge trap layer 1720 and the outer charge trap layer 1722 is about 1:1, although other ratios are also possible.
在其它實施例中，該外部電荷捕獲層1722及該阻擋介電層1716中任一者或兩者可包括一高介電係數介電質。合適高介電係數介電質包含例如矽氧氮化鉿、矽氧化鉿或氧化鉿類之含鉿材料，例如矽氧氮化鋯、矽氧化鋯或氧化鋯類之含鋯材料，及例如三氧化二釔類之含釔材料。In other embodiments, either or both of the external charge trapping layer 1722 and the blocking dielectric layer 1716 can comprise a high dielectric constant dielectric. Suitable high-k dielectrics include cerium-containing materials such as cerium lanthanum oxynitride, cerium lanthanum oxide or cerium oxide, such as zirconium-containing materials such as zirconium oxynitride, hafnium oxynitride or zirconia, and for example three A bismuth-containing material containing cerium oxide.
圖17C說明圖17A中安排成位元成本可調或BiCS架構1726之非平面式多閘極元件1700垂直串之剖面圖。該架構1726由一非平面式多閘極元件1700垂直串或堆疊所構成，其中，每一個元件或單元包含位在該基板1706上方並連接該記憶體元件之源極和汲極(未顯示於圖形中)之通道1702，具有一繞式閘極(GAA)結構，其中，該奈米線通道1702之所有邊側係由一閘極1712所封閉。相較於一簡單層堆疊，該BiCS架構減少關鍵性微影成像步驟數，使得每一記憶體位元之成本下降。Figure 17C illustrates a cross-sectional view of the vertical string of non-planar multi-gate elements 1700 arranged in Figure 17A as a bit cost adjustable or BiCS architecture 1726. The architecture 1726 is comprised of a vertical string or stack of non-planar multi-gate elements 1700, wherein each element or cell includes a source and a drain located above the substrate 1706 and connected to the memory element (not shown) Channel 1702 of the figure) has a wound gate (GAA) structure in which all sides of the nanowire channel 1702It is closed by a gate 1712. Compared to a simple layer stack, the BiCS architecture reduces the number of critical lithography imaging steps, resulting in a reduction in the cost per memory bit.
在另一實施例中，該記憶體元件係或包含一非平面式元件，包含由一基板上之一些傳導半導體層上方或之處凸出的半導體材料內或之中所形成之一垂直奈米線通道。在圖18A切面所示之本實施例一版本中，該記憶體元件1800包括由連接該元件之源極1804和汲極1806之半導體材料圓柱體中所形成之垂直奈米線通道1802。該通道1802係由一穿隧氧化物層1808、一電荷捕獲區域1810、一阻擋層1812及位於該阻擋層上面以形成該記憶體元件1800之控制閘極之閘極層1814所環繞。該通道1802可包含在一實質上實心半導體材料圓柱體外層內之環狀區域，或包含形成於一介電填充材料圓柱體上方之環狀層。如同上述水平奈米線，該通道1802可包括用以形成一單結晶通道之多晶矽或再結晶多晶矽。選擇性地，於該通道1802包含一結晶矽所在處，該通道可被形成以相對於該通道一長軸具有<100>表面結晶方位。In another embodiment, the memory component is or comprises a non-planar component comprising one of a plurality of semiconductor nanomaterials formed in or on a semiconductor material overlying a conductive semiconductor layer on a substrate. Line channel. In the first embodiment of the embodiment shown in Fig. 18A, the memory element 1800 includes a vertical nanowire channel 1802 formed by a column of semiconductor material connecting the source 1804 and the drain 1806 of the element. The channel 1802 is surrounded by a tunneling oxide layer 1808, a charge trapping region 1810, a barrier layer 1812, and a gate layer 1814 overlying the barrier layer to form a control gate of the memory device 1800. The channel 1802 can comprise an annular region within a substantially outer layer of a substantially solid semiconductor material cylinder or an annular layer formed over a cylinder of dielectric filler material. Like the horizontal nanowires described above, the channel 1802 can include polycrystalline germanium or recrystallized polycrystalline germanium to form a single crystalline channel. Optionally, the channel 1802 includes a crystalline germanium that can be formed to have a <100> surface crystalline orientation relative to a long axis of the channel.
在一些實施例中，例如圖18B所示那個，該電荷捕獲區域1810可為一分離式電荷捕獲區域，包含最接近該穿隧氧化物層1808之至少一第一或內部電荷捕獲層1816及一第二或外部電荷捕獲層1818。選擇性地，該第一和第二電荷捕獲層可由一中間氧化物或抗穿隧層1820所分開。In some embodiments, such as the one shown in FIG. 18B, the charge trapping region 1810 can be a separate charge trapping region comprising at least a first or internal charge trapping layer 1816 and one closest to the tunneling oxide layer 1808. A second or external charge trap layer 1818. Optionally, the first and second charge trapping layers may be separated by an intermediate oxide or anti-tunneling layer 1820.
如同上述實施例，該第一電荷捕獲層1816及該第二電荷捕獲層1818中任一者或兩者可包括氮化矽或氮氧化矽，並可經由例如包含氧化亞氮/氨及二氯矽烷/氨氣體混合物之化學氣相沉積製程，以量身定做之比值和流速來提供一含矽又含氧之氮氧化物層而形成之。As with the above embodiments, either or both of the first charge trap layer 1816 and the second charge trap layer 1818 may include tantalum nitride or hafnium oxynitride, and may include, for example, nitrous oxide/ammonia and dichloride. A chemical vapor deposition process of a decane/ammonia gas mixture is formed by providing a niobium-containing and oxygen-containing oxynitride layer at a tailored ratio and flow rate.
最後，該第二電荷捕獲層1818及該阻擋層1812中任一者或兩者可包括一高介電係數介電質，例如，矽氧氮化鉿、矽氧化鉿、氧化鉿、矽氧氮化鋯、矽氧化鋯、氧化鋯或三氧化二釔。Finally, either or both of the second charge trap layer 1818 and the barrier layer 1812 may comprise a high dielectric constant dielectric, for example, hafnium oxynitride, antimony oxide, antimony oxide, antimony oxide Zirconia, yttria zirconia, zirconia or antimony trioxide.
該第一電荷捕獲層1816之合適厚度可從大約30埃至大約80埃(具有一些變異值，例如，±10埃)，其中，大約5-20埃厚度可經由基氧化作用來耗用，以形成該抗穿隧層1820。該第二電荷捕獲層1818之合適厚度至少為30埃，且該阻擋介電層1812之合適厚度可約為30-70埃。A suitable thickness of the first charge trap layer 1816 can range from about 30 angstroms to about 80 angstroms (with some variation, for example, ±10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to The anti-tunneling layer 1820 is formed. A suitable thickness of the second charge trap layer 1818 is at least 30 angstroms, and a suitable thickness of the barrier dielectric layer 1812 can be about 30-70 angstroms.
圖18A之記憶體元件1800不是使用一閘極優先就是使用閘極後製方案來製造之。圖19A-F說明用於製造圖18A之非平面式多閘極元件之閘極優先方案。圖20A-F說明用於製造圖18A之非平面式多閘極元件之閘極後製方案。The memory component 1800 of Figure 18A is fabricated using either a gate priority or a gate post scheme. 19A-F illustrate a gate priority scheme for fabricating the non-planar multi-gate element of FIG. 18A. 20A-F illustrate a gate post-production scheme for fabricating the non-planar multi-gate element of FIG. 18A.
參考至圖19A，在一閘極優先方案中，例如一阻擋氧化物之第一或下方介電層1902係形成於一基板1906內，例如一源極或一汲極之第一摻雜擴散區域1904上方。一閘極層1908係沉積於該第一介電層1902上方以形成該元件之控制閘極，且一第二或上方介電層1910形成於其上方。如同上述實施例，該第一和第二介電層1902、1910可經由化學氣相沉積製程、基氧化製程來沉積，或經由氧化一部分下層或下方基板而形成之。該閘極層1908可包括經由化學氣相沉積製程所沉積之金屬或摻雜多晶矽。大體上，該閘極層1908之厚度約為40-50埃，且該第一和第二介電層1902、1910約為20-80埃。Referring to FIG. 19A, in a gate priority scheme, for example, a first or lower dielectric layer 1902 of a barrier oxide is formed in a substrate 1906, such as a source or a first doped diffusion region of a drain. Above 1904. A gate layer 1908 is deposited over the first dielectric layer 1902 to form a control gate of the device, and a second or upper dielectric layer 1910 is formed thereover. As with the above embodiments, the first and second dielectric layers 1902, 1910 can be deposited via a chemical vapor deposition process, a base oxidation process, or via oxidation of a portion of the lower or lower substrate. The gate layer 1908 can include a metal or doped polysilicon deposited via a chemical vapor deposition process. Generally, the gate layer 1908 has a thickness of about 40-50 angstroms, and the first and second dielectric layers 1902, 1910 are about 20-80 angstroms.
參考至圖19B，一第一開口1912係蝕刻穿透該上方閘極層1908及該第一和第二介電層1902、1910，到達該基板1906內之擴散區域1904。接著，穿隧氧化物層1914、電荷捕獲區域1916及阻擋介電層1918係接著沉積於該開口中，並將該上方介電層1910之表面平坦化以產生圖19C所示之中間結構。Referring to FIG. 19B, a first opening 1912 is etched through the upper gate layer 1908 and the first and second dielectric layers 1902, 1910 to reach a diffusion region in the substrate 1906.1904. Next, a tunnel oxide layer 1914, a charge trapping region 1916, and a blocking dielectric layer 1918 are subsequently deposited in the opening, and the surface of the upper dielectric layer 1910 is planarized to produce the intermediate structure shown in FIG. 19C.
雖未顯示，但是會了解到如同上述實施例，該電荷捕獲區域1916可包含一分離式電荷捕獲區域，包括較接近該穿隧氧化物層1914之至少一下方或底部電荷捕獲層及位在該底部電荷捕獲層上面之一上方或頂部電荷捕獲層。大體上，該頂部電荷捕獲層包括一含矽又缺氧之氮化物層，並包括散佈於多個電荷捕獲層之多數電荷捕獲，而該底部電荷捕獲層包括一含氧氮化物或氮氧化矽，且相對於該頂部電荷捕獲層係含氧的，以減少其中之電荷捕獲數量。在一些實施例中，該分離式電荷捕獲區域1916進一步包含至少一中間或抗穿隧薄層，該薄層包括例如一氧化物之介電質以分開該頂部電荷捕獲層與該底部電荷捕獲層。Although not shown, it will be appreciated that as with the above-described embodiments, the charge trapping region 1916 can include a separate charge trapping region including at least one lower or bottom charge trapping layer closer to the tunneling oxide layer 1914 and Above or at the top of the bottom charge trap layer. Generally, the top charge trap layer comprises a germanium-containing and oxygen-deficient nitride layer and includes a majority of charge traps dispersed in a plurality of charge trap layers, and the bottom charge trap layer comprises an oxynitride or bismuth oxynitride layer. And with respect to the top charge trapping layer containing oxygen to reduce the amount of charge trapping therein. In some embodiments, the split charge trap region 1916 further includes at least one intermediate or anti-channel tunneling layer, the thin layer including a dielectric such as an oxide to separate the top charge trap layer from the bottom charge trap layer .
接著，圖19D之第二或通道開口1920係異向性地蝕刻穿透穿隧氧化物層1914、電荷捕獲區域1916及阻擋介電層1918。參考至圖19E，一半導體材料1922係沉積於該通道開口中，以於其中形成一垂直通道1924。該垂直通道1924可包含在一實質上實心半導體材料圓柱體外層內之環狀區域，或如圖19E所示地，可包含環繞一介電填充材料1926圓柱體之獨立半導體材料層1922。Next, the second or via opening 1920 of FIG. 19D is anisotropically etched through the tunneling oxide layer 1914, the charge trapping region 1916, and the blocking dielectric layer 1918. Referring to Figure 19E, a semiconductor material 1922 is deposited in the via opening to form a vertical via 1924 therein. The vertical channel 1924 can comprise an annular region within a substantially outer layer of a substantially solid semiconductor material, or as shown in Figure 19E, can comprise a separate layer of semiconductor material 1922 surrounding a cylinder of dielectric filler material 1926.
參考至圖19F，將該上方介電層1910表面平坦化，且包含形成於其中之例如一源極或一汲極之第二摻雜擴散區域1930之半導體材料層1928沉積於該上方介電層上方以形成所示元件。Referring to FIG. 19F, the surface of the upper dielectric layer 1910 is planarized, and a semiconductor material layer 1928 including a second doped diffusion region 1930 formed therein, for example, a source or a drain, is deposited on the upper dielectric layer. Top to form the components shown.
參考至圖20A，在一閘極後製方案中，例如一氧化物之介電層2002係形成於一基板2006表面上之犧牲層2004上方，一開口係蝕刻穿透該介電及犧牲層並於其中形成一垂直通道2008。如同上述實施例，該垂直通道2008可包含在例如多晶矽或單結晶矽之實質上實心半導體材料2010圓柱體之外層內之環狀區域，或可包含環繞一介電填充材料(未顯示)圓柱體之獨立半導體材料層。該介電層2002可包括能夠電性隔離該記憶體元件1800中接著形成之閘極層與一上方電性作用層或另一記憶體元件之例如氧化矽的任何合適介電材料。該犧牲層2004可包括相對於該介電層2002、基板2006和垂直通道2008之材料可具有高選擇性來蝕刻或移除之任何合適材料。Referring to FIG. 20A, in a gate post-production scheme, for example, a dielectric of oxideA layer 2002 is formed over the sacrificial layer 2004 on the surface of a substrate 2006. An opening etches through the dielectric and sacrificial layers and forms a vertical via 2008 therein. As with the above embodiments, the vertical channel 2008 can comprise an annular region within a layer of a substantially solid semiconductor material 2010 cylinder such as a polycrystalline germanium or a single crystalline germanium, or can comprise a cylindrical surrounding a dielectric fill material (not shown). A layer of independent semiconductor material. The dielectric layer 2002 can include any suitable dielectric material that can electrically isolate a gate layer that is subsequently formed in the memory element 1800 from an upper active layer or another memory element, such as hafnium oxide. The sacrificial layer 2004 can include any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer 2002, substrate 2006, and vertical channel 2008.
參考至圖20B，一第二開口2012係蝕刻穿透介電及犧牲層2002、2004，到達該基板1906，且該犧牲層2004被蝕刻或移除。該犧牲層2004可包括相對於該介電層2002、基板2006和垂直通道2008之材料可具有高選擇性來蝕刻或移除之任何合適材料。在一實施例中，該犧牲層2004包括可經由緩衝式氧化物蝕刻技術(BOE蝕刻技術)來移除。Referring to FIG. 20B, a second opening 2012 is etched through the dielectric and sacrificial layers 2002, 2004 to the substrate 1906, and the sacrificial layer 2004 is etched or removed. The sacrificial layer 2004 can include any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer 2002, substrate 2006, and vertical channel 2008. In an embodiment, the sacrificial layer 2004 includes removal via a buffered oxide etch technique (BOE etch technique).
參考至圖20C及20D，穿隧氧化物層2014、電荷捕獲區域2016及阻擋介電層2018係依序沉積於該開口中，且將該介電層2002之表面平坦化以產生圖20C所示之中間結構。在一些實施例中，例如圖20D所示那個，該電荷捕獲區域2016可為一分離式電荷捕獲區域，包含最接近該穿隧氧化物層2014之至少一第一或內部電荷捕獲層2016a及一第二或外部電荷捕獲層2016b。選擇性地，該第一和第二電荷捕獲層可由一中間氧化物或抗穿隧層2020所分開。Referring to FIGS. 20C and 20D, a tunneling oxide layer 2014, a charge trapping region 2016, and a blocking dielectric layer 2018 are sequentially deposited in the opening, and the surface of the dielectric layer 2002 is planarized to produce the surface shown in FIG. 20C. The middle structure. In some embodiments, such as the one shown in FIG. 20D, the charge trapping region 2016 can be a separate charge trapping region comprising at least one first or internal charge trapping layer 2016a and one closest to the tunneling oxide layer 2014. Second or external charge trapping layer 2016b. Optionally, the first and second charge trapping layers may be separated by an intermediate oxide or anti-tunneling layer 2020.
接著，一閘極層2022被沉積至該第二開口2012中，並將該上方介電層2002之表面平坦化以產生圖20E所示之中間結構。如同上述實施例，該閘極層2022可包括一沉積金屬或一摻雜多晶矽。最後，一開口2024係蝕刻穿透該閘極層2022以形成各記憶體元件2026之控制閘極。Next, a gate layer 2022 is deposited into the second opening 2012, and theThe surface of the upper dielectric layer 2002 is planarized to produce the intermediate structure shown in Figure 20E. As with the above embodiments, the gate layer 2022 can comprise a deposited metal or a doped polysilicon. Finally, an opening 2024 is etched through the gate layer 2022 to form a control gate for each memory element 2026.
因此，一非揮發性電荷捕獲記憶體元件之製造方法已被揭示。根據本發明一實施例，一基板係在一叢集工具之第一製程腔室內承受一第一基氧化製程以形成一第一介電層。一電荷捕獲層可接著在該叢集工具之第二製程腔室內沉積於該第一介電層上方。在一實施例中，該電荷捕獲層接著係在該叢集工具之第一製程腔室內承受一第二基氧化製程以在該電荷捕獲層上方形成一第二介電層。藉由在一叢集工具內形成一氧化物-氮化物-氧化物(ONO)堆疊所有各層，各層間之界面損毀可被降低。因此，根據本發明一實施例，一氧化物-氮化物-氧化物堆疊係以一次操作製造於叢集工具內，用以在該氧化物-氮化物-氧化物堆疊各層間保留一原始界面。在一特定實施例中，該叢集工具係一單晶圓叢集工具。Therefore, a method of manufacturing a non-volatile charge trapping memory element has been disclosed. According to an embodiment of the invention, a substrate is subjected to a first base oxidation process in a first process chamber of a cluster tool to form a first dielectric layer. A charge trap layer can then be deposited over the first dielectric layer in a second process chamber of the cluster tool. In one embodiment, the charge trap layer is then subjected to a second base oxidation process in the first process chamber of the cluster tool to form a second dielectric layer over the charge trap layer. By forming all of the oxide-nitride-oxide (ONO) stacks in a cluster tool, the interface damage between the layers can be reduced. Thus, in accordance with an embodiment of the invention, an oxide-nitride-oxide stack is fabricated in a cluster tool in a single operation to maintain an original interface between the oxide-nitride-oxide stack layers. In a particular embodiment, the cluster tool is a single wafer cluster tool.
600‧‧‧基板600‧‧‧Substrate
602‧‧‧第一介電層602‧‧‧First dielectric layer
604‧‧‧電荷捕獲層604‧‧‧ Charge trapping layer
606‧‧‧第二介電層606‧‧‧Second dielectric layer
608‧‧‧閘極層608‧‧‧ gate layer
610‧‧‧介電間隔側壁610‧‧‧Dielectric spacer sidewall
612‧‧‧源極和汲極區域612‧‧‧Source and bungee regions
614‧‧‧通道區域614‧‧‧Channel area
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/539,458US8940645B2 (en) | 2007-05-25 | 2012-07-01 | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
| Publication Number | Publication Date |
|---|---|
| TW201419419A TW201419419A (en) | 2014-05-16 |
| TWI594327Btrue TWI594327B (en) | 2017-08-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106121057ATWI709174B (en) | 2012-07-01 | 2013-07-01 | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
| TW102123447ATWI594327B (en) | 2012-07-01 | 2013-07-01 | Base oxidation method for fabricating non-volatile charge trapping memory elements |
| Application Number | Title | Priority Date | Filing Date |
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| TW106121057ATWI709174B (en) | 2012-07-01 | 2013-07-01 | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
| Country | Link |
|---|---|
| KR (2) | KR102146640B1 (en) |
| CN (2) | CN104781916A (en) |
| TW (2) | TWI709174B (en) |
| WO (1) | WO2014008161A1 (en) |
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