本發明是有關於一種半導體元件及其製造方法，且特別是有關於一種薄膜電晶體及其製造方法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a thin film transistor and a method of fabricating the same.
顯示面板包括畫素陣列基板、對向基板以及設置於對向基板與畫素陣列基板之間的顯示介質。畫素陣列基板包括多條掃描線、多條資料線、多個薄膜電晶體以及與薄膜電晶體電性連接的多個畫素電極。薄膜電晶體包括閘極、覆蓋閘極的閘絕緣層、配置於閘絕緣層上方的半導體圖案以及分別與半導體圖案二側電性連接的源極與汲極。為了防止在形成源極、汲極的過程中半導體圖案受損，薄膜電晶體更可包括設置在源極與半導體圖案之間和汲極與半導體圖案之間的蝕刻阻擋層。The display panel includes a pixel array substrate, a counter substrate, and a display medium disposed between the opposite substrate and the pixel array substrate. The pixel array substrate includes a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes electrically connected to the thin film transistors. The thin film transistor includes a gate, a gate insulating layer covering the gate, a semiconductor pattern disposed above the gate insulating layer, and a source and a drain electrically connected to the two sides of the semiconductor pattern, respectively. In order to prevent damage to the semiconductor pattern during formation of the source and drain, the thin film transistor may further include an etch barrier disposed between the source and the semiconductor pattern and between the drain and the semiconductor pattern.
當顯示面板的面積變大時，資料線與掃描線的長度也隨之變長。資料線與掃描線的長度變長時，資料線與掃描線的阻值也跟著變大，而不利於顯示面板的驅動。此時，製造者需將資料線與掃描線的厚度加大，以補償因其長度變長而增加的阻值。一般而言，薄膜電晶體的閘極與掃描線是屬於同一膜層。換言之，薄膜電晶體的閘極與掃描線是一起製作的。因此，當掃描線的厚度加大時，閘極也跟著加大。為了良好地覆蓋閘極，閘絕緣層的厚度也需加大。然而，隨著閘絕緣層的厚度增加，閘極與半導體圖案之間的距離也變大，而不利於閘極控制在半導體圖案中傳遞的電流。更進一步地說，若閘極對所述電流的控制能力不佳，當源極與汲極之間的電壓差改變時，薄膜電晶體的起始電壓也會隨之產生偏移過大的問題。When the area of the display panel becomes larger, the lengths of the data lines and the scanning lines also become longer. When the lengths of the data lines and the scan lines become longer, the resistance values of the data lines and the scan lines also become larger, which is disadvantageous for the driving of the display panel. At this point, the manufacturer needs to increase the thickness of the data line and the scan line to compensate for the increased resistance due to its length becoming longer. In general, the gate of the thin film transistor and the scan line belong to the same film layer. In other words, the gate of the thin film transistor is fabricated together with the scan line. Therefore, as the thickness of the scanning line is increased, the gate is also increased. In order to cover the gate well, the thickness of the gate insulating layer also needs to be increased. However, as the thickness of the gate insulating layer increases, the distance between the gate and the semiconductor pattern also becomes large, which is disadvantageous for the gate to control the current transferred in the semiconductor pattern. Furthermore, if the gate has poor control of the current, when the voltage difference between the source and the drain changes, the initial voltage of the thin film transistor also has a problem of excessive offset.
本發明提供一種薄膜電晶體，其性能佳。The present invention provides a thin film transistor which has excellent performance.
本發明提供一種薄膜電晶體的製造方法，其可製造出性能佳的薄膜電晶體。The present invention provides a method of producing a thin film transistor which can produce a thin film transistor having excellent properties.
本發明的薄膜電晶體，包括閘極、絕緣層、第一半導體圖案、第二半導體圖案、蝕刻阻擋圖案源極以及汲極。絕緣層覆蓋閘極。第一半導體圖案配置於絕緣層上。第一半導體圖案具有通道區、第一源極區以及第一汲極區。第一源極區與第一汲極區分別位於通道區的相對二側。第二半導體圖案配置於第一半導體圖案上。第二半導體圖案具有分別與通道區、第一源極區、第一汲極區重疊的抑制區、第二源極區以及第二汲極區。蝕刻阻擋圖案配置於第二半導體圖案上。源極與汲極覆蓋部份的蝕刻阻擋圖案。源極與第一半導體圖案的第一源極區以及第二半導體圖案的第二源極區電性連接。汲極與第一半導體圖案的第一汲極區以及第二半導體圖案的第二汲極區電性連接。通道區的阻值為R1。抑制區的阻值為R2。第二源極區的阻值及第二汲極區的阻值為R3。第一源極區的阻值及第一汲極區的阻值為R4。R2＞R1＞R3≧R4。The thin film transistor of the present invention comprises a gate, an insulating layer, a first semiconductor pattern, a second semiconductor pattern, an etch stop pattern source, and a drain. The insulating layer covers the gate. The first semiconductor pattern is disposed on the insulating layer. The first semiconductor pattern has a channel region, a first source region, and a first drain region. The first source region and the first drain region are respectively located on opposite sides of the channel region. The second semiconductor pattern is disposed on the first semiconductor pattern. The second semiconductor pattern has a suppression region, a second source region, and a second drain region, respectively overlapping the channel region, the first source region, and the first drain region. The etch barrier pattern is disposed on the second semiconductor pattern. An etch stop pattern of the source and drain cap portions. The source is electrically connected to the first source region of the first semiconductor pattern and the second source region of the second semiconductor pattern. The drain is electrically connected to the first drain region of the first semiconductor pattern and the second drain region of the second semiconductor pattern. The resistance of the channel area is R1. The resistance of the suppression zone is R2. The resistance of the second source region and the resistance of the second drain region are R3. The resistance of the first source region and the resistance of the first drain region are R4. R2>R1>R3≧R4.
本發明的薄膜電晶體的製造方法，包括下列步驟：在基板上形成閘極；在基板上形成絕緣層，以覆蓋閘極；在絕緣層上依序形成第一半導體層以及第二半導體層，其中第二半導體層的阻值大於第一半導體層的阻值；圖案化第一半導體層及第二半導體層，以形成第一半導體圖案及第二半導體圖案，其中第一半導體圖案具有通道區以及分別位於通道區相對二側的第一源極預定區與第一汲極預定區，第二半導體圖案具有分別與通道區、第一源極預定區、第一汲極預定區重疊的抑制區、第二源極預定區與第二汲極預定區。於第二半導體圖案上形成蝕刻阻擋圖案，蝕刻阻擋圖案與第二半導體圖案的抑制區以及第一半導體圖案的通道區重疊且暴露出第二半導體圖案的第二源極預定區以及第二汲極預定區；以蝕刻阻擋圖案為罩幕，對第一半導體圖案的第一源極預定區及第一汲極預定區和第二半導體圖案的第二源極預定區及第二汲極預定區進行局部改質處理程序，以降低第一源極預定區、第一汲極預定區、第二源極預定區以及第二汲極預定區的阻值，而使第一源極預定區、第一汲極預定區、第二源極預定區以及第二汲極預定區分別轉變為第一源極區、第一汲極區、第二源極區以及第二汲極區，其中通道區的阻值為R1，抑制區的阻值為R2，第二源極區的阻值以及第二汲極區的阻值為R3，第一源極區的阻值以及第一汲極區的阻值為R4，而R2＞R1＞R3≧R4；以及形成源極與汲極，其中源極與第一半導體圖案的第一源極區以及第二半導體圖案的第二源極區電性連接，而汲極與第一半導體圖案的第一汲極區以及第二半導體圖案的第二汲極區電性連接。The method for manufacturing a thin film transistor of the present invention comprises the steps of: forming a gate on a substrate; forming an insulating layer on the substrate to cover the gate; and sequentially forming the first semiconductor layer and the second semiconductor layer on the insulating layer, Wherein the resistance of the second semiconductor layer is greater than the resistance of the first semiconductor layer; patterning the first semiconductor layer and the second semiconductor layer to form a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern has a channel region and a first source predetermined region and a first drain predetermined region respectively located on opposite sides of the channel region, and the second semiconductor pattern has a suppression region overlapping the channel region, the first source predetermined region, and the first drain predetermined region, respectively The second source predetermined area and the second drain predetermined area. Forming an etch barrier pattern on the second semiconductor pattern, the etch barrier pattern overlapping the suppression region of the second semiconductor pattern and the channel region of the first semiconductor pattern and exposing the second source predetermined region and the second drain of the second semiconductor pattern a predetermined area; the etch barrier pattern is used as a mask, and the first source predetermined region and the first drain predetermined region of the first semiconductor pattern and the second source predetermined region and the second drain predetermined region of the second semiconductor pattern are performed a local upgrading process to reduce the resistance values of the first source predetermined region, the first drain predetermined region, the second source predetermined region, and the second drain predetermined region, and the first source predetermined region, the first The drain predetermined region, the second source predetermined region, and the second drain predetermined region are respectively converted into a first source region, a first drain region, a second source region, and a second drain region, wherein the channel region is blocked The value is R1, the resistance of the suppression region is R2, the resistance of the second source region and the resistance of the second drain region are R3, the resistance of the first source region and the resistance of the first drain region. R4, and R2>R1>R3≧R4; and forming a source and a drain, wherein The source is electrically connected to the first source region of the first semiconductor pattern and the second source region of the second semiconductor pattern, and the drain is opposite to the first drain region of the first semiconductor pattern and the second semiconductor pattern The bungee area is electrically connected.
在本發明的一實施例中，上述的第一半導體圖案較第二半導體圖案靠近閘極。In an embodiment of the invention, the first semiconductor pattern is closer to the gate than the second semiconductor pattern.
在本發明的一實施例中，R3＞R4。In an embodiment of the invention, R3 > R4.
在本發明的一實施例中，上述的第一半導體圖案的通道區與第二半導體圖案的抑制區切齊，第一半導體圖案的第一源極區與第二半導體圖案的第二源極區切齊，而第一半導體圖案的第一汲極區與第二半導體圖案的第二汲極區切齊。In an embodiment of the invention, the channel region of the first semiconductor pattern is aligned with the suppression region of the second semiconductor pattern, the first source region of the first semiconductor pattern and the second source region of the second semiconductor pattern. The first drain region of the first semiconductor pattern is aligned with the second drain region of the second semiconductor pattern.
在本發明的一實施例中，上述的蝕刻阻擋圖案暴露出第一半導體圖案的外緣以及第二半導體圖案的外緣，且源極與汲極覆蓋第一半導體圖案的外緣以及第二半導體圖案的外緣。In an embodiment of the invention, the etch barrier pattern exposes an outer edge of the first semiconductor pattern and an outer edge of the second semiconductor pattern, and the source and the drain cover the outer edge of the first semiconductor pattern and the second semiconductor The outer edge of the pattern.
在本發明的一實施例中，上述的蝕刻阻擋圖案具有分別暴露出第二源極區與第二汲極區的多個貫孔。源極以及汲極填入所述多個貫孔而分別與第二半導體圖案的第二源極區以及第二汲極區電性連接。In an embodiment of the invention, the etch barrier pattern has a plurality of through holes exposing the second source region and the second drain region, respectively. The source and the drain are filled in the plurality of through holes and electrically connected to the second source region and the second drain region of the second semiconductor pattern, respectively.
在本發明的一實施例中，是在形成閘極之後，依序形成上述的第一半導體層以及第二半導體層。In an embodiment of the invention, the first semiconductor layer and the second semiconductor layer are sequentially formed after the gate is formed.
基於上述，利用『R2＞R1＞R3≧R4』的技術特徵下，當施加適當電壓於閘極時，電流大致上會在靠近閘極的第一源極區、第一汲極區以及通道區中傳遞，而不易在遠離閘極的抑制區中傳遞。藉此，閘極對電流的控制能力可提升，而不易發生習知技術中起始電壓偏移過大的問題。Based on the above, with the technical feature of "R2>R1>R3≧R4", when an appropriate voltage is applied to the gate, the current will be substantially near the first source region, the first drain region, and the channel region of the gate. Passed in, not easily transmitted in the suppression zone away from the gate. Thereby, the gate's ability to control the current can be improved, and the problem of excessive starting voltage shift in the prior art is less prone to occur.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1E為本發明一實施例之薄膜電晶體製造方法的剖面示意圖。請參照圖1A，首先，提供基板110。基板110可為剛性基板或可撓性基板。舉例而言，剛性基板的材質可為厚玻璃或其它可適用的材料，可撓性基板的材質可為薄玻璃、聚醯亞胺（Polyimide；PI）、聚萘二甲酸乙二醇酯（Polyethylene Naphthalate；PEN）、聚乙烯對苯二甲酸酯（polyethylene terephthalate；PET）、聚醚碸（Polyethersulfone；PES）、薄金屬、或其它可適用的材料，但本發明不以此為限。1A to 1E are schematic cross-sectional views showing a method of manufacturing a thin film transistor according to an embodiment of the present invention. Referring to FIG. 1A, first, a substrate 110 is provided. The substrate 110 can be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may be thick glass or other applicable materials, and the material of the flexible substrate may be thin glass, polyimide (PI), polyethylene naphthalate (Polyethylene). Naphthalate; PEN), polyethylene terephthalate (PET), polyethersulfone (PES), thin metal, or other applicable materials, but the invention is not limited thereto.
請參照圖1A，接著，在基板110上形成閘極G。在本實施例中，閘極G例如為金屬材料，但本發明不限於此，在其他實施例中，閘極G也可以使用其他導電材料（例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層）。然後，在基板110上形成絕緣層120，以覆蓋閘極G與部份基板110。絕緣層120的材料可為無機材料（例如：氧化矽、氮化矽、氮氧化矽、或上述至少二種材料的堆疊層）、有機材料或上述之組合。Referring to FIG. 1A, a gate G is formed on the substrate 110. In the present embodiment, the gate G is, for example, a metal material, but the invention is not limited thereto. In other embodiments, the gate G may also use other conductive materials (for example, alloys, nitrides of metal materials, metal materials). An oxide, a nitrogen oxide of a metal material, or a stacked layer of a metal material and other conductive materials). Then, an insulating layer 120 is formed on the substrate 110 to cover the gate G and the portion of the substrate 110. The material of the insulating layer 120 may be an inorganic material (for example, tantalum oxide, tantalum nitride, niobium oxynitride, or a stacked layer of at least two materials described above), an organic material, or a combination thereof.
請參照圖1A，接著，在絕緣層120上依序形成第一半導體層130以及第二半導體層140。第二半導體層140覆蓋第一半導體層130。第二半導體層140的阻值大於第一半導體層130的阻值。在本實施例中，可使用相同的材料透過氣相沉積法形成阻值不同的第一半導體層130與第二半導體層140。詳言之，在沉積第一半導體層130的過程中，可通入高比例的氬氣（Ar）與低比例的氧氣（O2），以形成阻值小的第一半導體層130；在沉積第二半導體層140的過程中，可通入低比例的氬氣與高比例的氧氣，以形成阻值大的第二半導體層140。然而，本發明不限於此，在其他實施例中，也可用其他適當方法，形成阻值小的第一半導體層130與阻值大的第二半導體層140。Referring to FIG. 1A, next, the first semiconductor layer 130 and the second semiconductor layer 140 are sequentially formed on the insulating layer 120. The second semiconductor layer 140 covers the first semiconductor layer 130. The resistance of the second semiconductor layer 140 is greater than the resistance of the first semiconductor layer 130. In the present embodiment, the first semiconductor layer 130 and the second semiconductor layer 140 having different resistance values can be formed by vapor deposition using the same material. In detail, in the process of depositing the first semiconductor layer 130, a high proportion of argon (Ar) and a low proportion of oxygen (O2 ) may be introduced to form the first semiconductor layer 130 having a small resistance; During the second semiconductor layer 140, a low proportion of argon gas and a high proportion of oxygen may be introduced to form the second semiconductor layer 140 having a large resistance. However, the present invention is not limited thereto. In other embodiments, the first semiconductor layer 130 having a small resistance and the second semiconductor layer 140 having a large resistance may be formed by other suitable methods.
在本實施例中，第一、二半導體層130、140的材料可選用金屬氧化物半導體材料，例如：銦鎵鋅氧化物（Indium-Gallium-Zinc Oxide；IGZO）、銦鋅氧化物（Indium-Zinc Oxide；IZO）、鎵鋅氧化物（Gallium-Zinc Oxide；GZO）、鋅錫氧化物（Zinc-Tin Oxide；ZTO）、銦錫氧化物（Indium-Tin Oxide；ITO）或其他適合的金屬氧化物半導體材料。然而，本發明不限於此，在其他實施例中，第一、二半導體層130、140也可選用含矽半導體材料（例如：非晶矽、多晶矽、微晶矽或單晶矽等）或其他種類的半導體材料。在其他實施例中，若選用含矽半導體材料做為第一、二半導體層130、140的材料，阻值小的第一半導體層130可為輕摻雜（light doped）半導體材料，而阻值大的第二半導體層140可為本質（或稱為本徵）半導體材料，但本發明不以此為限。In this embodiment, the materials of the first and second semiconductor layers 130 and 140 may be selected from metal oxide semiconductor materials, such as: Indium-Gallium-Zinc Oxide (IGZO), Indium-Zinc Oxide (Indium- Zinc Oxide; IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO), Indium-Tin Oxide (ITO) or other suitable metal oxides Semiconductor materials. However, the present invention is not limited thereto. In other embodiments, the first and second semiconductor layers 130 and 140 may also be made of a germanium-containing semiconductor material (for example, amorphous germanium, polycrystalline germanium, microcrystalline germanium or single crystal germanium) or the like. A variety of semiconductor materials. In other embodiments, if the germanium-containing semiconductor material is selected as the material of the first and second semiconductor layers 130 and 140, the first semiconductor layer 130 having a small resistance may be a light doped semiconductor material and the resistance value. The large second semiconductor layer 140 may be an intrinsic (or intrinsic) semiconductor material, but the invention is not limited thereto.
請參照圖1A及圖1B，接著，圖案化第一半導體層130及第二半導體層140，以形成相堆疊的第一半導體圖案132與第二半導體圖案142。在本實施例中，可選擇性地利用同一光罩同時圖案化第一半導體層130與第二半導體層140，以形成相重合的第一半導體圖案132與第二半導體圖案142。然而，本發明不限於此，在其他實施例中，也可分別地圖案化第一半導體層130與第二半導體層140，以形成相堆疊的第一半導體圖案132與第二半導體圖案142。如圖1B所示，第一半導體圖案132具有通道區132a以及分別位於通道區132a相對二側的第一源極預定區132b與第一汲極預定區132c。第二半導體圖案142具有分別與通道區132a、第一源極預定區132b、第一汲極預定區132c重疊的抑制區142a、第二源極預定區142b與第二汲極預定區142c。在本實施例中，通道區132a、第一源極預定區132b及第一汲極預定區132c可分別與抑制區142a、第二源極預定區142b及第二汲極預定區142c切齊，但本發明不以此為限。Referring to FIGS. 1A and 1B , the first semiconductor layer 130 and the second semiconductor layer 140 are patterned to form a first semiconductor pattern 132 and a second semiconductor pattern 142 that are stacked. In this embodiment, the first semiconductor layer 130 and the second semiconductor layer 140 may be simultaneously patterned by using the same mask to form the first semiconductor pattern 132 and the second semiconductor pattern 142 that are coincident. However, the present invention is not limited thereto. In other embodiments, the first semiconductor layer 130 and the second semiconductor layer 140 may also be separately patterned to form the first semiconductor pattern 132 and the second semiconductor pattern 142 that are stacked. As shown in FIG. 1B, the first semiconductor pattern 132 has a channel region 132a and a first source predetermined region 132b and a first drain predetermined region 132c respectively located on opposite sides of the channel region 132a. The second semiconductor pattern 142 has a suppression region 142a, a second source predetermined region 142b, and a second drain predetermined region 142c that overlap with the channel region 132a, the first source predetermined region 132b, and the first drain predetermined region 132c, respectively. In this embodiment, the channel region 132a, the first source predetermined region 132b, and the first drain predetermined region 132c may be aligned with the suppression region 142a, the second source predetermined region 142b, and the second drain predetermined region 142c, respectively. However, the invention is not limited thereto.
請參照圖1C及圖1D，接著，降低第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b以及第二汲極預定區142c（標示於圖1C）的阻值，以使第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b以及第二汲極預定區142c分別轉變為第一源極區132b’、第一汲極區132c’、第二源極區142b’以及第二汲極區142c’（標示於圖1D）。Referring to FIG. 1C and FIG. 1D, subsequently, the resistance of the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c (shown in FIG. 1C) is lowered. a value such that the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c are converted into the first source region 132b' and the first drain A region 132c', a second source region 142b', and a second drain region 142c' (shown in Figure 1D).
詳言之，請參照圖1C，在本實施例中，可先形成蝕刻阻擋層（未繪示），以覆蓋第一半導體圖案132、第二半導體圖案142以及被第一、二半導體圖案132、142露出的部份絕緣層120；然後，於所述蝕刻阻擋層上形成與抑制區142a重疊且不與第二源極預定區142b、第二汲極預定區142c重疊的光阻圖案PR；之後，以光阻圖案PR為罩幕，圖案化所述蝕刻阻擋層，以形成蝕刻阻擋圖案150。蝕刻阻擋圖案150與第二半導體圖案142的抑制區142a以及第一半導體圖案132的通道區132a重疊且暴露出第二半導體圖案142的第二源極預定區142b以及第二汲極預定區142c。In detail, referring to FIG. 1C, in the embodiment, an etch barrier layer (not shown) may be formed to cover the first semiconductor pattern 132, the second semiconductor pattern 142, and the first and second semiconductor patterns 132, 142 a portion of the exposed insulating layer 120; then, a photoresist pattern PR overlapping the suppression region 142a and not overlapping the second source predetermined region 142b and the second drain predetermined region 142c is formed on the etch barrier layer; The etch stop layer is patterned with the photoresist pattern PR as a mask to form an etch barrier pattern 150. The etch barrier pattern 150 overlaps the suppression region 142a of the second semiconductor pattern 142 and the channel region 132a of the first semiconductor pattern 132 and exposes the second source predetermined region 142b and the second drain predetermined region 142c of the second semiconductor pattern 142.
請參照圖1D，接著，以蝕刻阻擋圖案150為罩幕，對第一半導體圖案132的第一源極預定區132b及第一汲極預定區132c和第二半導體圖案142的第二源極預定區142b及第二汲極預定區142c（標示於圖1C）進行局部改質處理程序，以降低第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b以及第二汲極預定區142c的阻值。藉此，第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b及第二汲極預定區142c分別轉變為第一源極區132b’、第一汲極區132c’、第二源極區142b’及第二汲極區142c’。在本實施例中，通道區132a與抑制區142a可切齊（matched），第一源極區132b’與第二源極區142b’可切齊，而第一汲極區132c’與第二汲極區142c’可切齊，但本發明不以此為限。Referring to FIG. 1D, next, the first source predetermined region 132b and the first drain predetermined region 132c and the second source of the second semiconductor pattern 142 of the first semiconductor pattern 132 are predetermined by using the etch barrier pattern 150 as a mask. The region 142b and the second drain predetermined region 142c (shown in FIG. 1C) perform a partial modification process to reduce the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the first The resistance of the second drain predetermined area 142c. Thereby, the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c are respectively converted into the first source region 132b' and the first drain region. 132c', second source region 142b' and second drain region 142c'. In this embodiment, the channel region 132a and the suppression region 142a may be matched, the first source region 132b' and the second source region 142b' may be aligned, and the first drain region 132c' and the second The bungee region 142c' can be aligned, but the invention is not limited thereto.
在本實施例中，上述局部改質處理程序可以是『在通入氣體的情況下開啟電漿』的步驟。舉例而言，當第一、二半導體層130、140的材料為金屬氧化物半導體材料時，可通入氨氣（NH3）或氫氣（H2）以及惰性氣體進行電漿處理程序。所述電漿處理程序有助於讓第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b及第二汲極預定區142c暴露在缺氧的環境下，進而降低第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b及第二汲極預定區142c的阻值。在其他實施例中，若第一半導體層130以及第二半導體層140為含矽半導體材料（例如：非晶矽、多晶矽、微晶矽或單晶矽等），則可以蝕刻阻擋圖案150為罩幕，對第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b及第二汲極預定區142c進行離子佈植（ion implantation）工序，以使其分別轉變為阻值較低的第一源極區132b’、第一汲極區132c’、第二源極區142b’與第二汲極區142c’。In the embodiment, the partial modification process may be a step of "opening the plasma in the case of introducing a gas". For example, when the material of the first and second semiconductor layers 130, 140 is a metal oxide semiconductor material, a plasma treatment process may be performed by introducing ammonia gas (NH3 ) or hydrogen gas (H2 ) and an inert gas. The plasma processing program helps expose the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c to an oxygen-deficient environment, thereby further The resistance values of the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c are lowered. In other embodiments, if the first semiconductor layer 130 and the second semiconductor layer 140 are germanium-containing semiconductor materials (eg, amorphous germanium, polycrystalline germanium, microcrystalline germanium, or single crystal germanium, etc.), the barrier pattern 150 may be etched into a mask. The screen performs an ion implantation process on the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c to convert them into The first source region 132b' having a lower resistance, the first drain region 132c', the second source region 142b' and the second drain region 142c'.
需說明的是，本發明之局部改質處理程序並不限制一定要開啟電漿。在其他實施例中，也可用其他方法降低第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b及第二汲極預定區142c的阻值。舉例而言，當第一、二半導體層130、140的材料為金屬氧化物半導體材料時，可通入氨氣（NH3）以及氫氣（H2）而不開啟電漿，藉此，也可降低第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b及第二汲極預定區142c的阻值。It should be noted that the partial modification process of the present invention does not limit the necessity to turn on the plasma. In other embodiments, the resistance values of the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c may also be reduced by other methods. For example, when the material of the first and second semiconductor layers 130, 140 is a metal oxide semiconductor material, ammonia gas (NH3 ) and hydrogen gas (H2 ) can be introduced without turning on the plasma, thereby also The resistance values of the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c are lowered.
值得注意的是，經過上述降低阻值的動作後，通道區132a的阻值R1，抑制區142a的阻值R2、第二源極區142b’的阻值R3、第二汲極區142c’的阻值R3、第一源極區132b’的阻值R4以及第一汲極區132c’阻值為R4滿足：R2＞R1＞R3≧R4。It should be noted that after the above-mentioned action of reducing the resistance, the resistance value R1 of the channel region 132a, the resistance value R2 of the suppression region 142a, the resistance value R3 of the second source region 142b', and the second drain region 142c' The resistance value R3, the resistance value R4 of the first source region 132b', and the resistance value of the first drain region 132c' are R4 satisfying: R2>R1>R3≧R4.
詳言之，在上述降低阻值的過程中，由於通道區132a及抑制區142a受到蝕刻阻擋圖案150的遮蔽，因此，通道區132a的阻值及抑制區142a的阻值大致上維持不變，而抑制區142a的阻值R2及通道區132a的阻值分別與阻值大的第二半導體層140及阻值小的第一半導體層130相同。換言之，抑制區142a的阻值R2大於通道區132a的阻值R1（即R2＞R1）。另一方面，在上述降低阻值的過程中，第二源極預定區142b及第二汲極預定區142c未受到蝕刻阻擋圖案150的遮蔽，因此，第二源極區142b’的阻值R3以及第二汲極區142c’阻值R3會小於抑制區142a的阻值R2（即R2＞R3）。類似地，在上述降低阻值的過程中，由於第一源極預定區132b及第一汲極預定區132c未受到蝕刻阻擋圖案150的遮蔽，因此，第一源極區132b’的阻值R4以及第一汲極區132c’阻值R4會小於通道區132a的阻值R1（即R1＞R4）。此外，由於第二源極預定區142b及第二汲極預定區142c的阻值大於第一源極預定區132b及第一汲極預定區132c的阻值，且在上述降低阻值的過程中，第一源極預定區132b及第一汲極預定區132c分別被第二源極預定區142b及第二汲極預定區142c遮蔽，因此第二源極區142b’的阻值R3以及第二汲極區142c’阻值R3會大於或等於第一源極區132b’的阻值R4以及第一汲極區132c’阻值R4（即R3≧R4）。In detail, in the process of lowering the resistance, since the channel region 132a and the suppression region 142a are shielded by the etch barrier pattern 150, the resistance of the channel region 132a and the resistance of the suppression region 142a remain substantially unchanged. The resistance R2 of the suppression region 142a and the resistance of the channel region 132a are the same as those of the second semiconductor layer 140 having a large resistance and the first semiconductor layer 130 having a small resistance. In other words, the resistance R2 of the suppression region 142a is greater than the resistance R1 of the channel region 132a (ie, R2 > R1). On the other hand, in the above process of lowering the resistance, the second source predetermined region 142b and the second drain predetermined region 142c are not shielded by the etch barrier pattern 150, and therefore, the resistance value R3 of the second source region 142b' And the resistance value R3 of the second drain region 142c' is smaller than the resistance R2 of the suppression region 142a (ie, R2>R3). Similarly, in the above process of lowering the resistance, since the first source predetermined region 132b and the first drain predetermined region 132c are not shielded by the etch barrier pattern 150, the resistance value R4 of the first source region 132b' is And the resistance value R4 of the first drain region 132c' is smaller than the resistance R1 of the channel region 132a (ie, R1>R4). In addition, since the resistance values of the second source predetermined region 142b and the second drain predetermined region 142c are greater than the resistance values of the first source predetermined region 132b and the first drain predetermined region 132c, and in the process of lowering the resistance The first source predetermined region 132b and the first drain predetermined region 132c are respectively shielded by the second source predetermined region 142b and the second drain predetermined region 142c, and thus the resistance value R3 of the second source region 142b' and the second The resistance value R3 of the drain region 142c' is greater than or equal to the resistance R4 of the first source region 132b' and the resistance R4 of the first drain region 132c' (ie, R3≧R4).
綜合上述四式（即R2＞R1；R2＞R3；R1＞R4；R3≧R4）可知，R2＞R1＞R4及R2＞R3≧R4。本發明所述技術領域具有通常知識者能夠調控上述局部改質處理程序的製程參數（例如：製程溫度、製程時間及/或電漿成份等），而使第二源極區142b’的阻值R3以及第二汲極區142c’阻值R3小於通道區132a的阻值R1（即R1＞R3），進而使通道區132a的阻值R1，抑制區142a的阻值R2、第二源極區142b’的阻值R3、第二汲極區142c’阻值R3、第一源極區132b’的阻值R4以及第一汲極區132c’阻值為R4滿足：R2＞R1＞R3≧R4。Combining the above four formulas (ie, R2>R1; R2>R3; R1>R4; R3≧R4), it is known that R2>R1>R4 and R2>R3≧R4. The technical field of the present invention has a process parameter (for example, process temperature, process time, and/or plasma composition, etc.) that can be adjusted by the general knowledge to control the partial modification process, and the resistance of the second source region 142b' is made. R3 and the second drain region 142c' resistance R3 are smaller than the resistance value R1 of the channel region 132a (ie, R1>R3), thereby making the resistance value R1 of the channel region 132a, the resistance value R2 of the suppression region 142a, and the second source region. The resistance R3 of the 142b', the resistance R3 of the second drain region 142c', the resistance R4 of the first source region 132b', and the resistance of the first drain region 132c' are R4: R2>R1>R3≧R4 .
請參照圖1D及圖1E，接著，可選擇性地去除光阻圖案PR。然後，在蝕刻阻擋圖案150以及第二半導體圖案142上形成源極S與汲極D。源極S與第一半導體圖案132的第一源極區132b’以及第二半導體圖案142的第二源極區142b’電性連接。汲極D與第一半導體圖案132的第一汲極區132c’以及第二半導體圖案142的第二汲極區142c’電性連接。基於導電性考量，在本實施例中，源極S與汲極D通常使用金屬材料製作，然而，本發明不限於此，在其他實施例中，源極S、汲極D也可使用其他導電材質（例如：合金、金屬氮化物、金屬氧化物、金屬氮氧化物或其他適合的材料）或金屬材料與其他導電材料的堆疊層製作。於此，便完成了本實施例的薄膜電晶體TFT。Referring to FIG. 1D and FIG. 1E, the photoresist pattern PR may be selectively removed. Then, a source S and a drain D are formed on the etching stopper pattern 150 and the second semiconductor pattern 142. The source S is electrically connected to the first source region 132b' of the first semiconductor pattern 132 and the second source region 142b' of the second semiconductor pattern 142. The drain D is electrically connected to the first drain region 132c' of the first semiconductor pattern 132 and the second drain region 142c' of the second semiconductor pattern 142. In the present embodiment, the source S and the drain D are usually made of a metal material. However, the present invention is not limited thereto. In other embodiments, the source S and the drain D may also use other conductive materials. Materials (eg alloys, metal nitrides, metal oxides, metal oxynitrides or other suitable materials) or metal materials are fabricated with stacked layers of other conductive materials. Here, the thin film transistor TFT of the present embodiment is completed.
請參照圖1E，薄膜電晶體TFT包括閘極G、絕緣層120、第一半導體圖案132、第二半導體圖案142、蝕刻阻擋圖案150、源極S與汲極D。閘極G配置於基板110上。絕緣層120覆蓋閘極G與部份基板110。第一半導體圖案132配置於絕緣層120上且與閘極G重疊。第一半導體圖案132具有通道區132a以及分別位於通道區132a相對二側的第一源極區132b’與第一汲極區132c’。第二半導體圖案142配置於第一半導體圖案132上且與閘極G重疊。第一半導體圖案132比第二半導體圖案142靠近閘極G。第二半導體圖案142具有分別與通道區132a、第一源極區132b’、第一汲極區132c’重疊的抑制區142a、第二源極區142b’以及第二汲極區142c’。Referring to FIG. 1E, the thin film transistor TFT includes a gate G, an insulating layer 120, a first semiconductor pattern 132, a second semiconductor pattern 142, an etch barrier pattern 150, a source S, and a drain D. The gate G is disposed on the substrate 110. The insulating layer 120 covers the gate G and a portion of the substrate 110. The first semiconductor pattern 132 is disposed on the insulating layer 120 and overlaps the gate G. The first semiconductor pattern 132 has a channel region 132a and a first source region 132b' and a first drain region 132c' respectively located on opposite sides of the channel region 132a. The second semiconductor pattern 142 is disposed on the first semiconductor pattern 132 and overlaps the gate G. The first semiconductor pattern 132 is closer to the gate G than the second semiconductor pattern 142. The second semiconductor pattern 142 has a suppression region 142a, a second source region 142b', and a second drain region 142c' respectively overlapping the channel region 132a, the first source region 132b', and the first drain region 132c'.
蝕刻阻擋圖案150配置於第二半導體圖案142的抑制區142a上且暴露出第二半導體圖案142的第二源極區142b’以及第二汲極區142c’。源極S以及汲極D覆蓋部份的蝕刻阻擋圖案150。源極S與第一半導體圖案132的第一源極區132b’以及第二半導體圖案142的第二源極區142b’電性連接。汲極D與第一半導體圖案132的第一汲極區132c’以及第二半導體圖案142的第二汲極區142c’電性連接。在本實施例中，蝕刻阻擋圖案150暴露出第一半導體圖案132的外緣132d以及第二半導體圖案142的外緣142d。源極S與汲極D彼此分離且分別覆蓋蝕刻阻擋圖案150的相對二外緣150a。源極S與汲極D更覆蓋第一半導體圖案132的外緣132d以及第二半導體圖案142的外緣142d。然而，本發明不限於此，在其他實施例中，蝕刻阻擋圖案也可呈其他態樣，以下將於後續段落中舉例說明。The etch barrier pattern 150 is disposed on the suppression region 142a of the second semiconductor pattern 142 and exposes the second source region 142b' and the second drain region 142c' of the second semiconductor pattern 142. The source S and the drain D cover a portion of the etch barrier pattern 150. The source S is electrically connected to the first source region 132b' of the first semiconductor pattern 132 and the second source region 142b' of the second semiconductor pattern 142. The drain D is electrically connected to the first drain region 132c' of the first semiconductor pattern 132 and the second drain region 142c' of the second semiconductor pattern 142. In the present embodiment, the etch barrier pattern 150 exposes the outer edge 132d of the first semiconductor pattern 132 and the outer edge 142d of the second semiconductor pattern 142. The source S and the drain D are separated from each other and cover the opposite outer edges 150a of the etch barrier pattern 150, respectively. The source S and the drain D cover the outer edge 132d of the first semiconductor pattern 132 and the outer edge 142d of the second semiconductor pattern 142. However, the present invention is not limited thereto, and in other embodiments, the etch barrier pattern may also be in other aspects, as will be exemplified in the following paragraphs.
值得注意的是，通道區132a的阻值為R1，抑制區142a的阻值為R2，第二源極區142b’的阻值以及第二汲極區142c’的阻值為R3，第一源極區132b’的阻值以及第一汲極區132c’的阻值為R4，而R2＞R1＞R3≧R4。通道區132a的阻值R1、抑制區142a的阻值R2，第二源極區142b’的阻值R3、第二汲極區142c’的阻值R3，第一源極區132b’的阻值R4以及第一汲極區132c’的阻值R4均大於源極S的阻值與汲極D的阻值。利用『R2＞R1＞R3≧R4』的技術特徵下，當施加適當電壓於閘極G時，電流大致上會沿著路徑I1、I2傳遞，而不易在阻值大的抑制區142a（也就距離閘極G較遠處）中傳遞。藉此，閘極G對在電流的控制能力佳，而不易發生習知技術中起始電壓偏移過大的問題。It should be noted that the resistance of the channel region 132a is R1, the resistance of the suppression region 142a is R2, the resistance of the second source region 142b', and the resistance of the second drain region 142c' are R3, the first source. The resistance of the polar region 132b' and the resistance of the first drain region 132c' are R4, and R2 > R1 > R3 ≧ R4. The resistance value R1 of the channel region 132a, the resistance value R2 of the suppression region 142a, the resistance value R3 of the second source region 142b', the resistance value R3 of the second drain region 142c', and the resistance value of the first source region 132b' The resistance R4 of R4 and the first drain region 132c' is greater than the resistance of the source S and the resistance of the drain D. With the technical feature of "R2>R1>R3≧R4", when an appropriate voltage is applied to the gate G, the current is substantially transmitted along the paths I1 and I2, and it is not easy to be in the suppression region 142a having a large resistance value. Passed in the distance from the gate G). Thereby, the gate G has a good ability to control the current, and is less prone to the problem that the initial voltage offset is too large in the prior art.
更進一步地說，在R2＞R1＞R3＝R4的條件下，當施加適當電壓於閘極G時，電流大致上會沿著路徑I2傳遞，也就是說，電流大致上會依序通過源極S、第二源極區142b’、第一源極區132b’、通道區132a、第一汲極區132c’、第二汲極區142c’與汲極D。在R2＞R1＞R3＞R4的條件下，當施加適當電壓於閘極G時，電流大致上會沿著路徑I1傳遞，也就是說，電流大致上會依序通過源極S、第一源極區132b’、通道區132a、第一汲極區132c’與汲極D。比較路徑I1、I2可知，當R2＞R1＞R3＞R4時（即電流在路徑I1中傳遞時），有更高的比例的電流傳遞路徑中是貼近閘極G，而在路徑I1中傳遞的電流更容易受到閘極G的控制。換言之，若令R2＞R1＞R3＞R4，則薄膜電晶體TFT的起始電壓偏移的問題可獲得更為顯著的改善。Furthermore, under the condition of R2>R1>R3=R4, when an appropriate voltage is applied to the gate G, the current is substantially transmitted along the path I2, that is, the current substantially passes through the source in sequence. S, a second source region 142b', a first source region 132b', a channel region 132a, a first drain region 132c', a second drain region 142c', and a drain D. Under the condition of R2>R1>R3>R4, when an appropriate voltage is applied to the gate G, the current is substantially transmitted along the path I1, that is, the current substantially passes through the source S and the first source in sequence. Polar region 132b', channel region 132a, first drain region 132c' and drain D. Comparing the paths I1 and I2, it can be seen that when R2>R1>R3>R4 (that is, when the current is transmitted in the path I1), a higher proportion of the current transfer path is closer to the gate G and transmitted in the path I1. The current is more susceptible to the control of the gate G. In other words, if R2 > R1 > R3 > R4, the problem of the initial voltage shift of the thin film transistor TFT can be more significantly improved.
圖2A至圖2E為本發明另一實施例之薄膜電晶體製造方法的剖面示意圖。圖2A至圖2E的薄膜電晶體製造方法與圖1A至圖1E的薄膜電晶體製造方法類似，因此相同或相對應的元件，以相同或相對應的標號表示。圖2A至圖2E的薄膜電晶體製造方法與圖1A至圖1E的薄膜電晶體製造方法的主要差異在於：二者之蝕刻阻擋圖案150、150A的型態不同。以下主要就此差異處做說明，二者相同處還請依照圖2A至圖2E中的標號參照前述說明，於此便不再重述。2A to 2E are schematic cross-sectional views showing a method of fabricating a thin film transistor according to another embodiment of the present invention. 2A to 2E are similar to the thin film transistor manufacturing method of Figs. 1A to 1E, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. The main difference between the thin film transistor manufacturing method of FIGS. 2A to 2E and the thin film transistor manufacturing method of FIGS. 1A to 1E is that the etching barrier patterns 150 and 150A of the two are different in type. In the following, the difference is mainly explained. If the two are the same, please refer to the above description in accordance with the reference numerals in FIG. 2A to FIG. 2E, and the description will not be repeated here.
請參照圖2A，首先，提供基板110。接著，在基板110上形成閘極G。然後，在基板110上形成絕緣層120，以覆蓋閘極G與部份基板110。接著，在絕緣層120上依序形成第一半導體層130以及第二半導體層140。第二半導體層140覆蓋第一半導體層130。第二半導體層140的阻值大於第一半導體層130的阻值。請參照圖2A及圖2B，接著，圖案化第一半導體層130及第二半導體層140，以形成相堆疊的第一半導體圖案132與第二半導體圖案142。第一半導體圖案132具有通道區132a以及分別位於通道區132a相對二側的第一源極預定區132b與第一汲極預定區132c。第二半導體圖案142具有分別與通道區132a、第一源極預定區132b、第一汲極預定區132c重疊的抑制區142a、第二源極預定區142b與第二汲極預定區142c。Referring to FIG. 2A, first, a substrate 110 is provided. Next, a gate G is formed on the substrate 110. Then, an insulating layer 120 is formed on the substrate 110 to cover the gate G and the portion of the substrate 110. Next, the first semiconductor layer 130 and the second semiconductor layer 140 are sequentially formed on the insulating layer 120. The second semiconductor layer 140 covers the first semiconductor layer 130. The resistance of the second semiconductor layer 140 is greater than the resistance of the first semiconductor layer 130. Referring to FIGS. 2A and 2B , the first semiconductor layer 130 and the second semiconductor layer 140 are patterned to form a first semiconductor pattern 132 and a second semiconductor pattern 142 that are stacked. The first semiconductor pattern 132 has a channel region 132a and a first source predetermined region 132b and a first drain predetermined region 132c respectively located on opposite sides of the channel region 132a. The second semiconductor pattern 142 has a suppression region 142a, a second source predetermined region 142b, and a second drain predetermined region 142c that overlap with the channel region 132a, the first source predetermined region 132b, and the first drain predetermined region 132c, respectively.
請參照圖2C及圖2D，接著，降低第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b以及第二汲極預定區142c（標示於圖2C）的阻值，以使第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b以及第二汲極預定區142c分別轉變為第一源極區132b’、第一汲極區132c’、第二源極區142b’以及第二汲極區142c’（標示於圖2D）。Referring to FIG. 2C and FIG. 2D, subsequently, the resistance of the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c (shown in FIG. 2C) is lowered. a value such that the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c are converted into the first source region 132b' and the first drain A region 132c', a second source region 142b', and a second drain region 142c' (shown in Figure 2D).
詳言之，請參照圖2C，在本實施例中，可先形成蝕刻阻擋層（未繪示），以覆蓋第一半導體圖案132、第二半導體圖案142以及被第一、二半導體圖案132、142露出的部份絕緣層120；然後，於所述蝕刻阻擋層上形成與抑制區142a重疊且不與第二源極預定區142b、第二汲極預定區142c重疊的光阻圖案PR；之後，以光阻圖案PR為罩幕，圖案化所述蝕刻阻擋層，以形成蝕刻阻擋圖案150。蝕刻阻擋圖案150A與第二半導體圖案142的抑制區142a以及第一半導體圖案132的通道區132a重疊且暴露出第二半導體圖案142的第二源極預定區142b以及第二汲極預定區142c。與圖1A至圖1E的蝕刻阻擋圖案150不同的是，蝕刻阻擋圖案150A具有分別暴露出第二源極區142b’與第二汲極區142c’的二貫孔150b。蝕刻阻擋圖案150A除了覆蓋通道區132a與抑制區142a外，蝕刻阻擋圖案150A更覆蓋第一半導體圖案132的外緣（或說側壁）132d以及第二半導體圖案142的外緣（或說側壁）142d。In detail, referring to FIG. 2C, in the embodiment, an etch barrier layer (not shown) may be formed to cover the first semiconductor pattern 132, the second semiconductor pattern 142, and the first and second semiconductor patterns 132, 142 a portion of the exposed insulating layer 120; then, a photoresist pattern PR overlapping the suppression region 142a and not overlapping the second source predetermined region 142b and the second drain predetermined region 142c is formed on the etch barrier layer; The etch stop layer is patterned with the photoresist pattern PR as a mask to form an etch barrier pattern 150. The etch barrier pattern 150A overlaps the suppression region 142a of the second semiconductor pattern 142 and the channel region 132a of the first semiconductor pattern 132 and exposes the second source predetermined region 142b and the second drain predetermined region 142c of the second semiconductor pattern 142. Unlike the etch barrier pattern 150 of FIGS. 1A through 1E, the etch barrier pattern 150A has two through holes 150b exposing the second source region 142b' and the second drain region 142c', respectively. The etching stopper pattern 150A covers the outer edge (or sidewall) 132d of the first semiconductor pattern 132 and the outer edge (or sidewall) 142d of the second semiconductor pattern 142 except for the channel region 132a and the suppression region 142a. .
請參照圖2D，接著，以蝕刻阻擋圖案150A為罩幕，對第一半導體圖案132的第一源極預定區132b及第一汲極預定區132c和第二半導體圖案142的第二源極預定區142b及第二汲極預定區142c （標示於圖2C）進行局部改質處理程序，以降低第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b以及第二汲極預定區142c的阻值。藉此，將第一源極預定區132b、第一汲極預定區132c、第二源極預定區142b及第二汲極預定區142c分別轉變為第一源極區132b’、第一汲極區132c’、第二源極區142b’及第二汲極區142c’。Referring to FIG. 2D, next, the first source predetermined region 132b and the first drain predetermined region 132c and the second source of the second semiconductor pattern 142 of the first semiconductor pattern 132 are predetermined by using the etch barrier pattern 150A as a mask. The region 142b and the second drain predetermined region 142c (shown in FIG. 2C) perform a partial modification process to reduce the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the first The resistance of the second drain predetermined area 142c. Thereby, the first source predetermined region 132b, the first drain predetermined region 132c, the second source predetermined region 142b, and the second drain predetermined region 142c are respectively converted into the first source region 132b' and the first drain A region 132c', a second source region 142b', and a second drain region 142c'.
請參照圖2D及圖2E，接著，可選擇性地去除光阻圖案PR。然後，在蝕刻阻擋圖案150A以及第二半導體圖案142上形成源極S與汲極D。源極S與第一半導體圖案132的第一源極區132b’以及第二半導體圖案142的第二源極區142b’電性連接。詳言之，在本實施例中，第一半導體圖案132的第一源極區132b’與第二半導體圖案142的第二源極區142b’電性接觸，源極S填入蝕刻阻擋圖案150A的貫孔150b而與第二半導體圖案142的第二源極區142b’電性接觸。汲極D與第一半導體圖案132的第一汲極區132c’以及第二半導體圖案142的第二汲極區142c’電性連接。詳言之，在本實施例中，第一半導體圖案132的第一汲極區132c’與第二半導體圖案142的第二汲極區142c’電性接觸，汲極D填入蝕刻阻擋圖案150A的貫孔150b而與第二半導體圖案142的第二汲極區142c’電性接觸。Referring to FIG. 2D and FIG. 2E, the photoresist pattern PR may be selectively removed. Then, a source S and a drain D are formed on the etching stopper pattern 150A and the second semiconductor pattern 142. The source S is electrically connected to the first source region 132b' of the first semiconductor pattern 132 and the second source region 142b' of the second semiconductor pattern 142. In detail, in the embodiment, the first source region 132b' of the first semiconductor pattern 132 is in electrical contact with the second source region 142b' of the second semiconductor pattern 142, and the source S is filled with the etch barrier pattern 150A. The through hole 150b is in electrical contact with the second source region 142b' of the second semiconductor pattern 142. The drain D is electrically connected to the first drain region 132c' of the first semiconductor pattern 132 and the second drain region 142c' of the second semiconductor pattern 142. In detail, in the embodiment, the first drain region 132c' of the first semiconductor pattern 132 is in electrical contact with the second drain region 142c' of the second semiconductor pattern 142, and the drain D is filled with the etch barrier pattern 150A. The through hole 150b is in electrical contact with the second drain region 142c' of the second semiconductor pattern 142.
請參照圖2E，薄膜電晶體TFT’包括閘極G、絕緣層120、第一半導體圖案132、第二半導體圖案142、蝕刻阻擋圖案150A、源極S與汲極D。閘極G配置於基板110上。絕緣層120覆蓋閘極G與部份基板110。第一半導體圖案132配置於絕緣層120上且與閘極G重疊。第一半導體圖案132具有通道區132a以及分別位於通道區132a相對二側的第一源極區132b’與第一汲極區132c’。第二半導體圖案142配置於第一半導體圖案132上且與閘極G重疊。第一半導體圖案132比第二半導體圖案142靠近閘極G。第二半導體圖案142具有分別與通道區132a、第一源極區132b’、第一汲極區132c’重疊的抑制區142a、第二源極區142b’以及第二汲極區142c’。蝕刻阻擋圖案150A配置於第二半導體圖案142的抑制區142a上且暴露出第二半導體圖案142的第二源極區142b’以及第二汲極區142c’。源極S以及汲極D覆蓋部份的蝕刻阻擋圖案150A。源極S與第一半導體圖案132的第一源極區132b’以及第二半導體圖案142的第二源極區142b’電性連接。汲極D與第一半導體圖案132的第一汲極區132c’以及第二半導體圖案142的第二汲極區142c’電性連接。薄膜電晶體TFT’具有與薄膜電晶體TFT類似的功效與優點，於此便不再重述。Referring to FIG. 2E, the thin film transistor TFT' includes a gate G, an insulating layer 120, a first semiconductor pattern 132, a second semiconductor pattern 142, an etch barrier pattern 150A, a source S, and a drain D. The gate G is disposed on the substrate 110. The insulating layer 120 covers the gate G and a portion of the substrate 110. The first semiconductor pattern 132 is disposed on the insulating layer 120 and overlaps the gate G. The first semiconductor pattern 132 has a channel region 132a and a first source region 132b' and a first drain region 132c' respectively located on opposite sides of the channel region 132a. The second semiconductor pattern 142 is disposed on the first semiconductor pattern 132 and overlaps the gate G. The first semiconductor pattern 132 is closer to the gate G than the second semiconductor pattern 142. The second semiconductor pattern 142 has a suppression region 142a, a second source region 142b', and a second drain region 142c' respectively overlapping the channel region 132a, the first source region 132b', and the first drain region 132c'. The etch barrier pattern 150A is disposed on the suppression region 142a of the second semiconductor pattern 142 and exposes the second source region 142b' and the second drain region 142c' of the second semiconductor pattern 142. The source S and the drain D cover a portion of the etch barrier pattern 150A. The source S is electrically connected to the first source region 132b' of the first semiconductor pattern 132 and the second source region 142b' of the second semiconductor pattern 142. The drain D is electrically connected to the first drain region 132c' of the first semiconductor pattern 132 and the second drain region 142c' of the second semiconductor pattern 142. The thin film transistor TFT' has similar effects and advantages as the thin film transistor TFT, and will not be repeated here.
綜上所述，本發明一實施例的薄膜電晶體包括閘極、位於閘極上方的第一、二半導體圖案、與第一半導體圖案的第一源極區和第二半導體圖案的第二源極區電性連接的源極以及與第一半導體圖案的第一汲極區和第二半導體圖案的第二汲極區電性連接的汲極。第一半導體圖案具有通道區、第一源極區以及第一汲極區。第二半導體圖案具有分別與第一半導體圖案的通道區、第一源極區、第一汲極區重疊的抑制區、第二源極區以及第二汲極區。通道區的阻值為R1，抑制區的阻值為R2，第二源極區的阻值為R3、第二汲極區的阻值為R3，第一源極區的阻值為R4，第一汲極區的阻值為R4，而R2＞R1＞R3≧R4。利用『R2＞R1＞R3≧R4』的技術特徵下，當施加適當電壓於閘極時，電流大致上會在靠近閘極的第一源極區、第一汲極區與通道區中傳遞，而不易在遠離閘極的抑制區中傳遞。藉此，閘極對電流的控制能力可提升，而不易發生習知技術中起始電壓偏移過大的問題。In summary, the thin film transistor of one embodiment of the present invention includes a gate, first and second semiconductor patterns above the gate, and a first source region of the first semiconductor pattern and a second source of the second semiconductor pattern a source electrically connected to the pole region and a drain electrically connected to the first drain region of the first semiconductor pattern and the second drain region of the second semiconductor pattern. The first semiconductor pattern has a channel region, a first source region, and a first drain region. The second semiconductor pattern has a suppression region, a second source region, and a second drain region respectively overlapping the channel region of the first semiconductor pattern, the first source region, and the first drain region. The resistance of the channel region is R1, the resistance of the suppression region is R2, the resistance of the second source region is R3, the resistance of the second drain region is R3, and the resistance of the first source region is R4, The resistance of a drain region is R4, and R2>R1>R3≧R4. With the technical feature of "R2>R1>R3≧R4", when an appropriate voltage is applied to the gate, the current is substantially transmitted in the first source region, the first drain region, and the channel region near the gate. It is not easy to pass in the suppression zone away from the gate. Thereby, the gate's ability to control the current can be improved, and the problem of excessive starting voltage shift in the prior art is less prone to occur.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
110‧‧‧基板
120‧‧‧絕緣層
130‧‧‧第一半導體層
132‧‧‧第一半導體圖案
132a‧‧‧通道區
132b‧‧‧第一源極預定區
132b’‧‧‧第一源極區
132c‧‧‧第一汲極預定區
132c’‧‧‧第一汲極區
132d‧‧‧外緣
140‧‧‧第二半導體層
142‧‧‧第二半導體圖案
142a‧‧‧抑制區
142b‧‧‧第二源極預定區
142b’‧‧‧第二源極區
142c‧‧‧第二汲極預定區
142c’‧‧‧第二汲極區
142d‧‧‧外緣
150、150A‧‧‧蝕刻阻擋圖案110‧‧‧Substrate
120‧‧‧Insulation
130‧‧‧First semiconductor layer
132‧‧‧First semiconductor pattern
132a‧‧‧Channel area
132b‧‧‧First source reservation area
132b'‧‧‧First source area
132c‧‧‧First bungee booking area
132c'‧‧‧First bungee area
132d‧‧‧ outer edge
140‧‧‧Second semiconductor layer
142‧‧‧Second semiconductor pattern
142a‧‧‧Suppressed area
142b‧‧‧Second source reservation area
142b'‧‧‧Second source area
142c‧‧‧Second bungee booking area
142c'‧‧‧Second bungee area
142d‧‧‧ outer edge
150, 150A‧‧‧etch barrier pattern
150a‧‧‧外緣150a‧‧‧ outer edge
150b‧‧‧貫孔150b‧‧‧through hole
D‧‧‧汲極D‧‧‧汲
G‧‧‧閘極G‧‧‧ gate
I1、I2‧‧‧路徑I1, I2‧‧‧ path
PR‧‧‧光阻圖案PR‧‧‧resist pattern
S‧‧‧源極S‧‧‧ source
TFT、TFT’‧‧‧薄膜電晶體TFT, TFT'‧‧‧thin film transistor
圖1A至圖1E為本發明一實施例之薄膜電晶體製造方法的剖面示意圖。 圖2A至圖2E為本發明另一實施例之薄膜電晶體製造方法的剖面示意圖。1A to 1E are schematic cross-sectional views showing a method of manufacturing a thin film transistor according to an embodiment of the present invention. 2A to 2E are schematic cross-sectional views showing a method of fabricating a thin film transistor according to another embodiment of the present invention.
110‧‧‧基板110‧‧‧Substrate
120‧‧‧絕緣層120‧‧‧Insulation
132‧‧‧第一半導體圖案132‧‧‧First semiconductor pattern
132a‧‧‧通道區132a‧‧‧Channel area
132b’‧‧‧第一源極區132b’‧‧‧First source area
132c’‧‧‧第一汲極區132c’‧‧‧ First bungee area
132d‧‧‧外緣132d‧‧‧ outer edge
142‧‧‧第二半導體圖案142‧‧‧Second semiconductor pattern
142a‧‧‧抑制區142a‧‧‧Suppressed area
142b’‧‧‧第二源極區142b’‧‧‧Second source area
142c’‧‧‧第二汲極區142c’‧‧‧Second bungee
142d‧‧‧外緣142d‧‧‧ outer edge
150‧‧‧蝕刻阻擋圖案150‧‧‧etch barrier pattern
150a‧‧‧外緣150a‧‧‧ outer edge
D‧‧‧汲極D‧‧‧汲
G‧‧‧閘極G‧‧‧ gate
I1、I2‧‧‧路徑I1, I2‧‧‧ path
S‧‧‧源極S‧‧‧ source
TFT‧‧‧薄膜電晶體TFT‧‧‧thin film transistor
| Application Number | Priority Date | Filing Date | Title |
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| TW104133965ATWI567871B (en) | 2015-10-16 | 2015-10-16 | Thin film transistor and method of manufacturing same |
| CN201610010130.2ACN105428423B (en) | 2015-10-16 | 2016-01-07 | Thin film transistor and method of manufacturing the same |
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| TW104133965ATWI567871B (en) | 2015-10-16 | 2015-10-16 | Thin film transistor and method of manufacturing same |
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| TW201715650A TW201715650A (en) | 2017-05-01 |
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| TW104133965ATWI567871B (en) | 2015-10-16 | 2015-10-16 | Thin film transistor and method of manufacturing same |
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