本發明有關一種發光二極體陣列結構，尤指一種於晶粒覆晶(flip chip)或晶圓級覆晶貼合過程中無需精密對位的發光二極體陣列結構。The present invention relates to a light emitting diode array structure, and more particularly to a light emitting diode array structure that does not require precise alignment during a flip chip or wafer level flip chip bonding process.
隨著實施需求不斷的提高，遂有廠商提供了發光二極體陣列結構就如美國專利公告第US 6,547,249號專利案所揭，該專利案揭露了一種形成於高電阻性基板上之發光裝置之陣列，該陣列提出了一種實施方案，其包含有一第一發光裝置、一第二發光裝置，區隔該第一發光裝置及該第二發光裝置的一溝渠或一離子植入區域，以及一連接該第一發光裝置與該第二發光裝置的第一內連線。由此可知，該專利案是利用該第一內連線來完成該第一發光裝置與該第二發光裝置的連接，然而該第一內連線是在該陣列研製過程中，將鋁、銅、金或其他合金經沉積工法所製得，而該沉積工法的增加，變相地增加了該陣列的研製程序，亦令良率出現不確定性。As the implementation requirements continue to increase, the manufacturer has provided a light-emitting diode array structure as disclosed in U.S. Patent No. 6,547,249, which discloses a light-emitting device formed on a high-resistance substrate. Array, the array provides an embodiment, comprising a first illuminating device, a second illuminating device, a trench or an ion implantation region separating the first illuminating device and the second illuminating device, and a connection a first interconnect of the first illuminating device and the second illuminating device. It can be seen that the patent uses the first interconnect to complete the connection between the first illuminating device and the second illuminating device. However, the first interconnecting wire is aluminum and copper during the development of the array. Gold, or other alloys are produced by the deposition method, and the increase in the deposition method increases the development procedure of the array in disguise, and the yield is uncertain.
再者，現有發光二極體結構的封裝主要有二，其一為打線(Wire bonding)技法，其二則為覆晶(Flip chip)技法。以打線技法進行做說明，打線技法是將晶片置放基板上，再經打線令晶片與封裝基板上之連結點連接，而覆晶技法則是於晶粒的連接位置生成凸塊(Bump)，再將晶片翻轉，令凸塊面對與基板，作直接連結。換言之，以覆晶技法實施的封裝結構需於封裝過程中，將晶粒上的電極與基板上的電路圖案進行精密對位，才可產生電性連接。Furthermore, there are two main packages of the existing LED structure, one of which is a wire bonding technique, and the other of which is a Flip chip technique. According to the wire-laying technique, the wire-laying technique is to place the wafer on the substrate, and then connect the wafer to the connection point on the package substrate by wire bonding, and the flip chip technique generates a bump at the connection position of the die. The wafer is then flipped so that the bumps face the substrate and are directly connected. In other words, the package structure implemented by the flip chip technique needs to precisely align the electrodes on the die with the circuit pattern on the substrate during the packaging process to produce an electrical connection.
除此之外，現有發光二極體結構的晶片金屬貼合方式主要有二，其一為整面金屬貼合技法，其二為晶圓級的覆晶貼合技法。其中，整面金屬貼合技法是將晶片的金屬層與基板的金屬層相互貼合，而晶圓級的覆晶貼合技法則是在晶片上長凸塊金屬，於後再將晶片翻轉，令凸塊金屬面對一成長基板上的電路圖案，作直接連接，此後再將該成長基板去除後，進行晶粒製作。換言之，以晶圓級的覆晶貼合技法實施，於貼合過程中同樣需令欲覆晶的凸塊金屬與該成長基板上的圖案金屬進行對位，才可完成電性連接。In addition, there are two main types of wafer metal bonding methods for the existing light-emitting diode structure, one of which is a full-surface metal bonding technique, and the other is a wafer-level flip chip bonding technique. Among them, the whole surface metal bonding technique is to laminate the metal layer of the wafer and the metal layer of the substrate, and the wafer-level flip chip bonding technique is to form a bump metal on the wafer, and then flip the wafer. The bump metal is directly connected to the circuit pattern on the growth substrate, and then the growth substrate is removed, and then the crystal grain is formed. In other words, the wafer-level flip-chip bonding technique is performed, and in the bonding process, the bump metal to be flipped is also aligned with the pattern metal on the growth substrate to complete the electrical connection.
由上可知，現有發光二極體陣列結構需增加研製程序才可完成複數發光體之間的連接，且現有封裝技術或覆晶貼合技術，於實施過程中需進行精密對位才可續行，稍有閃失即可能產生短路，且用於精密對位的高端儀器造價昂貴，變相增加了研製成本。除此之外，習用更有令複數發光體根據電路設計依序黏合於基板上的技術方案，但此種實施方式需對每一發光體進行精確地對位，而導致該發光二極體陣列結構的研製時間拉長，不利於大量製造。It can be seen from the above that the existing LED array structure needs to be added to the development process to complete the connection between the plurality of illuminants, and the existing packaging technology or the flip chip bonding technology needs to be precisely aligned in the implementation process before continuing. A slight flash may result in a short circuit, and the high-end instruments used for precision alignment are expensive, and the disguise increases the development cost. In addition, the conventional method has a technical solution for sequentially bonding the plurality of illuminants to the substrate according to the circuit design. However, in this embodiment, each illuminant needs to be accurately aligned, resulting in the illuminating diode array. The development time of the structure is lengthened, which is not conducive to mass production.
本發明的主要目的，在於解決現有發光二極體陣列研製技法需繁瑣對位所帶來的問題。The main object of the present invention is to solve the problems caused by the cumbersome alignment of the existing LED array development techniques.
為達上述目的，本發明提供一種發光二極體陣列結構，包含有一基底以及至少二發光體。該基底包含一承載基板以及複數排列設置於該承載基板上的金屬單元，每一該金屬單元外緣的任二點界定出一端點間距。該二發光體被同步設置於該基底之上，每一該發光體包含有互為電性相異並分隔設置的一第一電極及一第二電極，每一該發光體於該第一電極與該第二電極之間界定出一電極間距，該電極間距大於該端點間距，每一該發光體的該第一電極與該第二電極分別與該些金屬單元的至少其中之一電性連接，且其中一該發光體的該第一電極與另一該發光體的該第二電極電性連接於相同的至少一該金屬單元，令二該發光體形成串聯。其中，於一實施例中，該發光體的該第一電極與另一該發光體的該第二電極之間具有一小於該端點間距的連接間距以連接於相同的至少一該金屬單元。To achieve the above object, the present invention provides a light emitting diode array structure comprising a substrate and at least two illuminants. The substrate comprises a carrier substrate and a plurality of metal units arranged on the carrier substrate, and any two points of the outer edge of the metal unit define an end point spacing. The two illuminants are synchronously disposed on the substrate, and each of the illuminants includes a first electrode and a second electrode that are electrically separated and spaced apart from each other, and each of the illuminants is disposed on the first electrode With theAn electrode spacing is defined between the second electrodes, and the electrode spacing is greater than the end point spacing. The first electrode and the second electrode of each of the illuminants are electrically connected to at least one of the metal units, respectively. And the first electrode of the illuminant and the second electrode of the other illuminant are electrically connected to the same at least one metal unit, so that the illuminants are connected in series. In one embodiment, the first electrode of the illuminator and the second electrode of the other illuminator have a connection pitch smaller than the end point spacing to connect to the same at least one metal unit.
於一實施例中，該些發光體分別為一三族氮系列(氮化鋁鎵銦)半導體發光疊層或一三族磷系列(磷化鋁鎵銦)半導體發光疊層。In one embodiment, the illuminants are respectively a tri-family nitrogen series (aluminum gallium indium nitride) semiconductor light-emitting stack or a tri-family phosphorus series (aluminum gallium phosphide) semiconductor light-emitting stack.
為達到上述目的，本發明亦提供另一實施方案，該發光二極體陣列結構包含一基底以及至少二發光體。該基底包含一承載基板以及複數排列設置於該承載基板上的金屬單元，每一該金屬單元外緣的任二點界定出一端點間距。該二發光體被同步設置於該基底之上，每一該發光體包含有互為電性相異並分隔設置的一第一電極及一第二電極，每一該發光體於該第一電極與該第二電極之間界定出一電極間距，該電極間距大於該端點間距，二該發光體的該第一電極連接於相同的至少一該金屬單元，二該發光體的該第二電極則連接於其他相同的至少一該金屬單元，令二該發光體形成並聯。其中，二該發光體的二該第一電極之間具有一小於該端點間距的連接間距以連接於相同的至少一該金屬單元，二該發光體的二該第二電極之間則具有該連接間距以連接於其他相同的至少一該金屬單元。於一實施例中，該些發光體分別為一三族氮系列(氮化鋁鎵銦)半導體發光疊層或一三族磷系列(磷化鋁鎵銦)半導體發光疊層。In order to achieve the above object, the present invention also provides another embodiment, the LED array structure comprising a substrate and at least two illuminants. The substrate comprises a carrier substrate and a plurality of metal units arranged on the carrier substrate, and any two points of the outer edge of the metal unit define an end point spacing. The two illuminants are synchronously disposed on the substrate, and each of the illuminants includes a first electrode and a second electrode that are electrically separated and spaced apart from each other, and each of the illuminants is disposed on the first electrode An electrode spacing is defined between the second electrode and the second electrode, wherein the first electrode of the illuminant is connected to the same at least one metal unit, and the second electrode of the illuminant Then connected to at least one of the same at least one metal unit, so that the illuminants are formed in parallel. Wherein the two first electrodes of the illuminator have a connection pitch smaller than the end point spacing to connect to the same at least one metal unit, and the second illuminant has the second electrode The connection pitch is connected to other identical at least one of the metal units. In one embodiment, the illuminants are respectively a tri-family nitrogen series (aluminum gallium indium nitride) semiconductor light-emitting stack or a tri-family phosphorus series (aluminum gallium phosphide) semiconductor light-emitting stack.
為達到上述目的，本發明亦提供另一實施方案，該發光二極體陣列結構包含一基座以及複數發光體。該基底包含一承載基板以及複數排列設置於該承載基板上的金屬單元，每一該金屬單元外緣的任二點界定出一端點間距。該些發光體被同步設置於該基底之上並形成矩陣，每一該發光體包含有互為電性相異並分隔設置的一第一電極及一第二電極，每一該發光體於該第一電極與該第二電極之間界定出一電極間距，該電極間距大於該端點間距，該些發光體依序連接形成串聯電路，該些發光體被設定為電性連接關係的該第一電極與該第二電極之間具有一小於該端點間距的連接間距，而該些發光體被設定為電性隔離關係的該第一電極或該第二電極之間具有一大於該端點間距的隔離間距。In order to achieve the above object, the present invention also provides another embodiment, the LED array structure comprising a pedestal and a plurality of illuminants. The substrate comprises a carrier substrate and a plurality of arraysA metal unit disposed on the carrier substrate, and any two points of the outer edge of the metal unit define an end point spacing. The illuminants are synchronously disposed on the substrate and form a matrix, and each of the illuminants includes a first electrode and a second electrode which are electrically separated from each other and are disposed apart from each other. An electrode spacing is defined between the first electrode and the second electrode, and the electrode spacing is greater than the end point spacing. The illuminants are sequentially connected to form a series circuit, and the illuminants are set to be electrically connected. An electrode and the second electrode have a connection pitch smaller than the distance between the end points, and the illuminants are set to be electrically isolated to have a greater than the end between the first electrode or the second electrode The separation spacing of the spacing.
於一實施例中，該些發光體分別為一三族氮系列(氮化鋁鎵銦)半導體發光疊層或一三族磷系列(磷化鋁鎵銦)半導體發光疊層。In one embodiment, the illuminants are respectively a tri-family nitrogen series (aluminum gallium indium nitride) semiconductor light-emitting stack or a tri-family phosphorus series (aluminum gallium phosphide) semiconductor light-emitting stack.
為達到上述目的，本發明亦提供另一實施方案，該發光二極體陣列結構包含一基底及複數發光體。該基底包含一承載基板以及複數排列設置於該承載基板上的金屬單元，每一該金屬單元外緣的任二點界定出一端點間距。該複數發光體被同步設置於該基底之上並形成矩陣，每一該發光體包含有互為電性相異並分隔設置的一第一電極及一第二電極，每一該發光體於該第一電極與該第二電極之間界定出一電極間距，該電極間距大於該端點間距，該些發光體組成並聯電路，該並聯電路包含至少二並聯分支，該二並聯分支中的該些發光體被設定為電性連接關係的該第一電極或該第二電極之間具有一小於該端點間距的連接間距，該二並聯分支被設定為電性隔離關係的該第一電極或該第二電極之間具有一大於該端點間距的隔離間距，每一該並聯分支中被設定為電性連接關係的該第一電極與該第二電極之間具有該連接間距。In order to achieve the above object, the present invention also provides another embodiment, the LED array structure comprising a substrate and a plurality of illuminants. The substrate comprises a carrier substrate and a plurality of metal units arranged on the carrier substrate, and any two points of the outer edge of the metal unit define an end point spacing. The plurality of illuminants are synchronously disposed on the substrate and form a matrix, and each of the illuminators includes a first electrode and a second electrode which are electrically separated from each other and are disposed apart from each other. An electrode spacing is defined between the first electrode and the second electrode, the electrode spacing is greater than the end point spacing, and the illuminants comprise a parallel circuit, the parallel circuit comprising at least two parallel branches, and the two parallel branches The first electrode or the second electrode of the illuminant is electrically connected to have a connection pitch smaller than the distance between the end points, and the two parallel branches are set to be electrically connected to the first electrode or the first electrode The second electrodes have an isolation gap greater than the spacing of the end points, and the connection distance between the first electrode and the second electrode in each of the parallel branches is set to be electrically connected.
於一實施例中，該些發光體分別為一三族氮系列(氮化鋁鎵銦)半導體發光疊層或一三族磷系列(磷化鋁鎵銦)半導體發光疊層。In one embodiment, the illuminants are respectively a tri-family nitrogen series (aluminum gallium indium nitride) semiconductor light-emitting stack or a tri-family phosphorus series (aluminum gallium phosphide) semiconductor light-emitting stack.
透過上述技術方案，相較於習用具有以下特點：本發明相較於習用將複數發光體根據電路設計依序設置於基板上的實施方式，本發明以佈設於該基底上的該些金屬單元取代了習用需先於基板上形成出的串聯電路或並聯電路。本發明令該些發光體同步設置於該基板之上，並根據欲形成電路中的電性連接關係或電性隔離關係，令該些發光體的該第一電極或該第二電極以該連接間距或該隔離間距設置於該些金屬單元，如此一來，即可以透過一次性的黏合設置達到串聯或並聯電路，簡化作業程序，降低該發光二極體陣列結構的研製成本。Through the above technical solution, the present invention has the following features: the present invention replaces the embodiments in which the plurality of illuminants are sequentially disposed on the substrate according to the circuit design, and the present invention replaces the metal units disposed on the substrate. It is customary to use a series circuit or a parallel circuit formed on the substrate. The illuminating body is disposed on the substrate synchronously, and the first electrode or the second electrode of the illuminants is connected by the electrical connection relationship or the electrical isolation relationship in the circuit to be formed. The pitch or the isolation pitch is set on the metal units, so that the series or parallel circuit can be realized through the one-time bonding arrangement, the operation procedure is simplified, and the development cost of the LED array structure is reduced.
1‧‧‧基底1‧‧‧Base
11‧‧‧承載基板11‧‧‧Carrier substrate
12‧‧‧金屬單元12‧‧‧Metal units
121‧‧‧端點間距121‧‧‧End point spacing
122‧‧‧分隔間距122‧‧‧ Separation spacing
13‧‧‧第一端子13‧‧‧First terminal
14‧‧‧第二端子14‧‧‧second terminal
15‧‧‧第一連接通道15‧‧‧First connection channel
16‧‧‧第二連接通道16‧‧‧Second connection channel
2‧‧‧發光體(第一發光體)2‧‧‧Lights (first illuminator)
21‧‧‧第一電性半導體層21‧‧‧First electrical semiconductor layer
22‧‧‧活性層22‧‧‧Active layer
23‧‧‧第二電性半導體層23‧‧‧Second electrical semiconductor layer
24‧‧‧第一電極24‧‧‧First electrode
25‧‧‧第二電極25‧‧‧second electrode
26‧‧‧電極間距26‧‧‧electrode spacing
27‧‧‧連接間距27‧‧‧ Connection spacing
28‧‧‧隔離間距28‧‧‧Isolation spacing
3‧‧‧第二發光體3‧‧‧second illuminant
34‧‧‧第一電極34‧‧‧First electrode
35‧‧‧第二電極35‧‧‧second electrode
4‧‧‧第三發光體4‧‧‧3rd illuminant
44‧‧‧第一電極44‧‧‧First electrode
45‧‧‧第二電極45‧‧‧second electrode
5‧‧‧第四發光體5‧‧‧fourth illuminant
54‧‧‧第一電極54‧‧‧First electrode
55‧‧‧第二電極55‧‧‧second electrode
61、62‧‧‧並聯分支61, 62‧‧‧ parallel branches
圖1，本發明一實施例的結構剖面示意圖。Figure 1 is a cross-sectional view showing the structure of an embodiment of the present invention.
圖2，本發明陣列結構第一實施例的仰視示意圖。Figure 2 is a bottom plan view of a first embodiment of the array structure of the present invention.
圖3，本發明陣列結構第二實施例的仰視示意圖。Figure 3 is a bottom plan view of a second embodiment of the array structure of the present invention.
圖4，本發明陣列結構第三實施例的仰視示意圖。Figure 4 is a bottom plan view of a third embodiment of the array structure of the present invention.
圖5，本發明陣列結構第四實施例的仰視示意圖。Figure 5 is a bottom plan view of a fourth embodiment of the array structure of the present invention.
有關本發明的詳細說明及技術內容，現就配合圖式說明如下：本發明提供一種發光二極體陣列結構，以簡化發光二極體陣列的對位需求，令該發光二極體陣列得在簡易的對位後即完成連接，大幅地改善習用作業程序，降低發光二極體陣列結構的研製成本。然，本發明該發光二極體陣列結構得以串聯或並聯或串並聯組合的型態實施，於此為能具體說明本案技術，本案以同一技術概念的原則，遂分多個實施方案逐一解釋。The detailed description and the technical content of the present invention are described below with reference to the following drawings: The present invention provides a light emitting diode array structure to simplify the alignment requirement of the light emitting diode array, so that the light emitting diode array is obtained. After the simple alignment, the connection is completed, the conventional operation procedure is greatly improved, and the development cost of the LED array structure is reduced. However, the LED array structure of the present invention can be implemented in series or parallel or series-parallel combination, and is an energy device.Explain the technology of this case. This case is explained one by one according to the principle of the same technical concept.
請參閱圖1及圖2，於一實施例中，本發明該發光二極體陣列結構包含有一基底1以及至少二發光體2，其中該基底1包含一承載基板11，複數排列設置於該承載基板11上的金屬單元12，一相對該些金屬單元12佈設於該承載基板11另側的第一端子13，以及一設於該承載基板11並與該第一端子13位於同側的第二端子14。進一步地，該承載基板11可由一高阻性且具較佳熱傳導係數的材質製成，所稱材質可選自由電性絕緣的矽、氮化鋁(AlN)、合成鑽石(CVD鑽石)以及高導熱陶瓷基板所組成群組的其中之一。另一方面，佈設於該承載基板11上的該些金屬單元12可分別為一金屬或合金材料製成，例如金、銀、鋁或其合金。又，該些金屬單元12得經物理或化學等處理程序排列設置於該承載基板11上，且被設定為彼此互不接觸，每一該金屬單元12之間的間距得根據實施需求作適度調整，該些金屬單元12的排列方式亦可根據實施需求作適度調整，舉例來說，於一實施例中，該些金屬單元12更可以規則陣列的方式排列設置於該承載基板11上，如圖2。然而，除上述實施方式之外，每一該金屬單元12彼此分開並交錯設置於該承載基板11，如圖2。再者，復請參閱圖2，本發明每一該金屬單元12得為一方形、一三角形、一圓形或一十字形等幾何圖形，而每一該金屬單元12外緣的任二點界定出一端點間距121，再者，本發明任二該金屬單元12之間更具有一小於該端點間距121的分隔間距122。此外，本發明該基底1進一步設有一第一連接通道15及一第二電性連接通道16，該第一連接通道15連接該第一端子13以及位置與該第一端子13相應的至少一該金屬單元12，該第二連接通道16則連接該第二端子14以及位置於該第二端子14相應的至少一該金屬單元12，該第一連接通道15與該第二連接通道16互為隔離。Referring to FIG. 1 and FIG. 2, in an embodiment, the LED array structure comprises a substrate 1 and at least two illuminators 2, wherein the substrate 1 comprises a carrier substrate 11 , and the plurality of arrays are disposed on the carrier a metal unit 12 on the substrate 11 , a first terminal 13 disposed on the other side of the carrier substrate 11 opposite to the metal unit 12 , and a second portion disposed on the carrier substrate 11 and on the same side of the first terminal 13 Terminal 14. Further, the carrier substrate 11 can be made of a material having high resistance and good thermal conductivity, and the material can be selected from the group consisting of electrically insulating bismuth, aluminum nitride (AlN), synthetic diamond (CVD diamond) and high. One of the groups of thermally conductive ceramic substrates. On the other hand, the metal units 12 disposed on the carrier substrate 11 may be made of a metal or alloy material, such as gold, silver, aluminum or alloys thereof. Moreover, the metal units 12 are arranged on the carrier substrate 11 by physical or chemical processing procedures, and are set to be in contact with each other, and the spacing between each of the metal units 12 is appropriately adjusted according to implementation requirements. The arrangement of the metal units 12 can also be adjusted according to the implementation requirements. For example, in an embodiment, the metal units 12 can be arranged on the carrier substrate 11 in a regular array manner. 2. However, in addition to the above embodiments, each of the metal units 12 is separated from each other and staggered to the carrier substrate 11, as shown in FIG. Furthermore, referring to FIG. 2, each of the metal units 12 of the present invention has a geometric shape such as a square, a triangle, a circle or a cross, and any two points of the outer edge of the metal unit 12 are defined. An end point spacing 121 is formed. Further, the second metal unit 12 of the present invention further has a separation interval 122 smaller than the end point spacing 121. In addition, the substrate 1 of the present invention further includes a first connecting channel 15 and a second electrical connecting channel 16 , the first connecting channel 15 connecting the first terminal 13 and at least one corresponding to the first terminal 13 Metal unitThe second connecting channel 16 is connected to the second terminal 14 and at least one metal unit 12 corresponding to the second terminal 14. The first connecting channel 15 and the second connecting channel 16 are isolated from each other.
復請參閱圖1，本發明該些發光體2可分別為未經切割的一晶圓中的一基本單位，或者是該晶圓經裁切後所形成的晶粒。該些發光體2結構相同，其可為一三族氮系列(氮化鋁鎵銦)半導體發光疊層或一三族磷系列(磷化鋁鎵銦)半導體發光疊層。舉例來說，每一該發光體2製成後包含依序層疊的一第一電性半導體層21，一活性層22，一第二電性半導體層23，以及互為電性相異並分隔設置的一第一電極24與一第二電極25。進一步說明，每一該發光體2於研製過程中，將部份的該第二電性半導體層23與該活性層22蝕刻移除，裸露相對應部份的該第一電性半導體層21，而該第一電極24設置於該第一電性半導體層21且形成歐姆接觸(Ohmic contact)，該第二電極25則設置於該第二電性半導體層23上並形成歐姆接觸。又，該第一電極24與該第二電極25的材質可分別一金屬或合金材料。再者，本發明每一該發光體2更於該第一電極24與該第二電極25之間界定出一電極間距26，且該電極間距26大於該端點間距121。藉此，以令每一該發光體2於佈設的過程中，該第一電極24與該第二電極25分別於該些金屬單元12的至少其中之一電性連接，換言之，該第一電極24與該第二電極25分別設置於不同的至少一該金屬單元12。Referring to FIG. 1 , the illuminators 2 of the present invention may be a basic unit in an uncut wafer, or a die formed by cutting the wafer. The illuminants 2 have the same structure, and may be a tri-family nitrogen series (aluminum gallium indium nitride) semiconductor light-emitting stack or a tri-family phosphorus series (aluminum gallium phosphide) semiconductor light-emitting stack. For example, each of the illuminants 2 is formed to include a first electrical semiconductor layer 21, an active layer 22, a second electrical semiconductor layer 23, and are electrically separated and separated from each other. A first electrode 24 and a second electrode 25 are disposed. Further, during the development of the illuminant 2, a portion of the second electrical semiconductor layer 23 and the active layer 22 are etched away to expose a corresponding portion of the first electrical semiconductor layer 21, The first electrode 24 is disposed on the first electrical semiconductor layer 21 and forms an ohmic contact. The second electrode 25 is disposed on the second electrical semiconductor layer 23 and forms an ohmic contact. Moreover, the material of the first electrode 24 and the second electrode 25 may be a metal or an alloy material, respectively. Furthermore, each of the illuminators 2 of the present invention defines an electrode spacing 26 between the first electrode 24 and the second electrode 25, and the electrode spacing 26 is greater than the end point spacing 121. In this way, the first electrode 24 and the second electrode 25 are electrically connected to at least one of the metal units 12, in other words, the first electrode. 24 and the second electrode 25 are respectively disposed on different at least one of the metal units 12.
承上，為清楚解釋本案用於串聯或並聯的實施方案，於此遂以二該發光體2進行舉例說明，但並不以所舉數量為限制。於此遂先以串聯實施方案進行說明，並請參閱圖2，於串聯實施例中，該些發光體2於作業的過程中，被同步設置於該基底1之上，而其中一該發光體2的該第一電極24與另一該發光體2的該第二電極25連接於相同的至少一該金屬單元12，而令二該發光體2形成串聯。進一步地，本發明令該發光體2的該第一電極24與另一該發光體2的該第二電極25之間具有一小於該端點間距121的連接間距27，藉此以令該發光體2的該第一電極24與另一該發光體2的該第二電極25連接於相同的至少一該金屬單元12。再者，並請參閱圖3，於並聯實施例中，二該發光體2的該第一電極24連接於相同的至少一該金屬單元12，而該發光體2的該第二電極25則連接於其他相同的至少一該金屬單元12，而令二該發光體2形成並聯。進一步地，本發明令二該發光體2的二該第一電極24之間具有小於該端點間距12的連接間距27，二該發光體2的二該第二電極25亦具有該連接間距27以連接與其他相同的至少一該金屬單元12。In order to clearly explain the embodiment of the present invention for series or parallel connection, the illuminant 2 is exemplified herein, but it is not limited by the number. Herein, a series implementation is described first, and referring to FIG. 2, in the series embodiment, the illuminants 2 are synchronously disposed on the substrate 1 during the operation, and one of the illuminants The first electrode 24 of the second electrode 25 is connected to the same at least one metal unit 12 of the other illuminant 2, andThe illuminants 2 are formed in series. Further, the present invention has a connection pitch 27 between the first electrode 24 of the illuminant 2 and the second electrode 25 of the other illuminant 2 that is smaller than the end point spacing 121, thereby enabling the illuminating The first electrode 24 of the body 2 and the second electrode 25 of the other illuminant 2 are connected to at least one of the same metal units 12. In addition, referring to FIG. 3, in the parallel embodiment, the first electrode 24 of the illuminant 2 is connected to the same at least one metal unit 12, and the second electrode 25 of the illuminant 2 is connected. The other at least one metal unit 12 is the same, and the illuminants 2 are formed in parallel. Further, the present invention has two connection intervals 27 between the first electrodes 24 of the illuminant 2 and less than the end point spacing 12, and the second electrodes 25 of the illuminant 2 also have the connection pitch 27. To connect at least one of the metal units 12 identical to the others.
除上述實施方案之外，本發明該發光二極體陣列結構更得將該些發光體2以M×N陣列的方式配置，如2×2陣列、3×2陣列等。於此為詳細說明，遂以2×2陣列進行舉例說明，但並不以此為限。請參閱圖4，於此首先說明該發光二極體陣列結構為串聯陣列的實施方式，於此實施例中，該些發光體2被同步設置於該基底1之上並形成矩陣，該些發光體2被依序連接形成一串聯電路，該些發光體2中被設定為電性連接關係的該第一電極24與該第二電極25之間具有小於該端點間距121的該連接間距27，而該些發光體2被設定為電性隔離關係的該第一電極24或該第二電極25之間具有一大於該端點間距121的隔離間距28。復請參閱圖4，為清楚說明本案技術，遂將該些發光體2定義為一第一發光體2、一第二發光體3、一第三發光體4以及一第四發光體5，其中，該第一發光體2與該第二發光體3位於同一列上，而該第三發光體4與該第二發光體3位於不同列但位於同一行上，該第四發光體5則與該第三發光體4位於同一列上。承上，於封裝的初始，該第一發光體2、該第二發光體3、該第三發光體4以及該第四發光體5被同步設置於該基底1之上，且設定該第一發光體2的該第一電極24設置於該些金屬單元12的至少其中之一，該第一發光體2的該第二電極25則設置於該些金屬單元12的其他至少其中之一，該第二發光體3的該第一電極34與該第一發光體2的該第二電極25則以該連接間距27設置於相同的至少一該金屬單元12，該第二發光體3的該第二電極35則設置於該些金屬單元12的其他至少其中之一。又，該第三發光體4的該第一電極44以該連接間距27設置於相同的至少一該金屬單元12，而該第三發光體4的該第二電極45設置於該些金屬單元12的其他至少其中之一，且由於該第三發光體4的該第二電極45與該第二發光體3的該第一電極34被設定為電性隔離關係，故令該第三發光體4的該第二電極45與該第二發光體3的該第一電極34之間具有該隔離間距28。再者，該第四發光體5的該第一電極54以該連接間距27與該第三發光體4的該第二電極45設置於相同的至少一該金屬單元12，該第四發光體5的該第二電極55則設置於該些金屬單元12的另外其中之一。然而，由於該第四發光體5與該第一發光體2被設定為電性隔離關係，故該第四發光體5的該第一電極54與該第一發光體2的該第二電極25之間具有該隔離間距28，而該第四發光體5的該第二電極55與該第一發光體2的該第一電極24之間亦具有該隔離間距28。據此，經本發明上述的佈局，即可令該第一發光體2、該第二發光體3、該第三發光體4以及該第四發光體5依序連接，而形成該串聯電路。再者，本發明為了產生該隔離間距28，進一步令每一該發光體2的該第一電極24或該第二電極25得根據距離需求進行調整，換言之該第一電極24與該第二電極25的電極大小並非一定相等，而可為相異，就如圖4所繪。In addition to the above embodiments, the light-emitting diode array structure of the present invention is configured such that the light-emitting bodies 2 are arranged in an M×N array, such as a 2×2 array, a 3×2 array, or the like. For the detailed description, 遂 is illustrated by a 2×2 array, but is not limited thereto. Referring to FIG. 4, an embodiment in which the LED array structure is a series array is first described. In this embodiment, the illuminants 2 are synchronously disposed on the substrate 1 and form a matrix. The body 2 is sequentially connected to form a series circuit, and the connection distance 27 between the first electrode 24 and the second electrode 25 in the illuminant 2 that is set to be electrically connected is less than the end point spacing 121 And the illuminants 2 are disposed in an electrically isolated relationship between the first electrode 24 or the second electrode 25 with an isolation gap 28 greater than the end point spacing 121. Referring to FIG. 4, in order to clearly illustrate the technology of the present invention, the illuminants 2 are defined as a first illuminant 2, a second illuminator 3, a third illuminant 4, and a fourth illuminant 5, wherein The first illuminant 2 and the second illuminator 3 are located in the same row, and the third illuminant 4 and the second illuminant 3 are located in different columns but on the same row, and the fourth illuminant 5 is The third illuminants 4 are located on the same column. The first illuminator 2, the second illuminator 3, the third illuminant 4, and the fourth illuminant 5 are synchronously disposed on the substrate 1 at the initial stage of the package.The first electrode 24 of the first illuminant 2 is disposed on at least one of the metal units 12, and the second electrode 25 of the first illuminant 2 is disposed on the metal unit 12 In at least one of the other, the first electrode 34 of the second illuminant 3 and the second electrode 25 of the first illuminant 2 are disposed at the same at least one metal unit 12 at the connection pitch 27, the first The second electrode 35 of the two illuminants 3 is disposed at at least one of the other of the metal units 12. The first electrode 44 of the third illuminant 4 is disposed on the same at least one metal unit 12 at the connection pitch 27, and the second electrode 45 of the third illuminant 4 is disposed on the metal unit 12 At least one of the other, and the third electrode 45 of the third illuminant 4 is electrically isolated from the first electrode 34 of the second illuminator 3, so that the third illuminant 4 is The second electrode 45 and the first electrode 34 of the second illuminant 3 have the separation gap 28. The first electrode 54 of the fourth illuminant 5 is disposed on the same at least one metal unit 12 at the connection pitch 27 and the second electrode 45 of the third illuminant 4, and the fourth illuminant 5 The second electrode 55 is disposed on the other of the metal units 12. However, since the fourth illuminator 5 and the first illuminant 2 are electrically isolated, the first electrode 54 of the fourth illuminant 5 and the second electrode 25 of the first illuminant 2 are The isolation gap 28 is provided between the second electrode 55 of the fourth illuminant 5 and the first electrode 24 of the first illuminant 2 . Accordingly, according to the above arrangement of the present invention, the first luminous body 2, the second luminous body 3, the third luminous body 4, and the fourth luminous body 5 can be sequentially connected to form the series circuit. Furthermore, in order to generate the isolation gap 28, the first electrode 24 or the second electrode 25 of each of the illuminants 2 is further adjusted according to the distance requirement, in other words, the first electrode 24 and the second electrode. The electrode sizes of 25 are not necessarily equal, but may be different, as depicted in Figure 4.
請參閱圖5，現就說明本案該發光二極體陣列結構為並聯陣列的實施方式，於此實施例中，該些發光體2被同步設置於該基底1之上並形成矩陣，且該些發光體2連接後組成一並聯電路，該並聯電路包含至少二並聯分支61、62，該二並聯分支61、62中的該些發光體2被設定為電性連接關係的該第一電極24或該第二電極25之間具有小於該端點間距121的該連接間距27，而該二並聯分支61、62中被設定為電性隔離關係的該第一電極24或該第二電極25之間具有大於該端點間距121的隔離間距28，且每一該並聯分支61、62中被設定為電性連接關係的該第一電極24與該第二電極25之間具有該連接間距27。然，為了清楚說明本案技術，於此遂以前揭該第一發光體2、該第二發光體3、該第三發光體4以及該第四發光體5進行說明，該第一發光體2與該第二發光體3位於同一列上，而該第三發光體4與該第一發光體2位於不同列但位於同一行上，該第四發光體5則與該第三發光體4位於同一列上，且定義該第一發光體2與該第二發光體3屬於同一該並聯分支61，而該第三發光體4與該第四發光體5屬於另一該並聯分支62。於封裝開始，該第一發光體2、該第二發光體3、該第三發光體4及該第四發光體5被同步設置於該基底1之上，該第一發光體2的該第一電極24被設置於該些金屬單元12的至少其中之一，該第一發光體2的該第二電極25則設置於該些金屬單元12的其他至少其中之一，該第二發光體3的該第一電極34與該第一發光體2的該第二電極25則以該連接間距27設置於相同的至少一該金屬單元12，該第二發光體3的該第二電極35則設置於該些金屬單元12的其他至少其中之一。又，該第三發光體4的該第一電極44與該第一發光體2的該第一電極24設定為電性連接關係，故該第三發光體4的該第一電極44與該第一發光體2的該第一電極24以該連接間距27設置於相同的至少一該金屬單元12，而該第三發光體4的該第二電極45與該第一發光體2的該第二電極25被設定為電性隔離關係，故該第三發光體4的該第二電極45與該第一發光體2的該第二電極25即以該隔離間距28分隔。又，該第四發光體5的該第一電極54與該第三發光體4的該第二電極45被設定為電性連接關係，是故令該第四發光體5的該第一電極54與該第三發光體4的該第二電極45以該連接間距27設置於相同的至少一該金屬單元12之上。然而，該第四發光體5的該第一電極54與該第二發光體3的該第一電極34被設定為電性隔離關係，故令該第四發光體5的該第一電極54與該第二發光體3的該第一電極34以該隔離間距28分隔。再者，該第四發光體5的該第二電極55與該第二發光體3的該第二電極35被設定為電性連接關係，而令該第四發光體5的該第二電極55與該第二發光體3的該第二電極35以該連接間距27設置於相同的至少一該金屬單元12。如此，完成黏合後，該第一發光體2、該第二發光體3、該第三發光體4以及該第四發光體5即形成矩陣並聯。Referring to FIG. 5, an embodiment in which the LED array structure is a parallel array is described. In this embodiment, the illuminants 2 are synchronously disposed on the substrate 1 and form a moment.Arrays, and the illuminants 2 are connected to form a parallel circuit, the parallel circuit comprising at least two parallel branches 61, 62, and the illuminants 2 of the two parallel branches 61, 62 are set to be electrically connected The first electrode 24 or the second electrode 25 has the connection pitch 27 smaller than the end point spacing 121, and the first electrode 24 or the first of the two parallel branches 61, 62 is set to be electrically isolated. The two electrodes 25 have an isolation gap 28 greater than the end point spacing 121, and the first electrode 24 and the second electrode 25 are electrically connected to each other of the parallel branches 61, 62. Connection spacing 27. However, in order to clarify the technique of the present invention, the first illuminator 2, the second illuminator 3, the third illuminator 4, and the fourth illuminator 5 are previously described. The first illuminator 2 and The second illuminants 3 are located in the same row, and the third illuminants 4 are located in different columns from the first illuminant 2 but on the same row, and the fourth illuminant 5 is located in the same row as the third illuminant 4. In the column, it is defined that the first illuminant 2 and the second illuminant 3 belong to the same parallel branch 61, and the third illuminant 4 and the fourth illuminant 5 belong to the other parallel branch 62. The first illuminator 2, the second illuminator 3, the third illuminant 4, and the fourth illuminator 5 are synchronously disposed on the substrate 1 at the beginning of the package, and the first illuminant 2 An electrode 24 is disposed on at least one of the metal units 12, and the second electrode 25 of the first illuminant 2 is disposed on at least one of the other of the metal units 12, the second illuminant 3 The first electrode 34 and the second electrode 25 of the first illuminant 2 are disposed at the same at least one metal unit 12 at the connection pitch 27, and the second electrode 35 of the second illuminant 3 is disposed. At least one of the other of the metal units 12. Moreover, the first electrode 44 of the third illuminant 4 and the first electrode 24 of the first illuminant 2 are electrically connected, so the first electrode 44 of the third illuminant 4 and the first The first electrode 24 of an illuminant 2 is disposed at the same at least one metal unit 12 at the connection pitch 27, and the second electrode 45 of the third illuminant 4 and the second portion of the first illuminant 2 The electrode 25 is set to be electrically isolated, so the second electrode 45 of the third illuminant 4 and the second portion of the first illuminant 2The electrodes 25 are separated by this isolation spacing 28. Moreover, the first electrode 54 of the fourth illuminant 5 and the second electrode 45 of the third illuminant 4 are electrically connected, so that the first electrode 54 of the fourth illuminant 5 is configured. The second electrode 45 of the third illuminant 4 is disposed on the same at least one of the metal units 12 at the connection pitch 27. However, the first electrode 54 of the fourth illuminant 5 and the first electrode 34 of the second illuminant 3 are electrically isolated, so that the first electrode 54 of the fourth illuminant 5 is The first electrodes 34 of the second illuminant 3 are separated by the isolation spacing 28. Furthermore, the second electrode 55 of the fourth illuminant 5 and the second electrode 35 of the second illuminant 3 are electrically connected, and the second electrode 55 of the fourth illuminant 5 is set. The second electrode 35 of the second illuminant 3 is disposed at the same at least one metal unit 12 at the connection pitch 27. In this manner, after the bonding is completed, the first illuminant 2, the second illuminator 3, the third illuminant 4, and the fourth illuminator 5 form a matrix in parallel.
承上所述，本發明令被設定為電性隔離關係的二該發光體2的該第一電極24或該第二電極25以該隔離間距28分隔設置，然為產生該隔離間距28，被設定以該隔離間距28分隔設置的該第一電極24或該第二電極25的根據該隔離間距28的距離需求，調整其大小，以與產生該隔離間距28。According to the above description, the first electrode 24 or the second electrode 25 of the illuminant 2 that is set to be electrically isolated is separated by the isolation gap 28, but the isolation gap 28 is generated. The distance between the first electrode 24 or the second electrode 25 separated by the isolation pitch 28 according to the isolation pitch 28 is set to be adjusted to generate the isolation gap 28.
綜上所述，本發明該發光二極體陣列結構包含一基底及至少二發光體，該基底包含一承載基板以及複數排列設置於該承載基板上的金屬單元，每一該金屬單元外緣的任二點界定出一端點間距。每一該發光體包含有互為電性相異並分隔設置的一第一電極及一第二電極，每一該發光體於該第一電極與該第二電極之間界定出一電極間距，該電極間距大於該端點間距，且該些發光體更依據串聯需求或並聯或串並聯組合需求界定每一該第一電極及每一該第二電極之間具有一小於該端點間距的連接間距，或一大於該端點間距的隔離間距。藉此，令該些發光體得同步設置於該基底之上，且無需精密對位。In summary, the LED array structure of the present invention comprises a substrate and at least two illuminators, the substrate comprising a carrier substrate and a plurality of metal units arranged on the carrier substrate, each of the outer edges of the metal unit Any two points define an endpoint spacing. Each of the illuminants includes a first electrode and a second electrode that are electrically separated and spaced apart from each other, and each of the illuminators defines an electrode spacing between the first electrode and the second electrode. The electrode spacing is greater than the end point spacing, and the illuminants further define a connection between each of the first electrodes and each of the second electrodes that is less than the end spacing according to series requirements or parallel or series-parallel combination requirements. Spacing, or oneAn isolation gap greater than the endpoint spacing. Thereby, the illuminants are synchronously disposed on the substrate without precise alignment.
以上已將本發明做一詳細說明，惟以上所述者，僅為本發明之一較佳實施例而已，當不能以此限定本發明實施之範圍，即凡依本發明申請專利範圍所作之均等變化與修飾，皆應仍屬本發明之專利涵蓋範圍內。The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Variations and modifications are still within the scope of the patents of the present invention.
11‧‧‧承載基板11‧‧‧Carrier substrate
12‧‧‧金屬單元12‧‧‧Metal units
121‧‧‧端點間距121‧‧‧End point spacing
122‧‧‧分隔間距122‧‧‧ Separation spacing
2‧‧‧發光體2‧‧‧Lights
24‧‧‧第一電極24‧‧‧First electrode
25‧‧‧第二電極25‧‧‧second electrode
26‧‧‧電極間距26‧‧‧electrode spacing
27‧‧‧連接間距27‧‧‧ Connection spacing
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104138176ATWI555241B (en) | 2015-11-19 | 2015-11-19 | A light emitting diode array structure |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104138176ATWI555241B (en) | 2015-11-19 | 2015-11-19 | A light emitting diode array structure |
| Publication Number | Publication Date |
|---|---|
| TWI555241Btrue TWI555241B (en) | 2016-10-21 |
| TW201719939A TW201719939A (en) | 2017-06-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104138176ATWI555241B (en) | 2015-11-19 | 2015-11-19 | A light emitting diode array structure |
| Country | Link |
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| TW (1) | TWI555241B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201330323A (en)* | 2011-11-18 | 2013-07-16 | Luxvue Technology Corp | Microluminescent diode |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201330323A (en)* | 2011-11-18 | 2013-07-16 | Luxvue Technology Corp | Microluminescent diode |
| Publication number | Publication date |
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| TW201719939A (en) | 2017-06-01 |
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