本發明係有關於快閃記憶體(Flash Memory)之控制，尤指一種用來管理一記憶裝置之方法以及其相關之記憶裝置與控制器。The present invention relates to the control of flash memory, and more particularly to a method for managing a memory device and its associated memory device and controller.
近年來由於快閃記憶體的技術不斷地發展，各種可攜式記憶裝置(例如：符合SD/MMC、CF、MS、XD標準之記憶卡)被廣泛地實施於諸多應用中。因此，這些可攜式記憶裝置中之快閃記憶體的存取控制遂成為相當熱門的議題。In recent years, due to the continuous development of flash memory technology, various portable memory devices (for example, memory cards conforming to SD/MMC, CF, MS, and XD standards) have been widely implemented in many applications. Therefore, access control of flash memory in these portable memory devices has become a hot topic.
以常用的NAND型快閃記憶體而言，其主要可區分為單階細胞(Single Level Cell,SLC)與多階細胞(Multiple Level Cell,MLC)兩大類之快閃記憶體。單階細胞快閃記憶體中之每個被當作記憶細胞(Memory Cell；亦可稱為「記憶單元」)的電晶體只有兩種電荷值，分別用來表示邏輯值0與邏輯值1。另外，多階細胞快閃記憶體中之每個被當作記憶細胞的電晶體的儲存能力則被充分利用，係採用較高的電壓來驅動，以透過不同級別的電壓在一個電晶體中記錄多個位元之資訊(例如：00、01、11、10)；理論上，多階細胞快閃記憶體的記錄密度可以達到單階細胞快閃記憶體的記錄密度之兩倍以上，這對於曾經在發展過程中遇到瓶頸的NAND型快閃記憶體之相關產業而言，是非常好的消息。In the conventional NAND type flash memory, it can be mainly divided into two types of flash memory: single level cell (SLC) and multiple level cell (MLC). Each of the single-order cellular flash memories, which are treated as memory cells (also known as "memory cells"), has only two types of charge values, which are used to represent a logical value of 0 and a logical value of 1, respectively. In addition, the storage capacity of each of the multi-order cellular flash memory, which is treated as a memory cell, is fully utilized and is driven by a higher voltage to record in a transistor through different levels of voltage. Information on multiple bits (eg 00, 01, 11, 10); in theory, the recording density of multi-level cellular flash memory can reach more than twice the recording density of single-order cellular flash memory, It is very good news for industries related to NAND-type flash memory that have encountered bottlenecks in the development process.
相較於單階細胞快閃記憶體，由於多階細胞快閃記憶體之價格較便宜，並且在有限的空間裡可提供較大的容量，故多階細胞快閃記憶體很快地成為市面上之可攜式記憶裝置競相採用的主流。依據相關技術，由於某些類型的多階細胞快閃記憶體的運作複雜，故傳統的記憶體控制器會將多階細胞快閃記憶體內的一部分實體區塊組態成單階細胞記憶區塊，以供接收來自主裝置(Host Device)之寫入資料。然而，某些問題就產生了。例如：由於多階細胞快閃記憶體內的一部分實體區塊被組態成單階細胞記憶區塊，多階細胞快閃記憶體內可供用來作為多階細胞記憶區塊的實體區塊之數量就減少了，使得傳統的記憶裝置之整體儲存容量減少了。又例如：傳統的記憶體控制器先將接收資料暫時地寫入單階細胞記憶區塊，再將資料從單階細胞記憶區塊收集到多階細胞記憶區塊，其中這些單階細胞記憶區塊的儲存空間很容易用完，故傳統的記憶體控制器需要頻繁地抹除這些單階細胞記憶區塊。於是，傳統的記憶體控制器的工作負荷大幅地增加了，且這些額外的運作需要額外的處理時間，使得傳統的記憶裝置之整體效能變差。因此，需要一種新穎的方法來加強控管快閃記憶體之資料存取，以在不產生副作用(例如：儲存資料錯誤)的狀況下提升整體效能。Compared to single-order cellular flash memory, multi-order cellular flash memory quickly becomes a market because multi-stage cellular flash memory is cheaper and provides a larger capacity in a limited space. The mainstream of portable memory devices on the competition. According to related technology, due toSome types of multi-order cellular flash memory are complicated to operate, so the traditional memory controller configures a part of the physical blocks in the multi-order cellular flash memory into a single-order cellular memory block for receiving from The data written by the host device (Host Device). However, some problems have arisen. For example, since a part of the physical block in the multi-order cell flash memory is configured as a single-order cell memory block, the number of physical blocks available in the multi-order cell flash memory as a multi-order cell memory block is This has been reduced, resulting in a reduction in the overall storage capacity of conventional memory devices. For example, the traditional memory controller temporarily writes the received data into the single-order cell memory block, and then collects the data from the single-order cell memory block to the multi-order cell memory block, wherein these single-order cell memory regions The storage space of the block is easy to use, so the traditional memory controller needs to erase these single-order cell memory blocks frequently. As a result, the workload of the conventional memory controller has been greatly increased, and these additional operations require additional processing time, which deteriorates the overall performance of the conventional memory device. Therefore, there is a need for a novel method to enhance data access to control flash memory to improve overall performance without side effects (eg, storage data errors).
因此，本發明之目的之一在於提供一種用來管理一記憶裝置之方法以及其相關之記憶裝置與控制器，以解決上述問題。Accordingly, it is an object of the present invention to provide a method for managing a memory device and associated memory device and controller to solve the above problems.
本發明之另一目的在於提供一種用來管理一記憶裝置之方法以及其相關之記憶裝置與控制器，以提昇記憶裝置之運作效能。Another object of the present invention is to provide a method for managing a memory device and its associated memory device and controller to improve the operational efficiency of the memory device.
本發明之至少一較佳實施例中提供一種用來管理一記憶裝置之方法，該記憶裝置包含至少一非揮發性(Non-volatile,NV)記憶體元件，每一非揮發性記憶體元件包含複數個區塊(Block)，該方法係應用於該記憶裝置中之一控制器，該控制器係用來控制該至少一非揮發性記憶體元件，該方法包含有下列步驟：將接收自一主裝置(Host Device)之資料暫時地儲存於該控制器中之一揮發性記憶體作為接收資料，並動態地監控該接收資料的資料量以決定是否立即將該接收資料寫入該至少一非揮發性記憶體元件，其中接收自該主裝置之至少一寫入指令指出該主裝置要求寫入該資料；以及當決定立即將該接收資料寫入該至少一非揮發性記憶體元件時，將該接收資料直接寫入該至少一非揮發性記憶體元件中之一特定非揮發性記憶體元件當中被組態成多階細胞(Multiple Level Cell,MLC)記憶區塊之一特定區塊，而非藉由先將該接收資料暫時地寫入被組態成單階細胞(Single Level Cell,SLC)記憶區塊之任何其它區塊來間接地將該接收資料寫入該特定區塊。At least one preferred embodiment of the present invention provides a method for managing a memory device, the memory device including at least one non-volatile (NV) memory component, each non-volatile memory component comprising a plurality of blocks, the method being applied to a controller in the memory device, the controller is for controlling the at least one non-volatile memory component, the method comprising the following steps: receiving a block The data of the host device is temporarily stored in the controller as one of the volatile memory as the received data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data to the at least one non- a volatile memory component, wherein at least one write command received from the master device indicates that the master device requires writing of the data;When it is determined that the received data is immediately written into the at least one non-volatile memory component, the received data is directly written into one of the at least one non-volatile memory component, and the specific non-volatile memory component is configured to be configured A specific block of one of the Multiple Level Cell (MLC) memory blocks, rather than by temporarily writing the received data to a single-level cell (SLC) memory block. Any other block indirectly writes the received data to the particular block.
本發明於提供上述方法之同時，亦對應地提供一種記憶裝置，包含有：至少一非揮發性記憶體元件，每一非揮發性記憶體元件包含複數個區塊；以及一控制器，用來控制該至少一非揮發性記憶體元件，該控制器包含一處理單元，以依據內嵌於該處理單元或接收自該處理單元之外之一程式碼來管理該記憶裝置。另外，該控制器將接收自一主裝置之資料暫時地儲存於該控制器中之一揮發性記憶體作為接收資料，並動態地監控該接收資料的資料量以決定是否立即將該接收資料寫入該至少一非揮發性記憶體元件，其中接收自該主裝置之至少一寫入指令指出該主裝置要求寫入該資料。此外，當決定立即將該接收資料寫入該至少一非揮發性記憶體元件時，該控制器將該接收資料直接寫入該至少一非揮發性記憶體元件中之一特定非揮發性記憶體元件當中被組態成多階細胞記憶區塊之一特定區塊，而非藉由先將該接收資料暫時地寫入被組態成單階細胞記憶區塊之任何其它區塊來間接地將該接收資料寫入該特定區塊。While providing the above method, the present invention also correspondingly provides a memory device comprising: at least one non-volatile memory element, each non-volatile memory element comprising a plurality of blocks; and a controller for The at least one non-volatile memory component is controlled, the controller including a processing unit to manage the memory device according to a code embedded in or received from the processing unit. In addition, the controller temporarily stores the data received from a master device in one of the volatile memory of the controller as the received data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data. The at least one non-volatile memory component is received, wherein at least one write command received from the master device indicates that the master device requires writing of the data. In addition, when it is decided to immediately write the received data to the at least one non-volatile memory component, the controller directly writes the received data to one of the at least one non-volatile memory component, the specific non-volatile memory. The component is configured as a specific block of one of the multi-order cell memory blocks, rather than indirectly by first temporarily writing the received data to any other block configured as a single-order cell memory block. The received data is written to the specific block.
本發明於提供上述方法之同時，亦對應地提供一種記憶裝置之控制器，該記憶裝置包含至少一非揮發性記憶體元件，每一非揮發性記憶體元件包含複數個區塊，該控制器包含有：一處理單元，用來依據內嵌於該處理單元或接收自該處理單元之外之一程式碼來管理該記憶裝置。另外，該控制器將接收自一主裝置之資料暫時地儲存於該控制器中之一揮發性記憶體作為接收資料，並動態地監控該接收資料的資料量以決定是否立即將該接收資料寫入該至少一非揮發性記憶體元件，其中接收自該主裝置之至少一寫入指令指出該主裝置要求寫入該資料。此外，當決定立即將該接收資料寫入該至少一非揮發性記憶體元件時，該控制器將該接收資料直接寫入該至少一非揮發性記憶體元件中之一特定非揮發性記憶體元件當中被組態成多階細胞記憶區塊之一特定區塊，而非藉由先將該接收資料暫時地寫入被組態成單階細胞記憶區塊之任何其它區塊來間接地將該接收資料寫入該特定區塊。While providing the above method, the present invention also correspondingly provides a controller for a memory device, the memory device comprising at least one non-volatile memory component, each non-volatile memory component comprising a plurality of blocks, the controller The method includes: a processing unit configured to manage the memory device according to a code embedded in the processing unit or received from the processing unit. In addition, the controller temporarily stores the data received from a master device in one of the volatile memory of the controller as the received data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data. The at least one non-volatile memory component is received, wherein at least one write command received from the master device indicates that the master device requires writing of the data. In addition, when it is decided to immediately write the received data to theIn at least one non-volatile memory component, the controller directly writes the received data into one of the at least one non-volatile memory component and is configured as a multi-level cellular memory block One of the particular blocks, rather than indirectly writing the received data to the particular block, by first temporarily writing the received data to any other block configured as a single-order cellular memory block.
本發明的好處之一是，相較於相關技術，本發明之方法、記憶裝置、與控制器可省下單階細胞記憶區塊所佔用的儲存空間，以提供更多的多階細胞記憶區塊。因此，本發明提供較相關技術更高的儲存容量。One of the advantages of the present invention is that the method, the memory device, and the controller of the present invention can save the storage space occupied by the single-order cell memory block to provide more multi-order cell memory regions than the related art. Piece. Thus, the present invention provides a higher storage capacity than related art.
本發明的另一好處是，相較於相關技術，本發明之方法、記憶裝置、與控制器可大幅地省下先將接收資料暫時地寫入單階細胞記憶區塊再將資料從單階細胞記憶區塊收集到多階細胞記憶區塊的時間，還可省下頻繁地抹除單階細胞記憶區塊的時間。因此，本發明提供較相關技術更佳的效能。Another advantage of the present invention is that the method, the memory device, and the controller of the present invention can substantially save the temporary reception of the received data into the single-order cell memory block and then the data from the single order. The time at which the cellular memory block collects multiple levels of cellular memory blocks also saves time in frequently erasing single-order cellular memory blocks. Thus, the present invention provides better performance than related techniques.
100‧‧‧記憶裝置100‧‧‧ memory device
110‧‧‧處理單元110‧‧‧Processing unit
120‧‧‧揮發性記憶體120‧‧‧ volatile memory
130‧‧‧傳輸介面130‧‧‧Transport interface
140_0,140_1,...,140_N‧‧‧非揮發性記憶體元件140_0,140_1,...,140_N‧‧‧Non-volatile memory components
150‧‧‧匯流排150‧‧‧ busbar
200‧‧‧用來管理一記憶裝置之方法200‧‧‧Methods for managing a memory device
210,220‧‧‧步驟210,220‧‧ steps
BLK(0),BLK(1),BLK(2),...,BLK(M),BLK(m)‧‧‧區塊BLK(0), BLK(1), BLK(2),...,BLK(M),BLK(m)‧‧‧ blocks
CHP(n)‧‧‧快閃晶片CHP(n)‧‧‧flash chip
Data(0),Data(1),Data(2),Data(3),Data(4),Data(5),Data(6),Data(7),Data(8),...‧‧‧資料Data(0), Data(1), Data(2), Data(3), Data(4), Data(5), Data(6), Data(7), Data(8),...‧‧ ‧data
Page(0),Page(1),Page(2),Page(3),Page(4),Page(5),Page(6),Page(7),Page(8),...,Page(189),Page(190),Page(191)‧‧‧頁Page(0), Page(1), Page(2), Page(3), Page(4), Page(5), Page(6), Page(7), Page(8),...,Page (189), Page (190), Page (191) ‧ ‧ page
Page(63)‧‧‧頁Page (63) ‧ ‧ page
SEC(0),SEC(1),SEC(2),SEC(3)‧‧‧區段SEC(0), SEC(1), SEC(2), SEC(3)‧‧‧ Section
WL0,WL1,WL2,...,WL63‧‧‧字線WL0, WL1, WL2,..., WL63‧‧‧ word line
第1圖為依據本發明一第一實施例之一種記憶裝置的示意圖。1 is a schematic view of a memory device in accordance with a first embodiment of the present invention.
第2圖繪示本發明之一實施例中關於第1圖所示之非揮發性記憶體元件中之一者的內容安排，其中該非揮發性記憶體元件於本實施例中係為快閃晶片。2 is a view showing an arrangement of one of the non-volatile memory elements shown in FIG. 1 in an embodiment of the present invention, wherein the non-volatile memory element is a flash chip in this embodiment. .
第3圖繪示本發明之另一實施例中關於第1圖所示之非揮發性記憶體元件中之一者的內容安排，其中該非揮發性記憶體元件於本實施例中係為快閃晶片。FIG. 3 is a diagram showing the content arrangement of one of the non-volatile memory elements shown in FIG. 1 in another embodiment of the present invention, wherein the non-volatile memory element is flashed in this embodiment. Wafer.
第4圖為依據本發明一實施例之一種用來管理一記憶裝置之方法。Figure 4 is a diagram of a method for managing a memory device in accordance with an embodiment of the present invention.
第5圖繪示第4圖所示之方法於一實施例中所涉及之控制方案。FIG. 5 is a diagram showing the control scheme involved in the method shown in FIG. 4 in an embodiment.
第6圖繪示第5圖所示之控制方案的工作流程。Figure 6 shows the workflow of the control scheme shown in Figure 5.
第7圖繪示第4圖所示之方法於另一實施例中所涉及之控制方案。Figure 7 is a diagram showing the control scheme involved in the method shown in Figure 4 in another embodiment.
請參考第1圖，其繪示依據本發明一第一實施例之一種記憶裝置100的示意圖。記憶裝置100包含：一處理單元110，一揮發性(Volatile)記憶體120，一傳輸介面130，複數個非揮發性(Non-volatile,NV)記憶體元件140_0、140_1、...、與140_N(符號「N」代表一正整數)諸如(N+1)個快閃晶片，以及一匯流排150。於典型狀況下，於傳輸介面130耦接至一主裝置(未顯示於第1圖)之後，該主裝置可透過傳輸介面130來存取(Access)記憶裝置100。舉例來說，該主裝置可代表一個人電腦，例如一膝上型電腦或一桌上型電腦。Please refer to FIG. 1 , which illustrates a schematic diagram of a memory device 100 in accordance with a first embodiment of the present invention. The memory device 100 includes: a processing unit 110, a volatile (Volatile) memory 120, a transmission interface 130, and a plurality of non-volatile (NV) memory elements 140_0, 140_1, ..., and 140_N (The symbol "N" represents a positive integer) such as (N+1) flash chips, and a bus 150. In a typical case, after the transmission interface 130 is coupled to a host device (not shown in FIG. 1), the host device can access the memory device 100 through the transmission interface 130. For example, the primary device can represent a personal computer, such as a laptop or a desktop computer.
處理單元110可依據內嵌於處理單元110中或接收自處理單元110之外的程式碼(未顯示)來管理記憶裝置100。例如：該程式碼可為內嵌於處理單元110之硬體碼，尤其是一唯讀記憶體碼(ROM code)。又例如：該程式碼可為接收自處理單元110之外的韌體碼。尤其是，處理單元110係用來控制揮發性記憶體120、傳輸介面130、非揮發性記憶體元件140_0、140_1、...、與140_N、以及匯流排150。本實施例之處理單元110可為一高級縮減指令集電腦機器(Advanced Reduced Instruction Set Computer Machine,Advanced RISC Machine,ARM)處理器或一亞哥縮減指令集電腦核心(Argonaut RISC Core,ARC)處理器。這只是為了說明的目的而已，並非對本發明之限制。依據本實施例之不同的變化例，處理單元110可為其它種處理器。The processing unit 110 can manage the memory device 100 in accordance with code (not shown) embedded in or received from the processing unit 110. For example, the code may be a hardware code embedded in the processing unit 110, especially a ROM code. For another example, the code may be a firmware code received from the processing unit 110. In particular, processing unit 110 is used to control volatile memory 120, transmission interface 130, non-volatile memory elements 140_0, 140_1, . . . , and 140_N, and bus bar 150. The processing unit 110 of this embodiment may be an Advanced Reduced Instruction Set Computer (Advanced RISC Machine, ARM) processor or an Argonaut RISC Core (ARC) processor. . This is for illustrative purposes only and is not a limitation of the invention. According to various variations of this embodiment, processing unit 110 can be other types of processors.
另外，揮發性記憶體120可用來儲存一全域頁位址鏈結表(Global Page Address Linking Table)、該主裝置所存取之資料、以及用來存取記憶裝置100之其它所需資訊。本實施例之揮發性記憶體120可為一動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)或一靜態隨機存取記憶體(Static Random Access Memory,SRAM)。這只是為了說明的目的而已，並非對本發明之限制。依據本實施例之不同的變化例，揮發性記憶體120可為其它種揮發性記憶體。例如：揮發性記憶體120可包含一靜態隨機存取記憶體(Static Random Access Memory,SRAM)。In addition, the volatile memory 120 can be used to store a Global Page Address Linking Table, information accessed by the host device, and other required information for accessing the memory device 100. The volatile memory 120 of this embodiment may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). This is for illustrative purposes only and is not a limitation of the invention. According to different variations of the embodiment, the volatile memory 120Can be other kinds of volatile memory. For example, the volatile memory 120 can include a static random access memory (SRAM).
依據本實施例，第1圖所示之傳輸介面130係用來傳輸資料以及該主裝置與記憶裝置100之間的指令，其中傳輸介面130符合一特定通訊標準諸如串列高級技術附件(Serial Advanced Technology Attachment,SATA)標準、並列高級技術附件(Parallel Advanced Technology Attachment,PATA)標準、或通用序列匯流排(Universal Serial Bus,USB)標準。例如：記憶裝置100係一設置於該主裝置中之固態硬碟(Solid State Drive,SSD)，且該特定通訊標準可為用來實施該主裝置之內部通訊的一些典型通訊標準，諸如串列高級技術附件標準或並列高級技術附件標準。又例如：記憶裝置100係一固態硬碟且位於該主裝置之外，並且該特定通訊標準可為用來實施該主裝置之外部通訊的一些典型通訊標準，諸如通用序列匯流排標準。這只是為了說明的目的而已，並非對本發明之限制。依據本實施例之不同的變化例，記憶裝置100可為一可攜式記憶裝置諸如一記憶卡，且該特定通訊標準可為用來實施一記憶卡之輸入/輸出介面的一些典型通訊標準，諸如安全數碼(Secure Digital,SD)標準或小型快閃(Compact Flash,CF)標準。According to the embodiment, the transmission interface 130 shown in FIG. 1 is used for transmitting data and instructions between the host device and the memory device 100, wherein the transmission interface 130 conforms to a specific communication standard such as a serial advanced technology accessory (Serial Advanced). Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, or Universal Serial Bus (USB) standard. For example, the memory device 100 is a Solid State Drive (SSD) disposed in the host device, and the specific communication standard may be some typical communication standard used to implement internal communication of the host device, such as serial Advanced Technical Attachment Standard or Parallel Advanced Technical Attachment Standard. For another example, the memory device 100 is a solid state drive and is external to the host device, and the particular communication standard can be some typical communication standard used to implement external communication of the host device, such as a universal serial bus standard. This is for illustrative purposes only and is not a limitation of the invention. According to different variants of the embodiment, the memory device 100 can be a portable memory device such as a memory card, and the specific communication standard can be some typical communication standard for implementing an input/output interface of a memory card. Such as the Secure Digital (SD) standard or the Compact Flash (CF) standard.
另外，非揮發性記憶體元件140_0、140_1、...、與140_N係用來儲存資料，其中非揮發性記憶體元件140_0、140_1、...、與140_N可為(但不限於)NAND型快閃晶片。匯流排150係用來耦接處理單元110、揮發性記憶體120、傳輸介面130、和非揮發性記憶體元件140_0、140_1、...、與140_N，以及用來進行其通訊。於本實施例中，第1圖所示架構中除了非揮發性記憶體元件140_0、140_1、...、與140_N之外的部分可整合成一控制器，尤其是一積體電路(Integrated Circuit,IC)諸如一控制器晶片，其中該控制器係用來控制記憶裝置100中之至少一非揮發性記憶體元件諸如非揮發性記憶體元件140_0、140_1、...、與140_N，故可視為記憶裝置100之控制器。In addition, the non-volatile memory elements 140_0, 140_1, ..., and 140_N are used to store data, wherein the non-volatile memory elements 140_0, 140_1, ..., and 140_N may be (but are not limited to) NAND type Flash chip. The bus bar 150 is used to couple the processing unit 110, the volatile memory 120, the transmission interface 130, and the non-volatile memory elements 140_0, 140_1, ..., and 140_N, and to communicate therewith. In this embodiment, the parts other than the non-volatile memory elements 140_0, 140_1, ..., and 140_N in the architecture shown in FIG. 1 can be integrated into a controller, especially an integrated circuit (Integrated Circuit, IC), such as a controller chip, wherein the controller is used to control at least one non-volatile memory component such as non-volatile memory components 140_0, 140_1, ..., and 140_N in memory device 100, such that The controller of the memory device 100.
第2圖繪示本發明一實施例中關於第1圖所示之非揮發性記憶體元件140_0、140_1、...、與140_N中之任一非揮發性記憶體元件140_n的內容安排，其中非揮發性記憶體元件140_n於本實施例中可稱為快閃晶片CHP(n)，而索引n可代表落入區間[0,N]的範圍內之任一整數。如第2圖所示，非揮發性記憶體元件140_0、140_1、...、與140_N中之每一非揮發性記憶體元件諸如快閃晶片CHP(n)可包含複數個區塊(Block)諸如第2圖所示之各個區塊BLK(0)、BLK(1)、BLK(2)、...、與BLK(M)(符號「M」代表一正整數)，其中每一區塊可包含複數頁，而每一頁可包含複數個區段。於本實施例中，一區段可為最小讀取單位。換言之，在一讀取運作期間，處理單元110可讀取一個區段或複數個區段。這只是為了說明的目的而已，並非對本發明之限制。Figure 2 is a diagram showing the non-volatile recording shown in Figure 1 in an embodiment of the present invention.The content arrangement of any one of the non-volatile memory elements 140_n of the body elements 140_0, 140_1, ..., and 140_N, wherein the non-volatile memory element 140_n may be referred to as a flash wafer CHP (n in this embodiment) And the index n can represent any integer falling within the range of the interval [0, N]. As shown in FIG. 2, each of the non-volatile memory elements 140_0, 140_1, ..., and 140_N, such as the flash wafer CHP(n), may include a plurality of blocks. Each of the blocks BLK(0), BLK(1), BLK(2), ..., and BLK(M) (the symbol "M" represents a positive integer) as shown in Fig. 2, each block Multiple pages can be included, and each page can contain a plurality of segments. In this embodiment, a segment can be the minimum read unit. In other words, during a read operation, processing unit 110 can read one segment or a plurality of segments. This is for illustrative purposes only and is not a limitation of the invention.
如第2圖所示，在非揮發性記憶體元件140_n諸如快閃晶片CHP(n)中之一區塊(例如區塊BLK(0))被組態成單階細胞(Single Level Cell,SLC)記憶區塊的狀況下，該區塊諸如區塊BLK(0)可包含一預定數量之多頁，諸如分別對應於複數個字線(Word-Line)WL0、WL1、WL2、...、與WL63之各頁Page(0)、Page(1)、Page(2)、...、與Page(63)，其中每一頁諸如頁Page(0)可包含區段SEC(0)、SEC(1)、SEC(2)、與SEC(3)。這只是為了說明的目的而已，並非對本發明之限制。依據本實施例之某些變化例，諸如第3圖所示之實施例，在非揮發性記憶體元件140_n諸如快閃晶片CHP(n)中之一區塊(例如區塊BLK(0))被組態成多階細胞(Multiple Level Cell,MLC)記憶區塊諸如三階細胞(Triple Level Cell,TLC)記憶區塊的狀況下，該區塊諸如區塊BLK(0)可包含一預定數量之多頁，諸如分別對應於上述複數個字線WL0、WL1、WL2、...、與WL63之各組頁{Page(0),Page(1),Page(2)}、{Page(3),Page(4),Page(5)}、{Page(6),Page(7),Page(8)}、...、與{Page(189),Page(190),Page(191)}，其中每一頁諸如頁Page(0)可包含區段SEC(0)、SEC(1)、SEC(2)、與SEC(3)。As shown in FIG. 2, one of the non-volatile memory elements 140_n such as the flash wafer CHP(n) (for example, the block BLK(0)) is configured as a single-level cell (Single Level Cell, SLC). In the case of a memory block, the block, such as block BLK(0), may comprise a predetermined number of pages, such as corresponding to a plurality of word lines (Word-Line) WL0, WL1, WL2, ..., respectively. Pages (0), Page(1), Page(2), ..., and Page(63) with WL63, where each page such as Page(0) may contain a section SEC(0), SEC (1), SEC (2), and SEC (3). This is for illustrative purposes only and is not a limitation of the invention. According to some variations of this embodiment, such as the embodiment illustrated in FIG. 3, one of the non-volatile memory elements 140_n, such as a flash wafer CHP(n) (eg, block BLK(0)) In the case of being configured as a multiple level cell (MLC) memory block such as a Triple Level Cell (TLC) memory block, the block such as block BLK(0) may contain a predetermined number a plurality of pages, such as respective pages {Page(0), Page(1), Page(2)}, {Page(3) corresponding to the plurality of word lines WL0, WL1, WL2, ..., and WL63, respectively. ), Page(4), Page(5)}, {Page(6), Page(7), Page(8)},..., and {Page(189), Page(190), Page(191) }, where each page such as page Page(0) may contain sections SEC(0), SEC(1), SEC(2), and SEC(3).
第4圖為依據本發明一實施例之一種用來管理一記憶裝置之方法200。該方法可應用於第1圖所示之記憶裝置100，尤其是上述之控制器(例如：透過處理單元110執行上述程式碼之記憶體控制器)，其中執行上述程式碼之該控制器係用來控制上述之至少一非揮發性記憶體元件諸如第1圖所示之非揮發性記憶體元件140_0、140_1、...、與140_N。該方法說明如下：於步驟210中，該控制器將接收自該主裝置之資料暫時地儲存於該控制器中之揮發性記憶體120作為接收資料，並動態地監控該接收資料的資料量以決定是否立即將該接收資料寫入上述之至少一非揮發性記憶體元件，其中接收自該主裝置之至少一寫入指令指出該主裝置要求寫入該資料。尤其是，當該接收資料的資料量達到一預定資料量門檻值PDDA_TH時，該控制器決定立即將該接收資料寫入上述之至少一非揮發性記憶體元件。Figure 4 is a diagram of a memory device for managing a memory device in accordance with an embodiment of the present invention.Method 200. The method can be applied to the memory device 100 shown in FIG. 1 , in particular, the above-mentioned controller (for example, a memory controller that executes the above code through the processing unit 110 ), wherein the controller for executing the above code is used. The at least one non-volatile memory component such as the non-volatile memory components 140_0, 140_1, ..., and 140_N shown in FIG. 1 are controlled. The method is as follows: In step 210, the controller temporarily stores the data received from the main device in the volatile memory 120 in the controller as receiving data, and dynamically monitors the amount of data of the received data. Determining whether the received data is immediately written to the at least one non-volatile memory component, wherein at least one write command received from the primary device indicates that the primary device requires the data to be written. In particular, when the amount of data of the received data reaches a predetermined data threshold PDDA_TH, the controller determines to immediately write the received data to the at least one non-volatile memory component.
於步驟220中，當決定立即將該接收資料寫入上述之至少一非揮發性記憶體元件時，該控制器將該接收資料直接寫入上述之至少一非揮發性記憶體元件中之一特定非揮發性記憶體元件當中被組態成多階細胞記憶區塊(例如第3圖所示實施例中具有192頁Page(0),Page(1),...,Page(191)之該區塊)之一特定區塊，而非藉由先將該接收資料暫時地寫入被組態成單階細胞記憶區塊(例如第2圖所示實施例中具有64頁Page(0),Page(1),...,Page(63)之該區塊)之任何其它區塊來間接地將該接收資料寫入該特定區塊。例如：該特定非揮發性記憶體元件可為第3圖所示實施例中之快閃晶片CHP(n)，其中該特定區塊可為區塊{BLK(0),BLK(1),BLK(2),...,BLK(M)}中之一區塊諸如區塊BLK(m)，而索引m可代表落入區間[0,M]的範圍內之任一整數。In step 220, when it is determined that the received data is immediately written into the at least one non-volatile memory component, the controller directly writes the received data to one of the at least one non-volatile memory component. Among the non-volatile memory elements, it is configured as a multi-order cell memory block (for example, in the embodiment shown in FIG. 3, there are 192 pages of Page(0), Page(1), ..., Page(191). a particular block, rather than by first temporarily writing the received data into a single-order cellular memory block (eg, having 64 pages of Page(0) in the embodiment shown in FIG. 2, Any other block of Page(1), ..., the block of Page (63) indirectly writes the received data to the particular block. For example, the specific non-volatile memory component can be the flash wafer CHP(n) in the embodiment shown in FIG. 3, wherein the specific block can be a block {BLK(0), BLK(1), BLK. One of the blocks (2), ..., BLK(M)} such as the block BLK(m), and the index m may represent any integer falling within the range of the interval [0, M].
依據本實施例，在該特定區塊中之一記憶細胞(Memory Cell)被用來儲存複數個位元的狀況下，該複數個位元需被重複地寫入該記憶細胞達一預定次數PDNT_WR以使該記憶細胞於該特定非揮發性記憶體元件當中被正確地程式化(Programmed)，以致該複數個位元中之每一位元均正確地儲存於該記憶細胞以供進一步讀取，其中預定次數PDNT_WR大於一。實作上，揮發性記憶體120的儲存容量大於或等於預定資料量門檻值PDDA_TH和預定次數PDNT_WR之乘積(PDDA_TH * PDNT_WR)，以容許該接收資料之至少一部分被用於該記憶細胞之重複寫入運作。例如：針對某些類型的多階細胞快閃記憶體而言，該特定區塊可被組態成三階細胞記憶區塊，而預定次數PDNT_WR可等於三，並且預定資料量門檻值PDDA_TH可等於該特定非揮發性記憶體元件當中屬於一個字線(Word-Line)之一組記憶細胞的儲存容量。這只是為了說明的目的而已，並非對本發明之限制。According to this embodiment, in a case where one memory cell (Memory Cell) in the specific block is used to store a plurality of bits, the plurality of bits are repeatedly written into the memory cell for a predetermined number of times PDNT_WR So that the memory cells are correctly programmed in the particular non-volatile memory element such that each of the plurality of bits is correctly stored in the memory cell for further reading, The predetermined number of times PDNT_WR is greater than one. In practice,The storage capacity of the volatile memory 120 is greater than or equal to the product of the predetermined data amount threshold PDDA_TH and the predetermined number of times PDNT_WR (PDDA_TH * PDNT_WR) to allow at least a portion of the received data to be used for the repeated write operation of the memory cell. For example, for certain types of multi-level cellular flash memory, the particular block can be configured as a third-order cellular memory block, and the predetermined number of PDNT_WR can be equal to three, and the predetermined data threshold value PDDA_TH can be equal to Among the specific non-volatile memory elements, the storage capacity of one of the memory cells belonging to one word line. This is for illustrative purposes only and is not a limitation of the invention.
請注意，於本實施例中，該控制器可多次將該接收資料直接寫入該特定區塊，以確保使用者資料不會有任何錯誤。尤其是，在該控制器之控制下，該接收資料被寫入該特定區塊之次數達到預定次數PDNT_WR以使該特定區塊中屬於一特定字線之一特定組記憶細胞於該特定非揮發性記憶體元件當中被正確地程式化，以致該接收資料中之每一位元均正確地儲存於該特定組記憶細胞以供進一步讀取。Please note that in this embodiment, the controller can directly write the received data to the specific block to ensure that the user data does not have any errors. In particular, under the control of the controller, the received data is written into the specific block for a predetermined number of times PDNT_WR such that a particular group of memory cells belonging to a particular word line in the particular block is in the particular non-volatile The memory elements are correctly programmed so that each bit in the received data is correctly stored in the particular set of memory cells for further reading.
另外，在該主裝置欲從上述之至少一非揮發性記憶體元件讀取該資料的狀況下(例如該主裝置傳送一個或多個讀取指令至記憶裝置100)，該資料於步驟210中尚未被寫入任何非揮發性記憶體元件。因此，在決定立即將該接收資料寫入上述之至少一非揮發性記憶體元件之前，當接收自該主裝置之至少一讀取指令指出該主裝置要求讀取該資料之至少一部分時，該控制器可自揮發性記憶體120讀取該資料之該至少一部分以供回傳予該主裝置，而非自該特定非揮發性記憶體元件讀取該資料之該至少一部分。In addition, in the case that the master device wants to read the data from the at least one non-volatile memory component (for example, the master device transmits one or more read commands to the memory device 100), the data is in step 210. Has not been written to any non-volatile memory components. Therefore, before deciding to immediately write the received data to the at least one non-volatile memory element, when at least one read command received from the host device indicates that the host device requests to read at least a portion of the data, The controller can read the at least a portion of the data from the volatile memory 120 for transmission back to the host device, rather than reading the at least a portion of the data from the particular non-volatile memory component.
依據本實施例之某些變化例，該控制器自該主裝置分別接收複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...，且將該複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...暫時地儲存於揮發性記憶體120，其中該複數組資料中之每一組資料包含複數頁，且該複數組資料中之每一組資料的資料量等於預定資料量門檻值PDDA_TH。尤其是，該控制器自揮發性記憶體120分別讀取該複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...，以分別將該複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...直接寫入該特定區塊，並且多次將該複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...中之第一組資料{Data(0),Data(1),Data(2)}直接寫入該特定區塊，其中第一組資料{Data(0),Data(1),Data(2)}被寫入該特定區塊之次數達到預定次數PDNT_WR以使該特定區塊中屬於一特定字線之一特定組記憶細胞於該特定非揮發性記憶體元件當中被正確地程式化，以致第一組資料{Data(0),Data(1),Data(2)}中之每一位元均正確地儲存於該特定組記憶細胞以供進一步讀取。According to some variations of the embodiment, the controller receives the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), respectively, from the master device. Data(5)}, {Data(6), Data(7), Data(8)}, ..., and the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6), Data(7), Data(8)}, ... are temporarily stored in the volatile memory 120, wherein the plural Each group of data in the group data includes a plurality of pages, and the data amount of each group of data in the complex array data is equal to a predetermined data amount threshold PDDA_TH. In particular, the controller is self-containedThe volatile memory 120 reads the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6, respectively) ), Data(7), Data(8)}, ..., to separate the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4 ), Data(5)}, {Data(6), Data(7), Data(8)}, ... directly write to the specific block, and the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6), Data(7), Data(8)},... The first set of data {Data(0), Data(1), Data(2)} is directly written to the specific block, where the first set of data {Data(0), Data(1), Data(2)} is Writing the specific block a predetermined number of times PDNT_WR such that a particular group of memory cells belonging to a particular word line in the particular block are correctly programmed in the particular non-volatile memory element, such that the first group Each bit of the data {Data(0), Data(1), Data(2)} is correctly stored in the particular set of memory cells for further reading.
第5圖繪示第4圖所示之方法200於一實施例中所涉及之控制方案，而第6圖繪示第5圖所示之控制方案的工作流程300，其中第5圖所示之資料Data(0)、Data(1)、Data(2)、Data(3)、Data(4)、Data(5)、Data(6)、Data(7)、Data(8)、...中之每一者可為一頁資料。例如：一頁資料的大小可為16KB(Kilobyte，即千位元組)。這只是為了說明的目的而已，並非對本發明之限制。5 is a diagram showing a control scheme involved in the method 200 shown in FIG. 4, and FIG. 6 is a diagram showing a workflow 300 of the control scheme shown in FIG. 5, wherein FIG. 5 is shown in FIG. Data (0), Data (1), Data (2), Data (3), Data (4), Data (5), Data (6), Data (7), Data (8), ... Each of them can be a page of information. For example, the size of a page of data can be 16KB (Kilobyte, that is, thousands of bytes). This is for illustrative purposes only and is not a limitation of the invention.
於步驟310中，該控制器自該主裝置逐頁地接收包含複數頁之第一組資料{Data(0),Data(1),Data(2)}直到第一組資料{Data(0),Data(1),Data(2)}的總接收資料量達到預定資料量門檻值PDDA_TH，且將第一組資料{Data(0),Data(1),Data(2)}暫時地儲存於揮發性記憶體120，其中在第一組資料{Data(0),Data(1),Data(2)}之總接收資料量達到預定資料量門檻值PDDA_TH之前，第一組資料{Data(0),Data(1),Data(2)}並未被寫入該特定區塊。In step 310, the controller receives the first set of data {Data(0), Data(1), Data(2)} containing the plural pages page by page from the master device until the first group of data {Data(0) The total received data amount of Data(1), Data(2)} reaches the predetermined data amount threshold PDDA_TH, and the first group of data {Data(0), Data(1), Data(2)} is temporarily stored in The volatile memory 120, wherein the first group of data {Data(0) before the total received data amount of the first group of data {Data(0), Data(1), Data(2)} reaches the predetermined data amount threshold PDDA_TH ), Data(1), Data(2)} are not written to this particular block.
於步驟312中，當第一組資料{Data(0),Data(1),Data(2)}之總接收資料量達到預定資料量門檻值PDDA_TH時，該控制器自揮發性記憶體120讀取第一組資料{Data(0),Data(1),Data(2)}之至少一部分，以將第一組資料{Data(0),Data(1),Data(2)}直接寫入該特定區塊。In step 312, when the total received data amount of the first group of data {Data(0), Data(1), Data(2)} reaches the predetermined data amount threshold PDDA_TH, the controller reads from the volatile memory 120. Taking at least a portion of the first set of data {Data(0), Data(1), Data(2)} to the first group of fundsThe material {Data(0), Data(1), Data(2)} is directly written to the specific block.
於步驟320中，該控制器自該主裝置逐頁地接收包含複數頁之第二組資料{Data(3),Data(4),Data(5)}直到第二組資料{Data(3),Data(4),Data(5)}的總接收資料量達到預定資料量門檻值PDDA_TH，且將第二組資料{Data(3),Data(4),Data(5)}暫時地儲存於揮發性記憶體120，其中在第二組資料{Data(3),Data(4),Data(5)}之總接收資料量達到預定資料量門檻值PDDA_TH之前，第二組資料{Data(3),Data(4),Data(5)}並未被寫入該特定區塊。In step 320, the controller receives a second set of data {Data(3), Data(4), Data(5)} containing a plurality of pages from the master device page by page until the second group of data {Data(3) The total received data amount of Data(4), Data(5)} reaches the predetermined data amount threshold PDDA_TH, and the second group data {Data(3), Data(4), Data(5)} is temporarily stored in The volatile memory 120, wherein the second group of data {Data(3) is before the total amount of received data of the second group of data {Data(3), Data(4), Data(5)} reaches the predetermined data amount threshold PDDA_TH ), Data(4), Data(5)} are not written to this particular block.
於步驟322中，當第二組資料{Data(3),Data(4),Data(5)}之總接收資料量達到預定資料量門檻值PDDA_TH時，該控制器自揮發性記憶體120讀取第二組資料{Data(3),Data(4),Data(5)}之至少一部分，以將第二組資料{Data(3),Data(4),Data(5)}直接寫入該特定區塊，並且第二次將第一組資料{Data(0),Data(1),Data(2)}直接寫入該特定區塊。In step 322, when the total received data amount of the second group of data {Data(3), Data(4), Data(5)} reaches the predetermined data amount threshold PDDA_TH, the controller reads from the volatile memory 120. Taking at least a portion of the second set of data {Data(3), Data(4), Data(5)} to directly write the second set of data {Data(3), Data(4), Data(5)} This particular block, and the first time the first set of data {Data(0), Data(1), Data(2)} is written directly to that particular block.
於步驟330中，該控制器自該主裝置逐頁地接收包含複數頁之第三組資料{Data(6),Data(7),Data(8)}直到第三組資料{Data(6),Data(7),Data(8)}的總接收資料量達到預定資料量門檻值PDDA_TH，且將第三組資料{Data(6),Data(7),Data(8)}暫時地儲存於揮發性記憶體120，其中在第三組資料{Data(6),Data(7),Data(8)}之總接收資料量達到預定資料量門檻值PDDA_TH之前，第三組資料{Data(6),Data(7),Data(8)}並未被寫入該特定區塊。In step 330, the controller receives a third set of data {Data(6), Data(7), Data(8)} containing a plurality of pages from the master device page by page until the third group of data {Data(6) The total received data amount of Data(7), Data(8)} reaches the predetermined data amount threshold PDDA_TH, and the third group data {Data(6), Data(7), Data(8)} is temporarily stored in The volatile memory 120, wherein the third group of data {Data(6) is before the total received data amount of the third group of data {Data(6), Data(7), Data(8)} reaches the predetermined data amount threshold PDDA_TH. ), Data(7), Data(8)} are not written to this particular block.
於步驟332中，當第三組資料{Data(6),Data(7),Data(8)}之總接收資料量達到預定資料量門檻值PDDA_TH時，該控制器自揮發性記憶體120讀取第三組資料{Data(6),Data(7),Data(8)}之至少一部分，以將第三組資料{Data(6),Data(7),Data(8)}直接寫入該特定區塊，並且第二次將第二組資料{Data(3),Data(4),Data(5)}直接寫入該特定區塊，以及第三次將第一組資料{Data(0),Data(1),Data(2)}直接寫入該特定區塊，藉此，第一組資料{Data(0),Data(1),Data(2)}中之任一頁資料的每一位元均正確地儲存於該特定區塊以供進一步讀取。例如：在預定次數PDNT_WR等於三的狀況下，第一組資料{Data(0),Data(1),Data(2)}之寫入運作已完成。In step 332, when the total received data amount of the third group of data {Data(6), Data(7), Data(8)} reaches the predetermined data amount threshold PDDA_TH, the controller reads from the volatile memory 120. Take at least part of the third set of data {Data(6), Data(7), Data(8)} to directly write the third set of data {Data(6), Data(7), Data(8)} The specific block, and the second time the second set of data {Data(3), Data(4), Data(5)} is written directly to the specific block, and the third time the first set of data {Data( 0), Data (1), Data (2)} directly write to the specific block, whereby the first set of data {Data (0),Each bit of the data of any of Data(1), Data(2)} is correctly stored in the particular block for further reading. For example, in the case where the predetermined number of times PDNT_WR is equal to three, the writing operation of the first group of materials {Data(0), Data(1), Data(2)} has been completed.
針對該複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...中之後續各組資料，該控制器可依據第6圖所示之工作流程300所掲露的運作(尤其是步驟330及步驟332中之運作)對應地進行處理；依此類推。例如：當該複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...中之第四組資料{Data(9),Data(10),Data(11)}之總接收資料量達到預定資料量門檻值PDDA_TH時，該控制器自揮發性記憶體120讀取第四組資料{Data(9),Data(10),Data(11)}之至少一部分，以將第四組資料{Data(9),Data(10),Data(11)}直接寫入該特定區塊，並且第二次將第三組資料{Data(6),Data(7),Data(8)}直接寫入該特定區塊，以及第三次將第二組資料{Data(3),Data(4),Data(5)}直接寫入該特定區塊，藉此，第二組資料{Data(3),Data(4),Data(5)}中之任一頁資料的每一位元均正確地儲存於該特定區塊以供進一步讀取，其中，在預定次數PDNT_WR等於三的狀況下，第二組資料{Data(3),Data(4),Data(5)}之寫入運作已完成。於是，藉由利用第6圖所示之工作流程300，該複數組資料{Data(0),Data(1),Data(2)}、{Data(3),Data(4),Data(5)}、{Data(6),Data(7),Data(8)}、...中之所有的資料最終均正確地儲存於該特定區塊以供進一步讀取。本實施例與前述實施例/變化例相仿之處不再重複贅述。For the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6), Data(7), The subsequent sets of data in Data(8)}, ..., the controller can be correspondingly operated according to the operations disclosed in the workflow 300 shown in FIG. 6 (especially the operations in steps 330 and 332) Processing; and so on. For example: when the complex array data {Data (0), Data (1), Data (2)}, {Data (3), Data (4), Data (5)}, {Data (6), Data (7 When the total amount of received data of the fourth group of data {Data(9), Data(10), Data(11)} of Data(8)}, ... reaches the predetermined data amount threshold PDDA_TH, the controller Reading at least a portion of the fourth set of data {Data(9), Data(10), Data(11)} from the volatile memory 120 to the fourth set of data {Data(9), Data(10), Data (11)} directly write to the specific block, and the third time to write the third set of data {Data(6), Data(7), Data(8)} directly to the specific block, and the third time The second set of data {Data(3), Data(4), Data(5)} is directly written to the specific block, whereby the second set of data {Data(3), Data(4), Data(5) Each bit of any page of the } is correctly stored in the specific block for further reading, wherein, in the case that the predetermined number of times PDNT_WR is equal to three, the second group of data {Data(3), Data (4), the write operation of Data(5)} has been completed. Thus, by using the workflow 300 shown in FIG. 6, the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5) All data in {}(}, {Data(6), Data(7), Data(8)}, ... are finally correctly stored in this particular block for further reading. The description of the embodiment that is similar to the foregoing embodiment/variation will not be repeated.
第7圖繪示第4圖所示之方法200於另一實施例中所涉及之控制方案，其中第7圖所示之資料Data(0)、Data(1)、Data(2)、Data(3)、Data(4)、Data(5)、Data(6)、Data(7)、Data(8)、...中之每一者可為16KB的大小之資料，且可區分為一組各自為4KB的大小之資料(於第7圖中係分別標示成「4K」，即4KB的大小之意)。本實施例可用於隨機邏輯位址的資料之寫入。這只是為了說明的目的而已，並非對本發明之限制。FIG. 7 is a diagram showing a control scheme involved in the method 200 shown in FIG. 4 in another embodiment, wherein the data (0), Data (1), Data (2), and Data (FIG. 7) are shown in FIG. 3), Data (4), Data (5), Data (6), Data (7), Data (8), ... each of which can be 16 KB of size data, and can be divided into a group The data of each size of 4 KB (in Figure 7 is indicated as "4K", which is the size of 4 KB). This embodiment can be used for writing data of random logical addresses. This is for illustrative purposes only and is not a limitation of the invention.
依據本實施例，該控制器可利用揮發性記憶體120收集隨機邏輯位址的資料，其中一個隨機寫入運作的資料之大小可為4KB。當收集到的資料之大小達到16KB時，該控制器可將所收集到16KB之資料視為第5圖所示實施例中之一頁資料(例如：資料Data(0)；又例如：其它資料Data(1)、Data(2)、Data(3)、Data(4)、Data(5)、Data(6)、Data(7)、Data(8)、...中之任一者)來進行處理。本實施例與前述實施例/變化例相仿之處不再重複贅述。According to the embodiment, the controller can use the volatile memory 120 to collect data of random logical addresses, wherein the size of a random write operation data can be 4 KB. When the size of the collected data reaches 16 KB, the controller can treat the collected 16 KB of data as one page of the embodiment shown in Figure 5 (for example: data Data (0); for example: other data Data (1), Data (2), Data (3), Data (4), Data (5), Data (6), Data (7), Data (8), ... any one of them) Process it. The description of the embodiment that is similar to the foregoing embodiment/variation will not be repeated.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100‧‧‧記憶裝置100‧‧‧ memory device
110‧‧‧處理單元110‧‧‧Processing unit
120‧‧‧揮發性記憶體120‧‧‧ volatile memory
130‧‧‧傳輸介面130‧‧‧Transport interface
140_0,140_1,...,140_N‧‧‧非揮發性記憶體元件140_0,140_1,...,140_N‧‧‧Non-volatile memory components
150‧‧‧匯流排150‧‧‧ busbar
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