本發明是有關於一種封裝結構及其製作方法，且特別是有關於一種多晶片堆疊封裝結構及其製作方法。The present invention relates to a package structure and a method of fabricating the same, and more particularly to a multi-wafer stack package structure and a method of fabricating the same.
隨著半導體技術的改良，使得液晶顯示器具有低的消耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點，因而廣泛地應用在行動電話、筆記型電腦或桌上型電腦的液晶螢幕及液晶電視等與生活息息相關之電子產品。其中，顯示器之驅動晶片(driver IC)更是液晶顯示器不可或缺的重要元件。With the improvement of semiconductor technology, liquid crystal displays have the advantages of low power consumption, light weight, high resolution, high color saturation, long life, etc., and thus are widely used in mobile phones, notebook computers or desktop computers. LCD screens and LCD TVs and other electronic products that are closely related to life. Among them, the driver IC of the display is an indispensable component of the liquid crystal display.
因應液晶顯示裝置驅動晶片各種應用之需求，一般是採用捲帶自動接合封裝技術進行晶片封裝，其中包括有薄膜覆晶(Chip On Film,COF)封裝、捲帶承載封裝(Tape Carrier Package,TCP)等。捲帶自動接合封裝係將半導體晶片電性連接於表面形成有配線構造的可撓性薄膜基材上，其中配線構造包含輸入端引腳及輸出端引腳，這些引腳的內端電性連接晶片之電性端點(例如：凸塊)。In view of the needs of various applications of liquid crystal display device driving wafers, wafer packaging is generally carried out by using tape and tape automatic bonding packaging technology, including chip on film (COF) packaging and tape carrier package (TCP). Wait. The tape automatic bonding package electrically connects the semiconductor wafer to the flexible film substrate having the wiring structure formed on the surface, wherein the wiring structure includes an input terminal pin and an output terminal pin, and the inner ends of the pins are electrically connected. The electrical end of the chip (for example:Bump).
詳細而言，以捲帶自動接合方式進行晶片封裝的製程，係在完成可撓性薄膜基材上的線路及晶片上的凸塊製程之後，將可撓性薄膜基材上之元件設置區與晶片對位，並利用熱壓頭進行加熱及加壓，以進行內引腳接合(inner lead bonding，ILB)，使晶片上的凸塊與可撓性基板上的內引腳產生共晶接合而電性連接。然而，由於行動裝置、液晶顯示器、液晶電視等電子產品之功能需求日益複雜化、速度及解析度不斷提升，驅動晶片之積體電路密度亦須配合不斷增加，且接點/引腳之間隙則須持續縮減。然而，於晶片之有限空間內，增加輸出入端點(I/O)以及縮小間隙在電性表現、製程及良率上皆有其瓶頸。In detail, the process of performing wafer package by the tape and tape automatic bonding method is to complete the component setting area on the flexible film substrate after completing the process on the flexible film substrate and the bump process on the wafer. The wafer is aligned and heated and pressurized by a thermal head for inner lead bonding (ILB) to cause eutectic bonding of the bumps on the wafer to the inner leads on the flexible substrate. Electrical connection. However, as the functional requirements of electronic devices such as mobile devices, liquid crystal displays, and liquid crystal televisions are becoming more complex, speed, and resolution are increasing, the integrated circuit density of the driving chips must be increased, and the gap between contacts and pins is increased. Must continue to shrink. However, in the limited space of the chip, increasing the input and output terminals (I/O) and narrowing the gap have bottlenecks in electrical performance, process, and yield.
本發明提供一種多晶片堆疊封裝結構，適於在不需增加單顆晶片之積體電路密度與持續縮減接點/引腳間距之情況下，仍可增加輸出入端點(I/O)的數量，以因應電子產品高速、多功能、高解析度、高效能等需求。The present invention provides a multi-wafer stacked package structure suitable for increasing input/output terminals (I/O) without increasing the integrated circuit density of a single wafer and continuously reducing the contact/pin pitch. The number is in response to the needs of high-speed, multi-functional, high-resolution, high-performance electronic products.
本發明另提供一種多晶片堆疊封裝結構的製作方法，可於一次製程即同時接合多個晶片，可有效縮減製作時間及程序，進而降低製造成本。The present invention further provides a method for fabricating a multi-wafer stacked package structure, which can simultaneously bond a plurality of wafers in one process, thereby effectively reducing production time and procedures, thereby reducing manufacturing costs.
本發明的多晶片堆疊封裝結構包括晶片堆疊結構以及可撓性基板。晶片堆疊結構包括第一晶片與第二晶片。第一晶片具有第一主動表面以及多個配置於第一主動表面上的第一接墊。第二晶片具有第二主動表面以及多個配置於第二主動表面上的第二接墊，其中第二晶片疊置於第一晶片的第一主動表面上並暴露出第一接墊。可撓性基板包括至少一絕緣層、多個第一引腳以及多個的第二引腳。絕緣層具有第一表面、第二表面以及元件孔。第一引腳位於絕緣層之第一表面上並延伸至元件孔中，而與第一接墊電性連接。第二引腳設置於絕緣層之第二表面上並延伸至元件孔中，而與第二接墊電性連接。The multi-wafer stacked package structure of the present invention includes a wafer stack structure and a flexible substrate. The wafer stack structure includes a first wafer and a second wafer. First waferThere is a first active surface and a plurality of first pads disposed on the first active surface. The second wafer has a second active surface and a plurality of second pads disposed on the second active surface, wherein the second wafer is stacked on the first active surface of the first wafer and exposes the first pads. The flexible substrate includes at least one insulating layer, a plurality of first pins, and a plurality of second pins. The insulating layer has a first surface, a second surface, and an element hole. The first pin is located on the first surface of the insulating layer and extends into the component hole to be electrically connected to the first pad. The second pin is disposed on the second surface of the insulating layer and extends into the component hole to be electrically connected to the second pad.
在本發明的一實施例中，上述的多晶片堆疊封裝結構更包括封裝膠體。封裝膠體填充於元件孔內以包覆第一晶片、第二晶片、第一引腳以及第二引腳。In an embodiment of the invention, the multi-wafer stack package structure further includes an encapsulant. The encapsulant is filled in the component hole to cover the first wafer, the second wafer, the first pin, and the second pin.
在本發明的一實施例中，上述的可撓性基板更包括一防焊層。防焊層分別配置於絕緣層之第一表面與第二表面上，以局部覆蓋第一引腳與第二引腳。In an embodiment of the invention, the flexible substrate further includes a solder resist layer. The solder resist layers are respectively disposed on the first surface and the second surface of the insulating layer to partially cover the first pin and the second pin.
在本發明的一實施例中，上述的多晶片堆疊封裝結構更包括膠層。膠層配置於第一晶片與第二晶片之間，其中膠層為導熱膠材。In an embodiment of the invention, the multi-wafer stack package structure further includes a glue layer. The adhesive layer is disposed between the first wafer and the second wafer, wherein the adhesive layer is a thermal conductive adhesive.
在本發明的一實施例中，上述的第二晶片的第二主動表面的面積小於或等於第一晶片的第一主動表面的面積。In an embodiment of the invention, the area of the second active surface of the second wafer is less than or equal to the area of the first active surface of the first wafer.
本發明另提出一種多晶片堆疊封裝結構的製作方法包括以下步驟。提供第一晶片，第一晶片具有第一主動表面以及多個配置於第一主動表面上的第一接墊。將第二晶片貼附於第一晶片的第一主動表面上並暴露出第一接墊，以形成晶片堆疊結構，其中第二晶片具有第二主動表面以及多個配置於第二主動表面上的第二接墊。提供可撓性基板，可撓性基板包括至少一絕緣層、多個第一引腳以及多個第二引腳，絕緣層具有第一表面、第二表面以及元件孔，第一引腳位於絕緣層之第一表面上並延伸至元件孔中，第二引腳設置於絕緣層之第二表面上並延伸至元件孔中。將晶片堆疊結構與絕緣層的元件孔對位，並藉由熱壓頭使得第一引腳與第二引腳分別和第一接墊與第二接墊接合而彼此電性連接。The present invention further provides a method for fabricating a multi-wafer stacked package structure including the following steps. A first wafer is provided, the first wafer having a first active surface and a plurality of first pads disposed on the first active surface. Attaching the second wafer to the first waferThe first active surface exposes the first pad to form a wafer stack structure, wherein the second wafer has a second active surface and a plurality of second pads disposed on the second active surface. Providing a flexible substrate, the flexible substrate comprising at least one insulating layer, a plurality of first pins and a plurality of second pins, the insulating layer having a first surface, a second surface, and an element hole, the first pin being located in the insulation The first surface of the layer extends into the component hole, and the second pin is disposed on the second surface of the insulating layer and extends into the component hole. The wafer stack structure is aligned with the component holes of the insulating layer, and the first pin and the second pin are electrically connected to each other by bonding with the first pad and the second pad by the thermal head.
在本發明的一實施例中，上述的熱壓頭具有第一壓合面與第二壓合面。藉由下壓熱壓頭使得第一壓合面與第二壓合面分別抵接第一引腳以及第二引腳，並使得第一引腳與第二引腳分別和第一接墊與第二接墊接合而彼此電性連接。In an embodiment of the invention, the thermal head has a first pressing surface and a second pressing surface. The first pressing surface and the second pressing surface respectively abut the first pin and the second pin by pressing the thermal head, and respectively making the first pin and the second pin and the first pad respectively The second pads are joined to each other and electrically connected to each other.
在本發明的一實施例中，上述的熱壓頭具有多個引腳讓位區，以令在下壓熱壓頭的過程中，熱壓頭藉由引腳讓位區避開第二引腳，以令第一壓合面與第二壓合面分別抵接第一引腳以及第二引腳。In an embodiment of the invention, the thermal head has a plurality of pin yielding regions, so that during the pressing of the thermal head, the thermal head avoids the second pin by the pin yielding region. The first pressing surface and the second pressing surface respectively abut the first pin and the second pin.
在本發明的一實施例中，在將晶片堆疊結構與絕緣層的元件孔對位，並藉由熱壓頭使得第一引腳與第二引腳分別與第一接墊與第二接墊接合而彼此電性連接後，更包括於元件孔內填充封裝膠體，且封裝膠體包覆第一晶片、第二晶片、第一引腳以及第二引腳。In an embodiment of the invention, the wafer stack structure is aligned with the component holes of the insulating layer, and the first pin and the second pin are respectively connected to the first pad and the second pad by the thermal head. After being electrically connected to each other, the package hole is filled in the component hole, and the package paste covers the first wafer, the second wafer, the first pin and the second pin.
基於上述，本發明的多晶片堆疊封裝結構包括晶片堆疊結構以及具有多層引腳之可撓性基板，其中晶片堆疊結構之第二晶片配置於第一晶片的第一主動表面上，並暴露出第一主動表面上的第一接墊，以使第一晶片與第二晶片分別與配置於可撓性基板之絕緣層的相對二表面上的第一引腳與第二引腳電性連接。據此，本發明之多晶片堆疊封裝結構可藉由多個晶片的配置以及多層引腳之可撓性基板，使單一封裝體在不需增加單顆晶片之積體電路密度與持續縮減接點/引腳間距之情況下，仍可增加輸出入端點(I/O)的數量，以因應電子產品高速、多功能、高解析度、高效能等需求。Based on the above, the multi-wafer stacked package structure of the present invention includes a wafer stacka structure and a flexible substrate having a plurality of layers, wherein the second wafer of the wafer stack is disposed on the first active surface of the first wafer and exposes the first pads on the first active surface to make the first The first and second pins of the wafer and the second wafer are respectively electrically connected to opposite surfaces of the insulating layer disposed on the flexible substrate. Accordingly, the multi-wafer stack package structure of the present invention can make the single package body without increasing the integrated circuit density of the single chip and continuously reduce the contact point by the configuration of the plurality of wafers and the flexible substrate of the multi-layer pins. In the case of /pin pitch, the number of input/output terminals (I/O) can still be increased to meet the needs of high-speed, multi-function, high-resolution, high-performance electronic products.
另一方面，本發明的多晶片堆疊封裝結構的製作方法係藉由一熱壓頭使得第一引腳與第二引腳分別與第一接墊與第二接墊共晶接合而彼此電性連接。由於熱壓頭係因應可撓性基板上的引腳佈局以及晶片上的接墊佈局，而具有引腳讓位區及其相應的壓合面。據此，可於一次製程即同時接合多個晶片，可有效縮減製作時間及程序，進而降低製造成本。On the other hand, the multi-wafer stack package structure of the present invention is fabricated by electrically bonding the first pin and the second pin to the first pad and the second pad, respectively, by a thermal head. connection. Since the thermal head corresponds to the pin layout on the flexible substrate and the pad layout on the wafer, the pin-receiving area and its corresponding pressing surface are provided. According to this, a plurality of wafers can be joined at the same time in one process, which can effectively reduce the production time and the program, thereby reducing the manufacturing cost.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
20‧‧‧熱壓頭20‧‧‧Hot head
20a‧‧‧第一壓合面20a‧‧‧First press fit
20b‧‧‧第二壓合面20b‧‧‧Second press surface
20c‧‧‧引腳讓位區20c‧‧‧ pin giving area
100A、100B‧‧‧多晶片堆疊封裝結構100A, 100B‧‧‧Multi-wafer stacked package structure
101‧‧‧晶片堆疊結構101‧‧‧ wafer stack structure
110‧‧‧第一晶片110‧‧‧First chip
110a‧‧‧第一主動表面110a‧‧‧First active surface
110b‧‧‧背面110b‧‧‧Back
112‧‧‧第一接墊112‧‧‧First mat
120‧‧‧第二晶片120‧‧‧second chip
120a‧‧‧第二主動表面120a‧‧‧Second active surface
122‧‧‧第二接墊122‧‧‧second mat
130a、130b‧‧‧可撓性基板130a, 130b‧‧‧flexible substrate
131‧‧‧元件孔131‧‧‧Component hole
132、134‧‧‧絕緣層132, 134‧‧‧ insulation
132a‧‧‧第一表面132a‧‧‧ first surface
132b‧‧‧第二表面132b‧‧‧second surface
136‧‧‧第一引腳136‧‧‧First pin
138‧‧‧第二引腳138‧‧‧second pin
140‧‧‧膠層140‧‧‧ glue layer
150‧‧‧封裝膠體150‧‧‧Package colloid
160‧‧‧防焊層160‧‧‧ solder mask
圖1A是本發明的一實施例的多晶片堆疊封裝結構的剖面示意圖。1A is a cross-sectional view showing a multi-wafer stacked package structure according to an embodiment of the present invention.
圖1B是本發明另一實施例的多晶片堆疊封裝結構的局部剖示圖。1B is a partial cross-sectional view showing a multi-wafer stacked package structure according to another embodiment of the present invention.
圖2A至圖2C是圖1A的多晶片堆疊封裝結構的多個可能實施例的局部俯視圖。2A-2C are partial top views of various possible embodiments of the multi-wafer stacked package structure of FIG. 1A.
圖3A至圖3D是本發明一實施例的多晶片堆疊封裝結構的製作方法的流程剖面示意圖。3A to 3D are schematic cross-sectional views showing a process of fabricating a multi-wafer stacked package structure according to an embodiment of the present invention.
圖4是圖3C的熱壓頭的立體示意圖。Figure 4 is a perspective view of the thermal head of Figure 3C.
圖1A是本發明的一實施例的多晶片堆疊封裝結構的局部剖示圖。請參考圖1A，在本實施例中，多晶片堆疊封裝結構100A包括晶片堆疊結構101以及可撓性基板130a，其中晶片堆疊結構101包括第一晶片110與第二晶片120。第一晶片110具有第一主動表面110a以及多個配置於第一主動表面110a上的第一接墊112。第二晶片120具有第二主動表面120a以及多個配置於第二主動表面120a上的第二接墊122，其中第二晶片120堆疊於第一晶片110的第一主動表面110a上並暴露出第一接墊112。1A is a partial cross-sectional view showing a multi-wafer stacked package structure in accordance with an embodiment of the present invention. Referring to FIG. 1A, in the present embodiment, the multi-wafer stacked package structure 100A includes a wafer stack structure 101 and a flexible substrate 130a, wherein the wafer stack structure 101 includes a first wafer 110 and a second wafer 120. The first wafer 110 has a first active surface 110a and a plurality of first pads 112 disposed on the first active surface 110a. The second wafer 120 has a second active surface 120a and a plurality of second pads 122 disposed on the second active surface 120a. The second wafer 120 is stacked on the first active surface 110a of the first wafer 110 and exposed. A pad 112.
可撓性基板130a包括至少一絕緣層132、多個第一引腳136以及多個第二引腳138，其中本實施例的絕緣層係以單層結構舉例說明，但非用以限制本發明，絕緣層的層數亦可視封裝結構之線路佈局而有所調整，在以下其他實施例將進一步做說明。The flexible substrate 130a includes at least one insulating layer 132, a plurality of first leads 136, and a plurality of second leads 138. The insulating layer of the embodiment is exemplified by a single layer structure, but is not intended to limit the present invention. The number of layers of the insulating layer can also be adjusted according to the layout of the package structure, which will be further described in other embodiments below.
在本實施例中，絕緣層132具有第一表面132a與第二表面132b，第一引腳136設置於絕緣層132之第一表面132a上並與第一接墊112連接，而第二引腳138設置於絕緣層132之第二表面132b上並與第二接墊122連接。其中，可撓性基板130a之絕緣層132例如是由聚乙烯對苯二甲酸酯(polyethylene terephthalate,PET)、聚醯亞胺(Polyimide,PI)、聚醚(polyethersulfone,PES)或碳酸脂(polycarbonate,PC)等材質所製成。另一方面，第一引腳136以及第二引腳138則例如是由銅等導電金屬材質所構成。第一晶片110上之第一接墊112以及第二晶片120上之第二接墊122可以是凸塊，其材質例如是金、銅或其他導電材料。In this embodiment, the insulating layer 132 has a first surface 132a and a second surface.The first pin 136 is disposed on the first surface 132a of the insulating layer 132 and connected to the first pad 112, and the second pin 138 is disposed on the second surface 132b of the insulating layer 132 and connected to the second surface. The pads 122 are connected. The insulating layer 132 of the flexible substrate 130a is made of, for example, polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES) or carbonate ( Made of polycarbonate, PC). On the other hand, the first pin 136 and the second pin 138 are made of, for example, a conductive metal material such as copper. The first pads 112 on the first wafer 110 and the second pads 122 on the second wafer 120 may be bumps made of, for example, gold, copper or other conductive material.
詳細而言，可撓性基板130a之絕緣層132具有元件孔131用以容納晶片，其中第一晶片110與第二晶片120即位於元件孔131內。第一引腳136由絕緣層132之第一表面132a延伸至元件孔131中，而與第一接墊112電性連接。第二引腳138由絕緣層132之第二表面132b延伸至元件孔131中，而與第二接墊122電性連接。具體而言，第二引腳138之端部較第一引腳136之端部更靠近元件孔131之中心點。一般而言，第一晶片110以及第二晶片120是藉由熱壓接合技術使第一接墊112以及第二接墊122分別與第一引腳136以及第二引腳138共晶接合，來達到機械性與電性的連接。In detail, the insulating layer 132 of the flexible substrate 130a has an element hole 131 for accommodating the wafer, wherein the first wafer 110 and the second wafer 120 are located in the element hole 131. The first pin 136 extends from the first surface 132a of the insulating layer 132 into the component hole 131 to be electrically connected to the first pad 112. The second pin 138 extends from the second surface 132b of the insulating layer 132 into the component hole 131 to be electrically connected to the second pad 122. Specifically, the end of the second pin 138 is closer to the center point of the component hole 131 than the end of the first pin 136. In general, the first die 110 and the second die 120 are eutectic bonded to the first pin 136 and the second pin 138 by a thermocompression bonding technique, respectively. A mechanical and electrical connection is achieved.
如圖1A所示，第一晶片110與第二晶片120之間配置有膠層140。膠層140可以是導熱膠材，例如是由環氧樹脂(epoxy)混合氧化鋁(Al2O3)、氮化鋁(AlN)或氮化硼(BN)等填料所製成。據此，第二晶片120不但可藉由膠層140而緊密貼附於第一主動表面110a，亦可將第二晶片120上所產生的熱能透過膠層140而傳遞至第一晶片110。As shown in FIG. 1A, a glue layer 140 is disposed between the first wafer 110 and the second wafer 120. The glue layer 140 may be a thermally conductive rubber material, for example, made of an epoxy-filled alumina (Al2 O3 ), aluminum nitride (AlN) or boron nitride (BN) filler. Accordingly, the second wafer 120 can be closely attached to the first active surface 110a by the adhesive layer 140, and the thermal energy generated on the second wafer 120 can be transmitted to the first wafer 110 through the adhesive layer 140.
另一方面，元件孔131內填入有封裝膠體150。封裝膠體150包覆第一晶片110、第二晶片120、第一引腳136以及第二引腳138，以固定第一晶片110以及第二晶片120與可撓性基板130a之間的相對位置，並且保護電性接點。更詳細來說，封裝膠體150可將第一晶片110的背面110b暴露出，也因此，無論是第一晶片110所產生的熱能，亦或是第二晶片120傳遞至第一晶片110的熱能，皆可自第一晶片110的背面110b而傳遞至外界，用以提高散熱功效。On the other hand, the component hole 131 is filled with the encapsulant 150. The encapsulant 150 covers the first wafer 110, the second wafer 120, the first pin 136, and the second pin 138 to fix the relative position between the first wafer 110 and the second wafer 120 and the flexible substrate 130a. And protect the electrical contacts. In more detail, the encapsulant 150 can expose the back surface 110b of the first wafer 110, and thus, whether the thermal energy generated by the first wafer 110 or the thermal energy of the second wafer 120 is transferred to the first wafer 110, All can be transmitted from the back surface 110b of the first wafer 110 to the outside to improve the heat dissipation effect.
此外，在本實施例中，可撓性基板130a更包括防焊層160。防焊層160分別配置於絕緣層132之第一表面132a與第二表面132b上，以局部覆蓋第一引腳136與第二引腳138，用以保護第一引腳136與第二引腳138，防止第一引腳136與第二引腳138因外露被污染而短路。具體而言，第一引腳136與第二引腳138延伸至元件孔131中之部分未被防焊層160所覆蓋。Further, in the present embodiment, the flexible substrate 130a further includes a solder resist layer 160. The solder resist layer 160 is respectively disposed on the first surface 132a and the second surface 132b of the insulating layer 132 to partially cover the first pin 136 and the second pin 138 for protecting the first pin 136 and the second pin 138, preventing the first pin 136 and the second pin 138 from being short-circuited due to contamination. Specifically, a portion of the first pin 136 and the second pin 138 extending into the element hole 131 is not covered by the solder resist layer 160.
圖1B是本發明另一實施例的多晶片堆疊封裝結構的局部剖示圖。請參考圖1B，圖1B的多晶片堆疊封裝結構100B與圖1A的多晶片堆疊封裝結構100A的不同處在於：多晶片堆疊封裝結構100B的可撓性基板130b為一多層可撓性基板的結構，其具有雙層絕緣層132與134，且第一引腳136位於絕緣層132與134之間。1B is a partial cross-sectional view showing a multi-wafer stacked package structure according to another embodiment of the present invention. Referring to FIG. 1B, the multi-wafer stacked package structure 100B of FIG. 1B is different from the multi-wafer stacked package structure 100A of FIG. 1A in that the flexible substrate 130b of the multi-wafer stacked package structure 100B is a multilayer flexible substrate. Structure having double insulating layers 132 and 134, and first pin 136 is located at insulating layers 132 and 134between.
就製程上而言，可撓性基板130b例如是將第一引腳136與第二引腳138分別設置於絕緣層132之第一表面132a與第二表面132b上之後，接著將絕緣層134貼附於絕緣層132之第一表面132a上而覆蓋第一引腳136，用以支撐並保護第一引腳136。此外，在其他可能的實施例中，可撓性基板130b亦可是先將第一引腳136設置於絕緣層134上，接著將絕緣層134貼附於絕緣層132之第一表面132a上，以使第一引腳136位於絕緣層132與134之間。換言之，可撓性基板130b即是將兩個分別配置有單層線路層之絕緣層相互貼附而形成。For example, in the process, the flexible substrate 130b is disposed on the first surface 132a and the second surface 132b of the insulating layer 132, respectively, and then the insulating layer 134 is pasted. Attached to the first surface 132a of the insulating layer 132 to cover the first pin 136 for supporting and protecting the first pin 136. In addition, in other possible embodiments, the flexible substrate 130b may also be disposed on the insulating layer 134 first, and then the insulating layer 134 is attached on the first surface 132a of the insulating layer 132. The first pin 136 is positioned between the insulating layers 132 and 134. In other words, the flexible substrate 130b is formed by attaching two insulating layers each having a single-layer wiring layer to each other.
圖2A至圖2C是圖1A的多晶片堆疊封裝結構的多個可能實施例的局部俯視圖，其中為清楚表示封裝結構，圖2A至圖2C省略了封裝膠體150的繪示。請參考圖2A，在本實施例中，第二晶片120的第二主動表面120a的面積例如是小於第一晶片110的第一主動表面110a的面積，以暴露出第一接墊112。2A-2C are partial top views of various possible embodiments of the multi-wafer stacked package structure of FIG. 1A, wherein the package structure is omitted, and the illustration of the encapsulant 150 is omitted in FIGS. 2A-2C. Referring to FIG. 2A , in the embodiment, the area of the second active surface 120 a of the second wafer 120 is, for example, smaller than the area of the first active surface 110 a of the first wafer 110 to expose the first pads 112 .
第一接墊112分佈於第一主動表面110a的周邊，而第二接墊122分佈於第二主動表面120a的周邊。於本實施例中，第二引腳138分別經過第一主動表面110a之各邊的中央區域而與第二晶片120上之第二接墊122連接，第一引腳136則避開第一主動表面110a之各邊的中央區域而分別經過中央區域之兩側並與第一晶片110上之第一接墊112連接。另一方面，接墊112、122更可以多排交錯方式配置，以有效縮減引腳136、138間之間距。如此佈局下，不僅可提高單位面積上引腳與接墊的數量，亦有助於提升封裝結構的線路佈局的彈性。The first pads 112 are distributed around the periphery of the first active surface 110a, and the second pads 122 are distributed around the periphery of the second active surface 120a. In this embodiment, the second pin 138 is connected to the second pad 122 on the second wafer 120 through the central region of each side of the first active surface 110a, and the first pin 136 avoids the first active The central regions of the sides of the surface 110a pass through the sides of the central region and are connected to the first pads 112 on the first wafer 110. On the other hand, the pads 112, 122 can be arranged in a multi-row staggered manner to effectively reduce the distance between the pins 136, 138. in this wayUnder the layout, not only can the number of pins and pads per unit area be increased, but also the flexibility of the layout of the package structure can be improved.
當然，本發明並不限定於前述的第一引腳136與第二引腳138的排列方式，如圖2B所示，第一引腳136與第二引腳138例如是以彼此交錯排列方式經過第一主動表面110a之各邊而分別與第一晶片110及第二晶片120連接。Of course, the present invention is not limited to the foregoing arrangement of the first pin 136 and the second pin 138. As shown in FIG. 2B, the first pin 136 and the second pin 138 are, for example, staggered with each other. The first active surface 110a is connected to the first wafer 110 and the second wafer 120, respectively.
另一方面，如圖2C所示，第二晶片120的第二主動表面120a的面積例如是等於第一晶片110的第一主動表面110a的面積，而第一晶片110與第二晶片120係以長邊對應短邊之十字相交方式形成堆疊結構，相同地，第二晶片120堆疊於第一晶片110的第一主動表面110a上並暴露出第一接墊112。於本實施例中，第一接墊112分佈於第一主動表面110a之短邊側，第二接墊122分佈於第二主動表面120a的四邊，而第一引腳136與第二引腳138係彼此交錯排列而分別與第一晶片110及第二晶片120連接。然而，本發明並不限制第一接墊112與第二接墊122以及第一引腳136與第二引腳138之配置方式，只要在封裝結構的空間允許之下，其配置方式可依設計需求做最適當之調整。需說明的是，圖1B的多晶片堆疊封裝結構100B的俯視結構大致上與圖1A的多晶片堆疊封裝結構100A相同或相似，本發明對此不加贅述。On the other hand, as shown in FIG. 2C, the area of the second active surface 120a of the second wafer 120 is, for example, equal to the area of the first active surface 110a of the first wafer 110, and the first wafer 110 and the second wafer 120 are The long side corresponds to the intersection of the short sides to form a stacked structure. Similarly, the second wafer 120 is stacked on the first active surface 110a of the first wafer 110 and exposes the first pads 112. In this embodiment, the first pads 112 are distributed on the short sides of the first active surface 110a, and the second pads 122 are distributed on the four sides of the second active surface 120a, and the first pins 136 and the second pins 138 are disposed. They are alternately arranged to each other and connected to the first wafer 110 and the second wafer 120, respectively. However, the present invention does not limit the arrangement of the first pad 112 and the second pad 122 and the first pin 136 and the second pin 138, as long as the space of the package structure allows, the configuration can be designed. Make the most appropriate adjustments to your needs. It should be noted that the top view structure of the multi-wafer stacked package structure 100B of FIG. 1B is substantially the same as or similar to the multi-wafer stacked package structure 100A of FIG. 1A, and the present invention does not further describe this.
為進一步說明前述實施例的內容，以下將以圖1A的多晶片堆疊封裝結構100A為例，並配合圖3A至圖3D對多晶片堆疊封裝結構的製作方法進行介紹。To further illustrate the contents of the foregoing embodiments, the multi-wafer stacked package structure 100A of FIG. 1A will be taken as an example, and the multi-wafer stacking will be described with reference to FIGS. 3A to 3D.The manufacturing method of the package structure is introduced.
圖3A至圖3D是本發明一實施例的多晶片堆疊封裝結構的製作方法的流程剖面示意圖。圖4是圖3C的熱壓頭的立體示意圖。本實施例的多晶片堆疊封裝結構的製作方法包括下列步驟。3A to 3D are schematic cross-sectional views showing a process of fabricating a multi-wafer stacked package structure according to an embodiment of the present invention. Figure 4 is a perspective view of the thermal head of Figure 3C. The manufacturing method of the multi-wafer stacked package structure of this embodiment includes the following steps.
首先，如圖3A所示，提供第一晶片110，其中第一晶片110具有第一主動表面110a以及多個配置於第一主動表面110a上的第一接墊112。第一接墊112可以是凸塊，其材質例如是金、銅或其他導電材料。First, as shown in FIG. 3A, a first wafer 110 is provided, wherein the first wafer 110 has a first active surface 110a and a plurality of first pads 112 disposed on the first active surface 110a. The first pad 112 may be a bump made of a material such as gold, copper or other conductive material.
接著，如圖3B所示，將第二晶片120藉由膠層140貼附於第一晶片110的第一主動表面110a上並暴露出第一接墊112，以形成晶片堆疊結構101，其中第二晶片120具有第二主動表面120a以及多個配置於第二主動表面120a上的第二接墊122。同樣地，第二接墊122可以是凸塊，其材質例如是金、銅或其他導電材料。膠層140可以是導熱膠材，例如是由環氧樹脂(epoxy)混合氧化鋁(Al2O3)、氮化鋁(AlN)或氮化硼(BN)等填料所製成。據此，第二晶片120不但可藉由膠層140而緊密貼附於第一主動表面110a上，亦可將第二晶片120所產生的熱能透過膠層140而傳遞至第一晶片110。Next, as shown in FIG. 3B, the second wafer 120 is attached to the first active surface 110a of the first wafer 110 by the adhesive layer 140 and exposes the first pads 112 to form a wafer stack structure 101, wherein The two wafers 120 have a second active surface 120a and a plurality of second pads 122 disposed on the second active surface 120a. Similarly, the second pad 122 may be a bump made of a material such as gold, copper or other conductive material. The glue layer 140 may be a thermally conductive rubber material, for example, made of an epoxy-filled alumina (Al2 O3 ), aluminum nitride (AlN) or boron nitride (BN) filler. Accordingly, the second wafer 120 can be closely attached to the first active surface 110a by the adhesive layer 140, and the thermal energy generated by the second wafer 120 can be transmitted to the first wafer 110 through the adhesive layer 140.
之後，如圖3C所示，提供一可撓性基板130a，其中可撓性基板130a包括絕緣層132、多個第一引腳136以及多個第二引腳138。絕緣層132具有第一表面132a與第二表面132b，第一引腳136設置於絕緣層132之第一表面132a上並延伸至元件孔131中，而第二引腳138設置於絕緣層132之第二表面132b上並延伸至元件孔131中。可撓性基板130a更包括防焊層160，防焊層160分別配置於絕緣層132之第一表面132a與第二表面132b上，以局部覆蓋第一引腳136與第二引腳138。具體而言，第一引腳136與第二引腳138延伸至元件孔131中之部分未被防焊層160所覆蓋。接著，將晶片堆疊結構101對位於絕緣層132的元件孔131，並藉由熱壓頭20加熱加壓使第一引腳136與第二引腳138分別與第一接墊112與第二接墊122彼此共晶接合，來達到機械性與電性的連接。具體而言，第二引腳138之端部較第一引腳136之端部更靠近元件孔131之中心點。Thereafter, as shown in FIG. 3C, a flexible substrate 130a is provided, wherein the flexible substrate 130a includes an insulating layer 132, a plurality of first leads 136, and a plurality of second leads 138. The insulating layer 132 has a first surface 132a and a second surface 132b. The first pin 136 is disposed on the first surface 132a of the insulating layer 132 and extends to the component hole.In the 131, the second pin 138 is disposed on the second surface 132b of the insulating layer 132 and extends into the element hole 131. The flexible substrate 130a further includes a solder resist layer 160 disposed on the first surface 132a and the second surface 132b of the insulating layer 132 to partially cover the first pin 136 and the second pin 138. Specifically, a portion of the first pin 136 and the second pin 138 extending into the element hole 131 is not covered by the solder resist layer 160. Next, the wafer stack structure 101 is disposed on the component hole 131 of the insulating layer 132, and is heated and pressurized by the thermal head 20 to make the first pin 136 and the second pin 138 respectively connect with the first pad 112 and the second pad. The pads 122 are eutectic bonded to each other to achieve a mechanical and electrical connection. Specifically, the end of the second pin 138 is closer to the center point of the component hole 131 than the end of the first pin 136.
在本實施例中，可撓性基板130a之絕緣層132例如是由聚乙烯對苯二甲酸酯(polyethylene terephthalate,PET)、聚醯亞胺(Polyimide,PI)、聚醚(polyethersulfone,PES)或碳酸脂(polycarbonate,PC)等材質所製成。另一方面，第一引腳136以及第二引腳138則例如是由銅所構成。第一晶片110上之第一接墊112以及第二晶片120上之第二接墊122可以是凸塊，其材質例如是金、銅或其他導電材料。In this embodiment, the insulating layer 132 of the flexible substrate 130a is made of, for example, polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES). Or made of polycarbonate (PC) and other materials. On the other hand, the first pin 136 and the second pin 138 are made of, for example, copper. The first pads 112 on the first wafer 110 and the second pads 122 on the second wafer 120 may be bumps made of, for example, gold, copper or other conductive material.
更詳細而言，熱壓頭20具有第一壓合面20a與第二壓合面20b，藉由下壓熱壓頭20可使得第一壓合面20a與第二壓合面20b分別抵接第一引腳136以及第二引腳138，並使得第一引腳136與第二引腳138分別與第一接墊112與第二接墊122共晶接合而彼此電性連接。其中，第一壓合面20a與第二壓合面20b是位於不同平面上，且熱壓頭20的第二壓合面20b的面積大於第二主動表面120a的面積，以令在下壓熱壓頭20的過程中，可使得第二晶片120容置於熱壓頭20內。More specifically, the thermal head 20 has a first pressing surface 20a and a second pressing surface 20b, and the first pressing surface 20a and the second pressing surface 20b are respectively abutted by pressing the thermal head 20 The first pin 136 and the second pin 138 are electrically connected to each other by bonding the first pin 136 and the second pin 138 to the first pad 112 and the second pad 122, respectively. Wherein, the first pressing surface 20a and the second pressing surface 20b are locatedOn the different planes, the area of the second pressing surface 20b of the thermal head 20 is larger than the area of the second active surface 120a, so that the second wafer 120 can be placed in the hot pressing during the pressing of the thermal head 20. Within the first 20 years.
在執行完上述步驟，如圖3D所示，於元件孔131內填入封裝膠體150，且封裝膠體150包覆第一晶片110、第二晶片120、第一引腳136以及第二引腳138。更詳細來說，封裝膠體150可將第一晶片110的背面110b暴露出，也因此，無論是第一晶片110所產生的熱能，亦或是第二晶片120傳遞至第一晶片110的熱能，皆可自第一晶片110的背面110b而傳遞至外界，用以提高散熱功效。最後，藉由熱固化或光固化的方式固化封裝膠體150，以固定第一晶片110以及第二晶片120與可撓性基板130a之間的相對位置。至此，多晶片堆疊封裝結構100A的製作已大致完成。After the above steps are performed, as shown in FIG. 3D, the encapsulant 150 is filled in the component hole 131, and the encapsulant 150 covers the first wafer 110, the second wafer 120, the first pin 136, and the second pin 138. . In more detail, the encapsulant 150 can expose the back surface 110b of the first wafer 110, and thus, whether the thermal energy generated by the first wafer 110 or the thermal energy of the second wafer 120 is transferred to the first wafer 110, All can be transmitted from the back surface 110b of the first wafer 110 to the outside to improve the heat dissipation effect. Finally, the encapsulant 150 is cured by heat curing or photocuring to fix the relative position between the first wafer 110 and the second wafer 120 and the flexible substrate 130a. So far, the fabrication of the multi-wafer stacked package structure 100A has been substantially completed.
另一方面，如圖4所示，熱壓頭20具有多個引腳讓位區20c，以令在下壓熱壓頭20的過程中，熱壓頭20藉由引腳讓位區20c避開第二引腳138，使得第一壓合面20a與第二壓合面20b分別抵接第一引腳136以及第二引腳138。據此，有效避免在下壓熱壓頭20的過程中，造成第一引腳136與第二引腳138的損毀，以大幅提高製程良率。On the other hand, as shown in FIG. 4, the thermal head 20 has a plurality of pin yielding regions 20c so that the thermal head 20 is avoided by the pin letting region 20c during the pressing of the thermal head 20. The second pin 138 is such that the first pressing surface 20a and the second pressing surface 20b abut the first pin 136 and the second pin 138, respectively. Accordingly, the first pin 136 and the second pin 138 are damaged during the process of pressing the thermal head 20 to greatly improve the process yield.
綜上所述，本發明的多晶片堆疊封裝結構包括晶片堆疊結構以及具有多層引腳之可撓性基板，其中晶片堆疊結構之第二晶片配置於第一晶片的第一主動表面上，並暴露出第一主動表面上的第一接墊，以使第一晶片與第二晶片分別與配置於可撓性基板之絕緣層的相對二表面上的第一引腳與第二引腳電性連接。據此，本發明之多晶片堆疊封裝結構可藉由多個晶片的配置以及多層引腳之可撓性基板，使單一封裝體在不需增加單顆晶片之積體電路密度與持續縮減接點/引腳間距之情況下，仍可增加輸出入端點(I/O)的數量，以因應電子產品高速、多功能、高解析度、高效能等需求。In summary, the multi-wafer stacked package structure of the present invention includes a wafer stack structure and a flexible substrate having a plurality of pins, wherein the second wafer of the wafer stack structure is disposed on the first active surface of the first wafer and exposed a first pad on the first active surface such that the first wafer and the second wafer are respectively disposed on the flexible baseThe first pin on the opposite surfaces of the insulating layer of the board is electrically connected to the second pin. Accordingly, the multi-wafer stack package structure of the present invention can make the single package body without increasing the integrated circuit density of the single chip and continuously reduce the contact point by the configuration of the plurality of wafers and the flexible substrate of the multi-layer pins. In the case of /pin pitch, the number of input/output terminals (I/O) can still be increased to meet the needs of high-speed, multi-function, high-resolution, high-performance electronic products.
另一方面，本發明的多晶片堆疊封裝結構的製作方法係藉由一熱壓頭使得第一引腳與第二引腳分別與第一晶片之第一接墊與第二晶片之第二接墊共晶接合而彼此電性連接。由於熱壓頭係因應可撓性基板上的引腳佈局以及晶片上的接墊佈局，而具有引腳讓位區及其相應的壓合面。據此，可於一次製程即同時接合多個晶片，可有效縮減製作時間及程序，進而降低製造成本。In another aspect, the multi-wafer stacked package structure of the present invention is formed by a thermal head such that the first pin and the second pin are respectively connected to the first pad of the first chip and the second chip. The pads are eutectic bonded and electrically connected to each other. Since the thermal head corresponds to the pin layout on the flexible substrate and the pad layout on the wafer, the pin-receiving area and its corresponding pressing surface are provided. According to this, a plurality of wafers can be joined at the same time in one process, which can effectively reduce the production time and the program, thereby reducing the manufacturing cost.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100A‧‧‧多晶片堆疊封裝結構100A‧‧‧Multi-wafer stacked package structure
101‧‧‧晶片堆疊結構101‧‧‧ wafer stack structure
110‧‧‧第一晶片110‧‧‧First chip
110a‧‧‧第一主動表面110a‧‧‧First active surface
110b‧‧‧背面110b‧‧‧Back
112‧‧‧第一接墊112‧‧‧First mat
120‧‧‧第二晶片120‧‧‧second chip
120a‧‧‧第二主動表面120a‧‧‧Second active surface
122‧‧‧第二接墊122‧‧‧second mat
130a‧‧‧可撓性基板130a‧‧‧Flexible substrate
131‧‧‧元件孔131‧‧‧Component hole
132‧‧‧絕緣層132‧‧‧Insulation
132a‧‧‧第一表面132a‧‧‧ first surface
132b‧‧‧第二表面132b‧‧‧second surface
136‧‧‧第一引腳136‧‧‧First pin
138‧‧‧第二引腳138‧‧‧second pin
140‧‧‧膠層140‧‧‧ glue layer
150‧‧‧封裝膠體150‧‧‧Package colloid
160‧‧‧防焊層160‧‧‧ solder mask
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102135400ATWI515865B (en) | 2013-09-30 | 2013-09-30 | Multi-chip stack package structure and fabrication method thereof |
| CN201310740186.XACN104517924B (en) | 2013-09-30 | 2013-12-30 | Multi-chip stacking packaging structure and manufacturing method thereof |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102135400ATWI515865B (en) | 2013-09-30 | 2013-09-30 | Multi-chip stack package structure and fabrication method thereof |
| Publication Number | Publication Date |
|---|---|
| TW201513296A TW201513296A (en) | 2015-04-01 |
| TWI515865Btrue TWI515865B (en) | 2016-01-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102135400ATWI515865B (en) | 2013-09-30 | 2013-09-30 | Multi-chip stack package structure and fabrication method thereof |
| Country | Link |
|---|---|
| CN (1) | CN104517924B (en) |
| TW (1) | TWI515865B (en) |
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| TWI871069B (en)* | 2023-11-01 | 2025-01-21 | 財團法人工業技術研究院 | Multi-die integrated package design method and system using the same |
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| CN104517924A (en) | 2015-04-15 |
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