本發明涉及到可編程記憶體元件，如使用在記憶體陣列之可編程電阻元件。The present invention relates to programmable memory components, such as programmable resistive elements for use in a memory array.
可編程電阻元件通常是指元件之電阻狀態可在編程後改變。電阻狀態可以由電阻值來決定。例如，電阻性元件可以是單次性可編程OTP(One-Time Programmable)元件(如電性熔絲)，而編程方法可以施用高電壓，來產生高電流通過OTP元件。當這大電流經由打開的編程選擇器流過OTP元件，OTP元件將被燒成高或低電阻狀態(取決於是熔絲或反熔絲)而加以編程。A programmable resistive element generally means that the resistive state of the component can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element can be a one-time programmable OTP (One-Time Programmable) element (such as an electrical fuse), and the programming method can apply a high voltage to generate a high current through the OTP element. When this large current flows through the OTP component via the open programming selector, the OTP component will be programmed to be fired in a high or low resistance state (depending on whether it is a fuse or an antifuse).
電性熔絲是一種常見的OTP，而這種可編程電阻元件，可以是多晶矽，矽化多晶矽，矽化物，熱隔離的主動區，金屬，金屬合金或它們的組合。金屬可以是鋁，銅或其他過渡金屬。其中最常用的電性熔絲是矽化的多晶矽，用互補式金氧半導體晶體管(CMOS)的閘極製成，用來作為內連接(interconnect)。電性熔絲也可以是一個或多個接點(contact)或層間接點(via)，而不是小片段的內連接。高電流可把接點或層間接點燒成高電阻狀態。電性熔絲可以是反熔絲，其中高電壓使電阻降低，而不是提高電阻。反熔絲可由一個或多個接點或層間接點組成，並含有絕緣體於其間。反熔絲也可由CMOS閘極耦合於CMOS本體，其含有閘極氧化層當做為絕緣體。Electrical fuses are a common type of OTP, and such programmable resistive elements can be polycrystalline germanium, germanium polysilicon, germanium, thermally isolated active regions, metals, metal alloys or combinations thereof. The metal can be aluminum, copper or other transition metal. The most commonly used electrical fuse is a deuterated polysilicon, made of a gate of a complementary MOS transistor (CMOS), used as an interconnect. The electrical fuse can also be one or more contacts or layer invias, rather than an internal connection of small segments. High current can burn contacts or layers indirectly to a high resistance state. Electrical fuseIt can be an anti-fuse, where a high voltage reduces the resistance rather than increasing the resistance. The antifuse may be composed of one or more contacts or layer indirect points and has an insulator therebetween. The antifuse can also be coupled to the CMOS body by a CMOS gate that contains a gate oxide layer as an insulator.
一種傳統的可編程電阻式記憶存儲單元如第一圖所示。存儲單元10包含電阻元件11和N型金氧半導體晶體管(NMOS)編程選擇器12。電阻元件11一端耦合到NMOS的汲極，另一端耦合到正電壓V+。NMOS12的閘極耦合到選擇信號(SEL)，源極耦合到負電壓V-。當高電壓加在V+而低電壓加在V-時，電阻元件10則可被編程，經由提高編程選擇信號(SEL)來打開NMOS12。一種最常見的電阻元件是矽化多晶矽，乃是在同時製作MOS閘極時用的同樣材料。NMOS編程選擇器12的面積，需要足夠大，以提供所需的編程電流持續幾微秒。矽化多晶矽的編程電流通常是從幾毫安(對寬度約40奈米的熔絲)至20毫安(對寬度約0.6微米熔絲)。因此使用矽化多晶矽的電性熔絲存儲單元面積往往是非常大的。A conventional programmable resistive memory storage unit is shown in the first figure. The memory cell 10 includes a resistive element 11 and an N-type MOS transistor (NMOS) programming selector 12. The resistive element 11 is coupled at one end to the drain of the NMOS and at the other end to a positive voltage V+. The gate of NMOS 12 is coupled to a select signal (SEL) and the source is coupled to a negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the resistive element 10 can be programmed to turn on the NMOS 12 by increasing the program select signal (SEL). One of the most common resistive components is deuterated polysilicon, which is the same material used in the fabrication of MOS gates at the same time. The area of the NMOS programming selector 12 needs to be large enough to provide the required programming current for a few microseconds. The programming current for deuterated polysilicon is typically from a few milliamps (for a fuse of about 40 nanometers in width) to 20 milliamps (for a fuse of about 0.6 micrometers in width). Therefore, the area of the electrical fuse storage unit using the deuterated polysilicon is often very large.
可編程電阻元件可以是可逆的電阻元件，可以重複編程且可逆編程成數位邏輯值“0”或“1”。可編程電阻元件可從相變材料來製造，如鍺(Ge)，銻(Sb)，碲(Te)的組成Ge2Sb2Te5(GST-225)或包括成分銦(In)，錫(Sn)或硒(Se)的GeSbTe類材料。經由高電壓短脈衝或低電壓長脈衝，相變材料可被編程成非晶體態高電阻狀態或結晶態低電阻狀態。可逆電阻元件可以是電阻式隨機存取記憶體(電阻式記憶體RRAM)，存儲單元由在金屬或金屬合金電極之間的金屬氧化物，如鉑/氧化鎳/鉑(Pt/NiO/Pt)，氮化鈦/氧化鋅/氧化鉿/氮化鈦(TiN/TiOx/HfO2/TiN)製成。該電阻狀態可逆性的改變是經由電壓或電流脈衝的極性，強度，持續時間，產生或消滅導電細絲。另一種類似電阻式隨機存取記憶體(RRAM)的可編程電阻元件，就是導電橋隨機存取記憶體(CBRAM)。此記憶體是基於電化學沉積和移除在金屬或金屬合金電極之間的固態電解質薄膜裏的金屬離子。電極可以是一個可氧化陽極和惰性陰極，而且電解質可以是摻銀或銅的硫系玻璃如硒化鍺(GeSe)或硒化硫(GeS)等。該電阻狀態可逆性的改變是經由電壓或電流脈衝的極性，強度，持續時間，產生或消滅導電橋。The programmable resistive element can be a reversible resistive element that can be reprogrammed and reversibly programmable to a digital logic value of "0" or "1". Programmable resistive elements can be fabricated from phase change materials such as germanium (Ge), germanium (Sb), germanium (Te), Ge2Sb2Te5 (GST-225) or include indium (In), tin (Sn) or selenium ( Se) GeSbTe type material. The phase change material can be programmed to an amorphous high resistance state or a crystalline low resistance state via a high voltage short pulse or a low voltage long pulse. The reversible resistance element may be a resistive random access memory (resistive memory RRAM), and the memory unit is made of a metal oxide between metal or metal alloy electrodes, such as platinum/nickel oxide/platinum (Pt/NiO/Pt). , titanium nitride / zinc oxide / yttria / titanium nitride(TiN/TiOx/HfO2/TiN). The reversible change in resistance state is the generation or elimination of conductive filaments via the polarity, intensity, duration of the voltage or current pulse. Another programmable resistive element like Resistive Random Access Memory (RRAM) is Conductive Bridge Random Access Memory (CBRAM). This memory is based on electrochemical deposition and removal of metal ions in a solid electrolyte film between metal or metal alloy electrodes. The electrode may be an oxidizable anode and an inert cathode, and the electrolyte may be a silver- or copper-containing chalcogenide glass such as strontium selenide (GeSe) or selenium sulphide (GeS). The reversible change in resistance state is the generation or elimination of the conductive bridge via the polarity, intensity, duration of the voltage or current pulse.
如第二圖a所示，相變記憶體(PCM)是另一種傳統的可編程電阻元件20。PCM存儲單元包含相變薄膜(Phase Change Material)21和當作編程選擇器的雙極性電晶體22，其具有P+射極23、N型基極27和集極25(為P型基體)。相變薄膜21一端耦合到雙極性電晶體22的射極23，另一端耦合到正電壓V+。雙極性電晶體22的N型基極27耦合到負電壓V-，而集極25耦合到接地。在V+和V-間施加適當的電壓持續適當的時間，相變薄膜21可被編程成高或低電阻狀態，根據電壓和持續時間而定。按照慣例，編程相變記憶體成高電阻狀態(或重設狀態)大約需要持續50ns的3V電壓，消耗大約300uA的電流。編程相變記憶體成低電阻狀態(或設置狀態)需要持續300ns左右的2V電壓，消耗大約100uA的電流。As shown in the second diagram a, phase change memory (PCM) is another conventional programmable resistive element 20. The PCM memory cell includes a phase change material 21 and a bipolar transistor 22 as a program selector having a P+ emitter 23, an N-type base 27, and a collector 25 (which is a P-type substrate). The phase change film 21 is coupled at one end to the emitter 23 of the bipolar transistor 22 and at the other end to a positive voltage V+. The N-type base 27 of the bipolar transistor 22 is coupled to a negative voltage V- and the collector 25 is coupled to ground. Applying the appropriate voltage between V+ and V- for a suitable period of time, the phase change film 21 can be programmed to a high or low resistance state, depending on voltage and duration. Conventionally, programming a phase change memory into a high resistance state (or reset state) requires approximately 3 volts of 50 ns and consumes approximately 300 uA. Programming the phase change memory into a low-resistance state (or set state) requires a 2V voltage of approximately 300ns and consumes approximately 100uA of current.
另一種相變記憶體(PCM)的可編程電阻元件如第二圖b所示。相變記憶體材料有相變薄膜21'和一二極體22'。相變薄膜21'被耦合在二極體陽極22'和正電壓V+之間。二極體的陰極22'被耦合到負電壓V-。施加適當的電壓在V+和V-之間持續一段適當的時間，相變薄膜21'可以被編程為高或低電阻狀態，根據電壓和持續時間而定。請見“Kwang-Jin Lee et al.,“A90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput,”International Solid-State Circuit Conference,2007,pp.472-273。第二圖b所示為使用一個二極體作為每一個相變記憶體(PCM)存儲單元的編程選擇器的例子。雖然這項技術可以減少PCM存儲單元尺寸到只有6.8F2(F代表特徵大小)，二極體需要非常複雜的製造過程，如選擇性磊晶成長(SEG)。如此一來對嵌入式PCM的應用，將變的非常昂貴。Another phase change memory (PCM) programmable resistive element is shown in Figure 2b. The phase change memory material has a phase change film 21' and a diode 22'. The phase change film 21' is coupled between the diode anode 22' and the positive voltage V+. The cathode 22' of the diode is coupled to a negative voltage V-. Applying the appropriate voltage between V+ and V- for an appropriate period of time, the phase change film 21' can be programmed to a high or low resistance state, depending on voltage and duration. See "Kwang-Jin Lee et al., "A90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," International Solid-State Circuit Conference, 2007, pp. 472-273. Figure 2b shows Use a diode as an example of a programming selector for each phase change memory (PCM) memory cell. Although this technique can reduce the PCM memory cell size to only 6.8F2 (F stands for feature size), the diode needs Very complex manufacturing processes, such as selective epitaxial growth (SEG), will make the application of embedded PCM very expensive.
第二圖c顯示了一種傳統雙極性電晶體22的截面圖。雙極性電晶體22包括P+主動區(active region)23、N淺井24、N+主動區27、P型基體25和用來隔離元件的淺溝槽隔離(STI)26。P+主動區23和N+主動區27耦合到N井24，且為雙極性電晶體22裏射極和基極二極體的P和N端，而P型基體25是雙極性電晶體22的集極。這種存儲單元需要N淺井24比淺溝槽隔離26淺，來妥善隔離每個存儲單元，因而需要比標準CMOS邏輯制程多3-4道光罩，而使得它的製作比較昂貴。A second diagram c shows a cross-sectional view of a conventional bipolar transistor 22. The bipolar transistor 22 includes a P+ active region 23, an N shallow well 24, an N+ active region 27, a P-type substrate 25, and a shallow trench isolation (STI) 26 for isolating components. P+ active region 23 and N+ active region 27 are coupled to N-well 24 and are the P and N terminals of the emitter and base diodes of bipolar transistor 22, while P-type substrate 25 is a set of bipolar transistors 22. pole. Such a memory cell requires N shallow wells 24 to be shallower than shallow trench isolations 26 to properly isolate each memory cell, thus requiring 3-4 more photomasks than standard CMOS logic processes, making it more expensive to fabricate.
二極體也可以從多晶矽製造。第三圖顯示一多晶矽二極體的橫截面。要形成多晶矽二極體，多晶矽是由N+植入一端而P+植入另一端，二端之間的間距Lc含有固有(intrinsic)的摻雜劑。固有的摻雜劑是由外擴散或污染所造成之些微N型或P型摻雜劑，而非刻意的摻雜。矽化物阻擋層應用於多晶矽上以防止矽化物在多晶矽的表面上形成，從而防止短路。多晶矽的P+和N+兩端由接點帶出以形成二極體的PN兩端。作為一例子，多晶矽二極體可見Ming-Dou Ker et al.,“Ultra High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes with Polysilicon Diodes,”IEEE Transaction of Circuit and System-II,Vol.54,No.1,January 2007,pp.47-51。The diode can also be fabricated from polycrystalline germanium. The third figure shows the cross section of a polycrystalline germanium diode. To form a polycrystalline germanium diode, the polycrystalline germanium is implanted with one end by N+ and P+ implanted with the other end, and the spacing Lc between the two ends contains an intrinsic dopant. Intrinsic dopants are micro N-type or P-type dopants caused by out-diffusion or contamination, rather than deliberate doping. A telluride barrier layer is applied to the polysilicon to prevent the formation of germanide on the surface of the polysilicon to prevent short circuits. Both ends of P+ and N+ of the polysilicon are brought out by contacts to form both ends of the PN of the diode. As an example, polycrystalline germanium diodes are visibleMing-Dou Ker et al., "Ultra High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes with Polysilicon Diodes," IEEE Transaction of Circuit and System-II, Vol. 54, No. 1, January 2007, pp. 47-51.
第四圖顯示第三圖的多晶矽二極體的電流電壓特性。目前的電流電壓曲線顯示有用的二極體行為，如二極體的閾值電壓約為0.6V而漏電流低於1nA。經由改變間距Lc，多晶矽二極體的擊穿電壓和漏電流可以相應調整。The fourth graph shows the current-voltage characteristics of the polycrystalline germanium diode of the third graph. Current current-voltage curves show useful diode behavior, such as a diode with a threshold voltage of about 0.6V and a leakage current of less than 1nA. By changing the pitch Lc, the breakdown voltage and leakage current of the polysilicon diode can be adjusted accordingly.
這項專利是關於使用二極體作為編程選擇器的可編程電阻元件存儲單元之實施例。可編程的電阻元件可以使用標準CM0S邏輯製程，以減少存儲單元的大小和成本。This patent is an embodiment of a programmable resistive element memory cell that uses a diode as a programming selector. Programmable resistive components can use standard CMOS logic to reduce memory cell size and cost.
因此本發明提供一種可逆性可編程電阻式記憶體，包括：多個可逆性可編程電阻式存儲單元，至少有一可逆性可編程電阻式存儲單元包括：一可逆性可編程電阻式元件耦合到第一電源電壓線；及一二極體建構於多晶矽上，包括至少一第一端和一第二端，其中該第一端具有一第一型摻雜，該第二端具有一第二型的摻雜，該第一端提供了該二極體的一第一端，該第二端提供二極體的一第二端，該第一端和第二端皆存在一共同的多晶矽上，該第一端被耦合到該可逆性可編程電阻式元件，而該第二端被耦合到第二電源電壓線；其中第一和第二端的摻雜劑是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造，其中，經由施加電壓到該第一和第二電源電壓線，該可逆性可編程電阻式元件被配置為可編程，從而改變電阻為不同的邏輯狀態。Therefore, the present invention provides a reversible programmable resistive memory, comprising: a plurality of reversible programmable resistive memory cells, at least one reversible programmable resistive memory cell comprising: a reversible programmable resistive component coupled to a power supply voltage line; and a diode is formed on the polysilicon, including at least a first end and a second end, wherein the first end has a first type doping, and the second end has a second type Doping, the first end provides a first end of the diode, the second end provides a second end of the diode, and the first end and the second end both have a common polysilicon A first end is coupled to the reversible programmable resistive element and the second end is coupled to a second supply voltage line; wherein the dopants of the first and second ends are from a complementary metal oxide semiconductor (CMOS) device a source or drain doped implant fabrication, wherein the reversible programmable resistive element is configured to be programmable by applying a voltage to the first and second supply voltage lines, thereby changing the resistance to a different logic status.
本發明提供一種相變記憶體，包括：多個相變存儲單元，至少有一相變存儲單元包括：一相變薄膜耦合到第一電源電壓線；及一二極體包括至少一第一端和一第二端，其中該第一端具有一第一型摻雜，該第二端具有一第二型摻雜，該第一端提供了該二極體的一第一端而該第二端提供該二極體的一第二端，該第一端和第二端皆存在一個共同的多晶矽上，該第一端耦合到相變薄膜，而該第二端耦合到第二電源電壓線；其中該第一和第二端的摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造，其中，經由施加電壓到第一和第二電源電壓線，相變薄膜被配置為可編程，從而可逆的改變電阻為不同的邏輯狀態。The present invention provides a phase change memory comprising: a plurality of phase change memory cells, at least one phase change memory cell comprising: a phase change film coupled to the first supply voltage line; and a diode comprising at least a first end and a second end, wherein the first end has a first type doping, the second end has a second type doping, the first end provides a first end of the diode and the second end Providing a second end of the diode, wherein the first end and the second end each have a common polysilicon, the first end is coupled to the phase change film, and the second end is coupled to the second power voltage line; Wherein the doping of the first and second ends is fabricated from a doped implant of a source or a drain of a complementary metal oxide semiconductor (CMOS) device, wherein the voltage is applied to the first and second supply voltage lines, The variable film is configured to be programmable, thereby reversibly changing the resistance to different logic states.
本發明提供一種電子系統，包括：一種處理器；及一可逆性可編程電阻式記憶體可操作地連接到處理器，該可逆性可編程電阻式記憶體包括至少數個可逆性可編程電阻存儲單元來提供數據存儲，每個可逆性可編程電阻存儲單元包括：一可逆性可編程電阻元件被耦合到第一電源電壓線；及一二極體包含至少一第一端和一第二端，其中該第一端具有第一型摻雜，而該第二端具有第二型摻雜，該第一端提供了二極體的一第一端，該第二端提供二極體的一第二端，該第一和第二端皆存在一個共同的多晶矽上，該第一端耦合到該可逆性可編程電阻元件而該第二端耦合到一第二電源電壓線；其中該第一和第二端的摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造；其中，經由施加電壓到第一和第二電源電壓線，可逆性可編程電阻元件被配置為可編程，從而可逆的改變電阻到不同的邏輯狀態。The present invention provides an electronic system comprising: a processor; and a reversible programmable resistive memory operatively coupled to the processor, the reversible programmable resistive memory comprising at least a plurality of reversible programmable resistive memories a unit for providing data storage, each reversible programmable resistance memory unit comprising: a reversible programmable resistance element coupled to the first supply voltage line; and a diode comprising at least a first end and a second end Wherein the first end has a first type doping and the second end has a second type doping, the first end provides a first end of the diode, and the second end provides a second of the diode a second end, the first and second ends each having a common polysilicon, the first end coupled to the reversible programmable resistive element and the second end coupled to a second supply voltage line; wherein the first sum The doping of the second end is fabricated from a doped implant of a source or a drain of a complementary metal oxide semiconductor (CMOS) device; wherein the reversible programmable resistive element is via application of a voltage to the first and second supply voltage lines Is configured to be Cheng, thereby reversibly changing the resistance to a different logic state.
本發明提供一種方法來提供一個可逆性電阻式記憶體，包括：提供多個可逆性可編程電阻存儲單元，至少有一可逆性可編程電阻存儲單元包括至少(i)一可逆性可編程電阻元件被耦合到第一電源電壓線；及(ii)一二極體包含至少一第一端和一第二端，該第一端具有第一型摻雜，而該第二端具有第二型摻雜，該第一端提供了該二極體的一第一端，該第二端提供該二極體的一第二端，該第一和第二端皆存在一個共同的多晶矽上，而其摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造，該第一端耦合到電阻元件而該第二端耦合到一第二電源電壓線；及經由施加電壓到第一和第二電壓線，來編程至少一可逆性可編程電阻存儲單元到一邏輯狀態。The present invention provides a method for providing a reversible resistive memory, including:Providing a plurality of reversible programmable resistance memory cells, at least one reversible programmable resistance memory cell comprising at least (i) a reversible programmable resistance element coupled to the first supply voltage line; and (ii) a diode comprising At least a first end and a second end, the first end having a first type doping and the second end having a second type doping, the first end providing a first end of the diode The second end provides a second end of the diode, and the first and second ends each have a common polysilicon, and the doping is from a source or a cathode of a complementary metal oxide semiconductor (CMOS) device. a pole doped implant fabrication, the first end being coupled to the resistive element and the second end coupled to a second supply voltage line; and programming at least one reversible via applying a voltage to the first and second voltage lines Program the resistor storage unit to a logic state.
10‧‧‧存儲單元10‧‧‧ storage unit
11‧‧‧電阻元件11‧‧‧Resistive components
12‧‧‧NMOS編程選擇器12‧‧‧ NMOS programming selector
21‧‧‧相變薄膜21‧‧‧ phase change film
20,20’‧‧‧可編程電阻元件20,20'‧‧‧Programmable Resistive Components
22‧‧‧雙極性電晶體22‧‧‧Bipolar transistor
23‧‧‧P+射極23‧‧‧P+ emitter
27‧‧‧N型基極27‧‧‧N type base
25‧‧‧集極25‧‧‧
22'‧‧‧二極體22'‧‧‧ Diode
23‧‧‧P+主動區23‧‧‧P+ active zone
24‧‧‧N淺井24‧‧‧N shallow well
27‧‧‧N+主動區27‧‧‧N+ Active Area
25‧‧‧P型基體25‧‧‧P type substrate
26‧‧‧淺溝槽隔離26‧‧‧Shallow trench isolation
30‧‧‧存儲單元30‧‧‧storage unit
31‧‧‧可逆性可編程電阻元件31‧‧‧Reversible programmable resistance element
32‧‧‧多晶矽二極體32‧‧‧ Polycrystalline germanium diode
34‧‧‧多晶矽34‧‧‧Polysilicon
33‧‧‧P+植入層33‧‧‧P+ implant layer
37‧‧‧N+植入層37‧‧‧N+ implant layer
d‧‧‧距離D‧‧‧distance
36‧‧‧矽化物阻擋層36‧‧‧ Telluride barrier
39‧‧‧選項層39‧‧‧ option layer
50‧‧‧可逆性可編程電阻元件存儲單元50‧‧‧Reversible programmable resistive element memory unit
42‧‧‧電阻元件42‧‧‧Resistive components
41,43‧‧‧緩衝金屬41,43‧‧‧buffer metal
30‧‧‧多晶矽二極體30‧‧‧ Polycrystalline germanium diode
42‧‧‧薄膜42‧‧‧film
40-1,40-2,40-3‧‧‧接點填塞物40-1, 40-2, 40-3‧‧‧Contact plugs
32‧‧‧陽極接點32‧‧‧Anode contacts
39‧‧‧陰極接點39‧‧‧Cathode contacts
35‧‧‧矽化物阻擋層35‧‧‧ Telluride barrier
49‧‧‧介電質49‧‧‧Dielectric
44‧‧‧金屬44‧‧‧Metal
70‧‧‧邊界為70‧‧‧ border is
71‧‧‧多晶矽二極體71‧‧‧ Polycrystalline germanium diode
75‧‧‧相變材料元件75‧‧‧ Phase change material components
73‧‧‧P+植入層73‧‧‧P+ implant layer
77‧‧‧N+植入層77‧‧‧N+ implant layer
72‧‧‧陽極72‧‧‧Anode
79‧‧‧陰極79‧‧‧ cathode
80‧‧‧矽化物阻擋層80‧‧‧ Telluride barrier
78‧‧‧位元線78‧‧‧ bit line
77‧‧‧字元線77‧‧‧ character line
76‧‧‧第一層金屬(metal1)76‧‧‧First metal (metal1)
100‧‧‧可編程電阻記憶體100‧‧‧Programmable Resistor Memory
101‧‧‧陣列101‧‧‧Array
110‧‧‧記憶體存儲單元110‧‧‧ memory storage unit
111‧‧‧電阻元件111‧‧‧Resistive components
112‧‧‧二極體112‧‧‧ diode
150-i‧‧‧字元線驅動器150-i‧‧‧ character line driver
BLR0175-0‧‧‧參考位元線BLR0175-0‧‧‧ reference bit line
WLBi152-i‧‧‧字元線WLBi152-i‧‧‧ character line
172-i‧‧‧後解碼器172-i‧‧‧After decoder
LWLBi‧‧‧局部字元線LWLBi‧‧‧local word line
vddi‧‧‧電源電壓Vddi‧‧‧Power supply voltage
120-j,125‧‧‧Y-write通道閘120-j, 125‧‧‧Y-write channel gate
130-j,135‧‧‧Y-read通道閘130-j, 135‧‧‧Y-read channel gate
S700-S760,S800-S870‧‧‧步驟S700-S760, S800-S870‧‧‧ steps
700‧‧‧處理器系統700‧‧‧Processor System
740‧‧‧記憶體740‧‧‧ memory
744‧‧‧可編程電阻元件744‧‧‧Programmable resistance element
742‧‧‧存儲單元陣列742‧‧‧Memory Cell Array
710‧‧‧中央處理單元710‧‧‧Central Processing Unit
715‧‧‧共同匯流排715‧‧‧Common bus
720‧‧‧輸入輸出單元720‧‧‧Input and output unit
730‧‧‧硬盤驅動器730‧‧‧ Hard disk drive
750‧‧‧光碟750‧‧‧DVD
740‧‧‧記憶體740‧‧‧ memory
760‧‧‧其他記憶體760‧‧‧Other memory
第一圖顯示一種傳統的可編程電阻式記憶存儲單元示意圖。The first figure shows a schematic diagram of a conventional programmable resistive memory storage unit.
第二圖a顯示相變記憶體(PCM)用的另一種傳統可編程電阻式元件示意圖，其採用雙極型晶體管作為編程選擇器。Figure 2a shows a schematic diagram of another conventional programmable resistive element for phase change memory (PCM) that uses a bipolar transistor as a programming selector.
第二圖b顯示一種傳統相變記憶體(PCM)截面圖，其採用二極體作為編程選擇器。Figure 2b shows a conventional phase change memory (PCM) cross-section using a diode as a programming selector.
第二圖c顯示另一種傳統相變記憶體(PCM)存儲單元的橫截面，其採用雙極型晶體管作為編程選擇器。Figure 2c shows a cross section of another conventional phase change memory (PCM) memory cell that employs a bipolar transistor as a programming selector.
第三圖顯示一多晶矽二極體的橫截面。The third figure shows the cross section of a polycrystalline germanium diode.
第四圖顯示如第三圖所示的多晶矽二極體的電流電壓特性圖。The fourth graph shows the current-voltage characteristics of the polysilicon diode as shown in the third figure.
第五圖顯示使用一根據本發明的多晶矽二極體於可逆性可編程電阻式存儲單元的方塊圖。The fifth figure shows a block diagram of a reversible programmable resistive memory cell using a polysilicon diode according to the present invention.
第六圖顯示一可逆性可編程電阻式存儲單元的頂視圖。此存儲單元實施例使用多晶矽二極體為編程選擇器。The sixth figure shows a top view of a reversible programmable resistive memory cell. This memory cell embodiment uses a polysilicon diode as a programming selector.
第七圖顯示一可逆性可編程電阻元件的截面圖。此電阻元件使用相變材料作為電阻元件。此外根據此實施例，具有緩衝金屬層耦合相變材料層和其他金屬及多晶矽二極體。The seventh figure shows a cross-sectional view of a reversible programmable resistance element. This resistive element uses a phase change material as a resistive element. Further in accordance with this embodiment, there is a buffer metal layer coupled with a phase change material layer and other metal and polycrystalline germanium diodes.
第八圖顯示一相變記憶體存儲單元的頂視圖。根據此實施例，其使用多晶矽二極體當編程選擇器。The eighth figure shows a top view of a phase change memory storage unit. According to this embodiment, it uses a polysilicon diode as a programming selector.
第九圖顯示一可逆性可編程電阻式記憶體的一部分示意圖。根據此一實施例，由n行和(m+1)列的單二極體存儲單元與n個字元線驅動器一起構成。The ninth diagram shows a portion of a reversible programmable resistive memory. According to this embodiment, a single diode memory cell of n rows and (m+1) columns is constructed with n word line drivers.
第十圖a描繪一種可編程電阻式記憶體編程方法流程圖。Figure 11 a depicts a flow chart of a programmable resistive memory programming method.
第十圖b描繪一種可編程電阻式記憶體方讀取法流程圖。Figure 11b depicts a flow chart of a programmable resistive memory side reading method.
第十一圖顯示一種處理器(Processor)的系統的實施例示意圖。An eleventh diagram shows a schematic diagram of an embodiment of a processor system.
在此揭露實施例，使用至少一多晶矽二極體當編程選擇器的可編程電阻式元件。此二極體可以包括植入層於一多晶矽基板內之P+和N。由於P+和N+植入層都是以現成的標準CMOS邏輯製程，這些元件可用一個有效率及符合成本效益的方法做成。沒有額外的光罩或製程步驟，以節省成本。這可編程電阻式元件可以包括在電子系統裏。Embodiments are disclosed herein that use at least one polysilicon diode to program a programmable resistive element of a selector. The diode may include P+ and N implanted in a polycrystalline germanium substrate. Since both the P+ and N+ implant layers are in a ready-to-use standard CMOS logic process, these components can be fabricated in an efficient and cost effective manner. There are no additional masks or process steps to save costs. This programmable resistive element can be included in an electronic system.
第五圖所示為使用一多晶矽二極體的可逆性可編程電阻式記憶體存儲單元30的實施例方塊圖。特別是，存儲單元30包括一可逆性可編程電阻元件31和一多晶矽二極體32。電阻元件31可耦合在多晶矽二極體32的陽極和高電壓V+之間。多晶矽二極體32的陰極可耦合到低電壓V-。在一實施例裏，記憶體存儲單元30可以是相變記憶體存儲單元，其含有相變材料的電阻元件31。多晶矽二極體32可作為編程選擇器。可逆性可編程電阻元件31和多晶矽二極體32於電源電壓V+和V-之間是可互換的。經由一適當的時間裏施加適當的電壓在V+和V-之間，可逆性可編程電阻元件31可根據電壓和持續時間被編程為高或低電阻狀態，因此編程記憶體存儲單元30可存儲數據值(例如，數據的位元)。多晶矽二極體的P+和N+植入層可以使用矽化物阻擋層(SBL)來隔離。The fifth diagram shows a block diagram of an embodiment of a reversible programmable resistive memory storage unit 30 using a polysilicon diode. In particular, memory cell 30 includes a reversible programmable resistive element 31 and a polysilicon diode 32. The resistive element 31 can be coupled between the anode of the polysilicon diode 32 and the high voltage V+. The cathode of the polysilicon diode 32 can be coupled to a low voltage V-. In one embodiment, the memory storage unit 30 can be a phase change memory storage unit that includes a resistive element 31 of phase change material. Polycrystalline germanium diode32 can be used as a programming selector. The reversible programmable resistive element 31 and the polysilicon diode 32 are interchangeable between supply voltages V+ and V-. The reversible programmable resistive element 31 can be programmed to a high or low resistance state according to voltage and duration by applying an appropriate voltage between V+ and V- over a suitable time, so the programmed memory storage unit 30 can store data. Value (for example, the bit of the data). The P+ and N+ implant layers of the polysilicon diode can be isolated using a telluride barrier layer (SBL).
第六圖顯示用多晶矽二極體32作為編程選擇器的可逆性可編程電阻存儲單元30實施例頂視圖。可逆性可編程電阻單元30包括一可逆性可編程元件31耦合到第一電源電壓V+和一二極體32。二極體32作為可逆性可編程電阻單元30的編程選擇器。該二極體32是建立在一塊多晶矽34，即多晶矽基板。構建PMOS或NMOS元件源極或汲極的P+和N+植入層33和37用來形成多晶矽二極體32的P，N兩端於多晶矽34上。矽化物阻擋層36阻擋矽化物形成於多晶矽的表面，以防止多晶矽二極體32的P和N端短路。P+植入層33和N+植入層37的距離d可用於調整擊穿電壓和漏電流。一選項層39可以引進N型淺源汲極(NLDD)、P型淺源汲極(PLDD)植入層、或NMOS和PMOS門檻電壓的摻雜植入技術於N+植入層37和P+植入層33之間，以進一步控制二極體的導通電阻。該選項層39所植入區可於標準CMOS上產生各種類的植入層，且不會增加額外費用。The sixth diagram shows a top view of an embodiment of a reversible programmable resistance memory cell 30 with a polysilicon diode 32 as a programming selector. The reversible programmable resistance unit 30 includes a reversible programmable element 31 coupled to the first supply voltage V+ and a diode 32. The diode 32 acts as a programming selector for the reversible programmable resistance unit 30. The diode 32 is built on a polysilicon 34, a polycrystalline germanium substrate. The P+ and N+ implant layers 33 and 37, which are used to form the source or drain of the PMOS or NMOS device, are used to form P, N across the polysilicon 34 of the polysilicon diode 32. The telluride barrier layer 36 blocks the formation of a telluride on the surface of the polysilicon to prevent short-circuiting of the P and N terminals of the polysilicon diode 32. The distance d between the P+ implant layer 33 and the N+ implant layer 37 can be used to adjust the breakdown voltage and leakage current. An optional layer 39 may incorporate an N-type shallow source drain (NLDD), a P-type shallow source drain (PLDD) implant layer, or an NMOS and PMOS threshold voltage doping implant technique for the N+ implant layer 37 and P+ implants. Between layers 33 to further control the on-resistance of the diode. The implanted area of the option layer 39 can produce various types of implant layers on standard CMOS without additional cost.
第七圖顯示了一可逆性可編程電阻元件存儲單元50的截面圖。根據此一實施例，其使用相變材料(Phase Change Material)作為電阻元件42，具緩衝金屬41和43，和多晶矽二極體30(位在矽基體上的介電質49上)。多晶矽二極體30在多晶矽基板31上有P+植入區33和N+植入區37，且此兩個植入區通過陽極接點32和陰極接點39為二極體的P，N兩端。矽化物阻擋層(STI)35隔離P+植入區33和N+植入區37。二極體31的P+植入區33經由接點填塞物40-1被耦合到作為緩衝層的下層金屬41。這下層金屬41，經由接點填塞物40-2被耦合到相變材料的一層薄膜42(如GST薄膜)。上層金屬43也被耦合到相變材料的薄膜42。上層金屬43經過接點填塞物40-3被耦合到位元線(Bitline)的另一種金屬44。相變薄膜42可以有化學成分鍺(Ge)、銻(Sb)和碲(Te)，如GexSbyTez(x，y和z是任意數字)，或如Ge2Sb2Te5(GST-225)。GST可以摻至少有一或更多種的銦(In)，錫(Sn)或硒(Se)，以提高性能。相變的存儲單元結構，可顯著平面化。這意味著相變薄膜42的面積大於被耦合到編程選擇器薄膜的接觸面積；或從矽基體表面到相變薄膜42的高度，遠小於平行於矽基體薄膜的尺寸。在此實施例裏，相變薄膜42的有效區遠遠大於接觸面積，使編程特性可以更均勻，和具可重複性。相變薄膜42不是垂直結構，不坐落在高大的接點上面，能更適合嵌入式相變記憶體的應用，尤其是當多晶矽二極體30作為編程選擇器時，可使存儲單元的面積非常小。對此技藝知悉者可知結構和製造過程可能會有所不同，而且上述相變薄膜(如GST film)的結構和緩衝金屬只作說明用途。The seventh diagram shows a cross-sectional view of a reversible programmable resistive element memory unit 50. According to this embodiment, a phase change material is used as the resistive element 42, with buffer metals 41 and 43, and a polysilicon diode 30 (on the dielectric 49 on the tantalum substrate). The polycrystalline germanium diode 30 has a P+ implant region 33 and an N+ implant region 37 on the polycrystalline germanium substrate 31, and the two implant regions are connected through the anode contact 32 and the cathode.Point 39 is the P and N ends of the diode. A telluride barrier layer (STI) 35 isolates the P+ implant region 33 and the N+ implant region 37. The P+ implant region 33 of the diode 31 is coupled to the underlying metal 41 as a buffer layer via the contact plug 40-1. This underlying metal 41 is coupled to a layer of film 42 (e.g., GST film) of phase change material via contact tampon 40-2. The upper metal 43 is also coupled to the film 42 of phase change material. The upper metal 43 is coupled to another metal 44 of the bitline via contact plug 40-3. The phase change film 42 may have chemical compositions of germanium (Ge), antimony (Sb), and tellurium (Te), such as GexSbyTez (x, y and z are arbitrary numbers), or as Ge2Sb2Te5 (GST-225). The GST may be doped with at least one or more of indium (In), tin (Sn) or selenium (Se) to improve performance. The phase change memory cell structure can be significantly planarized. This means that the area of the phase change film 42 is larger than the contact area coupled to the programmable selector film; or the height from the surface of the ruthenium substrate to the phase change film 42, much smaller than the size parallel to the ruthenium base film. In this embodiment, the effective area of the phase change film 42 is much larger than the contact area, making the programming characteristics more uniform and repeatable. The phase change film 42 is not a vertical structure and is not located above the tall contacts, and is more suitable for the application of the embedded phase change memory, especially when the polysilicon diode 30 is used as a programming selector, the area of the memory cell can be made very large. small. It is known to those skilled in the art that the structure and manufacturing process may vary, and the structure of the phase change film (such as GST film) and the buffer metal are for illustrative purposes only.
第八圖顯示了一種相變材料(Phase Change Material)存儲單元的頂視圖。按照此實例，存儲單元擁有一多晶矽二極體作為編程選擇器，其邊界為70。相變材料的存儲單元有多晶矽二極體71和相變材料元件75。多晶矽二極體71具有陽極72和陰極79，分別被P+植入層73和N+植入層77所覆蓋。矽化物阻擋層(STI)80阻擋矽化物形成於多晶矽二極體71的表面，防止多晶矽二極體71的陽極72和陰極79短路。陽極72經由第一層金屬(metal1)76耦合到相變材料薄膜75。相變材料薄膜75耦合到垂直方向的第三層金屬(metal3)78位元線(BL)。多晶矽二極體71的陰極79耦合到水平方向的第二層金屬(metal2)77字元線(WL)。施加適當的電壓於位元線78和字元線77之間一段適當的時間，相變材料75可被編程為相應的0或1狀態。由於編程相變材料存儲單元是依據溫度升高，而不是如對電性熔絲的電遷移，相變薄膜(如GST薄膜)的陽極和陰極可以有對稱的面積。對此技藝知悉者可知相變薄膜，結構和佈線風格，和金屬的結構可在其他實施例裏有所不同。The eighth figure shows a top view of a phase change material storage unit. According to this example, the memory cell has a polysilicon diode as a programming selector with a boundary of 70. The memory cell of the phase change material has a polysilicon diode 71 and a phase change material element 75. The polysilicon diode 71 has an anode 72 and a cathode 79, which are covered by a P+ implant layer 73 and an N+ implant layer 77, respectively. A telluride barrier layer (STI) 80 blocks the formation of a telluride on the surface of the polycrystalline germanium diode 71, preventing the anode of the polycrystalline germanium diode 71.72 and cathode 79 are shorted. The anode 72 is coupled to the phase change material film 75 via a first layer of metal (metal 1) 76. The phase change material film 75 is coupled to a third layer metal (metal3) 78 bit line (BL) in the vertical direction. The cathode 79 of the polysilicon diode 71 is coupled to a horizontal second metal (metal 2) 77 word line (WL). Applying the appropriate voltage between bit line 78 and word line 77 for a suitable period of time, phase change material 75 can be programmed to a corresponding 0 or 1 state. Since the programmed phase change material storage unit is based on an increase in temperature rather than electromigration as an electrical fuse, the anode and cathode of the phase change film (e.g., GST film) may have a symmetrical area. It is known to those skilled in the art that phase change films, structures and wiring styles, and metal structures may differ in other embodiments.
編程相變記憶體(PCM)，如相變薄膜，取決於相變薄膜的物理特性，如玻璃化轉變溫度和熔化溫度。要重設(寫1)，需要被加熱超出熔化溫度，然後驟降溫。要設置(寫0)，相變薄膜需要被加熱到熔化和玻璃化轉變之間的溫度，然後退火處理。典型的相變材料薄膜的玻璃化轉變溫度約200℃，熔融溫度約攝氏600度。這些溫度決定相變記憶體(PCM)的操作溫度，因為在特定溫度下一段長時間後電阻狀態可能會發生變化。但是，大多數應用需要保留數據10年，從工作溫度0到85℃或-40到125℃。為了在元件的壽命期限和在如此寬的溫度範圍內維持存儲單元的穩定性，相變記憶體可以被定期讀取出，然後將數據寫回相同的存儲單元，此為更新機制。更新週期可能會相當長，如超過一秒鐘(例如，分鐘，小時，天，星期，甚至幾個月)。更新機制可由記憶體內部產生或從記憶體外部觸發。長時間的更新週期以維持存儲單元的穩定性，也可以應用於其他新興的記憶體，如電阻式隨機存取記憶體(RRAM)，導電橋隨機存取記憶體(CBRAM)，和磁化隨機存取記憶體(MRAM)等。Programming phase change memory (PCM), such as phase change films, depends on the physical properties of the phase change film, such as glass transition temperature and melting temperature. To reset (write 1), it needs to be heated beyond the melting temperature and then cooled down. To set (write 0), the phase change film needs to be heated to the temperature between the melting and the glass transition and then annealed. A typical phase change material film has a glass transition temperature of about 200 ° C and a melting temperature of about 600 ° C. These temperatures determine the operating temperature of the phase change memory (PCM) because the resistance state may change over a long period of time at a particular temperature. However, most applications need to retain data for 10 years, from operating temperatures of 0 to 85 ° C or -40 to 125 ° C. In order to maintain the stability of the memory cell over the lifetime of the component and over such a wide temperature range, the phase change memory can be periodically read out and then the data is written back to the same memory cell, which is an update mechanism. The update cycle can be quite long, such as more than one second (for example, minutes, hours, days, weeks, or even months). The update mechanism can be generated internally by the memory or externally from the memory. Long-term update cycle to maintain memory cell stability, can also be applied to other emerging memory, such as resistive random access memory (RRAM), conductive bridge random access memory (CBRAM), and magnetizationMachine access memory (MRAM) and so on.
根據另一實施例，可編程電阻元件可用於建立一記憶體。根據此實施例，第九圖顯示了可編程電阻記憶體100的一部分，由n行x(m+1)列的單二極體存儲單元110的一陣列101和n個字元線驅動器150-i(i=0,1,...,n-1)所構建。記憶體陣列101有m個正常列和一參考列，共用一感應放大器做差動感應。於同一列的每個記憶體存儲單元110有一電阻元件111被耦合到當編程選擇器的一二極體112的P端和到一位元線BL j170-j(j=0,1,..m-1)或參考位元線BLR01-0。在同一行的記憶體存儲單元110的二極體112的N端經由局部字元線LWLBi154-i,(i=0,1,…,n-1)被耦合到一字元線WLBi152-i，。每個字元線WLBi被耦合到至少一局部字元線LWLBi，此處i=0,1,…,n-1。該LWLBi154-i通常由高電阻材料，如N井或多晶矽構建，來連接存儲單元，然後經由接點或層間接點、緩衝器或後解碼器172-i(i=0,1,...,n-1)耦合到WLBi(例如，低電阻金屬WLBi)。當使用二極體作為編程選擇器，可能需要緩衝器或後解碼器172-i，因為有電流流過WLBi，特別是當WLBi驅動多個存儲單元來同時編程和讀取。該字元線WLBi是由字元線驅動器150-i所驅動，為了編程和讀取，其電源電壓vddi可以在不同的電壓之間被切換。每個BLj170-j或BLR0175-0都經由一Y-寫(Y-write)通道閘120-j或125被耦合到一電源電壓VDDP來編程，其中BLj170-j及BLR0175-0分別由被YSWBj(j=0,1,..,m-1)及YSWRB0選取。Y-write通道閘120-j(j=0,1,…,m-1)或125可以由PMOS所建構，然而NMOS，二極體，或雙極型元件可以在一些實施例裏使用。每BL或BLR0經由一Y-read通道閘130-j或135被耦合到一數據線DLj或參考數據線DLR0，且BL及BLR0分別由YSRj(j=0,1,..,m-1)及YSRR0所選定。在記憶體陣列101這一部分，m正常的數據線DLj(j=0,1,…,m-1)被連接到一感應放大器140的一輸入端160。該參考數據線DLR0提供了感應放大器140的另一輸入端161(一般在參考部分裏不需要多工器)。感應放大器140的輸出端是Q0。According to another embodiment, a programmable resistive element can be used to create a memory. According to this embodiment, the ninth diagram shows a portion of the programmable resistive memory 100, an array 101 of n-diode memory cells 110 of n rows x (m+1) columns and n word line drivers 150- Constructed by i(i=0,1,...,n-1). The memory array 101 has m normal columns and a reference column, and shares a sense amplifier for differential sensing. Each of the memory storage units 110 in the same column has a resistive element 111 coupled to the P terminal of a diode 112 of the programming selector and to a bit line BL j170-j (j=0, 1, .. M-1) or reference bit line BLR01-0. The N terminal of the diode 112 of the memory cell 110 in the same row is coupled to a word line WLBi 152-i via a local word line LWLBi154-i, (i = 0, 1, ..., n-1), . Each word line WLBi is coupled to at least one local word line LWLBi, where i = 0, 1, ..., n-1. The LWLBi154-i is typically constructed of a high-resistance material, such as a N-well or polysilicon, to connect the memory cells and then pass through a contact or layer indirect point, buffer or post-decoder 172-i (i=0,1,... , n-1) is coupled to WLBi (eg, low resistance metal WLBi). When a diode is used as the programming selector, a buffer or post decoder 172-i may be required because current flows through WLBi, particularly when WLBi drives multiple memory cells for simultaneous programming and reading. The word line WLBi is driven by the word line driver 150-i, and its power supply voltage vddi can be switched between different voltages for programming and reading. Each BLj170-j or BLR0175-0 is programmed via a Y-write channel gate 120-j or 125 coupled to a supply voltage VDDP, where BLj170-j and BLR0175-0 are respectively by YSWBj ( j=0,1,..,m-1) and YSWRB0 are selected. The Y-write channel gate 120-j (j = 0, 1, ..., m-1) or 125 may be constructed by a PMOS, although an NMOS, diode, or bipolar element may be used in some embodiments. Each BL or BLR0 is coupled via a Y-read channel gate 130-j or 135To a data line DLj or a reference data line DLR0, and BL and BLR0 are selected by YSRj (j = 0, 1, ..., m-1) and YSRR0, respectively. In the portion of the memory array 101, m normal data lines DLj (j = 0, 1, ..., m-1) are coupled to an input 160 of a sense amplifier 140. The reference data line DLR0 provides the other input 161 of the sense amplifier 140 (generally no multiplexer is required in the reference portion). The output of sense amplifier 140 is Q0.
要編程一存儲單元，特定的WLBi和YSWBj被開啟而高電壓被提供到VDDP，其中i=0,1,..,n-1而j=0,1,...,m-1。在一些實例裏，經由打開WLRBi(i=0,1,...,n-1)和YSWRB0，參考存儲單元可以被編程為0或1。要讀取一存儲單元，一數據列線160可以由啟用特定的WLBi和YSRj，(其中i=0,1,...,n-1，和j=0,1,...,m-1)來選到，而一參考數據線DLR0161可以由啟用特定的一參考存儲單元來選到，其皆被耦合到感應放大器140。此感應放大器140可以被用來感應和比較DLj和DLR0與接地之間的電阻差異，同時關閉所有YSWBj和YSWRB0，其中j=0,1,..,m-1。To program a memory cell, the particular WLBi and YSWBj are turned on and the high voltage is supplied to VDDP, where i = 0, 1, .., n-1 and j = 0, 1, ..., m-1. In some examples, the reference memory cell can be programmed to 0 or 1 by turning on WLRBi (i = 0, 1, ..., n-1) and YSWRB0. To read a memory cell, a data column line 160 can be enabled by a particular WLBi and YSRj, (where i = 0, 1, ..., n-1, and j = 0, 1, ..., m- 1) Selected, and a reference data line DLR0161 can be selected by enabling a particular reference memory unit, which is coupled to sense amplifier 140. This sense amplifier 140 can be used to sense and compare the difference in resistance between DLj and DLR0 and ground, while turning off all YSWBj and YSWRB0, where j = 0, 1, .., m-1.
第十圖a和第十圖b顯示一流程圖實施例，分別描繪一可編程電阻式記憶體的編程方法S700和讀取方法S800。方法S700和S800描述了可編程電阻式記憶體(如第九圖的可編程電阻記憶體100)的編程和讀取。此外，雖然說是一個步驟流程，對此技藝知悉者可知至少一些步驟可能會以不同的順序進行，包括同時或跳過。The tenth diagram a and the tenth diagram b show a flowchart embodiment, respectively describing a programmable resistance memory programming method S700 and a reading method S800. Methods S700 and S800 describe the programming and reading of a programmable resistive memory (such as the programmable resistive memory 100 of Figure 9). In addition, although it is a step process, it is known to those skilled in the art that at least some of the steps may be performed in a different order, including simultaneous or skipping.
第十圖a描繪可編程電阻記憶體編程方法S700的流程。根據此實施例，在第一步驟S710，選擇適當的電源選擇器以施加高電壓電源到字元線和位元線驅動器。在第二步驟S720，在控制邏輯(第九圖裏沒有顯示)裏進行分析要被編程的數據，根據什麼類型的可編程電阻元件。對於相變記憶體(PCM)，編程到一個0(設定)和編程到一個1(重設)需要不同的電壓和持續時間，所以一個控制邏輯決定了輸入數據，並選擇適當的電源選擇器和啟動適當的時序控制信號。在第三步驟S730，選擇一個存儲單元的一行(群)，所以相對的局部字元線可被開啟。在第四步驟S740，停用感應放大器，以節省電源和防止干擾到編程的運作。在第五步驟S750，一存儲單元的一列(群)，可以被選定並且相對應的Y-write通道閘可以被打開來耦合所選的位元線(群)到一電源電壓。在最後一步驟S760，在一已建立的傳導路徑來驅動所需的電流一段所需要的時間來完成編程的運作。對於大多數可編程電阻記憶體，這個傳導路徑是由一個高壓電源，通過被選的一位元線(群)，電阻元件，作為編程選擇器的二極體，以及一局部字元線(群)驅動器的NMOS下拉元件到接地。The tenth diagram a depicts the flow of the programmable resistance memory programming method S700. According to this embodiment, in a first step S710, an appropriate power supply selector is selected to apply a high voltage power supply to the word line and bit line drivers. In a second step S720, the data to be programmed is analyzed in the control logic (not shown in the ninth figure), depending on what typeProgrammable resistor element. For phase change memory (PCM), programming to a 0 (set) and programming to a 1 (reset) requires different voltages and durations, so a control logic determines the input data and selects the appropriate power selector and Start the appropriate timing control signal. In a third step S730, a row (group) of one memory cell is selected, so the relative local word line can be turned on. In a fourth step S740, the sense amplifier is deactivated to save power and prevent interference to the programmed operation. In a fifth step S750, a column (group) of memory cells can be selected and the corresponding Y-write channel gate can be opened to couple the selected bit line (group) to a supply voltage. At the last step S760, the programmed operation is completed by an established conduction path to drive the required current for a desired period of time. For most programmable resistor memories, this conduction path is made up of a high voltage power supply through the selected bit line (group), the resistive element, the diode as the programming selector, and a local word line (group) ) Drive the NMOS pull-down component to ground.
第十圖b描繪可編程電阻記憶體讀取方法S800流程圖。在第一步驟S810，提供合適的電源選擇器來選電源電壓給局部字元線驅動器，感應放大器和其他電路。在第二步驟S820，所有Y-write通道閘，例如位元線編程選擇器，可以被關閉。在第三步驟S830，所需的局部字元線驅動器(群)可以被選，使作為編程選擇器(群)的二極體(群)具有傳導路徑到接地。在第四步驟S840，啟動感應放大器和準備感應的輸入信號。在第五步驟S850，數據線和參考數據線被預先充電到可編程電阻元件存儲單元的V-電壓。在第六步驟S860，選所需的Y-read通道閘，使所需的位元線被耦合到感應放大器的一輸入端。一傳導路徑於是被建立，從位元線到所要的存儲單元的電阻元件，作為編程選擇器(群)的二極體(群)和局部字元線驅動器的下拉元件到接地。這同樣適用於參考分支。在最後一步驟S870，感應放大器可以比較讀取電流與參考電流的差異來決定邏輯輸出是0或1以完成讀取操作。Figure 10b depicts a flow chart of a programmable resistive memory reading method S800. In a first step S810, a suitable power selector is provided to select the supply voltage to the local word line driver, sense amplifier and other circuitry. In a second step S820, all Y-write channel gates, such as bit line programming selectors, can be turned off. In a third step S830, the desired local word line driver (group) can be selected such that the diodes (groups) as programming selectors (groups) have a conductive path to ground. In a fourth step S840, the sense amplifier and the input signal ready for sensing are activated. In a fifth step S850, the data line and the reference data line are precharged to the V-voltage of the programmable resistive element memory cell. In a sixth step S860, the desired Y-read pass gate is selected such that the desired bit line is coupled to an input of the sense amplifier. A conduction path is then established, from the bit line to the desired resistive element of the memory cell, as a diode of the programming selector (group)(group) and pull down the component of the local word line driver to ground. The same applies to the reference branch. At the last step S870, the sense amplifier can compare the difference between the read current and the reference current to determine whether the logic output is 0 or 1 to complete the read operation.
第十一圖顯示了一種處理器系統700的一實施例。根據此實施例，處理器系統700可以包括在記憶體740中的可編程電阻元件744(例如在存儲單元陣列742裏)。處理器系統700可以，例如屬於一電腦系統。電腦系統可以包括中央處理單元(CPU)710，它經由共同匯流排715來和多種記憶體和周邊裝置溝通，如輸入輸出單元720，硬盤驅動器730，光碟750，記憶體740，和其他記憶體760。其他記憶體760是一種傳統的記憶體如靜態記憶體(SRAM)，動態記憶體(DRAM)，或閃存記憶體(flash)，通常經由記憶體控制器來和與中央處理單元710溝通。中央處理單元710一般是一種微處理器，一種數位信號處理器，或其他可編程數位邏輯元件。記憶體740最好是以積體電路來構造，其中包括具有至少有一可編程電阻元件744的存儲單陣列742。通常，記憶體740經由記憶體控制器來接觸中央處理單元710。如果需要，可合併記憶體740與處理器(例如中央處理單元710)在單片積體電路。An eleventh diagram shows an embodiment of a processor system 700. According to this embodiment, processor system 700 can include programmable resistive elements 744 (eg, in memory cell array 742) in memory 740. Processor system 700 can, for example, belong to a computer system. The computer system can include a central processing unit (CPU) 710 that communicates with various memory and peripheral devices via a common bus 715, such as input and output unit 720, hard disk drive 730, optical disk 750, memory 740, and other memory 760. . The other memory 760 is a conventional memory such as static memory (SRAM), dynamic memory (DRAM), or flash memory, typically communicated with the central processing unit 710 via a memory controller. Central processing unit 710 is typically a microprocessor, a digital signal processor, or other programmable digital logic element. Memory 740 is preferably constructed in an integrated circuit including a memory array 742 having at least one programmable resistive element 744. Typically, memory 740 contacts central processing unit 710 via a memory controller. If desired, the memory 740 can be combined with a processor (e.g., central processing unit 710) in a monolithic integrated circuit.
本發明可以部分或全部實現於積體電路上，在印刷電路板(PCB)上，或在系統上。該可編程電阻元件可以是熔絲，反熔絲，或新出現的非揮發行性記憶體。熔絲可以是矽化或非矽化多晶矽熔絲，熱隔離的主動區熔絲，金屬熔絲，接點熔絲，或層間接點熔絲。反熔絲可以是一個閘極氧化層崩潰反熔絲，介電質於其間的接點或層間接點反熔絲。新出現的非揮發行性記憶體可以是磁性記憶體(MRAM)，相變記憶體(PCM)，導電橋隨機存取記憶體(CBRAM)，或電阻隨機存取記憶體(RRAM)。雖然編程機制不同，其邏輯狀態可以由不同的電阻值來區分。The invention may be implemented in part or in whole on an integrated circuit, on a printed circuit board (PCB), or on a system. The programmable resistive element can be a fuse, an anti-fuse, or an emerging non-volatile memory. The fuse may be a deuterated or non-deuterated polysilicon fuse, a thermally isolated active region fuse, a metal fuse, a contact fuse, or a layer indirect fuse. The antifuse can be a gate oxide breakdown antifuse, a dielectric junction or a layer indirect antifuse. The emerging non-volatile memory can be magnetic memory (MRAM), phase change memory (PCM), conductive bridge random access memoryBody (CBRAM), or Resistive Random Access Memory (RRAM). Although the programming mechanism is different, its logic state can be distinguished by different resistance values.
然以上所述者，僅為本發明之較佳實施例，當不能限定本發明實施之範圍，即凡依本發明申請專利範圍所作之均等變化與修飾等，皆應仍屬本發明之專利涵蓋範圍意圖保護之範疇。However, the above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the equivalent changes and modifications made by the scope of the present invention should still be covered by the patent of the present invention. The scope of the scope is intended to protect.
30‧‧‧存儲單元30‧‧‧storage unit
31‧‧‧可逆性可編程電阻元件31‧‧‧Reversible programmable resistance element
32‧‧‧多晶矽二極體32‧‧‧ Polycrystalline germanium diode
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US37566010P | 2010-08-20 | 2010-08-20 |
| Publication Number | Publication Date |
|---|---|
| TW201220566A TW201220566A (en) | 2012-05-16 |
| TWI492433Btrue TWI492433B (en) | 2015-07-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100129686ATWI492433B (en) | 2010-08-20 | 2011-08-19 | Reversible programmable resistive memory and providing method, phase change memory, electronic system |
| TW100129684ATWI479487B (en) | 2010-08-20 | 2011-08-19 | Magnetic memory, electronic system, memory and method thereof |
| TW100129685ATWI445137B (en) | 2010-08-20 | 2011-08-19 | Single-time programmable memory, electronic system, electrical fuse memory, programmable resistive memory and method thereof |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100129684ATWI479487B (en) | 2010-08-20 | 2011-08-19 | Magnetic memory, electronic system, memory and method thereof |
| TW100129685ATWI445137B (en) | 2010-08-20 | 2011-08-19 | Single-time programmable memory, electronic system, electrical fuse memory, programmable resistive memory and method thereof |
| Country | Link |
|---|---|
| US (1) | US8804398B2 (en) |
| CN (3) | CN102376360B (en) |
| TW (3) | TWI492433B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9224496B2 (en) | 2010-08-11 | 2015-12-29 | Shine C. Chung | Circuit and system of aggregated area anti-fuse in CMOS processes |
| US9818478B2 (en) | 2012-12-07 | 2017-11-14 | Attopsemi Technology Co., Ltd | Programmable resistive device and memory using diode as selector |
| US9496033B2 (en) | 2010-08-20 | 2016-11-15 | Attopsemi Technology Co., Ltd | Method and system of programmable resistive devices with read capability using a low supply voltage |
| US9236141B2 (en) | 2010-08-20 | 2016-01-12 | Shine C. Chung | Circuit and system of using junction diode of MOS as program selector for programmable resistive devices |
| US9251893B2 (en) | 2010-08-20 | 2016-02-02 | Shine C. Chung | Multiple-bit programmable resistive memory using diode as program selector |
| US9460807B2 (en) | 2010-08-20 | 2016-10-04 | Shine C. Chung | One-time programmable memory devices using FinFET technology |
| US9431127B2 (en) | 2010-08-20 | 2016-08-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices |
| US9042153B2 (en) | 2010-08-20 | 2015-05-26 | Shine C. Chung | Programmable resistive memory unit with multiple cells to improve yield and reliability |
| US10229746B2 (en) | 2010-08-20 | 2019-03-12 | Attopsemi Technology Co., Ltd | OTP memory with high data security |
| US10923204B2 (en) | 2010-08-20 | 2021-02-16 | Attopsemi Technology Co., Ltd | Fully testible OTP memory |
| US9025357B2 (en) | 2010-08-20 | 2015-05-05 | Shine C. Chung | Programmable resistive memory unit with data and reference cells |
| US8804398B2 (en) | 2010-08-20 | 2014-08-12 | Shine C. Chung | Reversible resistive memory using diodes formed in CMOS processes as program selectors |
| US9019742B2 (en) | 2010-08-20 | 2015-04-28 | Shine C. Chung | Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory |
| US10249379B2 (en) | 2010-08-20 | 2019-04-02 | Attopsemi Technology Co., Ltd | One-time programmable devices having program selector for electrical fuses with extended area |
| US10916317B2 (en) | 2010-08-20 | 2021-02-09 | Attopsemi Technology Co., Ltd | Programmable resistance memory on thin film transistor technology |
| US9070437B2 (en) | 2010-08-20 | 2015-06-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink |
| US8488359B2 (en) | 2010-08-20 | 2013-07-16 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices |
| US8830720B2 (en) | 2010-08-20 | 2014-09-09 | Shine C. Chung | Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices |
| US9824768B2 (en) | 2015-03-22 | 2017-11-21 | Attopsemi Technology Co., Ltd | Integrated OTP memory for providing MTP memory |
| US9711237B2 (en) | 2010-08-20 | 2017-07-18 | Attopsemi Technology Co., Ltd. | Method and structure for reliable electrical fuse programming |
| US8488364B2 (en) | 2010-08-20 | 2013-07-16 | Shine C. Chung | Circuit and system of using a polysilicon diode as program selector for resistive devices in CMOS logic processes |
| US9076513B2 (en) | 2010-11-03 | 2015-07-07 | Shine C. Chung | Low-pin-count non-volatile memory interface with soft programming capability |
| US8988965B2 (en) | 2010-11-03 | 2015-03-24 | Shine C. Chung | Low-pin-count non-volatile memory interface |
| US9019791B2 (en) | 2010-11-03 | 2015-04-28 | Shine C. Chung | Low-pin-count non-volatile memory interface for 3D IC |
| US8913449B2 (en) | 2012-03-11 | 2014-12-16 | Shine C. Chung | System and method of in-system repairs or configurations for memories |
| US9496265B2 (en) | 2010-12-08 | 2016-11-15 | Attopsemi Technology Co., Ltd | Circuit and system of a high density anti-fuse |
| US10586832B2 (en) | 2011-02-14 | 2020-03-10 | Attopsemi Technology Co., Ltd | One-time programmable devices using gate-all-around structures |
| US8848423B2 (en) | 2011-02-14 | 2014-09-30 | Shine C. Chung | Circuit and system of using FinFET for building programmable resistive devices |
| US10192615B2 (en) | 2011-02-14 | 2019-01-29 | Attopsemi Technology Co., Ltd | One-time programmable devices having a semiconductor fin structure with a divided active region |
| US8607019B2 (en) | 2011-02-15 | 2013-12-10 | Shine C. Chung | Circuit and method of a memory compiler based on subtractive approach |
| KR20130043533A (en)* | 2011-10-20 | 2013-04-30 | 삼성전자주식회사 | Non-volatile memory device having conductive buffer pattern and method of forming the same |
| US8912576B2 (en) | 2011-11-15 | 2014-12-16 | Shine C. Chung | Structures and techniques for using semiconductor body to construct bipolar junction transistors |
| US9324849B2 (en) | 2011-11-15 | 2016-04-26 | Shine C. Chung | Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC |
| US9136261B2 (en) | 2011-11-15 | 2015-09-15 | Shine C. Chung | Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection |
| US8861249B2 (en) | 2012-02-06 | 2014-10-14 | Shine C. Chung | Circuit and system of a low density one-time programmable memory |
| US8917533B2 (en) | 2012-02-06 | 2014-12-23 | Shine C. Chung | Circuit and system for testing a one-time programmable (OTP) memory |
| US9007804B2 (en) | 2012-02-06 | 2015-04-14 | Shine C. Chung | Circuit and system of protective mechanisms for programmable resistive memories |
| US9076526B2 (en) | 2012-09-10 | 2015-07-07 | Shine C. Chung | OTP memories functioning as an MTP memory |
| US9183897B2 (en) | 2012-09-30 | 2015-11-10 | Shine C. Chung | Circuits and methods of a self-timed high speed SRAM |
| TW201417102A (en) | 2012-10-23 | 2014-05-01 | Ind Tech Res Inst | Resistive random-access memory devices |
| US9324447B2 (en) | 2012-11-20 | 2016-04-26 | Shine C. Chung | Circuit and system for concurrently programming multiple bits of OTP memory devices |
| TWI608483B (en)* | 2012-12-07 | 2017-12-11 | 上峰科技股份有限公司 | Circuit and system of 3d programmable resistive device and memory using diode as selector |
| US9178143B2 (en)* | 2013-07-29 | 2015-11-03 | Industrial Technology Research Institute | Resistive memory structure |
| WO2015023290A1 (en)* | 2013-08-16 | 2015-02-19 | Intel Corporation | Memory cell with retention using resistive memory |
| CN104425448B (en)* | 2013-09-10 | 2019-04-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of anti-fuse structures |
| TWI550621B (en)* | 2013-09-21 | 2016-09-21 | 上峰科技股份有限公司 | Circuit and system of using junction diode as program selector for electrical fuses with extended area for one-time programmable devices |
| GB2534077A (en)* | 2013-09-21 | 2016-07-13 | Chung Shine | Circuit and system of using junction diode as program selector for one-time programmable devices |
| US9087841B2 (en)* | 2013-10-29 | 2015-07-21 | International Business Machines Corporation | Self-correcting power grid for semiconductor structures method |
| US9437815B1 (en)* | 2014-04-30 | 2016-09-06 | Adesto Technologies Corporation | Resistive switching memory device architecture for reduced cell damage during processing |
| US9412473B2 (en) | 2014-06-16 | 2016-08-09 | Shine C. Chung | System and method of a novel redundancy scheme for OTP |
| US20170250223A1 (en)* | 2014-11-19 | 2017-08-31 | Hewlett-Packard Development Company, L.P. | A resistive random-access memory in printed circuit board |
| US20160343719A1 (en)* | 2015-05-22 | 2016-11-24 | Globalfoundries Singapore Pte. Ltd. | Interposers for integrated circuits with one-time programming and methods for manufacturing the same |
| US9495627B1 (en)* | 2015-12-15 | 2016-11-15 | International Business Machines Corporation | Magnetic tunnel junction based chip identification |
| KR102465966B1 (en) | 2016-01-27 | 2022-11-10 | 삼성전자주식회사 | Memory device and electronic apparatus comprising the same memory device |
| CN107204397B (en)* | 2016-03-18 | 2019-06-21 | 中国科学院微电子研究所 | Selection device for bipolar resistive random access memory and preparation method thereof |
| US9953705B2 (en) | 2016-04-26 | 2018-04-24 | Western Digital Technologies, Inc. | Planar memory cell architectures in resistive memory devices |
| CN107887389B (en)* | 2016-09-30 | 2020-08-04 | 财团法人交大思源基金会 | Integrated circuit memory and method of operation |
| CN108630722B (en)* | 2017-03-22 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Memory cell and method of forming the same, memory array structure and method of forming the same |
| US11062786B2 (en) | 2017-04-14 | 2021-07-13 | Attopsemi Technology Co., Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
| US10535413B2 (en) | 2017-04-14 | 2020-01-14 | Attopsemi Technology Co., Ltd | Low power read operation for programmable resistive memories |
| US10726914B2 (en) | 2017-04-14 | 2020-07-28 | Attopsemi Technology Co. Ltd | Programmable resistive memories with low power read operation and novel sensing scheme |
| US11615859B2 (en) | 2017-04-14 | 2023-03-28 | Attopsemi Technology Co., Ltd | One-time programmable memories with ultra-low power read operation and novel sensing scheme |
| US10770160B2 (en) | 2017-11-30 | 2020-09-08 | Attopsemi Technology Co., Ltd | Programmable resistive memory formed by bit slices from a standard cell library |
| US10991756B2 (en) | 2018-10-23 | 2021-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bipolar selector with independently tunable threshold voltages |
| US11637235B2 (en) | 2019-01-18 | 2023-04-25 | Everspin Technologies, Inc. | In-plane spin orbit torque magnetoresistive stack/structure and methods therefor |
| US11107859B2 (en) | 2019-08-05 | 2021-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell with unipolar selectors |
| US11348652B2 (en)* | 2019-10-30 | 2022-05-31 | Hefei Reliance Memory Limited | Neural network inference accelerator based on one-time-programmable (OTP) memory arrays with one-way selectors |
| US11663455B2 (en)* | 2020-02-12 | 2023-05-30 | Ememory Technology Inc. | Resistive random-access memory cell and associated cell array structure |
| CN113078160A (en)* | 2021-03-30 | 2021-07-06 | 上海华力微电子有限公司 | Electrically programmable fuse unit and electrically programmable fuse array |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040113183A1 (en)* | 2002-12-13 | 2004-06-17 | Ilya Karpov | Isolating phase change memory devices |
| US20040264244A1 (en)* | 2003-06-12 | 2004-12-30 | Sharp Kabushiki Kaisha | Nonvolatile semiconductor memory device and control method thereof |
| US20060108625A1 (en)* | 2004-11-23 | 2006-05-25 | Moon-Sook Lee | Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated |
| US20070267675A1 (en)* | 2006-05-19 | 2007-11-22 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices including oxygen-deficient metal oxide layers and methods of manufacturing the same |
| US20090097300A1 (en)* | 2005-12-27 | 2009-04-16 | Kazuya Ishihara | Variable resistance element, its manufacturing method and semiconductor memory device comprising the same |
| US20090272958A1 (en)* | 2008-05-02 | 2009-11-05 | Klaus-Dieter Ufert | Resistive Memory |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3198670A (en) | 1961-03-09 | 1965-08-03 | Bunker Ramo | Multi-tunnel diode |
| US4148046A (en) | 1978-01-16 | 1979-04-03 | Honeywell Inc. | Semiconductor apparatus |
| US4192059A (en) | 1978-06-06 | 1980-03-11 | Rockwell International Corporation | Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines |
| US5962903A (en) | 1995-06-08 | 1999-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarized plug-diode mask ROM structure |
| JP3220055B2 (en) | 1997-07-17 | 2001-10-22 | 松下電器産業株式会社 | An optimizing device for optimizing a machine language instruction sequence or an assembly language instruction sequence, and a compiler device for converting a source program described in a high-level language into a machine language or an assembly language instruction sequence. |
| US20030075778A1 (en) | 1997-10-01 | 2003-04-24 | Patrick Klersy | Programmable resistance memory element and method for making same |
| US6405160B1 (en) | 1998-08-03 | 2002-06-11 | Motorola, Inc. | Memory compiler interface and methodology |
| EP2241968B1 (en) | 1998-08-24 | 2012-06-27 | MicroUnity Systems Engineering, Inc. | System with wide operand architecture, and method |
| JP2000150634A (en) | 1998-11-13 | 2000-05-30 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| US6400540B1 (en) | 1999-03-12 | 2002-06-04 | Sil.Able Inc. | Clamp circuit to prevent ESD damage to an integrated circuit |
| US6813705B2 (en) | 2000-02-09 | 2004-11-02 | Hewlett-Packard Development Company, L.P. | Memory disambiguation scheme for partially redundant load removal |
| JP3367500B2 (en) | 2000-03-15 | 2003-01-14 | 日本電気株式会社 | Semiconductor device |
| US20010043449A1 (en) | 2000-05-15 | 2001-11-22 | Nec Corporation | ESD protection apparatus and method for fabricating the same |
| US7058788B2 (en) | 2001-02-23 | 2006-06-06 | Falconstor Software, Inc. | Dynamic allocation of computer memory |
| US6483734B1 (en) | 2001-11-26 | 2002-11-19 | Hewlett Packard Company | Memory device having memory cells capable of four states |
| US6707729B2 (en) | 2002-02-15 | 2004-03-16 | Micron Technology, Inc. | Physically alternating sense amplifier activation |
| US6937528B2 (en) | 2002-03-05 | 2005-08-30 | Micron Technology, Inc. | Variable resistance memory and method for sensing same |
| US6803804B2 (en) | 2002-05-24 | 2004-10-12 | Raminda U. Madurawe | Programmable latch array using antifuses |
| US6850438B2 (en) | 2002-07-05 | 2005-02-01 | Aplus Flash Technology, Inc. | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations |
| US7196369B2 (en) | 2002-07-15 | 2007-03-27 | Macronix International Co., Ltd. | Plasma damage protection circuit for a semiconductor device |
| US6778420B2 (en) | 2002-09-25 | 2004-08-17 | Ovonyx, Inc. | Method of operating programmable resistant element |
| JP2004193282A (en) | 2002-12-10 | 2004-07-08 | Renesas Technology Corp | Non-volatile semiconductor memory device |
| US7800933B2 (en) | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance |
| US7652326B2 (en) | 2003-05-20 | 2010-01-26 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| US20050035410A1 (en)* | 2003-08-15 | 2005-02-17 | Yee-Chia Yeo | Semiconductor diode with reduced leakage |
| US7461371B2 (en) | 2003-09-11 | 2008-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | General purpose memory compiler system and associated methods |
| US6952038B2 (en) | 2003-12-08 | 2005-10-04 | Macronix International Co., Ltd. | 3D polysilicon ROM and method of fabrication thereof |
| US7027326B2 (en) | 2004-01-05 | 2006-04-11 | International Business Machines Corporation | 3T1D memory cells using gated diodes and methods of use thereof |
| US7511982B2 (en) | 2004-05-06 | 2009-03-31 | Sidense Corp. | High speed OTP sensing scheme |
| US7212432B2 (en) | 2004-09-30 | 2007-05-01 | Infineon Technologies Ag | Resistive memory cell random access memory device and method of fabrication |
| US7423897B2 (en) | 2004-10-01 | 2008-09-09 | Ovonyx, Inc. | Method of operating a programmable resistance memory array |
| US8179711B2 (en) | 2004-10-26 | 2012-05-15 | Samsung Electronics Co., Ltd. | Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell |
| US20060092689A1 (en) | 2004-11-04 | 2006-05-04 | Daniel Braun | Reference current source for current sense amplifier and programmable resistor configured with magnetic tunnel junction cells |
| US7035141B1 (en) | 2004-11-17 | 2006-04-25 | Spansion Llc | Diode array architecture for addressing nanoscale resistive memory arrays |
| US7391064B1 (en) | 2004-12-01 | 2008-06-24 | Spansion Llc | Memory device with a selection element and a control line in a substantially similar layer |
| US7487320B2 (en) | 2004-12-15 | 2009-02-03 | International Business Machines Corporation | Apparatus and system for dynamically allocating main memory among a plurality of applications |
| US8217490B2 (en) | 2005-05-09 | 2012-07-10 | Nantero Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
| US8183665B2 (en) | 2005-11-15 | 2012-05-22 | Nantero Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
| EP1729303B1 (en) | 2005-06-03 | 2010-12-15 | STMicroelectronics Srl | Method for multilevel programming of phase change memory cells using a percolation algorithm |
| US7433247B2 (en) | 2005-09-26 | 2008-10-07 | Macronix International Co., Ltd. | Method and circuit for reading fuse cells in a nonvolatile memory during power-up |
| US7701038B2 (en) | 2005-10-31 | 2010-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-gain vertex lateral bipolar junction transistor |
| US8115280B2 (en) | 2005-10-31 | 2012-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Four-terminal gate-controlled LVBJTs |
| US20070132049A1 (en)* | 2005-12-12 | 2007-06-14 | Stipe Barry C | Unipolar resistance random access memory (RRAM) device and vertically stacked architecture |
| US7728384B2 (en) | 2006-05-30 | 2010-06-01 | Macronix International Co., Ltd. | Magnetic random access memory using single crystal self-aligned diode |
| US7495947B2 (en) | 2006-07-31 | 2009-02-24 | Sandisk 3D Llc | Reverse bias trim operations in non-volatile memory |
| US20080094885A1 (en)* | 2006-10-24 | 2008-04-24 | Macronix International Co., Ltd. | Bistable Resistance Random Access Memory Structures with Multiple Memory Layers and Multilevel Memory States |
| JP4577695B2 (en) | 2006-11-07 | 2010-11-10 | エルピーダメモリ株式会社 | Semiconductor memory device and manufacturing method of semiconductor memory device |
| US7436695B2 (en) | 2006-11-21 | 2008-10-14 | Infineon Technologies Ag | Resistive memory including bipolar transistor access devices |
| CN101271881A (en) | 2007-03-20 | 2008-09-24 | 联华电子股份有限公司 | Anti-fuse and memory cell without causing non-linear current after fusing |
| US7802057B2 (en) | 2007-12-27 | 2010-09-21 | Intel Corporation | Priority aware selective cache allocation |
| JP4482039B2 (en) | 2008-01-11 | 2010-06-16 | 株式会社東芝 | Resistance change memory |
| US7859043B2 (en) | 2008-02-25 | 2010-12-28 | Tower Semiconductor Ltd. | Three-terminal single poly NMOS non-volatile memory cell |
| US20090230446A1 (en) | 2008-03-17 | 2009-09-17 | Technology Alliance Group, Inc. | Semiconductor device and bypass capacitor module |
| JP5371274B2 (en) | 2008-03-27 | 2013-12-18 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US8154005B2 (en) | 2008-06-13 | 2012-04-10 | Sandisk 3D Llc | Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars |
| US20100091546A1 (en) | 2008-10-15 | 2010-04-15 | Seagate Technology Llc | High density reconfigurable spin torque non-volatile memory |
| US20100108980A1 (en) | 2008-11-03 | 2010-05-06 | Industrial Technology Research Institute | Resistive memory array |
| KR20100064715A (en) | 2008-12-05 | 2010-06-15 | 삼성전자주식회사 | Nonvolatile memory device using variable resistive element |
| US8089137B2 (en) | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
| US8305790B2 (en) | 2009-03-16 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical anti-fuse and related applications |
| US8488362B2 (en) | 2009-04-29 | 2013-07-16 | Macronix International Co., Ltd. | Graded metal oxide resistance based semiconductor memory device |
| US8168538B2 (en) | 2009-05-26 | 2012-05-01 | Macronix International Co., Ltd. | Buried silicide structure and method for making |
| US8154904B2 (en) | 2009-06-19 | 2012-04-10 | Sandisk 3D Llc | Programming reversible resistance switching elements |
| KR20110061912A (en) | 2009-12-02 | 2011-06-10 | 삼성전자주식회사 | Nonvolatile memory cell and nonvolatile memory device including same |
| US8589851B2 (en) | 2009-12-15 | 2013-11-19 | Memoir Systems, Inc. | Intelligent memory system compiler |
| US8547720B2 (en) | 2010-06-08 | 2013-10-01 | Sandisk 3D Llc | Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines |
| US8488359B2 (en) | 2010-08-20 | 2013-07-16 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices |
| US9025357B2 (en) | 2010-08-20 | 2015-05-05 | Shine C. Chung | Programmable resistive memory unit with data and reference cells |
| US9251893B2 (en) | 2010-08-20 | 2016-02-02 | Shine C. Chung | Multiple-bit programmable resistive memory using diode as program selector |
| US9019742B2 (en) | 2010-08-20 | 2015-04-28 | Shine C. Chung | Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory |
| US8488364B2 (en) | 2010-08-20 | 2013-07-16 | Shine C. Chung | Circuit and system of using a polysilicon diode as program selector for resistive devices in CMOS logic processes |
| US9042153B2 (en) | 2010-08-20 | 2015-05-26 | Shine C. Chung | Programmable resistive memory unit with multiple cells to improve yield and reliability |
| US20120047322A1 (en) | 2010-08-20 | 2012-02-23 | Chung Shine C | Method and System of Using One-Time Programmable Memory as Multi-Time Programmable in Code Memory of Processors |
| US9070437B2 (en) | 2010-08-20 | 2015-06-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink |
| US8804398B2 (en) | 2010-08-20 | 2014-08-12 | Shine C. Chung | Reversible resistive memory using diodes formed in CMOS processes as program selectors |
| US8913449B2 (en) | 2012-03-11 | 2014-12-16 | Shine C. Chung | System and method of in-system repairs or configurations for memories |
| US8988965B2 (en) | 2010-11-03 | 2015-03-24 | Shine C. Chung | Low-pin-count non-volatile memory interface |
| US9496265B2 (en) | 2010-12-08 | 2016-11-15 | Attopsemi Technology Co., Ltd | Circuit and system of a high density anti-fuse |
| US8848423B2 (en) | 2011-02-14 | 2014-09-30 | Shine C. Chung | Circuit and system of using FinFET for building programmable resistive devices |
| US8607019B2 (en) | 2011-02-15 | 2013-12-10 | Shine C. Chung | Circuit and method of a memory compiler based on subtractive approach |
| US9136261B2 (en) | 2011-11-15 | 2015-09-15 | Shine C. Chung | Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection |
| JP5293800B2 (en) | 2011-12-08 | 2013-09-18 | 第一精工株式会社 | Electrical connector |
| US8861249B2 (en) | 2012-02-06 | 2014-10-14 | Shine C. Chung | Circuit and system of a low density one-time programmable memory |
| US9007804B2 (en) | 2012-02-06 | 2015-04-14 | Shine C. Chung | Circuit and system of protective mechanisms for programmable resistive memories |
| US8917533B2 (en) | 2012-02-06 | 2014-12-23 | Shine C. Chung | Circuit and system for testing a one-time programmable (OTP) memory |
| US9076526B2 (en) | 2012-09-10 | 2015-07-07 | Shine C. Chung | OTP memories functioning as an MTP memory |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040113183A1 (en)* | 2002-12-13 | 2004-06-17 | Ilya Karpov | Isolating phase change memory devices |
| US20040264244A1 (en)* | 2003-06-12 | 2004-12-30 | Sharp Kabushiki Kaisha | Nonvolatile semiconductor memory device and control method thereof |
| US20060108625A1 (en)* | 2004-11-23 | 2006-05-25 | Moon-Sook Lee | Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated |
| US20090097300A1 (en)* | 2005-12-27 | 2009-04-16 | Kazuya Ishihara | Variable resistance element, its manufacturing method and semiconductor memory device comprising the same |
| US20070267675A1 (en)* | 2006-05-19 | 2007-11-22 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices including oxygen-deficient metal oxide layers and methods of manufacturing the same |
| US20090272958A1 (en)* | 2008-05-02 | 2009-11-05 | Klaus-Dieter Ufert | Resistive Memory |
| Publication number | Publication date |
|---|---|
| TW201220566A (en) | 2012-05-16 |
| CN102376359A (en) | 2012-03-14 |
| CN102522499A (en) | 2012-06-27 |
| CN102376360B (en) | 2015-03-04 |
| CN102522499B (en) | 2014-09-24 |
| TW201225219A (en) | 2012-06-16 |
| TW201214430A (en) | 2012-04-01 |
| TWI445137B (en) | 2014-07-11 |
| TWI479487B (en) | 2015-04-01 |
| US8804398B2 (en) | 2014-08-12 |
| CN102376360A (en) | 2012-03-14 |
| CN102376359B (en) | 2014-10-01 |
| US20120044747A1 (en) | 2012-02-23 |
| Publication | Publication Date | Title |
|---|---|---|
| TWI492433B (en) | Reversible programmable resistive memory and providing method, phase change memory, electronic system | |
| TWI452680B (en) | Phase-change memory, electronics system, reversible resistive memory and method for providing the same | |
| US9305973B2 (en) | One-time programmable memories using polysilicon diodes as program selectors | |
| CN101006517A (en) | Electrical device and method of manufacturing therefor | |
| US10128313B2 (en) | Non-volatile memory device and structure thereof | |
| CN217562572U (en) | Phase change memory |