本發明係有關於一種半導體封裝件之製法，尤指一種避免半導體晶片在製程中偏離原預定位置之半導體封裝件之製法。The present invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating a semiconductor package in which a semiconductor wafer is prevented from deviating from a predetermined position in a process.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能與高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，遂發展出晶圓級封裝(Wafer Level Packaging，WLP)的技術。With the booming electronics industry, electronic products are gradually moving toward versatility and high performance. In order to meet the packaging requirements for semiconductor package miniaturization, Wafer Level Packaging (WLP) technology was developed.
第1A至1F圖所示者，係習知晶圓級半導體封裝件之製法的剖視圖。1A to 1F are cross-sectional views showing a conventional method of fabricating a wafer level semiconductor package.
如第1A圖所示，首先，提供一承載板10。As shown in FIG. 1A, first, a carrier board 10 is provided.
如第1B圖所示，接著，於該承載板10上形成一熱剝離膠帶(thermal release tape)11。As shown in FIG. 1B, a thermal release tape 11 is then formed on the carrier sheet 10.
如第1C圖所示，貼合複數具有作用面12a之半導體晶片12於該熱剝離膠帶11上，該作用面12a上具有複數電極墊121，且該半導體晶片12係以其作用面12a貼附於該熱剝離膠帶11上。As shown in FIG. 1C, a plurality of semiconductor wafers 12 having an active surface 12a are bonded to the thermal release tape 11, and the active surface 12a has a plurality of electrode pads 121, and the semiconductor wafer 12 is attached by its active surface 12a. On the thermal peeling tape 11.
如第1D圖所示，以模壓(molding)方式於該熱剝離膠帶11上形成封裝膠體13，以使該封裝膠體13完全包覆該半導體晶片12。As shown in FIG. 1D, the encapsulant 13 is formed on the thermal release tape 11 by a molding method so that the encapsulant 13 completely covers the semiconductor wafer 12.
如第1E圖所示，之後進行烘烤步驟，以硬化該封裝膠體13，並使該熱剝離膠帶11失去黏性，進而移除該熱剝離膠帶11與承載板10。As shown in FIG. 1E, a baking step is then performed to harden the encapsulant 13 and the thermal release tape 11 is lost in viscosity, thereby removing the thermal release tape 11 and the carrier sheet 10.
如第1F圖所示，最後，於半導體晶片12之作用面12a及同側之封裝膠體13表面上形成線路層14。後續可視需要進行切單作業(未圖示)，以完成一不具封裝基板之封裝件。As shown in FIG. 1F, finally, the wiring layer 14 is formed on the active surface 12a of the semiconductor wafer 12 and the surface of the encapsulant 13 on the same side. A subsequent singulation operation (not shown) may be performed to complete a package without a package substrate.
惟，前述習知半導體封裝件之製法中，該熱剝離膠帶具有可撓性，其於模壓製程中受熱時會膨脹，造成其上的半導體晶片偏離原本預定位置；此外，該封裝膠體注入封裝用之模具內時，其封裝膠體之流動所產生之側推力更容易使黏附於該熱化離型膠層上之半導體晶片發生偏移。一旦該半導體晶片發生偏移，後續形成之線路層與該半導體晶片之電極墊間的對位將產生困難，進而造成良率過低及產品可靠度不佳等問題。However, in the manufacturing method of the conventional semiconductor package, the thermal release tape has flexibility, which expands when heated during the molding process, causing the semiconductor wafer thereon to deviate from the original predetermined position; in addition, the package is used for injection molding. In the mold, the side thrust generated by the flow of the encapsulant is more likely to cause the semiconductor wafer adhered to the thermal release layer to be offset. Once the semiconductor wafer is shifted, the alignment between the subsequently formed circuit layer and the electrode pads of the semiconductor wafer will be difficult, resulting in problems such as low yield and poor product reliability.
而且，由於封裝膠體之熱膨脹係數不同於承載板之熱膨脹係數，所以在加熱以硬化該封裝膠體後，會使得整體結構翹曲(warpage)，導致後續製程難以進行。Moreover, since the thermal expansion coefficient of the encapsulant is different from the thermal expansion coefficient of the carrier sheet, after heating to harden the encapsulant, the overall structure warpage is caused, which makes subsequent processes difficult to perform.
再者，因為習知之製法必須使用熱剝離膠帶，故無法有效降低製造成本。Furthermore, since the conventional method requires the use of a thermal release tape, the manufacturing cost cannot be effectively reduced.
因此，如何克服上述習知技術的種種問題，實已成為目前業界所急需解決的課題。Therefore, how to overcome the various problems of the above-mentioned prior art has becomeAt present, the industry is in urgent need of solving problems.
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：於第一承載板上形成第一黏著層；將至少一具有相對之作用面與非作用面的半導體晶片以其作用面接置於該第一黏著層上，且該作用面上形成有複數電極墊；於該第一黏著層上形成包覆該半導體晶片的具有相對之第一表面與第二表面之封裝膠體，該第一表面係面向該第一黏著層；對該封裝膠體進行第一切單步驟，以形成貫穿該封裝膠體之第一表面與第二表面的凹槽；藉由第二黏著層於該封裝膠體之第二表面上接置第二承載板；移除該第一承載板與第一黏著層；於該凹槽中填入黏著材；於該封裝膠體之第一表面與黏著材上形成電性連接該電極墊的線路增層結構；以及移除該第二承載板與第二黏著層。In view of the above-mentioned deficiencies of the prior art, the present invention provides a method of fabricating a semiconductor package, comprising: forming a first adhesive layer on a first carrier; and at least one semiconductor wafer having opposing active and non-active surfaces An active surface is disposed on the first adhesive layer, and a plurality of electrode pads are formed on the active surface; and an encapsulant having an opposite first surface and a second surface covering the semiconductor wafer is formed on the first adhesive layer The first surface is facing the first adhesive layer; the first singulation step is performed on the encapsulant to form a groove extending through the first surface and the second surface of the encapsulant; and the second adhesive layer is disposed thereon Attaching a second carrier to the second surface of the encapsulant; removing the first carrier and the first adhesive layer; filling the recess with the adhesive; forming on the first surface of the encapsulant and the adhesive Electrically connecting the line build-up structure of the electrode pad; and removing the second carrier plate and the second adhesive layer.
於前述之半導體封裝件之製法中，於移除該第二承載板與第二黏著層之後，復包括進行第二切單步驟，且於移除該第二承載板與第二黏著層之後及於進行該第二切單步驟之前，復包括將該封裝膠體之第二表面接置於一切割用膠帶上，並於進行該第二切單步驟之後，移除該切割用膠帶。In the foregoing method of fabricating a semiconductor package, after removing the second carrier and the second adhesive layer, the second singulation step is performed, and after the second carrier and the second adhesive layer are removed, Before performing the second singulation step, the second surface of the encapsulant is attached to a dicing tape, and after the second singulation step, the dicing tape is removed.
依上所述之半導體封裝件之製法，於接置該第二承載板之後及於移除該第二承載板與第二黏著層之前，復包括於該線路增層結構上覆蓋保護層，且於形成該線路增層結構之後及於移除該第二承載板與第二黏著層之前，復包括於該線路增層結構上形成複數導電元件，且該導電元件係為銲球。According to the manufacturing method of the semiconductor package, after the second carrier is attached and before the second carrier and the second adhesive layer are removed, the protective layer is covered on the circuit build-up structure, and After forming the line build-up structure and before removing the second carrier layer and the second adhesive layer,A plurality of conductive elements are formed on the line build-up structure, and the conductive elements are solder balls.
又於前述之半導體封裝件之製法中，該第一承載板係包括層疊之第一基材與第一剝離層，且該第一剝離層係接觸該第一黏著層，形成該第一基材之材質係為晶圓或玻璃，該第二承載板係包括層疊之第二基材與第二剝離層，且該第二剝離層係接觸該第二黏著層，形成該第二基材之材質係為晶圓或玻璃。In the above method for fabricating a semiconductor package, the first carrier layer includes a first substrate and a first release layer, and the first release layer contacts the first adhesive layer to form the first substrate. The material is a wafer or a glass, the second carrier plate comprises a second substrate and a second release layer, and the second release layer contacts the second adhesive layer to form a material of the second substrate. It is made of wafer or glass.
於本發明之半導體封裝件之製法中，該線路增層結構係為線路重佈層。In the method of fabricating the semiconductor package of the present invention, the line build-up structure is a line redistribution layer.
由上可知，由於本發明係於形成封裝膠體之後，先對該封裝膠體進行切單步驟，如此則能先釋放應力，以改善習知之翹曲情形；此外，因為本發明未使用習知之熱剝離膠帶，故無習知之熱剝離膠帶受熱變形而導致半導體晶片偏移之缺失，進而能增進對位精度、提升良率和產品可靠度且降低製造成本。As can be seen from the above, since the present invention is to perform a singulation step on the encapsulant after forming the encapsulant, the stress can be released first to improve the warpage condition; moreover, since the present invention does not use the conventional thermal stripping Tape, so there is no known thermal peeling tape which is deformed by heat and causes the loss of semiconductor wafer offset, which can improve the alignment accuracy, improve the yield and product reliability, and reduce the manufacturing cost.
10‧‧‧承載板10‧‧‧Bearing board
11‧‧‧熱剝離膠帶11‧‧‧Hot peeling tape
12、22‧‧‧半導體晶片12, 22‧‧‧ semiconductor wafer
12a、22a‧‧‧作用面12a, 22a‧‧‧ action surface
121、221‧‧‧電極墊121, 221‧‧‧electrode pads
13‧‧‧封裝膠體13‧‧‧Package colloid
14‧‧‧線路層14‧‧‧Line layer
20‧‧‧第一承載板20‧‧‧First carrier board
201‧‧‧第一基材201‧‧‧First substrate
202‧‧‧第一剝離層202‧‧‧First peeling layer
21‧‧‧第一黏著層21‧‧‧First adhesive layer
22b‧‧‧非作用面22b‧‧‧Non-active surface
23‧‧‧封裝膠體23‧‧‧Package colloid
23a‧‧‧第一表面23a‧‧‧ first surface
23b‧‧‧第二表面23b‧‧‧ second surface
230a‧‧‧第一凹槽230a‧‧‧first groove
230b‧‧‧第二凹槽230b‧‧‧second groove
24‧‧‧第二黏著層24‧‧‧Second Adhesive Layer
25‧‧‧第二承載板25‧‧‧Second carrier board
251‧‧‧第二基材251‧‧‧Second substrate
252‧‧‧第二剝離層252‧‧‧Second stripping layer
26‧‧‧黏著材26‧‧‧Adhesive
27‧‧‧線路增層結構27‧‧‧Line layering structure
28‧‧‧導電元件28‧‧‧Conductive components
29‧‧‧保護層29‧‧‧Protective layer
30‧‧‧切割用膠帶30‧‧‧Cutting Tape
31‧‧‧鐵圈31‧‧‧iron ring
第1A至1F圖所示者係習知晶圓級半導體封裝件之製法的剖視圖；以及第2A至2N圖所示者係本發明之半導體封裝件之製法的剖視圖。1A to 1F are cross-sectional views showing a method of fabricating a conventional wafer-level semiconductor package; and FIGS. 2A to 2N are cross-sectional views showing a method of fabricating the semiconductor package of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easilyOther advantages and effects of the present invention are understood.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「中」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "in" and "one" are used in this specification for the purpose of description, and are not intended to limit the scope of the invention. Adjustments, where there is no material change, are considered to be within the scope of the invention.
第2A至2N圖所示者，係本發明之半導體封裝件之製法的剖視圖。2A to 2N are cross-sectional views showing a method of fabricating the semiconductor package of the present invention.
如第2A圖所示，於第一承載板20上形成第一黏著層21，該第一承載板20係包括層疊之第一基材201與第一剝離層202，且該第一剝離層202係接觸該第一黏著層21，形成該第一基材201之材質係為晶圓或玻璃。As shown in FIG. 2A, a first adhesive layer 21 is formed on the first carrier 20, and the first carrier 20 includes a first substrate 201 and a first peeling layer 202, and the first peeling layer 202 is formed. The first adhesive layer 21 is contacted, and the material of the first substrate 201 is made of wafer or glass.
如第2B圖所示，將至少一具有相對之作用面22a與非作用面22b的半導體晶片22以其作用面22a接置於該第一黏著層21上，且該作用面22a上形成有複數電極墊221。As shown in FIG. 2B, at least one semiconductor wafer 22 having an opposite active surface 22a and an inactive surface 22b is placed on the first adhesive layer 21 with its active surface 22a, and the active surface 22a is formed with a plurality of Electrode pad 221.
如第2C圖所示，於該第一黏著層21上形成包覆該半導體晶片22的具有相對之第一表面23a與第二表面23b之封裝膠體23，該第一表面23a係面向該第一黏著層21。As shown in FIG. 2C, an encapsulant 23 having an opposite first surface 23a and a second surface 23b covering the semiconductor wafer 22 is formed on the first adhesive layer 21. The first surface 23a faces the first Adhesive layer 21.
如第2D圖所示，對該封裝膠體23進行第一切單步驟，以形成貫穿該封裝膠體23之第一表面23a與第二表面23b的第一凹槽230a。As shown in FIG. 2D, the encapsulant 23 is subjected to a first singulation step to form a first recess 230a extending through the first surface 23a and the second surface 23b of the encapsulant 23.
如第2E圖所示，藉由第二黏著層24於該封裝膠體23之第二表面23b上接置第二承載板25，該第二承載板25係包括層疊之第二基材251與第二剝離層252，且該第二剝離層252係接觸該第二黏著層24，形成該第二基材251之材質係為晶圓或玻璃。As shown in FIG. 2E, the second carrier 25 is attached to the second surface 23b of the encapsulant 23 by the second adhesive layer 24. The second carrier 25 includes the stacked second substrate 251 and the second substrate. The second peeling layer 252 is in contact with the second adhesive layer 24, and the material of the second substrate 251 is made of wafer or glass.
如第2F圖所示，使該第一承載板20之第一剝離層202與第一黏著層21彼此分離，以移除該第一承載板20。As shown in FIG. 2F, the first peeling layer 202 of the first carrier 20 and the first adhesive layer 21 are separated from each other to remove the first carrier 20.
如第2G圖所示，移除該第一黏著層21。The first adhesive layer 21 is removed as shown in FIG. 2G.
如第2H圖所示，於該第一凹槽230a中填入黏著材26。As shown in FIG. 2H, the adhesive material 26 is filled in the first recess 230a.
如第2I圖所示，於該封裝膠體23之第一表面23a與黏著材26上形成電性連接該電極墊221的單層或多層之線路增層結構27，並於該線路增層結構27上形成複數導電元件28，該線路增層結構27可為線路重佈層(RDL)，該導電元件28可為銲球。As shown in FIG. 2I, a single-layer or multi-layer line build-up structure 27 electrically connected to the electrode pad 221 is formed on the first surface 23a of the encapsulant 23 and the adhesive material 26, and the line build-up structure 27 is formed on the line build-up structure 27 A plurality of conductive elements 28 are formed thereon. The line build-up structure 27 can be a line redistribution layer (RDL), which can be a solder ball.
如第2J圖所示，於該線路增層結構27與導電元件28上覆蓋保護層29，該保護層29可為保護膠帶(protective tape)。As shown in FIG. 2J, the wiring layer 27 and the conductive member 28 are covered with a protective layer 29, which may be a protective tape.
如第2K圖所示，使該第二承載板25之第二剝離層252與第二黏著層24彼此分離，以移除該第二承載板25。As shown in FIG. 2K, the second peeling layer 252 of the second carrier 25 and the second adhesive layer 24 are separated from each other to remove the second carrier 25.
如第2L圖所示，移除該第二黏著層24，並將該封裝膠體23之第二表面23b接置於一切割用膠帶30上，且移除該保護層29，該切割用膠帶30可固定於一鐵圈31上。As shown in FIG. 2L, the second adhesive layer 24 is removed, and the second surface 23b of the encapsulant 23 is placed on a cutting tape 30, and moved.In addition to the protective layer 29, the cutting tape 30 can be fixed to an iron ring 31.
如第2M圖所示，利用雷射進行第二切單步驟，以形成貫穿該封裝膠體23與線路增層結構27的第二凹槽230b。As shown in FIG. 2M, a second singulation step is performed using a laser to form a second recess 230b extending through the encapsulant 23 and the line build-up structure 27.
如第2N圖所示，移除該切割用膠帶30與鐵圈31，而得到至少一半導體封裝件。As shown in FIG. 2N, the dicing tape 30 and the iron ring 31 are removed to obtain at least one semiconductor package.
綜上所述，由於本發明係於形成封裝膠體之後，先對該封裝膠體進行切單步驟，如此則能先釋放應力，以改善習知之翹曲情形；此外，因為本發明未使用習知之熱剝離膠帶，故無習知之熱剝離膠帶受熱變形而導致半導體晶片偏移之缺失，進而能增進對位精度、提升良率和產品可靠度且降低製造成本。In summary, since the present invention is to perform a singulation step on the encapsulant after forming the encapsulant, the stress can be released first to improve the conventional warping condition; moreover, because the present invention does not use the conventional heat Since the tape is peeled off, there is no known thermal peeling tape which is thermally deformed to cause a loss of semiconductor wafer offset, thereby improving alignment accuracy, improving yield and product reliability, and reducing manufacturing cost.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
22‧‧‧半導體晶片22‧‧‧Semiconductor wafer
22a‧‧‧作用面22a‧‧‧Action surface
22b‧‧‧非作用面22b‧‧‧Non-active surface
221‧‧‧電極墊221‧‧‧electrode pads
23‧‧‧封裝膠體23‧‧‧Package colloid
23a‧‧‧第一表面23a‧‧‧ first surface
23b‧‧‧第二表面23b‧‧‧ second surface
27‧‧‧線路增層結構27‧‧‧Line layering structure
28‧‧‧導電元件28‧‧‧Conductive components
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| TW102117715ATWI488275B (en) | 2013-05-20 | 2013-05-20 | Method for manufacturing semiconductor package |
| CN201310202960.1ACN104183504B (en) | 2013-05-20 | 2013-05-28 | Method for manufacturing semiconductor package |
| Application Number | Priority Date | Filing Date | Title |
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| TW102117715ATWI488275B (en) | 2013-05-20 | 2013-05-20 | Method for manufacturing semiconductor package |
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| TW201445689A TW201445689A (en) | 2014-12-01 |
| TWI488275Btrue TWI488275B (en) | 2015-06-11 |
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| TW102117715ATWI488275B (en) | 2013-05-20 | 2013-05-20 | Method for manufacturing semiconductor package |
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| TW (1) | TWI488275B (en) |
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