本發明係有關於半導體裝置，特別係有關於一種維持焊接定位之覆晶封裝構造。The present invention relates to semiconductor devices, and more particularly to a flip chip package structure for maintaining solder positioning.
在半導體產業中，以往的封裝方式中是將晶片設置於基板上，再利用打線技術(wire-bond)連接晶片與基板，並完成兩者之間的電性連接關係。而覆晶封裝技術(Flip-Chip)是一種先進的晶片封裝技術，有別於過去晶片封裝的方式，是在晶片主動面上設置凸塊，例如銲料凸塊或銲球，之後再將晶片翻轉過來使其主動面朝向基板，利用凸塊本身電性連接晶片與基板，藉此縮短了晶片與基板之間的傳輸距離，達到更優於打線連接的電性性能而逐漸普及。In the semiconductor industry, in the conventional packaging method, a wafer is placed on a substrate, and a wafer and a substrate are connected by a wire-bond, and an electrical connection relationship between the two is completed. Flip-Chip is an advanced chip packaging technology. It is different from the past wafer packaging method in that bumps are placed on the active surface of the wafer, such as solder bumps or solder balls, and then the wafer is flipped. The active surface is directed toward the substrate, and the bump itself is electrically connected to the substrate and the substrate, thereby shortening the transmission distance between the wafer and the substrate, and achieving better electrical performance than the wire bonding connection.
之後，IBM公司首先發展出一種創新的覆晶封裝技術，晶片上凸塊係採用金屬柱取代以往的銲球，另以焊接劑連接晶片上的金屬柱與基板上的接墊，在迴焊時不會有以往銲球成球的形狀改變，故金屬柱的間距可容許縮小的更為密集(凸塊間距可達到小於50微米，例如30微米)，達到更高密度或是省略RDL(重配置線路層)的凸塊配置，這種技術便稱之為「金屬柱焊接的晶片連接」，也就是所謂的MPS-C2(Metal Post Solder-Chip Connection)技術。此一MPS-C2相關技術已可見於美國專利US 6,229,220 B1號「Bump structure,bump forming method and package connecting body」。After that, IBM first developed an innovative flip chip packaging technology. The bumps on the wafer replaced the solder balls with metal posts, and the solder paste was used to connect the metal posts on the wafer to the pads on the substrate. There will be no shape change of the ball into the ball in the past, so the spacing of the metal columns can be allowed to shrink more densely (the bump spacing can be less than 50 microns, for example 30 microns), to achieve higher density or to omit RDL (reconfiguration) The bump configuration of the circuit layer is called "metal pillar soldered wafer connection", which is called the MPS-C2 (Metal Post Solder-Chip Connection) technology. This MPS-C2 related art is described in U.S. Patent No. 6,229,220 B1, "Bump structure, bump forming method and package connecting body".
如第1圖所示，一種習知MPS-C2架構的覆晶封裝構造100主要包含一晶片110與一基板120。該晶片110之主動面111上係設有複數個例如金屬柱之凸塊112，用以覆晶接合至該基板120。該基板120係具有複數個接墊121，並且分別對應於該些凸塊112。詳細而言，該些凸塊112係藉由複數個焊接劑130黏合於該些接墊121上，並達成該晶片110與該基板120之電性連接關係。更進一步地，該覆晶封裝構造100係可形成有一封膠體140，用以包覆該些凸塊112、該些接墊121與該些焊接劑130。As shown in FIG. 1 , a conventional flip-chip package structure 100 of the MPS-C2 architecture mainly includes a wafer 110 and a substrate 120 . The active surface 111 of the wafer 110 is provided with a plurality of bumps 112, such as metal posts, for flip-chip bonding to the substrate 120. The substrate 120 has a plurality of pads 121 and corresponding to the bumps 112, respectively. In detail, the bumps 112 are bonded to the pads 121 by a plurality of soldering agents 130, and the electrical connection relationship between the wafers 110 and the substrate 120 is achieved. Further, the flip chip package structure 100 can be formed with a glue body 140 for covering the bumps 112, the pads 121 and the soldering agents 130.
一般來說，傳統的覆晶封裝以及MPS-C2技術都屬於凸塊微間距(fine pitch)的晶片結合，凸塊會具有較為密集的配置。因此，在覆晶接合製程中，會利用機台辨識系統尋找基標進行對位校準，這樣一來會需要用到對位非常精準的機台(可容許位移公差在25微米以內)，方可順利接合該晶片110與該基板120，然高精準度覆晶接合機台本身的成本相當昂貴。此外，即使精準接合，在接合該晶片110與該基板120之後至迴焊步驟之傳輸過程，機台轉換的震動以及焊接劑或助焊劑的溢流也會造成凸塊112焊接到錯誤之接墊121之情形，將導致電性連接失敗，特別運用在MPS-C2產品會有更明顯的產量下降。In general, conventional flip chip packages and MPS-C2 technologies are all bonded to a fine pitch wafer, and the bumps have a denser configuration. Therefore, in the flip chip bonding process, the machine identification system is used to find the base mark for alignment calibration, which requires the use of a very accurate alignment machine (with a tolerance of 25 microns or less). The wafer 110 and the substrate 120 are smoothly bonded, but the cost of the high precision flip chip bonding machine itself is quite expensive. In addition, even with precise bonding, after the wafer 110 and the substrate 120 are bonded to the transfer process, the vibration of the machine conversion and the overflow of the solder or flux may cause the bumps 112 to be soldered to the wrong pads. In the case of 121, it will lead to the failure of electrical connection, especially in the MPS-C2 product, there will be more obvious production decline.
為了解決上述之問題，本發明之主要目的係在於一種維持焊接定位之覆晶封裝構造，使基標有對位時自動晶片定位之作用並維持至迴焊步驟，即使有機械對位誤差以及由晶片接合至迴焊之傳輸過程中仍能使晶片之凸塊正確對準基板之接墊以達到精準焊接，特別運用於MPS-C2(金屬柱焊接的晶片連接)產品有較佳產量。In order to solve the above problems, the main object of the present invention is to provide a flip chip package structure for maintaining solder positioning, so that the base mark has the function of automatic wafer positioning when it is aligned and maintains to the reflow step, even if there is mechanical alignment error and The wafer bonding to reflow transfer process can still correctly align the bumps of the wafer with the pads of the substrate for precision soldering, especially for MPS-C2 (metal pillar soldered wafer connections) products with better yield.
本發明之次一目的係在於提供一種維持焊接定位之覆晶封裝構造，能在對位與迴焊時在晶片之凸塊與基板之接墊之間維持一間隙，以避免焊接劑被擠壓而溢出，並可提供晶片與基板之間較佳的水平度，特別運用於MPS-C2(金屬柱焊接的晶片連接)產品有較佳可靠度。A second object of the present invention is to provide a flip chip package structure for maintaining solder positioning, which can maintain a gap between the bumps of the wafer and the pads of the substrate during alignment and reflow to prevent the solder from being squeezed. The overflow, and can provide a better level of the wafer and the substrate, especially for MPS-C2 (metal pillar soldered wafer connection) products have better reliability.
本發明之再一目的係在於提供一種維持焊接定位之覆晶封裝構造，能達到在低溫或常溫下進行晶片與基板之間的對位再予以迴焊達到焊接固定之功效。A further object of the present invention is to provide a flip chip package structure for maintaining solder positioning, which can achieve the effect of re-welding between the wafer and the substrate at a low temperature or a normal temperature to achieve solder bonding.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種維持焊接定位之覆晶封裝構造，主要包含一晶片以及一基板。該晶片於其主動面上係設有複數個凸塊與至少一浮突狀基標。該基板係具有複數個接墊與至少一基標座，該基標座係具有一凹陷基標圖案，係對應於該浮突狀基標，當該晶片對位設置於該基板上，該浮突狀基標係鑲埋於該凹陷基標圖案內，俾使該些凸塊對準於該些接墊。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a flip chip package structure for maintaining solder positioning, which mainly comprises a wafer and a substrate. The wafer is provided with a plurality of bumps and at least one embossed base on its active surface. The substrate has a plurality of pads and at least one base. The base has a recessed base pattern corresponding to the embossed base. When the wafer is aligned on the substrate, the floating The protruding base marks are embedded in the recessed base mark pattern, so that the bumps are aligned with the pads.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之覆晶封裝構造中，該凹陷基標圖案內係可設有複數個第一導滑斜壁，以利該浮突狀基標之導滑定位。In the above flip chip package structure, the plurality of first guide sliding walls may be disposed in the recessed base mark pattern to facilitate the guide sliding positioning of the embossed base.
在前述之覆晶封裝構造中，該凹陷基標圖案係可為半錐凹穴，而該浮突狀基標係可具有對應之複數個第二導滑斜壁，以使該浮突狀基標具有一半錐形截面，以完全填滿該凹陷基標圖案。In the foregoing flip chip package structure, the recessed base mark pattern may be a semi-cone recessed hole, and the embossed base mark system may have a corresponding plurality of second guide sliding inclined walls to make the embossed base The mark has a semi-conical section to completely fill the recessed base mark pattern.
在前述之覆晶封裝構造中，該浮突狀基標係可位於該晶片之主動面之一角隅。In the foregoing flip chip package configuration, the embossed base label can be located at one corner of the active face of the wafer.
在前述之覆晶封裝構造中，該浮突狀基標與該基標座之嵌埋結合厚度係可不小於該些凸塊之高度。In the above flip chip package structure, the buried bonding thickness of the embossed base and the base can be not less than the height of the bumps.
在前述之覆晶封裝構造中，可另包含有複數個焊接劑，係焊接該些凸塊至該些接墊。In the above flip chip package structure, a plurality of soldering agents may be further included, and the bumps are soldered to the pads.
在前述之覆晶封裝構造中，該些凸塊係可為不迴焊變形之金屬柱，以構成為MPS-C2封裝型態。In the above flip chip package structure, the bumps may be metal pillars that are not reflow-deformed to form an MPS-C2 package.
在前述之覆晶封裝構造中，該浮突狀基標係可複數個對稱地相對於該些凸塊位於該晶片之主動面周邊。In the foregoing flip chip package structure, the embossed base label may be symmetrically positioned relative to the bumps at the periphery of the active surface of the wafer.
在前述之覆晶封裝構造中，該浮突狀基標之頂面形狀係可選自於四方形、條形、三角形與L形之其中之一。In the foregoing flip chip package configuration, the top surface shape of the embossed base may be selected from one of a square, a strip, a triangle, and an L shape.
在前述之覆晶封裝構造中，該浮突狀基標係可與該些凸塊具有相同之高度與材質。In the above flip chip package structure, the embossed base label can have the same height and material as the bumps.
由以上技術方案可以看出，本發明之維持焊接定位之覆晶封裝構造，有以下優點與功效：It can be seen from the above technical solutions that the flip chip package structure for maintaining solder positioning of the present invention has the following advantages and effects:
一、可藉由浮突狀基標與基標座之特定組合關係作為其中一技術手段，由於基標座係具有凹陷基標圖案，係對應於浮突狀基標，當晶片對位設置於基板上，浮突狀基標係鑲埋於凹陷基標圖案內，俾使凸塊對準於接墊。因此，使基標有對位時自動晶片定位之作用並維持至迴焊步驟，即使有機械對位誤差以及由晶片接合至迴焊之傳輸過程中仍能使晶片之凸塊正確對準基板之接墊以達到精準焊接，特別運用於MPS-C2(金屬柱焊接的晶片連接)產品有較佳產量。1. A specific combination of the embossed base and the base can be used as one of the technical means, since the base frame has a concave base mark, corresponding to the embossed base, when the wafer is aligned On the substrate, the embossed base mark is embedded in the recessed base mark pattern, so that the bumps are aligned with the pads. Therefore, the base mark has the function of automatic wafer positioning when it is aligned and is maintained until the reflow step, even if there is mechanical alignment error and the bump of the wafer is correctly aligned with the substrate during the transfer from wafer bonding to reflow. The pads are used for precision soldering, especially for MPS-C2 (wafer bonding for metal post soldering) products with better yield.
二、可藉由浮突狀基標與基標座之特定組合關係作為其中一技術手段，由於浮突狀基標與基標座之嵌埋結合厚度係不小於凸塊之高度，故能在對位與迴焊時在晶片之凸塊與基板之接墊之間維持一間隙，以避免焊接劑被擠壓而溢出，並可提供晶片與基板之間較佳的水平度，特別運用於MPS-C2(金屬柱焊接的晶片連接)產品有較佳可靠度。Second, the specific combination relationship between the embossed base and the base can be used as one of the technical means. Since the thickness of the embedded combination of the embossed base and the base is not less than the height of the bump, Maintain a gap between the bumps of the wafer and the pads of the substrate during the reflow and reflow to avoid the solder being squeezed out and provide better level between the wafer and the substrate, especially for MPS -C2 (metal pillar soldered wafer connection) products have better reliability.
三、可藉由浮突狀基標與基標座之特定組合關係作為其中一技術手段，能達到在低溫或常溫下進行晶片與基板之間的對位再予以迴焊達到焊接固定之功效。Third, the specific combination relationship between the embossed base and the base can be used as one of the technical means, and the effect of re-welding between the wafer and the substrate at the low temperature or normal temperature to achieve the welding fixation can be achieved.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之第一具體實施例，一種維持焊接定位之覆晶封裝構造舉例說明於第2圖之截面示意圖、第3A至3C圖在覆晶接合過程中元件截面示意圖以及第4A與4B圖繪示其晶片與基板之局部上視示意圖。該維持焊接定位之覆晶封裝構造200係主要包含一晶片210以及一基板220。According to a first embodiment of the present invention, a flip chip package structure for maintaining solder positioning is illustrated in a cross-sectional view in FIG. 2, a cross-sectional view of the device in the flip chip bonding process, and FIGS. 4A and 4B in FIGS. 3A to 3C. A partial top view of the wafer and the substrate is shown. The flip chip package structure 200 for maintaining solder positioning mainly includes a wafer 210 and a substrate 220.
請參閱第2圖所示，該晶片210之主動面211上係設有複數個凸塊212與至少一浮突狀基標213。詳細而言，該主動面211係可另形成有複數個銲墊(圖中未繪出)，用以連接該些凸塊212，在銲墊與凸塊之間另可設置凸塊下金屬層(圖中未繪出)，以避免凸塊內成份的金屬擴散。在本實施例中，該晶片210係可為一集成電路(integrated circuit,IC)的載體，由一晶圓(wafer)分割而成。該浮突狀基標213之作用係供機台辨識系統辨認以作為對位參考點。在本發明中利用該浮突狀基標213之浮突狀結構配合基板上設置基標座更具有對位時晶片固定之作用。較佳地，該浮突狀基標213係可複數個對稱地相對於該些凸塊212位於該晶片210之主動面211周邊，以不影響該些凸塊212的配置位置，並且具有在迴焊時發揮間隔維持之作用。Referring to FIG. 2 , the active surface 211 of the wafer 210 is provided with a plurality of bumps 212 and at least one embossed base 213 . In detail, the active surface 211 may be further formed with a plurality of pads (not shown) for connecting the bumps 212, and a lower under bump metal layer may be disposed between the pads and the bumps. (not shown) to avoid metal diffusion of the components in the bump. In this embodiment, the wafer 210 can be an integrated circuit (IC) carrier, which is divided by a wafer. The function of the embossed base 213 is recognized by the machine identification system as a reference point of reference. In the present invention, the embossed structure of the embossed base 213 is used to cooperate with the substrate on the substrate to further have the effect of wafer fixation during alignment. Preferably, the embossed base 213 is symmetrically located at a periphery of the active surface 211 of the wafer 210 with respect to the bumps 212 so as not to affect the arrangement positions of the bumps 212, and has a back The role of interval maintenance is maintained during welding.
該基板220係具有複數個接墊221與至少一基標座222，該基標座222係具有一凹陷基標圖案223，係對應於該浮突狀基標213，當該晶片210對位設置於該基板220上，該浮突狀基標213係鑲埋於該凹陷基標圖案223內，俾使該些凸塊212對準於該些接墊221。具體而言，該基板220係可為一印刷電路板(printed circuit board,PCB)，作為整體封裝結構之主要承載與電性連接之媒介物。具體而言，由於設置了多個浮突狀基標213於該主動面211上，同樣地，該基板220之基標座222亦設有多個圖案對應之凹陷基標圖案223，故能在該晶片210與該基板220之間建立一種對位時晶片固定之關係。The substrate 220 has a plurality of pads 221 and at least one base 222. The base 222 has a recessed base mark 223 corresponding to the embossed base 213. When the wafer 210 is aligned The embossed base 213 is embedded in the recessed base mark 223 on the substrate 220 to align the bumps 212 with the pads 221 . Specifically, the substrate 220 can be a printed circuit board (PCB) as a main carrier and electrical connection medium of the overall package structure. Specifically, since a plurality of embossed bases 213 are disposed on the active surface 211, the base base 222 of the substrate 220 is also provided with a plurality of recessed base marks 223 corresponding to the pattern, so A relationship between the wafer 210 and the substrate 220 to establish a wafer alignment during alignment is established.
此外，該覆晶封裝構造200可另包含有複數個焊接劑230，係焊接該些凸塊212至該些接墊221。在一較佳實施例中，該些焊接劑230係可選用一般所使用符合規定之無鉛銲料或低溫銲料，在覆晶接合之前係可預先沾著於該晶片210之該些凸塊212之頂面(即遠離該晶片210並平行於該主動面211之凸塊表面)。在一較佳實施例中，該些凸塊212係可為不迴焊變形之金屬柱，例如金柱、銅柱或高溫錫鉛柱，以構成為MPS-C2(金屬柱焊接的晶片連接)封裝型態。換言之，該些凸塊212之熔點應較高於使該些焊接劑230熔化之迴焊溫度，故不會在迴焊製程中導致該些凸塊212產生變形或成球之情況。In addition, the flip chip package structure 200 may further include a plurality of soldering agents 230 for soldering the bumps 212 to the pads 221 . In a preferred embodiment, the soldering agents 230 may be selected from commonly used lead-free solders or low-temperature solders, which may be pre-sticked to the tops of the bumps 212 of the wafer 210 prior to flip chip bonding. The face (ie, the surface of the bump away from the wafer 210 and parallel to the active face 211). In a preferred embodiment, the bumps 212 can be metal pillars that are not reflowed, such as gold pillars, copper pillars, or high temperature tin-lead pillars, to form MPS-C2 (metal pillar soldered wafer connections). Package type. In other words, the melting points of the bumps 212 should be higher than the reflow temperature at which the soldering agents 230 are melted, so that the bumps 212 are not deformed or balled during the reflow process.
特別是，該浮突狀基標213係可與該些凸塊212具有相同之高度與材質，故可同時電鍍形成以簡化製程。在本實施例中，該些凸塊212、該浮突狀基標213與該基標座222之材質係皆可選自於銅(Cu)，其中該浮突狀基標213可為一銅柱(Cu post)，而該基標座222亦可為一銅穴(Cu cave)凹座。In particular, the embossed base 213 can have the same height and material as the bumps 212, so that it can be plated simultaneously to simplify the process. In this embodiment, the bumps 212, the embossed base 213, and the base of the base 222 may be selected from copper (Cu), wherein the embossed base 213 may be a copper. A post (Cu post), and the base base 222 can also be a Cu cave recess.
較佳地，如第3A圖所示，該凹陷基標圖案223內係可設有複數個第一導滑斜壁224，以利該浮突狀基標213之導滑定位，而該浮突狀基標213僅需要能定位的效果即可，不需要對應之形狀。具體而言，該些第一導滑斜壁224之傾斜角度係可介於45度至90度之間，在覆晶接合時更有利於該浮突狀基標213沿著該些第一導滑斜壁224滑至預定位置，以使該晶片210順利精準定位至該基板220之上方。因此，在覆晶接合製程中可以選用對位精確度較差的機台，也能輕易地利用該浮突狀基標213對準於該基標座222，達到該些凸塊212對準於該些接墊221。如第3C圖所示，當該浮突狀基標213鑲埋至該凹陷基標圖案223內，即該浮突狀基標213的頂面重疊至該凹陷基標圖案223之底面，便能準確地將該晶片210對位設置於該基板220上，故機台可容許公差得以擴大。Preferably, as shown in FIG. 3A, the recessed base mark pattern 223 may be provided with a plurality of first sliding inclined walls 224 to guide the guiding and positioning of the floating protruding bases 213, and the floating protrusions The shape base 213 only needs to be able to be positioned, and does not require a corresponding shape. Specifically, the inclination angles of the first sliding inclined walls 224 may be between 45 degrees and 90 degrees, and the floating guiding bases 213 are more favorable along the first guiding layers during the flip chip bonding. The sliding inclined wall 224 slides to a predetermined position to smoothly and accurately position the wafer 210 above the substrate 220. Therefore, in the flip chip bonding process, a machine with poor alignment accuracy can be selected, and the embossed base 213 can be easily aligned with the base block 222 to achieve alignment of the bumps 212. Some pads 221. As shown in FIG. 3C, when the embossed base 213 is embedded in the recessed base mark 223, that is, the top surface of the embossed base 213 is overlapped to the bottom surface of the recessed base mark 223, The wafer 210 is accurately positioned on the substrate 220, so that the tolerance of the machine can be expanded.
更具體地，該維持焊接定位之覆晶封裝構造200係可另包含一封膠體240，以包覆該些凸塊212、該些接墊221與該基標座222。在一較佳實施例中，該封膠體240係可為一底部填充膠(underfill)，故能利用底部填充膠的高流動性，用以避免該晶片210與該基板220之間形成空隙。More specifically, the flip chip package structure 200 for maintaining the solder positioning may further include a glue body 240 to cover the bumps 212, the pads 221 and the base block 222. In a preferred embodiment, the encapsulant 240 can be an underfill, so that the high fluidity of the underfill can be utilized to avoid void formation between the wafer 210 and the substrate 220.
因此，本發明藉由浮突狀基標與基標座之特定組合關係作為其中一技術手段，使得該浮突狀基標213具有對位與晶片固定之雙重作用，即使有機械對位誤差以及由該晶片210接合之後至迴焊之間的傳輸過程中，仍然能使該晶片210之該些凸塊212正確對準該基板220之對應之接墊221以達到精準焊接，特別運用於MPS-C2(金屬柱焊接的晶片連接)產品有較佳產量。這是因為本發明之該基標座222係具有該凹陷基標圖案223，能夠供該浮突狀基標213之鑲埋，機台轉換的震動以及該些焊接劑230(或助焊劑)的溢流都不會造成該晶片210在焊接之前與迴焊中的位偏移。Therefore, the present invention has as a technical means by the specific combination relationship between the embossed base and the base, so that the embossed base 213 has the dual function of alignment and wafer fixation, even if there is mechanical alignment error and During the transfer from the bonding of the wafer 210 to the reflow process, the bumps 212 of the wafer 210 can still be correctly aligned with the corresponding pads 221 of the substrate 220 for precision soldering, especially for MPS- C2 (metal pillar soldered wafer connections) products have better yields. This is because the base base 222 of the present invention has the recessed base mark pattern 223, which can be used for the embedding of the embossed base 213, the vibration of the machine conversion, and the solder 230 (or flux). The overflow does not cause a shift in the position of the wafer 210 prior to soldering and reflow.
此外，較佳地，該浮突狀基標213與該基標座222之嵌埋結合厚度係可不小於該些凸塊212之高度，以在該晶片210之該些凸塊212與該基板220之該些接墊221之間維持一間隙，也就是說，該晶片210與該基板220之間的覆晶間距是可由該浮突狀基標213與該基標座222所控制決定的，而達到該晶片210與該基板220之間的水平。藉由在對位與迴焊時在該晶片210之該些凸塊212與該基板220之該些接墊221之間維持一間隙，以避免該些焊接劑230被擠壓而溢出，並可提供該晶片210與該基板220之間較佳的水平度。In addition, the embedded bonding thickness of the embossed base 213 and the base 222 is not less than the height of the bumps 212 to cover the bumps 212 and the substrate 220 of the wafer 210. A gap is maintained between the pads 221, that is, the flip-chip spacing between the wafer 210 and the substrate 220 can be controlled by the embossed base 213 and the base 222, and A level between the wafer 210 and the substrate 220 is reached. By maintaining a gap between the bumps 212 of the wafer 210 and the pads 221 of the substrate 220 during alignment and reflow, the solder 230 is prevented from being squeezed and overflowed. A preferred level of level between the wafer 210 and the substrate 220 is provided.
本發明還揭示該維持焊接定位之覆晶封裝構造200的一種可行但非限定的製造方法舉例說明於第3A至3C圖在製程中元件截面示意圖，用以清楚彰顯本發明之其中一功效，其詳細步驟說明如下所示。The present invention also discloses a possible but non-limiting manufacturing method for the flip chip package structure 200 for maintaining solder positioning. The cross-sectional schematic view of the components in the process of FIGS. 3A to 3C is used to clearly demonstrate one of the effects of the present invention. The detailed steps are explained below.
首先，請參閱第3A圖所示，執行一覆晶接合之對位與熱壓合步驟，以使該晶片210對準於該基板220之上方。當該浮突狀基標213對準於該凹陷基標圖案223，該些凸塊212即對準於該些接墊221。在本步驟中，當該晶片210對位完成並往下壓合至該基板220時，可利用該些第一導滑斜壁224提供之導滑作用，該浮突狀基標213沿著該凹陷基標圖案223之第一導滑斜壁224達到自動對位。本步驟中，該些焊接劑230將可沾附至該些接墊221，達到初步焊接或尚未焊接即可。First, referring to FIG. 3A, a flip chip bonding alignment and thermal lamination step is performed to align the wafer 210 above the substrate 220. When the embossed base 213 is aligned with the recessed base mark 223, the bumps 212 are aligned with the pads 221 . In this step, when the wafer 210 is aligned and pressed down to the substrate 220, the guiding effect provided by the first sliding inclined walls 224 can be utilized, and the embossed base 213 is along the The first guide slant wall 224 of the recessed base mark pattern 223 reaches the automatic alignment. In this step, the soldering agents 230 will be adhered to the pads 221 for preliminary soldering or not yet soldered.
請參閱第3B圖所示，如為未焊接狀態，在覆晶接合之對位之後至迴焊步驟之前的傳輸過程，可先藉由一上夾具10夾持該晶片210，並且一下夾具20夾持該基板220，以上下夾合該晶片210與該基板220。由於該浮突狀基標213已鑲埋於該凹陷基標圖案223內，該晶片210不會有位偏移現象，以使該些凸塊212可保持對準於該些接墊221，並且該些焊接劑230可仍保持糊膏狀，尚未燒結成金屬焊接界面。Referring to FIG. 3B, in the unwelded state, after the alignment of the flip chip bonding to the transfer process before the reflow step, the wafer 210 may be first clamped by an upper clamp 10, and the lower clamp 20 is clamped. Holding the substrate 220, the wafer 210 and the substrate 220 are sandwiched above and below. Since the embossed base 213 has been embedded in the recessed base mark 223, the wafer 210 does not have a bit offset phenomenon, so that the bumps 212 can remain aligned with the pads 221, and The solders 230 may remain paste-like and have not yet been sintered into a metal solder interface.
請參閱第3C圖所示，執行覆晶接合之迴焊步驟，該些焊接劑230到達迴焊溫度會熔化，以焊接至該些接墊221。由於該浮突狀基標213係鑲埋於該凹陷基標圖案223內，故該晶片210沒有位偏移，該些焊接劑230便不會被擠壓或溢流外擴，達到精準焊接之功效。在上述迴焊步驟之後，降溫後該些焊接劑230呈固態，作為焊接界面，能穩固地焊接接合該些凸塊212與該些接墊221，使得該晶片210與該基板220之間達成電性連接關係。因此，本發明更進一步能達到在低溫或常溫下進行該晶片210與該基板220之間的對位再予以迴焊達到焊接固定之功效。此外，本發明之維持焊接定位之覆晶封裝構造200非限定於上述製造方法，亦可以既有的覆晶結合之迴焊或是熱壓合技術予以實施。Referring to FIG. 3C, a reflow process of flip chip bonding is performed, and the solder paste 230 is melted to reach the reflow temperature to be soldered to the pads 221. Since the embossed base 213 is embedded in the recessed base mark 223, the wafer 210 is not displaced, and the solder 230 is not squeezed or overflowed to achieve precise soldering. efficacy. After the reflowing step, the soldering agent 230 is solid after cooling, and as the soldering interface, the bumps 212 and the pads 221 can be firmly soldered to achieve electrical connection between the wafer 210 and the substrate 220. Sexual connection relationship. Therefore, the present invention can further achieve the effect of performing re-reflow between the wafer 210 and the substrate 220 at a low temperature or a normal temperature to achieve solder bonding. Further, the flip chip package structure 200 for maintaining solder positioning of the present invention is not limited to the above-described manufacturing method, and may be implemented by a conventional flip chip bonding reflow or thermocompression bonding technique.
較佳地，如第4A與4B圖所示，該浮突狀基標213係可位於該晶片210之主動面211之一角隅，故該浮突狀基標213係較該些凸塊212更遠離該晶片210之主動面211的中心位置，以方便機台辨識系統快速尋找以進行對位校準。Preferably, as shown in FIGS. 4A and 4B , the embossed base 213 can be located at a corner of the active surface 211 of the wafer 210 , so the embossed base 213 is more than the bumps 212 . It is away from the center position of the active surface 211 of the wafer 210 to facilitate the rapid identification of the machine identification system for alignment calibration.
此外，本發明並不局限浮突狀基標與凸塊之頂面形狀。該浮突狀基標213之頂面形狀係可選自於四方形、條形、三角形與L形之其中之一。在本發明中，無論該浮突狀基標213之頂面形狀為何，甚至是上述頂面形狀之組合，皆能在覆晶接合製程在迴焊時以及迴焊之前的傳輸過程提供機械定位使晶片不位移之功效，以使該晶片210精準地接合於該基板220上。Moreover, the present invention is not limited to the apical shape of the embossed base and the top surface of the bump. The top surface shape of the embossed base 213 may be selected from one of a square, a strip, a triangle, and an L shape. In the present invention, regardless of the shape of the top surface of the embossed base 213, or even the combination of the top surface shapes, mechanical positioning can be provided during the transfer process of the flip chip bonding process during reflow and before reflow. The wafer is not displaced so that the wafer 210 is accurately bonded to the substrate 220.
請參閱第4A與4B圖所示，每一凸塊212之頂面係可為矩形，而使該些凸塊212形成為方柱體。並且，每一接墊221係可為條狀，以分別對應於每一凸塊212。在本實施例中，該浮突狀基標213之頂面形狀係為四方形，並且該凹陷基標圖案223之底面形狀亦為可對應之四方形。所謂的「四方形」係指正方形或矩形，能提供更便利之對位效果。Referring to FIGS. 4A and 4B, the top surface of each of the bumps 212 may be rectangular, and the bumps 212 may be formed as square cylinders. Moreover, each of the pads 221 may be strip-shaped to correspond to each of the bumps 212, respectively. In this embodiment, the top surface shape of the embossed base 213 is square, and the shape of the bottom surface of the recessed base mark 223 is also a corresponding square. The so-called "square" means square or rectangular and can provideMore convenient alignment effect.
請參閱第5A與5B圖所示，在一變化實施例中改變浮突狀基標與凹陷基標圖案之形狀，該浮突狀基標213a、213b之頂面形狀係可為條形，而位於該基板220上之該基標座222亦具有可對應條形之該凹陷基標圖案223a、223b。其中，所謂的「條形」係指具有兩對相互平行的邊且鄰邊不相等之形狀。詳細而言，該浮突狀基標213a與該浮突狀基標213b係可為不同的排列方向，其中該浮突狀基標213a之一長邊係垂直於另一角隅之該浮突狀基標213b之一長邊。並且，如第5B圖所示，該凹陷基標圖案223a與該凹陷基標圖案223b係可分別位於與該浮突狀基標213a與該浮突狀基標213b對應之角隅。因此，在翻轉該晶片210進行對位，該浮突狀基標213a可嵌埋於該凹陷基標圖案223a，該浮突狀基標213b可嵌埋於該凹陷基標圖案223b，毋須考慮該晶片210對位設置於該基板220上之方向性，亦能輕易地藉由該浮突狀基標213與該基標座222達到精準的定位效果。Referring to FIGS. 5A and 5B, in a variant embodiment, the shape of the embossed base mark and the recessed base mark pattern are changed, and the top surface shape of the embossed base marks 213a, 213b may be strip-shaped, and The base base 222 located on the substrate 220 also has the recessed base marks 223a, 223b corresponding to the strip shape. Here, the term "bar" means a shape having two pairs of mutually parallel sides and the adjacent sides are not equal. In detail, the embossed base 213a and the embossed base 213b may be in different alignment directions, wherein one of the embossed bases 213a has a long side that is perpendicular to the other horn. One of the bases 213b has a long side. Further, as shown in FIG. 5B, the recessed base mark pattern 223a and the recessed base mark pattern 223b are respectively located at corners corresponding to the embossed base mark 213a and the embossed base mark 213b. Therefore, in the flipping of the wafer 210 for alignment, the embossed base 213a can be embedded in the recessed base mark 223a, and the embossed base 213b can be embedded in the recessed base mark 223b, without considering the The directionality of the wafer 210 disposed on the substrate 220 can also be easily achieved by the embossed base 213 and the base 222.
請參閱第6A與6B圖所示，每一凸塊212之頂面係可為圓形，而形成為一圓柱體。而每一接墊221係同樣為圓形，以供對應凸塊212之接合。在另一變化實施例中，該浮突狀基標之頂面形狀係可為三角形與L形。具體而言，如第6A圖中，該浮突狀基標213c之頂面形狀為L形，並設置於該晶片210之主動面211之右上方角隅，而該浮突狀基標213d之頂面形狀為三角形，並設置於該晶片210之主動面211之左上方角隅。如第6B圖中，呈L形之該凹陷基標圖案223c係位於圖中左方，而呈三角形之該凹陷基標圖案223d係位於圖中右方。在覆晶接合時翻轉該晶片210進行對位，該浮突狀基標213c可嵌埋於該凹陷基標圖案223c，該浮突狀基標213d可嵌埋於該凹陷基標圖案223d。Referring to FIGS. 6A and 6B, the top surface of each of the bumps 212 may be circular and formed into a cylinder. Each of the pads 221 is also circular in shape for the engagement of the corresponding bumps 212. In another variant embodiment, the top surface of the embossed base can be triangular and L-shaped. Specifically, as shown in FIG. 6A, the top surface of the embossed base 213c has an L shape and is disposed at the upper right corner of the active surface 211 of the wafer 210.The top surface of the embossed base 213d has a triangular shape and is disposed at a left upper corner 主动 of the active surface 211 of the wafer 210. As shown in Fig. 6B, the recessed base mark pattern 223c which is L-shaped is located on the left side in the figure, and the recessed base mark pattern 223d which is triangular is located on the right side in the figure. The wafer 210 is inverted during the flip chip bonding, and the embossed base 213c can be embedded in the recessed base mark 223c, and the embossed base 213d can be embedded in the recessed base mark 223d.
依據本發明之第二具體實施例，另一種維持焊接定位之覆晶封裝構造舉例說明於第7圖之截面示意圖與第8圖之元件截面示意圖。其中與第一實施例相同的主要元件將以相同符號標示，不再詳予贅述。According to a second embodiment of the present invention, another flip chip package structure for maintaining solder positioning is illustrated in a cross-sectional view of FIG. 7 and a cross-sectional view of an element of FIG. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail.
本發明不局限於MPS-C2產品，亦可運用以銲球接合之覆晶封裝構造。請參閱第7圖所示，該維持焊接定位之覆晶封裝構造300係主要包含一晶片210與一基板220。該晶片210於其主動面211上係設有複數個凸塊212與至少一浮突狀基標213。該基板220係具有複數個接墊221與至少一基標座222，該基標座222係具有一凹陷基標圖案223，係對應於該浮突狀基標213，當該晶片210對位設置於該基板220上，該浮突狀基標213係鑲埋於該凹陷基標圖案223內。在本實施例中，該些凸塊212係選自於銲料凸塊與銲球之其中之一，並藉由該些凸塊212本身焊接至該些接墊221，以達成該晶片210與該基板220之電性連接關係。The present invention is not limited to the MPS-C2 product, and a flip chip package structure using solder ball bonding can also be used. Referring to FIG. 7 , the flip chip package structure 300 for maintaining solder positioning mainly includes a wafer 210 and a substrate 220 . The wafer 210 is provided with a plurality of bumps 212 and at least one embossed base 213 on the active surface 211 thereof. The substrate 220 has a plurality of pads 221 and at least one base 222. The base 222 has a recessed base mark 223 corresponding to the embossed base 213. When the wafer 210 is aligned The embossed base 213 is embedded in the recessed base mark pattern 223 on the substrate 220. In this embodiment, the bumps 212 are selected from one of the solder bumps and the solder balls, and are soldered to the pads 221 by the bumps 212 themselves to achieve the wafer 210 and the The electrical connection relationship of the substrate 220.
請參閱第8圖所示，在本實施例中，在覆晶接合過程之對位步驟中，該些接墊221係可預先塗佈有複數個助焊劑350，以利該些凸塊212沾觸至該些接墊221上的助焊劑350。該些凸塊212在迴焊時會熔化成球，進而焊接至該些接墊221。Referring to FIG. 8, in the present embodiment, in the flip chip bonding processIn the alignment step, the pads 221 may be pre-coated with a plurality of fluxes 350 to facilitate the bumps 212 to touch the fluxes 350 on the pads 221 . The bumps 212 are melted into balls during reflow and are soldered to the pads 221.
在本較佳實施例中，該凹陷基標圖案223係可為半錐凹穴，而該浮突狀基標213係可具有對應之複數個第二導滑斜壁314，以使該浮突狀基標213具有一半錐形截面，以完全填滿該凹陷基標圖案223(如第7圖所示)。故該浮突狀基標213與該凹陷基標圖案223係可具有彼此相互對應之形狀，並藉由該些第二導滑斜壁314與該些第一導滑斜壁224之傾斜設計，更有利於該浮突狀基標213滑入至該凹陷基標圖案223，故能在覆晶接合之熱壓合步驟中(即迴焊之前)達到自動固定晶片使其不偏斜位移之功效。並且，在該凹陷基標圖案223內不需要膠填滿也不會產生過大空隙。In the preferred embodiment, the recessed base mark pattern 223 can be a half-cone recessed hole, and the embossed base mark 213 can have a corresponding plurality of second guide sliding inclined walls 314 to make the floating protrusion The base mark 213 has a semi-conical section to completely fill the recessed base mark pattern 223 (as shown in Fig. 7). Therefore, the embossed base 213 and the recessed base 223 have a shape corresponding to each other, and are designed by the inclination of the second slanting wall 314 and the first slanting walls 224. It is more advantageous for the embossed base 213 to slide into the recessed base mark pattern 223, so that the effect of automatically fixing the wafer to be unbiased displacement can be achieved in the thermal compression step of the flip chip bonding (ie, before reflow). Moreover, no excess voids are formed in the recessed base mark pattern 223 without the glue being filled.
在迴焊之過程或之前的傳輸操作時，藉由該浮突狀基標213與該基標座222之設置，當該浮突狀基標213鑲埋於該凹陷基標圖案223內時，該浮突狀基標213與該基標座222之間產生自動導滑至晶片定位之關係，便能使得該些凸塊212準確地焊接於該些接墊221，不會有晶片位移的現象，更可免除上述因銲球彼此碰觸或橋接焊連而造成之短路問題。此外，該浮突狀基標213與該基標座222之嵌埋組合結構亦能在對位與迴焊時在該晶片210與該基板220之間維持一固定的覆晶間隙與水平度，以避免該些凸塊212被擠壓或拉扯而變形，而具有較佳產品可靠度。When the embossed base 213 and the base 222 are disposed during the reflow process or the previous transfer operation, when the embossed base 213 is embedded in the recessed base mark 223, The relationship between the embossed base 213 and the base 222 is automatically guided to the position of the wafer, so that the bumps 212 can be accurately soldered to the pads 221 without wafer displacement. Moreover, the short circuit problem caused by the solder balls touching each other or bridging the solder joints can be eliminated. In addition, the embedded combination structure of the embossed base 213 and the base 222 can maintain a fixed flip-chip gap and level between the wafer 210 and the substrate 220 during alignment and reflow.Degrees to prevent the bumps 212 from being deformed by being squeezed or pulled, and having better product reliability.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
10‧‧‧上夾具10‧‧‧Upper fixture
20‧‧‧下夾具20‧‧‧ Lower fixture
100‧‧‧覆晶封裝構造100‧‧‧Flip chip package structure
110‧‧‧晶片110‧‧‧ wafer
111‧‧‧主動面111‧‧‧Active surface
112‧‧‧凸塊112‧‧‧Bumps
120‧‧‧基板120‧‧‧Substrate
121‧‧‧接墊121‧‧‧ pads
130‧‧‧焊接劑130‧‧‧Solder
140‧‧‧封膠體140‧‧‧ Sealant
200‧‧‧維持焊接定位之覆晶封裝構造200‧‧‧Flip-chip package structure for maintaining solder positioning
210‧‧‧晶片210‧‧‧ wafer
211‧‧‧主動面211‧‧‧ active face
212‧‧‧凸塊212‧‧‧Bumps
213‧‧‧浮突狀基標213‧‧‧Floating base
213a‧‧‧浮突狀基標213a‧‧‧Floating base
213b‧‧‧浮突狀基標213b‧‧‧Floating base
213c‧‧‧浮突狀基標213c‧‧‧Floating base
213d‧‧‧浮突狀基標213d‧‧‧Floating base
220‧‧‧基板220‧‧‧Substrate
221‧‧‧接墊221‧‧‧ pads
222‧‧‧基標座222‧‧‧base base
223‧‧‧凹陷基標圖案223‧‧‧ recessed base mark pattern
223a‧‧‧凹陷基標圖案223a‧‧‧ recessed base mark pattern
223b‧‧‧凹陷基標圖案223b‧‧‧ recessed base mark pattern
223c‧‧‧凹陷基標圖案223c‧‧‧ recessed base mark pattern
223d‧‧‧凹陷基標圖案223d‧‧‧ recessed base mark pattern
224‧‧‧第一導滑斜壁224‧‧‧First sliding sloping wall
230‧‧‧焊接劑230‧‧‧welding agent
240‧‧‧封膠體240‧‧‧ Sealant
300‧‧‧維持焊接定位之覆晶封裝構造300‧‧‧Flip-chip package construction to maintain solder positioning
314‧‧‧第二導滑斜壁314‧‧‧Second guiding sloping wall
350‧‧‧助焊劑350‧‧‧ Flux
第1圖：為習知的覆晶封裝構造之截面示意圖。Fig. 1 is a schematic cross-sectional view showing a conventional flip chip package structure.
第2圖：依據本發明之第一具體實施例的一種維持焊接定位之覆晶封裝構造之截面示意圖。2 is a cross-sectional view showing a flip chip package structure for maintaining solder positioning in accordance with a first embodiment of the present invention.
第3A至3C圖：依據本發明之第一具體實施例的在該覆晶封裝構造之覆晶接合過程中元件截面示意圖。3A to 3C are cross-sectional views showing the elements in the flip chip bonding process of the flip chip package structure in accordance with the first embodiment of the present invention.
第4A與4B圖：依據本發明之第一具體實施例的該覆晶封裝構造之晶片與基板之局部上視示意圖。4A and 4B are partial top views of the wafer and substrate of the flip chip package structure in accordance with the first embodiment of the present invention.
第5A與5B圖：依據本發明之第一具體實施例之一變化例的該覆晶封裝構造之晶片與基板之局部上視示意圖。5A and 5B are partial top views of the wafer and substrate of the flip chip package structure according to a variation of the first embodiment of the present invention.
第6A與6B圖：依據本發明之第一具體實施例之一變化例的該覆晶封裝構造之晶片與基板之局部上視示意圖。6A and 6B are partial top views of the wafer and substrate of the flip chip package structure according to a variation of the first embodiment of the present invention.
第7圖：依據本發明之第二具體實施例的另一種維持焊接定位之覆晶封裝構造之截面示意圖。Figure 7: Another maintenance welding in accordance with a second embodiment of the present inventionA schematic cross-sectional view of a flip chip package structure positioned.
第8圖：依據本發明之第二具體實施例的在該覆晶封裝構造之覆晶接合過程中對位前之元件截面示意圖。Figure 8 is a cross-sectional view of an element prior to alignment in a flip chip bonding process of the flip chip package structure in accordance with a second embodiment of the present invention.
210．．．晶片210. . . Wafer
211．．．主動面211. . . Active surface
212．．．凸塊212. . . Bump
213．．．浮突狀基標213. . . Buoyant base
220．．．基板220. . . Substrate
221．．．接墊221. . . Pad
222．．．基標座222. . . Base base
223．．．凹陷基標圖案223. . . Concave base mark pattern
224．．．第一導滑斜壁224. . . First sliding slope
230．．．焊接劑230. . . Solder
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099102170ATWI480992B (en) | 2010-01-26 | 2010-01-26 | Flip-chip package maintaining alignment during soldering |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099102170ATWI480992B (en) | 2010-01-26 | 2010-01-26 | Flip-chip package maintaining alignment during soldering |
| Publication Number | Publication Date |
|---|---|
| TW201126671A TW201126671A (en) | 2011-08-01 |
| TWI480992Btrue TWI480992B (en) | 2015-04-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099102170ATWI480992B (en) | 2010-01-26 | 2010-01-26 | Flip-chip package maintaining alignment during soldering |
| Country | Link |
|---|---|
| TW (1) | TWI480992B (en) |
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| US10304716B1 (en) | 2017-12-20 | 2019-05-28 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
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| US10304716B1 (en) | 2017-12-20 | 2019-05-28 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
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