本發明係關於一種記憶體裝置，尤指一種具有場增強排列的記憶體裝置。The present invention relates to a memory device, and more particularly to a memory device having a field enhanced arrangement.
電阻記憶體是一種有前景的非揮發性記憶體。尤其，M.J Lee在IEDM pp. 771-774,2007所刊登的“具有氧化物二極體的2堆疊ID-IR交叉點結構做為開關元件用於高密度電阻記憶體應用”；及C.H. Ho在Symp. VLSI Tech.,pp.228-229,2007所刊登的“一種高度可信賴的自排列分級氧化物WOx電阻記憶體：導電機制及可信度”；以及在2010年1月19日美國臨時申請案61/296,231中討論WOxRRAM為具有有前景的記憶體特性。Resistive memory is a promising non-volatile memory. In particular, MJ Lee published in IEDM pp. 771-774, 2007 "2 stacked ID-IR cross-point structures with oxide diodes as switching elements for high-density resistive memory applications"; and CH Ho Symp. VLSI Tech., pp. 228-229, 2007, "A highly reliable self-aligned graded oxide WOx resistive memory: conductive mechanism and reliability"; and on January 19, 2010, USA WOx RRAM is discussed in Provisional Application No. 61/296,231 as having promising memory characteristics.
所討論的記憶體具有插頭的外型，且在形成記憶體胞元的時候與一相當高的電流需求有關。The memory in question has the appearance of a plug and is associated with a relatively high current demand when forming a memory cell.
本發明的一主要目的為提供一記憶體裝置，其具有一金屬氧化物記憶體元件、一非傳導元件以及一傳導元件。It is a primary object of the present invention to provide a memory device having a metal oxide memory device, a non-conductive component, and a conductive component.
該金屬氧化物記憶體元件，位於具有一第一電壓的一第一電極與具有一第二電壓的一第二電極之間的一電流路徑中。例如：該第一與第二電極為上部與底部電極。其他實施例可以有不同的電極排列。該非傳導元件，鄰近於該金屬氧化物記憶體元件。在一實施例中，該非傳導元件包含在該第二電極上的一襯墊的一氧化物。The metal oxide memory device is located in a current path between a first electrode having a first voltage and a second electrode having a second voltage. For example, the first and second electrodes are upper and bottom electrodes. Other embodiments may have different electrode arrangements. The non-conductive element is adjacent to the metal oxide memory element. In one embodiment, the non-conductive element comprises an oxide of a liner on the second electrode.
該傳導元件，位於該第一電極與該第二電極間的電流路徑中。在一實施例中，該傳導元件包含位於該第二電極上的一襯墊、以及位於該襯墊中的一插頭。該傳導元件具有與該第一電極距離一第一距離的一第一部分以及與該第二電極距離一第二距離的一第二部分，如此該第一距離大於該第二距離。The conducting element is located in a current path between the first electrode and the second electrode. In one embodiment, the conductive element includes a pad on the second electrode and a plug in the pad. The conductive element has a first portion at a first distance from the first electrode and a second portion at a second distance from the second electrode such that the first distance is greater than the second distance.
該金屬氧化物記憶體元件位於該傳導元件的該第一部分與該第一電極之間。該非傳導元件位於該傳導元件的該第二部分與該第一電極之間。在數種實施例中，如此排列增強了在非傳導元件中的電場，也增強了靠近該非傳導元件的金屬氧化物記憶體元件的部分的電場。The metal oxide memory device is between the first portion of the conductive element and the first electrode. The non-conductive element is located between the second portion of the conductive element and the first electrode. In several embodiments, such an arrangement enhances the electric field in the non-conducting element and also enhances the electric field near the portion of the metal oxide memory element of the non-conducting element.
某些實施例包括在該金屬氧化物記憶體元件上執行一重設操作以及一設定操作的電路。在另一實施例中，在正規操作前，該電路不會執行與該重設操作及該設定操作不同之一形成操作。這是記憶體胞元的增進的電場的好處。在一實施例中，該重設操作以及該設定操作具有一共同的電壓極性。在另一實施例中，該重設操作以及該設定操作具有相反的電壓極性。Some embodiments include circuitry that performs a reset operation and a set operation on the metal oxide memory device. In another embodiment, the circuit does not perform a forming operation different from the reset operation and the set operation prior to the normal operation. This is the benefit of the enhanced electric field of the memory cells. In an embodiment, the reset operation and the set operation have a common voltage polarity. In another embodiment, the reset operation and the set operation have opposite voltage polarities.
在各種實施例中，該記憶體裝置係為一抗氧化物RAM，或一磁穿隧接面RAM。In various embodiments, the memory device is an anti-oxide RAM, or a magnetic tunnel junction RAM.
本發明的另一目的為提供一種製造一記憶體裝置的方法的技術，包含下列步驟：在一第一電極上方的一凹處形成一傳導元件，該傳導元件包括一第一導電材料以及一第二導電材料；從該傳導元件的該第一導電材料形成該記憶體裝置的一金屬氧化物記憶體元件；從該傳導元件的該第二導電材料形成一非傳導元件，該金屬氧化物記憶體元件鄰近該非傳導元件；以及在該金屬氧化物記憶體元件及該傳導元件上方形成一第二電極，以使(i)該金屬氧化物記憶體元件具有介於該傳導元件與該第二電極的餘料之間的一第一厚度，以及(ii)該非傳導元件具有介於該傳導元件與該第二電極的餘料之間的一第二厚度，該第一厚度大於該第二厚度。Another object of the present invention is to provide a technique for fabricating a memory device comprising the steps of forming a conductive element in a recess above a first electrode, the conductive element comprising a first conductive material and a first a second conductive material; forming a metal oxide memory element of the memory device from the first conductive material of the conductive element; forming a non-conductive element from the second conductive material of the conductive element, the metal oxide memory An element is adjacent to the non-conductive element; and a second electrode is formed over the metal oxide memory element and the conductive element such that (i) the metal oxide memory element has between the conductive element and the second electrode a first thickness between the remaining materials, and (ii) the non-conductive element having a second thickness between the conductive element and the remainder of the second electrode, the first thickness being greater than the second thickness.
在一實施例中，藉由氧化該傳導元件的一表面來一同執行形成該金屬氧化物記憶體元件的步驟及形成該非傳導元件的步驟。In one embodiment, the step of forming the metal oxide memory device and the step of forming the non-conductive element are performed together by oxidizing a surface of the conductive element.
在某些實施例中，形成該傳導元件的步驟包括形成具有一表面的該傳導元件，該表面包括該第一導電材料與該第二導電材料。該第一導電材料在該表面鄰近該第二導電材料。In some embodiments, the step of forming the conductive element includes forming the conductive element having a surface comprising the first conductive material and the second conductive material. The first conductive material is adjacent to the second conductive material on the surface.
某些實施例包括形成電路的步驟。該電路在該金屬氧化物記憶體元件上執行一重設操作以及一設定操作。在另一實施例中，在用於該記憶體胞元之正規使用的設定及重設操作之前，不需要不同於該設定及重設操作的一形成操作。場增強排列使得電場足夠高而藉由正規操作以開始正規的使用新的記憶體胞元。在一實施例中，該重設操作以及該設定操作具有一共同的電壓極性。在另一實施例中，該重設操作以及該設定操作具有相反的電壓極性。Some embodiments include the step of forming a circuit. The circuit performs a reset operation and a set operation on the metal oxide memory device. In another embodiment, a forming operation other than the setting and resetting operations is not required prior to the setting and resetting operations for the regular use of the memory cells. The field enhancement arrangement allows the electric field to be high enough to begin normal use of new memory cells by regular operation. In an embodiment, the reset operation and the set operation have a common voltage polarity. In another embodiment, the reset operation and the set operation have opposite voltage polarities.
在某些實施例中，該第二電極係為氧惰性的。氧惰性電極與寬電阻窗有關。In certain embodiments, the second electrode is oxygen inert. The oxygen inert electrode is associated with a wide resistance window.
在某些實施例中，形成該非傳導元件的步驟包括：在底部電極上氧化該傳導元件的一導電襯墊。In some embodiments, the step of forming the non-conductive element includes oxidizing a conductive pad of the conductive element on the bottom electrode.
在某些實施例中，形成該傳導元件的步驟包括：在底部電極上形成一導電襯墊；以及在該導電襯墊中形成一導電插頭。In some embodiments, the step of forming the conductive element includes: forming a conductive pad on the bottom electrode; and forming a conductive plug in the conductive pad.
在各種實施例中，該方法製造一抗氧化物RAM或一磁穿隧接面RAM。In various embodiments, the method fabricates an oxide RAM or a magnetic tunnel junction RAM.
本發明的又一目的為提供一種記憶體裝置，該記憶體裝置包括一記憶體胞元之交叉點陣列。在陣列中的該記憶體胞元包括在此處揭露的記憶體胞元。It is still another object of the present invention to provide a memory device that includes an array of intersections of memory cells. The memory cells in the array include the memory cells disclosed herein.
下列揭露的描述將典型地參考特定結構的實施例及方法。實施方式中應被了解的是沒有任何意圖去限制揭露於特定揭露的實施例及方法，但是揭露中可使用其他特徵、元件方法、及實施例來實施。較佳的實施例被描述用來說明目前的揭露，非限制其專利範圍。凡本領域人員具有通常知識者將在下列的描述認得種種相等的變化。如在各種實施例中的元件共同參照至參考數字。The following disclosure will typically refer to specific embodiments of the embodiments and methods. It should be understood that the embodiments are not intended to be limited to the details of the disclosed embodiments, and the invention may be practiced. The preferred embodiments are described to illustrate the present disclosure and not to limit the scope of the patent. Those of ordinary skill in the art will recognize various changes in the following description. Elements as in various embodiments are collectively referred to the reference numerals.
圖1為本發明之使用記憶體胞元實施一交叉點記憶體陣列100的部分示意圖，每一記憶體胞元包含一個二極體存取裝置與一基於記憶體元件的金屬氧化物。1 is a partial schematic diagram of a cross-point memory array 100 implemented using memory cells of the present invention, each memory cell including a diode access device and a memory element-based metal oxide.
如圖1的示意圖所示，該記憶體陣列100中的每一記憶體胞元包含一個二極體存取裝置與一基於記憶體元件的金屬氧化物(在圖1中藉由一可變電阻來表示每一個)，其被配置串接於在一相對應的字線110與一相對應的一位元線120之間的一電流路徑中。如下更詳細的描述，在一給定的記憶體胞元中的記憶體元件是可編程序為複數個電阻狀態包括一第一與一第二電阻狀態。As shown in the schematic diagram of FIG. 1, each memory cell in the memory array 100 includes a diode access device and a memory element-based metal oxide (in FIG. 1 by a variable resistor). Each of which is configured to be connected in series in a current path between a corresponding word line 110 and a corresponding one bit line 120. As described in more detail below, the memory elements in a given memory cell are programmable to a plurality of resistive states including a first and a second resistive state.
記憶體陣列100包含複數個字線110，其包括字線110a、字線110b、及字線110c在一第一方向平行延伸。記憶體陣列100還包含複數個位元線120，其包括位元線120a、位元線120b、及位元線120c在垂直於該第一方向的一第二方向上平行延伸。該記憶體陣列100參照至一交叉點陣列，因為該字線110與該位元線120互相交錯，但實體上無交叉，且該記憶體胞元位於該字線110與該位元線120這些交叉點的位置。The memory array 100 includes a plurality of word lines 110 including word lines 110a, word lines 110b, and word lines 110c extending in parallel in a first direction. The memory array 100 further includes a plurality of bit lines 120 including bit lines 120a, bit lines 120b, and bit lines 120c extending in parallel in a second direction perpendicular to the first direction. The memory array 100 is referenced to a cross-point array because the word line 110 and the bit line 120 are interlaced with each other, but there is no physical intersection, and the memory cell is located at the word line 110 and the bit line 120. The location of the intersection.
記憶體胞元115代表記憶體陣列100的記憶體胞元，且配置於該字線110b與該位元線120b的交叉點的位置，該記憶體胞元115包含一個二極體130與一記憶體元件140串接地配置。該二極體140電耦接於該字線110b，以及該記憶體元件140電耦接於該位元線120b。The memory cell 115 represents a memory cell of the memory array 100 and is disposed at a position of the intersection of the word line 110b and the bit line 120b. The memory cell 115 includes a diode 130 and a memory. The body element 140 is arranged in series. The diode 140 is electrically coupled to the word line 110b, and the memory element 140 is electrically coupled to the bit line 120b.
讀取或寫入該記憶體陣列100的記憶體胞元115可藉由施加適當的電壓脈衝至該相對應的字線110b與位元線120b以感應生成一電流穿過選擇的記憶體胞元115而達成。所施加電壓的程度與期間視所執行的操作而定。例如：一讀取操作或一編製程式的操作。The memory cell 115 that reads or writes to the memory array 100 can induce a current to pass through the selected memory cell by applying an appropriate voltage pulse to the corresponding word line 110b and bit line 120b. 115 and reached. The extent to which the voltage is applied is dependent on the operation performed during the period. For example: a read operation or a program operation.
在儲存於該記憶體胞元115的資料值的一讀取(或感測)操作中，偏壓電路(請參考，例如圖9中的偏壓配置供應電壓，電流源36)耦接於該相對應的字線110b與位元線120b以施加適合振幅與持續期間的穿越該記憶體胞元115的偏壓佈置，以感應電流流過而不會造成記憶體元件140的電阻狀態的改變。流經記憶體胞元115的電流由該記憶體元件140的電阻決定，因此該資料值儲存於該記憶體胞元115。例如藉由感測該放大器比較在位元線120b上的電流與一適當的參考電流可決定該資料值(請參考，例如，在圖9中結構24的感測放大器/資料)。In a read (or sense) operation of the data value stored in the memory cell 115, a bias circuit (refer to, for example, the bias configuration supply voltage in FIG. 9, current source 36) is coupled to The corresponding word line 110b and bit line 120b are arranged to apply a bias voltage that traverses the memory cell 115 for a suitable amplitude and duration to induce a current flow without causing a change in the resistance state of the memory element 140. . The current flowing through the memory cell 115 is determined by the resistance of the memory element 140, so the data value is stored in the memory cell 115. The data value can be determined, for example, by sensing the amplifier comparing the current on bit line 120b with an appropriate reference current (see, for example, sense amplifier/data of structure 24 in FIG. 9).
在一資料值被儲存於該記憶體胞元115的編製程式操作中，偏壓電路(請參考，例如圖9中的偏壓配置供應電壓，電流源36)耦合至對應的字線110b與位元線120b以施加適合振幅與持續期間的穿越該記憶體胞元115的偏壓佈置，以感應在記憶體元件140中的一程控的改變，以在記憶體胞元115中儲存該資料值，該記憶體元件140的電阻相對應於在該記憶體胞元115中所儲存的該資料值。In a programming operation in which a data value is stored in the memory cell 115, a bias circuit (refer to, for example, the bias configuration supply voltage in FIG. 9, current source 36) is coupled to the corresponding word line 110b and The bit line 120b is arranged to apply a bias voltage across the memory cell 115 for a suitable amplitude and duration to sense a programmed change in the memory element 140 to store the data value in the memory cell 115. The resistance of the memory element 140 corresponds to the data value stored in the memory cell 115.
偏壓佈置包括一第一偏壓佈置，其足以順向偏壓該二極體130以及從相對應於第一已程式狀態的電阻至相對應於第二已程式狀態的電阻改變該記憶體元件140的電阻狀態。該偏壓佈置亦包括一第二偏壓佈置，其足以順向偏壓該二極體130以及從相對應於第二已程式狀態的電阻至相對應於第一已程式狀態的電阻改變該記憶體元件140的電阻狀態。在實施例中用於記憶體元件140的單極操作的每一個偏壓配置可包含一個或更多個電壓脈衝，且該電壓程度與脈衝次數對於每一個實施例而言可憑經驗決定。The biasing arrangement includes a first biasing arrangement sufficient to forward bias the diode 130 and change the memory component from a resistor corresponding to the first programmed state to a corresponding corresponding second programmed state The resistance state of 140. The biasing arrangement also includes a second biasing arrangement sufficient to positively bias the diode 130 and change the memory from a resistor corresponding to the second programmed state to a corresponding corresponding to the first programmed state The resistance state of the body element 140. Each bias configuration for unipolar operation of memory element 140 in an embodiment may include one or more voltage pulses, and the degree of voltage and number of pulses may be determined empirically for each embodiment.
圖2A和2B顯示在交叉點陣列100之內排列的記憶體胞元(包括代表性的記憶體胞元115)之一實施例的部份截面圖，圖2A是顯示沿著位元線120的截面，而圖2B是顯示沿著字線的截面。2A and 2B show partial cross-sectional views of one embodiment of memory cells (including representative memory cells 115) arranged within cross-point array 100, and FIG. 2A is shown along bit line 120. Section, while Figure 2B shows the section along the word line.
參閱圖2A和2B，該記憶體胞元115包括位於字線110b之內的一摻雜的半導體區域132。字線110b含有導電型態與該摻雜的半導體區域132相反的摻雜的半導體物質。因此，在該摻雜的半導體區域132與字線110b之間界定出一PN接合134，二極體130包括該摻雜的半導體區域132以及字線110b鄰近於該摻雜的半導體區域132的部份。在所示的實施例中，字線110b含有摻雜的P型半導體物質例如多晶矽，而該摻雜的半導體區域132含有摻雜的N型半導體物質。Referring to Figures 2A and 2B, the memory cell 115 includes a doped semiconductor region 132 located within word line 110b. Word line 110b contains a doped semiconductor material having a conductivity profile opposite that of doped semiconductor region 132. Thus, a PN junction 134 is defined between the doped semiconductor region 132 and the word line 110b, the diode 130 including the doped semiconductor region 132 and the portion of the word line 110b adjacent to the doped semiconductor region 132 Share. In the illustrated embodiment, word line 110b contains a doped P-type semiconductor material such as polysilicon, and the doped semiconductor region 132 contains a doped N-type semiconductor material.
在另一實施例中，字線130可包含其他的導電物質，例如鎢、氮化鈦、氮化鉭、鋁，而該二極體可由字線110上面具有不同導電型態的第一與第二摻雜區域所構成。在又一實施例中，可讓一輕度摻雜區域位於多個具相反導電性的高摻雜區域之間而形成該二極體，這是由於觀察發現可以改進該二極體的崩潰電壓。In another embodiment, the word line 130 may include other conductive materials such as tungsten, titanium nitride, tantalum nitride, aluminum, and the diode may be first and the same by different conductivity patterns on the word line 110. The two doped regions are formed. In yet another embodiment, a lightly doped region can be formed between a plurality of highly doped regions of opposite conductivity to form the diode, as it is observed that the breakdown voltage of the diode can be improved. .
該記憶體胞元115包括有一傳導元件150，其延伸穿過介質170以將二極體130耦接於記憶體元件140。The memory cell 115 includes a conductive element 150 that extends through the dielectric 170 to couple the diode 130 to the memory component 140.
於所示的實施例中，傳導元件150含有鎢而且記憶體元件140含有鎢氧化物WOx。記憶體元件140被一層氮化鈦150A或是被氮化矽與氮化鈦的夾層所圍繞。其他的物質亦可用作襯墊。In the illustrated embodiment, the conductive element 150 and memory element comprising tungsten 140 containing tungsten oxide WOx. The memory element 140 is surrounded by a layer of titanium nitride 150A or an interlayer of tantalum nitride and titanium nitride. Other substances can also be used as a liner.
於所示的實施例中，形成含有鎢氧化物的記憶體元件140的實施方式包括直接電漿氧化、下游電漿氧化、熱擴散氧化、濺鍍和反應式濺鍍。電漿氧化製程的實施方式包括有純氧氣化學作用或混合的化學作用，例如氧氣/氮氣或氧氣/氮氣/氫氣。在下游電漿氧化的一實施例中，該下游電漿被施加約1500毫托耳的壓力、約1000瓦的功率、氧氣與氫氣流速比率在0.1到100之間、約150℃的溫度，並且持續10到2000秒的時間。參閱如美國專利申請號11/955,137，在此將其併作參考。這項製程亦導致該層150A其頂部的氧化，以形成一場增強元件999。場增強元件999包含圍繞其程度可接觸到上部電極的記憶體元件的氮化鈦氧化物TiNOx。鎢氧化物WOx是以較該氮化鈦氧化物層的厚度更厚層的方法而形成。因此，介於該上部電極以及圍繞於鎢插頭的襯墊頂端的介質厚度小於穿過該記憶體元件到鎢插頭頂端的介質厚度。由於距離較短，位於上部電極與襯墊之間的電場大於上部電極與鎢插頭表面之間的電場。而且，位於鎢氧化物之上部的電場密度被加強。當鎢插頭的直徑，或者說是襯墊之內徑，是位於約20微秒的數量級或以下，用於約1.5伏特量級的施加電壓，所加強的電場成為沿著整個記憶體元件的截面實質上均勻的增加。In the illustrated embodiment, embodiments of forming a memory element 140 comprising tungsten oxide include direct plasma oxidation, downstream plasma oxidation, thermal diffusion oxidation, sputtering, and reactive sputtering. Embodiments of the plasma oxidation process include pure oxygen chemistry or mixed chemistry such as oxygen/nitrogen or oxygen/nitrogen/hydrogen. In an embodiment of downstream plasma oxidation, the downstream plasma is applied at a pressure of about 1500 mTorr, a power of about 1000 watts, a ratio of oxygen to hydrogen flow rate between 0.1 and 100, a temperature of about 150 °C, and Lasts 10 to 2000 seconds. See, for example, U.S. Patent Application Serial No. 11/955, the entire disclosure of which is incorporated herein by reference. This process also causes oxidation of the top of layer 150A to form a reinforcing element 999. Field enhancing element 999 includes titanium nitride oxide TiNOx that is accessible to the memory element of the upper electrode. The tungsten oxide WOx is formed by a thicker layer than the thickness of the titanium nitride oxide layer. Thus, the thickness of the medium between the upper electrode and the top end of the pad surrounding the tungsten plug is less than the thickness of the medium passing through the memory element to the tip of the tungsten plug. Due to the short distance, the electric field between the upper electrode and the pad is larger than the electric field between the upper electrode and the surface of the tungsten plug. Moreover, the electric field density at the upper portion of the tungsten oxide is enhanced. When the diameter of the tungsten plug, or the inner diameter of the gasket, is on the order of about 20 microseconds or less, for an applied voltage on the order of about 1.5 volts, the enhanced electric field becomes a cross section along the entire memory element. A substantially uniform increase.
在另一實施例中，記憶體元件140可包含選自於下列的一或多種金屬氧化物：如鈦氧化物、鎳氧化物、鋁氧化物、銅氧化物、鋯氧化物、鈦-鎳氧化物、鍶-鋯氧化物、氧化鈮、氧化鉭、鉻摻雜鋯酸鍶、鉻摻雜鈦酸鍶、氯化聚醚、鑭鈣錳氧、以及過渡金屬氧化物等等。電場增強元件的材料例如二氧化矽、HfOx、TiNOx、TiOx、AlOx、以及WOx等，可擇優使得其具有較記憶體元件14更高的電阻。In another embodiment, the memory element 140 can comprise one or more metal oxides selected from the group consisting of titanium oxide, nickel oxide, aluminum oxide, copper oxide, zirconium oxide, titanium-nickel oxide. , cerium-zirconium oxide, cerium oxide, cerium oxide, chromium-doped cerium zirconate, chromium-doped barium titanate, chlorinated polyether, barium calcium manganese oxide, and transition metal oxides, and the like. Materials of the electric field enhancing element such as cerium oxide, HfOx , TiNOx , TiOx , AlOx , and WOx may be preferred such that they have a higher electrical resistance than the memory element 14.
多個位元線120包括作為該記憶體胞元115一上部電極的位元線120b。該等位元線120電耦接於記憶體元件140，伸入並且透出如圖2B所示的截面。該等位元線120包含一或多層導體材料。該等位元線120可含有鎳或鉑或其他高功函數導電物質。並且，上部與底部電極和導體可以是氮化鈦、鐿、鋱、釔、鑭、鈧、鋯、鉿、鋁、鉭、鈦、鈮、鉻、釩、鋅、鎢、鉬、銅、錸、釕、鈷、鎳、鉑、鉛、銠等等。高功函數電極降低操作的切換電流。以鎳為例，於60 nm的操作電流降至100微安培以下而切換速度小於50微秒，可以預期在85℃具有大於300年的保存期間。而且，具有相似的生成自由能的上部電極能改善保存性質。The plurality of bit lines 120 include a bit line 120b as an upper electrode of the memory cell 115. The bit line 120 is electrically coupled to the memory element 140 and extends into and out of the cross section as shown in FIG. 2B. The bit line 120 includes one or more layers of conductor material. The bit line 120 can contain nickel or platinum or other high work function conductive material. Moreover, the upper and bottom electrodes and conductors may be titanium nitride, tantalum, niobium, tantalum, niobium, hafnium, zirconium, hafnium, aluminum, niobium, titanium, niobium, chromium, vanadium, zinc, tungsten, molybdenum, copper, niobium, Antimony, cobalt, nickel, platinum, lead, antimony and the like. The high work function electrode reduces the switching current of the operation. Taking nickel as an example, the operating current at 60 nm drops below 100 microamperes and the switching speed is less than 50 microseconds, which can be expected to have a shelf life of more than 300 years at 85 °C. Moreover, the upper electrode having similar free energy of generation can improve the preservation property.
介質174分隔相鄰的位元線120。於所示的實施例中，介質170、172含有矽氧化物。然而，亦可選用其他介電材料。The medium 174 separates adjacent bit lines 120. In the illustrated embodiment, the media 170, 172 contain a cerium oxide. However, other dielectric materials may also be used.
從圖2A和2B所是的截面圖可以看出陣列100的記憶體胞元係安排在字線110與位元線120的交叉點位置。以記憶體胞元115作為代表，其安排於字線110b與位元線120b的交叉點位置。此外，記憶體元件140與傳導元件150、160具有一第一寬度，其實質上和該等字線110(參閱圖2A)的寬度114相同。而且，記憶體元件140與傳導元件150、160具有一第二寬度，其實質上和該等位元線120(參閱圖2B)的寬度124相同。在此所用的“實質上”一詞是為了容納製造允差。因此，陣列100的記憶體胞元的該截面區域完全由該等字線110和該等位元線120的尺寸所決定，讓陣列100能有一高記憶體密度。It can be seen from the cross-sectional views of FIGS. 2A and 2B that the memory cell of array 100 is arranged at the intersection of word line 110 and bit line 120. Represented by the memory cell 115, it is arranged at the intersection of the word line 110b and the bit line 120b. In addition, memory element 140 and conductive elements 150, 160 have a first width that is substantially the same as width 114 of word lines 110 (see FIG. 2A). Moreover, memory element 140 and conductive elements 150, 160 have a second width that is substantially the same as width 124 of the bit line 120 (see FIG. 2B). The term "substantially" as used herein is intended to accommodate manufacturing tolerances. Thus, the cross-sectional area of the memory cells of array 100 is entirely determined by the size of the word lines 110 and the bit lines 120, allowing the array 100 to have a high memory density.
該等字線110具有字線寬度114，並且由字線分隔距離112分隔相鄰的字線110(參閱圖2A)。該等位元線120具有位元線寬度124，並且由位元線分隔距離122分隔相鄰的位元線120(參閱圖2B)。在較佳實施例中，字線寬度114與字線分隔距離112的總和等於用於形成陣列100的製程的特徵尺寸F的兩倍，而位元線寬度124與位元線分隔距離122的總和也等於該特徵尺寸F的兩倍。再則，F較佳為於用於形成該等字線110與該等位元線120的製程(典型為平面印刷製程)之一最小特徵尺寸，其使得陣列100的記憶體胞元具有4F2的記憶體胞元面積。The word lines 110 have a word line width 114 and the adjacent word lines 110 are separated by a word line separation distance 112 (see FIG. 2A). The bit line 120 has a bit line width 124, and the adjacent bit line 120 is separated by a bit line separation distance 122 (see FIG. 2B). In the preferred embodiment, the sum of the word line width 114 and the word line separation distance 112 is equal to twice the feature size F of the process used to form the array 100, and the sum of the bit line width 124 and the bit line separation distance 122. It is also equal to twice the feature size F. Furthermore, F is preferably one of the smallest feature sizes of the process (typically a planar printing process) used to form the word lines 110 and the bit lines 120, such that the memory cells of the array 100 have 4F2 The area of the memory cell.
如圖2A-2B所示的記憶體陣列100，記憶體元件140自行與導電插頭150對齊。以下所述較詳細的製造實施例中，記憶體元件140是經由傳導元件150的材料氧化所形成。As with the memory array 100 shown in Figures 2A-2B, the memory component 140 is self-aligned with the conductive plug 150. In the more detailed fabrication embodiment described below, the memory element 140 is formed by oxidation of the material of the conductive element 150.
操作狀態下，耦接到相對應的字線110b和位元線120b的偏壓電路(例如，參閱圖9的偏壓配置供應電壓、電流源36)施以偏壓排列於整個記憶體胞元115，以順向偏壓於二極體130，並於記憶體元件140的電阻狀態中感應一可程控的變更。記憶體元件140的電阻顯示儲存於記憶體胞元115的資料值。In an operational state, a bias circuit coupled to the corresponding word line 110b and bit line 120b (eg, the bias configuration supply voltage, current source 36 of FIG. 9) is biased throughout the memory cell. Element 115 is biased forward to diode 130 and induces a programmable change in the resistive state of memory element 140. The resistance of the memory element 140 displays the data value stored in the memory cell 115.
圖3至6表示用以製造如圖2A-2B所示記憶體胞元的交叉點陣列100之生產流程各步驟。Figures 3 through 6 illustrate the various steps of the production process for fabricating the array of intersections 100 of the memory cells of Figures 2A-2B.
圖3A-3B顯示在一基板上形成字線110以及在字線110上形成介質170的第一步驟之截面圖，字線110由一第一方向伸展進入並穿出圖3A所示的截面圖，所示的實施例含有摻雜的半導體材料。字線110具有字線寬度114，並且由字線分隔距離112分隔相鄰的字線。3A-3B are cross-sectional views showing a first step of forming a word line 110 on a substrate and forming a dielectric 170 on the word line 110, the word line 110 extending from a first direction and passing through the cross-sectional view shown in FIG. 3A. The illustrated embodiment contains a doped semiconductor material. Word line 110 has a word line width 114 and is separated by word line separation distance 112 by adjacent word lines.
接著，具有寬度610的偏壓陣列600形成於介質170之內，以露出部分的字線110，摻雜的半導體區域132於字線110之間例如用離子植入方式形成，產生的結構如圖4A-4B的截面圖所示。Next, a bias array 600 having a width 610 is formed within the dielectric 170 to expose portions of the word lines 110, and the doped semiconductor regions 132 are formed between the word lines 110, for example, by ion implantation, resulting in a structure as shown in FIG. The cross section of 4A-4B is shown.
該摻雜的半導體區域132具有與字線110相反的傳導類型。因此該摻雜的半導體區域132與字線110定義了PN接合134，二極體130包括摻雜的半導體區域132以及靠近摻雜的半導體區域132的一部分字線110。The doped semiconductor region 132 has a conductivity type opposite to the word line 110. The doped semiconductor region 132 and the word line 110 thus define a PN junction 134 that includes a doped semiconductor region 132 and a portion of the word line 110 adjacent the doped semiconductor region 132.
接著，在圖4A-4B中，傳導元件150是在導通孔600中形成的，導致如圖5A-5B截面圖所示的結構。在本實施例中的傳導元件150包括材料鎢，且可藉由導通孔600以化學氣相沈積材料鎢，接著施以平面化的步驟如化學機械磨光來形成。Next, in FIGS. 4A-4B, the conductive member 150 is formed in the via hole 600, resulting in a structure as shown in the cross-sectional view of FIGS. 5A-5B. The conductive member 150 in this embodiment includes a material of tungsten, and can be formed by chemical vapor deposition of a material tungsten by via holes 600, followed by a planarization step such as chemical mechanical polishing.
然後，一部分的傳導元件150及襯墊150A的氧化形成記憶體元件140與場增強排列999，該場增強元件999與對應的傳導元件150以及襯墊150A的剩餘部分自行排列，導致如圖6A-6B截面圖所示的結構。氧化可以包括電漿氧化以及一選擇性的熱氧化步驟。例如：可使用直接氧電漿氧化法或下游氧電漿氧化法。實施例中包括純氧氣化學作用或混合的化學作用，如氧氣/氮氣或氧氣/氮氣/氫氣。因為記憶體元件140是由傳導元件150的氧化所形成的，因此不需要額外的遮蔽物來形成記憶體元件140。Then, oxidation of a portion of the conductive element 150 and the liner 150A forms the memory element 140 and the field enhancement arrangement 999, the field enhancement element 999 and the corresponding conductive element 150 and the remainder of the liner 150A are self-aligned, resulting in Figure 6A- Structure shown in section 6B. Oxidation can include plasma oxidation and a selective thermal oxidation step. For example, direct oxygen plasma oxidation or downstream oxygen plasma oxidation can be used. Examples include pure oxygen chemistry or mixed chemistry such as oxygen/nitrogen or oxygen/nitrogen/hydrogen. Because memory element 140 is formed by oxidation of conductive element 150, no additional mask is required to form memory element 140.
之後，金屬氧化物記憶體元件140利用暴露於包含至少一氮氣、氫氣或氬氣的氣體下，溫度高於100℃來選擇性固化。該金屬氧化物記憶體元件140較佳在溫度高於150℃暴露於上述氣體中來固化。將金屬氧化物記憶體元件140暴露於氣體中可藉由使用任何合適的高溫系統來實現，例如：熔爐系統或快速熱脈衝(RTP系統)。暴露過程的時間、溫度及壓力取決於數種因素，包括所使用的系統，以及各實施例的不同。例如：溫度範圍可以從150℃到500℃，時間從10到10,000秒，在10-5到10-2托耳間的壓力。下面將詳細討論關於圖11A-11B，此處所述之固化金屬氧化物記憶體元件140是為了說明改善金屬氧化物記憶體元件140的電阻轉換性能以及循環耐久性。Thereafter, the metal oxide memory device 140 is selectively cured by exposure to a gas comprising at least one of nitrogen, hydrogen or argon at a temperature above 100 °C. The metal oxide memory device 140 is preferably cured by exposure to the above gases at a temperature above 150 °C. Exposing the metal oxide memory element 140 to a gas can be accomplished by using any suitable high temperature system, such as a furnace system or a rapid thermal pulse (RTP system). The time, temperature, and pressure of the exposure process depend on several factors, including the system used, and the differences in the various embodiments. For example, the temperature range can be from 150 ° C to 500 ° C, the time is from 10 to 10,000 seconds, and the pressure is between 10-5 and 10-2 Torr. As will be discussed in greater detail below with respect to Figures 11A-11B, the cured metal oxide memory device 140 described herein is for purposes of illustrating improved electrical resistance conversion performance and cycle durability of the metal oxide memory device 140.
形成高功函數位元線130使用例如物理氣相沈積法，以介質174分開，形成於如圖6A-6B所示之結構上，而導致如圖2A-2B所示之交叉點陣列100。在某些實施例中，關於圖4A-4B所述的金屬氧化物記憶體元件140的選擇性暴露程序可替代操作於位元線130上。偏壓電路如供應電壓和/或電流源可形成在相同的裝置如記憶體元件上，以及耦合到字線110和位元線120用於應用此處所述之偏壓配置。形成位元線130與介質174可藉由將位元線材料成型於圖4A-4B中的結構，在位元線130上形成介質，以及執行一平面化程序如化學機械磨光。The high work function bit line 130 is formed, for example, by physical vapor deposition, separated by a medium 174, formed on the structure as shown in FIGS. 6A-6B, resulting in the cross point array 100 as shown in FIGS. 2A-2B. In some embodiments, the selective exposure process for the metal oxide memory device 140 described with respect to FIGS. 4A-4B can be substituted for operation on the bit line 130. A bias voltage circuit, such as a supply voltage and/or current source, can be formed on the same device, such as a memory device, and coupled to word line 110 and bit line 120 for applying the biasing configuration described herein. Forming the bit line 130 and the dielectric 174 can form a dielectric on the bit line 130 by forming the bit line material into the structure of FIGS. 4A-4B, and performing a planarization process such as chemical mechanical polishing.
在圖6B之後，一具有導體的上部電極形成。After FIG. 6B, an upper electrode having a conductor is formed.
圖7為本發明的一整合電路10的簡化流程圖，該整合電路10包括記憶體胞元的交叉點記憶體陣列100，該記憶體胞元包括一金屬氧化物為基礎之記憶體元件以及一二極體存取裝置。字線解碼器14與複數個字線16耦合且電子通訊。位元線(行)解碼器18與複數個位元線20電子通訊以從陣列100中的記憶體胞元(未顯示)讀取與寫進資料。位址供應於排線22上至字線解碼器與驅動器14以及位元線解碼器18。方塊24中的感測放大器及資料進入結構經由資料排線26耦合至位元線解碼器18。資料的提供係從整合電路10上的輸入/輸出埠，或從整合電路10內部或外部的其他資料源藉由資料進入線28至方塊24中的資料進入結構。其他的電路30可包括於整合電路10中，如一普遍用途的處理器或特殊用途的應用電路，或模組的結合提供由陣列100所支援的在晶片上的系統功能。資料的提供係從方塊24中的感測放大器藉由資料輸出線32至整合電路10上的輸入/輸出埠，或整合電路10內部或外部的其他資料終點。7 is a simplified flow diagram of an integrated circuit 10 of the present invention, the integrated circuit 10 including a memory cell of a cross-point memory array 100, the memory cell including a metal oxide based memory component and a Diode access device. Word line decoder 14 is coupled to a plurality of word lines 16 and is in electronic communication. A bit line (row) decoder 18 is in electronic communication with a plurality of bit lines 20 to read and write data from memory cells (not shown) in array 100. The address is supplied to the line 22 to the word line decoder and driver 14 and the bit line decoder 18. The sense amplifier and data entry structure in block 24 is coupled to bit line decoder 18 via data line 26. The data is provided from the input/output ports on the integrated circuit 10, or from other sources within or outside of the integrated circuit 10, through the data entry line 28 to the data in block 24 into the structure. Other circuits 30 may be included in the integrated circuit 10, such as a general purpose processor or special purpose application circuit, or a combination of modules to provide system functions on the wafer supported by the array 100. The data is provided from the sense amplifier in block 24 via the data output line 32 to the input/output ports on the integrated circuit 10, or to other data endpoints internal or external to the integrated circuit 10.
在本實施例中所實施的控制器34使用偏壓配置狀態機器，控制偏壓配置供應電壓36的應用，如讀取、制訂計畫、以及為核對電壓制訂計畫。控制器34可使用習知的特殊用途邏輯電路來實施。在另一實施例中，控制器34包括一普遍用途的處理器，其可執行於相同的整合電路上以執行一電腦程式來控制該裝置的操作。在又另一實施例中，特殊用途的邏輯電路與普遍用途的處理器可結合以利用於控制器34的實施。The controller 34 implemented in this embodiment uses a bias configuration state machine to control the application of the bias configuration supply voltage 36, such as reading, formulating a plan, and formulating a plan for verifying the voltage. Controller 34 can be implemented using conventional special purpose logic circuitry. In another embodiment, controller 34 includes a general purpose processor that can execute on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, special purpose logic circuitry can be utilized in conjunction with a general purpose processor to utilize the implementation of controller 34.
如上述關於圖6A-6B，在製造具有二極體存取裝置的記憶體胞元時金屬氧化物記憶體元件140可藉由暴露於包含至少一氮氣、氫氣或氬氣的氣體中來固化。As described above with respect to Figures 6A-6B, the metal oxide memory device 140 can be cured by exposure to a gas comprising at least one of nitrogen, hydrogen or argon when fabricating a memory cell having a diode access device.
其他金屬氧化物如鈦氧化物、鎳氧化物、鋁氧化物、銅氧化物、鋯氧化物、鈮氧化物、鉭氧化物、鈦-鎳氧化物、鉻摻雜鋯酸鍶、鉻摻雜鈦酸鍶、氯化聚醚、以及鑭鈣錳氧可與高功函數上部電極材料一同使用。Other metal oxides such as titanium oxide, nickel oxide, aluminum oxide, copper oxide, zirconium oxide, cerium oxide, cerium oxide, titanium-nickel oxide, chromium-doped lanthanum zirconate, chromium-doped titanium The acid bismuth, chlorinated polyether, and barium calcium manganese oxide can be used together with the high work function upper electrode material.
此裝置不僅可使用雙極操作，亦可使用單極操作。雙極操作表示該裝置可以相反極性的電場來設定或重設操作。單極操作表示該裝置可以相同極性的電場來設定或重設操作。This device can be used not only for bipolar operation but also for unipolar operation. Bipolar operation means that the device can be set or reset by an electric field of opposite polarity. Unipolar operation means that the device can be set or reset by an electric field of the same polarity.
圖8為具有一電場增強排列的一範例記憶體胞元的簡單示意圖。Figure 8 is a simplified schematic diagram of an exemplary memory cell having an electric field enhanced arrangement.
一記憶體如抗氧化物RAM或磁穿隧接面抗磁性RAM具有一場增強排列。記憶體胞元具有一上部電極與一底部電極，且記憶體元件排列於上部電極與底部電極間的電流路徑中的電系列。A memory such as an anti-oxidation RAM or a magnetic tunnel junction RC has an enhanced alignment. The memory cell has an upper electrode and a bottom electrode, and the memory element is arranged in an electrical series in the current path between the upper electrode and the bottom electrode.
在上部電極與底部電極間的電流路徑中的電系列，一傳導元件或導體具有“U”字形截面。該傳導元件的“U”字形截面的凹處部分位於與上部電極距離第一距離d1處，對應該記憶體元件的厚度d1。該傳導元件的“U”字形截面的臂狀部分位於與上部電極距離第二距離d2處，對應環繞該記憶體元件的非導電絕緣體1的厚度d2。關於從上部電極算起的距離，d1是從該上部電極至傳導元件的“U”字形截面的凹處部分的第一距離，d2是從該上部電極至傳導元件的“U”字形截面的臂狀部分的第二距離，且d1比d2大。一非導電絕緣體2環繞該傳導元件及該非導電絕緣體1。An electrical series in the current path between the upper electrode and the bottom electrode, a conductive element or conductor having a "U" shaped cross section. The recessed portion of the "U" shaped cross section of the conductive element is located at a first distance d1 from the upper electrode, corresponding to the thickness d1 of the memory element. The arm portion of the U-shaped cross section of the conducting element is located at a second distance d2 from the upper electrode, corresponding to the thickness d2 of the non-conductive insulator 1 surrounding the memory element. Regarding the distance from the upper electrode, d1 is the first distance from the upper electrode to the concave portion of the "U"-shaped cross section of the conductive member, and d2 is the arm of the "U"-shaped cross section from the upper electrode to the conductive member. The second distance of the shaped portion, and d1 is larger than d2. A non-conductive insulator 2 surrounds the conductive element and the non-conductive insulator 1.
絕緣體1與絕緣體2可以是相同或不同的材料。薄絕緣體1可導致在記憶體胞元中的電場的大小(尺寸)規模越來越小。因此，絕緣體1的材料需求為高電阻材料，如可在絕緣體1內支撐高電場的二氧化矽或氮氧化鈦(TiNOx)。為使場增強，d2的厚度需小於d1。The insulator 1 and the insulator 2 may be the same or different materials. The thin insulator 1 can cause the size (size) of the electric field in the memory cell to become smaller and smaller. Therefore, the material requirement of the insulator 1 is a high-resistance material such as cerium oxide or titanium oxynitride (TiNOx ) which can support a high electric field in the insulator 1. In order to enhance the field, the thickness of d2 needs to be less than d1.
絕緣體1越薄以及記憶體元件的寬度越窄，則在絕緣體1的末端及記憶體元件內所產生的電場越高。The thinner the insulator 1 and the narrower the width of the memory element, the higher the electric field generated at the end of the insulator 1 and in the memory element.
圖9為具有一電場增強排列的一範例記憶體胞元的一截面圖TEM影像。Figure 9 is a cross-sectional TEM image of an exemplary memory cell having an electric field enhanced arrangement.
在圖9中，60 nm裝置的TEM影像以金屬氧化物TiNOx作為記憶體元件為特徵。記憶體元件的上部被非導電絕緣體TiNOx所環繞。傳導元件為(i)導電性鎢插頭以及(ii)環繞記憶體元件與導電性鎢插頭底部的導電性氮化鈦(TiN)襯墊兩者的組合。在此實施例中，一自排列的場增強裝置排列係藉由氧化TiN襯墊為絕緣TiNOx，如此WOx被迫凸出於其餘的TiN襯墊上。In Figure 9, the TEM image of the 60 nm device features metal oxide TiNOx as the memory element. The upper portion of the memory element is surrounded by a non-conductive insulator TiNOx . The conductive element is a combination of (i) a conductive tungsten plug and (ii) a conductive titanium nitride (TiN) liner surrounding the memory element and the bottom of the conductive tungsten plug. In this embodiment, a self-aligned field enhancement system arranged by means of an insulating oxidized TiN liner TiNOx, WOx thus forced to protrude from the rest of the TiN liner.
WOx電阻式記憶體與互補金氧半導體具有很好的相容性，且具有簡單的製作法。然而，不像過渡金屬氧化物，WOx呈現低起始電阻吸引高電流，且嚴重限制其寫入頻寬。WOx resistive memory has good compatibility with complementary MOS and has a simple manufacturing method. However, unlike transition metal oxides, WOx exhibits a low initial resistance to attract high currents and severely limits its write bandwidth.
WOx與其他過渡金屬氧化物電阻式記憶體不同。由於溫度的限制，RTO過程無法完全消除在原生的WOx電阻式記憶體元件中鎢-次氧化物形成洩漏路徑。一形成過程改變該低電阻狀態為一高電阻狀態。此操作需要高電壓/電流以及需要正確的極性；該形成脈衝的相反極性無法達到一高電阻狀態。WOx is different from other transition metal oxide resistive memories. Due to temperature limitations, the RTO process does not completely eliminate the tungsten-suboxide formation leakage path in native WOx resistive memory devices. A forming process changes the low resistance state to a high resistance state. This operation requires high voltage/current and requires the correct polarity; the opposite polarity of the formed pulse cannot reach a high resistance state.
WOx電阻式記憶體的X射線光電子光譜學分析指出WOx電阻式記憶體表面的頂層主要由WO3所組成，且在低於表面約2.5 nm處，其組成改變為WO2+W2O5+WO3的混合。導電式原子力顯微鏡顯示洩漏路徑可藉由應用一電流穿過原子力顯微鏡尖端來消除，暗示洩漏路徑被氧化所密封係由焦耳熱所導致。X-ray photoelectron spectroscopy analysis of WOx RRAM noted that WOx top surface of the resistive memory composed mainly of WO3, and at less than about 2.5 nm of the surface, changed the composition of WO2 + W2 O Mix of5 + WO3 . Conductive atomic force microscopy shows that the leak path can be eliminated by applying a current through the tip of the atomic force microscope, suggesting that the leak path is oxidized and the seal is caused by Joule heat.
對於形成過程一提議的機制為：正電壓從較低於表面處吸引負O2-離子，且將有漏洞的次氧化物轉換為絕緣WO3。該上部電極係為氧惰性的。下面的表格顯示一氧惰性上部電極(TiN,Pt)較一氧反應上部電極(Al,Ti,W)顯示較佳的電阻式記憶體的高電阻狀態/低電阻狀態(HRS/LRS)比。The proposed mechanism for the formation process is that the positive voltage attracts negative O2- ions from below the surface and converts the vulnerable suboxide to the insulating WO3 . The upper electrode is oxygen inert. The table below shows that the oxygen-exhaust upper electrode (TiN, Pt) exhibits a better resistive memory high resistance/low resistance state (HRS/LRS) ratio than the one oxygen reaction upper electrode (Al, Ti, W).
下面敘述設定/重設機制。對於設定操作，產生一或多WO3-n燈絲，經由電化學氧化還原反應架起上部與底部電極的橋樑。該導電性WO3-n層產生低電阻狀態。對於重設操作，WO3-n燈絲破裂且藉由形成程序的相同機制轉換為絕緣的WO3(由較深處拉出的O2-所氧化)。因此，最初僅在未加工的裝置上以大量的洩漏路徑形成特殊的重設。The setting/reset mechanism will be described below. For the set operation, one or more WO3-n filaments are produced, bridging the upper and bottom electrodes via an electrochemical redox reaction. The conductive WO3-n layer produces a low resistance state. For the reset operation, the WO3-n filament is broken and converted to an insulating WO3 (oxidized by O2 drawn deeper) by the same mechanism of forming the procedure. Therefore, a special reset is initially formed with only a large number of leak paths on the unmachined device.
電阻決定層靠近上部WOx表面。因此，完全密封的WO3係藉由一正規的重設脈衝來達成。對於各種不同尺寸(60 nm,80 nm,100 nm)的裝置實施設定/重設電壓與電流顯示重設與設定的V/I與裝置大小沒有或很弱的依賴關係，暗示WOx電阻式記憶體的重設與設定機制透過氧化還原反應過程中燈絲的形成與分裂來支配。50 ns的重設脈衝具有一中間重設電壓保持在約-1.3V，且一中間設定電流保持在約0.65 mA。The resistance determines the layer near the upper WOx surface. Thus, the fully sealed WO3 is achieved by a regular reset pulse. For various devices of different sizes (60 nm, 80 nm, 100 nm), the setting/reset voltage and current display reset and set V/I have no or very weak dependence on device size, suggesting WOx resistive memory The resetting and setting mechanism of the body is governed by the formation and splitting of the filament during the redox reaction. The 50 ns reset pulse has an intermediate reset voltage maintained at approximately -1.3V and an intermediate set current maintained at approximately 0.65 mA.
起始的電阻分佈是與50個最近的180 nm WOx電阻式記憶體裝置以及50個最近的60 nm WOx電阻式記憶體裝置來比較。在60 nm，具有寬分佈(log R介於3.8與6.5之間)的起始電阻更高，而對於180 nm裝置(log R介於2.5與3.0之間)是非常緊的。此可由洩漏路徑的密度來解釋。若洩漏路徑密度接近在60 nm×60 nm的面積中的單一數字，則此分佈係由統計學波動所預期。The initial resistance distribution is compared to the 50 nearest 180 nm WOx resistive memory devices and the 50 most recent 60 nm WOx resistive memory devices. At 60 nm, the initial resistance is higher with a broad distribution (log R between 3.8 and 6.5) and very tight for a 180 nm device (log R between 2.5 and 3.0). This can be explained by the density of the leak path. If the leak path density is close to a single number in the area of 60 nm x 60 nm, this distribution is expected from statistical fluctuations.
緊的程序電壓分佈是由於從50、60 nm WOx電阻式記憶體胞元的設定與重設操作。對於重設(電阻約100 kohm)平均電壓是1.91 V，標準差0.31 V，而對於設定(電阻約10 kohm)平均電壓是1.31 V，標準差0.22 V。The tight program voltage distribution is due to the setting and reset operation of the WOx resistive memory cells from 50, 60 nm. The average voltage for reset (resistance approx. 100 kohm) is 1.91 V with a standard deviation of 0.31 V, while for the set (resistance approx. 10 kohm) the average voltage is 1.31 V with a standard deviation of 0.22 V.
瞬變電流的電流-時間圖顯示在60 nm WOx電阻式記憶體胞元上50 ns的重設與設定脈衝表現良好。可達到具有60 nm WOx電阻式記憶體胞元的多層式晶片操作，以至少四層在20KO與80KO之間產生兩個額外的層次，且該多層次晶片的耐久力＞104循環。＞109讀取次數的優異的讀取擾亂免疫存在時，以通常層次約1.5×105ohms在0.25 V的重設狀態，通常層次約2.0×105ohms在0.5 V的重設狀態，通常層次約7.5×103ohms在0.5 V的重設狀態。The current-time plot of the transient current shows that the 50 ns reset and set pulse performed well on the 60 nm WOx resistive memory cell. A multi-layer wafer operation with 60 nm WOx resistive memory cells can be achieved, resulting in two additional layers between 20 KO and 80 KO in at least four layers, and the multi-layer wafer has a durability of >104 cycles. >109 Read times of excellent read disturb immunity in the presence of a typical level of about 1.5 × 105 ohms in a reset state of 0.25 V, usually a level of about 2.0 × 105 ohms in a reset state of 0.5 V, usually The level is about 7.5 × 103 ohms in the reset state of 0.5 V.
圖10為在中央的電場v.s.記憶體胞元的直徑的圖，係由模擬以範例記憶體胞元來重設與設定操作而來，兩者皆包括具有與不具有一電場增強排列的情況。Figure 10 is a graph of the diameter of the central electric field v.s. memory cells, which are simulated and reset by the exemplary memory cells, both with and without an electric field enhancement arrangement.
不具有該電場增強排列的該範例記憶體胞元被參照為一棒狀結構。在棒狀結構中，該傳導元件缺乏“U”字形截面，取而代之的是具有一插頭的簡單矩形截面。The example memory cell that does not have the electric field enhancement arrangement is referred to as a rod-like structure. In the rod-like structure, the conducting element lacks a "U" shaped cross section and is instead a simple rectangular cross section with a plug.
不具有該電場增強排列的該範例記憶體胞元被參照為場增強結構。因為傳導元件的“U”字形截面的兩臂之尖端更靠近上部電極，介於上部電極與傳導元件之間的一給定電位差(例如分享底部電極的電壓)與棒狀結構相比具有更短的距離來改變；因此，具有電場增強排列的電場(根據E=V/d)會更高，接近傳導元件的“U”字形截面的兩臂之尖端。The example memory cell that does not have the electric field enhancement arrangement is referred to as a field enhancement structure. Since the tips of the two arms of the U-shaped cross section of the conducting element are closer to the upper electrode, a given potential difference between the upper electrode and the conducting element (eg sharing the voltage of the bottom electrode) is shorter than the rod-like structure. The distance varies; therefore, the electric field with an enhanced electric field arrangement (according to E = V/d) will be higher, approaching the tip of both arms of the "U" shaped cross section of the conducting element.
當W插頭的尺寸下修時，WOx中心的電場會相當高。接近邊緣的電場會更高。此電場增強特徵為在W插頭結構內自行排列而不需要耗費任何額外的屏蔽。When the size of the W plug is repaired, the electric field at the center of the WOx can be quite high. The electric field near the edge will be higher. This electric field enhancement feature is self-aligned within the W plug structure without the need for any additional shielding.
圖11為由具有一電場增強排列的各種直徑範例記憶體胞元在一形成操作下模擬而來的截面圖的電場圖。Figure 11 is an electric field diagram of a cross-sectional view simulated by a variety of diameter exemplary memory cells having an electric field enhanced arrangement under a forming operation.
圖11針對具有10 nm至100 nm直徑的記憶體元件，顯示電場強度v.s.與記憶體元件中心的距離。對於1.5 V之施加電壓，一致增加該記憶體元件尺寸達到約20 nm，資料顯示場實質上被增強了。Figure 11 shows the distance between the electric field strength v.s. and the center of the memory element for a memory element having a diameter of 10 nm to 100 nm. For an applied voltage of 1.5 V, the memory element size is increased to approximately 20 nm, and the data display field is substantially enhanced.
記憶體元件的各種直徑範圍從100 nm、80 nm、60 nm、40 nm、20 nm到10 nm。圖11將記憶體胞元的中心集合起來。圖11指出，當插頭的尺寸下修時，傳導元件的“U”字形截面的兩臂會更靠近。高電場的側邊位置對應記憶體胞元的半徑(直徑的一半)。Memory elements range in diameter from 100 nm, 80 nm, 60 nm, 40 nm, 20 nm to 10 nm. Figure 11 summarizes the centers of memory cells. Figure 11 indicates that when the size of the plug is repaired, the arms of the "U" shaped cross section of the conductive element will be closer. The side position of the high electric field corresponds to the radius of the memory cell (half the diameter).
圖12為由具有電場增強排列的100 nm直徑的示範記憶體胞元模擬而來的電場的二維圖。Figure 12 is a two dimensional map of an electric field simulated from a 100 nm diameter exemplary memory cell with an electric field enhanced arrangement.
圖13為由具有電場增強排列的20 nm直徑的示範記憶體胞元模擬而來的電場的二維圖。Figure 13 is a two-dimensional plot of an electric field simulated from a 20 nm diameter exemplary memory cell with an electric field enhanced arrangement.
比較圖12與圖13亦顯示當插頭的尺寸下修時，傳導元件的“U”字形截面的兩臂會更靠近，且近似傳導元件的“U”字形截面的兩臂的高電場漸增地聚集於中心。Comparing Fig. 12 with Fig. 13 also shows that when the size of the plug is repaired, the arms of the U-shaped cross section of the conducting element will be closer, and the high electric field of the two arms of the "U" shaped section of the conducting element is gradually increased. Gathered in the center.
圖14為由具有電場增強排列的各種直徑的範例記憶體胞元在一形成操作下的實驗結果而來的脈衝電壓圖。Figure 14 is a pulse voltage diagram of experimental results of a sample memory cell of various diameters having an electric field enhanced arrangement under a forming operation.
圖15為由具有電場增強排列的各種直徑的範例記憶體胞元在各種操作下的實驗結果而來的電流圖。Figure 15 is a graph of currents from experimental results of exemplary memory cells of various diameters with enhanced electric field alignment under various operations.
圖14與圖15顯示當胞元尺寸上升時，初始形成程序所需的電壓與電流快速下降。因此，在60 nm或以下，初始形成程序實際上是被忽略的。在如此小的記憶體胞元尺寸中，控制電路可省略，或者簡化而不操作，一具有命令碼的不同形成操作不同於一規律設定或重設操作的命令碼。取而代之的是，可執行規律操作。Figures 14 and 15 show that the voltage and current required for the initial formation process drop rapidly as the cell size increases. Therefore, at 60 nm or less, the initial formation procedure is actually ignored. In such a small memory cell size, the control circuitry can be omitted, or simplified, without operation, a command code having a different command forming operation than a regular set or reset operation. Instead, regular operations can be performed.
圖16為由具有電場增強排列的60 nm直徑的範例記憶體胞元在重設與設定操作的多次循環下的實驗結果而來的電阻v.s.脈衝電壓期間圖。Figure 16 is a graph of resistance v.s. pulse voltage period from experimental results of a 60 nm diameter sample memory cell with an electric field enhanced arrangement under multiple cycles of reset and set operations.
圖16指出如此小的記憶體胞元不需要不同的形成操作。Figure 16 indicates that such small memory cells do not require different forming operations.
圖17為由具有電場增強排列的60 nm直徑的範例記憶體胞元在重設與設定操作的多次循環下而來的電阻v.s.循環次數圖。Figure 17 is a graph of the number of resistance v.s. cycles from multiple cycles of reset and set operations of a 60 nm diameter example memory cell with an electric field enhanced arrangement.
圖17指出60 nm裝置的循環耐久力大於一百萬次。在一百萬次循環的重設/設定操作中，重設/設定電阻窗仍保持良好的分離。大約10倍電阻窗可藉由程式確認演算法來妥善地保持。Figure 17 indicates that the cycle endurance of the 60 nm device is greater than one million times. In the reset/set operation of one million cycles, the reset/set resistor window remains well separated. Approximately 10 times the resistance window can be properly maintained by a program validation algorithm.
圖18為對於具有電場增強排列的60 nm直徑的範例記憶體胞元在一實質的加熱期間後的電阻v.s.保持時間圖。Figure 18 is a graph showing the resistance v.s. retention time for a 60 nm diameter example memory cell with an electric field enhanced arrangement after a substantial heating period.
重設與設定狀態即使在150℃、2000小時的烘烤後亦充分地分離。The reset and set states were sufficiently separated even after baking at 150 ° C for 2000 hours.
以上所述係利用較佳實施例詳細說明本發明，而非限制本發明的範圍，因此熟知此技藝的人士應能明瞭，適當而作些微的改變與調整，仍將不失本發明之要義所在，亦不脫離本發明之精神和範圍，故都應視為本發明的進一步實施狀況。The above description of the present invention is intended to be illustrative of the present invention and not to limit the scope of the present invention, and it should be understood by those skilled in the art that modifications and adjustments may be made as appropriate, without departing from the scope of the invention. Further, the present invention should be considered as further implementations of the present invention without departing from the spirit and scope of the invention.
100．．．記憶體陣列100. . . Memory array
110,110a,110b,110c．．．字線110, 110a, 110b, 110c. . . Word line
120,120a,120b,120c．．．位元線120, 120a, 120b, 120c. . . Bit line
115．．．記憶體胞元115. . . Memory cell
130．．．二極體130. . . Dipole
140．．．記憶體元件140. . . Memory component
132．．．摻雜的半導體區域132. . . Doped semiconductor region
134．．．PN接合134. . . PN junction
170,172,174．．．介質170,172,174. . . medium
150A．．．襯墊150A. . . pad
999．．．場增強元件999. . . Field enhancement component
150,160．．．傳導元件150,160. . . Conduction element
114．．．字線寬度114. . . Word line width
124．．．位元線寬度124. . . Bit line width
112．．．字線分隔距離112. . . Word line separation distance
122．．．位元線分隔距離122. . . Bit line separation distance
600．．．導通孔600. . . Via
610．．．偏壓陣列寬度610. . . Bias array width
10．．．整合電路10. . . Integrated circuit
14．．．字線解碼器14. . . Word line decoder
16．．．複數個字線16. . . Multiple word lines
18．．．位元線(行)解碼器18. . . Bit line (row) decoder
20．．．複數個位元線20. . . Multiple bit lines
22．．．排線twenty two. . . Cable
26．．．資料排線26. . . Data cable
28．．．資料進入線28. . . Data entry line
30．．．其他電路30. . . Other circuit
32．．．資料輸出線32. . . Data output line
34．．．控制器34. . . Controller
36．．．偏壓配置供應電壓36. . . Bias configuration supply voltage
圖1為本發明之使用記憶體胞元實施一交叉點記憶體陣列的部分示意圖。1 is a partial schematic view of a cross-point memory array implemented using memory cells of the present invention.
圖2A與2B為在交叉點陣列100之內排列的記憶體胞元之一實施例的部份截面圖。2A and 2B are partial cross-sectional views of one embodiment of a memory cell arranged within a cross-point array 100.
圖3-6說明用以製造如圖2A-2B所示之記憶體胞元的交叉點陣列的一製造順序步驟。3-6 illustrate a fabrication sequence step for fabricating a cross-point array of memory cells as shown in Figures 2A-2B.
圖7為本發明的一整合電路的簡化流程圖，該整合電路包括記憶體胞元的交叉點陣列，該記憶體胞元包括一金屬氧化物為基礎之記憶體元件以及一二極體存取裝置。7 is a simplified flow diagram of an integrated circuit of the present invention, the integrated circuit including an array of intersections of memory cells including a metal oxide based memory component and a diode access Device.
圖8為具有一電場增強排列的一範例記憶體胞元的簡單示意圖。Figure 8 is a simplified schematic diagram of an exemplary memory cell having an electric field enhanced arrangement.
圖9為具有一電場增強排列的一範例記憶體胞元的一截面圖TEM影像。Figure 9 is a cross-sectional TEM image of an exemplary memory cell having an electric field enhanced arrangement.
圖10為在中央的電場v.s.記憶體胞元的直徑的圖，係由模擬以範例記憶體胞元來重設與設定操作而來，兩者皆包括具有與不具有一電場增強排列的情況。Figure 10 is a graph of the diameter of the central electric field v.s. memory cells, which are simulated and reset by the exemplary memory cells, both with and without an electric field enhancement arrangement.
圖11為由具有一電場增強排列的各種直徑範例記憶體胞元在一形成操作下模擬而來的截面圖的電場圖。Figure 11 is an electric field diagram of a cross-sectional view simulated by a variety of diameter exemplary memory cells having an electric field enhanced arrangement under a forming operation.
圖12為由具有電場增強排列的100 nm直徑的示範記憶體胞元模擬而來的電場的二維圖。Figure 12 is a two dimensional map of an electric field simulated from a 100 nm diameter exemplary memory cell with an electric field enhanced arrangement.
圖13為由具有電場增強排列的20 nm直徑的示範記憶體胞元模擬而來的電場的二維圖。Figure 13 is a two-dimensional plot of an electric field simulated from a 20 nm diameter exemplary memory cell with an electric field enhanced arrangement.
圖14為由具有電場增強排列的各種直徑的範例記憶體胞元在一形成操作下的實驗結果而來的脈衝電壓圖。Figure 14 is a pulse voltage diagram of experimental results of a sample memory cell of various diameters having an electric field enhanced arrangement under a forming operation.
圖15為由具有電場增強排列的各種直徑的範例記憶體胞元在各種操作下的實驗結果而來的電流圖。Figure 15 is a graph of currents from experimental results of exemplary memory cells of various diameters with enhanced electric field alignment under various operations.
圖16為由具有電場增強排列的60 nm直徑的範例記憶體胞元在重設與設定操作的多次循環下的實驗結果而來的電阻v.s.脈衝電壓期間圖。Figure 16 is a graph of resistance v.s. pulse voltage period from experimental results of a 60 nm diameter sample memory cell with an electric field enhanced arrangement under multiple cycles of reset and set operations.
圖17為由具有電場增強排列的60 nm直徑的範例記憶體胞元在重設與設定操作的多次循環下而來的電阻v.s.循環次數圖。Figure 17 is a graph of the number of resistance v.s. cycles from multiple cycles of reset and set operations of a 60 nm diameter example memory cell with an electric field enhanced arrangement.
圖18為對於具有電場增強排列的60 nm直徑的範例記憶體胞元在一實質的加熱期間後的電阻v.s.保持時間圖。Figure 18 is a graph showing the resistance v.s. retention time for a 60 nm diameter example memory cell with an electric field enhanced arrangement after a substantial heating period.
100．．．記憶體陣列100. . . Memory array
110,110a,110b,110c．．．字線110, 110a, 110b, 110c. . . Word line
120,120a,120b,120c．．．位元線120, 120a, 120b, 120c. . . Bit line
115．．．記憶體胞元115. . . Memory cell
130．．．二極體130. . . Dipole
140．．．記憶體元件140. . . Memory component
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