本申請案係根據先行申請之日本專利申請案(申請號為2010-210476，申請日為2010年9月21日)主張優先權，本案藉由參照而併入該案所有內容。The present application claims priority based on the prior Japanese patent application (Application No. 2010-210476, filed on Sep. 21, 2010), which is incorporated herein by reference.
本發明之實施型態係有關於半導體元件及其製造方法。Embodiments of the present invention relate to semiconductor devices and methods of fabricating the same.
MOSFET(Metal Oxide Semiconductor Field Effect Transistor)或IGBT(Insulated Gate Bipolar Transistor)等之Power半導體元件，係具有高速開關特性、數十～數百V之反向阻止電壓(耐壓)，廣泛被使用於家庭用電氣機器、通訊機器、車載用馬達等之電力變換、控制等。於是，為了讓該等機器之效率提高、消耗電力下降，而對於半導體元件，謀求具有高耐壓及低通態電阻(On-State Resistance)之特性。例如，具備交互地配置p型及n型半導體層之超級接合(super junction)構造之半導體元件方面，可兼具高耐壓與低通態電阻。A Power semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) has a high-speed switching characteristic and a reverse blocking voltage (withstand voltage) of several tens to several hundreds V, and is widely used in homes. Power conversion, control, etc. of electrical equipment, communication equipment, and vehicle-mounted motors. Therefore, in order to improve the efficiency of these devices and reduce the power consumption, the semiconductor element has characteristics of high withstand voltage and low on-state resistance. For example, a semiconductor device having a super junction structure in which p-type and n-type semiconductor layers are alternately arranged can have both high withstand voltage and low on-state resistance.
然而，問題在於對超級接合構造施加偏壓時，pn接合之電容會急遽減少，半導體元件之輸出電容會大幅改變。亦即，具備超級接合構造之半導體元件，依存於輸出電容之開關雜訊是較高。於是，一種可以增大輸出電容並減低開關雜訊之、具備超級接合構造之半導體元件是必要的。However, the problem is that when a bias is applied to the super-junction structure, the capacitance of the pn junction is drastically reduced, and the output capacitance of the semiconductor element is largely changed. That is, in the semiconductor device having the super junction structure, the switching noise depending on the output capacitor is high. Therefore, a semiconductor element having a super junction structure which can increase the output capacitance and reduce switching noise is necessary.
本發明之實施型態，係提供一種可以加大輸出電容並減低開關雜訊(switching noise)之、具備超級接合(super junction)構造之半導體元件及其製造方法。According to an embodiment of the present invention, a semiconductor device having a super junction structure and a method of manufacturing the same can be provided which can increase an output capacitance and reduce switching noise.
關於本發明實施型態之半導體元件，係具備：包含交互地被設在沿著第1半導體層主面之方向之第1導電型之第1柱(pillar)與第2導電型之第2柱之第2半導體層，在從前述第2半導體層表面在前述第1半導體層之方向所設置之溝槽(trench)內部被埋入之第1控制電極，與被設在前述第2半導體層上、且連接在前述第1控制電極之第2控制電極。在除了前述第2控制電極所覆蓋之部分以外之前述第2半導體層表面，設置第2導電型之第1半導體領域；在前述第1半導體領域之表面，選擇性地設置從前述第2控制電極所覆蓋之前述第2半導體層表面疏離之第1導電型之第2半導體領域。再者，鄰接在前述第2半導體領域之第2導電型之第3半導體領域，是選擇性地被設在前述第1半導體領域之表面。A semiconductor device according to an embodiment of the present invention includes: a first pillar of a first conductivity type and a second pillar of a second conductivity type which are alternately provided in a direction along a principal surface of the first semiconductor layer The second semiconductor layer is provided on the first control electrode which is embedded in a trench provided in the direction of the first semiconductor layer from the surface of the second semiconductor layer, and is provided on the second semiconductor layer And connected to the second control electrode of the first control electrode. a first semiconductor region of a second conductivity type is provided on a surface of the second semiconductor layer excluding a portion covered by the second control electrode, and a second control electrode is selectively provided on a surface of the first semiconductor region The second semiconductor field of the first conductivity type in which the surface of the second semiconductor layer is covered. Further, the third semiconductor field adjacent to the second conductivity type in the second semiconductor field is selectively provided on the surface of the first semiconductor region.
根據本發明實施型態，係能夠提供一種可以加大輸出電容並減低開關雜訊之、具備超級接合構造之半導體元件及其製造方法。According to an embodiment of the present invention, it is possible to provide a semiconductor device having a super junction structure which can increase an output capacitance and reduce switching noise, and a method of manufacturing the same.
以下，針對本發明之實施型態參照圖面加以說明。又，以下之實施型態中，在圖面中之同一部分附以同一圖號而其詳細的說明則酌情省略，針對相異之部分則酌情予以說明。以第1導電型為n型、第2導電型為p型加以說明，但是，將第1導電型設為p型、將第2導電型設為n型亦可。Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same portions in the drawings are denoted by the same reference numerals, and the detailed description thereof will be omitted as appropriate, and the differences will be described as appropriate. Although the first conductivity type is an n-type and the second conductivity type is a p-type, the first conductivity type may be a p-type and the second conductivity type may be an n-type.
圖1係顯示關於本實施型態之半導體元件100之模式圖。圖1(a)係顯示剖面構造之斜視圖，圖1(b)為顯示閘極電極12及15配置之平面圖。圖1(a)，為了顯示閘極電極12及15、與n型源極領域7及P+接觸(contact)領域8，而以除去層間絕緣膜23及源極電極19之狀態顯示(參照圖8)。Fig. 1 is a schematic view showing a semiconductor device 100 of the present embodiment. Fig. 1(a) is a perspective view showing a cross-sectional structure, and Fig. 1(b) is a plan view showing the arrangement of the gate electrodes 12 and 15. 1(a), in order to display the gate electrodes 12 and 15, and the n-type source region 7 and the P+ contact region 8, the state of the interlayer insulating film 23 and the source electrode 19 is removed (see the figure). 8).
如圖1(a)所示，半導體元件100，係具備：第1半導體層之n型汲極層2、第2半導體層之漂移(drift)層3、從漂移層3表面被埋入設在n型汲極層之方向之溝槽(trench)13內部之第1控制電極之閘極電極12、與被設在漂移層3上之第2控制電極之閘極電極15。As shown in FIG. 1(a), the semiconductor device 100 includes an n-type drain layer 2 of a first semiconductor layer, a drift layer 3 of a second semiconductor layer, and a buried surface from the surface of the drift layer 3. The gate electrode 12 of the first control electrode inside the trench 13 in the direction of the n-type drain layer and the gate electrode 15 of the second control electrode provided on the drift layer 3.
漂移層3，係在沿著n型汲極層2之主面2a之方向，包含交互地被設置之第1柱之n型柱4、與第2柱之p型柱5。The drift layer 3 includes an n-type pillar 4 of a first column and a p-type pillar 5 of a second column which are alternately disposed in a direction along the principal surface 2a of the n-type drain layer 2.
閘極電極12，係中介被設在溝槽13內面之第1絕緣膜之閘極絕緣膜11，而被埋入溝槽13內部。The gate electrode 12 is buried in the inside of the trench 13 by interposing the gate insulating film 11 of the first insulating film provided on the inner surface of the trench 13.
閘極電極15，係中介被設在漂移層3表面之第2絕緣膜之閘極絕緣膜14，而被設在漂移層3上。The gate electrode 15 is provided on the drift layer 3 by interposing the gate insulating film 14 of the second insulating film provided on the surface of the drift layer 3.
在漂移層3表面，除了閘極電極15所覆蓋之部分以外，還設置第1半導體領域之p型基極(base)領域6。但是，如圖1所示，沿著閘極電極15之p型基極領域6之外緣6a，也可以是在閘極電極15之下延伸。On the surface of the drift layer 3, in addition to the portion covered by the gate electrode 15, a p-type base region 6 of the first semiconductor region is provided. However, as shown in FIG. 1, the outer edge 6a of the p-type base region 6 along the gate electrode 15 may also extend below the gate electrode 15.
再者，在p型基極領域6之表面，設置著第2半導體領域之n型源極領域7。n型源極領域7，係從閘極電極15所覆蓋之漂移層3表面被疏離設置。Further, on the surface of the p-type base region 6, an n-type source region 7 of the second semiconductor field is provided. The n-type source region 7 is provided so as to be separated from the surface of the drift layer 3 covered by the gate electrode 15.
然後，鄰接在n型源極領域7，第3半導體領域之p+接觸領域8，選擇性地被設在p型基極領域6表面。n型源極領域7、與p+接觸領域8，係導電連接於未圖示之源極電極19。Then, adjacent to the n-type source region 7, the p+ contact region 8 of the third semiconductor field is selectively provided on the surface of the p-type base region 6. The n-type source region 7 and the p+ contact region 8 are electrically connected to a source electrode 19 (not shown).
關於本實施型態之半導體元件100方面，能夠藉由對被埋入溝槽13之閘極電極12施加閘極電壓，中介被形成在p型基極領域6與閘極絕緣11之界面之反轉通道，而在導電連接於n型汲極層2之第1主電之汲極電極、與第2主電極之源極電極19，兩者之間讓汲極電流流過。With respect to the semiconductor device 100 of the present embodiment, the gate voltage can be applied to the gate electrode 12 buried in the trench 13, and the intermediate is formed on the interface between the p-type base region 6 and the gate insulating 11 In the transfer channel, a drain current flows between the first main electric drain electrode electrically connected to the n-type drain layer 2 and the second main electrode source electrode 19.
另一方面，被設在漂移層3上之閘極電極15，係如圖1(a)中所示，n型源極領域7，是挾著p+接觸領域8之一部份8a，並從閘極電極15被疏離設置。藉此，例如，能夠作成即使在被形成在閘極電極15下之p型基極領域6之擴散部6a、與閘極絕緣膜14，之界面形成反轉通道，在閘極電極15下也不會讓汲極電流流動之構成。於是，能夠讓閘極電極15下所形成之反轉通道之閾值電壓變小，防止汲極電流集中在閘極電極15。On the other hand, the gate electrode 15 provided on the drift layer 3 is as shown in FIG. 1(a), and the n-type source region 7 is adjacent to a portion 8a of the p+ contact region 8, and The gate electrode 15 is separated from the gate electrode. Thereby, for example, it is possible to form an inversion channel even at the interface between the diffusion portion 6a of the p-type base region 6 formed under the gate electrode 15 and the gate insulating film 14, and also under the gate electrode 15 Will not let the bungee current flow. Thus, the threshold voltage of the inversion channel formed under the gate electrode 15 can be made small, and the gate current can be prevented from being concentrated on the gate electrode 15.
圖1(b)係例示半導體元件100之閘極電極12及15、與n型柱4及p型柱5之配置關係之平面圖。圖1(a)所示之斜視圖之正面的剖面構造，係模式地顯示圖1(b)中之Ia-Ia剖面。Fig. 1(b) is a plan view showing the arrangement relationship between the gate electrodes 12 and 15 of the semiconductor device 100 and the n-type pillar 4 and the p-type pillar 5. The cross-sectional structure of the front side of the oblique view shown in Fig. 1(a) schematically shows the Ia-Ia cross section in Fig. 1(b).
例如，n型柱4及p型柱5，係能夠延伸於沿著汲極層2主面2a之方向條狀設置。然後，如圖1(a)及(b)所示，閘極電極12，係能夠沿著n型柱4及p型柱5之延伸方向，設置在n型柱4表面所形成之溝槽13中。For example, the n-type pillar 4 and the p-type pillar 5 can be extended in a strip shape along the direction of the main surface 2a of the drain layer 2. Then, as shown in FIGS. 1(a) and 1(b), the gate electrode 12 is provided with a groove 13 formed on the surface of the n-type pillar 4 along the extending direction of the n-type pillar 4 and the p-type pillar 5. in.
閘極電極15，係能夠在與n型柱4及p型柱5之延伸方向交差之方向，梯狀設置連接相鄰接之閘極電極12。然後，在閘極電極15所覆蓋之漂移層3中，係包含p型柱5之一部份。The gate electrode 15 can be connected to the adjacent gate electrode 12 in a ladder shape in a direction intersecting the extending direction of the n-type pillar 4 and the p-type pillar 5. Then, in the drift layer 3 covered by the gate electrode 15, a portion of the p-type pillar 5 is included.
如圖1(b)所示，閘極電極15，係在直交於p型柱5延伸方向之方向，將配置位置交替變換而設置。As shown in FIG. 1(b), the gate electrode 15 is provided in a direction orthogonal to the direction in which the p-type pillar 5 extends, and the arrangement position is alternately changed.
圖2係概念地圖示關於半導體元件100、以及圖14所示比較例之半導體元件600之電壓-電容特性。縱軸顯示電容值C、橫軸顯示源極汲極間電壓Vds。FIG. 2 conceptually illustrates voltage-capacitance characteristics of the semiconductor element 100 and the semiconductor element 600 of the comparative example shown in FIG. The vertical axis shows the capacitance value C and the horizontal axis shows the source-drain voltage Vds .
圖2所示之Cds係半導體元件100之源極汲極間電容，而Cgd1表示半導體元件100之閘極汲極間電容、Cgd2則表示關於比較例之半導體元件600之閘極汲極間電容。As shown in FIG source of C 2ds-based semiconductor device 100 between the drain electrode of the capacitor, and Cgd1 showing a gate electrode of the semiconductor element 100 between the drain capacitance, Cgd2 on said semiconductor element of Comparative Example gate electrode 600. Drain Capacitance.
例如，Cds會隨Vds提高而減少，而在圖2中所示之A領域會急劇變小。該A領域之Cds之減少，係對應在n型柱4與p型柱5之間之pn接合，n型柱4及p型柱5分別擴張之空乏層會連接、漂移層3空乏化。於是，當漂移層3全體空乏層擴張時，Cds趨近於最小值，其後，對於Vds之上昇而顯示緩慢的減少傾向。For example, Cds will decrease as Vds increases, while the A field shown in Figure 2 will drastically become smaller. The decrease in Cds in the A field corresponds to the pn junction between the n-type column 4 and the p-type column 5, and the depletion layers respectively expanding the n-type column 4 and the p-type column 5 are connected, and the drift layer 3 is depleted. Then, when the entire depletion layer of the drift layer 3 is expanded, Cds approaches a minimum value, and thereafter, a tendency to decrease slowly is exhibited with respect to the rise of Vds .
一方面，Cgd1，會隨Vds變高而減少，Vds移到A領域而飽和。其後，顯示對於Vds之上昇而逐漸地增加之傾向。In one aspect, Cgd1, will be increased to decrease with Vds, Vds moved art A saturated. Thereafter, there is a tendency to gradually increase with respect to the rise of Vds .
Cgd1係被埋入溝槽13之閘極電極12之底部、與汲極電極17兩者之間之電容。在源極汲極間施加Vds，隨著從p型基極領域6及p型柱5、與n型柱4之間之pn接合，空乏層擴張至n型柱4而Cgd1減少。Cgd1 is buried in the bottom of the gate electrode 12 of the trench 13 and the capacitance between the drain electrode 17. Vds is applied between the source and the drain, and thevacant layer expands to the n-type pillar 4 and Cgd1 decreases as the pn junction between the p-type base region 6 and the p-type pillar 5 and the n-type pillar 4 is joined.
例如，圖14所示之半導體元件600中，施加Vds，在n型柱4及p型柱5空乏層會擴張直到漂移層3幾乎全體空乏化為止，Cgd2係以大的變化率減少。其後，漂移層3之空乏層擴張會鈍化，顯示Cgd2相對於Vds之上昇而逐漸地減少之傾向。For example, in the semiconductor device 600 shown in FIG. 14, Vds is applied, and the depletion layer of the n-type pillar 4 and the p-type pillar 5 is expanded until the drift layer 3 is almost completely depleted, and the Cgd2 system is reduced at a large rate of change. Thereafter, the expansion of the depletion layer of the drift layer 3 is passivated, showing a tendency that Cgd2 gradually decreases with respect to the rise of Vds .
相對於此，半導體元件100中，在漂移層3上設置閘極電極15，而在其下部並不形成p型基極領域6。因此，當閘極電極15下之p型柱5空乏化時，挾著p型柱5與汲極層2相向之閘極電極15之一部份，則成為挾著空乏層與汲極層2相向之型態。於是，閘極電極15之一部份，重新有助於Cgd1，一旦，減少Cgd1，則顯示Vds上昇而且增加之傾向。On the other hand, in the semiconductor element 100, the gate electrode 15 is provided on the drift layer 3, and the p-type base region 6 is not formed in the lower portion thereof. Therefore, when the p-type pillar 5 under the gate electrode 15 is depleted, a portion of the gate electrode 15 facing the p-type pillar 5 and the drain electrode layer 2 is adjacent to the depletion layer and the drain layer 2 The opposite type. Thus, one portion of the gate electrode 15 re-energizes Cgd1 , and once it decreases Cgd1 , it shows a tendency for Vds to rise and increase.
半導體元件100之輸出電容，係源極汲極間電容Cds、與閘極汲極間電容Cgd1之和。例如，半導體元件100與半導體元件600之相異點，如果是閘極電極15之有無，則可以認為半導體元件100之Cds、與半導體元件600之源極汲極間電容係大致相同。從而，因為Cgd1比Cgd2還要大，所以，半導體元件100之輸出電容，會變得比半導體元件600之輸出電容還要大。在汲極電壓Vds上昇、Cds大幅減少之後，相對的輸出電容之差會更大。The output capacitance of the semiconductor device 100 is the sum of the source-drain inter-electrode capacitance Cds and the gate-drain capacitance Cgd1 . For example, if the semiconductor element 100 is different from the semiconductor element 600, if it is the presence or absence of the gate electrode 15, it is considered that the Cds of the semiconductor element 100 is substantially the same as the source-drain capacitance of the semiconductor element 600. Accordingly, since the Cgd1 bigger than Cgd2, so that the output capacitance of the semiconductor device 100, the semiconductor element becomes higher than the larger output capacitor 600. After the drain voltage Vds rises and Cds decreases drastically, the difference in relative output capacitance will be greater.
例如，使半導體元件100及600開關動作之場合下之汲極電壓之變化量(dV/dt)，係與輸出電容成反比。從而，半導體元件100之汲極電壓之變化量，係比半導體元件600之汲極電壓之變化量還要小。接著，開關雜訊係與汲極電壓之變化率成正比，因而，半導體元件100之雜訊是比半導體元件600之雜訊還要低。For example, the amount of change in the drain voltage (dV/dt) in the case where the semiconductor elements 100 and 600 are switched is inversely proportional to the output capacitance. Therefore, the amount of change in the drain voltage of the semiconductor element 100 is smaller than the amount of change in the drain voltage of the semiconductor element 600. Then, the switching noise system is proportional to the rate of change of the drain voltage, and therefore, the noise of the semiconductor device 100 is lower than the noise of the semiconductor device 600.
亦即，半導體元件100，係作成在漂移層3上設置閘極電極15，而在閘極電極15之下部並不設p型基極領域6之構成。藉此，可以增大閘極汲極間電容Cgd1，並減低開關雜訊。That is, the semiconductor element 100 is formed such that the gate electrode 15 is provided on the drift layer 3, and the p-type base region 6 is not provided in the lower portion of the gate electrode 15. Thereby, the gate-to-drain capacitance Cgd1 can be increased and the switching noise can be reduced.
即使是圖14所示之半導體元件600，例如，閘極電極12之下部，也可以藉由增大從p型基極領域6與n型柱4之邊界突出於朝向汲極層2之方向之量ΔG，而增大閘極汲極間電容Cgd2。Even the semiconductor element 600 shown in FIG. 14 , for example, the lower portion of the gate electrode 12 can be protruded toward the gate layer 2 by increasing the boundary from the p-type base region 6 and the n-type pillar 4 . The amount ΔG increases the gate-bland capacitance Cgd2 .
然而，在增大ΔG使閘極電極12之底部在n型柱4中突出時，漂移層3空乏化而n型柱4之中成為高電場之場合，溝槽13底部之閘極絕緣膜11會更被形成高電場。於是，有因高電場而被加速之熱載子(hot carrier)，會往閘極絕緣膜11內部被注入，成為使閘極絕緣膜11之絕緣性劣化等、使可信賴性降低之原因之場合。However, when ΔG is increased to cause the bottom of the gate electrode 12 to protrude in the n-type pillar 4, the drift layer 3 is depleted and the n-type pillar 4 becomes a high electric field, and the gate insulating film 11 at the bottom of the trench 13 Will be more formed into a high electric field. Then, a hot carrier that is accelerated by a high electric field is injected into the gate insulating film 11, and the insulation property of the gate insulating film 11 is deteriorated, and the reliability is lowered. occasion.
相對於此，關於本實施型態之半導體元件100，係能夠藉由設置閘極電極15增大閘極汲極電容。藉此，也可以減少閘極電極12之往n型柱4之突出量，使可信賴性提升。On the other hand, in the semiconductor device 100 of the present embodiment, the gate drain capacitance can be increased by providing the gate electrode 15. Thereby, the amount of protrusion of the gate electrode 12 to the n-type pillar 4 can also be reduced, and the reliability can be improved.
閘極電極15下部，係成為空乏層擴大到與閘極絕緣膜14相接之漂移層3表面之狀態。但是，閘極電極15之正下方，因為是被保持在低電位之p型基極領域6所挾住，其電場係比漂移層3中央還要低的電場。從而，並無熱載子被注入閘極絕緣膜14，也就沒有使閘極絕緣膜14之絕緣性降低之情事。The lower portion of the gate electrode 15 is in a state in which the depletion layer is expanded to the surface of the drift layer 3 which is in contact with the gate insulating film 14. However, immediately below the gate electrode 15, since the p-type base region 6 held at a low potential is caught, the electric field is lower than the center of the drift layer 3. Therefore, no hot carrier is injected into the gate insulating film 14, and the insulation of the gate insulating film 14 is not lowered.
其次，參照圖3～圖8，說明半導體元件100之製造過程。Next, a manufacturing process of the semiconductor device 100 will be described with reference to FIGS. 3 to 8.
圖3(a)係顯示圖1之Ia-Ia剖面之模式圖，顯示在n型汲極層2上所設之漂移層3表面被形成溝槽13之狀態。Fig. 3(a) is a schematic view showing a cross section of Ia-Ia of Fig. 1, showing a state in which the surface of the drift layer 3 provided on the n-type drain layer 2 is formed with the trench 13.
n型汲極層2及漂移層3，例如，能夠設置在矽基板上。n型汲極層2，係能夠採用高濃度地塗布n型不純物之矽層。漂移層3，係包含p型柱5與n型柱4所構成之超級接合(super junction)構造。The n-type drain layer 2 and the drift layer 3 can be provided, for example, on a germanium substrate. The n-type drain layer 2 is capable of coating a layer of n-type impurities with a high concentration. The drift layer 3 includes a super junction structure composed of a p-type pillar 5 and an n-type pillar 4.
超級接合構造，例如，能夠在濃度比n型汲極層2還要低之n型矽層之表面，採用RIE(Reactive Ion Etching)法形成溝槽，其後，藉由在溝槽之內部使p型矽晶膜(epitaxial)成長而形成。The super-junction structure, for example, can form a trench by a RIE (Reactive Ion Etching) method on the surface of an n-type germanium layer having a lower concentration than the n-type drain layer 2, and thereafter, by making a groove inside the trench A p-type epitaxial film is grown to form.
其次，在設置溝槽13之漂移層3表面，中介絕緣膜24形成成為閘極電極12及15之導電層22。Next, on the surface of the drift layer 3 on which the trench 13 is provided, the dielectric insulating film 24 is formed as the conductive layer 22 of the gate electrodes 12 and 15.
絕緣膜24，例如，能夠採用熱氧化形成矽層表面之氧化矽膜(SiO2膜)，成為閘極絕緣膜11及閘極絕緣膜14。The insulating film 24 can be, for example, a ruthenium oxide film (SiO2 film) which is thermally oxidized to form a surface of the ruthenium layer, and becomes the gate insulating film 11 and the gate insulating film 14.
導電層22，例如，能夠採用利用CVD(Chemical Vapor Deposition)法形成之聚矽層。For the conductive layer 22, for example, a polyimide layer formed by a CVD (Chemical Vapor Deposition) method can be used.
圖4係顯示圖3後續之製造過程之模式圖，顯示圖案化導電層22形成閘極電極12及15之狀態。4 is a schematic view showing a subsequent manufacturing process of FIG. 3, showing a state in which the patterned conductive layer 22 forms the gate electrodes 12 and 15.
在此，在圖4(a)係顯示圖1(b)之Ia-Ia剖面構造，圖4(b)則顯示IVb-IVb剖面構造。以下，直到圖8都相同。Here, Fig. 4(a) shows the Ia-Ia cross-sectional structure of Fig. 1(b), and Fig. 4(b) shows the IVb-IVb cross-sectional structure. Hereinafter, it is the same until FIG.
例如，如圖4(b)所示，殘留被埋入溝槽13內部之部分，蝕刻漂移層3上之導電層22。藉此，閘極電極12被形成作為所謂溝槽閘極。For example, as shown in FIG. 4(b), the portion buried inside the trench 13 remains, and the conductive layer 22 on the drift layer 3 is etched. Thereby, the gate electrode 12 is formed as a so-called trench gate.
另一方面，閘極電極15，能夠選擇性地蝕刻漂移層3上之導電層22，如圖4(a)所示，連接設置相鄰接之閘極電極12之間。On the other hand, the gate electrode 15 can selectively etch the conductive layer 22 on the drift layer 3, as shown in FIG. 4(a), and connect between adjacent gate electrodes 12.
其次，在設置閘極電極12及15之漂移層3表面，例如，離子注入p型不純物之硼(B)，形成p型基極領域6。Next, on the surface of the drift layer 3 on which the gate electrodes 12 and 15 are provided, for example, boron (B) of p-type impurity is ion-implanted to form a p-type base region 6.
如圖5(a)及(b)所示，在除了閘極電極15所覆蓋之部分以外之漂移層3表面注入硼(B)，形成p型基極領域6。As shown in FIGS. 5(a) and (b), boron (B) is implanted on the surface of the drift layer 3 except for the portion covered by the gate electrode 15, to form a p-type base region 6.
然後，如圖6(a)、(b)所示，在漂移層3表面，例如，選擇性地離子注入n型不純物之砷(As)，形成n型源極領域7。再者，選擇性地離子注入p型不純物之硼(b)，形成p+接觸領域8。Then, as shown in FIGS. 6(a) and (b), on the surface of the drift layer 3, for example, arsenic (As) of an n-type impurity is selectively ion-implanted to form an n-type source region 7. Further, boron (b) of the p-type impurity is selectively ion-implanted to form the p+ contact region 8.
如圖6(a)所示，在除了閘極電極15所覆蓋之部分以外之漂移層3表面，形成n型源極領域7以及p+接觸領域8。As shown in FIG. 6(a), the n-type source region 7 and the p+ contact region 8 are formed on the surface of the drift layer 3 except for the portion covered by the gate electrode 15.
如圖6(b)所示，未設置閘極電極15之部分，係與圖14所示之半導體元件600相同形成溝槽閘極構造之MOSFET。As shown in FIG. 6(b), the portion where the gate electrode 15 is not provided is the same as the semiconductor element 600 shown in FIG. 14 to form a MOSFET having a trench gate structure.
其次，如圖7(a)及圖7(b)所示，在閘極電極12及閘極電極15、n型源極領域7、p+接觸領域8之上，形成層間絕緣膜23。Next, as shown in FIGS. 7(a) and 7(b), an interlayer insulating film 23 is formed on the gate electrode 12 and the gate electrode 15, the n-type source region 7, and the p+ contact region 8.
層間絕緣膜23，例如，能夠採用利用CVD法形成之SiO2膜。As the interlayer insulating film 23, for example, an SiO2 film formed by a CVD method can be used.
然後，如圖8(a)及圖8(b)所示，在閘極電極12及15上殘留層間絕緣膜23，選擇性地蝕刻n型源極領域7及p+接觸領域8之表面之絕緣膜24與層間絕緣膜23。Then, as shown in FIGS. 8(a) and 8(b), an interlayer insulating film 23 is left on the gate electrodes 12 and 15, and the surfaces of the n-type source region 7 and the p+ contact region 8 are selectively etched. The insulating film 24 and the interlayer insulating film 23.
其後，在層間絕緣膜23所覆蓋之閘極電極12及15上、以及、n型源極領域7及p+接觸領域8之表面，形成源極電極19。Thereafter, the source electrode 19 is formed on the gate electrodes 12 and 15 covered by the interlayer insulating film 23, and on the surfaces of the n-type source region 7 and the p+ contact region 8.
再者，能夠在n型汲極層2形成電性地接續之汲極電極17，使半導體元件100之構造完成。Further, the gate electrode 17 which is electrically connected can be formed in the n-type drain layer 2, and the structure of the semiconductor element 100 can be completed.
圖9係模式地顯示關於本實施型態變形例之半導體元件200構造之斜視圖。Fig. 9 is a perspective view schematically showing the configuration of a semiconductor element 200 according to a modification of the present embodiment.
半導體元件200，條狀設置之n型柱4及p型柱5之延伸方向，與被埋入閘極電極12之溝槽13之延伸方向直交之點方面，相異於半導體元件100。In the semiconductor element 200, the extending direction of the strip-shaped n-type pillar 4 and the p-type pillar 5 is different from the semiconductor element 100 in that it is orthogonal to the direction in which the trench 13 of the gate electrode 12 is buried.
半導體元件200中，例如，p型柱5上所設置之閘極電極15之下部，係被p型柱5之一部份之p型領域5b所佔據，直到p型柱5空乏化為止並無助於閘極汲極間電容Cgd。於是，如圖2中所示，在p型柱5空乏化而漂移層3全體成為空乏層時，始有助於Cgd，使汲極電壓Vds上昇同時Cgd增加。In the semiconductor element 200, for example, the lower portion of the gate electrode 15 provided on the p-type pillar 5 is occupied by the p-type field 5b of a portion of the p-type pillar 5 until the p-type pillar 5 is depleted. Helps the gate bucks capacitance Cgd . Then, as shown in FIG. 2, when the p-type pillar 5 is depleted and the entire drift layer 3 becomes a depletion layer, it contributes to Cgd , and the gate voltage Vds rises while Cgd increases.
圖10係模式地顯示關於本實施型態另一變形例之半導體元件300構造之斜視圖。Fig. 10 is a perspective view schematically showing the configuration of a semiconductor element 300 according to another modification of the present embodiment.
半導體元件300中，p型柱35之形成方法是不同於半導體元件100。p型柱35，例如，能夠藉由在對高電阻之晶膜層，選擇性地離子注入n型不純物及p型不純物，施以熱處理使之擴散之後，進而，增加堆積高電阻之晶膜，反覆進行離子注入n型不純物及p型不純物、施以熱處理之工程而形成。In the semiconductor element 300, the formation method of the p-type pillar 35 is different from that of the semiconductor element 100. The p-type pillar 35 can be formed by, for example, selectively ion-implanting an n-type impurity and a p-type impurity into a high-resistance crystal film layer, and then heat-distributing the film, thereby increasing the deposition of a high-resistance crystal film. It is formed by repeatedly performing ion implantation of n-type impurities and p-type impurities and applying heat treatment.
圖11係顯示關於本實施型態變形例之閘極電極配置之平面圖。Fig. 11 is a plan view showing a configuration of a gate electrode relating to a modification of the embodiment.
如圖11(a)所示，能夠條狀設置閘極電極15，在閘極電極12及n型柱4、p型柱5之延伸方向交差設置。As shown in FIG. 11(a), the gate electrode 15 can be provided in a strip shape, and is provided in a direction in which the gate electrode 12, the n-type pillar 4, and the p-type pillar 5 extend.
如圖11(b)所示，將閘極電極12設在p型柱5之兩側，閘極電極15，也可以跨過n型柱4連接閘極電極12之方式設置。該場合下，因為在閘極電極15之下並不設置p型柱5，所以，閘極電極15係直接有助於閘極汲極間電容Cgd。As shown in FIG. 11(b), the gate electrode 12 is provided on both sides of the p-type pillar 5, and the gate electrode 15 may be provided so as to connect the gate electrode 12 across the n-type pillar 4. In this case, because under the p-type pillar 15 is not provided in the gate electrode 5, so that the gate electrode 15 contributes directly to system inter-gate drain capacitance Cgd.
再者，也能夠將閘極電極12設置在沿著漂移層3表面之一方向疏離之複數之部分。於是，閘極電極15，能夠在閘極電極12之疏離部，以連接複數之部分之方式設置。結果，閘極電極12與閘極電極15，可交互串聯設置。Further, it is also possible to provide the gate electrode 12 at a plurality of portions which are separated in one direction along the surface of the drift layer 3. Thus, the gate electrode 15 can be provided in the alienation portion of the gate electrode 12 so as to connect a plurality of portions. As a result, the gate electrode 12 and the gate electrode 15 can be alternately arranged in series.
圖11(c)所示之例中，閘極電極12係於p型柱5之兩側，在p型柱5之延伸方向被疏離設置。閘極電極15，係具有跨過n型柱4而連接相鄰接之閘極電極12之部分(第1接合部15b)、與連接閘極電極12之疏離部ΔU之部分(第2接合部15a)。於是，閘極電極12與閘極電極15，係在n型柱4及p型柱5之延伸方向被串聯設置。如同圖所示，第2接合部15a，將疏離之第1接合部15b在n型柱4上接續，電性地接續閘極電極12之複數之部分。In the example shown in Fig. 11(c), the gate electrode 12 is attached to both sides of the p-type pillar 5, and is disposed apart from the extending direction of the p-type pillar 5. The gate electrode 15 has a portion (the first bonding portion 15b) that connects the adjacent gate electrode 12 across the n-type pillar 4, and a portion of the alienation portion ΔU that connects the gate electrode 12 (the second junction portion) 15a). Then, the gate electrode 12 and the gate electrode 15 are arranged in series in the extending direction of the n-type pillar 4 and the p-type pillar 5. As shown in the figure, the second joint portion 15a connects the first joint portion 15b that is separated from each other on the n-type pillar 4, and electrically connects a plurality of portions of the gate electrode 12.
圖12係顯示具有圖11(a)所示之閘極電極15之半導體元件400之模式圖。圖12(a)係模式地顯示半導體元件400構造之斜視圖，圖12(b)顯示XIIb-XIIb剖面構造之模式圖。Fig. 12 is a schematic view showing a semiconductor device 400 having the gate electrode 15 shown in Fig. 11(a). Fig. 12(a) is a perspective view showing the structure of the semiconductor element 400, and Fig. 12(b) is a schematic view showing the XIIb-XIIb cross-sectional structure.
半導體元件400中，n型柱4及p型柱5是被條狀設置，閘極電極15也是被設成條狀交差於複數之n型柱4及複數之p型柱5。如圖12(a)及(b)所示，閘極電極12，係在n型柱4之表面，沿著其延伸方向被設置。閘極電極15，係與複數之閘極電極12交差，且在其交點電性地連接。於是，因為閘極電極15之下並未設置p型基極領域6，所以，中介閘極絕緣膜11而與複數之n型柱4及p型柱5之表面相對向。In the semiconductor element 400, the n-type pillar 4 and the p-type pillar 5 are provided in a strip shape, and the gate electrode 15 is also provided in a strip shape to intersect the plurality of n-type pillars 4 and a plurality of p-type pillars 5. As shown in FIGS. 12(a) and (b), the gate electrode 12 is provided on the surface of the n-type pillar 4 along its extending direction. The gate electrode 15 intersects with a plurality of gate electrodes 12 and is electrically connected at its intersection. Then, since the p-type base region 6 is not provided under the gate electrode 15, the intermediate gate insulating film 11 faces the surfaces of the plurality of n-type pillars 4 and p-type pillars 5.
藉此，與在閘極電極15之下形成p型基極領域6之場合相比，較能夠增大閘極汲極間電容Cgd。此外，對n型柱4與p型柱5之間之pn接合施加逆偏壓、n型柱4及p型柱5一起空乏化之場合下，閘極汲極間電容Cgd也會變大。Thereby, it is possible to increase the gate-to-drain capacitance Cgd as compared with the case where the p-type base region 6 is formed under the gate electrode 15 . In addition, when a reverse bias is applied to the pn junction between the n-type pillar 4 and the p-type pillar 5, and the n-type pillar 4 and the p-type pillar 5 are depleted together, the gate-to-electrode capacitance Cgd also becomes large. .
在鄰接之閘極電極15之間的漂移層3表面，設置p型基極領域6。接著，在其表面選擇性地設置n型源極領域7與p+接觸領域8。n型源極領域7，係中介閘極絕緣膜11而與閘極電極12之側面相對向。p+接觸領域8，係被設置接續於p型基極領域6，將p型基極領域6與源極電極19(參照圖8(b))維持在相同電位。On the surface of the drift layer 3 between the adjacent gate electrodes 15, a p-type base region 6 is provided. Next, an n-type source region 7 and a p+ contact region 8 are selectively provided on the surface thereof. The n-type source region 7 is an intermediate gate insulating film 11 and faces the side surface of the gate electrode 12. The p+ contact region 8 is connected to the p-type base region 6 and maintains the p-type base region 6 and the source electrode 19 (see FIG. 8(b)) at the same potential.
如圖12(a)所示，n型源極領域7，係與閘極電極15下之漂移層3疏離設置。亦即，如同圖所示，在n型源極領域7與閘極電極15之間，介在p+接觸領域8之一部份8a，而將延伸在閘極電極15下之p型基極領域6之外緣(擴散部)6a、與n型源極領域7予以分離。藉此，抑制中介閘極電極15下所形成之反轉層而流動之汲極電流，迴避電流集中。亦即，如果在p型基極領域6之外緣(擴散部)6a連接n型源極領域7，則中介閘極電極15下所形成之閾值電壓低之反轉層讓汲極電流流動，會有產生電流集中之疑慮。As shown in FIG. 12(a), the n-type source region 7 is provided so as to be spaced apart from the drift layer 3 under the gate electrode 15. That is, as shown in the figure, between the n-type source region 7 and the gate electrode 15, there is a portion 8a of the p+ contact region 8 and a p-type base region extending under the gate electrode 15 The outer edge (diffusion portion) 6a is separated from the n-type source region 7. Thereby, the drain current flowing through the inversion layer formed under the intermediate gate electrode 15 is suppressed, and current concentration is avoided. That is, if the n-type source region 7 is connected to the outer edge (diffusion portion) 6a of the p-type base region 6, the inversion layer having a low threshold voltage formed under the intermediate gate electrode 15 causes the drain current to flow. There will be doubts about current concentration.
以上，第1實施型態中，係將電性地接續在閘極電極12之閘極電極15，中介閘極絕緣膜11而設在漂移層3表面。於是，藉由在閘極電極15下並不設p型基極領域，增大閘極汲極電容並減低開關雜訊。再者，將n型源極領域7從閘極電極15疏離而形成，抑制在閘極電極15下之閾值電壓低之反轉層流動之電流。藉此，在包含閘極電極12之溝槽閘極讓汲極電流流動，緩和電流集中。As described above, in the first embodiment, the gate electrode 15 of the gate electrode 12 is electrically connected to the gate electrode 15 and the gate insulating film 11 is provided on the surface of the drift layer 3. Thus, by not providing the p-type base region under the gate electrode 15, the gate drain capacitance is increased and the switching noise is reduced. Further, the n-type source region 7 is formed by being separated from the gate electrode 15, and the current flowing in the inversion layer having a low threshold voltage under the gate electrode 15 is suppressed. Thereby, the gate gate including the gate electrode 12 allows the drain current to flow, and the current concentration is alleviated.
圖13係顯示關於第2實施型態之半導體元件500構造之模式圖。圖13(a)係顯示除了源極電極19及層間絕緣膜23(參照圖8)以外之半導體元件500之晶片面之一部份之平面圖。圖13(b)則模式地顯示半導體元件500構造之斜視圖。Fig. 13 is a schematic view showing the configuration of the semiconductor device 500 of the second embodiment. Fig. 13 (a) is a plan view showing a part of the wafer surface of the semiconductor element 500 except the source electrode 19 and the interlayer insulating film 23 (see Fig. 8). Fig. 13(b) is a perspective view showing the configuration of the semiconductor element 500 in a schematic manner.
半導體元件500，係在n型柱4表面，沿著其延伸方向設置閘極電極12。於是，閘極電極15，係在設置n型柱4及p型柱5之漂移層3之領域大致全面，中介閘極絕緣膜11而被形成。The semiconductor element 500 is provided on the surface of the n-type pillar 4, and the gate electrode 12 is provided along the extending direction thereof. Then, the gate electrode 15 is formed in a substantially comprehensive field in which the drift layer 3 of the n-type pillar 4 and the p-type pillar 5 is provided, and the gate insulating film 11 is interposed.
p型基極領域6，在平行於n型汲極層2之主面2a之平面看來，係被設成散布於漂移層3表面之型態。於是，在閘極電極15，設置從其表面貫通到p型基極領域6之複數之開口31。The p-type base region 6 is formed in a pattern dispersed on the surface of the drift layer 3 in a plane parallel to the principal surface 2a of the n-type drain layer 2. Then, at the gate electrode 15, a plurality of openings 31 penetrating from the surface thereof to the p-type base region 6 are provided.
再者，在作成開口31底面之p型基極領域6之表面，選擇性地設置n型源極領域7、鄰接於n型源極領域7之p+接觸領域8。p型基極領域6，係被設在p型柱5上。於是，p+接觸領域8被形成接續在p型基極領域6。Further, on the surface of the p-type base region 6 on the bottom surface of the opening 31, the n-type source region 7 and the p+ contact region 8 adjacent to the n-type source region 7 are selectively provided. The p-type base field 6 is provided on the p-type column 5. Thus, the p+ contact field 8 is formed in the p-type base field 6.
半導體元件500，在被施加閘極電壓之場合下，在中介閘極電極15與閘極絕緣膜11而相向之p型基極領域6表面形成反轉層，且在源極汲極間讓汲極電流流動。再者，在中介閘極電極15與閘極絕緣膜11而相向之p型柱5表面也形成反轉層。藉此，在n型柱4之全體讓汲極電流流動，減低通態電阻(On-State Resistance)。In the case where the gate voltage is applied, the semiconductor element 500 forms an inversion layer on the surface of the p-type base region 6 where the intermediate gate electrode 15 and the gate insulating film 11 face each other, and between the source and the drain Extreme current flows. Further, an inversion layer is also formed on the surface of the p-type pillar 5 where the intermediate gate electrode 15 and the gate insulating film 11 face each other. Thereby, the drain current flows in the entire n-type pillar 4, and the On-State Resistance is reduced.
一方面，在n型柱4表面設置閘極電極12，與單純之平面閘極(planar gate)構造相比，較能夠增大閘極汲極間電容Cgd。藉此，能夠使輸出電容增加並減低開關雜訊。On the one hand, the gate electrode 12 is provided on the surface of the n-type pillar 4, and the gate-to-deuterium capacitance Cgd can be increased as compared with a simple planar gate structure. Thereby, the output capacitance can be increased and the switching noise can be reduced.
如上述實施型態所示，閘極電極12及15，係能夠配合n型柱4及p型柱5之構成、以及、所期待之閘極汲極間電容Cgd，選擇適當、適合之配置以設置。As shown in the above embodiment, the gate electrodes 12 and 15 can be combined with the configuration of the n-type pillar 4 and the p-type pillar 5, and the desired gate-to-electrode capacitance Cgd , and the appropriate and suitable configuration can be selected. To set.
上述實施型態，係針對n型柱4及p型柱5被條狀設置之例加以說明，但是，並非就被限定於此，也能夠適用於被構成格子狀、點狀等之超級接合構造。而且，溝槽閘極之構成雖也是針對條狀設置之例加以說明，但只要是與組合低電容之溝槽閘極構造、與高電容之表面閘極構造之實施型態之旨趣一致之構成，便不受限定於前述之例。In the above-described embodiment, the example in which the n-type column 4 and the p-type column 5 are provided in a strip shape is described. However, the present invention is not limited thereto, and can be applied to a super-joint structure in which a lattice shape or a dot shape is formed. . Further, although the configuration of the trench gate is also described as an example of the strip-shaped arrangement, it is equivalent to the combination of the low-capacitance trench gate structure and the high-capacitance surface gate structure. It is not limited to the foregoing examples.
以上，參照關於本發明之一實施型態加以說明本發明，但，本發明並不受限定於該等之實施型態。例如，基於申請時之技術水準，該業者得以作成之設計變更、或材料變更等，形成與本發明之技術上的思想相同之實施型態等等也被包含在本發明之技術的範圍。The present invention has been described above with reference to an embodiment of the present invention, but the present invention is not limited to the embodiments. For example, it is also within the scope of the technology of the present invention to form a design change, a material change, etc., which is the same as the technical idea of the present invention, based on the technical level at the time of application.
上述之實施型態，係以將矽作為材料之縱型Power MOSFET為例加以說明，但，如具有MOS閘極構造、以及、n型柱、p型柱之構造即可適用。例如，也可以適用於橫型裝置、或IGBT等其他開關裝置。材料則並不受限於矽，也適用於所謂SiC、GaN等材料，也能夠得到同樣效果。The above-described embodiment is described by taking a vertical power MOSFET using ruthenium as a material. However, it is applicable to a structure having a MOS gate structure and an n-type pillar or a p-type pillar. For example, it can also be applied to a horizontal device or another switching device such as an IGBT. The material is not limited to germanium, and is also applicable to materials such as SiC and GaN, and the same effect can be obtained.
100．．．半導體元件100. . . Semiconductor component
2．．．n型汲極層2. . . N-type bungee layer
3．．．漂移(drift)層3. . . Drift layer
4．．．n型柱4. . . N-column
5．．．p型柱5. . . P-column
6．．．p型基極(base)領域6. . . P-type base field
7．．．n型源極領域7. . . N-type source field
8．．．P+接觸(contact)領域8. . . P+ contact field
11,14．．．閘極絕緣膜11,14. . . Gate insulating film
12,15．．．閘極電極12,15. . . Gate electrode
13．．．溝槽(trench)13. . . Trench
19．．．源極電極19. . . Source electrode
23．．．層間絕緣膜twenty three. . . Interlayer insulating film
圖1係顯示關於第1實施型態之半導體元件之模式圖。(a)係顯示Ia-Ia剖面構造之斜視圖，(b)為顯示閘極電極配置之平面圖。Fig. 1 is a schematic view showing a semiconductor device of a first embodiment. (a) is a perspective view showing a cross-sectional structure of Ia-Ia, and (b) is a plan view showing a configuration of a gate electrode.
圖2係圖示關於第1實施型態之半導體元件之電壓-電容特性。Fig. 2 is a view showing voltage-capacitance characteristics of the semiconductor device of the first embodiment.
圖3(a)～圖8(b)係模式地顯示關於第1實施型態之半導體元件之製造過程之剖面圖。在圖3(a)～圖8(b)，各圖(a)係顯示圖1(b)之Ia-Ia剖面構造，各圖(b)則顯示圖1(b)之IVb-IVb剖面構造。3(a) to 8(b) are schematic cross-sectional views showing a manufacturing process of the semiconductor device of the first embodiment. 3(a) to 8(b), each of the figures (a) shows a cross-sectional structure of Ia-Ia of Fig. 1(b), and each of the figures (b) shows a cross-sectional structure of IVb-IVb of Fig. 1(b). .
圖9係模式地顯示關於第1實施型態變形例之半導體元件構造之斜視圖。Fig. 9 is a perspective view schematically showing the structure of a semiconductor element according to a modification of the first embodiment.
圖10係模式地顯示關於第1實施型態另一變形例之半導體元件構造之斜視圖。Fig. 10 is a perspective view showing the structure of a semiconductor element according to another modification of the first embodiment.
圖11係顯示關於第1實施型態變形例之閘極電極配置之平面圖。Fig. 11 is a plan view showing a configuration of a gate electrode in a modification of the first embodiment.
圖12係顯示具有圖11(a)所示之閘極電極之半導體元件之模式圖。(a)係模式地顯示半導體元件構造之斜視圖，(b)為顯示XIIb-XIIb剖面構造之模式圖。Fig. 12 is a schematic view showing a semiconductor element having the gate electrode shown in Fig. 11 (a). (a) is a perspective view showing the structure of the semiconductor element, and (b) is a schematic view showing the XIIb-XIIb cross-sectional structure.
圖13係顯示關於第2實施型態之半導體元件構造之模式圖。(a)係顯示除了源極電極及層間絕緣膜以外之半導體元件晶片面之一部份之平面圖。(b)則模式地顯示半導體元件構造之斜視圖。Fig. 13 is a schematic view showing the structure of a semiconductor element of a second embodiment. (a) is a plan view showing a part of the wafer surface of the semiconductor element except the source electrode and the interlayer insulating film. (b) A perspective view showing the structure of the semiconductor element in a pattern.
圖14係模式地顯示關於比較例之半導體元件之斜視圖。Fig. 14 is a perspective view showing a semiconductor element relating to a comparative example.
100．．．半導體元件100. . . Semiconductor component
2．．．n型汲極層2. . . N-type bungee layer
2a．．．汲極層2主面2a. . . Main surface of bungee layer 2
3．．．漂移(drift)層3. . . Drift layer
4．．．n型柱4. . . N-column
5．．．p型柱5. . . P-column
6．．．p型基極(base)領域6. . . P-type base field
6a．．．外緣6a. . . Outer edge
7．．．n型源極領域7. . . N-type source field
8．．．P+接觸(contact)領域8. . . P+ contact field
11,14．．．閘極絕緣膜11,14. . . Gate insulating film
12,15．．．閘極電極12,15. . . Gate electrode
13．．．溝槽(trench)13. . . Trench
17．．．汲極電極17. . . Bipolar electrode
| Application Number | Priority Date | Filing Date | Title |
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| JP2010210476 | 2010-09-21 |
| Publication Number | Publication Date |
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| TW201232781A TW201232781A (en) | 2012-08-01 |
| TWI462294Btrue TWI462294B (en) | 2014-11-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100133227ATWI462294B (en) | 2010-09-21 | 2011-09-15 | Semiconductor element and manufacturing method thereof |
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| CN (1) | CN102412298B (en) |
| TW (1) | TWI462294B (en) |
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| US20040012038A1 (en)* | 2002-04-17 | 2004-01-22 | Shigeo Kouzuki | Semiconductor device |
| TW200414273A (en)* | 2002-07-10 | 2004-08-01 | Toshiba Kk | Semiconductor device and the manufacturing method thereof |
| CN1890813A (en)* | 2003-12-24 | 2007-01-03 | 丰田自动车株式会社 | Trench gate field effect devices |
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| TW201232781A (en) | 2012-08-01 |
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