本發明是有關於一種電壓校正電路及方法，且特別是有關於一種電阻不匹配的電壓校正電路及方法。The present invention relates to a voltage correction circuit and method, and more particularly to a voltage correction circuit and method for resistor mismatch.
在積體電路中，電阻值的匹配度往往是一個重要的設計考量。諸如類比數位轉換器(Analog-to-Digital Converter；ADC)或數位類比轉換器(Digital-to-Analog Converter；DAC)，都有可能因為製程偏移所造成的電容不匹配而限制電路的效能，造成電路無法發揮原設計的水準。因為製程技術的限制，電阻的匹配性較電容為差，傳統電容與電阻混用式電路其線性度的瓶頸都在電阻。因此，對於積體電路設計來說，如何能對因製程偏移造成的電阻不匹配做補償，而使設計電路發揮原有效能與精準度，實為是一重要的問題。In integrated circuits, the matching of resistance values is often an important design consideration. Such as Analog-to-Digital Converter (ADC) or Digital-to-Analog Converter (DAC), it is possible to limit the performance of the circuit due to the capacitance mismatch caused by the process offset. The circuit is unable to perform at the level of the original design. Because of the limitations of process technology, the matching of resistors is worse than that of capacitors. The linearity of traditional capacitors and resistors is the resistor. Therefore, for the integrated circuit design, how to compensate for the resistance mismatch caused by the process offset, and make the design circuit play the original performance and accuracy, is an important problem.
本發明提供一種電阻不匹配的電壓校正電路及方法，可校正因電阻匹配不佳而產生的電壓誤差。The invention provides a voltage correction circuit and method for resistor mismatch, which can correct voltage errors caused by poor resistance matching.
本發明提出一種電阻不匹配的電壓校正電路，包括一比較器、一第一電容陣列、一第二電容陣列、一第一切換單元、一第二切換單元、一第三切換單元以及一電阻分壓產生模組。其中第一切換單元耦接於一目標校正電壓、第一電容陣列與比較器的負輸入端之間，切換第一電容陣列、比較器的負輸入端與一目標校正電壓間的耦接關係，以於比較器的負輸入端產生目標校正電壓。第二切換單元耦接於目標校正電壓、一接地電壓、第二電容陣列與比較器的正輸入端之間，切換第二電容陣列、比較器的正輸入端與目標校正電壓和一接地電壓間的耦接關係，以於比較器的正輸入端產生目標校正電壓或一參考電壓的電容分壓。第三切換單元耦接於第二電容陣列中的一第一參考電容、接地電壓以及參考電壓之間，切換第一參考電容、接地電壓和參考電壓間的耦接關係，其中當第二切換單元將第二電容陣列耦接至比較器的正輸入端時，第三切換單元將第一參考電容耦接至參考電壓，而於比較器的正輸入端產生參考電壓的電容分壓。電阻分壓產生模組耦接比較器的輸出端，產生目標校正電壓，並依據比較器的輸出調整目標校正電壓。The invention provides a voltage matching circuit with a resistor mismatch, comprising a comparator, a first capacitor array, a second capacitor array, a first switching unit, a second switching unit, a third switching unit and a resistor Pressure generating module. The first switching unit is coupled between a target correction voltage, the first capacitor array and the negative input end of the comparator, and switches a coupling relationship between the first capacitor array, the negative input end of the comparator, and a target correction voltage. The target correction voltage is generated at the negative input of the comparator. The second switching unit is coupled between the target correction voltage, a ground voltage, the second capacitor array and the positive input terminal of the comparator, and switches between the second capacitor array, the positive input terminal of the comparator, and the target correction voltage and a ground voltage The coupling relationship is such that a positive correction input of the comparator generates a target correction voltage or a capacitance division of a reference voltage. The third switching unit is coupled between a first reference capacitor, a ground voltage, and a reference voltage in the second capacitor array, and switches a coupling relationship between the first reference capacitor, the ground voltage, and the reference voltage, where the second switching unit When the second capacitor array is coupled to the positive input terminal of the comparator, the third switching unit couples the first reference capacitor to the reference voltage, and generates a capacitive voltage division of the reference voltage at the positive input terminal of the comparator. The resistor divider generation module is coupled to the output of the comparator to generate a target correction voltage and adjust the target correction voltage according to the output of the comparator.
在本發明之一實施例中，上述比較器之負輸入端與正輸入端分別具有一第一寄生電容與一第二寄生電容，第一切換單元於一第一操作期間將第一電容陣列與第一寄生電容耦接至一目標校正電壓，並於一第二操作期間將第一電容陣列耦接至比較器的負輸入端，而第二切換單元於第一操作期間將第二電容陣列與第二寄生電容分別耦接至一接地電壓與目標校正電壓，並於第二操作期間將第二電容陣列耦接至比較器的負輸入端，第三切換單元於第一操作期間將第一參考電容連接至接地電壓，並於第二操作期間將第一參考電容連接至參考電壓。In an embodiment of the present invention, the negative input terminal and the positive input terminal of the comparator respectively have a first parasitic capacitance and a second parasitic capacitance, and the first switching unit connects the first capacitor array with a first operation. The first parasitic capacitance is coupled to a target correction voltage, and the first capacitor array is coupled to the negative input terminal of the comparator during a second operation, and the second switching unit is coupled to the second capacitor array during the first operation The second parasitic capacitance is coupled to a ground voltage and a target correction voltage, respectively, and couples the second capacitor array to the negative input terminal of the comparator during the second operation, the third switching unit will first reference during the first operation The capacitor is connected to the ground voltage and the first reference capacitor is connected to the reference voltage during the second operation.
在本發明之一實施例中，上述之第一切換單元包括一第一開關、一第二開關以及一第三開關。其中第一開關耦接於比較器的負輸入端與目標校正電壓之間。第二開關之第一端耦接比較器的負輸入端，第二開關的第二端耦接第一電容陣列。第三開關耦接於第二開關的第二端與目標校正電壓之間，其中在第一操作期間，第一開關、第三開關為導通狀態，而第二開關為斷開狀態，而在第二操作期間，第一開關、第三開關為斷開狀態，第二開關為導通狀態。In an embodiment of the invention, the first switching unit includes a first switch, a second switch, and a third switch. The first switch is coupled between the negative input terminal of the comparator and the target correction voltage. The first end of the second switch is coupled to the negative input end of the comparator, and the second end of the second switch is coupled to the first capacitor array. The third switch is coupled between the second end of the second switch and the target correction voltage, wherein during the first operation, the first switch and the third switch are in an on state, and the second switch is in an off state, and in the During the second operation, the first switch and the third switch are in an off state, and the second switch is in an on state.
在本發明之一實施例中，上述之第二切換單元包括一第四開關、一第五開關以及一第六開關。其中第四開關耦接於比較器的正輸入端與目標校正電壓之間。第五開關之第一端耦接於比較器的正輸入端，第五開關的第二端耦接第二電容陣列。第六開關耦接於第五開關的第二端與接地電壓之間，其中在第一操作期間，第四開關以及第六開關為導通狀態，第五開關為斷開狀態，而在第二操作期間，第四開關以及第六開關為斷開狀態，第五開關為導通狀態。In an embodiment of the invention, the second switching unit includes a fourth switch, a fifth switch, and a sixth switch. The fourth switch is coupled between the positive input terminal of the comparator and the target correction voltage. The first end of the fifth switch is coupled to the positive input end of the comparator, and the second end of the fifth switch is coupled to the second capacitor array. The sixth switch is coupled between the second end of the fifth switch and the ground voltage, wherein during the first operation, the fourth switch and the sixth switch are in an on state, the fifth switch is in an off state, and in the second operation During the period, the fourth switch and the sixth switch are in an off state, and the fifth switch is in an on state.
在本發明之一實施例中，上述之第一電容陣列包括一第二參考電容以及一第三參考電容。其中第三參考電容與第二參考電容並聯耦接於第一切換單元與接地電壓之間。In an embodiment of the invention, the first capacitor array includes a second reference capacitor and a third reference capacitor. The third reference capacitor and the second reference capacitor are coupled in parallel between the first switching unit and the ground voltage.
在本發明之一實施例中，上述之第二電容陣列更包括一第四參考電容，其耦接於第二切換單元與接地電壓之間。In an embodiment of the invention, the second capacitor array further includes a fourth reference capacitor coupled between the second switching unit and the ground voltage.
在本發明之一實施例中，上述之目標校正電壓為參考電壓的電阻分壓。In an embodiment of the invention, the target correction voltage is a resistance division of the reference voltage.
在本發明之一實施例中，上述之第二參考電容之電容值為第三參考電容之電容值的2n-1倍，且第二參考電容與第三參考電容的電容值分別等於第一參考電容與第四參考電容的電容值。In an embodiment of the invention, the capacitance of the second reference capacitor is 2n -1 times the capacitance of the third reference capacitor, and the capacitance values of the second reference capacitor and the third reference capacitor are respectively equal to the first The capacitance of the reference capacitor and the fourth reference capacitor.
在本發明之一實施例中，上述之比較器包括一第一比較單元、一第二比較單元、一第一偏移電容、一第二偏移電容、一第七開關以及一第八開關。其中第一比較單元之正負輸入端分別耦接第二切換單元與第一切換單元。第二比較單元之輸出端耦接電阻分壓產生模組。第一偏移電容耦接於第一比較單元的第一輸出端與第二比較單元的負輸入端之間。第二偏移電容耦接於第一比較單元的第二輸出端與第二比較單元的正輸入端之間。第七開關耦接於第二比較單元的負輸入端與一共同電壓之間。第八開關耦接於第二比較單元的正輸入端與共同電壓之間。其中第七開關與第八開關於第一操作期間為導通狀態，而於第二操作期間為斷開狀態。In an embodiment of the invention, the comparator includes a first comparison unit, a second comparison unit, a first offset capacitor, a second offset capacitor, a seventh switch, and an eighth switch. The positive and negative input terminals of the first comparison unit are respectively coupled to the second switching unit and the first switching unit. The output end of the second comparison unit is coupled to the resistor divider generation module. The first offset capacitor is coupled between the first output end of the first comparison unit and the negative input end of the second comparison unit. The second offset capacitor is coupled between the second output end of the first comparison unit and the positive input end of the second comparison unit. The seventh switch is coupled between the negative input terminal of the second comparison unit and a common voltage. The eighth switch is coupled between the positive input terminal of the second comparison unit and the common voltage. The seventh switch and the eighth switch are in an on state during the first operation and are in an off state during the second operation.
在本發明之一實施例中，上述之電阻分壓產生模組包括一誤差調整單元以及一電阻分壓產生單元。其中誤差調整單元耦接比較器的輸出端。電阻分壓產生單元耦接誤差調整單元，用以對參考電壓進行電阻分壓，誤差調整單元依據比較器的輸出調整電阻分壓產生單元輸出目標校正電壓。In an embodiment of the invention, the resistor divider generation module includes an error adjustment unit and a resistor divider generation unit. The error adjustment unit is coupled to the output of the comparator. The resistance voltage dividing unit is coupled to the error adjusting unit for performing voltage division on the reference voltage, and the error adjusting unit adjusts the resistance voltage dividing unit to output the target correction voltage according to the output of the comparator.
本發明更提出一種電阻不匹配的電壓校正方法，適用於一電壓校正電路，其中電壓校正電路包括一比較器、一第一電容陣列以及一第二電容陣列，電壓校正方法包括下列步驟。在一第一操作期間以一目標校正電壓對第一電容陣列充電，並將第二電容陣列放電至一接地電壓。在一第二操作期間停止對第一電容陣列充電以及對第二電容陣列放電，將第一電容陣列與第二電容陣列分別耦接至比較器的負輸入端與正輸入端，同時並將第二電容陣列中的一參考電容耦接至一參考電壓，以分別於比較器的負輸入端與正輸入端產生目標校正電壓以及參考電壓的電容分壓。依據比較器的輸出調整目標校正電壓。The invention further provides a voltage matching method for resistor mismatch, which is suitable for a voltage correction circuit, wherein the voltage correction circuit comprises a comparator, a first capacitor array and a second capacitor array, and the voltage correction method comprises the following steps. The first capacitor array is charged with a target correction voltage during a first operation and the second capacitor array is discharged to a ground voltage. Stop charging the first capacitor array and discharging the second capacitor array during a second operation, respectively coupling the first capacitor array and the second capacitor array to the negative input terminal and the positive input terminal of the comparator, and A reference capacitor in the two capacitor array is coupled to a reference voltage to generate a target correction voltage and a capacitance division voltage of the reference voltage respectively at the negative input terminal and the positive input terminal of the comparator. The target correction voltage is adjusted according to the output of the comparator.
在本發明之一實施例中，上述電阻不匹配的電壓校正方法更包括在第一操作期間以目標校正電壓對比較器負輸入端之一第一寄生電容與正輸入端之一第二寄生電容進行充電，而在第二操作期間停止對第一寄生電容與第二寄生電容充電。In an embodiment of the invention, the resistor mismatching voltage correcting method further includes: during the first operation, the target parasitic capacitance is opposite to the first parasitic capacitance of the comparator and the second parasitic capacitance of the positive input terminal. Charging is performed while charging of the first parasitic capacitance and the second parasitic capacitance is stopped during the second operation.
在本發明之一實施例中，電阻不匹配的電壓校正方法，更包括在一第一操作期間，以共同電壓對比較器之一第一偏移電容與一第二偏移電容進行充電。In an embodiment of the invention, the voltage matching method of the resistor mismatch further includes charging the first offset capacitor and the second offset capacitor of the comparator with a common voltage during a first operation.
在本發明之一實施例中，上述之第一電容陣列與第二電容陣列具有相同的電容值。In an embodiment of the invention, the first capacitor array and the second capacitor array have the same capacitance value.
基於上述，本發明藉由電容分壓較電阻分壓準確的特性，以目標校正電壓的電容分壓為基準將製程漂移所造成之目標校正電壓的電阻分壓誤差調整至目標範圍內，進而改善電路的效能以及精準度。Based on the above, the present invention adjusts the resistance division error of the target correction voltage caused by the process drift to the target range by using the capacitance partial pressure and the resistance partial pressure accurate characteristic as the reference of the capacitance partial pressure of the target correction voltage, thereby improving The performance and accuracy of the circuit.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1繪示為本發明一實施例之電阻不匹配的電壓校正電路的示意圖。請參照圖1，電壓校正電路100包括一比較器102、一第一電容陣列104、一第二電容陣列106、一電阻分壓產生模組108、一第一切換單元110、一第二切換單元112以及一第三切換單元114，其中第一電容陣列104與第二電容陣列106具有相同的電容值。第一切換單元110耦接於一目標校正電壓VX1、第一電容陣列104與比較器102的負輸入端之間，其中目標校正電壓VX1為一電阻分壓電壓。第二切換單元112耦接於目標校正電壓VX1、一接地電壓GND、第二電容陣列106與比較器102的正輸入端之間，第三切換單元114耦接於第二電容陣列106中的一第一參考電容C1(繪示於圖2中)、接地電壓GND以及一參考電壓Vref之間。電阻分壓產生模組108則耦接比較器102的輸出端，其用以產生目標校正電壓VX1。另外，比較器102的負輸入端與正輸入端分別具有一第一寄生電容CP1與一第二寄生電容CP2。FIG. 1 is a schematic diagram of a voltage correction circuit with a resistor mismatch according to an embodiment of the invention. Referring to FIG. 1 , the voltage correction circuit 100 includes a comparator 102 , a first capacitor array 104 , a second capacitor array 106 , a resistor divider generation module 108 , a first switching unit 110 , and a second switching unit . 112 and a third switching unit 114, wherein the first capacitor array 104 and the second capacitor array 106 have the same capacitance value. The first switching unit 110 is coupled between a target correction voltage VX1, a first capacitor array 104 and a negative input terminal of the comparator 102, wherein the target correction voltage VX1 is a resistor divider voltage. The second switching unit 112 is coupled between the target correction voltage VX1, a ground voltage GND, the second capacitor array 106 and the positive input terminal of the comparator 102, and the third switching unit 114 is coupled to one of the second capacitor arrays 106. The first reference capacitor C1 (shown in FIG. 2), the ground voltage GND, and a reference voltage Vref. The resistor divider generation module 108 is coupled to the output of the comparator 102 for generating the target correction voltage VX1. In addition, the negative input terminal and the positive input terminal of the comparator 102 respectively have a first parasitic capacitance CP1 and a second parasitic capacitance CP2.
其中第一切換單元110切換第一電容陣列104、比較器102的負輸入端與目標校正電壓VX1間的耦接關係，以於比較器102的負輸入端產生目標校正電壓VX1。第二切換單元112切換第二電容陣列106、比較器102的正輸入端與目標校正電壓VX1和接地電壓GND間的耦接關係，以於比較器102的正輸入端產生目標校正電壓VX1或參考電壓Vref的電容分壓。第三切換單元114則切換第一參考電容C1、接地電壓GND和參考電壓Vref間的耦接關係。其中當第二切換單元112將第二電容陣列106耦接至比較器102的正輸入端時，第三切換單元114將第一參考電容C1耦接至參考電壓Vref，而於比較器102的正輸入端產生參考電壓Vref的電容分壓。另外，電阻分壓產生模組108則依據比較器102的輸出調整目標校正電壓VX1。如此便可利用電容分壓較電阻分壓準確的特性，以參考電壓Vref的電容分壓做為基準，依據參考電壓Vref的電容分壓和目標校正電壓VX1的比較結果將製程漂移所造成之目標校正電壓VX1的電阻分壓誤差調整至目標範圍內，進而改善電路的效能以及精準度。The first switching unit 110 switches the coupling relationship between the negative input terminal of the first capacitor array 104 and the comparator 102 and the target correction voltage VX1 to generate a target correction voltage VX1 at the negative input end of the comparator 102. The second switching unit 112 switches the coupling relationship between the positive input terminal of the second capacitor array 106 and the comparator 102 and the target correction voltage VX1 and the ground voltage GND to generate a target correction voltage VX1 or a reference at the positive input terminal of the comparator 102. The voltage division of the voltage Vref. The third switching unit 114 switches the coupling relationship between the first reference capacitor C1, the ground voltage GND, and the reference voltage Vref. When the second switching unit 112 couples the second capacitor array 106 to the positive input terminal of the comparator 102, the third switching unit 114 couples the first reference capacitor C1 to the reference voltage Vref, and the comparator 102 is positive. The input generates a capacitance divider of the reference voltage Vref. In addition, the resistor divider generation module 108 adjusts the target correction voltage VX1 according to the output of the comparator 102. In this way, the capacitor partial pressure can be utilized to accurately measure the voltage division, and the capacitor voltage division of the reference voltage Vref is used as a reference, and the result of the process drift is determined according to the comparison between the capacitance division voltage of the reference voltage Vref and the target correction voltage VX1. The resistance voltage division error of the correction voltage VX1 is adjusted to the target range, thereby improving the efficiency and accuracy of the circuit.
詳細來說，比較器102的負輸入端與正輸入端分別具有一第一寄生電容CP1與一第二寄生電容CP2。其中，第一切換單元110於一第一操作期間將第一電容陣列104與第一寄生電容CP1耦接至目標校正電壓VX1(其為一電阻分壓電壓)，以將第一電容陣列104與第一寄生電容CP1充電至目標校正電壓VX1，並於一第二操作期間停止對第一電容陣列104與第一寄生電容CP1充電，且將第一電容陣列104耦接至比較器102的負輸入端。另一方面，第二切換單元112則於第一操作期間將第二電容陣列106與第二寄生電容CP2分別耦接至一接地電壓GND以及目標校正電壓VX1，以將第二電容陣列106放電至接地電壓，並將第二寄生電容CP2充電至目標校正電壓VX1，而於第二操作期間，第二切換單元112停止對第二寄生電容CP2充電，並將第二電容陣列106耦接至比較器102的負輸入端。另外，第三切換單元114則於第一操作期間將第一參考電容C1連接至接地電壓GND，並於第二操作期間將第一參考電容C1連接至參考電壓Vref。In detail, the negative input terminal and the positive input terminal of the comparator 102 respectively have a first parasitic capacitance CP1 and a second parasitic capacitance CP2. The first switching unit 110 couples the first capacitor array 104 and the first parasitic capacitance CP1 to the target correction voltage VX1 (which is a resistor divider voltage) during a first operation to connect the first capacitor array 104 with The first parasitic capacitance CP1 is charged to the target correction voltage VX1, and stops charging the first capacitor array 104 and the first parasitic capacitance CP1 during a second operation, and couples the first capacitor array 104 to the negative input of the comparator 102. end. On the other hand, the second switching unit 112 respectively couples the second capacitor array 106 and the second parasitic capacitance CP2 to a ground voltage GND and a target correction voltage VX1 during the first operation to discharge the second capacitor array 106 to Grounding voltage and charging the second parasitic capacitance CP2 to the target correction voltage VX1, and during the second operation, the second switching unit 112 stops charging the second parasitic capacitance CP2, and couples the second capacitor array 106 to the comparator The negative input of 102. In addition, the third switching unit 114 connects the first reference capacitor C1 to the ground voltage GND during the first operation, and connects the first reference capacitor C1 to the reference voltage Vref during the second operation.
另外，電阻分壓產生模組108依據比較器102的比較結果來調整其輸出的目標校正電壓VX1。藉由反覆地實施第一操作期間與第二操作期間的操作，即可以分壓較準確的電容分壓做為基準，使目標校正電壓VX1漸漸地趨近參考電壓Vref的電容分壓，而將製程漂移所造成之電阻分壓誤差調整至目標範圍內，進而改善電路的效能以及精準度。In addition, the resistor divider generation module 108 adjusts the target correction voltage VX1 output by the comparator 102 according to the comparison result of the comparator 102. By repeatedly performing the operations during the first operation period and the second operation period, that is, the more accurate capacitance partial pressure can be divided as a reference, and the target correction voltage VX1 gradually approaches the capacitance division voltage of the reference voltage Vref, and The resistance voltage division error caused by the process drift is adjusted to the target range, thereby improving the performance and accuracy of the circuit.
圖2繪示為圖1實施例之電阻不匹配的電壓校正電路的更詳細的示意圖。請參照圖2，在本實施例中，第一電容陣列104包括一第二參考電容C2以及一第三參考電容C3，第二參考電容C2與第三參考電容C3並聯耦接於第一切換單元110與接地電壓GND之間。第二電容陣列106則更包括一第四參考電容C4，其耦接於第二切換單元112與接地電壓GND之間。在本實施例中目標校正電壓VX1為參考電壓Vref的電阻分壓。2 is a more detailed schematic diagram of the voltage correction circuit of the resistor mismatch of the embodiment of FIG. 1. Referring to FIG. 2, in the embodiment, the first capacitor array 104 includes a second reference capacitor C2 and a third reference capacitor C3. The second reference capacitor C2 and the third reference capacitor C3 are coupled in parallel to the first switching unit. 110 is between the ground voltage GND. The second capacitor array 106 further includes a fourth reference capacitor C4 coupled between the second switching unit 112 and the ground voltage GND. In the present embodiment, the target correction voltage VX1 is a resistance division of the reference voltage Vref.
另外，在本實施例中，第一切換單元110包括開關SW1~SW3，第二切換單元112則包括開關SW4~SW6。其中開關SW1耦接於比較器102的負輸入端與目標校正電壓VX1之間。開關SW2的第一端耦接至比較器102的負輸入端，第二端則耦接至第一電容陣列104。開關SW3耦接於開關SW2的第二端與目標校正電壓VX1之間。開關SW4耦接於比較器102的正輸入端與目標校正電壓VX1之間。開關SW5的第一端耦接至比較器102之正輸入端，第二端則耦接至第二電容陣列106。開關SW6耦接於開關SW5的第二端與接地電壓GND之間。In addition, in the embodiment, the first switching unit 110 includes switches SW1 SW SW3 , and the second switching unit 112 includes switches SW4 SW SW6 . The switch SW1 is coupled between the negative input terminal of the comparator 102 and the target correction voltage VX1. The first end of the switch SW2 is coupled to the negative input terminal of the comparator 102, and the second end is coupled to the first capacitor array 104. The switch SW3 is coupled between the second end of the switch SW2 and the target correction voltage VX1. The switch SW4 is coupled between the positive input terminal of the comparator 102 and the target correction voltage VX1. The first end of the switch SW5 is coupled to the positive input terminal of the comparator 102, and the second end is coupled to the second capacitor array 106. The switch SW6 is coupled between the second end of the switch SW5 and the ground voltage GND.
在本實施例中，比較器102包括一第一比較單元OP1、一第二比較單元OP2、一第一偏移電容COS1、一第二偏移電容COS2、開關SW7以及開關SW8。其中第一比較單元OP1之正負輸入端分別耦接至第二切換單元112與第一切換單元110，第一偏移電容COS1耦接於第一比較單元OP1的第一輸出端與第二比較單元OP2的負輸入端之間，第二偏移電容COS2耦接於第一比較單元OP1的第二輸出端與第二比較單元OP2的正輸入端之間。開關SW7耦接於第二比較單元OP2的負輸入端與一共同電壓VCM之間，開關SW8耦接於第二比較單元OP2的正輸入端與共同電壓VCM之間。第二比較單元OP2的輸出端則耦接至電阻分壓產生模組108。其中共同電壓VCM可例如設定為參考電壓Vref的二分之一，然不以此為限。In this embodiment, the comparator 102 includes a first comparison unit OP1, a second comparison unit OP2, a first offset capacitor COS1, a second offset capacitor COS2, a switch SW7, and a switch SW8. The first and second input units of the first comparison unit OP1 are coupled to the first switching unit 112 and the first switching unit 110. The first offset capacitor COS1 is coupled to the first output unit and the second comparison unit of the first comparison unit OP1. The second offset capacitor COS2 is coupled between the second output terminal of the first comparison unit OP1 and the positive input terminal of the second comparison unit OP2. The switch SW7 is coupled between the negative input terminal of the second comparison unit OP2 and a common voltage VCM, and the switch SW8 is coupled between the positive input terminal of the second comparison unit OP2 and the common voltage VCM. The output of the second comparison unit OP2 is coupled to the resistor divider generation module 108. The common voltage VCM can be set, for example, to one-half of the reference voltage Vref, but is not limited thereto.
進一步來說，電阻分壓產生模組108可包括一誤差調整單元204以及一電阻分壓產生單元206。其中誤差調整單元204耦接於比較器102的輸出端與電阻分壓產生單元206之間，誤差調整單元204用以依據比較器102的輸出調整電阻分壓產生單元206輸出目標校正電壓VX1。Further, the resistor divider generation module 108 can include an error adjustment unit 204 and a resistor divider generation unit 206. The error adjustment unit 204 is coupled between the output of the comparator 102 and the resistor divider generation unit 206. The error adjustment unit 204 is configured to output the target correction voltage VX1 according to the output of the comparator 102.
於一第一操作期間，開關SW1、開關SW3、開關SW4、開關SW6、開關SW7與開關SW8為導通狀態，而開關SW2與開關SW5為斷開狀態，另外第三切換單元202則將第一參考電容C1連接至接地電壓GND。如此將使得目標校正電壓VX1得以對第一電容陣列104、第一寄生電容CP1、第二寄生電容CP2充電、共同電壓VCM對第一偏移電容COS1與第二偏移電容COS2進行充電，並使第二電容陣列106被放電至接地電壓GND。藉由對第一偏移電容COS1與第二偏移電容COS2充電可將比較器102的偏移電壓儲存起來，而使比較器102成為一理想的比較器，避免其比較結果受到偏移電壓的影響。此外第一寄生電容CP1與第二寄生電容CP2也將在第一操作期間內被充電至與目標校正電壓VX1具有相同的電壓值。During a first operation, the switch SW1, the switch SW3, the switch SW4, the switch SW6, the switch SW7 and the switch SW8 are in an on state, and the switch SW2 and the switch SW5 are in an off state, and the third switching unit 202 is in a first reference. Capacitor C1 is connected to the ground voltage GND. This will cause the target correction voltage VX1 to charge the first capacitor array 104, the first parasitic capacitance CP1, the second parasitic capacitance CP2, and the common voltage VCM to charge the first offset capacitance COS1 and the second offset capacitance COS2, and The second capacitor array 106 is discharged to the ground voltage GND. The offset voltage of the comparator 102 can be stored by charging the first offset capacitor COS1 and the second offset capacitor COS2, so that the comparator 102 becomes an ideal comparator, and the comparison result is prevented from being offset by voltage. influences. Furthermore, the first parasitic capacitance CP1 and the second parasitic capacitance CP2 will also be charged to have the same voltage value as the target correction voltage VX1 during the first operation period.
在本實施例中，我們假設第四參考電容C4的電容值為C，第一參考電容C1之電容值為第四參考電容C4之電容值的2n-1倍，其中n為正整數，且第一參考電容C1與第四參考電容C4的電容值分別等於第二參考電容C2與第三參考電容C3的電容值。另外，第一寄生電容CP1與第二寄生電容CP2的電容值皆為CP。於第一操作期間，比較器102之正、負輸入端上之電壓V+、V-如下式所示：In this embodiment, we assume that the capacitance value of the fourth reference capacitor C4 is C, and the capacitance value of the first reference capacitor C1 is 2n -1 times the capacitance value of the fourth reference capacitor C4, where n is a positive integer, and The capacitance values of the first reference capacitor C1 and the fourth reference capacitor C4 are respectively equal to the capacitance values of the second reference capacitor C2 and the third reference capacitor C3. In addition, the capacitance values of the first parasitic capacitance CP1 and the second parasitic capacitance CP2 are both CP. During the first operation, the voltages V+ , V− on the positive and negative inputs of comparator 102 are as follows:
因此，第二寄生電容CP2上所儲存的電荷值Q1如下所示：Therefore, the charge value Q1 stored on the second parasitic capacitance CP2 is as follows:
其中ε為電阻分壓時因匹配不佳所產生的誤差量。Where ε is the amount of error due to poor matching when the resistor is divided.
於一第二操作期間，開關SW1、開關SW3、開關SW4、開關SW6、開關SW7與開關SW8為斷開狀態，而開關SW2與開關SW5為導通狀態。如此將使得第一電容陣列104、第一寄生電容CP1與第二寄生電容CP2停止被充電，第二電容陣列106停止放電，第二電容陣列106被耦接至比較器102的正輸入端，而參考電壓Vref可透過第三切換單元202對第二電容陣列106中之第一參考電容C1進行充電。此時第二寄生電容CP2與第二電容陣列106上所儲存的電荷可如下列式子所示：During a second operation, the switch SW1, the switch SW3, the switch SW4, the switch SW6, the switch SW7, and the switch SW8 are in an off state, and the switch SW2 and the switch SW5 are in an on state. This will cause the first capacitor array 104, the first parasitic capacitance CP1 and the second parasitic capacitance CP2 to stop being charged, the second capacitor array 106 to stop discharging, and the second capacitor array 106 being coupled to the positive input terminal of the comparator 102, and The reference voltage Vref can charge the first reference capacitor C1 in the second capacitor array 106 through the third switching unit 202. At this time, the second parasitic capacitance CP2 and the charge stored on the second capacitor array 106 can be as follows:
Q2=(V+-Vref)‧(2n-1)C+V+‧1C+V+‧CP (3)Q2=(V+ -Vref)‧(2n -1)C+V+ ‧1C+V+ ‧CP (3)
基於電荷守恆的原則，儲存電荷Q1與Q2的關係可如下列所示：Based on the principle of conservation of charge, the relationship between stored charge Q1 and Q2 can be as follows:
如此便可得到比較器102之正輸入端上之電壓V+如下所示：Thus, the voltage V+ at the positive input of the comparator 102 can be obtained as follows:
同時，比較器102之負輸入端上之電壓V-則如式(1)所示。由式(5)可看出，電阻分壓時因匹配不佳所產生的誤差量ε被縮減了CP/(2nC+CP)倍。藉由比較器102可比較出正輸入端之電壓V+與負輸入端之電壓V-的大小，如此電阻分壓產生模組108便可依據比較器102的輸出(亦即電壓V+與電壓V-的比較結果)調整其所產生的目標校正電壓VX1。例如當電壓V-大於電壓V+時，電阻分壓產生模組108可調高目標校正電壓VX1的電壓值。誤差調整單元204可藉由比較器102輸出的改變來判斷是否已完成電壓校正，若比較器102的輸出未改變(例如在本實施例中電壓V-仍大於電壓V+時)，則繼續進行下一回合的電壓校正，若比較器102的輸出改變(例如在本實施例中電壓V-轉為小於電壓V+)，則完成電壓校正。At the same time, the voltage V- on the negative input of the comparator 102 is as shown in equation (1). It can be seen from equation (5) that the error amount ε due to poor matching in the resistance division is reduced by CP/(2n C+CP) times. The comparator 102 can compare the voltage V+ of the positive input terminal with the voltage V− of the negative input terminal, so that the resistor divider generating module 108 can be based on the output of the comparator 102 (ie, the voltage V+ and the voltage). The comparison result of V- is adjusted to the target correction voltage VX1 generated by it. For example, when the voltage V- is greater than the voltage V+ , the resistance voltage dividing generating module 108 can adjust the voltage value of the target correction voltage VX1. The error adjustment unit 204 can determine whether the voltage correction has been completed by the change of the output of the comparator 102, and if the output of the comparator 102 has not changed (for example, when the voltage V- is still greater than the voltage V+ in this embodiment), proceeding The voltage correction for the next round, if the output of the comparator 102 changes (for example, in the present embodiment, the voltage V- is turned to be less than the voltage V+ ), the voltage correction is completed.
如此藉由反覆地執行第一操作期間與第二操作期間的動作直到比較器102的輸出結果改變，即可將電阻分壓時因匹配不佳所產生的誤差量ε降低至目標範圍內，進而得到的理想的電阻分壓。其中目標校正電壓VX1的調整尺度可依據實際情形設定，而目標校正電壓VX1的校正演算法可例如利用串列搜尋法或二元逼近法來獲得。By repeatedly performing the operations during the first operation period and the second operation until the output of the comparator 102 is changed, the error amount ε generated by the poor matching of the resistance partial pressure can be reduced to the target range. The ideal resistor divider is obtained. The adjustment scale of the target correction voltage VX1 may be set according to an actual situation, and the correction algorithm of the target correction voltage VX1 may be obtained, for example, by a tandem search method or a binary approximation method.
詳細來說，電阻分壓產生模組108可例如以圖3的方式來實施。圖3繪示為本發明一實施例之電阻分壓產生模組108的示意圖。其中電阻分壓產生單元206包括多個分壓電阻R1以及多個分壓開關SWR，其串接於一電源電壓VDD與接地電壓GND之間，各個分壓開關SWR與其對應的分壓電阻R1並聯。其中各個分壓開關SWR的導通狀態受控於誤差調整單元204，誤差調整單元204可依據比較器102的輸出調整分壓開關SWR的導通狀態，以調整電阻分壓產生單元206所產生的目標校正電壓VX1。In detail, the resistor divider generation module 108 can be implemented, for example, in the manner of FIG. FIG. 3 is a schematic diagram of a resistor divider generation module 108 according to an embodiment of the invention. The resistor divider generating unit 206 includes a plurality of voltage dividing resistors R1 and a plurality of voltage dividing switches SWR connected in series between a power supply voltage VDD and a ground voltage GND, and each voltage dividing switch SWR is connected in parallel with its corresponding voltage dividing resistor R1. . The conduction state of each of the voltage dividing switches SWR is controlled by the error adjustment unit 204, and the error adjustment unit 204 can adjust the conduction state of the voltage dividing switch SWR according to the output of the comparator 102 to adjust the target correction generated by the resistance voltage dividing generating unit 206. Voltage VX1.
值得注意的是，圖3所繪示之電阻分壓產生模組108僅為本發明的一示範性實施例，實際應用上並不以此為限。此外，上述第一參考電容C1的電容值亦不限定為第四參考電容C4之電容值的2n-1倍，第一參考電容C1的電容值將影響電壓校正電路200校正目標校正電壓VX1的精確度，使用者可依實際情形設計。It should be noted that the resistor divider generation module 108 illustrated in FIG. 3 is only an exemplary embodiment of the present invention, and the actual application is not limited thereto. In addition, the capacitance value of the first reference capacitor C1 is not limited to 2n -1 times the capacitance value of the fourth reference capacitor C4, and the capacitance value of the first reference capacitor C1 will affect the voltage correction circuit 200 to correct the target correction voltage VX1. Accuracy, the user can design according to the actual situation.
圖4繪示為本發明一實施例之電阻不匹配的電壓校正方法流程圖。歸納上述電壓校正電路100的電壓校正方法可包括下列步驟。在第一操作期間，以目標校正電壓VX1對第一電容陣列104充電，並將第二電容陣列106放電至接地電壓GND(步驟S402)。在考慮比較器102輸入端的寄生電容效應時，此時亦對比較器102負輸入端之第一寄生電容CP1與正輸入端之第二寄生電容CP2進行充電。在第二操作期間，停止對第一電容陣列104充電以及對第二電容陣列106放電，將第一電容陣列104與第二電容陣列106分別耦接至比較器102的負輸入端與正輸入端，同時並將第二電容陣列中的一參考電容耦接至一參考電壓，以分別於比較器102的負輸入端與正輸入端產生目標校正電壓VX1以及參考電壓Vref的電容分壓(步驟S404)。在考慮比較器102輸入端的寄生電容效應時，此時停止對第一寄生電容CP1與第二寄生電容CP2充電。在部分實施例中，亦可在第一操作期間先對比較器102的第一偏移電容COS1與第二偏移電容COS2進行充電，以避免其比較器102的比較結果受到偏移電壓影響。4 is a flow chart of a voltage correction method for resistor mismatch according to an embodiment of the invention. The voltage correction method of summarizing the voltage correction circuit 100 described above may include the following steps. During the first operation, the first capacitor array 104 is charged with the target correction voltage VX1, and the second capacitor array 106 is discharged to the ground voltage GND (step S402). When considering the parasitic capacitance effect at the input of the comparator 102, the first parasitic capacitance CP1 at the negative input terminal of the comparator 102 and the second parasitic capacitance CP2 at the positive input terminal are also charged. During the second operation, the charging of the first capacitor array 104 and the discharging of the second capacitor array 106 are stopped, and the first capacitor array 104 and the second capacitor array 106 are respectively coupled to the negative input terminal and the positive input terminal of the comparator 102. And simultaneously coupling a reference capacitor in the second capacitor array to a reference voltage to generate a capacitance division voltage of the target correction voltage VX1 and the reference voltage Vref at the negative input terminal and the positive input terminal of the comparator 102 respectively (step S404) ). When the parasitic capacitance effect at the input of the comparator 102 is considered, the charging of the first parasitic capacitance CP1 and the second parasitic capacitance CP2 is stopped at this time. In some embodiments, the first offset capacitor COS1 and the second offset capacitor COS2 of the comparator 102 may also be charged during the first operation to prevent the comparison result of the comparator 102 from being affected by the offset voltage.
接著，依據比較器102的輸出調整目標校正電壓VX1(步驟S406)。如此藉由重複步驟S402~S406，即可使目標校正電壓VX1逐漸趨近參考電壓Vref的電容分壓，而將製程漂移所造成之目標校正電壓VX1的電阻分壓誤差調整至目標範圍內，進而改善電路的效能以及精準度。Next, the target correction voltage VX1 is adjusted in accordance with the output of the comparator 102 (step S406). By repeating steps S402 to S406, the target correction voltage VX1 can gradually approach the capacitance division of the reference voltage Vref, and the resistance division error of the target correction voltage VX1 caused by the process drift can be adjusted to the target range. Improve circuit performance and accuracy.
綜上所述，本發明利用第一電容陣列以及第二電容陣列對目標校正電壓進行電容分壓，以於比較器的正負輸入端分別產生參考電壓的電容分壓以及目標校正電壓，並依據目標校正電壓的電容分壓和目標校正電壓的比較結果調整目標校正電壓，以使目標校正電壓逐漸趨近參考電壓的電容分壓。如此藉由電容分壓較電阻分壓準確的特性，以目標校正電壓的電容分壓為基準將製程漂移所造成之目標校正電壓的電阻分壓誤差調整至目標範圍內，即可改善電路的效能以及精準度。In summary, the present invention utilizes a first capacitor array and a second capacitor array to capacitively divide a target correction voltage to generate a capacitance partial voltage of a reference voltage and a target correction voltage at the positive and negative input terminals of the comparator, respectively, according to the target. The comparison result of the capacitance partial pressure of the correction voltage and the target correction voltage adjusts the target correction voltage so that the target correction voltage gradually approaches the capacitance division of the reference voltage. Thus, by the capacitance partial pressure and the resistance partial pressure accurate characteristic, the resistance division error of the target correction voltage caused by the process drift is adjusted to the target range based on the capacitance partial pressure of the target correction voltage, thereby improving the circuit performance. And accuracy.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．電壓校正電路100. . . Voltage correction circuit
102．．．比較器102. . . Comparators
104、106．．．電容陣列104, 106. . . Capacitor array
108．．．電阻分壓產生模組108. . . Resistance divider generation module
110、112、114、202．．．切換單元110, 112, 114, 202. . . Switching unit
204．．．誤差調整單元204. . . Error adjustment unit
206．．．電阻分壓產生單元206. . . Resistance divider generating unit
S402~S406．．．電壓校正方法的流程步驟S402~S406. . . Process steps of the voltage calibration method
SW1~SW8．．．開關SW1~SW8. . . switch
CP1、CP2．．．寄生電容CP1, CP2. . . Parasitic capacitance
VX1．．．目標校正電壓VX1. . . Target correction voltage
GND．．．接地電壓GND. . . Ground voltage
C1~C4．．．參考電容C1~C4. . . Reference capacitor
Vref．．．參考電壓Vref. . . Reference voltage
OP1、OP2．．．比較單元OP1, OP2. . . Comparison unit
COS1、COS2．．．偏移電容COS1, COS2. . . Offset capacitance
VCM．．．共同電壓VCM. . . Common voltage
R1．．．分壓電阻R1. . . Voltage divider resistor
VDD．．．電源電壓VDD. . . voltage
圖1繪示為本發明一實施例之電阻不匹配的電壓校正電路的示意圖。FIG. 1 is a schematic diagram of a voltage correction circuit with a resistor mismatch according to an embodiment of the invention.
圖2繪示為圖1實施例之電阻不匹配的電壓校正電路的更詳細的示意圖。2 is a more detailed schematic diagram of the voltage correction circuit of the resistor mismatch of the embodiment of FIG. 1.
圖3繪示為本發明一實施例之電阻分壓產生模組的示意圖。FIG. 3 is a schematic diagram of a resistor divider generating module according to an embodiment of the invention.
圖4繪示為本發明另一實施例之電壓校正方法的流程圖。4 is a flow chart of a voltage calibration method according to another embodiment of the present invention.
100．．．電壓校正電路100. . . Voltage correction circuit
102．．．比較器102. . . Comparators
104、106．．．電容陣列104, 106. . . Capacitor array
108．．．電阻分壓產生模組108. . . Resistance divider generation module
110、112、114．．．切換單元110, 112, 114. . . Switching unit
CP1、CP2．．．寄生電容CP1, CP2. . . Parasitic capacitance
VX1．．．目標校正電壓VX1. . . Target correction voltage
GND．．．接地電壓GND. . . Ground voltage
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100116860ATWI446712B (en) | 2011-05-13 | 2011-05-13 | Voltage calibration circuit and method for resistance mismatch |
| CN201110133057.5ACN102778913B (en) | 2011-05-13 | 2011-05-18 | Voltage correction circuit and method for unmatched resistance |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100116860ATWI446712B (en) | 2011-05-13 | 2011-05-13 | Voltage calibration circuit and method for resistance mismatch |
| Publication Number | Publication Date |
|---|---|
| TW201246781A TW201246781A (en) | 2012-11-16 |
| TWI446712Btrue TWI446712B (en) | 2014-07-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100116860ATWI446712B (en) | 2011-05-13 | 2011-05-13 | Voltage calibration circuit and method for resistance mismatch |
| Country | Link |
|---|---|
| CN (1) | CN102778913B (en) |
| TW (1) | TWI446712B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102020007243B3 (en)* | 2020-11-27 | 2022-05-05 | Daimler Ag | Method for determining at least one current capacitance value of a Y capacitance of a high-voltage vehicle electrical system, and electronic computing device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW441180B (en)* | 1998-05-14 | 2001-06-16 | Ind Tech Res Inst | Enhanced speed type of comparator with serial inverters |
| TWI253553B (en)* | 2004-05-31 | 2006-04-21 | Realtek Semiconductor Corp | Impedance calibration circuit and method thereof |
| US7136006B2 (en)* | 2004-12-16 | 2006-11-14 | Texas Instruments Incorporated | Systems and methods for mismatch cancellation in switched capacitor circuits |
| CN100433329C (en)* | 2005-11-14 | 2008-11-12 | 旺玖科技股份有限公司 | Capacitor mismatch automatic correction circuit |
| US20090167362A1 (en)* | 2007-12-28 | 2009-07-02 | Industrial Technology Research Institute | Comparator |
| US7847601B2 (en)* | 2008-11-21 | 2010-12-07 | Mediatek Inc. | Comparator and pipelined ADC utilizing the same |
| CN101820267B (en)* | 2009-02-26 | 2012-12-26 | 旺玖科技股份有限公司 | Capacitance automatic correction circuit and method |
| TWI391678B (en)* | 2009-09-30 | 2013-04-01 | Raydium Semiconductor Corp | Capacitance measurement circuit and method therefor |
| Publication number | Publication date |
|---|---|
| CN102778913A (en) | 2012-11-14 |
| CN102778913B (en) | 2015-03-25 |
| TW201246781A (en) | 2012-11-16 |
| Publication | Publication Date | Title |
|---|---|---|
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