本發明是有關於一種轉換器，特別是指一種零電壓切換電源轉換器。The present invention relates to a converter, and more particularly to a zero voltage switching power converter.
在論文「B. R. Lin and H. K. Chiang,“Analysis and Implementation of a Soft Switching Interleaved Forward Converter with Current Double Rectifier,”IET Electr. Power Appl.,Vol. 1,No. 5,pp. 697-704,2007.」提出一種習知的電源轉換器。In the paper "BR Lin and HK Chiang, "Analysis and Implementation of a Soft Switching Interleaved Forward Converter with Current Double Rectifier," IET Electr. Power Appl., Vol. 1, No. 5, pp. 697-704, 2007." A conventional power converter is proposed.
但是習知的電源轉換器的缺點為：However, the disadvantages of conventional power converters are:
1.所使用的開關應力是vin/1-D，其中vin為輸入電壓，D為功率開關導通比(duty ratio)，當D=0.5，開關應力為2vin，不適合高輸入電壓應用。1. The switching stress used is vin /1-D, where vin is the input voltage and D is the power switch duty ratio. When D = 0.5, the switching stress is 2vin , which is not suitable for high input voltage applications.
2.使用四個開關，增加硬體成本。2. Use four switches to increase hardware cost.
因此，本發明之目的，即在提供一種減少開關應力的零電壓切換電源轉換器。Accordingly, it is an object of the present invention to provide a zero voltage switching power converter that reduces switching stress.
該零電壓切換電源轉換器，包含：一第一分壓電容，具有一接收一輸入電壓的正極的第一端，及一第二端；一第二分壓電容，具有一電連接於該第一分壓電容之第二端的第一端，及一接收該輸入電壓的負極的第二端；一第一開關，具有一電連接於該第一分壓電容之第一端的第一端，及一第二端，且該第一開關受控制以切換於導通狀態和不導通狀態間；一第二開關，具有一第一端，及一電連接於該第二分壓電容之第二端的第二端，且該第二開關受控制以切換於導通狀態和不導通狀態間；一旁路二極體，具有一電連接於該第二開關之第一端的陽極及一電連接於該第一開關之第二端的陰極；第一及第二變壓器，每一變壓器具有一個初級側繞組和一個次級側繞組，且每一側電感皆具有一第一端及一第二端，其中，該第一變壓器的初級側繞組的第一端電連接於該第一開關之第一端，該第二變壓器的初級側繞組的第一端電連接於該第一變壓器的初級側繞組的第二端，該第二變壓器的初級側繞組的第二端電連接於該第二開關之第一端，該第二變壓器的次級側繞組的第二端電連接於該第一變壓器的次級側繞組的第二端；一共振電感，電連接於該第一分壓電容的第二端與該第一變壓器的初級側繞組的第二端之間；一第一二極體，具有一電連接於該第一變壓器的次級側繞組的第一端的陽極，及一陰極；一第二二極體，具有一電連接於該第二變壓器的次級側繞組的第一端的陽極，及一陰極；一第三二極體，具有一電連接於該第一變壓器的次級側繞組的第二端的陽極，及一電連接於該第一二極體之陰極的陰極；一第四二極體，具有一電連接於該第一變壓器的次級側繞組的第二端的陽極，及一電連接於該第二二極體之陰極的陰極；一第一輸出電感，具有一電連接於該第一二極體之陰極的第一端，及一第二端；一第二輸出電感，具有一電連接於該第二二極體之陰極的第一端，及一第二端；及一輸出電容，電連接於該第一輸出電感的第二端與該第一變壓器的次級側繞組的第二端之間，用於提供一輸出電壓。The zero voltage switching power converter comprises: a first voltage dividing capacitor having a first end of a positive pole receiving an input voltage, and a second end; a second voltage dividing capacitor having an electrical connection to the first a first end of the second end of the voltage dividing capacitor, and a second end of the negative terminal receiving the input voltage; a first switch having a first end electrically connected to the first end of the first voltage dividing capacitor, And a second end, wherein the first switch is controlled to switch between a conducting state and a non-conducting state; a second switch having a first end and a second end electrically connected to the second voltage dividing capacitor a second end, and the second switch is controlled to switch between a conducting state and a non-conducting state; a bypass diode having an anode electrically connected to the first end of the second switch and an electrical connection to the first a cathode of a second end of the switch; first and second transformers, each transformer having a primary side winding and a secondary side winding, and each side inductor has a first end and a second end, wherein The first end of the primary side winding of the first transformer is electrically connected a first end of the first switch, a first end of the primary side winding of the second transformer is electrically connected to a second end of the primary side winding of the first transformer, and a second end of the primary side winding of the second transformer is electrically Connected to the first end of the second switch, the second end of the secondary side winding of the second transformer is electrically connected to the second end of the secondary side winding of the first transformer; a resonant inductor electrically connected to the first end a second terminal of the voltage dividing capacitor and a second end of the primary side winding of the first transformer; a first diode having a first end electrically connected to the secondary side winding of the first transformer An anode, and a cathode; a second diode having an anode electrically connected to the first end of the secondary winding of the second transformer, and a cathode; and a third diode having an electrical connection An anode of the second end of the secondary side winding of the first transformer, and a cathode electrically connected to the cathode of the first diode; a fourth diode having a secondary electrically connected to the first transformer An anode of the second end of the side winding, and an electrical connection to the second diode a cathode of the cathode; a first output inductor having a first end electrically connected to the cathode of the first diode; and a second end; a second output inductor having an electrical connection to the second diode a first end of the cathode of the body, and a second end; and an output capacitor electrically connected between the second end of the first output inductor and the second end of the secondary side winding of the first transformer Provide an output voltage.
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一個較佳實施例的詳細說明中，將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.
如圖1所示，本發明零電壓切換電源轉換器之較佳實施例，包含：第一及第二分壓電容C1、C2、第一及第二開關Q1、Q2、旁路二極體DP、共振電感Lr、第一及第二變壓器T1、T2、第一至第四二極體D1~D4、第一及第二輸出電感L1、L2，及一輸出電容CO。As shown in FIG. 1, a preferred embodiment of the zero voltage switching power converter of the present invention comprises: first and second voltage dividing capacitors C1 , C2 , first and second switches Q1 , Q2 , and a bypass a diode DP , a resonant inductor Lr , first and second transformers T1 , T2 , first to fourth diodes D1 to D4 , first and second output inductors L1 , L2 , And an output capacitor CO .
第一分壓電容C1具有一接收一輸入電壓vin的正極的第一端，及一第二端。The first voltage dividing capacitor C1 has a first end of a positive pole receiving an input voltage vin and a second end.
第二分壓電容C2具有一電連接於該第一分壓電容C1之第二端的第一端，及一接收該輸入電壓vin的負極的第二端。The second voltage dividing capacitor C2 has a first end electrically connected to the second end of the first voltage dividing capacitor C1 and a second end receiving the negative voltage of the input voltage vin .
第一開關Q1具有一電連接於該第一分壓電容C1之第一端的第一端，及一第二端，且該第一開關Q1受控制以切換於導通狀態和不導通狀態間。Having a first switch Q1 is electrically connected to the first voltage divider terminal of the first capacitor C1, a first end and a second end, the first switchQ1 and controlled to switch to a conducting state and a nonconducting Between states.
第二開關Q2具有一第一端，及一電連接於該第二分壓電容C2之第二端的第二端，且該第二開關Q2受控制以切換於導通狀態和不導通狀態間。The second switch Q2 has a first end, and a second end electrically connected to the second end of the second voltage dividing capacitor C2 , and the second switch Q2 is controlled to be switched between a conducting state and a non-conducting state. between.
其中，該二開關Q1、Q2皆是N型功率半導體電晶體且實質上是呈交互導通，且該二開關Q1、Q2的導通期間沒有重疊，且該二開關Q1、Q2之第一端是汲極，該二開關Q1、Q2之第二端是源極。The two switches Q1 and Q2 are all N-type power semiconductor transistors and are substantially in conduction, and the two switches Q1 , Q2 have no overlap during the on period, and the two switches Q1 , Q2 The first end is a drain, and the second ends of the two switches Q1 and Q2 are sources.
旁路二極體DP具有一電連接於該第二開關Q2之第一端的陽極及一電連接於該第一開關Q1之第二端的陰極。The bypass diode DP has an anode electrically connected to the first end of the second switch Q2 and a cathode electrically connected to the second end of the first switch Q1 .
第一及第二變壓器T1、T2具有一個初級側繞組LP1和一個次級側繞組LP2，且每一側繞組LP1、LP2皆具有一第一端及一第二端，其中，該二繞組LP1、LP2的匝數比為N1：N2，且在本實施例中，該第一端是極性點端、該第二端是非極性點端。其中，在圖1中並無標示出該二變壓器T1、T2的磁化電感及漏電感，將於後文中說明。The first and second transformers T1 , T2 have a primary side winding LP1 and a secondary side winding LP2 , and each of the side windings LP1 , LP2 has a first end and a second end, wherein The turns ratio of the two windings LP1 and LP2 is N1 :N2 , and in this embodiment, the first end is a polarity point end, and the second end is a non-polar point end. Here, the magnetizing inductance and the leakage inductance of the two transformers T1 and T2 are not indicated in FIG. 1 and will be described later.
第一變壓器T1的初級側繞組LP1的第一端電連接於該第一開關Q1之第一端。The first end of the primary side winding LP1 of the first transformer T1 is electrically connected to the first end of the first switch Q1 .
第二變壓器T2的初級側繞組LP1的第一端電連接於該第一變壓器T1的初級側繞組LP1的第二端。第二變壓器T2的初級側繞組LP1的第二端電連接於該第二開關Q2之第二端。第二變壓器T2的次級側繞組LP2的第二端電連接於該第一變壓器T1的次級側繞組LP2的第二端。The first end of the primary side winding LP1 of the second transformer T2 is electrically connected to the second end of the primary side winding LP1 of the first transformer T1 . The second end of the primary side winding LP1 of the second transformer T2 is electrically connected to the second end of the second switch Q2 . Second end of the second transformer T2 of the secondary side winding LP2 is connected to the second terminal of the secondary winding LP2 of the first transformer T1.
共振電感Lr電連接於該第一分壓電容C1的第二端與該第一變壓器T1的初級側繞組LP1的第二端之間。The resonant inductor Lr is electrically connected between the second end of the first voltage dividing capacitor C1 and the second end of the primary side winding LP1 of the first transformer T1 .
第一二極體D1具有一電連接於該第一變壓器T1的次級側繞組LP2的第一端的陽極，及一陰極。The first diode D1 has an anode electrically connected to the first end of the secondary side winding LP2 of the first transformer T1 , and a cathode.
第二二極體D2具有一電連接於該第二變壓器T2的次級側繞組LP2的第一端的陽極，及一陰極。The second diode D2 has an anode electrically connected to the first end of the secondary side winding LP2 of the second transformer T2 , and a cathode.
第三二極體D3具有一電連接於該第一變壓器T1的次級側繞組LP2的第二端的陽極，及一電連接於該第一二極體D1之陰極的陰極。The third diode D3 has an anode electrically connected to the second end of the secondary side winding LP2 of the first transformer T1 and a cathode electrically connected to the cathode of the first diode D1 .
第四二極體D4具有一電連接於該該第一變壓器T1的次級側繞組LP2的第二端的陽極，及一電連接於該第二二極體D2之陰極的陰極。The fourth diode D4 has an anode electrically connected to the second end of the secondary side winding LP2 of the first transformer T1 and a cathode electrically connected to the cathode of the second diode D2 .
第一輸出電感L1具有一電連接於該第一二極體D1之陰極的第一端，及一第二端。The first output inductor L1 has a first end electrically connected to the cathode of the first diode D1 and a second end.
第二輸出電感L2具有一電連接於該第二二極體D2之陰極的第一端，及一第二端。The second output inductor L2 has a first end electrically connected to the cathode of the second diode D2 and a second end.
輸出電容CO電連接於該第一輸出電感L1的第二端與該第一變壓器T1的次級側繞組LP2的第二端之間，用於提供一輸出電壓vo到一負載。An output capacitor CO is electrically connected between the second end of the first output inductor L1 and the second end of the secondary side winding LP2 of the first transformer T1 for providing an output voltage vo to a load .
參閱圖2，為本實施例的操作時序圖，其中，參數vg1、vg2分別代表控制該第一及第二開關Q1、Q2是否導通的電壓，參數vCr1、vCr2分別代表該第一及第二開關Q1、Q2的寄生電容Cr1、Cr2的跨壓，參數iLm1、iLm2分別代表流經該二變壓器T1、T2的磁化電感Lm1、Lm2之電流，參數iLr代表流經該共振電感Lr之電流，參數iD1～iD4分別代表流過第一至第四二極體D1~D4的電流，參數iL1、iL2分別代表流過該第一輸出電感L1的電流、流過該第二輸出電感L2的電流，參數iLo代表總輸出電流。依據該二開關Q1、Q2的切換，本實施例會在十種模式下操作，且在以下模式中會於圖示中畫出該二變壓器T1、T2的磁化電感Lm1、Lm2及其漏電感Ll1、Ll2，且導通的元件以實線表示，不導通的元件以虛線表示，以下分別針對每一模式進行說明且令該二開關Q1、Q2的責任導通週期D＜0.5。Referring to FIG. 2, it is an operation timing diagram of the embodiment, wherein the parameters vg1 and vg2 respectively represent voltages for controlling whether the first and second switches Q1 and Q2 are turned on, and the parameters vCr1 and vCr2 respectively represent the The voltages of the parasitic capacitances Cr1 and Cr2 of the first and second switches Q1 and Q2 , the parameters iLm1 and iLm2 respectively represent the magnetizing inductances Lm1 and Lm2 flowing through the two transformers T1 and T2 . Current, the parameter iLr represents the current flowing through the resonant inductor Lr , and the parametersiD1 ～iD4 represent the current flowing through the first to fourth diodes D1 to D4 , respectively, and the parameters iL1 and iL2 respectively represent output current of the first inductor of L1 flows, flows through the second inductor L current output, the parameter i represents2Lo total output current. According to the switching of the two switches Q1 and Q2 , the present embodiment operates in ten modes, and in the following modes, the magnetizing inductances Lm1 and Lm2 of the two transformers T1 and T2 are drawn in the drawing. And the leakage inductances Ll1 , Ll2 , and the turned-on components are indicated by solid lines, and the non-conducting components are indicated by dashed lines. The following descriptions are respectively for each mode and the duty-switching period D of the two switches Q1 and Q2 is made . <0.5.
且以下分析，假設條件為：And the following analysis, the assumptions are:
1.第一及第二變壓器T1、T2的匝數比相等且磁化電感值相等(Lm1=Lm2=Lm)，且漏電感相等Ll1=Ll2=Ll。1. The first and second transformers T1 and T2 have equal turns ratios and equal magnetization inductance values (Lm1 = Lm2 = Lm ), and the leakage inductance is equal toLl1 =Ll2 =Ll .
2.磁化電感Lm遠大於共振電感Lr及漏電感Ll，即Lm>>Lr，Lm>>Ll。2. The magnetizing inductanceLm is much larger than the resonant inductor Lr and the leakage inductance Ll , that is, Lm >>Lr , Lm >>Ll .
3.第一及第二分壓電容C1、C2的電容值遠大於第一及第二開關Q1、Q2的寄生電容Cr1、Cr2。3. The capacitance values of the first and second voltage dividing capacitors C1 and C2 are much larger than the parasitic capacitances Cr1 and Cr2 of the first and second switches Q1 and Q2 .
4.第一及第二輸出電感L1、L2的電感值相等，即L1=L2。4. The inductance values of the first and second output inductors L1 and L2 are equal, that is,L1 =L2 .
5.輸出電容CO很大，輸出電壓vo可視為常數。5. The output capacitor CO is large, and the output voltagevo can be regarded as a constant.
6.操作在連續導通模式(CCM)。6. Operate in continuous conduction mode (CCM).
7.儲存於共振電感Lr及漏電感Ll1、Ll2的能量大於寄生電容Cr1、Cr2的能量，以達成零電壓切換(Zero voltage switching，ZVS)操作。7. The energy stored in the resonant inductor Lr and the leakage inductances Ll1 , Ll2 is greater than the energy of the parasitic capacitancesCr1 ,Cr2 to achieve a zero voltage switching (ZVS) operation.
模式一(時間：t0~t1)：Mode one (time: t0 ~t1):
參閱圖2及圖3a，第一開關Q1導通，而第二開關Q2不導通。Referring to Figures 2 and 3a, the first switch Q1 is turned on and the second switch Q2 is turned off.
第一開關Q1處於導通狀態，使儲存於分壓電容C1的能量藉由變壓器T1傳遞至負載，其詳細操作為：流經第一輸入電感Lm1的電流ｉLm1線性上升，且第一開關Q1二端跨壓vCr1=0，因此第一變壓器T1之初級側繞組LP1跨壓近似於第一分壓電容C1之電壓vP1vC1>0，且於第一變壓器T1之次級側繞組LP2產生一感應電壓vS1=nvC1>0而使第一二極體D1導通、第三二極體D3不導通，且磁化電感Lm1的電壓vL1=vS1-vo>0，其電流iL1線性上升，斜率為vC1/Lm。The first switch Q1 is in an on state, so that the energy stored in the voltage dividing capacitor C1 is transmitted to the load through the transformer T1 , and the detailed operation is that the currentiLm1 flowing through the first input inductor Lm1 linearly rises, anda first switch voltage across the second end QvCr1 = 0, and thus the first primary winding of transformer T1 LP1 approximates a first voltage across the voltage dividing capacitor C1vP1vC1> 0, and an induced voltagev S 1 = nv C 1> 0 so that the first diode D is turnedon. 1 T1 of the first transformer secondary winding LP2, a third diode D3 is non-conducting, and the voltagevL1 =vS1 -vo >0 of the magnetizing inductance Lm1 , the currentiL1 linearly rises, and the slope isvC1 /Lm .
第二開關Q2處於不導通狀態，因此其跨壓等同於輸入電壓vCr2=vin，第二變壓器T2經由旁路二極體DP作磁通重置，第二變壓器T2的初級側繞組LP1跨壓vP2-vP1<0，而使第二二極體D2不導通、第四二極體D4導通，第二輸出電感L2的電壓vL2=-Vo，且第二輸出電感L2的電流iL2線性下降，因此總輸出電流iLo=iL1+iL2會有漣波相消的效果。The second switch Q2 is in a non-conducting state, so its cross voltage is equivalent to the input voltagevCr2 =vin , the second transformer T2 is magnetically reset via the bypass diode DP , and the second transformer T2 Primary side winding LP1 across pressurevP2 -vP1 <0, leaving the second diode D2 non-conducting, the fourth diode D4 conducting, the voltage of the second output inductor L2vL2 =−Vo , and the second output inductance L the currenti2L2 decreases linearly, and therefore the total output currenti L o = i L 1 + i L 2 will ripple cancellation effect.
模式二(時間：t1~t2)：Mode 2 (time: t1 ~t2):
參閱圖2及圖3b，第一及第二開關Q1、Q2皆不導通。Referring to FIG. 2 and FIG. 3b, the first and second switches Q1 and Q2 are not turned on.
第一分壓電容C1提供一電流iQ1對第一開關Q1之寄生電容Cr1充電，使其電壓vCr1上升，由於旁路二極體DP導通，電壓vCr1和vCr2滿足vCr1+vCr2=vin，所以第二開關Q2之寄生電容Cr2放電，使其電壓vCr2下降。由於第一及第二開關Q1、Q2的寄生電容Cr1和Cr2非常小，vCr1上升和vCr2下降非常快，因此本階段歷時很短，第一輸入電感Lm1之電流iLm1可視為常數，同時i1=niL1，因此第一開關Q1之寄生電容電容Cr1受電流iQ1快速充電。A first dividing capacitorC. 1iQ1 provides a current to charge the first parasitic capacitance C of the switch Q1r1, vCr1 so that the voltage rises, since the bypass diode DP turned on, and the voltage vCr1 vCr2 satisfies vCr1 + vCr2 = vin , so the parasitic capacitance Cr2 of the second switch Q2 is discharged, causing the voltage vCr2 to decrease. Since the parasitic capacitances Cr1 and Cr2 of the first and second switches Q1 , Q2 are very small, vCr1 rises and vCr2 drops very fast, so this phase is very short, the first input inductor Lm1 The current iLm1 can be regarded as a constant At the same time, i1 =niL1 , so the parasitic capacitance Cr1 of the first switch Q1 is rapidly charged by the current iQ1 .
當vCr1上升至vC1，vCr2下降至vC2，第一變壓器T1之初級側繞組LP1的電壓vP1=0，第二變壓器T2之次級側繞組LP2的電壓vP2=0，因此vS1=0而且vS2=0，進入模式三。When vCr1 rises to vC1 , vCr2 falls to vC2 , the voltage of the primary side winding LP1 of the first transformer T1 is vP1 =0 , and the voltage of the secondary side winding LP2 of the second transformer T2 is vP2 =0 , so vS1 =0 and vS2 =0 , enter mode three.
模式三(時間：t2~t3)：Mode three (time: t2 ~ t3):
參閱圖2及圖3c，第一及第二開關Q1、Q2皆不導通。Referring to FIG. 2 and FIG. 3c, the first and second switches Q1 and Q2 are not turned on.
共振電感Lr，第一及第二漏電感Ll1和Ll2、第一及第二開關Q1、Q2之寄生電容Cr1和Cr2形成共振電路，第一開關Q1跨壓vCr1持續上升，第二開關Q2跨壓vCr2持續下降，共振電感Lr跨負電壓，其電流iLr下降，而使流經第一二極體D1的電流iD1遞減，流經第三二極體D3的電流iD3遞增，流經第二二極體D2的電流iD2遞增，流經第四二極體D4的電流iD4遞減。The resonant inductor Lr , the first and second leakage inductances Ll1 and Ll2 , the parasitic capacitancesCr1 and Cr2 of the first and second switches Q1 , Q2 form a resonant circuit, and the first switch Q1 crosses the voltagevCr1 continues to rise, the second switch Q2 continues to fall across the voltage vCr2 , the resonant inductor Lr across the negative voltage, the current iLr decreases, and the current iD1 flowing through the first diode D1 decreases, flowing through The currentiD3 of the third diode D3 is incremented, the current iD2 flowing through the second diode D2 is incremented, and the current iD4 flowing through the fourth diode D4 is decreased.
在模式三的共振電感Lr及漏電感Ll1、Ll2的初始儲能必須大於第二開關Q2之寄生電容Cr2的初始儲能，方能使第二開關Q2跨壓vCr2下降至零，達到ZVS的條件。In mode three resonant inductorLr and the leakage inductance LL1, Ll2 initial stored energy must be greater than the initial energy storage of the second switch Q2, a parasitic capacitance Cr2, the second switch Q2 can the cross voltage drop vCr2 To zero, reach the conditions of ZVS.
當第二開關Q2跨壓vCr2下降至0，第二開關Q2的本體二極體(body diode)DQ2導通，模式三結束。When the second switchQ2 falls to 0 across the voltage vCr2 , the body diode DQ2 of the second switch Q2 is turned on, and the mode 3 ends.
模式四(時間：t3~t4)：Mode four (time:t3 ~t4):
參閱圖2及圖3d，第一及第二開關Q1、Q2皆不導通。Referring to FIGS. 2 and 3d, the first and second switches Q1 and Q2 are not turned on.
模式四開始時，第二開關Q2跨壓vCr2箝位在零，而且vCr1=vin，且第二開關Q2之本體二極體DQ2導通，由於第二開關Q2之跨壓為零，在電流iQ2變成正值之前，必須將Q2切換為導通，達成ZVS操作，並進到模式五。When Mode 4 starts, the voltage across the second switch Q2 vCr2 clamped to zero and vCr1 = vin, and the second switch Q2 of the body diode DQ2 is turned on, the second switch Q2 of the voltage across the To zero, before current iQ2 becomes positive, Q2 must be switched to conduct, achieve ZVS operation, and proceed to mode five.
模式五(時間：t4~t5)：Mode five (time: t4 ~ t5):
參閱圖2及圖3e，第一開關Q1不導通，而第二開關Q2導通。Referring to FIG. 2 and FIG. 3E, a first switch Q1 is not turned on, the second switch Q2 is turned on.
模式五電路操作與模式四相同，故不重述。Mode 5 circuit operation is the same as mode 4, so it will not be repeated.
當第三二極體D3的電流iD3上升至iL1，第二二極體D2的電流iD2上升至iL2，換向完成，同時第一及第四二極體D1和D4轉變成截止，模式五結束。When the current iD3 of the third diode D3 rises to iL1 , the current iD2 of the second diode D2 rises to iL2 , the commutation is completed, and the first and fourth diodes D1 and D simultaneously4 turns into a cutoff, and mode five ends.
模式六(時間：t5~t6)：Mode six (time: t5 ~ t6):
參閱圖2及圖3f，第一開關Q1不導通，而第二開關Q2導通。Referring to FIG. 2 and FIG. 3f, the first switch Q1 is not turned on, the second switch Q2 is turned on.
第三二極體電流iD3=iL1，第二二極體電流iD2=iL2，第二輸入電感的電壓vP2vC2，其電流iLm2線性上升且斜率為vC2/Lm，第二變壓器T2的次級側繞組LP2的電壓vS2=nvP2>0，此時儲存在第二分壓電容C2之能量藉由第二變壓器T2傳遞至輸出負載。且第一變壓器T1經由旁路二極體DP作磁通重置(flux resetting)，且vP1=-vP2，因此電流iLm1線性下降。在輸出電感電流方面，因為vL2=vS2-vo>0，iL2線性上升；vL1=-vo，iL1線性下降，所以總輸出電流iLo=iL1+iL2會有漣波相消的效果。The third diode current iD3 =iL1 , the second diode current iD2 =iL2 , the voltage of the second input inductor vP2 vC2 , whose current iLm2 rises linearly and has a slope of vC2 /Lm , and the voltage of the secondary side winding LP2 of the second transformerT2 is vS2 =nvP2 >0 , and is stored in the second voltage dividing capacitor C at this time2 by the energy of the second transformer T2 is transmitted to the output load. And the first transformer T1 is flux resetted via the bypass diode DP , and vP1 =−vP2 , so the currentiLm1 linearly decreases. In terms of output inductor current, since vL2 =vS2 -vo >0,iL2 rises linearly; vL1 =-vo , iL1 decreases linearly, so the total output current iLo =iL1 +iL2 will The effect of chopping cancellation.
模式七(時間：t6~t7)：Mode seven (time:t6 ~t7):
參閱圖2及圖3g，第一及第二開關Q1、Q2皆不導通。Referring to FIG. 2 and FIG. 3g, the first and second switches Q1 and Q2 are not turned on.
電流iQ2為正值對第二開關Q2之寄生電容Cr2充電，使其電壓vCr2上升，由於旁路二極體DP導通，電壓vCr1和vCr2滿足vin=vCr1+vCr2，所以第一開關Q1之寄生電容Cr1放電，其電壓vCr1下降。由於第一及第二開關Q1、Q2的寄生電容Cr1和Cr2非常小，vCr2上升和vCr1下降非常快，因此模式七歷經的時間很短。The current iQ2 is positive and charges the parasitic capacitance Cr2 of the second switch Q2 to increase the voltage vCr2 . Since the bypass diode DP is turned on, the voltages vCr1 and vCr2 satisfy vin =vCr1 +vCr2 , so the parasitic capacitance Cr1 of the first switch Q1 is discharged, and the voltagevCr1 thereof is lowered. Since the parasitic capacitances Cr1 and Cr2 of the first and second switches Q1 , Q2 are very small, vCr2 rises and vCr1 drops very fast, so the time of mode seven is very short.
當第二開關Q2跨壓vCr2上升至vC2，此時vCr1下降至vC1，第二變壓器T2的初級側繞組LP1的電壓vP2=0，且第一變壓器T1的初級側繞組LP1的電壓vP1=0，使第一及第四二極體D1及D2開始導通，本階段結束。When the second switch Q2 rises to vC2 across the voltage vCr2 , at which time vCr1 drops to vC1 , the voltage vP2 of the primary side winding LP1 of the second transformer T2 =0, and the primary of the first transformer T1 The voltage vP1 =0 of the side winding LP1 causes the first and fourth diodes D1 and D2 to start to conduct, and this stage ends.
模式八(時間：t7~t8)：Mode eight (time:t7 ~t8):
參閱圖2及圖3h，第一及第二開關Q1、Q2皆不導通。Referring to FIG. 2 and FIG. 3h, the first and second switches Q1 and Q2 are not turned on.
第一及第二變壓器T1、T2的初級側繞組的電壓vP1和vP2箝位於零，iLm1和iLm2保持常數。共振電感Lr、漏電感Ll1和Ll2及第一及第二開關的寄生電容Cr1和Cr2形成共振電路，vCr2持續上升，vCr1持續下降。共振電感跨正電壓，其電流iLr上升。電流iD1遞增，iD3遞減，同時iD2遞減，iD4遞增。且共振電感及漏電感的初始儲能必須大於第一開關Q1的寄生電容Cr1的初始儲能，方能使第一開關跨壓vCr1下降至零，達到ZVS的條件。The voltages vP1 and vP2 of the primary side windings of the first and second transformers T1 , T2 are clamped at zero, and iLm1 and iLm2 remain constant. The resonant inductor Lr , the leakage inductances Ll1 and Ll2 , and the parasitic capacitances Cr1 and Cr2 of the first and second switches form a resonant circuit, vCr2 continues to rise, and vCr1 continues to decrease. The resonant inductor crosses a positive voltage and its current iLr rises. The current iD1 is incremented, iD3 is decremented, while iD2 is decremented and iD4 is incremented. And the initial energy storage of the resonant inductor and the leakage inductance must be greater than the initial energy storage of the parasitic capacitance Cr1 of the first switch Q1 , so that the first switch across the voltage vCr1 drops to zero, reaching the condition of ZVS.
當第一開關電壓vCr1下降至零，其本體二極體DQ1導通，進到模式九。When the first switching voltage vCr1 drops to zero, its body diode DQ1 is turned on, and proceeds to mode IX.
模式九(時間：t8~t9)：Mode nine (time:t8 ~t9):
參閱圖2及圖3i，第一及第二開關Q1、Q2皆不導通。Referring to FIG. 2 and FIG. 3i, the first and second switches Q1 and Q2 are not turned on.
電流流經第一開關Q1之本體二極體DQ1，第一開關Q1之跨壓為零，且第二開關Q2之跨壓vCr2=vin。因為vCr1=0，在第一開關電流iQ1變成正值之前，必須將第一開關Q1切換為導通，達成ZVS操作。又共振電感電壓vLr=vC1Lr/(Lr+0.5L1)，共振電感電流iLr線性上升。A current flowing through the first switch Q1 of the body diode DQ1, the first switch Q1 of voltage across zero, and the voltage across the second switch Q v2 ofCr2 = vin. Since vCr1 =0, before the first switching current iQ1 becomes a positive value, the first switch Q1 must be switched to be turned on to achieve a ZVS operation. Further, the resonant inductor voltage vLr = vC1 Lr / (Lr + 0.5L1 ), and the resonant inductor current iLr rises linearly.
當第一開關Q1切換為導通時，達成ZVS操作，模式九結束。When the first switch Q1 is turned on when switching to reach ZVS operation, the end of the nine modes.
模式十(時間：t9~t10)：Mode ten (time: t9 ~ t10):
參閱圖2及圖3i，第一開關Q1導通，且第二開關Q2不導通。Referring to FIG. 2 and FIG. 3i, a first switch Q1 turns on, and the second switch Q2 is not turned on.
模式十電路操作與模式九相同。Mode 10 circuit operation is the same as mode 9.
當第一二極體電流iD1上升至iL1，第四二極體電流iD4上升至iL2，換向完成，第二及第三二極體D2和D3轉變為截止，模式十結束。When the first diode current iD1 rises to iL1 , the fourth diode current iD4 rises to iL2 , the commutation is completed, and the second and third diodes D2 and D3 are turned off, mode ten End.
理論分析theoretical analysis
由上述可知Lm>>Lr，Lm>>L1，且第一開關Q1導通、第二開關Q2不導通時，vP1vC1；當第一開關Q1為不導通、第二開關Q2為導通時，vP1=-vC2。根據伏秒平衡定理，則It can be seen from the above that Lm >>Lr , Lm >>L1 , and the first switch Q1 is turned on and the second switch Q2 is turned off, vP1 vC1 ; when the first switchQ1 is non-conducting and the second switchQ2 is conducting,vP1 = -vC2 . According to the volt-second equilibrium theorem,
DvC1+(1-D)(-vC2)=0 (1)DvC1 +(1-D)(-vC2 )=0 (1)
其中第一開關Q1的導通比(duty ratio)為D，又因為Wherein the first switch Q1 has a duty ratioD , and because
vC1+vC2=vin (2)vC1 +vC2 =vin (2)
由式(1)(2)式可推出Can be introduced by formula (1) (2)
vC1=(1-D)vin，vC2=Dvin (3)vC1 =(1-D)vin ,vC2 =Dvin (3)
令n=N2/N1，電壓轉換比分析如下，當第一開關Q1為導通、第二開關Q2為不導通時，第一輸出電感L1電壓如式(4)所示：Let n=N2 /N1 , the voltage conversion ratio is analyzed as follows. When the first switch Q1 is turned on and the second switch Q2 is non-conductive, the voltage of the first output inductor L1 is as shown in the formula (4):
vL1=nvC1-vo=n(1-D)vin-vo (4)vL1 =nvC1 -vo =n(1-D)vin -vo (4)
當第一開關Q1為不導通、第二開關Q2為導通時，第一輸出電感L1電壓如式(5)所示：When the first switch Q1 is non-conducting and the second switch Q2 is conducting, the voltage of the first output inductor L1 is as shown in the formula (5):
vL1=-vo (5)vL1 =-vo (5)
穩態時，第一輸出電感L1滿足伏秒平衡定理。因此At steady state, the first output inductor L1 satisfies the volt-second equilibrium theorem. therefore
D[n(1-D)vin-vo]+(1-D)(-vo)=0 (6)D[n(1-D)vin -vo ]+(1-D)(-vo )=0 (6)
可得電壓轉換比Available voltage conversion ratio
由式(7)可知最大的電壓轉換比在開關導通比D=0.5時。It can be seen from equation (7) that the maximum voltage conversion ratio is when the switch conduction ratio D=0.5.
實驗模擬Experimental simulation
由圖4可知，在vin=400 V時，第一開關Q1之跨壓vQ1,ds都下降至零後，驅動信號vg1才切換為導通，達到ZVS性能，而第二開關Q2之跨壓vQ2,ds都下降至零後，驅動信號vg2才切換為導通，達到ZVS性能。從圖中可知其電壓應力皆為vin，模擬結果符合第一及第二開關Q1、Q2具有低電壓應力。After seen from FIG. 4, when vin = 400 V, the voltage across the first switch Q vQ1, ds of1 has fallen to zero, the drive signal vg1 was switched on to achieve ZVS performance, while the second switch Q2 After the voltage across the voltage vQ2, ds drops to zero, the drive signal vg2 is switched to conduct to achieve ZVS performance. It can be seen from the figure that the voltage stress isvin , and the simulation result is consistent with the low voltage stress of the first and second switches Q1 and Q2 .
如圖5為輸出電感電流iL1、iL2、iLo的波形量測圖，由模擬波形可知：在穩態操作下，iL1和iL2漣波反相，確實使漣波ΔiLo降低許多(ΔiL1ΔiL22.7A→ΔiLo0.4A)，可選用較小的輸出濾波電容元件，可使得轉換器體積減小，提高功率密度。另外，IL1=IL2=10A確實分擔總輸出電流(20 A)，可分散磁性元件的功率損失及熱應力，且具有高輸出電流且低輸出電流漣波的性能。Figure 5 shows the waveform measurement of the output inductor currents iL1 , iL2 , iLo . From the analog waveform, it can be seen that under steady-state operation, the inversion of iL1 and iL2 chopping does reduce the chopping ΔiLo much. (ΔiL1 ΔiL2 2.7A→ΔiLo 0.4A), a smaller output filter capacitor can be used to reduce the converter size and increase the power density. In addition, IL1 =IL2 =10A does share the total output current (20 A), disperses the power loss and thermal stress of the magnetic element, and has high output current and low output current chopping performance.
如圖6為該等二極體D1~D4的電流模擬圖，從圖中可知當第一開關Q1為導通時，第一二極體D1截止，第三二極體D3導通，等第一開關Q1為不導通時，第二開關Q2為導通時，二極體D1導通，二極體D3截止，此階段為和電流換向；當第二開關Q2為導通時，第二二極體D2導通，第四二極體D4截止，等第二開關Q2為不導通時，第一開關Q1為導通時，第二二極體D2截止，第四二極體D4導通，此階段為二極體電流iD2、iD4換向，=io/2=10A6 is a current simulation diagram of the diodes D1 -D4 . It can be seen from the figure that when the first switch Q1 is turned on, the first diode D1 is turned off, and the third diode D3 is turned on. When the first switch Q1 is non-conducting, when the second switch Q2 is turned on, the diode D1 is turned on, and the diode D3 is turned off. with When the second switch Q2 is turned on, the second diode D2 is turned on, the fourth diode D4 is turned off, and when the second switch Q2 is non-conductive, the first switch Q1 is turned on. When the second diode D2 is turned off, the fourth diode D4 is turned on, and the diode currents iD2 and iD4 are commutated at this stage. =io /2=10A
綜上所述，上述實施例具有以下優點：In summary, the above embodiment has the following advantages:
1.每一開關Q1、Q2有較低的電壓應力，其開關應力等同於輸入電壓vin，適用於高輸入電壓的應用。1. Each switch Q1 , Q2 has a lower voltage stress, and its switching stress is equivalent to the input voltage vin , which is suitable for high input voltage applications.
2.只包含二個開關Q1、Q2，能降低硬體成本。2. Only two switches Q1 and Q2 are included , which can reduce the hardware cost.
3.第一及第二開關Q1、Q2都能達到零電壓切換(ZVS)操作，減少切換損失，能提高功率轉換效率。3. The first and second switches Q1 and Q2 can achieve zero voltage switching (ZVS) operation, reduce switching losses, and improve power conversion efficiency.
4.因為並聯輸出結構具有電流分擔作用，可降低磁性元件之功率損失及熱應力的問題，所以適合高輸出電流應用。4. Because the parallel output structure has a current sharing function, which can reduce the power loss and thermal stress of the magnetic component, it is suitable for high output current applications.
5.具有輸出電流漣波相消作用，所以具有低輸出電流漣波。5. With output current chopping cancellation, it has low output current ripple.
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.
C1．．．第一分壓電容C1 . . . First voltage dividing capacitor
C2．．．第二分壓電容C2 . . . Second voltage dividing capacitor
Q1．．．第一開關Q1 . . . First switch
Q2．．．第二開關Q2 . . . Second switch
Dp．．．旁路二極體Dp . . . Bypass diode
Lr．．．共振電感Lr . . . Resonance inductor
T1．．．第一變壓器T1 . . . First transformer
T2．．．第二變壓器T2 . . . Second transformer
LP1．．．初級側繞組LP1 . . . Primary side winding
LP2．．．次級側繞組LP2 . . . Secondary side winding
D1~D4．．．第一至第四二極體D1 ~ D4 . . . First to fourth diodes
L1．．．第一輸出電感L1 . . . First output inductor
L2．．．第二輸出電感L2 . . . Second output inductor
CO．．．輸出電容CO . . . Output capacitor
vin．．．輸入電壓vin . . . Input voltage
vo．．．．輸出電壓vo . . . . The output voltage
Lm1~Lm2．．．磁化電感Lm1 ~ Lm2 . . . Magnetizing inductance
Ll1~Ll2．．．漏電感Ll1 ~ Ll2 . . . Leakage inductance
Cr1~Cr2．．．寄生電容Cr1 ~Cr2 . . . Parasitic capacitance
DQ1~DQ2．．．本體二極體DQ1 ~ DQ2 . . . Body diode
圖1是本發明零電壓切換電源轉換器之較佳實施例的一電路圖；1 is a circuit diagram of a preferred embodiment of a zero voltage switching power converter of the present invention;
圖2是該較佳實施例的一時序圖；Figure 2 is a timing diagram of the preferred embodiment;
圖3a是該較佳實施例於模式一的一電路圖；Figure 3a is a circuit diagram of the preferred embodiment in mode one;
圖3b是該較佳實施例於模式二的一電路圖；Figure 3b is a circuit diagram of the preferred embodiment in mode two;
圖3c是該較佳實施例於模式三的一電路圖；Figure 3c is a circuit diagram of the preferred embodiment in mode three;
圖3d是該較佳實施例於模式四的一電路圖；Figure 3d is a circuit diagram of the preferred embodiment in mode four;
圖3e是該較佳實施例於模式五的一電路圖；Figure 3e is a circuit diagram of the preferred embodiment in mode five;
圖3f是該較佳實施例於模式六的一電路圖；Figure 3f is a circuit diagram of the preferred embodiment in mode six;
圖3g是該較佳實施例於模式七的一電路圖；Figure 3g is a circuit diagram of the preferred embodiment in mode seven;
圖3h是該較佳實施例於模式八的一電路圖；Figure 3h is a circuit diagram of the preferred embodiment in mode eight;
圖3i是該較佳實施例於模式九的一電路圖；Figure 3i is a circuit diagram of the preferred embodiment in mode IX;
圖3j是該較佳實施例於模式十的一電路圖；Figure 3j is a circuit diagram of the preferred embodiment in mode ten;
圖4是該較佳實施例的第一種模擬圖；Figure 4 is a first simulation diagram of the preferred embodiment;
圖5是該較佳實施例的第二種模擬圖；及Figure 5 is a second simulation diagram of the preferred embodiment; and
圖6是該較佳實施例的第三種模擬圖。Figure 6 is a third simulation of the preferred embodiment.
C1．．．第一分壓電容C1 . . . First voltage dividing capacitor
C2．．．第二分壓電容C2 . . . Second voltage dividing capacitor
Q1．．．第一開關Q1 . . . First switch
Q2．．．第二開關Q2 . . . Second switch
DP．．．旁路二極體DP . . . Bypass diode
Lr．．．共振電感Lr . . . Resonance inductor
T1．．．第一變壓器T1 . . . First transformer
T2．．．第二變壓器T2 . . . Second transformer
LP1．．．初級側繞組LP1 . . . Primary side winding
LP2．．．次級側繞組LP2 . . . Secondary side winding
D1~D4．．．第一至第四二極體D1 ~ D4 . . . First to fourth diodes
L1．．．第一輸出電感L1 . . . First output inductor
L2．．．第二輸出電感L2 . . . Second output inductor
CO．．．輸出電容CO . . . Output capacitor
vin．．．輸入電壓vin . . . Input voltage
vo．．．輸出電壓vo . . . The output voltage
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101114365ATWI439034B (en) | 2012-04-23 | 2012-04-23 | Zero voltage switching power converter |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101114365ATWI439034B (en) | 2012-04-23 | 2012-04-23 | Zero voltage switching power converter |
| Publication Number | Publication Date |
|---|---|
| TW201345128A TW201345128A (en) | 2013-11-01 |
| TWI439034Btrue TWI439034B (en) | 2014-05-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101114365ATWI439034B (en) | 2012-04-23 | 2012-04-23 | Zero voltage switching power converter |
| Country | Link |
|---|---|
| TW (1) | TWI439034B (en) |
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| TWI572127B (en)* | 2016-08-26 | 2017-02-21 | 崑山科技大學 | Zero voltage switching forward high step-down converter input in series and output in parallel |
| TWI580167B (en)* | 2016-08-18 | 2017-04-21 | Single stage buck converter |
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| FR3084796B1 (en)* | 2018-07-31 | 2020-08-28 | Valeo Siemens Eautomotive Norway As | CONTINUOUS-CONTINUOUS VOLTAGE CONVERTER TO RESONANCE |
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI580167B (en)* | 2016-08-18 | 2017-04-21 | Single stage buck converter | |
| TWI572127B (en)* | 2016-08-26 | 2017-02-21 | 崑山科技大學 | Zero voltage switching forward high step-down converter input in series and output in parallel |
| Publication number | Publication date |
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| TW201345128A (en) | 2013-11-01 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |