本發明關於半導體裝置及其製造方法。The present invention relates to a semiconductor device and a method of fabricating the same.
習知將源極導線接合用金屬塊安裝於Cu(銅)基板而製造半導體封裝的方法，例如專利文獻1所示。A method of manufacturing a semiconductor package by mounting a metal block for source wire bonding on a Cu (copper) substrate is known, for example, as disclosed in Patent Document 1.
但是，專利文獻1所示半導體裝置之構造，接合導線為必要者，導致半導體裝置全體成為大型化之同時，製程亦變多，成本變高之問題亦存在。However, in the structure of the semiconductor device shown in Patent Document 1, the bonding wires are necessary, and the total size of the semiconductor device is increased, and the number of processes is also increased, and the cost is also increased.
習知半導體裝置，係具備於第1主面上配置有導線被引出的凸塊，於上述第1主面之相反側面介由第1導電物連接第1金屬電極，外側面以絕緣物覆蓋的半導體元件，由上述凸塊所引出之導線介由第2導電物連接第2金屬電極而成(參照例如專利文獻2)。A conventional semiconductor device includes a bump on which a lead wire is led to be disposed on a first main surface, and a first conductive material is connected to the first metal electrode on the opposite side surface of the first main surface, and an outer surface is covered with an insulator. In the semiconductor element, the lead wire drawn by the bump is connected to the second metal electrode via the second conductive material (see, for example, Patent Document 2).
但是，專利文獻2揭示之半導體裝置中，半導體元件未配置於半導體裝置之中央部，而是配置於第1金屬電極側。因而半導體裝置移動時半導體元件受到之衝擊變大之問題存在。另外，上述導電物係由導電性樹脂或高融點焊錫等構成，上述金屬電極係由Al、Cu、Au或包含彼等之合金等構成，因而半導體裝置全體變為大型化之同時，成本變高之問題存在。However, in the semiconductor device disclosed in Patent Document 2, the semiconductor element is not disposed in the central portion of the semiconductor device, but is disposed on the first metal electrode side. Therefore, there is a problem that the semiconductor element is subjected to an impact when the semiconductor device moves. Further, the conductive material is made of a conductive resin or a high-melting-point solder, and the metal electrode is made of Al, Cu, Au, or an alloy containing the same, and the semiconductor device is enlarged in size, and the cost is changed. The problem of high is there.
專利文獻1：特開平5-347324號公報Patent Document 1: Japanese Patent Publication No. 5-347324
專利文獻2：特開2000-252235號公報Patent Document 2: JP-A-2000-252235
本發明之一態樣提供之半導體裝置之製造方法，該半導體裝置係具有：半導體元件，其具有互呈對向之第1面及第2面；及設於上述第1面的電極；第1外部電極，和上述半導體元件之上述第1面呈對向，具有：相對於上述第1面呈大略平行的第1主面；相對於上述第1主面呈大略垂直的第1側面；及凸部，相對於上述第1主面朝垂直方向突出，被連接於設於上述半導體元件之上述第1面的電極；第2外部電極，和上述半導體元件之上述第2面呈對向，具有：相對於上述第2面呈大略平行的第2主面；相對於上述第2主面呈大略垂直的第2側面；及上述第2主面之相反側之面，和上述第2主面實質上同一大小的相反面；及絕緣體，用於覆蓋上述半導體元件、上述第1外部電極之上述凸部；上述第1側面、上述第2側面係被設為裝配(mount)面，上述半導體元件被配置於上述第1外部電極與上述第2外部電極之間；其特徵為具備：在半導體晶圓被形成之複數個上述半導體元件的，設於上述半導體晶圓之表面側的上述第1面之上述電極之各個之上，形成由導電體構成之上述凸部的工程；在上述表面的上述複數半導體元件彼此之間形成溝的工程；在上述凸部彼此之間的間隙與上述溝，填充絕緣體而形成密封部的工程；針對和上述半導體晶圓之上述表面呈對向的背面進行研磨直至上述密封部露出為止，將上述半導體晶圓分離成為上述各個半導體元件的工程；於上述凸部之各個之上，形成由導電體構成、成為上述第1外部電極之一部分之第1引線的工程；於上述複數個半導體元件之上述背面，直接形成成為上述第2外部電極之第2引線之導電材料層，而形成上述第2引線的工程；及在上述複數個半導體元件彼此之間切斷上述密封部，而將上述複數個半導體元件彼此予以分離的工程。A method of manufacturing a semiconductor device according to an aspect of the present invention, comprising: a semiconductor device having a first surface and a second surface facing each other; and an electrode provided on the first surface; The external electrode is opposed to the first surface of the semiconductor element, and has a first main surface that is substantially parallel to the first surface, a first side surface that is substantially perpendicular to the first main surface, and a convex surface. a portion that is protruded in a vertical direction with respect to the first main surface and is connected to an electrode provided on the first surface of the semiconductor element; and a second external electrode that faces the second surface of the semiconductor element and has: a second main surface that is substantially parallel with respect to the second surface; a second side surface that is substantially perpendicular to the second main surface; and a surface opposite to the second main surface, and the second main surface An opposite surface of the same size; and an insulator for covering the semiconductor element and the convex portion of the first external electrode; wherein the first side surface and the second side surface are mounted surfaces, and the semiconductor element is disposed The first external electric power mentioned above And the second external electrode; wherein the plurality of semiconductor elements formed on the semiconductor wafer are provided on each of the electrodes of the first surface on the surface side of the semiconductor wafer, a process of forming the convex portion composed of a conductor; a process of forming a groove between the plurality of semiconductor elements on the surface; and a process of forming a sealing portion by filling a gap between the convex portion and the groove; Polishing the back surface facing the surface of the semiconductor wafer until the sealing portion is exposed, separating the semiconductor wafer into the semiconductor elements, and forming an electrical conductor on each of the convex portions a step of forming a first lead which is a part of the first external electrode; forming a conductive material layer which is a second lead of the second external electrode on the back surface of the plurality of semiconductor elements, and forming the second lead And cutting the sealing portion between the plurality of semiconductor elements, and the plural The semiconductor element to be separated from one another project.
本發明之另一態樣提供之半導體裝置之製造方法，該半導體裝置係具有：半導體元件，其具有互呈對向之第1面及第2面；及設於上述第1面的電極；第1外部電極，和上述半導體元件之上述第1面呈對向，具有：相對於上述第1面呈大略平行的第1主面；相對於上述第1主面呈大略垂直的第1側面；及凸部，相對於上述第1主面朝垂直方向突出，被連接於上述電極；第2外部電極，和上述半導體元件之上述第2面呈對向，具有：相對於上述第2面呈大略平行的第2主面；相對於上述第2主面呈大略垂直的第2側面；及上述第2主面之相反側之面，和上述第2主面實質上同一大小的相反面；及絕緣體，用於覆蓋上述半導體元件、上述第1外部電極之上述凸部；上述第1側面、上述第2側面係被設為裝配面，上述半導體元件被配置於上述第1外部電極與上述第2外部電極之間；其特徵為具備：在半導體晶圓被形成之複數個上述半導體元件的，設於上述半導體晶圓之表面側的上述第1面之上述電極之各個之上，形成由導電體構成之上述凸部的工程；在上述半導體晶圓之上述表面以絕緣體覆蓋上述凸部而形成第1密封部的工程；在上述複數半導體元件彼此之間，形成自上述半導體晶圓之上述背面側到達上述第1密封部之中途的溝，而將上述複數半導體元件之各個予以分離的工程；在上述溝填充絕緣體而形成第2密封部的工程；研磨上述第1密封部使上述凸部露出的工程；於上述凸部之上，形成由導電體構成、成為上述第1外部電極之一部分之第1引線的工程；於上述複數個半導體元件之各個之上述背面，直接形成成為上述第2外部電極之第2引線之導電材料層，而形成上述第2引線的工程；及在上述複數個半導體元件彼此之間切斷上述第1及第2密封部，而將上述背面形成有第2引線的上述複數個半導體元件彼此予以分離的工程。According to still another aspect of the present invention, a semiconductor device includes: a semiconductor device having a first surface and a second surface facing each other; and an electrode provided on the first surface; The external electrode is opposed to the first surface of the semiconductor element, and has a first main surface that is substantially parallel to the first surface, and a first side surface that is substantially perpendicular to the first main surface; a convex portion that protrudes in a vertical direction with respect to the first main surface and is connected to the electrode; and a second external electrode that faces the second surface of the semiconductor element and has a substantially parallel relationship with respect to the second surface a second main surface; a second side surface that is substantially perpendicular to the second main surface; and a surface opposite to the second main surface and an opposite surface of substantially the same size as the second main surface; and an insulator The convex portion for covering the semiconductor element and the first external electrode; the first side surface and the second side surface are used as a mounting surface, and the semiconductor element is disposed on the first external electrode and the second external electrode Between In order to provide the plurality of semiconductor elements in which the semiconductor wafer is formed, the convex portion formed of the conductor is formed on each of the electrodes on the first surface of the surface side of the semiconductor wafer Forming a first sealing portion by covering the convex portion with an insulator on the surface of the semiconductor wafer; and forming the first sealing portion from the back surface side of the semiconductor wafer between the plurality of semiconductor elements a process of separating the plurality of semiconductor elements in the middle of the trench; a process of forming the second sealing portion by filling the trench in the trench; and polishing the first sealing portion to expose the protruding portion; And forming a first lead which is formed of a conductor and is a part of the first external electrode, and directly forms a conductive material which is a second lead of the second external electrode on each of the back surfaces of the plurality of semiconductor elements a step of forming the second lead; and cutting the first and second between the plurality of semiconductor elements In the sealing portion, the plurality of semiconductor elements in which the second lead is formed on the back surface are separated from each other.
本發明之另一態樣提供之半導體裝置之製造方法，該半導體裝置係具有：半導體元件，其具有互呈對向之第1面及第2面；及設於上述第1面的電極；第1外部電極，和上述半導體元件之上述第1面呈對向，具有：相對於上述第1面呈大略平行的第1主面；相對於上述第1主面呈大略垂直的第1側面；及凸部，相對於上述第1主面朝垂直方向突出，被連接於上述電極；第2外部電極，和上述半導體元件之上述第2面呈對向，具有：相對於上述第2面呈大略平行的第2主面；相對於上述第2主面呈大略垂直的第2側面；及上述第2主面之相反側之面，和上述第2主面實質上同一大小的相反面；及絕緣體，用於覆蓋上述半導體元件、上述第1外部電極之上述凸部；上述第1側面、上述第2側面係被設為裝配面，上述半導體元件被配置於上述第1外部電極與上述第2外部電極之間；其特徵為具備：在半導體晶圓表面形成之複數個上述半導體元件之，和上述半導體晶圓之上述表面相反側的背面之側，形成第2密封部的工程；在上述複數個半導體元件彼此之間，形成自上述半導體晶圓之上述表面到達上述第2密封部中途的溝，而將上述複數個半導體元件之各個予以分離的工程；於上述半導體晶圓之上述表面側，在上述溝填充絕緣體，以上述絕緣體覆蓋上述電極而形成第1密封部的工程；於上述第1密封部形成開口之工程，該開口係到達上述複數個半導體元件之各個之上述表面側之上述第1面之上述電極；於上述背面直接形成成為上述第2外部電極之第2引線之導電材料層，而形成上述第2引線的工程；於上述第1密封部之上述開口填充導電性材料，而形成和上述電極連接之上述凸部的工程；形成和上述凸部電連接，成為上述第1外部電極之一部分之第1引線的工程；於電極連接之上述凸部的工程；及切斷上述第1密封部，而將上述第1引線所連接的複數個半導體元件彼此予以分離的工程。According to still another aspect of the present invention, a semiconductor device includes: a semiconductor device having a first surface and a second surface facing each other; and an electrode provided on the first surface; The external electrode is opposed to the first surface of the semiconductor element, and has a first main surface that is substantially parallel to the first surface, and a first side surface that is substantially perpendicular to the first main surface; a convex portion that protrudes in a vertical direction with respect to the first main surface and is connected to the electrode; and a second external electrode that faces the second surface of the semiconductor element and has a substantially parallel relationship with respect to the second surface a second main surface; a second side surface that is substantially perpendicular to the second main surface; and a surface opposite to the second main surface and an opposite surface of substantially the same size as the second main surface; and an insulator The convex portion for covering the semiconductor element and the first external electrode; the first side surface and the second side surface are used as a mounting surface, and the semiconductor element is disposed on the first external electrode and the second external electrode Between The method of forming a second sealing portion on a side of a plurality of the semiconductor elements formed on a surface of the semiconductor wafer opposite to the surface of the semiconductor wafer, and forming a second sealing portion between the plurality of semiconductor elements Forming a groove from the surface of the semiconductor wafer to the middle of the second sealing portion to separate the plurality of semiconductor elements; and filling the trench with the insulator on the surface side of the semiconductor wafer The insulating member covers the electrode to form a first sealing portion, and the opening is formed in the first sealing portion, wherein the opening reaches the electrode on the first surface of the surface side of each of the plurality of semiconductor elements; The conductive material layer serving as the second lead of the second external electrode is directly formed on the back surface, and the second lead is formed. The opening of the first sealing portion is filled with a conductive material to form the electrode connected to the electrode. Engineering of the convex portion; forming and electrically connecting the convex portion to become a part of the first external electrode The first lead projects; Engineering the convex portion is connected to the electrode; and cutting the first sealing portion, and the plurality of semiconductor elements connected to the first lead of the works to be separated from each other.
本發明之另一態樣提供之半導體裝置之製造方法，該半導體裝置係具有：半導體元件，其具有互呈對向之第1面及第2面；及設於上述第1面的電極；第1外部電極，和上述半導體元件之上述第1面呈對向，具有：相對於上述第1面呈大略平行的第1主面；相對於上述第1主面呈大略垂直的第1側面；及凸部，相對於上述第1主面朝垂直方向突出，被連接於設於上述半導體元件之上述第1面的電極；第2外部電極，和上述半導體元件之上述第2面呈對向，具有：相對於上述第2面呈大略平行的第2主面；相對於上述第2主面呈大略垂直的第2側面；及上述第2主面之相反側之面，和上述第2主面實質上同一大小的相反面；及絕緣體，用於覆蓋上述半導體元件、上述第1外部電極之上述凸部；上述第1側面、上述第2側面係被設為裝配面，上述半導體元件被配置於上述第1外部電極與上述第2外部電極之間；其特徵為具備：在半導體晶圓被形成之複數個上述半導體元件之表面的上述複數個半導體元件彼此之間形成溝的工程；在上述溝填充絕緣體，以上述絕緣體覆蓋上述電極而形成密封部的工程，及於上述密封部形成開口的工程，該開口係到達上述複數個半導體元件之各個的上述表面側之上述第1面之上述電極者；於上述密封部之上述開口填充導電性材料，而形成連接於上述電極之上述凸部的工程；形成電連接於上述凸部，成為上述第1外部電極之一部分之第1引線的工程；研磨上述半導體晶圓之上述表面之對向的背面直至上述密封部露出為止，而將上述半導體晶圓分離為上述半導體元件之各個的工程；於上述半導體元件之上述背面，直接形成成為上述第2外部電極之第2引線之導電材料層，而形成上述第2引線的工程；及切斷上述密封部，而將連接有上述第1引線的複數個半導體元件彼此予以分離的工程。According to still another aspect of the present invention, a semiconductor device includes: a semiconductor device having a first surface and a second surface facing each other; and an electrode provided on the first surface; The external electrode is opposed to the first surface of the semiconductor element, and has a first main surface that is substantially parallel to the first surface, and a first side surface that is substantially perpendicular to the first main surface; The convex portion is protruded in a vertical direction with respect to the first main surface, and is connected to an electrode provided on the first surface of the semiconductor element; and the second external electrode is opposed to the second surface of the semiconductor element. a second main surface that is substantially parallel with respect to the second surface; a second side surface that is substantially perpendicular to the second main surface; and a surface opposite to the second main surface, and the second main surface An opposite surface of the same size; and an insulator for covering the semiconductor element and the convex portion of the first external electrode; wherein the first side surface and the second side surface are provided as mounting surfaces, and the semiconductor element is disposed on the surface First external electrode The second external electrode is characterized in that: a groove is formed between the plurality of semiconductor elements on a surface of the plurality of semiconductor elements on which the semiconductor wafer is formed; and the insulating body is filled in the trench a process of forming the sealing portion by covering the electrode, and a process of forming an opening in the sealing portion, the opening reaching the electrode of the first surface on the surface side of each of the plurality of semiconductor elements; and the sealing portion The opening is filled with a conductive material to form a structure connected to the convex portion of the electrode; a step of electrically connecting the convex portion to a first lead of the first external electrode; and polishing the semiconductor wafer The opposite surface of the surface is formed until the sealing portion is exposed, and the semiconductor wafer is separated into each of the semiconductor elements; and the second lead serving as the second external electrode is directly formed on the back surface of the semiconductor element. a layer of a conductive material to form the second lead; and to cut the dense Unit, and is connected to the first lead of the plurality of semiconductor elements to be separated from one another project.
本發明之另一態樣提供之半導體裝置，其特徵為具有：半導體元件，其具有互呈對向之第1面及第2面；及設於上述第1面的電極；第1外部電極，和上述半導體元件之上述第1面呈對向，具有：相對於上述第1面呈大略平行的第1主面；相對於上述第1主面呈大略垂直的第1側面；及凸部，相對於上述第1主面朝垂直方向突出，被連接於上述電極；第2外部電極，和上述半導體元件之上述第2面呈對向，具有：相對於上述第2面呈大略平行的第2主面；相對於上述第2主面呈大略垂直的第2側面；及上述第2主面之相反側之面，和上述第2主面實質上同一大小的相反面；及絕緣體，用於覆蓋上述半導體元件、上述第1外部電極之上述凸部；上述第1側面、上述第2側面係被設為裝配面，上述半導體元件被配置於上述第1外部電極與上述第2外部電極之間。According to still another aspect of the present invention, a semiconductor device includes: a semiconductor element having a first surface and a second surface facing each other; and an electrode provided on the first surface; and a first external electrode; And the first surface of the semiconductor element facing the first surface; the first main surface that is substantially parallel to the first surface; the first side surface that is substantially perpendicular to the first main surface; and the convex portion The first main surface protrudes in a vertical direction and is connected to the electrode; and the second external electrode faces the second surface of the semiconductor element and has a second main body that is substantially parallel to the second surface. a second side surface that is substantially perpendicular to the second main surface; a surface opposite to the second main surface and an opposite surface of substantially the same size as the second main surface; and an insulator for covering the surface The semiconductor element and the convex portion of the first external electrode; the first side surface and the second side surface are provided as a mounting surface, and the semiconductor element is disposed between the first external electrode and the second external electrode.
本發明之另一態樣提供之半導體裝置，其特徵為具有：半導體元件，其具有互呈對向之第1面及第2面；及設於上述第1面的電極；第1外部電極，和上述半導體元件之上述第1面呈對向，具有：相對於上述第1面呈大略平行的第1主面；相對於上述第1主面呈大略垂直的第1側面；及凸部，相對於上述第1主面朝垂直方向突出，被連接於上述電極；第2外部電極，和上述半導體元件之上述第2面呈對向，具有：相對於上述第2面呈大略平行的第2主面；及相對於上述第2主面呈大略垂直的第2側面；第3外部電極，和上述半導體元件之上述第1面呈對向，具有：相對於上述第1面呈大略平行的第3主面；相對於上述第3主面呈大略垂直的第3側面；及凸部，相對於上述第3主面朝垂直方向突出，接觸於上述第1面；及絕緣體，用於覆蓋上述半導體元件、上述第1外部電極之上述凸部、及上述第3外部電極之上述凸部；上述第1側面、上述第2側面及上述第3側面係被設為裝配面，上述半導體元件被配置於上述第1外部電極及上述第3外部電極與上述第2外部電極之間。According to still another aspect of the present invention, a semiconductor device includes: a semiconductor element having a first surface and a second surface facing each other; and an electrode provided on the first surface; and a first external electrode; And the first surface of the semiconductor element facing the first surface; the first main surface that is substantially parallel to the first surface; the first side surface that is substantially perpendicular to the first main surface; and the convex portion The first main surface protrudes in a vertical direction and is connected to the electrode; and the second external electrode faces the second surface of the semiconductor element and has a second main body that is substantially parallel to the second surface. And a second side surface that is substantially perpendicular to the second main surface; and the third external electrode faces the first surface of the semiconductor element and has a third parallel with respect to the first surface a main surface; a third side surface that is substantially perpendicular to the third main surface; and a convex portion that protrudes in a vertical direction with respect to the third main surface to contact the first surface; and an insulator for covering the semiconductor element The convex portion of the first external electrode And the convex portion of the third external electrode; the first side surface, the second side surface, and the third side surface are used as a mounting surface, and the semiconductor element is disposed on the first external electrode and the third external electrode Between the second external electrode and the second external electrode.
以下參照圖面說明本發明之各實施形態。Hereinafter, each embodiment of the present invention will be described with reference to the drawings.
又，圖面為模式或概念圖，各部分之厚度與寬度間之關係，部分間之大小之比例關係等未必限定為和現實同一者。另外，表示同一部分時因圖面關係而有以互相之不同尺寸或比例係數表示之情況。Further, the drawing is a mode or a conceptual diagram, and the relationship between the thickness and the width of each part, the proportional relationship between the sizes of the parts, and the like are not necessarily limited to the same as the reality. In addition, when the same portion is indicated, it may be represented by different sizes or proportional coefficients depending on the relationship of the drawings.
又，於說明書與各圖中，和上述說明之圖中同一要素原則上附加同一符號，並省略重複說明。In the drawings, the same components as those in the above-described drawings are denoted by the same reference numerals, and the description thereof will not be repeated.
圖1為本發明第1實施形態之半導體裝置之模式圖。Fig. 1 is a schematic view showing a semiconductor device according to a first embodiment of the present invention.
圖1(a)平面圖，圖1(b)為圖1(a)之A-A線斷面圖。Fig. 1(a) is a plan view, and Fig. 1(b) is a cross-sectional view taken along line A-A of Fig. 1(a).
如圖1(a)～(b)所示，本實施形態之半導體裝置，係具有半導體元件11；設於其兩側之第1外部電極82及第2外部電極83；用於密封半導體元件11的密封部70。As shown in FIGS. 1(a) to 1(b), the semiconductor device of the present embodiment includes a semiconductor element 11; a first external electrode 82 and a second external electrode 83 provided on both sides thereof; and a semiconductor element 11 for sealing Sealing portion 70.
半導體元件11，例如為二極體，其厚度T例如為100μm(微米)以上，400μm以下，一邊約為200μm之直方體。The semiconductor element 11 is, for example, a diode, and has a thickness T of, for example, 100 μm (micrometer) or more, 400 μm or less, and a square of about 200 μm.
第1外部電極82係包含連接於半導體元件11之表面之小的凸部82A，及朝外側延伸的大的第1引線82B。The first external electrode 82 includes a small convex portion 82A connected to the surface of the semiconductor element 11, and a large first lead 82B extending outward.
另外，第2外部電極83係包含第2引線83B。第2外部電極83(第2引線83B)，係連接於半導體元件11之背面，在相對於由第2外部電極83朝向半導體元件11之方向呈垂直之平面予以切斷時的第2外部電極83之斷面寬度，沿著由第2外部電極83朝向半導體元件11之方向實質上為一定。亦即，於第2外部電極83未設置凸部。Further, the second external electrode 83 includes the second lead 83B. The second external electrode 83 (second lead 83B) is connected to the back surface of the semiconductor element 11, and is cut by the second external electrode 83 when it is cut in a plane perpendicular to the direction in which the second external electrode 83 faces the semiconductor element 11. The cross-sectional width is substantially constant along the direction from the second outer electrode 83 toward the semiconductor element 11. That is, no convex portion is provided in the second outer electrode 83.
半導體元件11及凸部82A，係被埋入密封部70。The semiconductor element 11 and the convex portion 82A are buried in the sealing portion 70.
如上述說明，本實施形態之半導體裝置，係具有半導體元件11；第1外部電極82；第2外部電極83；及絕緣體(密封部70)。As described above, the semiconductor device of the present embodiment includes the semiconductor element 11, the first external electrode 82, the second external electrode 83, and the insulator (sealing portion 70).
半導體元件11，其具有互呈對向之第1面及第2面；及設於第1面的電極(未圖示)。半導體元件11，係設於半導體晶圓，例如第1面可為半導體晶圓之表面側之面，第2面可為半導體晶圓之表面之相反側的背面側之面。又，半導體元件11可另具有設於第2面的電極(未圖示)。以下說明中以第1面為表面，第2面為背面。The semiconductor element 11 has a first surface and a second surface that face each other, and an electrode (not shown) provided on the first surface. The semiconductor element 11 is provided on a semiconductor wafer. For example, the first surface may be a surface on the surface side of the semiconductor wafer, and the second surface may be a surface on the back side opposite to the surface of the semiconductor wafer. Further, the semiconductor element 11 may have an electrode (not shown) provided on the second surface. In the following description, the first surface is the surface, and the second surface is the back surface.
第1外部電極82，係和半導體元件11之第1面(表面)呈對向，具有：相對於第1面表面呈大略平行的第1主面；相對於第1主面呈大略垂直的第1側面；及凸部82A，相對於第1主面朝垂直方向突出，被連接於設於第1面的電極。The first outer electrode 82 is opposed to the first surface (surface) of the semiconductor element 11, and has a first main surface that is substantially parallel to the first surface and a vertical portion that is substantially perpendicular to the first main surface. The one side surface and the convex portion 82A project in the vertical direction with respect to the first main surface, and are connected to the electrode provided on the first surface.
第2外部電極，係和半導體元件11之第2面(背面)呈對向，具有：相對於第2面(背面)呈大略平行的第2主面；相對於第2主面呈大略垂直的第2側面；及第2主面之相反側之面，和第2主面實質上同一大小的相反面。於半導體元件11之第2面設置電極時，第2外部電極，係連接於半導體元件11之第2面上所設置之電極。The second external electrode is opposed to the second surface (back surface) of the semiconductor element 11, and has a second main surface that is substantially parallel to the second surface (back surface) and is substantially perpendicular to the second main surface. The second side surface and the surface opposite to the second main surface are substantially the same size as the second main surface. When an electrode is provided on the second surface of the semiconductor element 11, the second external electrode is connected to the electrode provided on the second surface of the semiconductor element 11.
密封部70，係用於覆蓋半導體元件11、第1外部電極82之凸部82A。The sealing portion 70 is for covering the semiconductor element 11 and the convex portion 82A of the first external electrode 82.
於該半導體裝置，第1側面、第2側面係被設為裝配(mount)面，半導體元件11被配置於第1外部電極與第2外部電極之間。In the semiconductor device, the first side surface and the second side surface are mounted surfaces, and the semiconductor element 11 is disposed between the first external electrode and the second external electrode.
依據此種構成之半導體裝置，可以提供全體構成為小型化之同時，可減低材料成本及製造成本的半導體裝置。According to the semiconductor device having such a configuration, it is possible to provide a semiconductor device which is reduced in material cost and manufacturing cost while being downsized as a whole.
另外，本具體例之半導體裝置，係於第1外部電極82設置凸部82A，於第2外部電極83未設置凸部。Further, in the semiconductor device of the specific example, the convex portion 82A is provided in the first outer electrode 82, and the convex portion is not provided in the second outer electrode 83.
如此則，和凸部設於第1外部電極82與第2外部電極83兩方之情況比較，可省略製程，可削減元件(凸部)，可達成低成本化。In this way, compared with the case where the convex portion is provided in both the first external electrode 82 and the second external electrode 83, the process can be omitted, and the element (convex portion) can be reduced, and the cost can be reduced.
密封部70，例如由樹脂構成。The sealing portion 70 is made of, for example, a resin.
另外，密封部70可具有複數個部分(例如第1密封部70A及第2密封部70B等)。該複數個部分(例如第1及第2密封部70A、70B)，可由同一材料構成，或由不同材料構成。密封部70之複數個部分係無縫隙地被接合。Further, the sealing portion 70 may have a plurality of portions (for example, the first sealing portion 70A and the second sealing portion 70B). The plurality of portions (for example, the first and second sealing portions 70A and 70B) may be made of the same material or of different materials. A plurality of portions of the sealing portion 70 are joined without gaps.
第1外部電極82及第2外部電極83，例如由銅形成，於本具體例之中，於第1引線82B與第2引線83B之表面，分別形成例如鎳或錫等之鍍層82C、83C。The first outer electrode 82 and the second outer electrode 83 are formed of, for example, copper. In the specific example, plating layers 82C and 83C such as nickel or tin are formed on the surfaces of the first lead 82B and the second lead 83B, respectively.
又，鍍層82C可視為第1外部電極82之一部分，另外，鍍層82C亦可視為和第1外部電極82獨立之不同部分。鍍層83C可視為第2外部電極83之一部分，另外，鍍層83C亦可視為和第2外部電極83獨立之不同部分。以下設定鍍層82C為和第1外部電極82獨立之不同部分，鍍層83C為和第2外部電極83獨立之不同部分。鍍層82C與鍍層83C之其中任一亦有可能被省略。Further, the plating layer 82C can be regarded as a part of the first external electrode 82, and the plating layer 82C can also be regarded as a different portion from the first external electrode 82. The plating layer 83C can be regarded as a part of the second external electrode 83, and the plating layer 83C can also be regarded as a different portion from the second external electrode 83. The plating layer 82C is set to be different from the first external electrode 82, and the plating layer 83C is a different portion from the second external electrode 83. Any of the plating layer 82C and the plating layer 83C may also be omitted.
該半導體裝置，係如後述之說明，可安裝於基板等。The semiconductor device can be mounted on a substrate or the like as will be described later.
半導體裝置之全長(沿著由第1外部電極82朝向第2外部電極83之方向的第1外部電極82之端部至第2外部電極83之端部為止之長度)，例如可設為約600μm。另外，密封部70之外徑(在和由第1外部電極82朝向第2外部電極83之方向垂直的平面切斷密封部70時之外徑)，例如可設為300μm弱(不足300μm)。另外，第1外部電極82及第2外部電極83之外徑(本具體例中，在和由第1外部電極82朝向第2外部電極83之方向垂直的平面切斷鍍層82C、83C時之外徑)，例如可設為300μm強(300μm多)。藉由設定第1外部電極82及第2外部電極83之外徑成為大於密封部70之外徑，則半導體裝置安裝於基板上時，可以簡單獲得和基板之外部電極間之接觸。The total length of the semiconductor device (the length from the end of the first external electrode 82 in the direction from the first external electrode 82 toward the second external electrode 83 to the end of the second external electrode 83) can be, for example, about 600 μm. . In addition, the outer diameter of the sealing portion 70 (the outer diameter when the sealing portion 70 is cut in a plane perpendicular to the direction from the first outer electrode 82 toward the second outer electrode 83) can be, for example, 300 μm weak (less than 300 μm). In addition, the outer diameter of the first outer electrode 82 and the second outer electrode 83 (in the specific example, when the plating layers 82C and 83C are cut off from the plane perpendicular to the direction from the first outer electrode 82 toward the second outer electrode 83) The diameter) can be, for example, 300 μm (300 μm or more). By setting the outer diameters of the first outer electrode 82 and the second outer electrode 83 to be larger than the outer diameter of the sealing portion 70, when the semiconductor device is mounted on the substrate, contact with the external electrodes of the substrate can be easily obtained.
又，可以設定密封部70之外徑成為大於第1外部電極82及第2外部電極83之外徑，如此則，半導體裝置安裝於基板時，可以容易藉由真空夾盤來拾取半導體裝置。Moreover, the outer diameter of the sealing portion 70 can be set larger than the outer diameters of the first outer electrode 82 and the second outer electrode 83. Thus, when the semiconductor device is mounted on the substrate, the semiconductor device can be easily picked up by the vacuum chuck.
又，密封部70之外徑大於第1外部電極82及第2外部電極83之外徑時，鍍層82C、83C雖較密封部70凹陷，但被裝配於基板之電極焊墊時，鍍層82C、83C與基板之電極焊墊間存在焊錫，半導體裝置可以確實被裝配。鍍層82C、83C與電極焊墊間存在之焊錫之厚度，例如可為約120μm。Further, when the outer diameter of the sealing portion 70 is larger than the outer diameters of the first outer electrode 82 and the second outer electrode 83, the plating layers 82C and 83C are recessed from the sealing portion 70, but when they are mounted on the electrode pads of the substrate, the plating layer 82C, Solder is present between the 83C and the electrode pads of the substrate, and the semiconductor device can be assembled. The thickness of the solder present between the plating layers 82C, 83C and the electrode pads may be, for example, about 120 μm.
又，如上述說明，密封部70之側面，可以較第1外部電極82之第1側面及第2外部電極83之第2側面凹陷。Further, as described above, the side surface of the sealing portion 70 may be recessed from the first side surface of the first outer electrode 82 and the second side surface of the second outer electrode 83.
另外，第1外部電極82之第1主面及第1側面之部分可設為鍍層(金屬鍍層)，第2外部電極83之第2主面及第2側面之部分可設為鍍層(金屬鍍層)。Further, a portion of the first main surface and the first side surface of the first external electrode 82 may be a plating layer (metal plating layer), and a portion of the second main surface and the second side surface of the second external electrode 83 may be a plating layer (metal plating) ).
第1外部電極82，可以至少具有形成於第1側面之鍍層，第2外部電極83，可以至少具有形成於第2側面之鍍層。The first outer electrode 82 may have at least a plating layer formed on the first side surface, and the second outer electrode 83 may have at least a plating layer formed on the second side surface.
第1外部電極82及第2外部電極83可設為鍍層金屬。The first outer electrode 82 and the second outer electrode 83 can be made of a plated metal.
本實施形態之半導體裝置極為輕巧，可實現高密度之裝配。另外，如後述之說明，可由1片半導體晶圓形成複數半導體裝置，可降低成本。The semiconductor device of the present embodiment is extremely lightweight and can be assembled at a high density. Further, as will be described later, a plurality of semiconductor devices can be formed from one semiconductor wafer, and the cost can be reduced.
以下說明具有上述構成之半導體裝置之製造方法。A method of manufacturing a semiconductor device having the above configuration will be described below.
以下說明之製造方法係關於半導體裝置之製造方法，該半導體裝置具備：半導體元件11，其具有互呈對向之第1面(表面)及第2面(背面)；及設於第1面的電極；第1外部電極82，係和半導體元件11之第1面呈對向，具有：相對於第1面呈大略平行的第1主面；相對於第1主面呈大略垂直的第1側面；及凸部82A，相對於第1主面朝垂直方向突出，被連接於設於半導體元件11之第1面的電極。第2外部電極83，係和半導體元件11之第2面呈對向，具有：相對於第2面呈大略平行的第2主面；相對於第2主面呈大略垂直的第2側面；及第2主面之相反側之面，和第2主面實質上同一大小的相反面；及絕緣體(密封部70)，係用於覆蓋半導體元件11、第1外部電極82之凸部82A；第1側面、第2側面係被設為裝配面，半導體元件11被配置於第1外部電極82與第2外部電極83之間者。The manufacturing method described below relates to a method of manufacturing a semiconductor device including: a semiconductor element 11 having a first surface (surface) and a second surface (back surface) facing each other; and a first surface The first outer electrode 82 is opposed to the first surface of the semiconductor element 11, and has a first main surface that is substantially parallel to the first surface, and a first side that is substantially perpendicular to the first main surface. And the convex portion 82A protrudes in the vertical direction with respect to the first main surface, and is connected to the electrode provided on the first surface of the semiconductor element 11. The second external electrode 83 is opposed to the second surface of the semiconductor element 11, and has a second main surface that is substantially parallel to the second surface, and a second side surface that is substantially perpendicular to the second main surface; a surface on the opposite side of the second main surface and an opposite surface of substantially the same size as the second main surface; and an insulator (sealing portion 70) for covering the semiconductor element 11 and the convex portion 82A of the first external electrode 82; The side surface and the second side surface are provided as a mounting surface, and the semiconductor element 11 is disposed between the first external electrode 82 and the second external electrode 83.
圖2表示第1實施形態之半導體裝置之製造方法之例示之流程圖。Fig. 2 is a flow chart showing an example of a method of manufacturing the semiconductor device of the first embodiment.
如圖2所示，該半導體裝置之製造方法，係具備：在半導體晶圓所形成之複數個半導體元件的，設於上述半導體晶圓之表面側的電極之上，形成由導電體構成之凸部82A的工程(步驟S110)；在上述表面的上述複數個半導體元件彼此之間形成溝的工程(步驟S120)；在上述凸部82A彼此之間的間隙與上述溝，填充絕緣體而形成密封部70的工程(步驟S130)；針對和上述半導體晶圓之上述表面呈對向的背面進行研磨直至上述密封部70露出為止，將上述半導體晶圓分離成為上述各個半導體元件11的工程(步驟S140)；於上述凸部82A之各個之上，形成由導電體構成、成為上述第1外部電極82之一部分之第1引線82B的工程(步驟S170)；於上述複數個半導體元件11之上述背面側，形成由導電體構成、成為上述第2外部電極83之第2引線83B的工程(步驟S180)；及在上述複數個半導體元件11彼此之間切斷上述密封部，而將上述複數個半導體元件11予以分離的工程(步驟S190)。As shown in FIG. 2, the semiconductor device manufacturing method includes a plurality of semiconductor elements formed on a semiconductor wafer, and is formed on an electrode on a surface side of the semiconductor wafer to form a bump formed of a conductor. The process of the portion 82A (step S110); forming a groove between the plurality of semiconductor elements on the surface (step S120); filling the gap between the convex portion 82A and the groove, filling the insulator to form a sealing portion The process of 70 (step S130); polishing the back surface facing the surface of the semiconductor wafer until the sealing portion 70 is exposed, and separating the semiconductor wafer into the semiconductor element 11 (step S140) On the respective convex portions 82A, a process of forming the first lead 82B which is a part of the first external electrode 82 and is formed of a conductor (step S170) is formed on the back side of the plurality of semiconductor elements 11 Forming a second lead 83B which is formed of a conductor and becomes the second external electrode 83 (step S180); and cutting between the plurality of semiconductor elements 11 The above-described sealing portion is broken, and the plurality of semiconductor elements 11 are separated (step S190).
又，上述各工程，在技術可能範圍內可以替換，亦可同時實施。Moreover, each of the above-mentioned projects may be replaced within the technical scope and may be implemented simultaneously.
具體言之可採用以下方法。Specifically, the following methods can be employed.
圖3(a)～(b)為第1實施形態之半導體裝置之製造方法之例示之工程圖。圖4(a)～(g)為第1實施形態之半導體裝置之製造方法之例示之工程圖，係接續圖3(b)之圖。3(a) to 3(b) are diagrams showing an example of a method of manufacturing the semiconductor device of the first embodiment. 4(a) to 4(g) are diagrams showing an example of a method of manufacturing a semiconductor device according to the first embodiment, which is a view subsequent to Fig. 3(b).
首先，如圖3(a)所示，準備形成有電極44(相當於設於第1面、亦即表面的電極)的半導體晶圓50。半導體晶圓50之厚度，例如為600μm。First, as shown in FIG. 3(a), a semiconductor wafer 50 on which an electrode 44 (corresponding to an electrode provided on the first surface, that is, the surface) is prepared. The thickness of the semiconductor wafer 50 is, for example, 600 μm.
之後，如圖3(b)所示，於電極44之上形成凸部82A。具體言之為，於電極44之上，作為鍍層之種層，藉由濺鍍法形成例如鈦(Ti)層與銅(Cu)層。之後，於半導體晶圓50之上壓合乾膜阻劑，介由遮罩進行曝光、顯像，於電極44之上之乾膜阻劑層形成開口。之後，進行銅等之鍍層而形成凸部82A。之後，剝離乾膜阻劑，以藥液等(例如蝕刻液)除去凸部82A以外之種層。凸部82A之厚度可設為例如約100μm。Thereafter, as shown in FIG. 3(b), a convex portion 82A is formed on the electrode 44. Specifically, on the electrode 44, as a seed layer of the plating layer, for example, a titanium (Ti) layer and a copper (Cu) layer are formed by sputtering. Thereafter, the dry film resist is pressed onto the semiconductor wafer 50, exposed and developed through the mask, and the dry film resist layer on the electrode 44 forms an opening. Thereafter, plating such as copper is performed to form the convex portion 82A. Thereafter, the dry film resist is peeled off, and a layer other than the convex portion 82A is removed by a chemical liquid or the like (for example, an etching liquid). The thickness of the convex portion 82A can be set to, for example, about 100 μm.
之後，如圖4(a)所示，於半導體晶圓50之表面側形成溝85。例如可藉由刃/切割鋸(blade/dicing saw)使寬約150μm之溝縱橫形成於半導體晶圓50之表面。Thereafter, as shown in FIG. 4(a), a groove 85 is formed on the surface side of the semiconductor wafer 50. For example, a groove having a width of about 150 μm can be formed on the surface of the semiconductor wafer 50 by a blade/dicing saw.
之後，如圖4(b)所示，以樹脂填埋溝85、凸部82A彼此之間隙而形成成為絕緣體之第1密封部70A(密封部70)。此時，於半導體晶圓50之表面塗布樹脂，研磨表面時凸部82A露出亦可。Then, as shown in FIG. 4(b), the first sealing portion 70A (sealing portion 70) serving as an insulator is formed by the gap between the resin filling groove 85 and the convex portion 82A. At this time, resin is applied to the surface of the semiconductor wafer 50, and the convex portion 82A may be exposed when the surface is polished.
之後，如圖4(c)所示，針對半導體晶圓50之背面進行研磨直至填埋於溝85的第1密封部70A(密封部70)露出為止，使變薄。如此而使形成於半導體晶圓50之半導體元件11分離。Thereafter, as shown in FIG. 4(c), the back surface of the semiconductor wafer 50 is polished until the first sealing portion 70A (sealing portion 70) buried in the groove 85 is exposed, and is thinned. Thus, the semiconductor element 11 formed on the semiconductor wafer 50 is separated.
之後，如圖4(d)所示，形成成為第1外部電極82之一部分的第1引線82B。亦即，以連接於凸部82A的方式形成第1引線82B。例如成為第1密封部70A(密封部70)的樹脂被塗布於半導體晶圓50之表面之後，研磨樹脂之背面使凸部82A露出時，以連接於由樹脂露出之凸部82A的方式形成第1引線82B。第1引線82B，例如可藉由銅之鍍層形成，其製程可以和形成凸部82A之製程同樣。第1引線82B之厚度，例如可設為約100μm。Thereafter, as shown in FIG. 4(d), the first lead 82B which is a part of the first external electrode 82 is formed. That is, the first lead 82B is formed to be connected to the convex portion 82A. For example, when the resin which is the first sealing portion 70A (sealing portion 70) is applied to the surface of the semiconductor wafer 50, and the back surface of the polishing resin is exposed to the convex portion 82A, the resin is formed so as to be connected to the convex portion 82A exposed by the resin. 1 lead 82B. The first lead 82B can be formed, for example, by a plating of copper, and the process can be the same as the process of forming the convex portion 82A. The thickness of the first lead 82B can be, for example, about 100 μm.
之後，如圖4(e)所示，於半導體元件11之背面(第2面)上形成成為第2外部電極83之第2引線83B。第2引線83B，例如可藉由濺鍍、銅鍍層，及濺鍍與銅鍍層之組合之一來形成，其製程可以和形成凸部82A之製程同樣。第2引線83B之厚度，例如可設為約100μm。Thereafter, as shown in FIG. 4(e), a second lead 83B serving as the second external electrode 83 is formed on the back surface (second surface) of the semiconductor element 11. The second lead 83B can be formed, for example, by sputtering, a copper plating, and a combination of sputtering and copper plating, and the process can be the same as the process of forming the convex portion 82A. The thickness of the second lead 83B can be, for example, about 100 μm.
之後，如圖4(f)所示將工件壓接於切割片87，藉由刃/切割鋸予以分離。Thereafter, the workpiece is crimped to the dicing sheet 87 as shown in Fig. 4 (f), and separated by a blade/cutting saw.
之後，如圖4(g)所示，由切割片87剝離，於第1引線82B及第2引線83B之表面，依序進行例如鎳層與錫層之鍍層，而形成鍍層82C、83C。亦即，鍍層82C、83C可包含鎳層、錫層、及鎳層與錫層之積層膜之至少之一。Thereafter, as shown in FIG. 4(g), the dicing sheet 87 is peeled off, and plating layers of, for example, a nickel layer and a tin layer are sequentially formed on the surfaces of the first lead 82B and the second lead 83B to form plating layers 82C and 83C. That is, the plating layers 82C, 83C may include at least one of a nickel layer, a tin layer, and a laminated film of a nickel layer and a tin layer.
又，此情況下，密封部70之外徑可以小於或大於鍍層82C、83C之外徑。Further, in this case, the outer diameter of the sealing portion 70 may be smaller or larger than the outer diameters of the plating layers 82C, 83C.
依據上述製造方法，可以提供全體小型化之同時，可以減低材料成本及製造成本的半導體裝置。According to the above manufacturing method, it is possible to provide a semiconductor device which can reduce the material cost and the manufacturing cost while reducing the overall size.
於本實施形態之半導體裝置及其製造方法，係於第1外部電極82設置凸部82A，但省略對第2外部電極83之凸部之提供。因此，和在第1外部電極82(表面)與第2外部電極83(背面)雙方設置凸部之情況比較，可省略製程，可削減元件(凸部)，相較於在表面與背面雙方設置凸部之情況更能實現低成本化。In the semiconductor device and the method of manufacturing the same according to the present embodiment, the convex portion 82A is provided on the first external electrode 82, but the provision of the convex portion of the second external electrode 83 is omitted. Therefore, compared with the case where the convex portion is provided on both the first outer electrode 82 (surface) and the second outer electrode 83 (back surface), the process can be omitted, and the element (convex portion) can be reduced, and the surface (front surface) and the back surface can be provided. In the case of the convex portion, the cost can be further reduced.
例如，在第1外部電極82與第2外部電極83雙方設置凸部時，例如係於如圖2所示步驟S140與步驟S170之間，實施在半導體晶圓背面形成和半導體元件11連接之由導電體構成之第2凸部之工程(例如步驟S150)，及以絕緣體填充第2凸部彼此間之間隙而形成第2密封部之工程(例如步驟S160)。和其比較，本實施形態之製造方法可省略上述步驟S150及步驟S160，相較於在表面與背面雙方設置凸部之情況更能實現低成本化。For example, when a convex portion is provided on both the first outer electrode 82 and the second outer electrode 83, for example, between step S140 and step S170 as shown in FIG. 2, the semiconductor element 11 is formed on the back surface of the semiconductor wafer. The process of forming the second convex portion of the conductor (for example, step S150) and the step of filling the gap between the second convex portions with the insulator to form the second sealing portion (for example, step S160). In contrast, in the manufacturing method of the present embodiment, the above-described steps S150 and S160 can be omitted, and the cost can be reduced as compared with the case where the convex portions are provided on both the front surface and the back surface.
圖5為第1實施形態之另一半導體裝置之模式圖。Fig. 5 is a schematic view showing another semiconductor device of the first embodiment.
亦即，該圖為和圖1(b)相當之模式斷面圖。That is, the figure is a schematic sectional view corresponding to Fig. 1(b).
如圖5所示，本具體例之半導體裝置中，凸部(凸部82A)被設於一方之外部電極(第1外部電極82)。本具體例中，絕緣體(密封部70)之側面、第1外部電極82之側面、第2外部電極83之側面實質上位於同一平面上。As shown in FIG. 5, in the semiconductor device of the specific example, the convex portion (the convex portion 82A) is provided on one of the external electrodes (the first external electrode 82). In this specific example, the side surface of the insulator (sealing portion 70), the side surface of the first outer electrode 82, and the side surface of the second outer electrode 83 are substantially on the same plane.
此種構成之半導體裝置可藉由以下方法製造。The semiconductor device of such a configuration can be manufactured by the following method.
圖6(a)～(c)為第1實施形態之半導體裝置之變形例之製造方法之例示之工程圖。6(a) to 6(c) are diagrams showing an example of a manufacturing method of a modification of the semiconductor device of the first embodiment.
本製造方法中，係於半導體晶圓50之電極44之上形成成為第1外部電極82之一部分的凸部82A，於半導體晶圓50之表面側形成溝85，以樹脂填埋溝85及凸部82A彼此間之間隙，而形成第1密封部70A。該工程係和圖3(a)、3(b)以及圖4(a)～(c)所示者相同，因此省略圖示。又，如圖4(c)所示，使凸部82A與半導體元件11之背面之電極(未圖示)由第1密封部70A露出。In the manufacturing method, the convex portion 82A which is a part of the first external electrode 82 is formed on the electrode 44 of the semiconductor wafer 50, the groove 85 is formed on the surface side of the semiconductor wafer 50, and the groove 85 and the convex are filled with the resin. The portion 82A is in a gap with each other to form the first sealing portion 70A. This engineering system is the same as those shown in FIGS. 3(a) and 3(b) and FIGS. 4(a) to 4(c), and thus the illustration thereof is omitted. Further, as shown in FIG. 4(c), the convex portion 82A and the electrode (not shown) on the back surface of the semiconductor element 11 are exposed by the first sealing portion 70A.
之後，如圖6(a)所示，於凸部82A之露出面與第1密封部70A之表面，壓合成為第1外部電極82之一部分的導電片86(導電性薄膜)。之後，於半導體元件11之背面之電極(未圖示)與第1密封部70A之背面，壓合成為第2外部電極83的導電片88。Then, as shown in FIG. 6(a), the conductive sheet 86 (conductive thin film) which is a part of the first external electrode 82 is press-compressed on the exposed surface of the convex portion 82A and the surface of the first sealing portion 70A. Thereafter, an electrode (not shown) on the back surface of the semiconductor element 11 and the back surface of the first sealing portion 70A are press-compressed into the conductive sheet 88 of the second external electrode 83.
該導電片86、88可適用任意之材料與厚度，例如可使用厚度為100μm之Cu等薄膜。另外，將導電片86、88壓合於凸部82A、第1密封部70A及半導體元件11之背面電極時，可使用導電性接著層。The conductive sheets 86 and 88 can be applied to any material and thickness, and for example, a film of Cu or the like having a thickness of 100 μm can be used. Further, when the conductive sheets 86 and 88 are pressed against the convex portion 82A, the first sealing portion 70A, and the back surface electrode of the semiconductor element 11, a conductive adhesive layer can be used.
之後，如圖6(b)所示，將工件(壓合有導電片86、88的半導體元件11)壓合於切割片(dicing sheet)87，藉由刃/切割鋸予以分離。此時，將第1密封部70A連同導電片86與導電片88一起切斷。切割溝之寬度可設為例如約60μm。如此則，導電片86與導電片88被分別切斷，分別成為第1引線82B及第2引線83B。如上述說明，於密封部70(及導電片86與導電片88)之切斷前，被壓合有成為第1引線之上述導電片及成為上述第2引線的導電片之複數個半導體元件11，係被壓合於壓合基材(切割片87)。如此則，複數個半導體元件11彼此之位置藉由切割片87被固定，複數個半導體元件11被分離後半導體元件11亦不會變為紊亂。Thereafter, as shown in FIG. 6(b), the workpiece (the semiconductor element 11 to which the conductive sheets 86 and 88 are bonded) is pressed against a dicing sheet 87, and separated by a blade/cutting saw. At this time, the first sealing portion 70A is cut together with the conductive sheet 86 together with the conductive sheet 88. The width of the dicing groove can be set, for example, to about 60 μm. In this manner, the conductive sheet 86 and the conductive sheet 88 are cut, and become the first lead 82B and the second lead 83B, respectively. As described above, before the cutting of the sealing portion 70 (and the conductive sheet 86 and the conductive sheet 88), the plurality of semiconductor elements 11 which are the conductive sheets of the first lead and the conductive sheets which are the second leads are pressed together. The film is pressed against a press-bonded substrate (cut sheet 87). In this manner, the positions of the plurality of semiconductor elements 11 are fixed by the dicing sheet 87, and the plurality of semiconductor elements 11 are separated, and the semiconductor element 11 does not become disordered.
之後，如圖6(c)所示，於由切割片87剝離之第1引線82B與第2引線83B之表面，例如依序進行鎳層與錫層之鍍層而形成鍍層82C、83C。Thereafter, as shown in FIG. 6(c), plating layers of the nickel layer and the tin layer are sequentially formed on the surfaces of the first lead 82B and the second lead 83B which are separated by the dicing sheet 87, for example, to form plating layers 82C and 83C.
如此而製造如圖5所示半導體裝置。於該製造方法中，第1引線82B與第2引線83B，並非藉由鍍層法，而是藉由導電片之壓合來進行，工程變為簡單，更能實現低成本化。Thus, a semiconductor device as shown in FIG. 5 was fabricated. In the manufacturing method, the first lead 82B and the second lead 83B are not pressed by the plating method, but are pressed by the conductive sheet, and the process is simplified, and the cost can be further reduced.
於該製造方法中，於如圖2所示流程圖，形成第1引線之工程(步驟S170)，係在凸部82A壓合導電片86之工程。又，此時，導電片86亦被壓合於第1密封部70A之表面。In the manufacturing method, the first lead wire is formed in the flow chart shown in FIG. 2 (step S170), and the conductive portion 86 is pressed against the convex portion 82A. Moreover, at this time, the conductive sheet 86 is also pressed against the surface of the first sealing portion 70A.
形成第2引線83B之工程(步驟S180)，係在半導體元件11之背面(例如半導體元件11之背面電極與第1密封部70A之背面)壓合導電片88(成為第2引線83B之導電材料層)之工程。The process of forming the second lead 83B (step S180) is to press the conductive sheet 88 on the back surface of the semiconductor element 11 (for example, the back surface of the semiconductor element 11 and the back surface of the first sealing portion 70A) (the conductive material of the second lead 83B) Layer) engineering.
如上述說明，於本實施形態之製造方法中可設為以下之至少之一：形成第1引線82B之工程，係包含在半導體元件11之第1面之側壓合成為第1引線82B之導電片的工程；與形成第2引線83B之工程，係包含在半導體元件11之第2面之側壓合成為第2引線83B之導電片的工程。As described above, in the manufacturing method of the present embodiment, at least one of the following steps can be employed: the process of forming the first lead 82B includes the conductive formation of the first lead 82B on the side of the first surface of the semiconductor element 11. The process of forming the second lead 83B includes a process of press-forming the conductive sheet of the second lead 83B on the side of the second surface of the semiconductor element 11.
本實施形態之製造方法，亦適用在第1外部電極82設置凸部82A，省略對第2外部電極83之凸部之提供的構成，為省略製程之高生產性之製造方法。In the manufacturing method of the present embodiment, the convex portion 82A is provided in the first outer electrode 82, and the configuration for providing the convex portion of the second outer electrode 83 is omitted, and the manufacturing method in which the high productivity of the process is omitted is omitted.
圖7為第2實施形態之半導體裝置之製造方法之例示之流程圖。Fig. 7 is a flow chart showing an example of a method of manufacturing a semiconductor device according to a second embodiment.
如圖7所示，本實施形態之製造方法，係具備：在半導體晶圓上形成之複數個半導體元件的，設於上述半導體晶圓之表面側的電極之各個之上，形成由導電體構成之凸部的工程(步驟S210)；在上述半導體晶圓之上述表面側以絕緣體覆蓋上述凸部而形成第1密封部的工程(步驟S220)；在上述複數個半導體元件彼此之間，形成自上述半導體晶圓之上述背面側到達上述第1密封部之中途的溝，而將上述複數個半導體元件之各個予以分離的工程(步驟S241)；在上述溝填充絕緣體而形成第2密封部的工程(步驟S251)；研磨上述第1密封部使上述凸部露出的工程(步驟S260)；於上述凸部之上形成由導電體構成、成為上述第1外部電極之一部分之第1引線的工程(步驟S280)；於上述複數個半導體元件彼此之上述背面，直接形成成為上述第2外部電極之第2引線之導電材料層，而形成上述第2引線的工程(步驟S290)；及在上述複數個半導體元件彼此之間切斷上述第1及第2密封部，而將藉由上述第2引線之形成而被形成的複數個半導體元件彼此予以分離的工程(步驟S295)。As shown in FIG. 7, the manufacturing method of the present embodiment includes a plurality of semiconductor elements formed on a semiconductor wafer, and is formed on each of the electrodes on the surface side of the semiconductor wafer to form a conductor. The process of the convex portion (step S210); forming a first sealing portion by covering the convex portion with an insulator on the surface side of the semiconductor wafer (step S220); forming a self between the plurality of semiconductor elements a process in which the back surface side of the semiconductor wafer reaches a groove in the middle of the first sealing portion, and each of the plurality of semiconductor elements is separated (step S241); and the second sealing portion is formed by filling the trench with an insulator (Step S251): polishing the first sealing portion to expose the convex portion (step S260); forming a first lead wire formed of a conductor and forming a portion of the first external electrode on the convex portion ( Step S280): forming a second conductive material layer serving as the second external electrode on the back surface of the plurality of semiconductor elements to form the second layer The process of the lead wire (step S290); and cutting the first and second sealing portions between the plurality of semiconductor elements, and separating the plurality of semiconductor elements formed by the formation of the second lead Engineering (step S295).
又，上述各工程，在技術可能範圍內可以替換，亦可同時實施。Moreover, each of the above-mentioned projects may be replaced within the technical scope and may be implemented simultaneously.
具體言之可採用以下方法。Specifically, the following methods can be employed.
圖8(a)～(h)為第2實施形態之半導體裝置之製造方法之例示之工程圖。8(a) to 8(h) are diagrams showing an example of a method of manufacturing a semiconductor device according to a second embodiment.
首先，如圖8(a)所示，準備形成有半導體元件11、以及電極44(設於半導體元件11之第1面、亦即表面的電極，為包含於半導體元件11者)及電極43(設於半導體元件11之第2面、亦即背面的電極，為包含於半導體元件11者)的半導體晶圓50。半導體晶圓50之厚度，例如為300μm。First, as shown in FIG. 8(a), a semiconductor element 11 and an electrode 44 (an electrode provided on the first surface of the semiconductor element 11, that is, an electrode included in the semiconductor element 11) and an electrode 43 are prepared ( The electrode provided on the second surface of the semiconductor element 11, that is, the back surface, is the semiconductor wafer 50 included in the semiconductor element 11. The thickness of the semiconductor wafer 50 is, for example, 300 μm.
之後，如圖8(b)所示，於電極44之上形成凸部82A。其方法可以和圖3(b)之上述說明者同樣。Thereafter, as shown in FIG. 8(b), a convex portion 82A is formed on the electrode 44. The method can be the same as that described above with reference to Fig. 3(b).
之後，如圖8(c)所示，以樹脂填埋凸部82A而形成第1密封部70A。亦即，於半導體晶圓50之表面側以樹脂(絕緣體)覆蓋凸部82A而形成第1密封部70A。此時，以埋沒凸部82A的方式形成較厚之樹脂。Thereafter, as shown in FIG. 8( c ), the first sealing portion 70A is formed by filling the convex portion 82A with a resin. In other words, the first sealing portion 70A is formed by covering the convex portion 82A with a resin (insulator) on the surface side of the semiconductor wafer 50. At this time, a thick resin is formed so as to bury the convex portion 82A.
之後，如圖8(d)所示，藉由刃/切割鋸由半導體晶圓50之背面側予以切斷，切斷半導體晶圓50，而形成到達第1密封部70A之中途的溝85。分離溝可以縱橫形成於半導體晶圓50之背面。Thereafter, as shown in FIG. 8(d), the blade/cutting saw is cut from the back side of the semiconductor wafer 50, and the semiconductor wafer 50 is cut to form a groove 85 that reaches the middle of the first sealing portion 70A. The separation trench may be formed vertically and horizontally on the back surface of the semiconductor wafer 50.
之後，如圖8(e)所示，以樹脂填埋半導體元件11而形成第2密封部70B。亦即，於溝85填埋樹脂(絕緣體)而形成第2密封部70B。本具體例中，電極43雖被埋設，但亦可使電極43之表面由第2密封部70B露出而形成第2密封部70B。Thereafter, as shown in FIG. 8(e), the semiconductor element 11 is filled with a resin to form the second sealing portion 70B. That is, the resin (insulator) is filled in the groove 85 to form the second sealing portion 70B. In the specific example, the electrode 43 is buried, but the surface of the electrode 43 may be exposed by the second sealing portion 70B to form the second sealing portion 70B.
之後，如圖8(f)所示，研磨第1密封部70A之表面使凸部82A露出。又，必要時可研磨第2密封部70B之表面使電極43露出。Thereafter, as shown in FIG. 8(f), the surface of the first sealing portion 70A is polished to expose the convex portion 82A. Further, if necessary, the surface of the second sealing portion 70B can be polished to expose the electrode 43.
之後，如圖8(g)所示，於凸部82A之上形成第1引線82B，於電極43之上形成第2引線83B。第1引線82B及第2引線83B，例如可藉由銅之鍍層形成，其製程可以和圖3(b)說明之形成凸部82A之製程同樣。Thereafter, as shown in FIG. 8(g), the first lead 82B is formed on the convex portion 82A, and the second lead 83B is formed on the electrode 43. The first lead 82B and the second lead 83B can be formed, for example, by a plating of copper, and the process can be the same as the process of forming the convex portion 82A described in FIG. 3(b).
之後，如圖8(h)所示，於第1引線82B及第2引線83B之表面，依序進行例如鎳層與錫層之鍍層，而形成鍍層82C、83C。鍍層82C、83C之至少之一，可包含鎳層、錫層、及鎳層與錫層之積層膜之至少之一。鍍層82C、83C之厚度，例如可設為5μm以上10μm以下之程度。之後，藉由刃/切割鋸予以分離，而完成半導體裝置。Thereafter, as shown in FIG. 8(h), for example, a plating layer of a nickel layer and a tin layer is sequentially formed on the surfaces of the first lead 82B and the second lead 83B to form plating layers 82C and 83C. At least one of the plating layers 82C and 83C may include at least one of a nickel layer, a tin layer, and a laminated film of a nickel layer and a tin layer. The thickness of the plating layers 82C and 83C can be, for example, about 5 μm or more and 10 μm or less. Thereafter, the semiconductor device is completed by separating by a blade/cutting saw.
於本實施形態之半導體裝置及其製造方法，係於第1外部電極82設置凸部82A，但省略對第2外部電極83之凸部之設置，因此，和在第1外部電極82與第2外部電極83雙方設置凸部之情況比較，可省略製程，可削減元件(凸部)，相較於在表面與背面雙方設置凸部之情況更能實現低成本化。In the semiconductor device and the method of manufacturing the same according to the present embodiment, the convex portion 82A is provided in the first external electrode 82, but the convex portion of the second external electrode 83 is omitted. Therefore, the first external electrode 82 and the second external electrode 82 are provided. In the case where the convex portions are provided on both the external electrodes 83, the process can be omitted, and the elements (protrusions) can be reduced, and the cost can be reduced as compared with the case where the convex portions are provided on both the front surface and the back surface.
例如，在第1外部電極82與第2外部電極83雙方設置凸部時，例如係於如圖7所示步驟S220與步驟S241之間，實施在半導體晶圓背面形成和上述半導體元件連接之由導電體構成之第2凸部之工程(例如步驟S230)，或者於步驟S251與步驟S280之間(例如步驟S260與步驟S280之間)，實施研磨上述第2密封部而使上述第2凸部露出之工程(例如步驟S270)。和其比較，本實施形態之製造方法可省略上述步驟S230及步驟S270，相較於在表面與背面雙方設置凸部之情況更能實現低成本化。For example, when a convex portion is provided on both the first outer electrode 82 and the second outer electrode 83, for example, between step S220 and step S241 shown in FIG. 7, a method of forming a semiconductor element on the back surface of the semiconductor wafer is performed. Polishing the second convex portion of the conductor (for example, step S230), or between step S251 and step S280 (for example, between step S260 and step S280), polishing the second sealing portion to cause the second convex portion The exposed project (for example, step S270). In contrast, in the manufacturing method of the present embodiment, the above-described steps S230 and S270 can be omitted, and the cost can be reduced as compared with the case where the convex portions are provided on both the front surface and the back surface.
如上述說明，依據本實施形態，可省略工程，可以更簡單之工程製造半導體裝置。As described above, according to the present embodiment, the engineering can be omitted, and the semiconductor device can be manufactured more easily.
本實施形態之製造方法，亦適用在第1外部電極82設置凸部82A，省略對第2外部電極83之凸部之提供的構成，為省略製程之高生產性之製造方法。In the manufacturing method of the present embodiment, the convex portion 82A is provided in the first outer electrode 82, and the configuration for providing the convex portion of the second outer electrode 83 is omitted, and the manufacturing method in which the high productivity of the process is omitted is omitted.
圖9為第3實施形態之半導體裝置之製造方法之例示之流程圖。Fig. 9 is a flow chart showing an example of a method of manufacturing a semiconductor device according to a third embodiment.
如圖9所示，本實施形態之製造方法，係具備：在半導體晶圓之表面上形成之複數個半導體元件之背面(上述半導體晶圓之上述表面之相反側之面)側，形成第2密封部的工程(步驟S310)；在上述複數個半導體元件彼此之間，形成自上述半導體晶圓之上述表面到達上述第2密封部之中途的溝，而將上述複數個半導體元件之各個予以分離的工程(步驟S320)；於上述半導體晶圓之上述表面側，在上述溝填充絕緣體，以上述絕緣體覆蓋上述電極而形成第1密封部的工程(步驟S330)；於上述第1密封部形成開口之工程(步驟S350)，該開口係到達上述複數個半導體元件之各個之上述表面側所設置之上述電極；於上述背面直接形成成為上述第2外部電極之第2引線之導電材料層，而形成上述第2引線的工程(步驟S362)；於上述第1密封部之上述開口填充導電性材料，而形成和上述電極連接之上述凸部82A的工程(步驟S371)；形成和上述凸部電連接，成為上述第1外部電極之一部分之第1引線的工程(步驟S372)；及切斷上述第1密封部與上述第2密封部之其中至少之一，而將基於上述第1引線之形成而被形成的複數個半導體裝置彼此予以分離的工程(步驟S380)。As shown in FIG. 9, the manufacturing method of the present embodiment includes a second surface of a plurality of semiconductor elements formed on the surface of the semiconductor wafer (the surface opposite to the surface of the semiconductor wafer). a process of sealing a portion (step S310); forming a groove from the surface of the semiconductor wafer to the middle of the second sealing portion between the plurality of semiconductor elements, and separating each of the plurality of semiconductor elements (Step S320), on the surface side of the semiconductor wafer, filling the trench in the trench, forming the first sealing portion by covering the electrode with the insulator (step S330), and forming an opening in the first sealing portion In the process (step S350), the opening reaches the electrode provided on the surface side of each of the plurality of semiconductor elements, and the conductive material layer serving as the second lead of the second external electrode is directly formed on the back surface to form a conductive material layer The second lead (step S362); the opening of the first sealing portion is filled with a conductive material to form the electrode The process of the convex portion 82A (step S371); forming a first lead wire electrically connected to the convex portion to be one of the first external electrodes (step S372); and cutting the first sealing portion and the first portion (2) A process in which at least one of the sealing portions separates a plurality of semiconductor devices formed based on the formation of the first lead (step S380).
又，上述各工程，在技術可能範圍內可以替換，亦可同時實施。Moreover, each of the above-mentioned projects may be replaced within the technical scope and may be implemented simultaneously.
具體言之可採用以下方法。Specifically, the following methods can be employed.
圖10(a)～(f)為第3實施形態之半導體裝置之製造方法之例示之工程圖。10(a) to 10(f) are diagrams showing an example of a method of manufacturing a semiconductor device according to a third embodiment.
圖11(a)～(e)為第3實施形態之半導體裝置之製造方法之例示之工程圖，圖11(a)為接續圖10(f)之圖。11(a) to 11(e) are diagrams showing an example of a method of manufacturing a semiconductor device according to a third embodiment, and Fig. 11(a) is a view subsequent to Fig. 10(f).
首先，如圖10(a)所示，準備形成有半導體元件11、以及電極44(設於半導體元件11之第1面、亦即表面的電極)及電極43(設於半導體元件11之第2面、亦即背面的電極)的半導體晶圓50。亦即，本製造方法，係另具備於複數個半導體元件11之個別之第2面(背面)，形成成為複數個半導體元件11之個別之一部分的電極43之工程。本具體例中，該電極43，係於複數個半導體元件11被形成為連續之層。其中，半導體晶圓50之厚度，例如為約300μm。本具體例中，電極43，可使用在複數個半導體元件11之中連接之形狀、例如未被圖案化者。形成為連續之層。First, as shown in FIG. 10(a), the semiconductor element 11 and the electrode 44 (electrode provided on the first surface of the semiconductor element 11, that is, the surface), and the electrode 43 (the second electrode provided in the semiconductor element 11) are prepared. The semiconductor wafer 50 of the surface, that is, the electrode on the back side. In other words, the manufacturing method is another step of forming the electrode 43 which is an integral part of the plurality of semiconductor elements 11 on the second surface (back surface) of the plurality of semiconductor elements 11. In this specific example, the electrode 43 is formed as a continuous layer of a plurality of semiconductor elements 11. The thickness of the semiconductor wafer 50 is, for example, about 300 μm. In the specific example, the electrode 43 may be formed in a shape connected to a plurality of semiconductor elements 11, for example, not patterned. Formed as a continuous layer.
之後，如圖10(b)所示，於半導體晶圓50之背面側以樹脂層形成第2密封部70B。該形成，可使用利用液狀樹脂之成形、傳遞成形、壓縮成形、及利用片狀樹脂的方法等。Thereafter, as shown in FIG. 10(b), the second sealing portion 70B is formed of a resin layer on the back side of the semiconductor wafer 50. For the formation, a method using a liquid resin, a transfer molding, a compression molding, a method using a sheet-like resin, or the like can be used.
之後，如圖10(c)所示，在半導體元件11之間切斷半導體晶圓50，形成到達第2密封部70B之中途的溝85。亦即，在複數個半導體元件11彼此之間，形成由半導體晶圓50之表面到達第2密封部70B之中途的溝85，而將複數個半導體元件11之各個予以分離。如此則，半導體元件11雖被分離，但成為以第2密封部70B予以固定之狀態。Thereafter, as shown in FIG. 10(c), the semiconductor wafer 50 is cut between the semiconductor elements 11, and a trench 85 that reaches the middle of the second sealing portion 70B is formed. That is, each of the plurality of semiconductor elements 11 is formed with a groove 85 that reaches the middle of the second sealing portion 70B from the surface of the semiconductor wafer 50, and separates the plurality of semiconductor elements 11. In this manner, the semiconductor element 11 is separated, but is fixed by the second sealing portion 70B.
之後，如圖10(d)所示，於溝85及半導體元件11之周圍填埋樹脂而形成第1密封部70A。亦即，於半導體晶圓50之表面側，在溝85填充樹脂(絕緣體)，而形成第1密封部70A。此時，亦可使用利用液狀樹脂之成形、傳遞成形、壓縮成形、及利用片狀樹脂的方法等。Thereafter, as shown in FIG. 10(d), resin is filled around the trench 85 and the semiconductor element 11, and the first sealing portion 70A is formed. That is, the resin 85 (insulator) is filled in the groove 85 on the surface side of the semiconductor wafer 50 to form the first sealing portion 70A. In this case, a method of molding, transfer molding, compression molding, and a sheet-like resin using a liquid resin may be used.
之後，如圖10(e)所示，分別沿哦第1密封部70A及第2密封部70B之表面使變薄，此時，電極44係設為填埋於第1密封部70A之中的狀態。特別是，第2密封部70B被除去，結果電極43由第1密封部70A露出。Thereafter, as shown in FIG. 10(e), the surfaces of the first sealing portion 70A and the second sealing portion 70B are thinned. In this case, the electrode 44 is filled in the first sealing portion 70A. status. In particular, the second sealing portion 70B is removed, and as a result, the electrode 43 is exposed by the first sealing portion 70A.
之後，如圖10(f)所示，由第1密封部70A之表面藉由雷射實施穿孔加工，形成到達電極44之孔90。亦即，於第1密封部70A形成到達電極44(設於複數個半導體元件11之個別表面側的電極)之孔90(開口)。Thereafter, as shown in FIG. 10(f), the surface of the first sealing portion 70A is subjected to a punching process by a laser to form a hole 90 reaching the electrode 44. In other words, the hole 90 (opening) reaching the electrode 44 (the electrode provided on the individual surface side of the plurality of semiconductor elements 11) is formed in the first sealing portion 70A.
之後，如圖11(a)所示，實施電極44之表面之潔淨，藉由無電解鍍層形成銅等之種層91。另外，種層91之形成亦可使用例如濺鍍法等任意方法。Thereafter, as shown in Fig. 11(a), the surface of the electrode 44 is cleaned, and a layer 91 of copper or the like is formed by electroless plating. Further, the seed layer 91 may be formed by any method such as a sputtering method.
之後，如圖11(b)所示，於孔90之周圍之第1密封部70A之表面形成阻劑92。該阻劑92不覆蓋孔90，而具有使孔90露出之圖案形狀。Thereafter, as shown in FIG. 11(b), a resist 92 is formed on the surface of the first sealing portion 70A around the hole 90. The resist 92 does not cover the aperture 90 but has a pattern shape that exposes the aperture 90.
之後，如圖11(c)所示，實施銅等之鍍層，形成第1外部電極82與第2外部電極83。亦即，形成包含於第1外部電極82的凸部82A(於孔90被填埋有導電材料之部分)及第1引線82B以及成為第2外部電極83的第2引線83B。Thereafter, as shown in FIG. 11(c), a plating layer of copper or the like is applied to form the first external electrode 82 and the second external electrode 83. In other words, the convex portion 82A included in the first outer electrode 82 (the portion in which the conductive material is filled in the hole 90), the first lead 82B, and the second lead 83B serving as the second outer electrode 83 are formed.
此時，第1引線82B與第2引線83B可以同時形成。又，本實施形態不限定於此，形成第1引線82B之後形成第2引線83B亦可。另外，形成第2引線83B之後形成第1引線82B亦可。各別形成第1引線82B與第2引線83B時，例如可採用塗布導電材料之方法或壓合導電片樹脂之方法。At this time, the first lead 82B and the second lead 83B can be simultaneously formed. Further, the present embodiment is not limited thereto, and the second lead 83B may be formed after the first lead 82B is formed. Further, the first lead 82B may be formed after the second lead 83B is formed. When the first lead 82B and the second lead 83B are formed separately, for example, a method of applying a conductive material or a method of pressing a conductive sheet resin may be employed.
如上述說明，本具體例中，形成凸部82A的工程，可以包含：在由開口(孔90)露出之電極44(設於第1面的電極)形成種層91的工程；及在開口周圍之第1密封部70A表面形成阻劑，在除去阻劑以外的區域，藉由電解鍍層法於種層91之上的開口(孔90)內部填充導電性材料的工程。As described above, in the specific example, the process of forming the convex portion 82A may include a process of forming the seed layer 91 on the electrode 44 (electrode provided on the first surface) exposed by the opening (the hole 90); and around the opening A resist is formed on the surface of the first sealing portion 70A, and a conductive material is filled in the opening (hole 90) on the seed layer 91 by an electrolytic plating method in a region other than the resist.
形成第1引線82B之工程可以包含：在開口(孔90)周圍之第1密封部70A表面形成阻劑，在除去阻劑以外的區域，藉由電解鍍層法形成連接於凸部82A之導電材料層。The process of forming the first lead 82B may include forming a resist on the surface of the first sealing portion 70A around the opening (the hole 90), and forming a conductive material connected to the convex portion 82A by an electrolytic plating method in a region other than the resist. Floor.
又，本具體例中，複數個半導體元件11之各個，係另具有：設於複數個半導體元件11之各別之第2面(背面)，延伸於複數個半導體元件11彼此間的電極(電極43)。Further, in this specific example, each of the plurality of semiconductor elements 11 further includes an electrode (electrode) provided on each of the second surface (back surface) of the plurality of semiconductor elements 11 and extending between the plurality of semiconductor elements 11 43).
又，本具體例之製造方法，係另具備：於複數個半導體元件11之各別之第2面，形成延伸於複數個半導體元件11彼此間的電極(電極43)之工程。形成第2引線83B之工程，係包含：形成連接於電極43(設於複數個半導體元件11之個別之第2面的電極)的第2引線83B之工程。Moreover, the manufacturing method of this specific example further includes a process of forming an electrode (electrode 43) extending between the plurality of semiconductor elements 11 on the respective second surfaces of the plurality of semiconductor elements 11. The process of forming the second lead 83B includes a process of forming the second lead 83B connected to the electrode 43 (the electrode provided on the second surface of the plurality of semiconductor elements 11).
於該複數個半導體元件11之各別之第2面，形成延伸於複數個半導體元件11彼此間的電極(電極43)之工程，係如圖10(a)所示，例如於步驟S310之前被實施。另外，於該複數個半導體元件11之各別之第2面，形成延伸於複數個半導體元件11彼此間的電極(電極43)之工程，例如可於形成第2引線83B之工程(步驟S362)之前之任意工程被實施。例如，可於第2密封部70B被除去，半導體元件11之第2面(設置電極43之面)由第1密封部70A露出之後被實施。The process of forming an electrode (electrode 43) extending between the plurality of semiconductor elements 11 on the second surface of each of the plurality of semiconductor elements 11 is as shown in FIG. 10(a), for example, before step S310. Implementation. Further, in the second surface of each of the plurality of semiconductor elements 11, a process of forming an electrode (electrode 43) extending between the plurality of semiconductor elements 11 is formed, for example, a process of forming the second lead 83B (step S362) Any previous project was implemented. For example, the second sealing portion 70B can be removed, and the second surface of the semiconductor element 11 (the surface on which the electrode 43 is provided) is exposed by the first sealing portion 70A.
之後，如圖11(d)所示，剝離阻劑92，將工件壓合於切割片94，藉由刃/切割鋸予以切斷，分離為半導體裝置。Thereafter, as shown in FIG. 11(d), the resist 92 is peeled off, the workpiece is pressed against the dicing sheet 94, and cut by a blade/cutting saw to be separated into a semiconductor device.
之後，如圖11(e)所示，由切割片94將半導體裝置剝離，於第1外部電極82及第2外部電極83之表面形成鍍層82C、83C。Thereafter, as shown in FIG. 11(e), the semiconductor device is peeled off by the dicing sheet 94, and plating layers 82C and 83C are formed on the surfaces of the first external electrode 82 and the second external electrode 83.
此情況下，密封部70之外徑可以大於鍍層82C、83C之外徑，或小於。In this case, the outer diameter of the sealing portion 70 may be larger than the outer diameter of the plating layers 82C, 83C, or smaller.
如上述說明，於上述第1密封部之上述開口填充導電材料，形成連接於上述電極的上述凸部82A的工程(步驟S371)與形成電連接於上述凸部82A，成為上述第1外部電極82之一部分的第1引線82B之工程(步驟S372)，可以藉由電解鍍層法等導孔填充(via filling)之形成方法統合實施。As described above, the opening of the first sealing portion is filled with a conductive material to form the convex portion 82A connected to the electrode (step S371), and is electrically connected to the convex portion 82A to be the first external electrode 82. The part of the first lead 82B (step S372) can be integrated by a method of forming a via filling such as an electrolytic plating method.
於上述導孔填充，例如以在孔90之內部鍍層液之對流程度低的部分，先行成長鍍層的方式來設定電解鍍層之條件。In the above-mentioned via hole filling, for example, the condition of the electrolytic plating layer is set by growing the plating layer in a portion where the degree of convection of the plating liquid inside the hole 90 is low.
圖12(a)～(f)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。12(a) to 12(f) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
於該方法，係使用圖3(a)所示半導體晶圓50、亦即形成有電極44(相當於設於第1面(表面)的電極)的半導體晶圓50。In this method, the semiconductor wafer 50 shown in FIG. 3(a), that is, the semiconductor wafer 50 on which the electrode 44 (corresponding to the electrode provided on the first surface (surface)) is formed.
如圖12(a)所示，和圖4(a)同樣，於半導體晶圓50之表面側形成溝85。例如可藉由刃/切割鋸使寬150μm程度之溝縱橫形成於半導體晶圓50之表面。As shown in FIG. 12(a), as in FIG. 4(a), a groove 85 is formed on the surface side of the semiconductor wafer 50. For example, a groove having a width of about 150 μm can be formed on the surface of the semiconductor wafer 50 by a blade/cutting saw.
之後，如圖12(b)所示，和圖4(b)同樣，藉由樹脂填埋溝85，形成成為絕緣體的第1密封部70A(密封部70)。Then, as shown in FIG. 12(b), similarly to FIG. 4(b), the first sealing portion 70A (sealing portion 70) serving as an insulator is formed by the resin filling groove 85.
之後，如圖12(c)所示，和圖10(f)同樣，由第1密封部70A之表面例如藉由雷射實施穿孔加工，形成到達電極44之孔90。亦即，於第1密封部70A形成到達電極44(設於複數個半導體元件11之個別表面側的電極)之孔90(開口)。Thereafter, as shown in FIG. 12(c), similarly to FIG. 10(f), the surface of the first sealing portion 70A is subjected to a punching process by, for example, a laser to form a hole 90 reaching the electrode 44. In other words, the hole 90 (opening) reaching the electrode 44 (the electrode provided on the individual surface side of the plurality of semiconductor elements 11) is formed in the first sealing portion 70A.
之後，如圖12(d)所示，和圖11(a)同樣，實施電極44之表面之潔淨，藉由無電解鍍層形成銅等之種層91。另外，種層91之形成亦可使用例如濺鍍法等任意方法。Thereafter, as shown in Fig. 12(d), as in Fig. 11(a), the surface of the electrode 44 is cleaned, and a layer 91 of copper or the like is formed by electroless plating. Further, the seed layer 91 may be formed by any method such as a sputtering method.
之後，如圖12(e)所示，和圖11(b)同樣，於孔90之周圍之第1密封部70A之表面形成阻劑92。該阻劑92不覆蓋孔90，而具有使孔90露出之圖案形狀。Thereafter, as shown in FIG. 12(e), a resist 92 is formed on the surface of the first sealing portion 70A around the hole 90, similarly to FIG. 11(b). The resist 92 does not cover the aperture 90 but has a pattern shape that exposes the aperture 90.
之後，如圖12(f)所示，和圖4(c)同樣，針對半導體晶圓50之背面側進行研磨直至填埋於溝85的第1密封部70A(密封部70)露出為止，使變薄。如此而使形成於半導體晶圓50之半導體元件11分離。又，研磨半導體晶圓50之背面側而使半導體元件11分離的工程，可於圖12(b)所示工程之後圖12(f)所示工程之前的任意階段實施。Then, as shown in FIG. 12(f), the back surface side of the semiconductor wafer 50 is polished until the first sealing portion 70A (sealing portion 70) buried in the groove 85 is exposed, as in FIG. Thinning. Thus, the semiconductor element 11 formed on the semiconductor wafer 50 is separated. Further, the process of polishing the back side of the semiconductor wafer 50 to separate the semiconductor element 11 can be carried out at any stage before the construction shown in Fig. 12(f) after the construction shown in Fig. 12(b).
又，和圖11(c)同樣，實施銅等之電解鍍層，形成凸部82A及第1引線82B。亦即，形成第1外部電極82。Further, similarly to FIG. 11(c), an electrolytic plating layer of copper or the like is applied to form the convex portion 82A and the first lead 82B. That is, the first external electrode 82 is formed.
之後，形成第2引線83B。例如可藉由實施銅等之電解鍍層之方法，同時形成第1引線82B與第2引線83B。此時，必要時可於半導體晶圓50之背面形成電極43，於電極43之表面實施銅等之電解鍍層，形成第2引線83B。Thereafter, the second lead 83B is formed. For example, the first lead 82B and the second lead 83B can be simultaneously formed by a method of performing electrolytic plating of copper or the like. At this time, if necessary, the electrode 43 may be formed on the back surface of the semiconductor wafer 50, and an electrolytic plating layer of copper or the like may be formed on the surface of the electrode 43 to form the second lead 83B.
又，第2引線83B可設於半導體晶圓50之背面側全面，此情況下，例如第2引線83B之形成可採用例如塗布導電材料之方法或壓合導電片樹脂之方法。Further, the second lead 83B may be provided on the back side of the semiconductor wafer 50. In this case, for example, the second lead 83B may be formed by, for example, a method of applying a conductive material or a method of pressing a conductive sheet resin.
如上述說明，第1引線82B與第2引線83B可以同時形成，或形成第1引線82B之後形成第2引線83B亦可。另外，形成第2引線83B之後形成第1引線82B亦可。各別形成第1引線82B與第2引線83B時，例如可採用塗布導電材料之方法或壓合導電片樹脂之方法。As described above, the first lead 82B and the second lead 83B may be formed at the same time, or the second lead 83B may be formed after the first lead 82B is formed. Further, the first lead 82B may be formed after the second lead 83B is formed. When the first lead 82B and the second lead 83B are formed separately, for example, a method of applying a conductive material or a method of pressing a conductive sheet resin may be employed.
如上述說明，形成第1引線82B與第2引線83B之後，例如藉由圖11(d)及圖11(e)說明之方法將半導體元件11分離，必要時形成鍍層82C、83C，而製造半導體裝置。As described above, after the first lead 82B and the second lead 83B are formed, the semiconductor element 11 is separated by, for example, the method described in FIGS. 11(d) and 11(e), and if necessary, the plating layers 82C and 83C are formed to manufacture a semiconductor. Device.
如上述說明，本實施形態之半導體裝置之製造方法，係具備：在半導體晶圓50所形成之複數個半導體元件11之表面的複數個半導體元件11彼此之間形成溝85的工程；在溝85填充絕緣體，以絕緣體覆蓋電極44而形成密封部70(第1密封部70A)的工程；於密封部70形成開口(孔90)的工程，該開口係到達複數個半導體元件11之各個表面側之第1面之電極44者；於密封部70之開口填充導電性材料，而形成連接於電極44之凸部82A的工程；形成電連接於凸部82A，成為第1外部電極82之一部分之第1引線82B的工程；針對和半導體晶圓11之表面呈對向的背面進行研磨直至密封部70露出為止，而將半導體晶圓50分離為各個半導體元件11的工程；於半導體元件11之背面，直接形成成為第2外部電極83之第2引線83B之導電材料層，而形成第2引線83B的工程；及切斷密封部70，而將連接有第1引線82B的複數個半導體元件11彼此予以分離的工程。As described above, the method of manufacturing the semiconductor device of the present embodiment includes the process of forming the trenches 85 between the plurality of semiconductor elements 11 on the surface of the plurality of semiconductor elements 11 formed on the semiconductor wafer 50. The insulating body is filled with an insulator to cover the electrode 44 to form the sealing portion 70 (first sealing portion 70A), and the opening portion (hole 90) is formed in the sealing portion 70, and the opening reaches the respective surface sides of the plurality of semiconductor elements 11. The electrode 44 of the first surface is filled with a conductive material in the opening of the sealing portion 70 to form a convex portion 82A connected to the electrode 44, and is electrically connected to the convex portion 82A to be a part of the first external electrode 82. The process of the lead wire 82B; polishing the back surface opposite to the surface of the semiconductor wafer 11 until the sealing portion 70 is exposed, and separating the semiconductor wafer 50 into the respective semiconductor elements 11; on the back surface of the semiconductor element 11, The conductive material layer serving as the second lead 83B of the second external electrode 83 is directly formed to form the second lead 83B, and the sealing portion 70 is cut, and the first lead 82B is connected. Semiconductor element 11 to be separated from one another project.
形成凸部82A的工程及形成第1引線82B的工程之至少1個，例如可以包含在孔90之周圍之第1密封部70A之表面形成阻劑，在除去阻劑以外的區域，藉由電解鍍層法於上述種層之上的上述開口內部填充導電性材料的工程。又，形成第1引線82B的工程及形成第2引線83B的工程之至少1個，亦可以使用壓合導電片的方法。At least one of the process of forming the convex portion 82A and the process of forming the first lead 82B may include, for example, forming a resist on the surface of the first sealing portion 70A around the hole 90, and performing electrolysis in a region other than the resist. The plating method is a process of filling a conductive material inside the opening above the above-mentioned seed layer. Further, at least one of the process of forming the first lead 82B and the process of forming the second lead 83B may be a method of pressing the conductive sheet.
圖13(a)～(d)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。13(a) to 13(d) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
彼等圖係表示圖11(a)之工程之後之工程的另一例。These figures represent another example of the work after the construction of Figure 11(a).
如圖13(a)所示，於複數個半導體元件11之各別之第2面形成第2引線83B(步驟S362)。之後，進行銅等之電解鍍層，形成凸部82A(步驟S371)。於該凸部82A之形成，可使用例如印刷導電糊等或注滴等各種方法予以塗布的方法。另外，步驟S362與步驟S371之順序可以替換。As shown in FIG. 13(a), the second lead 83B is formed on each of the second surfaces of the plurality of semiconductor elements 11 (step S362). Thereafter, electrolytic plating of copper or the like is performed to form the convex portion 82A (step S371). The formation of the convex portion 82A can be carried out by, for example, printing a conductive paste or the like or by various methods such as dropping. In addition, the order of step S362 and step S371 can be replaced.
之後，如圖13(b)所示，於孔90之周圍之第1密封部70A之表面形成阻劑92，該阻劑92不覆蓋孔90，而具有使孔90露出之形狀。Thereafter, as shown in FIG. 13(b), a resist 92 is formed on the surface of the first sealing portion 70A around the hole 90. The resist 92 does not cover the hole 90 and has a shape in which the hole 90 is exposed.
之後，如圖13(c)所示，在未被阻劑92覆蓋的凸部82A之上形成第1引線82B行解碼器第1外部電極82(步驟S372)。Thereafter, as shown in FIG. 13(c), the first lead 82B row decoder first external electrode 82 is formed on the convex portion 82A not covered by the resist 92 (step S372).
之後，如圖13(d)所示，剝離阻劑92，和例如圖11(d)所示說明同樣，分離半導體元件11，完成半導體裝置。Thereafter, as shown in FIG. 13(d), the resist 92 is peeled off, and the semiconductor element 11 is separated in the same manner as described, for example, in FIG. 11(d), to complete the semiconductor device.
又，例如於圖12(c)所示說明之工程之後，研磨半導體晶圓50之背面側將半導體元件11分離之後，形成凸部82A，形成第2引線83B，形成如圖13(a)所示構造之後，經由圖13(b)～(d)之工程，而可以形成半導體裝置。另外，於上述中，凸部82A之形成及第2引線83B之形成之順序可以替換。又，此情況下，必要時技術性可於任意階段形成背面側之電極43。Further, for example, after the process described in FIG. 12(c), the semiconductor element 11 is separated on the back side of the polished semiconductor wafer 50, and then the convex portion 82A is formed to form the second lead 83B, which is formed as shown in FIG. 13(a). After the structure is shown, a semiconductor device can be formed through the processes of FIGS. 13(b) to (d). Further, in the above, the order of formation of the convex portion 82A and the formation of the second lead 83B may be replaced. Further, in this case, it is technically possible to form the electrode 43 on the back side at any stage as necessary.
圖14(a)～(b)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。14(a) to 14(b) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
彼等圖係表示圖11(a)之工程之後之工程的另一例。These figures represent another example of the work after the construction of Figure 11(a).
如圖14(a)所示，於複數個半導體元件11之各別之第2面形成第2引線83B(步驟S362)。之後，進行銅等之電解鍍層，形成凸部82A及第1引線82B，形成第1外部電極82(步驟S371及步驟S372)。另外，步驟S362、步驟S371及步驟S372之順序可以替換。As shown in FIG. 14(a), the second lead 83B is formed on each of the second surfaces of the plurality of semiconductor elements 11 (step S362). Thereafter, electrolytic plating such as copper is performed to form the convex portion 82A and the first lead 82B, and the first external electrode 82 is formed (steps S371 and S372). In addition, the order of step S362, step S371, and step S372 may be replaced.
之後，如圖14(b)所示，例如藉由刃/切割鋸將第1引線82B之部分分割。此時，切斷密封部70(第1密封部70A)之至少一部分亦可。Thereafter, as shown in FIG. 14(b), the portion of the first lead 82B is divided by, for example, a blade/cutting saw. At this time, at least a part of the sealing portion 70 (first sealing portion 70A) may be cut.
之後，例如和圖11(d)之說明同樣，分離半導體元件11而完成半導體裝置。該方法為不使用阻劑92之方法，工程被簡化。Thereafter, the semiconductor device 11 is separated to complete the semiconductor device, for example, as in the description of FIG. 11(d). This method is a method in which the resist 92 is not used, and the engineering is simplified.
又，和分割第1引線82B之部分呈連續，而切斷密封部70(第1密封部70A)之全部，分離半導體元件11亦可。此情況下，例如於第1引線82B之部分之分割之前，將切割片94壓合於工件之後，連續將第1引線82B與半導體元件11予以分割。Further, the portion in which the first lead 82B is divided is continuous, and all of the sealing portion 70 (first sealing portion 70A) is cut, and the semiconductor element 11 may be separated. In this case, for example, before the division of the portion of the first lead 82B, the dicing sheet 94 is pressed against the workpiece, and the first lead 82B and the semiconductor element 11 are continuously divided.
又，例如於圖12(c)所示說明之工程之後，研磨半導體晶圓50之背面側將半導體元件11分離之後，形成凸部82A及第1引線82B，形成第2引線83B，形成如圖14(a)所示構造亦可。另外，於上述中，凸部82A及第1引線82B之形成，與第2引線83B之形成之順序可以替換。又，此情況下，必要時技術性可於任意階段形成背面側之電極43。Further, for example, after the process described in FIG. 12(c), the semiconductor element 11 is separated on the back side of the polished semiconductor wafer 50, and then the convex portion 82A and the first lead 82B are formed to form the second lead 83B, which is formed as shown in FIG. The structure shown in Fig. 14(a) is also acceptable. Further, in the above, the order in which the convex portion 82A and the first lead 82B are formed and the second lead 83B are formed may be replaced. Further, in this case, it is technically possible to form the electrode 43 on the back side at any stage as necessary.
圖15(a)～(b)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。15(a) to 15(b) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
彼等圖係表示圖11(a)之工程之後之工程的另一例。These figures represent another example of the work after the construction of Figure 11(a).
如圖15(a)所示，藉由銅等之電解鍍層，於複數個半導體元件11之各別之第2面形成第2引線83B，與此同時形成凸部82A及第1引線82B而形成第1外部電極82。於該方法，第1引線82B，係連續設於複數個半導體元件11之個別表面側，第2引線83B係連續設於複數個半導體元件11之個別背面側。As shown in Fig. 15 (a), the second lead 83B is formed on the second surface of each of the plurality of semiconductor elements 11 by electrolytic plating such as copper, and the convex portion 82A and the first lead 82B are formed simultaneously. The first outer electrode 82. In this method, the first lead 82B is continuously provided on the respective surface sides of the plurality of semiconductor elements 11, and the second lead 83B is continuously provided on the individual back side of the plurality of semiconductor elements 11.
之後，如圖15(b)所示，將切割片94壓合於工件，藉由刃/切割鋸將第1引線82B、密封部70(第1密封部70A)、及第2引線83B一次予以分割。Thereafter, as shown in FIG. 15(b), the dicing sheet 94 is pressed against the workpiece, and the first lead 82B, the sealing portion 70 (the first sealing portion 70A), and the second lead 83B are once applied by the blade/cutting saw. segmentation.
於該方法，工程更能被簡化。In this way, engineering can be simplified.
又，例如於圖12(c)所示說明之工程之後，研磨半導體晶圓50之背面側將半導體元件11分離之後，形成凸部82A及第1引線82B，形成第2引線83B，形成如圖15(a)所示構造亦可。另外，於上述中，凸部82A及第1引線82B之形成，與第2引線83B之形成之順序可以替換。又，此情況下，必要時技術性可於任意階段形成背面側之電極43。Further, for example, after the process described in FIG. 12(c), the semiconductor element 11 is separated on the back side of the polished semiconductor wafer 50, and then the convex portion 82A and the first lead 82B are formed to form the second lead 83B, which is formed as shown in FIG. The structure shown in Fig. 15(a) is also acceptable. Further, in the above, the order in which the convex portion 82A and the first lead 82B are formed and the second lead 83B are formed may be replaced. Further, in this case, it is technically possible to form the electrode 43 on the back side at any stage as necessary.
圖16(a)～(c)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。16(a) to 16(c) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
彼等圖係表示圖11(a)之工程之後之工程的另一例。These figures represent another example of the work after the construction of Figure 11(a).
如圖16(a)所示，藉由銅等之電解鍍層，於開口(孔90)之內部填充導電材料而形成凸部82A。於該凸部82A之形成，可使用例如印刷導電糊等或澆注法等各種方法予以塗布的方法。As shown in Fig. 16 (a), a conductive material is filled in the opening (hole 90) by an electrolytic plating layer such as copper to form a convex portion 82A. The formation of the convex portion 82A can be carried out by, for example, various methods such as printing a conductive paste or a casting method.
之後，如圖16(b)所示，藉由銅等之電解鍍層，於複數個半導體元件11之各別之第2面形成第2引線83B，與此同時形成第1引線82B而形成第1外部電極82。於第2引線83B之形成及第1引線82B之形成之至少之一，例如採用壓合導電片之方法亦可。Then, as shown in FIG. 16(b), the second lead 83B is formed on the second surface of each of the plurality of semiconductor elements 11 by electrolytic plating such as copper, and the first lead 82B is formed at the same time to form the first lead. External electrode 82. At least one of the formation of the second lead 83B and the formation of the first lead 82B may be, for example, a method of pressing a conductive sheet.
之後，如圖16(c)所示，例如將切割片94壓合於工件，藉由刃/切割鋸將第1引線82B、密封部70(第1密封部70A)、及第2引線83B彙整予以分割。Thereafter, as shown in FIG. 16(c), for example, the dicing sheet 94 is pressed against the workpiece, and the first lead 82B, the sealing portion 70 (the first sealing portion 70A), and the second lead 83B are gathered by the blade/cutting saw. Divide it.
該方法亦為工程被簡化之方法。This method is also a method of engineering simplification.
又，例如於圖12(c)所示說明之工程之後，研磨半導體晶圓50之背面側將半導體元件11分離之後，形成凸部82A，可以形成如圖16(a)所示構造。又，此情況下，必要時技術性可於任意階段形成背面側之電極43。Further, for example, after the process described in FIG. 12(c), the semiconductor element 11 is separated on the back side of the polished semiconductor wafer 50, and then the convex portion 82A is formed, and the structure shown in FIG. 16(a) can be formed. Further, in this case, it is technically possible to form the electrode 43 on the back side at any stage as necessary.
如上述說明，本實施形態之半導體裝置之製造方法可作各種變更實施。As described above, the method of manufacturing the semiconductor device of the present embodiment can be variously modified.
本實施形態之半導體裝置及其製造方法之中，係於第1外部電極82設置凸部82A，而省略對第2外部電極83之凸部之提供，因此和在第1外部電極82及第2外部電極83雙方設置凸部之情況比較，可省略製造工程，特別是，可削減元件(凸部)，相較於在表面與背面雙方設置凸部之情況更能達成低成本化。In the semiconductor device and the method of manufacturing the same according to the present embodiment, the convex portion 82A is provided in the first external electrode 82, and the provision of the convex portion of the second external electrode 83 is omitted. Therefore, the first external electrode 82 and the second external electrode 82 and the second external electrode 82 are provided. In the case where the convex portions are provided on both the external electrodes 83, the manufacturing process can be omitted, and in particular, the elements (convex portions) can be reduced, and the cost can be reduced as compared with the case where the convex portions are provided on both the front surface and the back surface.
例如在第1外部電極82及第2外部電極83雙方設置凸部時，例如係於如圖9所示步驟S330與步驟S350之間，實施在上述第2密封部形成到達上述半導體元件之上述背面側電極的開口之工程(例如步驟S340)，於步驟S350與步驟S362之間，實施在上述第2密封部之上述開口填埋導電材料而形成第2凸部之工程(例如步驟S361)。和此相比，本實施形態之製造方法之中，上述步驟S340與步驟S361則被省略，相較於在表面與背面雙方設置凸部之情況更能達成低成本化。For example, when both the first outer electrode 82 and the second outer electrode 83 are provided with convex portions, for example, between step S330 and step S350 shown in FIG. 9, the second sealing portion is formed to reach the back surface of the semiconductor element. In the process of opening the side electrode (for example, step S340), between the step S350 and the step S362, a process of filling the conductive material in the opening of the second sealing portion to form the second convex portion is performed (for example, step S361). In contrast, in the manufacturing method of the present embodiment, the above-described steps S340 and S361 are omitted, and the cost can be reduced as compared with the case where the convex portions are provided on both the front surface and the back surface.
如上述說明，依據本實施形態，可以省略工程，可以更簡略之工程製造半導體裝置。As described above, according to the present embodiment, the engineering can be omitted, and the semiconductor device can be manufactured more simply.
又，依據第2實施形態及第3實施形態之半導體裝置之製造方法，可也製造例如如圖1所示構成之半導體裝置(密封部70之斷面稍大於第1外部電極82及第2外部電極83)或如圖5所示構成之半導體裝置(密封部70之側面與第1外部電極82之側面及第2外部電極83之側面實質上位於同一平面上)等任意構成之半導體裝置。Further, according to the method of manufacturing the semiconductor device of the second embodiment and the third embodiment, a semiconductor device having the structure shown in FIG. 1 can be manufactured (the cross section of the sealing portion 70 is slightly larger than the first external electrode 82 and the second external portion). The electrode 83) or a semiconductor device having any configuration such as a semiconductor device (the side surface of the sealing portion 70 and the side surface of the first external electrode 82 and the side surface of the second external electrode 83 are substantially on the same plane) as shown in FIG.
圖17為第4實施形態之另一半導體裝置之模式圖。Fig. 17 is a schematic view showing another semiconductor device of the fourth embodiment.
亦即，該圖係相當於如圖1(b)所示之模式斷面圖。That is, the drawing corresponds to a schematic sectional view as shown in Fig. 1(b).
如圖17所示，於本具體例之半導體裝置中於半導體元件11之表面設置2個外部電極、亦即第1外部電極82及第3外部電極84。第3外部電極84，係具有對於和半導體元件11之表面呈大略平行的第1主面朝垂直方向突出，而連接於半導體元件11之表面電極的凸部84A。由，於圖中，半導體元件11之電極被省略。第3外部電極84具有凸部84A及第3引線84B，於第3外部電極84之表面設置鍍層84C。As shown in FIG. 17, in the semiconductor device of this specific example, two external electrodes, that is, the first external electrode 82 and the third external electrode 84 are provided on the surface of the semiconductor element 11. The third external electrode 84 has a convex portion 84A that is protruded in the vertical direction from the first main surface that is substantially parallel to the surface of the semiconductor element 11, and is connected to the surface electrode of the semiconductor element 11. In the figure, the electrodes of the semiconductor element 11 are omitted. The third external electrode 84 has a convex portion 84A and a third lead 84B, and a plating layer 84C is provided on the surface of the third external electrode 84.
另外，於半導體元件11之背面設置第2外部電極83，本具體例中，第2外部電極83不具備凸部。Further, the second external electrode 83 is provided on the back surface of the semiconductor element 11. In this specific example, the second external electrode 83 does not have a convex portion.
如上述說明，本實施形態之半導體裝置，係具備：半導體元件，其具有互呈對向之第1面(相當於表面)及第2面(相當於背面)，及設於第1面的電極(例如電極44)；第1外部電極82(包含凸部82A及第1引線82B)，和半導體元件11之第1面呈對向，具有：對於第1面呈大略平行的第1主面，對於第1主面呈大略垂直的第1側面，及凸部(凸部82A)，對於第1主面朝垂直方向突出，被連接於第1電極(電極44)；第2外部電極83(包含第2引線83B)，和半導體元件11之第2面呈對向，具有對於第2面呈大略平行的第2主面，對於第2主面呈大略垂直的第2側面；及第3外部電極84(包含凸部84A及第3引線84B)，和半導體元件11之第1面呈對向，具有對於第1面呈大略平行的第3主面，對於第3主面呈大略垂直的第3側面，及凸部84A，對於第3主面朝垂直方向突出，接觸於上述第1面；及絕緣體(密封部70)，用於覆蓋半導體元件11、第1外部電極82之凸部82A、及第3外部電極84之凸部84A。第1側面、第2側面及第3側面係被設為裝配面，半導體元件11被配置於第1外部電極82及第3外部電極84與第2外部電極83之間。As described above, the semiconductor device of the present embodiment includes the semiconductor element having the first surface (corresponding to the surface) and the second surface (corresponding to the back surface) facing each other, and the electrode provided on the first surface. (for example, the electrode 44); the first external electrode 82 (including the convex portion 82A and the first lead 82B) faces the first surface of the semiconductor element 11, and has a first main surface that is substantially parallel to the first surface. The first side surface that is substantially perpendicular to the first main surface and the convex portion (the convex portion 82A) are protruded in the vertical direction from the first main surface, and are connected to the first electrode (electrode 44), and the second external electrode 83 (including The second lead 83B) is opposed to the second surface of the semiconductor element 11, and has a second main surface that is substantially parallel to the second surface, a second side surface that is substantially perpendicular to the second main surface, and a third external electrode. 84 (including the convex portion 84A and the third lead 84B) is opposed to the first surface of the semiconductor element 11, and has a third main surface that is substantially parallel to the first surface, and a third main surface that is substantially perpendicular to the third main surface. The side surface and the convex portion 84A project in the vertical direction with respect to the third main surface to contact the first surface; and the insulator (sealing portion 70) for covering the half The conductor element 11, the convex portion 82A of the first outer electrode 82, and the convex portion 84A of the third outer electrode 84. The first side surface, the second side surface, and the third side surface are provided as a mounting surface, and the semiconductor element 11 is disposed between the first external electrode 82 and the third external electrode 84 and the second external electrode 83.
又，半導體元件11，可以設於第1面，具有和上述電極(電極44)呈分離之電極(未圖示)。此情況下，第3外部電極84之凸部84A，係連接於和上述電極(電極44)呈分離之上述電極。Further, the semiconductor element 11 may be provided on the first surface and have an electrode (not shown) separated from the electrode (electrode 44). In this case, the convex portion 84A of the third external electrode 84 is connected to the electrode separated from the electrode (electrode 44).
又，本具體例中，第2外部電極83不具備凸部，亦即，第2外部電極83另外具備：第2主面之相反側之面，和第2主面實質上同一大小的相反面。亦即，在由第2外部電極83朝半導體元件11之方向之垂直平面予以切斷時，第2夕外部電極83之斷面形狀，沿著第2外部電極83朝半導體元件11之方向實質上為一定。Further, in the present specific example, the second outer electrode 83 does not include a convex portion, that is, the second outer electrode 83 further includes a surface opposite to the second main surface and an opposite surface of substantially the same size as the second main surface . In other words, when the second outer electrode 83 is cut in the vertical plane in the direction of the semiconductor element 11, the cross-sectional shape of the second outer electrode 83 is substantially along the direction of the second outer electrode 83 toward the semiconductor element 11. Be sure.
例如半導體元件11為電晶體，第1外部電極82為閘極，第2外部電極83為汲極，第3外部電極84為源極。For example, the semiconductor element 11 is a transistor, the first external electrode 82 is a gate, the second external electrode 83 is a drain, and the third external electrode 84 is a source.
依據此種構成之半導體裝置，可以提供全體成為小型化之同時，可削減材料成本及製造成本的半導體裝置。According to the semiconductor device having such a configuration, it is possible to provide a semiconductor device which can reduce the material cost and the manufacturing cost while reducing the overall size.
此種半導體裝置，可以藉由如圖2～16說明之製造方法，及其之變形之製造方法來製造。另外，藉由省略第2外部電極83之凸部之設置，相較於在第1外部電極82(及第3外部電極84)與第2外部電極83之雙方設置凸部之情況，可以省略製程，另外，可以削減元件(凸部)，相較於在表面與背面雙方設置凸部之情況更能達成低成本化。Such a semiconductor device can be manufactured by a manufacturing method as described in FIGS. 2 to 16 and a modified manufacturing method thereof. In addition, by omitting the arrangement of the convex portions of the second external electrode 83, the process can be omitted as compared with the case where the convex portions are provided on both the first external electrode 82 (and the third external electrode 84) and the second external electrode 83. Further, the element (protrusion) can be reduced, and the cost can be reduced as compared with the case where the convex portion is provided on both the front surface and the back surface.
但是，本發明之實施形態不限定於此，第2外部電極83亦可以具有凸部。However, the embodiment of the present invention is not limited thereto, and the second outer electrode 83 may have a convex portion.
亦即，本發明之實施形態中，在半導體元件11之表面與背面分別被設置的第1外部電極82與第2外部電極83之至少一方具有凸部即可。另外，具備在半導體元件11之表面與背面之至少一方被設置的第3外部電極84亦可。第3外部電極84可以具有凸部，或不具備凸部。第3外部電極84可為單數，或複數。In other words, in the embodiment of the present invention, at least one of the first external electrode 82 and the second external electrode 83 provided on the front surface and the back surface of the semiconductor element 11 may have a convex portion. Further, the third external electrode 84 provided on at least one of the front surface and the back surface of the semiconductor element 11 may be provided. The third external electrode 84 may have a convex portion or may not have a convex portion. The third external electrode 84 can be singular or plural.
圖18為本發明實施形態之半導體裝置之裝配狀態之例示之模式圖。Fig. 18 is a schematic view showing an example of an assembled state of a semiconductor device according to an embodiment of the present invention.
如圖18所示，本發明任一實施形態之半導體裝置10a，例如被裝配於基板18之電極焊墊102之上。此時，第1外部電極82之第1側面及第2外部電極83之第2側面為裝配面。半導體元件11被配置於第1外部電極82與第2外部電極83之間。電極焊墊102、第1外部電極82與第2外部電極83，係藉由例如焊錫104電連接。As shown in FIG. 18, the semiconductor device 10a according to any of the embodiments of the present invention is mounted on the electrode pad 102 of the substrate 18, for example. At this time, the first side surface of the first outer electrode 82 and the second side surface of the second outer electrode 83 are the mounting surfaces. The semiconductor element 11 is disposed between the first external electrode 82 and the second external electrode 83. The electrode pad 102, the first external electrode 82, and the second external electrode 83 are electrically connected by, for example, solder 104.
本發明實施形態之半導體裝置之中，於封裝之側面全體被形成電極，因此裝配上具有優點。晶圓之批次處理之大量生產為可能，另外，為不使用框架或基板之製程，可實現低成本化。另外，習知導線接合構造基於長導線而成為困難的低箝位電壓化，在本實施形態之半導體裝置中成為可能。因此，半導體裝置可以超小型化，另外，使用該半導體裝置的電子機器亦可以實現超小型化。In the semiconductor device according to the embodiment of the present invention, since the electrodes are formed on the entire side surface of the package, there is an advantage in assembly. Mass production of wafer batch processing is possible, and cost reduction can be achieved in a process that does not use a frame or a substrate. Further, the conventional wire bonding structure becomes a difficult low clamping voltage based on a long wire, which is possible in the semiconductor device of the present embodiment. Therefore, the semiconductor device can be miniaturized, and the electronic device using the semiconductor device can be further miniaturized.
圖19為本發明實施形態之半導體裝置之裝配狀態之變形例之模式斜視圖。Fig. 19 is a schematic perspective view showing a modification of the assembled state of the semiconductor device according to the embodiment of the present invention.
如圖19所示，本發明任一實施形態之半導體裝置10a，例如被裝配於基板18之電極焊墊102之上，另外，於半導體裝置10a之上，被裝配本發明任一實施形態之半導體裝置10b。例如下側之半導體裝置10a之第1外部電極82與上側之半導體裝置10b之第1外部電極82，係藉由例如焊錫104連接，例如下側之半導體裝置10a之第2外部電極83與上側之半導體裝置10b之第2外部電極83，係藉由例如焊錫104連接。如此則，依據本發明實施形態之半導體裝置，半導體裝置之積層之裝配方法成為容易，使用該半導體裝置的電子機器更能實現小型化。As shown in FIG. 19, the semiconductor device 10a according to any of the embodiments of the present invention is mounted on the electrode pad 102 of the substrate 18, for example, and the semiconductor of any of the embodiments of the present invention is mounted on the semiconductor device 10a. Device 10b. For example, the first external electrode 82 of the lower semiconductor device 10a and the first external electrode 82 of the upper semiconductor device 10b are connected by, for example, solder 104, for example, the second external electrode 83 of the lower semiconductor device 10a and the upper side. The second external electrodes 83 of the semiconductor device 10b are connected by, for example, solder 104. As described above, according to the semiconductor device of the embodiment of the present invention, the method of assembling the stacked layers of the semiconductor device is easy, and the electronic device using the semiconductor device can be further reduced in size.
圖20為本發明實施形態之另一半導體裝置之裝配狀態之例之模式斜視圖。Fig. 20 is a schematic perspective view showing an example of an assembled state of another semiconductor device according to an embodiment of the present invention.
如圖20所示，圖17之例之半導體裝置(半導體裝置10c)，例如被裝配於基板18之電極焊墊102a、102b、102c之上。例如電極焊墊102a、102b、102c，係藉由例如焊錫104分別被連接於第1外部電極82、第2外部電極83及第3外部電極84。此時，亦將第1外部電極82之第1側面及第2外部電極83之第2側面設為裝配面，半導體元件11被裝配於第1外部電極82與第2外部電極83之間。As shown in FIG. 20, the semiconductor device (semiconductor device 10c) of the example of FIG. 17 is mounted on the electrode pads 102a, 102b, and 102c of the substrate 18, for example. For example, the electrode pads 102a, 102b, and 102c are connected to the first external electrode 82, the second external electrode 83, and the third external electrode 84, for example, by the solder 104. At this time, the first side surface of the first outer electrode 82 and the second side surface of the second outer electrode 83 are also mounted surfaces, and the semiconductor element 11 is mounted between the first outer electrode 82 and the second outer electrode 83.
以上係依據具體例說明本發明之實施形態，但本發明並不限定於彼等具體例。例如關於構成半導體裝置之半導體元件、電極、凸部、引線、鍍層、絕緣體、密封部、導電片等各要素之具體構成，業者可由習知範圍藉由適當選擇而同樣實施本發明，獲得同樣效果，而此亦包含於本發明之範圍。The embodiments of the present invention have been described above based on specific examples, but the present invention is not limited to the specific examples. For example, regarding the specific configuration of each element such as a semiconductor element, an electrode, a bump, a lead, a plating layer, an insulator, a sealing portion, and a conductive sheet constituting a semiconductor device, the present invention can be similarly implemented by a suitable range, and the same effect can be obtained. This is also included in the scope of the present invention.
另外，將各具體例之任意2個以上要素於技術可能範圍內加以組合者，只要有包含本發明之要旨之情況下，即包含於本發明之範圍。In addition, any two or more elements of the specific examples may be combined within the scope of the present invention, and are included in the scope of the present invention as long as they contain the gist of the present invention.
另外，作為本發明之實施形態，而依據上述半導體裝置及其製造方法，業者經由適當設計變更實施獲得之半導體裝置及其製造方法，只要有包含本發明之要旨之情況下，即包含於本發明之範圍。Further, in the semiconductor device and the method of manufacturing the same according to the embodiment of the present invention, the semiconductor device and the method of manufacturing the same obtained by an appropriate design change are included in the present invention as long as the gist of the present invention is included. The scope.
另外，於本發明之思想範疇內，業者想到之各種變更例及修正例，彼等變更例及修正例亦包含於本發明之範圍。例如對上述各實施形態，業者進行適當之構成要素追加、消除或設計變更，或進行工程之追加、省略、或條件變更者，只要具備本發明之要旨者，即包含於本發明之範圍。Further, various modifications and modifications of the invention are intended to be included within the scope of the invention. For example, in the above embodiments, the addition, elimination, or design change of an appropriate component, or the addition, omission, or change of conditions of the present invention is included in the scope of the present invention as long as it has the gist of the present invention.
11．．．半導體元件11. . . Semiconductor component
43．．．電極43. . . electrode
44．．．電極44. . . electrode
50．．．半導體晶圓50. . . Semiconductor wafer
82．．．第1外部電極82. . . First external electrode
83．．．第2外部電極83. . . Second external electrode
70．．．密封部70. . . Sealing part
70A．．．第1密封部70A. . . First seal
70B．．．第2密封部70B. . . Second seal
82C．．．鍍層82C. . . Plating
82B．．．第1引線82B. . . First lead
82A．．．凸部82A. . . Convex
83A．．．凸部83A. . . Convex
83B．．．第2引線83B. . . Second lead
83C．．．鍍層83C. . . Plating
85．．．溝85. . . ditch
87．．．切割片87. . . Cutting piece
86．．．導電片86. . . Conductive sheet
88．．．導電片88. . . Conductive sheet
90．．．孔90. . . hole
91．．．種層91. . . Seed layer
92．．．阻劑92. . . Resistor
94．．．導電片94. . . Conductive sheet
圖1(a)～(b)為本發明第1實施形態之半導體裝置之模式圖。1(a) to 1(b) are schematic views showing a semiconductor device according to a first embodiment of the present invention.
圖2為第1實施形態之半導體裝置之製造方法之例示之流程圖。Fig. 2 is a flow chart showing an example of a method of manufacturing the semiconductor device of the first embodiment.
圖3(a)～(b)為第1實施形態之半導體裝置之製造方法之例示之工程圖。3(a) to 3(b) are diagrams showing an example of a method of manufacturing the semiconductor device of the first embodiment.
圖4(a)～(g)為第1電施形態之半導體裝置之製造方法之例示之工程圖，係接續圖3(b)之圖。4(a) to 4(g) are diagrams showing an example of a method of manufacturing a semiconductor device of the first embodiment, which is a view subsequent to Fig. 3(b).
圖5為第1實施形態之另一半導體裝置之模式圖。Fig. 5 is a schematic view showing another semiconductor device of the first embodiment.
圖6(a)～(c)為第1實施形態之半導體裝置之變形例之製造方法之例示之工程圖。6(a) to 6(c) are diagrams showing an example of a manufacturing method of a modification of the semiconductor device of the first embodiment.
圖7為第2實施形態之半導體裝置之製造方法之例示之流程圖。Fig. 7 is a flow chart showing an example of a method of manufacturing a semiconductor device according to a second embodiment.
圖8(a)～(h)為第2實施形態之半導體裝置之製造方法之例示之工程圖。8(a) to 8(h) are diagrams showing an example of a method of manufacturing a semiconductor device according to a second embodiment.
圖9為第3實施形態之半導體裝置之另一製造方法之例示之流程圖。Fig. 9 is a flow chart showing an example of another manufacturing method of the semiconductor device of the third embodiment.
圖10(a)～(f)為第3實施形態之半導體裝置之製造方法之例示之工程圖。10(a) to 10(f) are diagrams showing an example of a method of manufacturing a semiconductor device according to a third embodiment.
圖11(a)～(e)為第3實施形態之半導體裝置之製造方法之例示之工程圖，圖11(a)為接續圖10(f)之圖。11(a) to 11(e) are diagrams showing an example of a method of manufacturing a semiconductor device according to a third embodiment, and Fig. 11(a) is a view subsequent to Fig. 10(f).
圖12(a)～(f)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。12(a) to 12(f) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
圖13(a)～(d)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。13(a) to 13(d) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
圖14(a)～(b)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。14(a) to 14(b) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
圖15(a)～(b)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。15(a) to 15(b) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
圖16(a)～(c)為第3實施形態之半導體裝置之另一製造方法之例示之工程圖。16(a) to 16(c) are diagrams showing an example of another manufacturing method of the semiconductor device of the third embodiment.
圖17為第4實施形態之另一半導體裝置之模式圖。Fig. 17 is a schematic view showing another semiconductor device of the fourth embodiment.
圖18為本發明實施形態之半導體裝置之裝配狀態之例示之模式圖。Fig. 18 is a schematic view showing an example of an assembled state of a semiconductor device according to an embodiment of the present invention.
圖19為本發明實施形態之半導體裝置之裝配狀態之變形例之模式斜視圖。Fig. 19 is a schematic perspective view showing a modification of the assembled state of the semiconductor device according to the embodiment of the present invention.
圖20為本發明實施形態之另一半導體裝置之裝配狀態之例之模式斜視圖。Fig. 20 is a schematic perspective view showing an example of an assembled state of another semiconductor device according to an embodiment of the present invention.
82C．．．鍍層82C. . . Plating
82B．．．第1引線82B. . . First lead
82A．．．凸部82A. . . Convex
70(70A)．．．密封部70 (70A). . . Sealing part
11．．．半導體元件11. . . Semiconductor component
83B．．．第2引線83B. . . Second lead
83C．．．鍍層83C. . . Plating
| Application Number | Priority Date | Filing Date | Title |
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| JP2009058708AJP2010056517A (en) | 2008-07-28 | 2009-03-11 | Semiconductor apparatus and method for manufacturing the same |
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| TW201044521A TW201044521A (en) | 2010-12-16 |
| TWI438879Btrue TWI438879B (en) | 2014-05-21 |
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| TW099101953ATWI438879B (en) | 2009-03-11 | 2010-01-25 | Semiconductor device and manufacturing method thereof |
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