本發明係相關於光電轉換裝置，尤其是相關於包括薄膜電晶體元件之光電轉換裝置，及設置有光電轉換裝置的電子裝置。The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device including a thin film transistor element, and an electronic device provided with the photoelectric conversion device.
已知有許多通常用於偵測電磁波之光電轉換裝置。例如，對紫外線到紅外線的光具有靈敏度之光電轉換裝置通常被稱作光學感測器。在其中，特別將在具有波長400至700nm的可見光區具有靈敏度之光學感測器稱作可見光感測器，及許多可見光感測器被用於依據人類環境而需要照度調整、開/關控制等之裝置。Many photoelectric conversion devices commonly used for detecting electromagnetic waves are known. For example, a photoelectric conversion device that is sensitive to ultraviolet to infrared light is generally referred to as an optical sensor. Among them, an optical sensor having sensitivity in a visible light region having a wavelength of 400 to 700 nm is called a visible light sensor, and many visible light sensors are used for illumination adjustment, on/off control, etc. depending on a human environment. Device.
在一些顯示裝置中，偵測顯示裝置的周遭亮度以調整顯示亮度。這是因為藉由以光學感測器偵測周遭亮度以及獲得適當的顯示亮度，而可降低顯示裝置不必要的電力。例如，具有用以調整亮度的光學感測器之顯示裝置的例子包括行動電話和電腦。In some display devices, the ambient brightness of the display device is detected to adjust the display brightness. This is because the unnecessary power of the display device can be reduced by detecting the ambient brightness with an optical sensor and obtaining an appropriate display brightness. For example, examples of display devices having optical sensors for adjusting brightness include a mobile phone and a computer.
此外，不僅周遭亮度而且顯示器的亮度，尤其是，液晶顯示裝置的背光之亮度係由光學感測器偵測，藉以調整顯示螢幕的亮度。In addition, not only the ambient brightness but also the brightness of the display, in particular, the brightness of the backlight of the liquid crystal display device is detected by the optical sensor, thereby adjusting the brightness of the display screen.
在光學感測器中，諸如光電二極體等光電轉換元件被用於光感測部分，及在放大器電路中放大光電轉換元件的輸出電流。例如，使用電流鏡電路當作光學感測器之放大器電路(例如，見參考文件1：日本專利號碼3444093)。In the optical sensor, a photoelectric conversion element such as a photodiode is used for the light sensing portion, and an output current of the photoelectric conversion element is amplified in the amplifier circuit. For example, a current mirror circuit is used as an amplifier circuit of an optical sensor (for example, see Reference 1: Japanese Patent No. 3444093).
參考文件1所示之光學感測器可利用放大光電流用的電路來偵測弱光。然而，當偵測弱光至強光時，輸出電流的範圍變得較廣，及在由外部負載電阻器等將輸出電流轉換成電壓時，輸出電壓與照度呈線性比例增加。因此，當獲得有關範圍廣的照度之輸出電壓時，有關照度的輸出電壓對弱光而言是幾mV,及對強光而言是幾V。因此，具有無法獲得廣泛動態範圍之問題。The optical sensor shown in Reference 1 can use a circuit for amplifying the photocurrent to detect weak light. However, when detecting weak light to strong light, the range of the output current becomes wider, and when the output current is converted into a voltage by an external load resistor or the like, the output voltage increases linearly with the illuminance. Therefore, when an output voltage with a wide range of illuminance is obtained, the output voltage of the illuminance is a few mV for weak light and a few V for strong light. Therefore, there is a problem that a wide dynamic range cannot be obtained.
為了解決上述問題，本發明的光電轉換裝置藉由平行設置通道長度L對通道寬度W之比，α=W/L，彼此不同的複數電晶體當作放大光電流之電流鏡電路的輸出側上之電晶體(下面稱作輸出側電晶體)，而使可應用照度範圍能夠加寬。In order to solve the above problem, the photoelectric conversion device of the present invention is configured by parallelly setting the ratio of the channel lengthL to the channel widthW , α =W/L , and the complex transistors different from each other are regarded as the output side of the current mirror circuit for amplifying the photocurrent. The transistor (hereinafter referred to as the output side transistor) allows the applicable illumination range to be widened.
在本發明的光電轉換裝置中，平行設置通道長度L對通道寬度W之比，α=W/L，彼此不同的複數電晶體當作放大光電流之電流鏡電路的輸出側上之電晶體。當內部電阻器串聯連接到各個輸出側電晶體，並且輸出流經複數電晶體之內部電阻器的電流總和時，可在直線區中以低照度驅動具有大量α之電晶體，及在直線區中以高照度驅動具有少量α之電晶體；藉由使用此，本發明的光電轉換裝置能夠具有較廣的可應用照度範圍。In the photoelectric conversion device of the present invention, the ratio of the channel lengthL to the channel widthW , α =W/L , is set in parallel, and the plurality of transistors different from each other are used as the transistors on the output side of the current mirror circuit for amplifying the photocurrent. When an internal resistor is connected in series to each of the output side transistors, and the current flowing through the internal resistors of the plurality of transistors is output, the transistor having a large amount of α can be driven in a linear region with low illumination, and in a straight line region The transistor having a small amount of α is driven with high illuminance; by using this, the photoelectric conversion device of the present invention can have a wide range of applicable illuminance.
下面，將參考圖式說明本發明的實施例模式。然而，可在許多模式中具體實現本發明，精於本技藝之人士應明白，只要不違背本發明的範疇和精神，可各式各樣地改變模式和細節。因此，本發明並不應侷限於下面的實施例模式之說明。在用於說明實施例模式的所有圖式中，可以相同參考號碼表示具有類似功能的部位或相同部位，並且省略其重複說明。Hereinafter, an embodiment mode of the present invention will be described with reference to the drawings. However, the present invention may be embodied in a number of modes, and those skilled in the art will appreciate that the modes and details can be varied in various ways without departing from the scope and spirit of the invention. Therefore, the present invention should not be limited to the description of the following embodiment modes. In all the drawings for explaining the mode of the embodiment, the same reference numerals are used to denote the parts having the similar functions or the same parts, and the repeated description thereof is omitted.
需注意的是，因為電晶體的結構所以難以清楚區分源極電極和汲極電極。另外，在某些例子中，依據電路的操作而切換電位的位準。因此，在此說明書中，源極電極和汲極電極各個被稱作第一電極或第二電極而不作特別的識別。例如，當第一電極是源極電極時，第二電極意指汲極電極，反之，當第一電極是汲極電極時，第二電極意指源極電極。It should be noted that it is difficult to clearly distinguish the source electrode and the drain electrode due to the structure of the transistor. Additionally, in some examples, the level of the potential is switched depending on the operation of the circuit. Therefore, in this specification, the source electrode and the drain electrode are each referred to as a first electrode or a second electrode without special recognition. For example, when the first electrode is a source electrode, the second electrode means a drain electrode, and conversely, when the first electrode is a drain electrode, the second electrode means a source electrode.
需注意的是，此說明書中的”連接”與”電連接”同義。因此，在本發明所揭示之結構中，除了預定的連接關係之外，亦可配置能夠在其間電連接之其他元件(例如，另一元件或開關)。It should be noted that the "connection" in this specification is synonymous with "electrical connection". Therefore, in the structure disclosed in the present invention, in addition to the predetermined connection relationship, other elements (e.g., another element or switch) capable of being electrically connected therebetween may be disposed.
將參考附圖說明此實施例模式。圖1為本發明的實施例模式1中之光電轉換裝置的電路組態圖。This embodiment mode will be explained with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit configuration diagram of a photoelectric conversion device in Embodiment Mode 1 of the present invention.
此實施例模式中的光電轉換裝置包括光電轉換元件103；電流鏡電路101，其為用以放大來自光電轉換元件103的輸出電流(又稱作光電流)之放大器電路；三內部電阻器106a至106c；負載電阻器107；高電位測電力供應線108；低電位測電力供應線109；及輸出終端110。電流鏡電路101包括參考側電晶體104和三輸出側電晶體105a至105c。The photoelectric conversion device in this embodiment mode includes a photoelectric conversion element 103; a current mirror circuit 101 which is an amplifier circuit for amplifying an output current (also referred to as photocurrent) from the photoelectric conversion element 103; three internal resistors 106a to 106c; load resistor 107; high potential power supply line 108; low potential power supply line 109; and output terminal 110. The current mirror circuit 101 includes a reference side transistor 104 and three output side transistors 105a to 105c.
需注意的是，在圖1中，參考側電晶體104和輸出側電晶體105a至105c是p通道場效電晶體。It is to be noted that, in FIG. 1, the reference side transistor 104 and the output side transistors 105a to 105c are p-channel field effect transistors.
需注意的是，在此說明書中，以VDD表示高電位側上的電力供應電位，以VSS表示低電位側上的電力供應電位。It is to be noted that, in this specification, the power supply potential on the high potential side is represented by VDD, and the power supply potential on the low potential side is represented by VSS.
在圖1中，將參考側電晶體104的第一電極和閘極電極彼此二極體連接。參考側電晶體104的第一電極連接到光電轉換元件103的陰極，參考側電晶體104的閘極電極連接到三輸出側電晶體105a至105c的各個閘極電極，及參考側電晶體104的第二電極連接到高電位側電力供應線108。In FIG. 1, the first electrode and the gate electrode of the reference side transistor 104 are connected to each other in a diode. The first electrode of the reference side transistor 104 is connected to the cathode of the photoelectric conversion element 103, the gate electrode of the reference side transistor 104 is connected to the respective gate electrodes of the three output side transistors 105a to 105c, and the reference side transistor 104 The second electrode is connected to the high potential side power supply line 108.
輸出側電晶體105a的第一電極連接到內部電阻器106a的一終端，及輸出側電晶體105a的第二電極連接到高電位側電力供應線108。內部電阻器106a的另一終端連接到負載電阻器107的一終端。在此說明書中，串聯連接輸出側電晶體105a和內部電阻器106a之電路被稱作輸出產生電路102a。The first electrode of the output side transistor 105a is connected to one terminal of the internal resistor 106a, and the second electrode of the output side transistor 105a is connected to the high potential side power supply line 108. The other terminal of the internal resistor 106a is connected to a terminal of the load resistor 107. In this specification, a circuit that connects the output side transistor 105a and the internal resistor 106a in series is referred to as an output generating circuit 102a.
以類似方式，輸出側電晶體105b的第一電極連接到內部電阻器106b的一終端，及輸出側電晶體105b的第二電極連接到高電位側電力供應線108。內部電阻器106b的另一終端連接到負載電阻器107的一終端。在此說明書中，串聯連接輸出側電晶體105b和內部電阻器106b之電路被稱作輸出產生電路102b。In a similar manner, the first electrode of the output side transistor 105b is connected to one terminal of the internal resistor 106b, and the second electrode of the output side transistor 105b is connected to the high potential side power supply line 108. The other terminal of the internal resistor 106b is connected to a terminal of the load resistor 107. In this specification, a circuit in which the output side transistor 105b and the internal resistor 106b are connected in series is referred to as an output generating circuit 102b.
以類似方式，輸出側電晶體105c的第一電極連接到內部電阻器106c的一終端，及輸出側電晶體105c的第二電極連接到高電位側電力供應線108。內部電阻器106c的另一終端連接到負載電阻器107的一終端。在此說明書中，串聯連接輸出側電晶體105c和內部電阻器106c之電路被稱作輸出產生電路102c。In a similar manner, the first electrode of the output side transistor 105c is connected to one terminal of the internal resistor 106c, and the second electrode of the output side transistor 105c is connected to the high potential side power supply line 108. The other terminal of the internal resistor 106c is connected to a terminal of the load resistor 107. In this specification, a circuit in which the output side transistor 105c and the internal resistor 106c are connected in series is referred to as an output generating circuit 102c.
負載電阻器107的一終端連接到輸出終端110。光電轉換元件103的陽極和負載電阻器107的另一終端連接到低電位側電力供應線109。A terminal of the load resistor 107 is connected to the output terminal 110. The anode of the photoelectric conversion element 103 and the other terminal of the load resistor 107 are connected to the low potential side power supply line 109.
接著，將說明此實施例模式的光電轉換裝置之操作。Next, the operation of the photoelectric conversion device of this embodiment mode will be explained.
光電轉換元件103輸出對應於入射在光電轉換元件103上之光的照度之光電流。當照度增加時，來自光電轉換元件103的光電流輸出增加。當來自光電轉換元件103的光電流輸出流到參考側電晶體104，在參考側電晶體104的閘極和源極之間形成電位差。在各個輸出側電晶體105a至105c的閘極和源極之間施加電位差。在電流鏡電路101中，將相同電壓施加到參考側電晶體104和輸出側電晶體105a至105c之閘極電極，使得能夠利用已流經參考側電晶體104的光電流當作參考來控制流經輸出側電晶體105a至105c之電流。The photoelectric conversion element 103 outputs a photocurrent corresponding to the illuminance of the light incident on the photoelectric conversion element 103. When the illuminance is increased, the photocurrent output from the photoelectric conversion element 103 is increased. When the photocurrent output from the photoelectric conversion element 103 flows to the reference side transistor 104, a potential difference is formed between the gate and the source of the reference side transistor 104. A potential difference is applied between the gate and the source of each of the output side transistors 105a to 105c. In the current mirror circuit 101, the same voltage is applied to the gate electrodes of the reference side transistor 104 and the output side transistors 105a to 105c, so that the flow can be controlled by using the photocurrent that has flowed through the reference side transistor 104 as a reference. The current through the output side transistors 105a to 105c.
根據光電流的電流流經輸出側電晶體105a至105c，藉以在輸出產生電路102a至102c中產生輸出電流。稍後將說明輸出產生電路102a至102c的操作。由複數輸出產生電路102a至102c所產生之輸出電流的總和流經負載電阻器107。因此，在負載電阻器107的終端之間形成電位差。當電位差是VRL及輸出電壓是Vout時，從輸出終端110輸出Vout=VRL+VSS。A current according to the photocurrent flows through the output side transistors 105a to 105c, thereby generating an output current in the output generating circuits 102a to 102c. The operations of the output generating circuits 102a to 102c will be described later. The sum of the output currents generated by the complex output generating circuits 102a to 102c flows through the load resistor 107. Therefore, a potential difference is formed between the terminals of the load resistor 107. When the potential difference isVRL and the output voltage isVout ,Vout =VRL + VSS is output from the output terminal 110.
接著，將參考圖2至4說明輸出產生電路102a至102c的操作。Next, the operations of the output generating circuits 102a to 102c will be explained with reference to Figs.
圖2為輸出產生電路102a的結構圖。將輸出側電晶體105a和內部電阻器106a串聯連接。根據光電流所產生之閘極電壓被施加到輸出側電晶體105a的閘極電極。以Vgate表示閘極電壓。此外，內部電阻器106a的第二電極之電位是輸出電位Vout。FIG. 2 is a structural diagram of the output generating circuit 102a. The output side transistor 105a and the internal resistor 106a are connected in series. A gate voltage generated according to the photocurrent is applied to the gate electrode of the output side transistor 105a. Thegate voltage is represented byVgate . Further, the potential of the second electrode of the internal resistor 106a is the output potentialVout .
圖3圖示輸出側電晶體105a和內部電阻器106a的電壓電流特性，其中流經輸出產生電路102a的電流是I，及輸出側電晶體105a和內部電阻器106a之間的連接部位之電位是V。在圖3中，垂直軸表示電流，而水平軸表示電壓。在圖3中，曲線301表示具有照度L1之光(單位：lux)入射在光電轉換元件上時之輸出側電晶體105a的電壓電流特性。曲線302表示具有照度L2(L1<L2)之光入射在光電轉換元件上時之輸出側電晶體105a的電壓電流特性。此外，直線303表示內部電阻器106a的電壓電流特性。利用對應於表示輸出側電晶體105a的電壓電流特性之曲線和內部電阻器106a的電壓電流特性之直線的交點(此被稱作操作點)之電壓V和電流I來操作輸出產生電路102a。3 illustrates voltage and current characteristics of the output side transistor 105a and the internal resistor 106a, in which the current flowing through the output generating circuit 102a isI , and the potential of the connection portion between the output side transistor 105a and the internal resistor 106a isV. In Figure 3, the vertical axis represents current and the horizontal axis represents voltage. In Figure 3, curve 301 represents the illumination lightL1 (unit: lux) having a voltage-current characteristic is incident upon the output side of the transistor 105a on the photoelectric conversion element. A curve 302 indicates a voltage current characteristic of the output side transistor 105a when light having an illuminanceL2 (L1 <L2 ) is incident on the photoelectric conversion element. Further, a line 303 represents the voltage current characteristics of the internal resistor 106a. The output generating circuit 102a is operated by the voltageV and the currentI corresponding to the intersection of the line representing the voltage-current characteristic of the output side transistor 105a and the line of the voltage-current characteristic of the internal resistor 106a (referred to as an operating point).
當具有照度L1之光進入時，輸出側電晶體105a具有曲線301所示之電壓電流特性，及輸出產生電路102a的操作點是曲線301和直線303的交點之點304。然後，電流I1流經輸出產生電路102a。When light having a luminanceL1 enters the output-side transistor 105a having a voltage-current characteristic shown in the curve 301, and the output operating point generating circuit 102a and line 301 is a curve 303 of the intersection point 304. Then, the currentI1 flows through the output generating circuit 102a.
那時，在飽和範圍中操作輸出側電晶體105a。飽和範圍是閘極和源極之間的電壓VGS，汲極和源極之間的電壓VDS，及輸出側電晶體105a的臨界電壓VTH之大小關係是∣VGS-VTH∣<∣VDS∣之範圍。在此範圍中，只依據輸出側電晶體105a的閘極和源極之間的電壓VGS之電流流經輸出側電晶體105a。因此，與照度成比例之電流流經輸出產生電路102a。At that time, the output side transistor 105a is operated in the saturation range. The saturation range is the voltageV GS between the gate and the source, the voltageV DS between the drain and the source, and the magnitude of the threshold voltageV TH of the output side transistor 105a is ∣V GS -V TH ∣ ∣V DS∣ range. In this range, a current of only the voltageV GS between the gate and the source of the output side transistor 105a flows through the output side transistor 105a. Therefore, a current proportional to the illuminance flows through the output generating circuit 102a.
在具有高於照度L1之照度的光進入時，當照度是在輸出側電晶體105a操作於飽和範圍中之範圍內時，與照度成比例之電流流經輸出產生電路102a。When light enters the above having luminanceL1 of illumination when illumination is on the output side of the transistor 105a operates in the saturation range in the scope of the generating circuit 102a and the current flowing through the output is proportional to the illuminance.
在進一步增加照度並且具有照度L2的光進入時，輸出側電晶體105a具有曲線302所示之電壓電流特性。那時，輸出產生電路102a的操作點是點305及電流I2流經輸出產生電路102a。The output side transistor 105a has a voltage current characteristic shown by a curve 302 when light having a further illuminance and having an illuminanceL2 is entered. At that time, the operating point of the output generating circuit 102a is point 305 and currentI2 flows through the output generating circuit 102a.
那時，在直線範圍中操作輸出側電晶體105a。直線範圍是閘極和源極之間的電壓VGS，汲極和源極之間的電壓VDS，及輸出側電晶體105a的臨界電壓VTH之大小關係是∣VGS-VTH∣>∣VDS∣之範圍。在此範圍中，依據輸出側電晶體105a的閘極和源極之間的電壓VGS和汲極和源極之間的電壓VDS之電流流經輸出側電晶體105a。因此，流經輸出產生電路102a的電流未與照度成比例，及逐漸變得更接近Imax。需注意的是，以(VDD-Vout)/Ri表示Imax。需注意的是，Ri是內部電阻器106的電阻值。At that time, the output side transistor 105a is operated in a straight line range. The linear range is the voltageV GS between the gate and the source, the voltageV DS between the drain and the source, and the magnitude of the threshold voltageV TH of the output side transistor 105a is ∣V GS-V TH∣> ∣V DS∣ range. In this range, a current according to the voltageV GS between the gate and the source of the output side transistor 105a and the voltageV DS between the drain and the source flows through the output side transistor 105a. Therefore, the current flowing through the output generating circuit 102a is not proportional to the illuminance, and gradually becomes closer toI max . It should be noted thatI max is represented by (VDD -V out) /R i . It should be noted thatR i is the resistance value of the internal resistor 106.
此處，圖4圖示輸出產生電路102a的照度電流特性。在圖4中，水平軸表示照度，而垂直軸表示流經輸出產生電路102a的電流。以對數刻度表示它們二者。Here, FIG. 4 illustrates the illuminance current characteristic of the output generating circuit 102a. In FIG. 4, the horizontal axis represents illuminance, and the vertical axis represents current flowing through the output generating circuit 102a. Both are represented on a logarithmic scale.
如上述，當照度是在輸出側電晶體105a於飽和範圍中操作之範圍內時(例如，照度L1)，與照度成比例的電流流經輸出產生電路102a。另一方面，當照度是在輸出側電晶體105a於直線範圍中操作之範圍內時(例如，照度L2)，流經輸出產生電路102a之電流未與照度成比例，及逐漸變得更接近Imax。As described above, when the illuminance is within the range in which the output side transistor 105a operates in the saturation range (for example, the illuminanceL1 ), a current proportional to the illuminance flows through the output generating circuit 102a. On the other hand, when the illuminance is within the range in which the output side transistor 105a operates in the linear range (for example, the illuminanceL2 ), the current flowing through the output generating circuit 102a is not proportional to the illuminance, and gradually becomes closer.I max.
雖然到目前為止已說明輸出產生電路102a，但是輸出產生電路102b和輸出產生電路102c亦以類似方式來操作。Although the output generation circuit 102a has been explained so far, the output generation circuit 102b and the output generation circuit 102c also operate in a similar manner.
接著，將再次說明此實施例模式的光電轉換裝置之操作。在此實施例模式的光電轉換裝置中，執行上述操作之複數輸出產生電路被並聯連接。此處，將說明如圖1所示之並聯連接三輸出產生電路102a至102c時的電路之操作。Next, the operation of the photoelectric conversion device of this embodiment mode will be described again. In the photoelectric conversion device of this embodiment mode, the complex output generating circuits that perform the above operations are connected in parallel. Here, the operation of the circuit when the three-output generating circuits 102a to 102c are connected in parallel as shown in FIG. 1 will be explained.
在三輸出產生電路102a至102c中，使輸出側電晶體105a至105c的通道長度L對通道寬度W之比，α=W/L，彼此不同。例如，第一輸出側電晶體105a的α是α1，第二輸出側電晶體105b的α是α2，及第三輸出側電晶體105c的α是α3。其大小關係是α1>α2>α3。較佳的是，α被設定如下：α1/α2=約10及α2/α3=約10。In the three output generating circuits 102a to 102c, the ratio of the channel lengthL of the output side transistors 105a to 105c to the channel widthW , α =W/L , is made different from each other. For example, α of the first output side transistor 105a is α1 , α of the second output side transistor 105b is α2 , and α of the third output side transistor 105c is α3 . Its size relationship is α1 >α2 >α3 . Preferably, α is set as follows: α1 /α2 = about 10 and α2 /α3 = about 10.
需注意的是，為了方便說明，內部電阻器106a至106c的電阻值被設定成相同的。然而，內部電阻器106a至106c的電阻值並不侷限於此，而可以是彼此不同的。It should be noted that the resistance values of the internal resistors 106a to 106c are set to be the same for convenience of explanation. However, the resistance values of the internal resistors 106a to 106c are not limited thereto, but may be different from each other.
圖5A至5C圖解那例子中的圖1所示之電路的操作。圖5A圖示輸出產生電路102a至102c的照度電流特性。在圖5A中，水平軸表示照度，而垂直軸表示流經輸出產生電路102a至102c之電流。以對數刻度表示它們二者。5A to 5C illustrate the operation of the circuit shown in Fig. 1 in that example. FIG. 5A illustrates illuminance current characteristics of the output generating circuits 102a to 102c. In Fig. 5A, the horizontal axis represents illuminance, and the vertical axis represents current flowing through the output generating circuits 102a to 102c. Both are represented on a logarithmic scale.
需注意的是，曲線501a表示第一輸出產生電路102a的照度電流特性，曲線501b表示第二輸出產生電路102b的照度電流特性，及曲線501c表示第三輸出產生電路102c的照度電流特性。It is to be noted that the curve 501a represents the illuminance current characteristic of the first output generating circuit 102a, the curve 501b represents the illuminance current characteristic of the second output generating circuit 102b, and the curve 501c represents the illuminance current characteristic of the third output generating circuit 102c.
在輸出產生電路102a至102c中，當輸出側電晶體105a至105c之α變得較大時，能夠以較低照度在直線範圍中驅動輸出側電晶體105a至105c，因為各個輸出側電晶體105a至105c串聯連接到內部電阻器106a至106c的其中之一個。因此，當輸出側電晶體105a至105c之α變得較大時，以更低的照度，流經輸出產生電路102a至102c的電流擊中峰值。In the output generating circuits 102a to 102c, when α of the output side transistors 105a to 105c becomes larger, the output side transistors 105a to 105c can be driven in a linear range with lower illuminance because the respective output side transistors 105a Up to 105c is connected in series to one of the internal resistors 106a to 106c. Therefore, when α of the output side transistors 105a to 105c becomes larger, the current flowing through the output generating circuits 102a to 102c hits a peak with a lower illuminance.
流經輸出產生電路102a至102c之電流的總和是此實施例模式的光電轉換裝置之輸出電流(以Iout表示輸出電流)。然後輸出電流流經負載電阻器107，及在負載電阻器107中所產生的電位差和VSS之總和被輸出當作輸出電壓Vout。The sum of the currents flowing through the output generating circuits 102a to 102c is the output current of the photoelectric conversion device of this embodiment mode (the output current is represented byI out). The output current then flows through the load resistor 107, and the sum of the potential difference generated in the load resistor 107 and VSS is output as the output voltageVout .
此處，在圖5B圖示流經輸出產生電路102a至102c之電流的總和(輸出電流)。此外，在圖5C圖示輸出電壓Vout。在圖5B及5C中，水平軸表示以對數刻度顯示之照度，而垂直軸表示以直線刻度表示之輸出電流或輸出電壓。Here, the sum (output current) of the currents flowing through the output generating circuits 102a to 102c is illustrated in FIG. 5B. Further, the output voltageV out is illustrated in FIG. 5C. In FIGS. 5B and 5C, the horizontal axis represents the illuminance displayed on a logarithmic scale, and the vertical axis represents the output current or output voltage expressed in a linear scale.
因為輸出電流Iout是流經輸出產生電路102a至102c之電流的總和，所以輸出電流Iout具有幾乎與圖5B所示之照度的對數成比例之特性。此外，輸出電壓Vout亦具有幾乎與照度的對數成比例之特性。Since the output currentI out is the sum of the currents flowing through the output generating circuits 102a to 102c, the output currentI out has a characteristic which is almost proportional to the logarithm of the illuminance shown in Fig. 5B. In addition, the output voltageVout also has a characteristic that is almost proportional to the logarithm of the illuminance.
以此方式，在此實施例模式的光電轉換裝置，能夠獲得幾乎與照度的對數成比例之輸出，並且能夠加寬可應用到光電轉換裝置的照度範圍。In this way, in the photoelectric conversion device of this embodiment mode, it is possible to obtain an output which is almost proportional to the logarithm of the illuminance, and it is possible to widen the illuminance range applicable to the photoelectric conversion device.
雖然在圖1所示之電路中並聯三個連接輸出產生電路，但是只要設置複數輸出產生電路，輸出產生電路的數目並不侷限於此。藉由增加輸出產生電路的數目，能夠加寬可應用到光電轉換裝置的照度範圍，並且能夠使有關照度的輸入之變化變小。Although three connection output generating circuits are connected in parallel in the circuit shown in Fig. 1, as long as the complex output generating circuit is provided, the number of output generating circuits is not limited thereto. By increasing the number of output generating circuits, it is possible to widen the range of illuminance applicable to the photoelectric conversion device, and it is possible to make the change in the input relating to illuminance small.
需注意的是，負載電阻器107可結合在光電轉換裝置內，或者可裝附諸如晶片電阻器等外部電阻器當作負載電阻器107。當負載電阻器107結合在光電轉換裝置內時，不需要外部電阻器，藉以可減少用以連接外部電阻器之步驟和部分的數目。此外，因為不需要用於外部電阻器的區域，所以可使電子裝置的光電轉換部位之區域變小。另一方面，當負載電阻器107是外部電阻器時，能夠抑制負載電阻變化的影響(尤其是，有關溫度的電阻變化)。It is to be noted that the load resistor 107 may be incorporated in the photoelectric conversion device, or an external resistor such as a wafer resistor may be attached as the load resistor 107. When the load resistor 107 is incorporated in the photoelectric conversion device, an external resistor is not required, whereby the number of steps and portions for connecting the external resistor can be reduced. Further, since the area for the external resistor is not required, the area of the photoelectric conversion portion of the electronic device can be made small. On the other hand, when the load resistor 107 is an external resistor, it is possible to suppress the influence of the change in the load resistance (in particular, the resistance change with respect to temperature).
雖然圖1所示之電路係由p通道電晶體所形成，但是亦可使用n通道電晶體。圖6圖示使用n通道電晶體的電路組態。Although the circuit shown in FIG. 1 is formed by a p-channel transistor, an n-channel transistor can also be used. Figure 6 illustrates the circuit configuration using an n-channel transistor.
圖6所示之光電轉換裝置包括光電轉換元件603；電流鏡電路601，其為用以放大來自光電轉換元件603的輸出電流(又稱作光電流)之放大器電路；三內部電阻器606a至606c；負載電阻器607；高電位測電力供應線608；低電位測電力供應線609；及輸出終端610。電流鏡電路601包括參考側電晶體604和三輸出側電晶體605a至605c。The photoelectric conversion device shown in FIG. 6 includes a photoelectric conversion element 603; a current mirror circuit 601 which is an amplifier circuit for amplifying an output current (also referred to as a photocurrent) from the photoelectric conversion element 603; and three internal resistors 606a to 606c. a load resistor 607; a high potential power supply line 608; a low potential power supply line 609; and an output terminal 610. The current mirror circuit 601 includes a reference side transistor 604 and three output side transistors 605a to 605c.
需注意的是，參考側電晶體604和輸出側電晶體605a至605c是圖6中的所有n通道場效電晶體。It is to be noted that the reference side transistor 604 and the output side transistors 605a to 605c are all n-channel field effect transistors in FIG.
需注意的是，以VDD表示高電位側上的電力供應電位，以VSS表示低電位側上的電力供應電位。It is to be noted that the power supply potential on the high potential side is represented by VDD, and the power supply potential on the low potential side is represented by VSS.
在圖6中，將參考側電晶體604的第一電極和閘極電極彼此二極體連接。參考側電晶體604的第一電極連接到光電轉換元件603的陽極，參考側電晶體604的閘極電極連接到三輸出側電晶體605a至605c的各個閘極電極，及參考側電晶體604的第二電極連接到低電位側電力供應線609。In FIG. 6, the first electrode and the gate electrode of the reference side transistor 604 are connected to each other in a diode. The first electrode of the reference side transistor 604 is connected to the anode of the photoelectric conversion element 603, the gate electrode of the reference side transistor 604 is connected to the respective gate electrodes of the three output side transistors 605a to 605c, and the reference side transistor 604 The second electrode is connected to the low potential side power supply line 609.
輸出側電晶體605a的第一電極連接到內部電阻器606a的一終端，及輸出側電晶體605a的第二電極連接到低電位側電力供應線609。內部電阻器606a的另一終端連接到負載電阻器607的一終端。在此說明書中，串聯連接輸出側電晶體605a和內部電阻器606a之電路被稱作輸出產生電路602a。The first electrode of the output side transistor 605a is connected to one terminal of the internal resistor 606a, and the second electrode of the output side transistor 605a is connected to the low potential side power supply line 609. The other terminal of internal resistor 606a is coupled to a terminal of load resistor 607. In this specification, a circuit in which the output side transistor 605a and the internal resistor 606a are connected in series is referred to as an output generating circuit 602a.
以類似方式，輸出側電晶體605b的第一電極連接到內部電阻器606b的一終端，及輸出側電晶體605b的第二電極連接到低電位側電力供應線609。內部電阻器606b的另一終端連接到負載電阻器607的一終端。在此說明書中，串聯連接輸出側電晶體605b和內部電阻器606b之電路被稱作輸出產生電路602b。In a similar manner, the first electrode of the output side transistor 605b is connected to one terminal of the internal resistor 606b, and the second electrode of the output side transistor 605b is connected to the low potential side power supply line 609. The other terminal of the internal resistor 606b is connected to a terminal of the load resistor 607. In this specification, a circuit in which the output side transistor 605b and the internal resistor 606b are connected in series is referred to as an output generating circuit 602b.
以類似方式，輸出側電晶體605c的第一電極連接到內部電阻器606c的一終端，及輸出側電晶體605c的第二電極連接到低電位側電力供應線609。內部電阻器606c的另一終端連接到負載電阻器607的一終端。在此說明書中，串聯連接輸出側電晶體605c和內部電阻器606c之電路被稱作輸出產生電路602c。In a similar manner, the first electrode of the output side transistor 605c is connected to one terminal of the internal resistor 606c, and the second electrode of the output side transistor 605c is connected to the low potential side power supply line 609. The other terminal of the internal resistor 606c is connected to a terminal of the load resistor 607. In this specification, a circuit that connects the output side transistor 605c and the internal resistor 606c in series is referred to as an output generating circuit 602c.
負載電阻器607的一終端連接到輸出終端610。光電轉換元件603的陰極和負載電阻器607的另一終端連接到高電位側電力供應線608。A terminal of the load resistor 607 is connected to the output terminal 610. The cathode of the photoelectric conversion element 603 and the other terminal of the load resistor 607 are connected to the high potential side power supply line 608.
圖6所示之電路的結構基本上類似於圖1所示之電路的結構，及執行基本上類似於圖1所示之電路操作的電路操作。圖1及圖6所示的電路之間的差是輸出電壓Vout。在圖6所示之電路的例子中，當負載電阻器607的終端之間的電位差是VRL時，從輸出中610輸出電壓Vout=VDD-VRL。The structure of the circuit shown in Figure 6 is substantially similar to the structure of the circuit shown in Figure 1, and performs circuit operations substantially similar to the circuit operation shown in Figure 1. The difference between the circuits shown in Figures 1 and 6 is the output voltageV out . In the example of the circuit shown in FIG. 6, when the potential difference between the terminals of the load resistor 607 isVRL , the voltageV out = VDD -VRL is output from the output 610.
此處，圖7A及7B圖示圖6所示之電路的輸出之照度特性。圖7A圖示輸出電流Iout的照度特性，及垂直軸表示輸出電流(直線刻度)和水平軸表示照度(對數刻度)。圖7B圖示輸出電壓Vout的照度特性，及垂直軸表示輸出電壓(直線刻度)和水平軸表示照度(對數刻度)。Here, FIGS. 7A and 7B illustrate the illuminance characteristics of the output of the circuit shown in FIG. Illumination characteristics 7A illustrates the output currentI out, and the vertical axis represents the output current (linear scale) and the horizontal axis represents luminance (logarithmic scale). Fig. 7B illustrates the illuminance characteristic of the output voltageVout , and the vertical axis represents the output voltage (linear scale) and the horizontal axis represents illuminance (logarithmic scale).
在圖1所示之電路中，當照度增加時，如圖5C所示一般，輸出電壓Vout增加。另一方面，在圖6所示之電路中，當照度增加，輸出電壓Vout減少。在任一例子中，輸出電流Iout具有幾乎與照度的對數成比例之特性。此外，輸出電壓Vout具有幾乎與照度的對數成比例之特性。In the circuit shown in Fig. 1, when the illuminance is increased, as shown in Fig. 5C, the output voltageVout is increased. On the other hand, in the circuit shown in Fig. 6, as the illuminance increases, the output voltageVout decreases. In either instance, the output currentI out characteristic has almost proportional to the logarithm of the illuminance of. Further, the output voltageV out has a characteristic that is almost proportional to the logarithm of the illuminance.
以此方式，在此實施例模式的光電轉換裝置中，可獲得幾乎與照度的對數成比例之輸出，及可加寬可應用到光電轉換裝置之照度範圍。In this way, in the photoelectric conversion device of this embodiment mode, an output which is almost proportional to the logarithm of the illuminance can be obtained, and the illuminance range applicable to the photoelectric conversion device can be widened.
雖然在圖6所示的電路中並聯連接三輸出產生電路，但是只要設置複數輸出產生電路，輸出產生電路的數目並不侷限於此。藉由增加輸出產生電路的數目，能夠加寬可應用到光電轉換裝置的照度範圍，及能夠使有關照度的輸出之變化變小。Although the three-output generating circuit is connected in parallel in the circuit shown in FIG. 6, the number of output generating circuits is not limited to this as long as the complex output generating circuit is provided. By increasing the number of output generating circuits, it is possible to widen the range of illuminance applicable to the photoelectric conversion device, and to make the change in the output of the illuminance smaller.
因為只由n通道電晶體或p通道電晶體形成此實施例模式所示之光電轉換裝置，所以能夠降低電晶體的製造步驟數目和成本。此外，可抑制由於製造處理所導致的電路特性之變化。Since the photoelectric conversion device shown in this embodiment mode is formed only by the n-channel transistor or the p-channel transistor, the number of manufacturing steps and cost of the transistor can be reduced. In addition, variations in circuit characteristics due to manufacturing processes can be suppressed.
當作此實施例模式所說明的光電轉換元件，能夠使用將光能轉換成電能之諸如一般光電二極體等元件。需注意的是，可利用各種類型的場效電晶體當作此實施例模式所說明之n通道電晶體和p通道電晶體。因此，對所使用的電晶體類型並無限制。例如，可利用包括以非晶矽為代表的非單晶半導體膜、微晶(又稱作半非晶)矽等之薄膜電晶體(TFT)。在使用TFT的例子中，具有各種優點。例如，因為可在低於使用單晶矽的例子之溫度的溫度中形成TFT，所以能夠減少製造成本，及能夠使製造設備較大。因為製造設備能夠是大的，所以可將TFT形成在大基板上。因此，能夠同時形成許多光電轉換裝置，製造成本低。此外，因為可在低溫中製造TFT，所以能夠使用具有低耐熱性的基板。因此，可將電晶體形成在光傳送基板上。因此，可藉由使用形成在光傳送基板上的電晶體來控制光電轉換元件中之光的傳輸。As the photoelectric conversion element explained in this embodiment mode, an element such as a general photodiode that converts light energy into electric energy can be used. It should be noted that various types of field effect transistors can be utilized as the n-channel transistors and p-channel transistors illustrated in this embodiment mode. Therefore, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) including a non-single crystal semiconductor film typified by amorphous germanium, microcrystals (also referred to as semi-amorphous) germanium, or the like can be used. In the example using TFT, there are various advantages. For example, since the TFT can be formed at a temperature lower than the temperature of the example using the single crystal germanium, the manufacturing cost can be reduced, and the manufacturing apparatus can be made large. Since the manufacturing equipment can be large, the TFT can be formed on a large substrate. Therefore, many photoelectric conversion devices can be formed at the same time, and the manufacturing cost is low. Further, since the TFT can be manufactured at a low temperature, a substrate having low heat resistance can be used. Therefore, a transistor can be formed on the light transmitting substrate. Therefore, the transmission of light in the photoelectric conversion element can be controlled by using a transistor formed on the light transmission substrate.
藉由在形成多晶矽時使用催化劑(如、鎳)，可進一步提高晶性，及可形成具有絕佳電特性的電晶體。因此，在同一基板上可形成在高速中操作的電路。藉由在形成微晶矽時使用催化劑(如、鎳)，可進一步提高晶性，及可形成具有絕佳電特性的電晶體。此時，藉由執行熱處理卻不必執行雷射照射就可提高晶性。在未將雷射用於結晶的例子中可抑制矽的晶性不均勻。因此，可抑制電晶體的特性之間的差。需注意的是，可在不使用催化劑(如、鎳)之下形成多晶矽和微晶矽。By using a catalyst (e.g., nickel) in the formation of polycrystalline germanium, crystallinity can be further improved, and a crystal having excellent electrical characteristics can be formed. Therefore, a circuit that operates at high speed can be formed on the same substrate. By using a catalyst (e.g., nickel) in the formation of microcrystalline germanium, crystallinity can be further improved, and a crystal having excellent electrical characteristics can be formed. At this time, crystallinity can be improved by performing heat treatment without performing laser irradiation. In the case where the laser is not used for crystallization, the crystal unevenness of ruthenium can be suppressed. Therefore, the difference between the characteristics of the transistors can be suppressed. It should be noted that polycrystalline germanium and microcrystalline germanium can be formed without the use of a catalyst such as nickel.
此外，可藉由使用半導體基板、SOI基板等來形成電晶體。因此，可形成具有特性、尺寸、形狀等變化少，具有高度電流供應能力，並且小尺寸之電晶體。藉由使用此種電晶體，可降低電路的電力消耗或可高度整合電路。Further, the transistor can be formed by using a semiconductor substrate, an SOI substrate, or the like. Therefore, it is possible to form a transistor having a small change in characteristics, size, shape, and the like, having a high current supply capability, and a small size. By using such a transistor, the power consumption of the circuit or the highly integrated circuit can be reduced.
另一選擇是，能夠使用包括諸如ZnO、a-InGaZnO、SiGe、GaAs、銦鋅氧化物(IZO)、銦錫氧化物(ITO)、或氧化錫(SnO)等化合物半導體或氧化物半導體之電晶體，藉由使此種化合物半導體或氧化物半導體變薄所獲得之薄膜電晶體等。因此，可降低製造溫度，及例如，可在室溫中形成此種電晶體。因此，可將電晶體直接形成在具有諸如塑膠基板或膜基板等低耐熱性的基板上。Alternatively, it is possible to use a compound semiconductor or oxide semiconductor including a ZnO, a-InGaZnO, SiGe, GaAs, indium zinc oxide (IZO), indium tin oxide (ITO), or tin oxide (SnO). A thin film transistor or the like obtained by thinning such a compound semiconductor or an oxide semiconductor. Therefore, the manufacturing temperature can be lowered, and, for example, such a crystal can be formed at room temperature. Therefore, the transistor can be formed directly on a substrate having low heat resistance such as a plastic substrate or a film substrate.
另一選擇是，亦可使用藉由使用噴墨法或印刷法所形成之電晶體。因此，可在室溫中形成，可在低真空中形成，或可在大基板上形成電晶體。此外，因為可在不使用遮罩(光罩)之下形成電晶體，所以可溶液地改變電晶體的佈局。另外，因為不需要使用抗蝕劑，所以可降低材料成本和可降低步驟數目。而且，因為只在必要部位形成膜，所以與在將膜形成於整個基板上之後執行蝕刻的製造方法相比，比較不浪費材料，如此可降低成本。Alternatively, a transistor formed by using an inkjet method or a printing method can also be used. Therefore, it can be formed at room temperature, can be formed in a low vacuum, or can form a transistor on a large substrate. Furthermore, since the transistor can be formed without using a mask (photomask), the layout of the transistor can be changed in solution. In addition, since the resist is not required, the material cost can be reduced and the number of steps can be reduced. Moreover, since the film is formed only at the necessary portion, the material is relatively wasted compared to the manufacturing method in which the etching is performed after the film is formed on the entire substrate, so that the cost can be reduced.
另一選擇是，可使用包括有機半導體或碳奈米管等之電晶體。因此，可使用能夠彎曲之基板來形成此種電晶體。因此，使用包括有機半導體或碳奈米管等的電晶體之裝置能夠抵抗撞擊。Alternatively, a transistor including an organic semiconductor or a carbon nanotube or the like can be used. Therefore, a substrate that can be bent can be used to form such a transistor. Therefore, a device using a transistor including an organic semiconductor or a carbon nanotube can resist impact.
各種類型的電晶體可用於場效電晶體，及可將電晶體形成在各種類型的基板上。因此，可將需要實現預定功能之所有電路形成在同一基板上。例如，可將需要實現預定功能之所有電路形成玻璃基板、塑膠基板、單晶基板、SOI基板上，或形成在各種基板上。藉由使用薄膜電晶體來形成場效電晶體，可將此實施例模式的光電轉換裝置形成在諸如玻璃基板等光傳送基板上。因此，在將光電轉換元件103或603形成於基板上之例子中，光電轉換元件103或603不僅可接收來自基板的一表面之光，而且可接收來自基板的背表面而經由基板傳送之光，藉以提高接收光的效能。Various types of transistors can be used for field effect transistors, and transistors can be formed on various types of substrates. Therefore, all circuits that need to implement a predetermined function can be formed on the same substrate. For example, all circuits that require a predetermined function can be formed on a glass substrate, a plastic substrate, a single crystal substrate, an SOI substrate, or formed on various substrates. The photoelectric conversion device of this embodiment mode can be formed on an optical transmission substrate such as a glass substrate by forming a field effect transistor using a thin film transistor. Therefore, in the example in which the photoelectric conversion element 103 or 603 is formed on the substrate, the photoelectric conversion element 103 or 603 can receive not only light from a surface of the substrate but also light transmitted from the back surface of the substrate via the substrate, In order to improve the performance of receiving light.
需注意的是，此實施例模式能夠與此說明書中的其他實施例模式之技術組件組合。It should be noted that this embodiment mode can be combined with the technical components of the other embodiment modes in this specification.
將參考圖式來說明此實施例模式。圖21圖解本發明的實施例模式2之光電轉換裝置的電路組態圖。This embodiment mode will be explained with reference to the drawings. Figure 21 is a circuit configuration diagram of a photoelectric conversion device of Embodiment Mode 2 of the present invention.
此實施例模式中的光電轉換裝置包括光電轉換元件103；第一電流鏡電路101和第二電流鏡電路211，其為用以放大來自光電轉換元件103的輸出電流(又稱作光電流)之放大器電路；三內部電阻器106a至106c；負載電阻器107；高電位測電力供應線108；低電位測電力供應線109；及輸出終端110。第一電流鏡電路101包括第一參考側電晶體104和三第一輸出側電晶體105a至105c。第二電流鏡電路211包括第二參考側電晶體212和第二輸出側電晶體213。The photoelectric conversion device in this embodiment mode includes a photoelectric conversion element 103; a first current mirror circuit 101 and a second current mirror circuit 211 for amplifying an output current (also referred to as photocurrent) from the photoelectric conversion element 103. An amplifier circuit; three internal resistors 106a to 106c; a load resistor 107; a high potential power supply line 108; a low potential power supply line 109; and an output terminal 110. The first current mirror circuit 101 includes a first reference side transistor 104 and three first output side transistors 105a to 105c. The second current mirror circuit 211 includes a second reference side transistor 212 and a second output side transistor 213.
在圖21中，所有第一參考側電晶體104和第一輸出側電晶體105a至105c都是p通道場效電晶體。第二參考側電晶體212和第二輸出側電晶體213二者都是n通道場效電晶體。In FIG. 21, all of the first reference side transistors 104 and the first output side transistors 105a to 105c are p-channel field effect transistors. Both the second reference side transistor 212 and the second output side transistor 213 are n-channel field effect transistors.
需注意的是，在此說明書中，以VDD表示高電位側上的電力供應電位，以VSS表示低電位側上的電力供應電位。It is to be noted that, in this specification, the power supply potential on the high potential side is represented by VDD, and the power supply potential on the low potential side is represented by VSS.
在圖21中，將第二參考側電晶體212的第一電極和閘極電極彼此二極體連接。將第二參考側電晶體212的第一電極連接到光電轉換元件103的陽極，第二參考側電晶體212的閘極電極連接到第二輸出側電晶體213的閘極電極，及第二參考側電晶體212的第二電極連接到低電位側電力供應線109。In FIG. 21, the first electrode and the gate electrode of the second reference side transistor 212 are connected to each other in a diode. The first electrode of the second reference side transistor 212 is connected to the anode of the photoelectric conversion element 103, the gate electrode of the second reference side transistor 212 is connected to the gate electrode of the second output side transistor 213, and the second reference The second electrode of the side transistor 212 is connected to the low potential side power supply line 109.
第二輸出側電晶體213的第一電極連接到第一參考側電晶體104的第一電極，及第二輸出側電晶體213的第二電極連接到低電位側電力供應線109。The first electrode of the second output side transistor 213 is connected to the first electrode of the first reference side transistor 104, and the second electrode of the second output side transistor 213 is connected to the low potential side power supply line 109.
第一參考側電晶體104的第一電極和閘極電極彼此二極體連接。第一參考側電晶體104的閘極電極連接到三第一輸出側電晶體105a至105c的各個閘極電極，及第一參考側電晶體104的第二電極連接到光電轉換元件103的陰極和高電位側電力供應線108。The first electrode and the gate electrode of the first reference side transistor 104 are connected to each other in a diode. The gate electrode of the first reference side transistor 104 is connected to each of the gate electrodes of the three first output side transistors 105a to 105c, and the second electrode of the first reference side transistor 104 is connected to the cathode of the photoelectric conversion element 103 and High potential side power supply line 108.
第一輸出側電晶體105a的第一電極連接到內部電阻器106a的一終端，及第一輸出側電晶體105a的第二電極連接到高電位側電力供應線108。內部電阻器106a的另一終端連接到負載電阻器107的一終端。在此說明書中，串聯連接第一輸出側電晶體105a和內部電阻器106a之電路被稱作輸出產生電路102a。The first electrode of the first output side transistor 105a is connected to one terminal of the internal resistor 106a, and the second electrode of the first output side transistor 105a is connected to the high potential side power supply line 108. The other terminal of the internal resistor 106a is connected to a terminal of the load resistor 107. In this specification, a circuit in which the first output side transistor 105a and the internal resistor 106a are connected in series is referred to as an output generating circuit 102a.
以類似方式，第一輸出側電晶體105b的第一電極連接到內部電阻器106b的一終端，及第一輸出側電晶體105b的第二電極連接到高電位側電力供應線108。內部電阻器106b的另一終端連接到負載電阻器107的一終端。在此說明書中，串聯連接第一輸出側電晶體105b和內部電阻器106b之電路被稱作輸出產生電路102b。In a similar manner, the first electrode of the first output side transistor 105b is connected to one terminal of the internal resistor 106b, and the second electrode of the first output side transistor 105b is connected to the high potential side power supply line 108. The other terminal of the internal resistor 106b is connected to a terminal of the load resistor 107. In this specification, a circuit in which the first output side transistor 105b and the internal resistor 106b are connected in series is referred to as an output generating circuit 102b.
以類似方式，第一輸出側電晶體105c的第一電極連接到內部電阻器106c的一終端，及第一輸出側電晶體105c的第二電極連接到高電位側電力供應線108。內部電阻器106c的另一終端連接到負載電阻器107的一終端。在此說明書中，串聯連接第一輸出側電晶體105c和內部電阻器106c之電路被稱作輸出產生電路102c。In a similar manner, the first electrode of the first output side transistor 105c is connected to one terminal of the internal resistor 106c, and the second electrode of the first output side transistor 105c is connected to the high potential side power supply line 108. The other terminal of the internal resistor 106c is connected to a terminal of the load resistor 107. In this specification, a circuit in which the first output side transistor 105c and the internal resistor 106c are connected in series is referred to as an output generating circuit 102c.
負載電阻器107的一終端連接到輸出終端110，及負載電阻器107的另一終端連接到低電位側電力供應線109。One terminal of the load resistor 107 is connected to the output terminal 110, and the other terminal of the load resistor 107 is connected to the low potential side power supply line 109.
接著，將說明此實施例模式的光電轉換裝置之操作。Next, the operation of the photoelectric conversion device of this embodiment mode will be explained.
光電轉換元件103輸出對應於入射在光電轉換元件103上之光的照度之光電流。當照度增加時，來自光電轉換元件103的光電流輸出增加。來自光電轉換元件103的光電流輸出流經第二參考側電晶體212，藉以在第二參考側電晶體212的閘極和源極之間形成電位差。在第二輸出側電晶體213的閘極和源極之間亦施加電位差。在第二電流鏡電路211中，藉由施加相同電壓到第二參考側電晶體212和第二輸出側電晶體213的閘極電極，利用已流經第二參考電晶體212的光電流當作參考來控制流經第二輸出側電晶體213的電流。The photoelectric conversion element 103 outputs a photocurrent corresponding to the illuminance of the light incident on the photoelectric conversion element 103. When the illuminance is increased, the photocurrent output from the photoelectric conversion element 103 is increased. The photocurrent output from the photoelectric conversion element 103 flows through the second reference side transistor 212, thereby forming a potential difference between the gate and the source of the second reference side transistor 212. A potential difference is also applied between the gate and the source of the second output side transistor 213. In the second current mirror circuit 211, by applying the same voltage to the gate electrodes of the second reference side transistor 212 and the second output side transistor 213, the photocurrent that has flowed through the second reference transistor 212 is utilized as The current flowing through the second output side transistor 213 is controlled with reference.
如上述，依據光電流的電流流經第二輸出側電晶體213。電流亦流經第一參考側電晶體104。因此，另外在第一電流鏡電路101中，如同第二電流鏡電路211一般，也施加相同電壓到第一參考側電晶體104和三輸出側電晶體105a至105c的閘極電極。然後，利用已流經第一參考側電晶體104的光電流當作參考來控制流經各個輸出側電晶體105a至105c之電流。As described above, the current according to the photocurrent flows through the second output side transistor 213. Current also flows through the first reference side transistor 104. Therefore, in the first current mirror circuit 101, as in the second current mirror circuit 211, the same voltage is applied to the gate electrodes of the first reference side transistor 104 and the three output side transistors 105a to 105c. Then, the current flowing through the respective output side transistors 105a to 105c is controlled using the photocurrent that has flowed through the first reference side transistor 104 as a reference.
結果，根據光電流的電流流經第一輸出側電晶體105a至105c，藉以在三輸出產生電路102a至102c中產生輸出電流。稍後將說明輸出產生電路102a至102c的操作。由複數輸出產生電路102a至102c所產生之輸出電流的總和流經負載電阻器107。因此，在負載電阻器107的終端之間形成電位差。當電位差是VRL及輸出電壓是Vout時，從輸出終端110輸出Vout=VRL+VSS。As a result, a current according to the photocurrent flows through the first output side transistors 105a to 105c, thereby generating an output current in the three output generating circuits 102a to 102c. The operations of the output generating circuits 102a to 102c will be described later. The sum of the output currents generated by the complex output generating circuits 102a to 102c flows through the load resistor 107. Therefore, a potential difference is formed between the terminals of the load resistor 107. When the potential difference isVRL and the output voltage isVout ,Vout =VRL + VSS is output from the output terminal 110.
此處，在第二電流鏡電路211中，若第二參考側電晶體212和第二輸出側電晶體213的特性相同，則具有與光電流的量相同之量的電流能夠流經第一電流鏡電路101中的第一參考側電晶體104。此外，藉由設定第二參考側電晶體212和第二輸出側電晶體213的通道長度L對通道寬度W之比，α=W/L，彼此不同，可放大光電流。例如，為了改變第二輸出側電晶體213之α值，可改變第二輸出側電晶體213的通道長度L和寬度W，或可增加第二輸出側電晶體213的數目，及可並聯連接第二輸出側電晶體213。Here, in the second current mirror circuit 211, if the characteristics of the second reference side transistor 212 and the second output side transistor 213 are the same, the current having the same amount as the amount of the photocurrent can flow through the first current. The first reference side transistor 104 in the mirror circuit 101. Further, by setting the ratio of the channel lengthL of the second reference side transistor 212 and the second output side transistor 213 to the channel widthW , α =W / L , different from each other, the photocurrent can be amplified. For example, in order to change the alpha value of the second output side transistor 213, the channel lengthL and the widthW of the second output side transistor 213 may be changed, or the number of the second output side transistors 213 may be increased, and the number of the second output side transistors 213 may be increased. Two output side transistors 213.
接著，將參考圖2至4說明輸出產生電路102a至102c的操作。Next, the operations of the output generating circuits 102a to 102c will be explained with reference to Figs.
圖2為輸出產生電路102a的結構圖。將輸出側電晶體105a和內部電阻器106a串聯連接。根據光電流所產生之閘極電壓被施加到第一輸出側電晶體105a的閘極電極。以Vgate表示閘極電壓。此外，內部電阻器106a的第二電極之電位是輸出電位Vout。FIG. 2 is a structural diagram of the output generating circuit 102a. The output side transistor 105a and the internal resistor 106a are connected in series. A gate voltage generated according to the photocurrent is applied to the gate electrode of the first output side transistor 105a. Thegate voltage is represented byVgate . Further, the potential of the second electrode of the internal resistor 106a is the output potentialVout .
圖3圖示第一輸出側電晶體105a和內部電阻器106a的電壓電流特性，其中流經輸出產生電路102a的電流是I，及第一輸出側電晶體105a和內部電阻器106a之間的連接部位之電位是V。在圖3中，垂直軸表示電流，而水平軸表示電壓。在圖3中，曲線301表示將具有照度L1之光(單位：lux)傳送到光電轉換元件時之第一輸出側電晶體105a的電壓電流特性。曲線302表示將具有照度L2(L1<L2)之光傳送到光電轉換元件時之第一輸出側電晶體105a的電壓電流特性。此外，直線303表示內部電阻器106a的電壓電流特性。利用對應於表示第一輸出側電晶體105a的電壓電流特性之曲線和內部電阻器106a的電壓電流特性之直線的交點(此被稱作操作點)之電壓V和電流I來操作輸出產生電路102a。3 illustrates voltage and current characteristics of the first output side transistor 105a and the internal resistor 106a, wherein the current flowing through the output generating circuit 102a is I, and the connection between the first output side transistor 105a and the internal resistor 106a The potential of the part isV. In Figure 3, the vertical axis represents current and the horizontal axis represents voltage. In Figure 3, curve 301 represents the light having a luminanceL1: a first output-side voltage-current characteristic when the transistor 105a (in lux) transmitted to the photoelectric conversion element. A curve 302 shows the voltage-current characteristics of the first output-side transistor 105a when light having the illuminanceL2 (L1 <L2 ) is transmitted to the photoelectric conversion element. Further, a line 303 represents the voltage current characteristics of the internal resistor 106a. The output generation circuit 102a is operated by a voltageV and a currentI corresponding to an intersection point (referred to as an operation point) of a line representing a voltage-current characteristic of the first output-side transistor 105a and a line of voltage-current characteristics of the internal resistor 106a. .
當具有照度L1之光進入時，第一輸出側電晶體105a具有曲線301所示之電壓電流特性，及輸出產生電路102a的操作點是曲線301和直線303的交點之點304。然後，電流I1流經輸出產生電路102a。When light having a luminanceL1 of enters, a first output-side transistor 105a having a voltage-current characteristic shown in the curve 301, and the output operating point generating circuit 102a and line 301 is a curve 303 of the intersection point 304. Then, the currentI1 flows through the output generating circuit 102a.
那時，在飽和範圍中操作第一輸出側電晶體105a。飽和範圍是閘極和源極之間的電壓VGS，汲極和源極之間的電壓VDS，及第一輸出側電晶體105a的臨界電壓VTH之大小關係是∣VGS-VTH∣<∣VDS∣之範圍。在此範圍中，只依據第一輸出側電晶體105a的閘極和源極之間的電壓VGS之電流流經第一輸出側電晶體105a。因此，與照度成比例之電流流經輸出產生電路102a。At that time, the first output side transistor 105a is operated in the saturation range. The saturation range is the voltageV GS between the gate and the source, the voltageV DS between the drain and the source, and the magnitude of the threshold voltageV TH of the first output side transistor 105a is ∣V GS-V TH ∣<∣V DS∣ range. In this range, the current according to the voltageV GS between the gate and the source of the first output side transistor 105a flows through the first output side transistor 105a. Therefore, a current proportional to the illuminance flows through the output generating circuit 102a.
在具有高於照度L1之照度的光進入時，當照度是在第一輸出側電晶體105a操作於飽和範圍中之範圍內時，與照度成比例之電流流經輸出產生電路102a。When light enters the above having luminanceL1 of illumination when the illumination is at a first side of the output transistor 105a operates in the saturation range in the scope of the generating circuit 102a and the current flowing through the output is proportional to the illuminance.
在進一步增加照度並且具有照度L2的光進入時，第一輸出側電晶體105a具有曲線302所示之電壓電流特性。那時，輸出產生電路102a的操作點是點305及電流I2流經輸出產生電路102a。The first output side transistor 105a has a voltage current characteristic shown by a curve 302 when light having further illuminance and having illuminanceL2 is entered. At that time, the operating point of the output generating circuit 102a is point 305 and currentI2 flows through the output generating circuit 102a.
那時，在直線範圍中操作第一輸出側電晶體105a。直線範圍是閘極和源極之間的電壓VGS，汲極和源極之間的電壓VDS，及第一輸出側電晶體105a的臨界電壓VTH之大小關係是∣VGS-VTH∣>∣VDS∣之範圍。在此範圍中，依據第一輸出側電晶體105a的閘極和源極之間的電壓VGS與汲極和源極之間的電壓VDS之電流流經第一輸出側電晶體105a。因此，流經輸出產生電路102a的電流未與照度成比例，及逐漸變得更接近Imax。需注意的是，以(VDD-Vout)/Ri表示Imax。需注意的是，Ri是內部電阻器106的電阻值。At that time, the first output side transistor 105a is operated in a linear range. The linear range is the voltageV GS between the gate and the source, the voltageV DS between the drain and the source, and the magnitude of the threshold voltageV TH of the first output side transistor 105a is ∣V GS-V TH ∣>∣V DS∣ range. In this range, a current according to the voltageV GS between the gate and the source of the first output side transistor 105a and the voltageV DS between the drain and the source flows through the first output side transistor 105a. Therefore, the current flowing through the output generating circuit 102a is not proportional to the illuminance, and gradually becomes closer toI max . It should be noted thatI max is represented by (VDD -V out) /R i . It should be noted thatR i is the resistance value of the internal resistor 106.
此處，圖4圖示輸出產生電路102a的照度電流特性。在圖4中，水平軸表示照度，而垂直軸表示流經輸出產生電路102a的電流。以對數刻度表示它們二者。Here, FIG. 4 illustrates the illuminance current characteristic of the output generating circuit 102a. In FIG. 4, the horizontal axis represents illuminance, and the vertical axis represents current flowing through the output generating circuit 102a. Both are represented on a logarithmic scale.
如上述，當照度是在第一輸出側電晶體105a於飽和範圍中操作之範圍內時(例如，照度L1)，與照度成比例的電流流經輸出產生電路102a。另一方面，當照度是在第一輸出側電晶體105a於直線範圍中操作之範圍內時(例如，照度L2)，流經輸出產生電路102a之電流未與照度成比例，及逐漸變得更接近Imax。As described above, when the illuminance is within the range in which the first output side transistor 105a operates in the saturation range (for example, the illuminanceL1 ), a current proportional to the illuminance flows through the output generating circuit 102a. On the other hand, when the illuminance is within the range in which the first output side transistor 105a operates in the linear range (for example, the illuminanceL2 ), the current flowing through the output generating circuit 102a is not proportional to the illuminance, and gradually becomes Closer toI max.
雖然到目前為止已說明輸出產生電路102a，但是輸出產生電路102b和輸出產生電路102c亦以類似方式來操作。Although the output generation circuit 102a has been explained so far, the output generation circuit 102b and the output generation circuit 102c also operate in a similar manner.
接著，將再次說明此實施例模式的光電轉換裝置之操作。在此實施例模式的光電轉換裝置中，執行上述操作之複數輸出產生電路被並聯連接。此處，將說明如圖21所示之並聯連接三輸出產生電路102a至102c時的電路之操作。Next, the operation of the photoelectric conversion device of this embodiment mode will be described again. In the photoelectric conversion device of this embodiment mode, the complex output generating circuits that perform the above operations are connected in parallel. Here, the operation of the circuit when the three-output generating circuits 102a to 102c are connected in parallel as shown in FIG. 21 will be explained.
在三輸出產生電路102a至102c中，使第一輸出側電晶體105a至105c的通道長度L對通道寬度W之比，α=W/L，彼此不同。例如，第一輸出側電晶體105a的α是α1，第二輸出側電晶體105b的α是α2，及第三輸出側電晶體105c的α是α3。其大小關係是α1>α2>α3。較佳的是，α被設定如下：α1/α2=約10及α2/α3=約10。In the three output generating circuits 102a to 102c, the ratio of the channel lengthL of the first output side transistors 105a to 105c to the channel widthW , α =W/L , is made different from each other. For example, α of the first output side transistor 105a is α1 , α of the second output side transistor 105b is α2 , and α of the third output side transistor 105c is α3 . Its size relationship is α1 >α2 >α3 . Preferably, α is set as follows: α1 /α2 = about 10 and α2 /α3 = about 10.
需注意的是，為了方便說明，內部電阻器106a至106c的電阻值被設定成相同的。然而，內部電阻器106a至106c的電阻值並不侷限於此，而可以是彼此不同的。It should be noted that the resistance values of the internal resistors 106a to 106c are set to be the same for convenience of explanation. However, the resistance values of the internal resistors 106a to 106c are not limited thereto, but may be different from each other.
圖5A至5C圖解那例子中的圖21所示之電路的操作。圖5A圖示輸出產生電路102a至102c的照度電流特性。在圖5A中，水平軸表示照度，而垂直軸表示流經輸出產生電路102a至102c之電流。以對數刻度表示它們二者。5A to 5C illustrate the operation of the circuit shown in Fig. 21 in that example. FIG. 5A illustrates illuminance current characteristics of the output generating circuits 102a to 102c. In Fig. 5A, the horizontal axis represents illuminance, and the vertical axis represents current flowing through the output generating circuits 102a to 102c. Both are represented on a logarithmic scale.
需注意的是，曲線501a表示第一輸出產生電路102a的照度電流特性，曲線501b表示第二輸出產生電路102b的照度電流特性，及曲線501c表示第三輸出產生電路102c的照度電流特性。It is to be noted that the curve 501a represents the illuminance current characteristic of the first output generating circuit 102a, the curve 501b represents the illuminance current characteristic of the second output generating circuit 102b, and the curve 501c represents the illuminance current characteristic of the third output generating circuit 102c.
在輸出產生電路102a至102c中，當第一輸出側電晶體105a至105c之α變得較大時，能夠以較低照度在直線範圍中驅動第一輸出側電晶體105a至105c，因為各個輸出側電晶體105a至105c串聯連接到內部電阻器106a至106c的其中之一個。因此，當第一輸出側電晶體105a至105c之α變得較大時，以更低的照度，流經輸出產生電路102a至102c的電流擊中峰值。In the output generating circuits 102a to 102c, when α of the first output side transistors 105a to 105c becomes larger, the first output side transistors 105a to 105c can be driven in a linear range with lower illuminance because each output The side transistors 105a to 105c are connected in series to one of the internal resistors 106a to 106c. Therefore, when α of the first output side transistors 105a to 105c becomes larger, the current flowing through the output generating circuits 102a to 102c hits a peak with a lower illuminance.
流經輸出產生電路102a至102c之電流的總和是此實施例模式的光電轉換裝置之輸出電流(以Iout表示輸出電流)。然後，輸出電流流經負載電阻器107，及在負載電阻器107中所產生的電位差和VSS之總和被輸出當作輸出電壓Vout。The sum of the currents flowing through the output generating circuits 102a to 102c is the output current of the photoelectric conversion device of this embodiment mode (the output current is represented byI out). Then, the output current flows through the load resistor 107, and the sum of the potential difference generated in the load resistor 107 and VSS is output as the output voltageV out .
在圖5B圖示流經輸出產生電路102a至102c之電流的總和(輸出電流)。此外，在圖5C圖示輸出電壓Vout。在圖5B及5C中，水平軸表示以對數刻度顯示之照度，而垂直軸表示以直線刻度表示之輸出電流或輸出電壓。The sum (output current) of the currents flowing through the output generating circuits 102a to 102c is illustrated in Fig. 5B. Further, the output voltageV out is illustrated in FIG. 5C. In FIGS. 5B and 5C, the horizontal axis represents the illuminance displayed on a logarithmic scale, and the vertical axis represents the output current or output voltage expressed in a linear scale.
因為輸出電流Iout是流經輸出產生電路102a至102c之電流的總和，所以輸出電流Iout具有幾乎與圖5B所示之照度的對數成比例之特性。此外，輸出電壓Vout亦具有幾乎與照度的對數成比例之特性。Since the output currentI out is the sum of the currents flowing through the output generating circuits 102a to 102c, the output currentI out has a characteristic which is almost proportional to the logarithm of the illuminance shown in Fig. 5B. In addition, the output voltageVout also has a characteristic that is almost proportional to the logarithm of the illuminance.
以此方式，在此實施例模式的光電轉換裝置中，能夠獲得幾乎與照度的對數成比例之輸出，並且能夠加寬可應用到光電轉換裝置的照度範圍。In this way, in the photoelectric conversion device of this embodiment mode, an output which is almost proportional to the logarithm of the illuminance can be obtained, and the illuminance range applicable to the photoelectric conversion device can be widened.
另外，當設置第二電流鏡電路211時，可將藉由放大光電流所獲得之電流輸入到第一電流鏡電路101。此能夠縮短使第一參考側電晶體104和第一輸出側電晶體105a至105c的閘極電壓變成預定電壓所需之時間。因此，在改變照度的例子中，可縮短達到預定值之輸出所需的時間，藉以能夠獲得即使改變照度輸出仍可具有高反應速度之光電轉換裝置。In addition, when the second current mirror circuit 211 is provided, the current obtained by amplifying the photocurrent can be input to the first current mirror circuit 101. This can shorten the time required to make the gate voltage of the first reference side transistor 104 and the first output side transistors 105a to 105c become a predetermined voltage. Therefore, in the example of changing the illuminance, the time required to reach the output of the predetermined value can be shortened, whereby the photoelectric conversion device which can have a high reaction speed even if the illuminance output is changed can be obtained.
雖然在圖21所示之電路中並聯三個連接輸出產生電路，但是只要設置複數輸出產生電路，輸出產生電路的數目並不侷限於此。藉由增加輸出產生電路的數目，能夠加寬可應用到光電轉換裝置的照度範圍，並且能夠使有關照度的輸入之變化變小。Although three connection output generating circuits are connected in parallel in the circuit shown in Fig. 21, the number of output generating circuits is not limited to this as long as the complex output generating circuit is provided. By increasing the number of output generating circuits, it is possible to widen the range of illuminance applicable to the photoelectric conversion device, and it is possible to make the change in the input relating to illuminance small.
需注意的是，負載電阻器107可結合在光電轉換裝置內，或者可裝附諸如晶片電阻器等外部電阻器當作負載電阻器107。當負載電阻器107結合在光電轉換裝置內時，不需要外部電阻器，藉以可減少用以連接外部電阻器之步驟和部分的數目。此外，因為不需要用於外部電阻器的區域，所以可使電子裝置的光電轉換部位之區域變小。另一方面，當負載電阻器107是外部電阻器時，能夠抑制負載電阻變化的影響(尤其是，有關溫度的電阻變化)。It is to be noted that the load resistor 107 may be incorporated in the photoelectric conversion device, or an external resistor such as a wafer resistor may be attached as the load resistor 107. When the load resistor 107 is incorporated in the photoelectric conversion device, an external resistor is not required, whereby the number of steps and portions for connecting the external resistor can be reduced. Further, since the area for the external resistor is not required, the area of the photoelectric conversion portion of the electronic device can be made small. On the other hand, when the load resistor 107 is an external resistor, it is possible to suppress the influence of the change in the load resistance (in particular, the resistance change with respect to temperature).
需注意的是，在圖21所示之電路中，雖然第二參考側電晶體212和第二輸出側電晶體213是n通道電晶體，及第一參考側電晶體104和第一輸出側電晶體105a至105c是p通道電晶體，但是可利用顛倒的例子。圖22圖示顛倒例子的電路組態。It should be noted that in the circuit shown in FIG. 21, the second reference side transistor 212 and the second output side transistor 213 are n-channel transistors, and the first reference side transistor 104 and the first output side are electrically The crystals 105a to 105c are p-channel transistors, but an inverted example can be utilized. Figure 22 illustrates the circuit configuration of the reverse example.
圖22所示之光電轉換裝置包括光電轉換元件603；電流鏡電路601和第二電流鏡電路611，其為用以放大來自光電轉換元件603的輸出電流(又稱作光電流)之放大器電路；三內部電阻器606a至606c；負載電阻器607；高電位測電力供應線608；低電位測電力供應線609；及輸出終端610。第一電流鏡電路601包括第一參考側電晶體604和三第一輸出側電晶體605a至605c。第二電流鏡電路611包括第二參考側電晶體612和第二輸出側電晶體613。The photoelectric conversion device shown in FIG. 22 includes a photoelectric conversion element 603; a current mirror circuit 601 and a second current mirror circuit 611, which are amplifier circuits for amplifying an output current (also referred to as photocurrent) from the photoelectric conversion element 603; Three internal resistors 606a to 606c; a load resistor 607; a high potential power supply line 608; a low potential power supply line 609; and an output terminal 610. The first current mirror circuit 601 includes a first reference side transistor 604 and three first output side transistors 605a to 605c. The second current mirror circuit 611 includes a second reference side transistor 612 and a second output side transistor 613.
在圖22中，所有第一參考側電晶體604和第一輸出側電晶體605a至605c都是n通道場效電晶體。第二參考側電晶體612和第二輸出側電晶體613二者都是p通道場效電晶體。In FIG. 22, all of the first reference side transistors 604 and the first output side transistors 605a to 605c are n-channel field effect transistors. Both the second reference side transistor 612 and the second output side transistor 613 are p-channel field effect transistors.
需注意的是，以VDD表示高電位側上的電力供應電位，以VSS表示低電位側上的電力供應電位。It is to be noted that the power supply potential on the high potential side is represented by VDD, and the power supply potential on the low potential side is represented by VSS.
在圖22中，將第二參考側電晶體612的第一電極和閘極電極彼此二極體連接。第二參考側電晶體612的第一電極連接到光電轉換元件603的陰極，第二參考側電晶體612的閘極電極連接到第二輸出側電晶體613的閘極電極，及第二參考側電晶體612的第二電極連接到高電位側電力供應線608。In FIG. 22, the first electrode and the gate electrode of the second reference side transistor 612 are connected to each other in a diode. The first electrode of the second reference side transistor 612 is connected to the cathode of the photoelectric conversion element 603, the gate electrode of the second reference side transistor 612 is connected to the gate electrode of the second output side transistor 613, and the second reference side The second electrode of the transistor 612 is connected to the high potential side power supply line 608.
第二輸出側電晶體613的第一電極連接到第一參考側電晶體604的第一電極，及第二輸出側電晶體613的第二電極連接到高電位側電力供應線608。The first electrode of the second output side transistor 613 is connected to the first electrode of the first reference side transistor 604, and the second electrode of the second output side transistor 613 is connected to the high potential side power supply line 608.
將第一參考側電晶體604的第一電極和閘極電極彼此二極體連接。第一參考側電晶體604的閘極電極連接到連接到三第一輸出側電晶體605a至605c的各個閘極電極，及第一參考側電晶體604的第二電極連接到光電轉換元件603的陽極和低電位側電力供應線609。The first electrode and the gate electrode of the first reference side transistor 604 are connected to each other in a diode. The gate electrode of the first reference side transistor 604 is connected to each of the gate electrodes connected to the three first output side transistors 605a to 605c, and the second electrode of the first reference side transistor 604 is connected to the photoelectric conversion element 603 An anode and a low potential side power supply line 609.
第一輸出側電晶體605a的第一電極連接到內部電阻器606a的一終端，及第一輸出側電晶體605a的第二電極連接到低電位側電力供應線609。內部電阻器606a的另一終端連接到負載電阻器607的一終端。在此說明書中，串聯連接第一輸出側電晶體605a和內部電阻器606a之電路被稱作輸出產生電路602a。The first electrode of the first output side transistor 605a is connected to one terminal of the internal resistor 606a, and the second electrode of the first output side transistor 605a is connected to the low potential side power supply line 609. The other terminal of internal resistor 606a is coupled to a terminal of load resistor 607. In this specification, a circuit in which the first output side transistor 605a and the internal resistor 606a are connected in series is referred to as an output generating circuit 602a.
以類似方式，第一輸出側電晶體605b的第一電極連接到內部電阻器606b的一終端，及第一輸出側電晶體605b的第二電極連接到低電位側電力供應線609。內部電阻器606b的另一終端連接到負載電阻器607的一終端。在此說明書中，串聯連接第一輸出側電晶體605b和內部電阻器606b之電路被稱作輸出產生電路602b。In a similar manner, the first electrode of the first output side transistor 605b is connected to one terminal of the internal resistor 606b, and the second electrode of the first output side transistor 605b is connected to the low potential side power supply line 609. The other terminal of the internal resistor 606b is connected to a terminal of the load resistor 607. In this specification, a circuit in which the first output side transistor 605b and the internal resistor 606b are connected in series is referred to as an output generating circuit 602b.
以類似方式，第一輸出側電晶體605c的第一電極連接到內部電阻器606c的一終端，及第一輸出側電晶體605c的第二電極連接到低電位側電力供應線609。內部電阻器606c的另一終端連接到負載電阻器607的一終端。在此說明書中，串聯連接第一輸出側電晶體605c和內部電阻器606c之電路被稱作輸出產生電路602c。In a similar manner, the first electrode of the first output side transistor 605c is connected to one terminal of the internal resistor 606c, and the second electrode of the first output side transistor 605c is connected to the low potential side power supply line 609. The other terminal of the internal resistor 606c is connected to a terminal of the load resistor 607. In this specification, a circuit in which the first output side transistor 605c and the internal resistor 606c are connected in series is referred to as an output generating circuit 602c.
負載電阻器607的一終端連接到輸出終端610。光電轉換元件603的陰極和負載電阻器607的另一終端連接到高電位側電力供應線608。A terminal of the load resistor 607 is connected to the output terminal 610. The cathode of the photoelectric conversion element 603 and the other terminal of the load resistor 607 are connected to the high potential side power supply line 608.
圖22所示之電路的結構基本上類似於圖21所示之電路的結構，及執行基本上類似於圖21所示之電路操作的電路操作。圖21及圖22所示的電路之間的差是輸出電壓Vout。在圖22所示之電路的例子中，當負載電阻器607的終端之間的電位差是VRL時，從輸出中610輸出電壓Vout=VDD-VRL。The structure of the circuit shown in Fig. 22 is substantially similar to the structure of the circuit shown in Fig. 21, and performs circuit operations substantially similar to those of the circuit shown in Fig. 21. The difference between the circuits shown in Figs. 21 and 22 is the output voltageV out . In the example of the circuit shown in FIG. 22, when the potential difference between the terminals of the load resistor 607 isVRL , the voltageV out = VDD -VRL is output from the output 610.
此處，圖7A及7B圖示圖22所示之電路的輸出之照度特性。圖7A圖示輸出電流Iout的照度特性，及垂直軸表示輸出電流(直線刻度)和水平軸表示照度(對數刻度)。圖7B圖示輸出電壓Vout的照度特性，及垂直軸表示輸出電壓(直線刻度)和水平軸表示照度(對數刻度)。Here, FIGS. 7A and 7B illustrate the illuminance characteristics of the output of the circuit shown in FIG. Illumination characteristics 7A illustrates the output currentI out, and the vertical axis represents the output current (linear scale) and the horizontal axis represents luminance (logarithmic scale). Fig. 7B illustrates the illuminance characteristic of the output voltageVout , and the vertical axis represents the output voltage (linear scale) and the horizontal axis represents illuminance (logarithmic scale).
在圖21所示之電路中，當照度增加時，如圖5C所示一般，輸出電壓Vout增加。另一方面，在圖22所示之電路中，當照度增加，輸出電壓Vout減少。在任一例子中，輸出電流Iout具有幾乎與照度的對數成比例之特性。此外，輸出電壓Vout具有幾乎與照度的對數成比例之特性。In the circuit shown in Fig. 21, when the illuminance is increased, as shown in Fig. 5C, the output voltageVout is increased. On the other hand, in the circuit shown in Fig. 22, as the illuminance increases, the output voltageVout decreases. In either instance, the output currentI out characteristic has almost proportional to the logarithm of the illuminance of. Further, the output voltageV out has a characteristic that is almost proportional to the logarithm of the illuminance.
以此方式，在此實施例模式的光電轉換裝置中，可獲得幾乎與照度的對數成比例之輸出，及可加寬可應用到光電轉換裝置之照度範圍。In this way, in the photoelectric conversion device of this embodiment mode, an output which is almost proportional to the logarithm of the illuminance can be obtained, and the illuminance range applicable to the photoelectric conversion device can be widened.
雖然在圖22所示的電路中並聯連接三輸出產生電路，但是只要設置複數輸出產生電路，輸出產生電路的數目並不侷限於此。藉由增加輸出產生電路的數目，能夠加寬可應用到光電轉換裝置的照度範圍，及能夠使有關照度的輸出之變化變小。Although the three-output generating circuit is connected in parallel in the circuit shown in FIG. 22, the number of output generating circuits is not limited to this as long as the complex output generating circuit is provided. By increasing the number of output generating circuits, it is possible to widen the range of illuminance applicable to the photoelectric conversion device, and to make the change in the output of the illuminance smaller.
需注意的是，因為此實施例模式中的光電轉換裝置包括n通道電晶體和p通道電晶體二者，所以可抑制由於電晶體的特性變化所導致之電路特性變化。It is to be noted that since the photoelectric conversion device in this embodiment mode includes both the n-channel transistor and the p-channel transistor, variations in circuit characteristics due to variations in characteristics of the transistor can be suppressed.
當作此實施例模式所說明的光電轉換元件，能夠使用將光能轉換成電能之諸如一般光電二極體等元件。As the photoelectric conversion element explained in this embodiment mode, an element such as a general photodiode that converts light energy into electric energy can be used.
需注意的是，可利用各種類型的場效電晶體當作此實施例模式所說明之n通道電晶體和p通道電晶體。因此，對所使用的電晶體類型並無限制。例如，可利用包括以非晶矽為代表的非單晶半導體膜、微晶(又稱作半非晶)矽等之薄膜電晶體(TFT)。在使用TFT的例子中，具有各種優點。例如，因為可在低於使用單晶矽的例子之溫度的溫度中形成TFT，所以能夠減少製造成本，及能夠使製造設備較大。因為製造設備能夠是大的，所以可將TFT形成在大基板上。因此，能夠同時形成許多光電轉換裝置，製造成本低。此外，因為可在低溫中製造TFT，所以能夠使用具有低耐熱性的基板。因此，可將電晶體形成在光傳送基板上。因此，可藉由使用形成在光傳送基板上的電晶體來控制光電轉換元件中之光的傳輸。It should be noted that various types of field effect transistors can be utilized as the n-channel transistors and p-channel transistors illustrated in this embodiment mode. Therefore, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) including a non-single crystal semiconductor film typified by amorphous germanium, microcrystals (also referred to as semi-amorphous) germanium, or the like can be used. In the example using TFT, there are various advantages. For example, since the TFT can be formed at a temperature lower than the temperature of the example using the single crystal germanium, the manufacturing cost can be reduced, and the manufacturing apparatus can be made large. Since the manufacturing equipment can be large, the TFT can be formed on a large substrate. Therefore, many photoelectric conversion devices can be formed at the same time, and the manufacturing cost is low. Further, since the TFT can be manufactured at a low temperature, a substrate having low heat resistance can be used. Therefore, a transistor can be formed on the light transmitting substrate. Therefore, the transmission of light in the photoelectric conversion element can be controlled by using a transistor formed on the light transmission substrate.
藉由在形成多晶矽時使用催化劑(如、鎳)，可進一步提高晶性，及可形成具有絕佳電特性的電晶體。因此，在同一基板上可形成在高速中操作的電路。藉由在形成微晶矽時使用催化劑(如、鎳)，可進一步提高晶性，及可形成具有絕佳電特性的電晶體。此時，藉由執行熱處理卻不必執行雷射照射就可提高晶性。在未將雷射用於結晶的例子中可抑制矽的晶性不均勻。因此，可抑制電晶體的特性之間的差。需注意的是，可在不使用催化劑(如、鎳)之下形成多晶矽和微晶矽。By using a catalyst (e.g., nickel) in the formation of polycrystalline germanium, crystallinity can be further improved, and a crystal having excellent electrical characteristics can be formed. Therefore, a circuit that operates at high speed can be formed on the same substrate. By using a catalyst (e.g., nickel) in the formation of microcrystalline germanium, crystallinity can be further improved, and a crystal having excellent electrical characteristics can be formed. At this time, crystallinity can be improved by performing heat treatment without performing laser irradiation. In the case where the laser is not used for crystallization, the crystal unevenness of ruthenium can be suppressed. Therefore, the difference between the characteristics of the transistors can be suppressed. It should be noted that polycrystalline germanium and microcrystalline germanium can be formed without the use of a catalyst such as nickel.
此外，可藉由使用半導體基板、SOI基板等來形成電晶體。因此，可形成具有特性、尺寸、形狀等變化少，具有高度電流供應能力，並且小尺寸之電晶體。藉由使用此種電晶體，可降低電路的電力消耗或可高度整合電路。另一選擇是，能夠使用包括諸如ZnO、a-InGaZnO、SiGe、GaAs、銦鋅氧化物(IZO)、銦錫氧化物(ITO)、或氧化錫(SnO)等化合物半導體或氧化物半導體之電晶體，藉由使此種化合物半導體或氧化物半導體變薄所獲得之薄膜電晶體等。因此，可降低製造溫度，及例如，可在室溫中形成此種電晶體。因此，可將電晶體直接形成在具有諸如塑膠基板或膜基板等低耐熱性的基板上。Further, the transistor can be formed by using a semiconductor substrate, an SOI substrate, or the like. Therefore, it is possible to form a transistor having a small change in characteristics, size, shape, and the like, having a high current supply capability, and a small size. By using such a transistor, the power consumption of the circuit or the highly integrated circuit can be reduced. Alternatively, it is possible to use a compound semiconductor or oxide semiconductor including a ZnO, a-InGaZnO, SiGe, GaAs, indium zinc oxide (IZO), indium tin oxide (ITO), or tin oxide (SnO). A thin film transistor or the like obtained by thinning such a compound semiconductor or an oxide semiconductor. Therefore, the manufacturing temperature can be lowered, and, for example, such a crystal can be formed at room temperature. Therefore, the transistor can be formed directly on a substrate having low heat resistance such as a plastic substrate or a film substrate.
另一選擇是，亦可使用藉由使用噴墨法或印刷法所形成之電晶體。因此，可在室溫中形成，可在低真空中形成，或可在大基板上形成電晶體。此外，因為可在不使用遮罩(光罩)之下形成電晶體，所以可溶液地改變電晶體的佈局。另外，因為不需要使用抗蝕劑，所以可降低材料成本和可降低步驟數目。而且，因為只在必要部位形成膜，所以與在將膜形成於整個基板上之後執行蝕刻的製造方法相比，比較不浪費材料，如此可降低成本。Alternatively, a transistor formed by using an inkjet method or a printing method can also be used. Therefore, it can be formed at room temperature, can be formed in a low vacuum, or can form a transistor on a large substrate. Furthermore, since the transistor can be formed without using a mask (photomask), the layout of the transistor can be changed in solution. In addition, since the resist is not required, the material cost can be reduced and the number of steps can be reduced. Moreover, since the film is formed only at the necessary portion, the material is relatively wasted compared to the manufacturing method in which the etching is performed after the film is formed on the entire substrate, so that the cost can be reduced.
另一選擇是，可使用包括有機半導體或碳奈米管等之電晶體。因此，可使用能夠彎曲之基板來形成此種電晶體。因此，使用包括有機半導體或碳奈米管等的電晶體之裝置能夠抵抗撞擊。Alternatively, a transistor including an organic semiconductor or a carbon nanotube or the like can be used. Therefore, a substrate that can be bent can be used to form such a transistor. Therefore, a device using a transistor including an organic semiconductor or a carbon nanotube can resist impact.
各種類型的電晶體可用於場效電晶體，及可將電晶體形成在各種類型的基板上。因此，可將需要實現預定功能之所有電路形成在同一基板上。例如，可將需要實現預定功能之所有電路形成玻璃基板、塑膠基板、單晶基板、SOI基板上，或形成在各種基板上。藉由使用薄膜電晶體來形成場效電晶體，可將此實施例模式的光電轉換裝置形成在諸如玻璃基板等光傳送基板上。因此，在將光電轉換元件103或603形成於基板上之例子中，光電轉換元件103或603不僅可接收來自基板的一表面之光，而且可接收來自基板的背表面而經由基板傳送之光，藉以提高接收光的效能。Various types of transistors can be used for field effect transistors, and transistors can be formed on various types of substrates. Therefore, all circuits that need to implement a predetermined function can be formed on the same substrate. For example, all circuits that require a predetermined function can be formed on a glass substrate, a plastic substrate, a single crystal substrate, an SOI substrate, or formed on various substrates. The photoelectric conversion device of this embodiment mode can be formed on an optical transmission substrate such as a glass substrate by forming a field effect transistor using a thin film transistor. Therefore, in the example in which the photoelectric conversion element 103 or 603 is formed on the substrate, the photoelectric conversion element 103 or 603 can receive not only light from a surface of the substrate but also light transmitted from the back surface of the substrate via the substrate, In order to improve the performance of receiving light.
需注意的是，此實施例模式能夠與此說明書中的其他實施例模式之技術組件組合。It should be noted that this embodiment mode can be combined with the technical components of the other embodiment modes in this specification.
此實施例模式將使用參考圖8A至8D、及圖9A至9C的橫剖面，呈現上述實施例模式所說明的光電轉換裝置之製造方法當作例子。This embodiment mode will use the cross-sectional views of FIGS. 8A to 8D and FIGS. 9A to 9C, and the manufacturing method of the photoelectric conversion device described in the above embodiment mode will be taken as an example.
首先，將光電轉換元件和場效電晶體形成在基板上(第一基板310)。在此實施例模式中，玻璃基板的其中之一的AN100被用於基板310。在藉由使用薄膜電晶體形成場效電晶體於基板上時，可以連續處理製造光電轉換元件和薄膜電晶體，因此，可大量生產光電轉換裝置，如此是有益的。First, a photoelectric conversion element and a field effect transistor are formed on a substrate (first substrate 310). In this embodiment mode, AN100 of one of the glass substrates is used for the substrate 310. When the field effect transistor is formed on the substrate by using the thin film transistor, the photoelectric conversion element and the thin film transistor can be continuously processed, and therefore, the photoelectric conversion device can be mass-produced, which is advantageous.
以電漿CVD形成充作基極絕緣膜312之包括氮的氧化矽膜(具有膜厚度100nm)，及在不暴露至大氣之下堆疊諸如包括氫的非晶矽膜(具有膜厚度54nm)等半導體膜。另外，可藉由堆疊氧化矽膜、氮化矽膜、及包括氮的氧化矽膜來形成基極絕緣膜312。例如，堆疊具有膜厚度50nm之包括氧的氮化矽膜和具有膜厚度100nm之包括氮的氧化矽膜之膜可被形成當作基極絕緣膜312。需注意的是，括氮的氧化矽膜和包括氧的氮化矽膜每一個充作障層，其防止諸如鹼性金屬等雜質從玻璃基板擴散。A ruthenium oxide film including nitrogen (having a film thickness of 100 nm) which is used as a base insulating film 312 by plasma CVD, and an amorphous ruthenium film (having a film thickness of 54 nm) including hydrogen is stacked without being exposed to the atmosphere. Semiconductor film. Further, the base insulating film 312 can be formed by stacking a tantalum oxide film, a tantalum nitride film, and a hafnium oxide film including nitrogen. For example, a film of tantalum nitride including oxygen having a film thickness of 50 nm and a yttrium oxide film including nitrogen having a film thickness of 100 nm may be formed as the base insulating film 312. It is to be noted that each of the niobium oxide film and the tantalum nitride film including oxygen act as a barrier layer which prevents impurities such as an alkali metal from diffusing from the glass substrate.
接著，藉由已知技術(固相磊晶法、雷射結晶法、使用催化金屬之結晶法等)使非晶矽膜結晶，以形成具有結晶結構的半導體膜(結晶半導體膜)，如、多晶矽膜。此處，多晶矽膜係由使用催化元素之結晶法所獲得的。首先，以塗佈器添加包括鎳重量10ppm的鎳醋酸溶液。需注意的是，可藉由濺鍍取代添加溶液，而在整個表面上分散鎳元素。接著，執行用以使非晶矽膜結晶之熱處理，以形成具有結晶結構的半導體膜(此處為多晶矽膜)。此處，多晶矽膜係藉由在執行熱處理(在500℃中達1小時)之後執行用以結晶化的熱處理(在550℃中達4小時)所獲得的。Then, the amorphous ruthenium film is crystallized by a known technique (solid phase epitaxy, laser crystallization, crystallization using a catalytic metal, etc.) to form a semiconductor film (crystalline semiconductor film) having a crystal structure, for example, Polycrystalline tantalum film. Here, the polycrystalline ruthenium film is obtained by a crystallization method using a catalytic element. First, a nickel acetic acid solution containing 10 ppm by weight of nickel was added by an applicator. It should be noted that the nickel may be dispersed on the entire surface by sputtering instead of the addition solution. Next, heat treatment for crystallizing the amorphous tantalum film is performed to form a semiconductor film (here, a polycrystalline tantalum film) having a crystal structure. Here, the polycrystalline ruthenium film was obtained by performing heat treatment for crystallization (up to 4 hours at 550 ° C) after performing heat treatment (up to 1 hour at 500 ° C).
接著，以稀釋的氫氟酸等去除多晶矽膜的表面上之氧化物膜。之後，在大氣或氧大氣中執行用以增加晶性程度和修補留在晶粒中的缺陷之雷射光的照射(具有波長308nm之XeCl)。Next, the oxide film on the surface of the polysilicon film is removed by dilute hydrofluoric acid or the like. Thereafter, irradiation of laser light (XeCl having a wavelength of 308 nm) for increasing the degree of crystallinity and repairing defects remaining in the crystal grains is performed in the atmosphere or the oxygen atmosphere.
使用具有波長400nm或更少之準分子雷射光，或YAG的第二諧波或第三諧波來當作雷射光。此處，使用具有重複率約10至1000Hz的脈衝雷射光，以光學系統將脈衝雷射光聚集到100至500mJ/cm2，及利用重疊率90至95%執行照射以掃描矽膜的表面。在此實施例模式中，在大氣中執行具有重複率30Hz和能量密度470mJ/cm2之雷射光的照射。Excimer laser light having a wavelength of 400 nm or less, or a second harmonic or a third harmonic of YAG is used as the laser light. Here, the pulsed laser light having a repetition rate of about 10 to 1000 Hz is used, the pulsed laser light is concentrated to 100 to 500 mJ/cm2 by an optical system, and the irradiation is performed with an overlap ratio of 90 to 95% to scan the surface of the ruthenium film. In this embodiment mode, irradiation with laser light having a repetition rate of 30 Hz and an energy density of 470 mJ/cm2 is performed in the atmosphere.
需注意的是，因為在大氣中或在氧大氣中執行雷射光照射，所以氧化膜被形成在表面上。雖然在此實施例模式呈現使用脈衝雷射的例子，但是也可使用連續波雷射。為了在半導體膜的結晶時獲得具有大晶粒尺寸之晶體，使用能夠連續振盪之固態雷射並且施加基波的第二至第四諧波較佳。典型上，施加Nd:YVO4雷射(基波為1064nm)的第二諧波(532nm)或第三諧波(355nm)。It is to be noted that since laser light irradiation is performed in the atmosphere or in an oxygen atmosphere, an oxide film is formed on the surface. Although the embodiment mode exhibits an example using a pulsed laser, a continuous wave laser can also be used. In order to obtain a crystal having a large crystal grain size upon crystallization of a semiconductor film, it is preferable to use a solid-state laser capable of continuously oscillating and applying second to fourth harmonics of the fundamental wave. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of a Nd:YVO4 laser (the fundamental is 1064 nm) is applied.
在使用連續波雷射的例子中，藉由非線性光學元件將從具有10W輸出的連續波YVO4雷射發出之雷射光轉換成諧波。此外，具有將YVO4晶體和非線性光學元件放在振盪器中及發出高諧波之方法。然後，藉由光學系統形成在照射表面上之具有矩形形狀或橢圓形狀的雷射光，及發射到欲處理的物體。此時，需要約0.01至100MW/cm2的能量密度(0.1至10MW/cm2較佳)。可藉由以約10至2000cm/s的速率相對雷射光移動半導體，而執行對半導體膜的照射。In the example using continuous wave laser, the laser light emitted from a continuous wave YVO4 laser having a 10 W output is converted into a harmonic by a nonlinear optical element. In addition, there is a method of placing a YVO4 crystal and a nonlinear optical element in an oscillator and emitting a high harmonic. Then, laser light having a rectangular shape or an elliptical shape formed on the illuminated surface by the optical system is emitted and emitted to the object to be processed. At this time, an energy density of about 0.01 to 100 MW/cm2 (preferably 0.1 to 10 MW/cm2 ) is required. Irradiation of the semiconductor film can be performed by moving the semiconductor relative to the laser light at a rate of about 10 to 2000 cm/s.
接著，除了以上述雷射光照射所形成的氧化物膜之外，使用具有總厚度1至5nm的氧化物膜所形成之屏障層係以臭氧水表面處理達120秒所形成的。屏障層係為了從膜去除為了使非晶矽膜結晶所添加之催化元素(如、鎳(Ni))所形成的。雖然此處屏障層係使用臭氧水所形成的，但是可以下面方法來形成屏障層：在氧大氣中，藉由以UV射線照射來氧化具有結晶結構的半導體膜之表面的方法；藉由氧電漿處理、電漿CVD、濺鍍、蒸發法等來氧化具有結晶結構的半導體膜之表面的方法，而沈積具有厚度約1至10nm之氧化物膜來形成屏障層。另一選擇是，可在形成屏障層之前去除以雷射光照射所形成的氧化物膜。Next, in addition to the oxide film formed by the above-described laser light irradiation, a barrier layer formed using an oxide film having a total thickness of 1 to 5 nm was formed by surface treatment with ozone water for 120 seconds. The barrier layer is formed by removing a catalytic element (for example, nickel (Ni)) added to crystallize the amorphous ruthenium film from the film. Although the barrier layer is formed using ozone water, the barrier layer may be formed by a method of oxidizing the surface of the semiconductor film having a crystalline structure by irradiation with UV rays in an oxygen atmosphere; A method of oxidizing the surface of a semiconductor film having a crystalline structure by slurry treatment, plasma CVD, sputtering, evaporation, or the like, and depositing an oxide film having a thickness of about 1 to 10 nm to form a barrier layer. Alternatively, the oxide film formed by the irradiation of the laser light may be removed prior to forming the barrier layer.
然後，藉由濺鍍，在屏障層上以厚度10至400nm，此處為100nm形成充作除氣地點之包括氬元素的非晶矽膜。使用矽目標，在包括氬的大氣之下形成包括氬元素的非晶矽膜。在藉由電漿CVD形成包括氬元素的非晶矽膜之例子中，沈積條件如下：甲矽烷對氬(SiH4:Ar)的流率是1:99，沈積壓力是6.665Pa，RF功率密度是0.087W/cm2，及沈積溫度是350℃。Then, an amorphous germanium film containing an argon element as a degassing site is formed on the barrier layer by sputtering at a thickness of 10 to 400 nm, here 100 nm. Using an ruthenium target, an amorphous ruthenium film including an argon element is formed under an atmosphere including argon. In the example of forming an amorphous tantalum film including an argon element by plasma CVD, the deposition conditions are as follows: a flow rate of methotane to argon (SiH4 : Ar) is 1:99, a deposition pressure is 6.665 Pa, and an RF power density It is 0.087 W/cm2 and the deposition temperature is 350 °C.
之後，將形成包括氬元素的非晶矽膜之基板置放在以650℃加熱的爐中，及執行熱處理達三分鐘以去除催化元素(除氣)。因此，減少具有結晶結構之半導體膜中的催化元素濃度。可使用燈退火設備取代爐具。Thereafter, a substrate on which an amorphous germanium film including an argon element was formed was placed in a furnace heated at 650 ° C, and heat treatment was performed for three minutes to remove catalytic elements (degassing). Therefore, the concentration of the catalytic element in the semiconductor film having a crystalline structure is reduced. Lamp annealing equipment can be used instead of the stove.
接著，在使用屏障層當作蝕刻停止器，以選擇性去除除氣地點之包括氬元素的非晶矽膜之後，以稀釋的氫氟酸選擇性去除屏障層。需注意的是，因為在除氣時鎳具有移動到具有高氧濃度的區域之傾向，所以在除氣之後去除使用氧化物膜所形成的屏障層較佳。Next, after the barrier layer is used as an etch stopper to selectively remove the amorphous germanium film including the argon element at the degassing site, the barrier layer is selectively removed with diluted hydrofluoric acid. It is to be noted that since nickel has a tendency to move to a region having a high oxygen concentration at the time of degassing, it is preferable to remove the barrier layer formed using the oxide film after degassing.
在未使用催化元素而執行半導體膜的結晶之例子中，不需要諸如形成屏障層、形成除氣地點、除氣用的加熱處理、去除除氣地點、及去除屏障層等上述步驟。In the example in which the crystallization of the semiconductor film is performed without using the catalytic element, the above steps such as formation of a barrier layer, formation of a degassing place, heat treatment for degassing, removal of a degassing place, and removal of a barrier layer are not required.
接著，在使用臭氧水於所獲得的具有結晶結構之半導體膜(如、結晶矽膜)的表面上形成薄氧化物膜之後，使用第一光遮罩形成從抗蝕劑所形成的遮罩，及執行蝕刻，以將半導體膜處理成想要的形狀，及形成被分成島型的半導體膜(在此說明書中，意指島型半導體區331)(見圖8A)。在形成島型半導體區之後，去除從抗蝕劑所形成的遮罩。Next, after forming a thin oxide film on the surface of the obtained semiconductor film having a crystalline structure (for example, a crystalline germanium film) using ozone water, a mask formed from the resist is formed using the first light mask, Etching is performed to process the semiconductor film into a desired shape, and to form a semiconductor film divided into island types (in this specification, the island-shaped semiconductor region 331) (see FIG. 8A). After the formation of the island-shaped semiconductor region, the mask formed from the resist is removed.
接著，若需要的話，以少量雜質元素(如、硼或磷)摻雜島型半導體區，以控制薄膜電晶體的臨界電壓。此處，使用由電漿激發而非質量分離二硼烷(B2H6)之離子摻雜法。Next, if necessary, the island-type semiconductor region is doped with a small amount of impurity elements (e.g., boron or phosphorus) to control the threshold voltage of the thin film transistor. Here, an ion doping method in which diborane (B2 H6 ) is excited by plasma rather than mass is used.
接著，以包括氫氟酸的蝕刻劑去除氧化物膜，同時，清洗島型半導體區331的表面。之後，形成包括矽當作主要成分的絕緣膜，其充作閘極絕緣膜313。此處，藉由電漿CVD以厚度115nm形成包括氮的氧化矽膜(組成比：Si=32%，O=59%，N=7%，及H=2%)。Next, the oxide film is removed by an etchant including hydrofluoric acid while cleaning the surface of the island-shaped semiconductor region 331. Thereafter, an insulating film including ruthenium as a main component is formed, which is filled as a gate insulating film 313. Here, a hafnium oxide film including nitrogen was formed by plasma CVD at a thickness of 115 nm (composition ratio: Si = 32%, O = 59%, N = 7%, and H = 2%).
接著，在於閘極絕緣膜313上形成金屬膜之後，使用第二光遮罩來形成閘極電極334、佈線314及315、和終端電極350(見圖8B)。例如，具有厚度30nm的氮化鉭和具有厚度370nm的鎢(W)之疊層膜被用於金屬膜。Next, after the metal film is formed on the gate insulating film 313, the gate electrode 334, the wirings 314 and 315, and the terminal electrode 350 (see FIG. 8B) are formed using the second photomask. For example, a laminated film having tantalum nitride having a thickness of 30 nm and tungsten (W) having a thickness of 370 nm is used for the metal film.
當作閘極電極334、佈線314及315、和終端電極350，由元素鈦(Ti)、鎢(W)、鉭(Ta)、鉬(Mo)、釹(Nd)、鈷(Co)、鋯(Zr)、鋅(Zn)、釕(Ru)、銠(Rh)、鈀(Pd)、鋨(Os)、銥(Ir)、鉑(Pt)、鋁(Al)、金(Au)、銀(Ag)、或銅(Cu)所形成的單層膜，或包括上述元素當作主要成分之合金材料或化合物材料；也可如上述膜一般使用由其氮化物所形成的單層膜，諸如氮化鈦、氮化鎢、氮化鉭、或氮化鉬等。As the gate electrode 334, the wirings 314 and 315, and the terminal electrode 350, the elements are titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), niobium (Nd), cobalt (Co), zirconium. (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), silver a single layer film formed of (Ag) or copper (Cu), or an alloy material or a compound material including the above elements as a main component; a film of a single layer formed of a nitride thereof may also be generally used as the above film, such as Titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride.
接著，給予一導電性類型之雜質被引進島型半導體區331，以形成TFT 113的源極區和汲極區337(見圖8C)。在此實施例模式中，形成n通道TFT，及將諸如磷(P)或砷(As)等n型雜質引進島型半導體區331內。Next, an impurity of a conductivity type is introduced into the island-type semiconductor region 331 to form a source region and a drain region 337 of the TFT 113 (see Fig. 8C). In this embodiment mode, an n-channel TFT is formed, and an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the island-type semiconductor region 331.
接著，在藉由CVD以厚度50nm形成包括氧化矽膜的第一中間層絕緣膜(未圖示)之後，執行使添加到各個島型半導體區的雜質元素活化之處理。此活化處理係由使用閃光燈源之快速熱退火法(RTA法)、利用YAG雷射或準分子雷射從基板的背面照射之方法、使用加熱爐的熱處理、或組合上述方法的任一種之方法所執行的。Next, after the first interlayer insulating film (not shown) including the hafnium oxide film is formed by CVD at a thickness of 50 nm, a process of activating the impurity elements added to the respective island-type semiconductor regions is performed. The activation treatment is a rapid thermal annealing method using an flash source (RTA method), a method of irradiating from the back surface of the substrate by YAG laser or excimer laser, a heat treatment using a heating furnace, or a combination of any of the above methods. Executed.
接著，以厚度例如10nm形成包括氫和氧的氮化矽膜之第二中間層絕緣膜316。Next, a second interlayer insulating film 316 of a tantalum nitride film including hydrogen and oxygen is formed in a thickness of, for example, 10 nm.
接著，在第二中間層絕緣膜316上形成使用絕緣材料所形成之第三中間層絕緣膜317(見圖8D)。藉由CVD所獲得的絕緣膜可被用於第三中間層絕緣膜317。在此實施例模式中，為了提高黏著性，以厚度900nm形成包括氮的氧化矽膜當作第三中間層絕緣膜317。Next, a third interlayer insulating film 317 formed using an insulating material is formed on the second interlayer insulating film 316 (see FIG. 8D). An insulating film obtained by CVD can be used for the third interlayer insulating film 317. In this embodiment mode, in order to improve the adhesion, a hafnium oxide film including nitrogen is formed as a third interlayer insulating film 317 at a thickness of 900 nm.
接著，執行熱處理(在300至550℃中熱處理達1至12小時，例如、在氮大氣中以410℃熱處理1小時)，以氫化島型半導體區331。執行此步驟以藉由包括在第二中間層絕緣膜316中的氫來終止島型半導體區331之懸鍵。不管是否形成閘極絕緣膜313都可氫化島型半導體區331。Next, heat treatment (heat treatment at 300 to 550 ° C for 1 to 12 hours, for example, heat treatment at 410 ° C for 1 hour in a nitrogen atmosphere) is performed to hydrogenate the island-shaped semiconductor region 331. This step is performed to terminate the dangling bonds of the island-type semiconductor region 331 by hydrogen included in the second interlayer insulating film 316. The island-shaped semiconductor region 331 can be hydrogenated regardless of whether or not the gate insulating film 313 is formed.
另一選擇是，當作第三中間層絕緣膜317，使用矽氧烷的絕緣膜和其疊層結構能夠被使用。使用矽(Si)和氧(O)的鍵之骨架結構形成矽氧烷。包括至少氫(如、烷基或芳香碳氫化合物)的有機基被使用當作取代基。另一選擇是，可使用氟當作有機基。Alternatively, as the third interlayer insulating film 317, an insulating film using a decane and a laminated structure thereof can be used. The skeleton structure of the bond of cerium (Si) and oxygen (O) is used to form a decane. An organic group including at least hydrogen (e.g., an alkyl group or an aromatic hydrocarbon) is used as a substituent. Alternatively, fluorine can be used as the organic group.
在使用矽氧烷的絕緣膜和其疊層結構當作第三中間層絕緣膜317之例子中，在形成第二中間層絕緣膜316之後，執行用以氫化島型半導體區331的熱處理，然後能夠形成第三中間層絕緣膜317。In the example in which the insulating film of the siloxane and the laminated structure thereof are used as the third interlayer insulating film 317, after the second interlayer insulating film 316 is formed, heat treatment for hydrogenating the island-shaped semiconductor region 331 is performed, and then The third interlayer insulating film 317 can be formed.
接著，使用第三光遮罩來形成從抗蝕劑所形成之遮罩，及選擇性蝕刻第一中間層絕緣膜、第二中間層絕緣膜316、第三中間層絕緣膜317、和閘極絕緣膜313以形成接觸孔。然後，去除從抗蝕劑所形成之遮罩。Next, a mask formed from the resist is formed using the third photomask, and the first interlayer insulating film, the second interlayer insulating film 316, the third interlayer insulating film 317, and the gate are selectively etched. The insulating film 313 is formed to form a contact hole. Then, the mask formed from the resist is removed.
需注意的是，第三中間層絕緣膜317可視需要來形成。在未形成第三中間層絕緣膜317的例子中，在形成第二中間層絕緣膜316之後，選擇性蝕刻第一中間層絕緣膜、第二中間層絕緣膜316、和閘極絕緣膜313以形成接觸孔。It is to be noted that the third interlayer insulating film 317 can be formed as needed. In the example in which the third interlayer insulating film 317 is not formed, after the second interlayer insulating film 316 is formed, the first interlayer insulating film, the second interlayer insulating film 316, and the gate insulating film 313 are selectively etched to A contact hole is formed.
接著，在以濺鍍形成金屬堆疊膜之後，使用第四光遮罩來形成從抗蝕劑所形成之遮罩，及選擇性蝕刻金屬膜以形成TFT 113的佈線319、連接電極320、終端電極351、和源極電極或汲極電極341。然後，去除從抗蝕劑所形成之遮罩。需注意的是，此實施例模式的金屬膜是三層的疊層膜：厚度100nm的Ti膜、厚度350nm之包括少量Si的Al膜、及厚度100nm的Ti膜。Next, after the metal stacked film is formed by sputtering, a mask formed of the resist is formed using the fourth photomask, and the wiring 319 for selectively etching the metal film to form the TFT 113, the connection electrode 320, and the terminal electrode are formed. 351, and a source electrode or a drain electrode 341. Then, the mask formed from the resist is removed. It is to be noted that the metal film of this embodiment mode is a three-layer laminated film: a Ti film having a thickness of 100 nm, an Al film including a small amount of Si having a thickness of 350 nm, and a Ti film having a thickness of 100 nm.
此外，在TFT 113的佈線319、連接電極320、終端電極351、和源極電極或汲極電極341每一個係由單層導電膜所形成之例子中，就耐熱性、導電性等而言，鈦(Ti膜)較佳。可使用由選自鎢(W)、鉭(Ta)、鉬(Mo)、釹(Nd)、鈷、(Co)、鋯(Zr)、鋅(Zn)、釕(Ru)、銠(Rh)、鈀(Pd)、鋨(Os)、銥(Ir)、及鉑(Pt)所形成的單層膜，或包含上述元素當作其主要成分之合金材料或化合物材料；諸如氮化鈦、氮化鎢、氮化鉭、或氮化鉬等從其氮化物所形成之單層膜來取代鈦膜。藉由形成TFT 113的佈線319、連接電極320、終端電極351、及源極電極或汲極電341每一個當作單層膜，在製造處理中可減少沈積步驟的數目。Further, in the example in which the wiring 319 of the TFT 113, the connection electrode 320, the terminal electrode 351, and the source electrode or the gate electrode 341 are each formed of a single-layer conductive film, in terms of heat resistance, conductivity, and the like, Titanium (Ti film) is preferred. It can be selected from the group consisting of tungsten (W), tantalum (Ta), molybdenum (Mo), niobium (Nd), cobalt, (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh). a single layer film formed of palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt), or an alloy material or a compound material containing the above elements as its main component; such as titanium nitride, nitrogen The titanium film is replaced by a single layer film formed of a nitride such as tungsten, tantalum nitride, or molybdenum nitride. By forming the wiring 319 of the TFT 113, the connection electrode 320, the terminal electrode 351, and the source electrode or the gate electrode 341 as a single layer film, the number of deposition steps can be reduced in the manufacturing process.
經由上述處理可製造使用多晶矽膜的頂部閘TFT 113。The top gate TFT 113 using a polysilicon film can be manufactured through the above process.
接著，在形成不容易由於與稍後形成之光電轉換層(典型上是非晶矽)作用而變成合金的導電金屬膜(如、鈦(Ti)或鉬(Mo))之後，使用第五光遮罩形成從抗蝕劑所形成之遮罩，及選擇性蝕刻導電金屬膜以形成覆蓋佈線319之保護電極318(見圖9A)。此處，使用以濺鍍所獲得之厚度200nm的Ti膜。需注意的是，分別以導電金屬膜之保護電極345、346、及348覆蓋TFT 113的連接電極320、終端電極351、及源極電極和汲極電極341。因此，導電金屬膜亦覆蓋在這些電極中露出的第二層中之Al膜的側面，使得導電金屬膜亦能夠防止鋁原子擴散到光電轉換層。Next, after forming a conductive metal film (for example, titanium (Ti) or molybdenum (Mo)) which is not easily alloyed by the action of a photoelectric conversion layer (typically an amorphous germanium) formed later, the fifth light is used. The mask forms a mask formed from the resist, and selectively etches the conductive metal film to form a protective electrode 318 covering the wiring 319 (see FIG. 9A). Here, a Ti film having a thickness of 200 nm obtained by sputtering was used. It is to be noted that the connection electrode 320, the terminal electrode 351, and the source electrode and the drain electrode 341 of the TFT 113 are covered with the protective electrodes 345, 346, and 348 of the conductive metal film, respectively. Therefore, the conductive metal film also covers the side faces of the Al film in the second layer exposed in these electrodes, so that the conductive metal film can also prevent diffusion of aluminum atoms to the photoelectric conversion layer.
需注意的是，在TFT 113的佈線319、連接電極320、終端電極351、和源極電極或汲極電極341每一個被形成當作單層導電膜之例子中，不一定要形成保護電極318、345、346、及348。It is to be noted that in the example in which the wiring 319 of the TFT 113, the connection electrode 320, the terminal electrode 351, and the source electrode or the gate electrode 341 are each formed as a single-layer conductive film, the protective electrode 318 does not have to be formed. , 345, 346, and 348.
接著，將包括p型半導體層111p、i型半導體層111i、及n型半導體層111n的光電轉換層111形成在第三中間層絕緣膜317上。Next, a photoelectric conversion layer 111 including a p-type semiconductor layer 111p, an i-type semiconductor layer 111i, and an n-type semiconductor layer 111n is formed on the third interlayer insulating film 317.
可藉由電漿CVD，使用包括諸如硼(B)等屬於週期表中的第13族之雜質元素的半非晶矽膜，而形成p型半導體層111p。The p-type semiconductor layer 111p can be formed by plasma CVD using a semi-amorphous germanium film including an impurity element such as boron (B) belonging to Group 13 of the periodic table.
需注意的是，佈線319與保護電極318與光電轉換層111的底層，即、此實施例模式中的p型半導體層111p，接觸。It is to be noted that the wiring 319 and the protective electrode 318 are in contact with the underlayer of the photoelectric conversion layer 111, that is, the p-type semiconductor layer 111p in this embodiment mode.
在形成p型半導體層111p之後，隨後形成i型半導體層111i、及n型半導體層111n。因此，形成包括p型半導體層111p、i型半導體層111i、及n型半導體層111n的光電轉換層111。After the p-type semiconductor layer 111p is formed, the i-type semiconductor layer 111i and the n-type semiconductor layer 111n are subsequently formed. Thus, the photoelectric conversion layer 111 including the p-type semiconductor layer 111p, the i-type semiconductor layer 111i, and the n-type semiconductor layer 111n is formed.
當作i型半導體層111i，例如可藉由電漿CVD來形成半非晶矽膜。此外，當作n型半導體層111n，可形成包括諸如磷(P)等屬於週期表中的第15族之雜質元素的半非晶矽膜，另一選擇是，在形成半非晶矽膜之後，可引進屬於週期表中的第15族之雜質元素。As the i-type semiconductor layer 111i, a semi-amorphous germanium film can be formed, for example, by plasma CVD. Further, as the n-type semiconductor layer 111n, a semi-amorphous germanium film including an impurity element belonging to Group 15 of the periodic table such as phosphorus (P) may be formed, and another option is to form a semi-amorphous germanium film. It is possible to introduce an impurity element belonging to Group 15 of the periodic table.
另一選擇是，非晶半導體膜與半非晶半導體膜可被用於p型半導體層111p、i型半導體層111i、及n型半導體層111n。Alternatively, an amorphous semiconductor film and a semi-amorphous semiconductor film can be used for the p-type semiconductor layer 111p, the i-type semiconductor layer 111i, and the n-type semiconductor layer 111n.
接著，在產生圖9B所示之結構的整個表面上以厚度1至30nm形成從絕緣材料(如、包括矽的無機絕緣膜)所形成的密封層324。此處，當作絕緣材料膜，以CVD形成具有厚度1μm之包括氮之氧化矽膜。藉由使用以CVD所形成之絕緣膜，可提高黏著性。Next, a sealing layer 324 formed of an insulating material (e.g., an inorganic insulating film including germanium) is formed on the entire surface of the structure shown in Fig. 9B to a thickness of 1 to 30 nm. Here, as the insulating material film, a cerium oxide film including nitrogen having a thickness of 1 μm was formed by CVD. Adhesion can be improved by using an insulating film formed by CVD.
接著，在蝕刻密封層324以提供開口部之後，藉由濺鍍來形成終端電極121及122。各個終端電極121及122係由鈦膜(Ti膜)(100nm)、鎳膜(Ni膜)(300nm)、及金膜(Au膜)(50nm)的疊層膜所形成。以此方式所獲得的終端電極121及122具有高於5N的固定強度，此5N的固定強度是足夠當作終端電極的固定強度。Next, after the sealing layer 324 is etched to provide an opening, the terminal electrodes 121 and 122 are formed by sputtering. Each of the terminal electrodes 121 and 122 is formed of a laminated film of a titanium film (Ti film) (100 nm), a nickel film (Ni film) (300 nm), and a gold film (Au film) (50 nm). The terminal electrodes 121 and 122 obtained in this manner have a fixing strength higher than 5 N, and the fixing strength of this 5 N is sufficient as the fixing strength of the terminal electrode.
藉由上述處理，形成能夠由焊料來連接之終端電極121和終端電極122，及可獲得圖9C所示之結構。By the above processing, the terminal electrode 121 and the terminal electrode 122 which can be connected by solder are formed, and the structure shown in Fig. 9C can be obtained.
需注意的是，可將基板切割成個別段以獲得複數光電轉換電路元件，使得可大量生產經由上述步驟所獲得的光電轉換電路。可從一大基板(如、600cm x 720cm)製造出許多光電轉換元件(如、2mm x 1.5mm)。It is to be noted that the substrate can be cut into individual segments to obtain a plurality of photoelectric conversion circuit elements, so that the photoelectric conversion circuit obtained through the above steps can be mass-produced. Many photoelectric conversion elements (eg, 2mm x 1.5mm) can be fabricated from a large substrate (eg, 600cm x 720cm).
需注意的是，當作此實施例模式所示之島型半導體區331的製造方法，可利用其他製造方法，並不侷限於上述製造方法。例如，可藉由使用SOI(絕緣體上矽晶片)基板來形成島型半導體區331。只要使用已知的SOI基板當作SOI基板是可以接受的，則並不將其結構和製造方法特別侷限於特定類型。當作SOI基板，典型上可指定SIMOX基板和接合基板。此外，接合基板的例子是ELTRAN(註冊商標)、UNIBOND(註冊商標)、Smart Cut(註冊商標)等。It should be noted that as a method of manufacturing the island-type semiconductor region 331 shown in this embodiment mode, other manufacturing methods can be utilized, and it is not limited to the above-described manufacturing method. For example, the island-shaped semiconductor region 331 can be formed by using an SOI (insulator on-wafer) substrate. As long as the use of a known SOI substrate as an SOI substrate is acceptable, its structure and manufacturing method are not particularly limited to a particular type. As the SOI substrate, a SIMOX substrate and a bonded substrate can be typically specified. Further, examples of the bonded substrate are ELTRAN (registered trademark), UNIBOND (registered trademark), and Smart Cut (registered trademark).
在SIMOX基板的例子中，將氧離子佈植到單晶矽基板內，及執行1300℃或更多的熱處理，以形成埋藏氧化物(BOX)層；因此，薄膜矽層被形成在單晶矽基板的表面上，及可獲得SOI結構。利用埋藏氧化物膜層將薄膜矽層與單晶矽基板絕緣。另外，在形成埋藏氧化物膜層之後，可使用執行更進一步的熱氧化之稱作ITOX(內部熱氧化)的技術。In the example of the SIMOX substrate, oxygen ions are implanted into the single crystal germanium substrate, and heat treatment at 1300 ° C or more is performed to form a buried oxide (BOX) layer; therefore, the thin film germanium layer is formed in the single crystal germanium. On the surface of the substrate, an SOI structure can be obtained. The thin film tantalum layer is insulated from the single crystal germanium substrate by a buried oxide film layer. Further, after forming the buried oxide film layer, a technique called ITOX (internal thermal oxidation) which performs further thermal oxidation can be used.
接合基板是SOI基板，其利用氧化物膜層插入在其間而接合兩單晶矽基板(第一單晶矽基板和第二單晶矽基板)，及在與接合側相對的側之表面上使單晶矽基板的其中之一變薄，藉以將薄膜矽層形成在單晶矽基板的表面上。氧化物膜層係可藉由熱氧化基板的其中之一(此處為第一單晶矽基板)所形成的。另外，可不使用黏著劑而直接接合兩單晶矽基板。The bonding substrate is an SOI substrate which is bonded between the two single crystal germanium substrates (the first single crystal germanium substrate and the second single crystal germanium substrate) by the oxide film layer interposed therebetween, and is formed on the surface on the side opposite to the bonding side. One of the single crystal germanium substrates is thinned to form a thin film tantalum layer on the surface of the single crystal germanium substrate. The oxide film layer can be formed by thermally oxidizing one of the substrates (here, the first single crystal germanium substrate). Further, the two single crystal germanium substrates can be directly bonded without using an adhesive.
當作接合基板，可藉由接合具有絕緣表面的玻璃基板、撓性基板等和單晶半導體基板來形成SOI基板，並不局限於接合兩單晶半導體基板。參考圖10A至10D來說明藉由接合玻璃基板和單晶半導體基板所形成之SOI基板。As the bonding substrate, the SOI substrate can be formed by bonding a glass substrate having an insulating surface, a flexible substrate, or the like to a single crystal semiconductor substrate, and is not limited to bonding the two single crystal semiconductor substrates. An SOI substrate formed by bonding a glass substrate and a single crystal semiconductor substrate will be described with reference to FIGS. 10A to 10D.
清洗圖10A所示之單晶半導體基板1101，添加以電場加速的離子到達距半導體基板1101的表面之預定深度，以形成削弱層1103。考慮將轉移到基座基板的半導體膜之厚度來添加離子。半導體膜的厚度被設定成5nm至500nm，10nm至200nm較佳，10nm至100nm更好，及10nm至50nm也不錯。考慮此種厚度來設定添加離子到單晶半導體基板1101的加速電壓。因為在分離之後藉由拋光或熔化來平坦化半導體膜的表面，所以緊接在分離之後的半導體膜之厚度被設定成50nm至500nm較佳。The single crystal semiconductor substrate 1101 shown in FIG. 10A is cleaned, and ions accelerated by an electric field are added to a predetermined depth from the surface of the semiconductor substrate 1101 to form a weakened layer 1103. Ions are added in consideration of the thickness of the semiconductor film transferred to the base substrate. The thickness of the semiconductor film is set to 5 nm to 500 nm, preferably 10 nm to 200 nm, more preferably 10 nm to 100 nm, and 10 nm to 50 nm. The acceleration voltage of the added ions to the single crystal semiconductor substrate 1101 is set in consideration of such a thickness. Since the surface of the semiconductor film is planarized by polishing or melting after the separation, the thickness of the semiconductor film immediately after the separation is preferably set to 50 nm to 500 nm.
削弱層1103係藉由添加氫、氦、或以氟為代表之鹵素的離子所形成的。在此例中，添加一種離子或包含單一種原子之不同質量數的複數種離子較佳。在添加氫離子的例子中，氫離子包括具有高比例的H3+離子之H+、H2+、及H3+離子較佳。由於高比例的H3+離子，可增加添加效率和可縮短添加時間。此結構使得稍後能夠容易地執行削弱層1103中的分離。The weakening layer 1103 is formed by adding hydrogen, helium, or an ion of a halogen represented by fluorine. In this case, it is preferred to add an ion or a plurality of ions comprising different mass numbers of a single atom. In the case of adding a hydrogen ion, it is preferable that the hydrogen ion include H+ , H2+ , and H3+ ions having a high proportion of H3+ ions. Due to the high proportion of H3+ ions, the addition efficiency can be increased and the addition time can be shortened. This structure makes it possible to easily perform the separation in the weakening layer 1103 later.
在將離子添加到單晶半導體基板1101的例子中，需要以高劑量條件添加離子，如此在一些例子中，單晶半導體基板1101的表面變得粗糙。因此，藉由在添加離子之表面上使用具有厚度50nm至200nm的氧化矽層、氮化矽層、氧氮化矽層等來形成防止離子添加的保護層較佳，以防止表面被離子摻雜破壞和失去平坦性。In the example of adding ions to the single crystal semiconductor substrate 1101, it is necessary to add ions at a high dose condition, so that in some examples, the surface of the single crystal semiconductor substrate 1101 becomes rough. Therefore, it is preferable to form a protective layer for preventing ion addition by using a yttrium oxide layer having a thickness of 50 nm to 200 nm, a tantalum nitride layer, a hafnium oxynitride layer or the like on the surface of the added ions to prevent the surface from being doped with ions. Destruction and loss of flatness.
接著，如圖10B所示，在單晶半導體基板1101的表面上設置壓力接合材料1122。然後，單晶半導體基板1101和壓力接合材料1122彼此裝附和加熱，也就是說，執行熱處理和壓力處理，藉以藉由在稍後步驟中使用削弱層1103當作裂面，而容易地分離單晶半導體基板1101與玻璃基板1100。熱處理的溫度是低於削弱層1103裂開以及削弱層1103變弱之溫度較佳，例如，當在低於400℃、低於350℃較佳、或低於300℃更好的溫度中執行熱處理時，削弱層1103中所形成的微小空腔之體積改變；然而，因為在單晶半導體基板的表面上設置壓力接合材料1122，所以能夠將單晶半導體基板的表面保持平坦。結果，削弱層1103中之微小空腔的體積變化產生削弱層1103的變形，及將沿著削弱層1103的單晶半導體基板1101變弱。執行壓力處理，以便在考慮玻璃基板1100和單晶半導體基板1101的抗壓性之下，垂直地施加壓力到接合表面。Next, as shown in FIG. 10B, a pressure bonding material 1122 is provided on the surface of the single crystal semiconductor substrate 1101. Then, the single crystal semiconductor substrate 1101 and the pressure bonding material 1122 are attached and heated to each other, that is, heat treatment and pressure treatment are performed, whereby the single crystal is easily separated by using the weakened layer 1103 as a cracked surface in a later step. The semiconductor substrate 1101 and the glass substrate 1100. The temperature of the heat treatment is preferably lower than the temperature at which the weakened layer 1103 is cleaved and the weakened layer 1103 is weakened, for example, when the heat treatment is performed at a temperature lower than 400 ° C, preferably lower than 350 ° C, or better than 300 ° C. At the time, the volume of the minute cavity formed in the weakened layer 1103 is changed; however, since the pressure bonding material 1122 is provided on the surface of the single crystal semiconductor substrate, the surface of the single crystal semiconductor substrate can be kept flat. As a result, the volume change of the minute cavity in the weakened layer 1103 causes deformation of the weakened layer 1103, and weakens the single crystal semiconductor substrate 1101 along the weakened layer 1103. Pressure treatment is performed so that pressure is applied perpendicularly to the joint surface under consideration of the pressure resistance of the glass substrate 1100 and the single crystal semiconductor substrate 1101.
如圖10C所示，玻璃基板1100和單晶半導體基板1101彼此裝附並且彼此接合。適當地清洗欲接合的表面。然後，在施加壓力在其上的同時裝附玻璃基板1100和單晶半導體基板1101，藉以將玻璃基板1100和單晶半導體基板1101彼此接合。以Van der Walls力形成接合。藉由將玻璃基板1100和單晶半導體基板1101彼此相對按壓，可藉由氫鍵來形成較強的接合。As shown in FIG. 10C, the glass substrate 1100 and the single crystal semiconductor substrate 1101 are attached to each other and joined to each other. Clean the surface to be joined properly. Then, the glass substrate 1100 and the single crystal semiconductor substrate 1101 are attached while pressure is applied thereto, whereby the glass substrate 1100 and the single crystal semiconductor substrate 1101 are bonded to each other. The joint is formed by Van der Walls force. By pressing the glass substrate 1100 and the single crystal semiconductor substrate 1101 against each other, a strong bond can be formed by hydrogen bonding.
為了獲得令人滿意的接合，可將表面活化較佳。例如，以原子束或離子束照射欲接合的表面。當使用原子束或離子束時，可使用氬等的鈍氣中性原子束或鈍氣離子束。另一選擇是，執行電漿照射或基處理。另外，可將玻璃基板和單晶半導體基板之接合表面的至少其中之一經過氧電漿的處理或以臭氧水清洗以成親水的。此種表面處理即使在低於400℃的溫度中仍能夠容易地執行不同材料種類之間的接合。In order to obtain a satisfactory joint, the surface activation is preferred. For example, the surface to be joined is irradiated with an atomic beam or an ion beam. When an atomic beam or an ion beam is used, an blunt neutral atomic beam or an obtuse gas ion beam of argon or the like can be used. Another option is to perform plasma irradiation or base treatment. In addition, at least one of the bonding surfaces of the glass substrate and the single crystal semiconductor substrate may be subjected to treatment with an oxygen plasma or with ozone water to be hydrophilic. Such surface treatment can easily perform bonding between different material types even at temperatures lower than 400 °C.
取代在將玻璃基板1100與單晶半導體基板1101彼此接合之前已執行的熱處理，在將玻璃基板1100與單晶半導體基板1101彼此接合之後，可以來自玻璃基板1100側的雷射光束照射單晶半導體基板1101，以加熱削弱層1103。結果，使削弱層變弱，以及可藉由使用削弱層當作裂面，而將單晶半導體基板1101與玻璃基板1100分開。Instead of the heat treatment performed before the glass substrate 1100 and the single crystal semiconductor substrate 1101 are bonded to each other, after the glass substrate 1100 and the single crystal semiconductor substrate 1101 are bonded to each other, the laser beam from the glass substrate 1100 side may be irradiated to the single crystal semiconductor substrate. 1101, to weaken the layer 1103 by heating. As a result, the weakened layer is weakened, and the single crystal semiconductor substrate 1101 can be separated from the glass substrate 1100 by using the weakened layer as a cracked surface.
如圖10D所示，在將玻璃基板1100與單晶半導體基板1101彼此接合之後，使用削弱層當作裂面，而將單晶半導體基板1101與玻璃基板1100分開，使得能夠獲得SOI基板。因為將單晶半導體基板1101的表面與玻璃基板1100彼此接合，所以將晶性與單晶半導體1101的晶性相同之半導體膜1102留在玻璃基板1100上。As shown in FIG. 10D, after the glass substrate 1100 and the single crystal semiconductor substrate 1101 are bonded to each other, the weakened layer is used as a cracked surface, and the single crystal semiconductor substrate 1101 is separated from the glass substrate 1100, so that the SOI substrate can be obtained. Since the surface of the single crystal semiconductor substrate 1101 and the glass substrate 1100 are bonded to each other, the semiconductor film 1102 having the same crystallinity as that of the single crystal semiconductor 1101 is left on the glass substrate 1100.
在使用削弱層當作裂面而將單晶半導體基板1101與玻璃基板1100分開之前，提供用以容易分離之觸發器較佳。尤其是，執行用以降低選擇的(部分)削弱層1103和半導體膜1102之黏著性，使得降低分離缺陷和提高產量。典型上，例如，藉由執行來自玻璃基板1100側或單晶半導體基板1101側的雷射光束照射或藉由使用晶粒切割器，而在削弱層1103中形成溝槽。It is preferable to provide a flip-flop for easy separation before separating the single crystal semiconductor substrate 1101 from the glass substrate 1100 using the weakened layer as a crack face. In particular, adhesion to reduce the selected (partial) weakened layer 1103 and the semiconductor film 1102 is performed, so that separation defects are reduced and yield is improved. Typically, a trench is formed in the weakened layer 1103 by, for example, performing laser beam irradiation from the side of the glass substrate 1100 or the side of the single crystal semiconductor substrate 1101 or by using a die cutter.
當單晶半導體基板1101與玻璃基板1100分開時，為玻璃基板1100和單晶半導體基板1101之表面的至少其中之一設置由光或熱可分離的黏著板，以固定玻璃基板1100和單晶半導體基板1101的其中之一個，而分離其中另一個，使得能夠更容易執行分離。在那時，藉由提供支撐構件給單晶半導體基板1101與玻璃基板1100的其中另一個，可容易地完成分離處理。When the single crystal semiconductor substrate 1101 is separated from the glass substrate 1100, an optical or heat-separable adhesive sheet is provided for at least one of the surfaces of the glass substrate 1100 and the single crystal semiconductor substrate 1101 to fix the glass substrate 1100 and the single crystal semiconductor. One of the substrates 1101 is separated from the other, so that separation can be performed more easily. At that time, the separation process can be easily performed by providing the support member to the other of the single crystal semiconductor substrate 1101 and the glass substrate 1100.
藉由化學機械拋光(CMP)將以分離所獲得的半導體膜之表面拋光成平坦面較佳。另一選擇是，可藉由以雷射光束照射半導體膜的表面來取代使用諸如CMP等物理拋光機構而執行平坦化。需注意的是，在具有10ppm或更低的氧濃度之氮大氣下下實施雷射光束照射較佳。這是因為若在氧大氣之下執行雷射光束的照射，則會使半導體膜的表面粗糙。此外，為了降低所獲得的半導體膜之厚度，可執行CMP等。It is preferable to polish the surface of the semiconductor film obtained by the separation into a flat surface by chemical mechanical polishing (CMP). Alternatively, planarization can be performed by irradiating the surface of the semiconductor film with a laser beam instead of using a physical polishing mechanism such as CMP. It is to be noted that it is preferred to perform laser beam irradiation under a nitrogen atmosphere having an oxygen concentration of 10 ppm or less. This is because if the irradiation of the laser beam is performed under an oxygen atmosphere, the surface of the semiconductor film is roughened. Further, in order to reduce the thickness of the obtained semiconductor film, CMP or the like can be performed.
上述說明是藉由將諸如玻璃基板等具有絕緣表面的基板和單晶半導體基板彼此裝附以製造SOI基板之方法。The above description is a method of manufacturing an SOI substrate by attaching a substrate having an insulating surface such as a glass substrate and a single crystal semiconductor substrate to each other.
此外，當作此實施例模式所示之島型半導體區331，可使用微晶半導體膜，而不侷限於多晶半導體膜和單晶半導體膜。Further, as the island-type semiconductor region 331 shown in this embodiment mode, a microcrystalline semiconductor film can be used without being limited to the polycrystalline semiconductor film and the single crystal semiconductor film.
多晶半導體膜是包括中間結構在非晶和結晶(包括單晶和多晶)結構之間的半導體之膜。半導體具有自由能量是穩定之第三狀態，及是具有短範圍等級和晶格變形之結晶物質。可將此半導體分散在具有其晶粒尺寸0.5至20mm之非晶半導體。在微晶半導體的典型例子之微晶矽中，其Raman光譜被位移至比表示單晶矽之521cm-1低的波數目側。也就是說，微晶矽具有在481cm-1和520cm-1之間的Raman光譜之峰值。微晶矽包括至少1at.%的氫或鹵素以終止懸鍵。而且，可包括諸如氦、氬、氪、或氖等稀有氣體元素，以進一步促進晶格變形，使得穩定性增加並且能夠獲得令人滿意的微晶半導體膜。在例如美國專利號碼4,409,134中揭示有關微晶半導體膜的此種說明。A polycrystalline semiconductor film is a film comprising a semiconductor having an intermediate structure between amorphous and crystalline (including single crystal and polycrystalline) structures. A semiconductor has a third state in which free energy is stable, and is a crystalline substance having a short range of levels and lattice deformation. This semiconductor can be dispersed in an amorphous semiconductor having a crystal grain size of 0.5 to 20 mm. In the microcrystalline germanium of a typical example of the microcrystalline semiconductor, the Raman spectrum is shifted to a side closer to the number of waves representing 521 cm-1 of the single crystal germanium. That is, the microcrystalline crucible has a peak of the Raman spectrum between 481 cm-1 and 520 cm-1 . The microcrystalline germanium includes at least 1 at.% hydrogen or halogen to terminate the dangling bonds. Moreover, a rare gas element such as helium, argon, neon, or krypton may be included to further promote lattice deformation, so that stability is increased and a satisfactory microcrystalline semiconductor film can be obtained. Such an explanation regarding a microcrystalline semiconductor film is disclosed in, for example, U.S. Patent No. 4,409,134.
此微晶半導體膜係由具有頻率為幾十MHz至幾百MHz之高頻電漿CVD或具有頻率為1GHz或更多之微波電漿CVD設備所形成。典型上，可藉由以氫稀釋諸如SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4、或SiF4等氫化矽，而形成微晶半導體膜。另一選擇是，除了氫化矽或氫之外，可藉由以選自氦、氮、氪、或氖的一或複數種稀有氣體元素稀釋氫化矽來形成微晶半導體膜。在那時，氫的流率對氫化矽的流率為：大於或等於5倍且小於或等於200倍，大於或等於50倍且小於或等於150倍較佳，100倍更好。The microcrystalline semiconductor film is formed by high frequency plasma CVD having a frequency of several tens of MHz to several hundreds of MHz or a microwave plasma CVD apparatus having a frequency of 1 GHz or more. Typically, a microcrystalline semiconductor film can be formed by diluting hydrogen hydride such as SiH4 , Si2 H6 , SiH2 Cl2 , SiHCl3 , SiCl4 , or SiF4 with hydrogen. Alternatively, the microcrystalline semiconductor film may be formed by diluting the hydrazine hydride with one or more rare gas elements selected from the group consisting of ruthenium, nitrogen, ruthenium, or osmium in addition to ruthenium or hydrogen. At that time, the flow rate of hydrogen to the hydrazine hydride is: 5 times or more and 200 times or less, 50 times or more and 150 times or less, more preferably 100 times.
當未特意添加用以控制價電子的雜質元素時，微晶半導體膜具有弱的n型導電性。因此，在形成微晶半導體膜的同時或之後，可將給予p型導電性的雜質元素添加到充作薄膜電晶體的通道形成區之微晶半導體膜，使得能夠控制臨界電壓。給予p型導電性的雜質元素之典型例子是硼，及以1ppm至1000ppm，1ppm至100ppm更好的比例，將諸如B2H6或BF3等雜質氣體添加到氫化矽。硼的濃度被設定在1 x 1014至6 x 1016atom/cm3較佳。The microcrystalline semiconductor film has weak n-type conductivity when an impurity element for controlling valence electrons is not intentionally added. Therefore, at the same time as or after the formation of the microcrystalline semiconductor film, an impurity element imparting p-type conductivity can be added to the microcrystalline semiconductor film serving as a channel formation region of the thin film transistor, so that the threshold voltage can be controlled. A typical example of the impurity element imparting p-type conductivity is boron, and an impurity gas such as B2 H6 or BF3 is added to the hydrazine hydride in a ratio of preferably 1 ppm to 1000 ppm, more preferably 1 ppm to 100 ppm. The concentration of boron is preferably set at 1 x 1014 to 6 x 1016 atoms/cm3 .
微晶半導體膜中之氧的濃度是5 x 1018cm-3或更低，1 x 1018cm-3或更低較佳。其內之氮和碳的各個濃度是1 x 1019cm-3或更低較佳。藉由降低混合在微晶半導體膜內之氧、氮、及碳的濃度，可防止微晶半導體膜具有n型導電性。The concentration of oxygen in the microcrystalline semiconductor film is 5 x 1018 cm-3 or less, preferably 1 x 1018 cm-3 or less. The respective concentrations of nitrogen and carbon therein are preferably 1 x 1019 cm-3 or less. By reducing the concentrations of oxygen, nitrogen, and carbon mixed in the microcrystalline semiconductor film, the microcrystalline semiconductor film can be prevented from having n-type conductivity.
由微晶半導體膜所製成的島型半導體區331被形成具有厚度大於0nm及小於或等於50nm，大於0nm及小於或等於20nm較佳。微晶半導體膜充作稍後欲形成之薄膜電晶體的通道形成區。藉由將微晶半導體膜的厚度設定在上述範圍中，稍後欲形成的薄膜電晶體變成完全空乏的。此外，因為微晶半導體膜係由微晶體所形成，所以微晶半導體膜的電阻小於非晶半導體膜的電阻。另外，在使用微晶半導體膜的薄膜電晶體之例子中，表示電流電壓特性之曲線的上升之斜率是陡峭的，及提高當作交換元件的反應性和能夠高速操作。此外，藉由將微晶半導體膜用於薄膜電晶體的通道形成區，可抑制薄膜電晶體的臨界電壓之間的變化。因此，可製造具有電特性變化小之液晶顯示裝置等。The island-shaped semiconductor region 331 made of a microcrystalline semiconductor film is formed to have a thickness of more than 0 nm and less than or equal to 50 nm, more preferably greater than 0 nm and less than or equal to 20 nm. The microcrystalline semiconductor film is used as a channel formation region of a thin film transistor to be formed later. By setting the thickness of the microcrystalline semiconductor film in the above range, the thin film transistor to be formed later becomes completely depleted. Further, since the microcrystalline semiconductor film is formed of microcrystals, the electric resistance of the microcrystalline semiconductor film is smaller than that of the amorphous semiconductor film. Further, in the example of the thin film transistor using the microcrystalline semiconductor film, the slope indicating the rise of the current-voltage characteristic curve is steep, and the reactivity as the exchange element is improved and the operation can be performed at a high speed. Further, by using the microcrystalline semiconductor film for the channel formation region of the thin film transistor, variation between the threshold voltages of the thin film transistor can be suppressed. Therefore, a liquid crystal display device or the like having a small change in electrical characteristics can be manufactured.
此外，微晶半導體膜的移動率高於非晶半導體膜的移動率。因此，藉由使用通道形成區係由微晶半導體膜所形成之薄膜電晶體當作顯示元件的開關，可降低通道形成區的面積，即、薄膜電晶體的面積。因此，可降低一像素中之薄膜電晶體的面積，及可提高像素的鏡孔比。結果，能夠製造具有高解析度之裝置。Further, the mobility of the microcrystalline semiconductor film is higher than the mobility of the amorphous semiconductor film. Therefore, by using the thin film transistor formed of the microcrystalline semiconductor film as a switch of the display element, the area of the channel formation region, that is, the area of the thin film transistor can be reduced. Therefore, the area of the thin film transistor in one pixel can be reduced, and the mirror hole ratio of the pixel can be improved. As a result, it is possible to manufacture a device with high resolution.
需注意的是，此實施例模式能夠與此說明書中的其他實施例模式之技術特徵組合。It should be noted that this embodiment mode can be combined with the technical features of other embodiment modes in this specification.
在此實施例模式中，參考橫剖面圖圖示不同於實施例模式2所示之例子的上述實施例模式中所說明之光電轉換電路的製造方法之例子。在此實施例模式中，參考圖11A至11D、圖12A至12C、及圖13說明場效電晶體係由底部閘TFT所形成之結構。In this embodiment mode, an example of a method of manufacturing the photoelectric conversion circuit explained in the above embodiment mode different from the example shown in Embodiment Mode 2 is illustrated with reference to a cross-sectional view. In this embodiment mode, the structure in which the field effect transistor system is formed by the bottom gate TFT will be described with reference to FIGS. 11A to 11D, FIGS. 12A to 12C, and FIG.
首先，基極絕緣膜312和金屬膜511被形成在基板310上(見圖11A)。在此實施例模式中，例如，具有厚度30nm的氮化鉭和具有厚度370nm的鎢(W)之疊層膜被用於金屬膜511。First, a base insulating film 312 and a metal film 511 are formed on the substrate 310 (see FIG. 11A). In this embodiment mode, for example, a laminated film having tantalum nitride having a thickness of 30 nm and tungsten (W) having a thickness of 370 nm is used for the metal film 511.
另一選擇是，可將由選自元素鈦(Ti)、鎢(W)、鉭(Ta)、鉬(Mo)、釹(Nd)、鈷(Co)、鋯(Zr)、鋅(Zn)、釕(Ru)、銠(Rh)、鈀(Pd)、鋨(Os)、銥(Ir)、鉑(Pt)、鋁(Al)、金(Au)、銀(Ag)、或銅(Cu)所形成的單層膜，或包括上述元素當作主要成分之合金材料或化合物材料，或從諸如氮化鈦、氮化鎢、氮化鉭、或氮化鉬等上述元素的氮化物所形成之單層膜用於金屬膜511。Alternatively, it may be selected from the group consisting of elemental titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), niobium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), Ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), silver (Ag), or copper (Cu) The formed single layer film, or an alloy material or a compound material including the above elements as a main component, or a nitride formed from a nitride such as titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride A single layer film is used for the metal film 511.
需注意的是，可將金屬膜511直接形成在基板310上，而不必在基板310上形成基極絕緣膜312。It is to be noted that the metal film 511 can be formed directly on the substrate 310 without forming the base insulating film 312 on the substrate 310.
接著，藉由使用金屬膜511來形成閘極電極512、佈線314及315、和終端電極350(見圖11B)。Next, the gate electrode 512, the wirings 314 and 315, and the terminal electrode 350 (see FIG. 11B) are formed by using the metal film 511.
接著，將形成覆蓋閘極電極512、佈線314及315、和終端電極350之閘極絕緣膜514。在此實施例模式中，閘極絕緣膜514係使用包括矽當作主要成分之絕緣膜所形成的，例如，藉由電漿CVD以厚度115nm所形成之包括氮的氧化矽膜(組成比為Si=32%，O=59%，N=7%，H=2%)。Next, a gate insulating film 514 covering the gate electrode 512, the wirings 314 and 315, and the terminal electrode 350 will be formed. In this embodiment mode, the gate insulating film 514 is formed using an insulating film including germanium as a main component, for example, a cerium oxide film including nitrogen formed by plasma CVD at a thickness of 115 nm (composition ratio is Si = 32%, O = 59%, N = 7%, H = 2%).
接著，在閘極絕緣膜514上形成島型半導體區515。島型半導體區515係使用類似於實施例模式2所說明之島型半導體區331的材料和製造處理之材料和製造處理所形成的(見圖11C)。Next, an island-shaped semiconductor region 515 is formed on the gate insulating film 514. The island-type semiconductor region 515 is formed using a material similar to the material of the island-type semiconductor region 331 described in Embodiment Mode 2 and a manufacturing process and a manufacturing process (see FIG. 11C).
在形成島型半導體區515之後，形成遮罩518，以覆蓋除了稍後充作TFT 503的源極區和汲極區521之區域外的部位，及給予一導電型之雜質被引進(見圖11D)。當作一導電型雜質，在形成n通道TFT的例子中，可使用磷(P)或砷(As)當作n型雜質，及在形成p通道TFT的例子中，可使用硼(B)當作p型雜質。在此實施例模式中，將n型雜質的磷(P)引進到島型半導體區515內，以形成TFT 503的源極區和汲極區521以及這些區域之間的通道形成區。After the formation of the island-type semiconductor region 515, a mask 518 is formed to cover a portion other than the region where the source region and the drain region 521 of the TFT 503 are later charged, and an impurity imparting a conductivity type is introduced (see FIG. 11D). As a conductive type impurity, in the case of forming an n-channel TFT, phosphorus (P) or arsenic (As) can be used as an n-type impurity, and in the case of forming a p-channel TFT, boron (B) can be used. As a p-type impurity. In this embodiment mode, phosphorus (P) of an n-type impurity is introduced into the island-type semiconductor region 515 to form a source region and a drain region 521 of the TFT 503 and a channel formation region between these regions.
接著，去除遮罩518，及形成未圖示之第一中間層絕緣膜、第二中間層絕緣膜316、及第三中間層絕緣膜317(見圖11E)。只要第一中間層絕緣膜的材料和製造處理是可接受的，則第二中間層絕緣膜316和第三中間層絕緣膜317係依據實施例模式2中的說明。Next, the mask 518 is removed, and a first interlayer insulating film, a second interlayer insulating film 316, and a third interlayer insulating film 317 (see FIG. 11E) (not shown) are formed. The second interlayer insulating film 316 and the third interlayer insulating film 317 are in accordance with the description in Embodiment Mode 2 as long as the material and manufacturing process of the first interlayer insulating film are acceptable.
在閘極絕緣膜514、第一中間層絕緣膜、第二中間層絕緣膜316、及第三中間層絕緣膜317中形成接觸孔，以及形成金屬膜。此外，選擇性蝕刻金屬膜以形成TFT 503的佈線319、連接電極320、終端電極351、和源極電極或汲極電極531。然後，去除從抗蝕劑所形成之遮罩。需注意的是，此實施例模式的金屬膜是三層的疊層膜：厚度100nm的Ti膜、厚度350nm之包括少量矽的Al膜、及厚度100nm的Ti膜。然後形成保護電極318、533、536、及538。Contact holes are formed in the gate insulating film 514, the first interlayer insulating film, the second interlayer insulating film 316, and the third interlayer insulating film 317, and a metal film is formed. Further, the metal film is selectively etched to form the wiring 319 of the TFT 503, the connection electrode 320, the terminal electrode 351, and the source electrode or the drain electrode 531. Then, the mask formed from the resist is removed. It is to be noted that the metal film of this embodiment mode is a three-layer laminated film: a Ti film having a thickness of 100 nm, an Al film including a small amount of germanium having a thickness of 350 nm, and a Ti film having a thickness of 100 nm. Protective electrodes 318, 533, 536, and 538 are then formed.
另一選擇是，當作其佈線319和保護電極318；其連接電極320和保護電極533；其終端電極351和保護電極538；其TFT 503的源極和汲極電極531及保護電極536，各個佈線和電極係可使用單層導電膜來形成。Another option is to use it as the wiring 319 and the guard electrode 318; the connection electrode 320 and the guard electrode 533; the terminal electrode 351 and the guard electrode 538; the source of the TFT 503 and the drain electrode 531 and the guard electrode 536, each The wiring and the electrode system can be formed using a single layer of a conductive film.
經由上述處理，可製造底部閘TFT503(見圖12A)。Through the above processing, the bottom gate TFT 503 can be manufactured (see FIG. 12A).
接著，將包括p型半導體層111p、i型半導體層111i、及n型半導體層111n之光電轉換層111形成在第三中間層絕緣膜317上(見圖12B)。關於光電轉換層111的材料，製造處理等實施例模式2提及過。Next, a photoelectric conversion layer 111 including a p-type semiconductor layer 111p, an i-type semiconductor layer 111i, and an n-type semiconductor layer 111n is formed on the third interlayer insulating film 317 (see FIG. 12B). Regarding the material of the photoelectric conversion layer 111, the manufacturing process and the like are mentioned in the embodiment mode 2.
接著，形成密封層324和終端電極121及122(見圖12C)。終端電極121連接到n型半導體層111n，而終端電極122係由以終端電極121相同的處理來形成。Next, a sealing layer 324 and terminal electrodes 121 and 122 are formed (see Fig. 12C). The terminal electrode 121 is connected to the n-type semiconductor layer 111n, and the terminal electrode 122 is formed by the same process as the terminal electrode 121.
另外，使用焊料364及363安裝具有電極361及362之基板360。需注意的是，藉由焊料364將基板360上的電極361連接到終端電極121。此外，藉由焊料363將基板360上的電極362連接到終端電極122(見圖13)。Further, the substrate 360 having the electrodes 361 and 362 is mounted using the solders 364 and 363. It is to be noted that the electrode 361 on the substrate 360 is connected to the terminal electrode 121 by the solder 364. Further, the electrode 362 on the substrate 360 is connected to the terminal electrode 122 by solder 363 (see FIG. 13).
在圖13所示之光電轉換電路中，進入光電轉換層111的光可藉由使用具有光傳送特性的基板310和基板360而從基板310側和基板360側二者進入。In the photoelectric conversion circuit shown in FIG. 13, light entering the photoelectric conversion layer 111 can be entered from both the substrate 310 side and the substrate 360 side by using the substrate 310 having the light transmission characteristics and the substrate 360.
需注意的是，此實施例模式可與此說明書中之其他實施例模式的技術特徵組合。It should be noted that this embodiment mode can be combined with the technical features of other embodiment modes in this specification.
參考圖14A至14B和圖15A及15B，此實施例模式將說明將本發明的光電轉換裝置設置在外殼中以控制進入的光之方向的每一個例子。Referring to Figures 14A to 14B and Figures 15A and 15B, this embodiment mode will explain each example in which the photoelectric conversion device of the present invention is disposed in a casing to control the direction of incoming light.
圖14A圖示藉由焊料364在圖9C所示之光電轉換裝置中將基板360上的電極361連接到終端電極121之後，形成外殼551，使得光不從基板310側而從基板360側進入光電轉換層111。在形成基板360側上的光電轉換層111之區域中，外殼551被設置有開口部。14A illustrates that after the electrode 361 on the substrate 360 is connected to the terminal electrode 121 in the photoelectric conversion device illustrated in FIG. 9C by the solder 364, the outer casing 551 is formed such that light does not enter the photovoltaic from the substrate 310 side from the substrate 310 side. Conversion layer 111. In a region where the photoelectric conversion layer 111 on the side of the substrate 360 is formed, the outer casing 551 is provided with an opening portion.
在圖14A中，具有終端電極121、電極361、及焊料364；然而，從基板360側進入之光經由密封層324斜斜地進入。因此，可產生光電流及可偵測光。In FIG. 14A, there are a terminal electrode 121, an electrode 361, and a solder 364; however, light entering from the substrate 360 side enters obliquely via the sealing layer 324. Therefore, photocurrent and detectable light can be generated.
此外，只要具有遮光功能，可將任何材料用於外殼551及下面將說明之外殼552至554。例如，可使用具有金屬材料或黑色素之樹脂材料等。Further, any material may be used for the outer casing 551 and the outer casings 552 to 554 which will be described below as long as it has a light blocking function. For example, a resin material having a metal material or melanin or the like can be used.
在圖14B中，圖13所示之光電轉換電路被設置有外殼552，使得光不從基板310側而從基板360側進入光電轉換層111。在形成基板360側上的光電轉換層111之區域中，外殼552被設置有開口部。In FIG. 14B, the photoelectric conversion circuit shown in FIG. 13 is provided with a casing 552 so that light does not enter the photoelectric conversion layer 111 from the substrate 310 side from the substrate 310 side. In a region where the photoelectric conversion layer 111 on the side of the substrate 360 is formed, the outer casing 552 is provided with an opening portion.
在圖14與圖14A中，從基板360側進入之光經由密封層324斜斜地進入光電轉換層111。因此，可產生光電流及可偵測光。In FIGS. 14 and 14A, light entering from the side of the substrate 360 obliquely enters the photoelectric conversion layer 111 via the sealing layer 324. Therefore, photocurrent and detectable light can be generated.
圖15A圖示藉由焊料364在圖9C所示之光電轉換裝置中在將基板360上的電極361安裝於終端電極121之後，形成外殼553，使得光不從基板360側而從基板310側進入光電轉換層111。在形成基板310側上的光電轉換層111之區域中，外殼553被設置有開口部。15A illustrates that after mounting the electrode 361 on the substrate 360 to the terminal electrode 121 in the photoelectric conversion device shown in FIG. 9C by the solder 364, the outer casing 553 is formed so that light does not enter from the substrate 310 side from the substrate 360 side. Photoelectric conversion layer 111. In a region where the photoelectric conversion layer 111 on the side of the substrate 310 is formed, the outer casing 553 is provided with an opening portion.
在圖15A中，從基板310側進入之光直接經由第三中間層絕緣膜317進入光電轉換層111，使得可產生光電流及可偵測光。In FIG. 15A, light entering from the substrate 310 side directly enters the photoelectric conversion layer 111 via the third interlayer insulating film 317, so that photocurrent and detectable light can be generated.
在圖15B中，圖13所示之光電轉換電路被設置有外殼554，使得光不從基板360側而從基板310側進入光電轉換層111。在形成基板310側上的光電轉換層111之區域中，外殼554被設置有開口部。In FIG. 15B, the photoelectric conversion circuit shown in FIG. 13 is provided with a casing 554 so that light does not enter the photoelectric conversion layer 111 from the substrate 310 side from the substrate 360 side. In a region where the photoelectric conversion layer 111 on the side of the substrate 310 is formed, the outer casing 554 is provided with an opening portion.
在圖15B中，從基板310側進入之光直接經由第三中間層絕緣膜317進入光電轉換層111，使得可產生光電流及可偵測光。In FIG. 15B, light entering from the side of the substrate 310 directly enters the photoelectric conversion layer 111 via the third interlayer insulating film 317, so that photocurrent and detectable light can be generated.
需注意的是，此實施例模式可與此說明書中之其他實施例模式的技術特徵組合。It should be noted that this embodiment mode can be combined with the technical features of other embodiment modes in this specification.
在此實施例模式中，說明將藉由使用本發明所獲得的光電轉換裝置結合在各種電子裝置中之每一個例子。當作應用本發明的電子裝置之例子，可指定電腦、顯示器、行動電話、電視接收器等。在圖16、圖17A及17B、圖18A及18B、圖19、和圖20A及20B圖示那些電子裝置的特定例子。In this embodiment mode, each of the examples in which various types of electronic devices are incorporated by using the photoelectric conversion device obtained by the present invention will be described. As an example of an electronic device to which the present invention is applied, a computer, a display, a mobile phone, a television receiver, or the like can be specified. Specific examples of those electronic devices are illustrated in FIGS. 16, 17A and 17B, FIGS. 18A and 18B, FIG. 19, and FIGS. 20A and 20B.
圖16圖示一行動電話，其包括主體(A)701、主體(B)702、外殼703、操作鍵704、聲頻輸入部705、聲頻輸出部706、電路基板707、顯示面板(A)708、顯示面板(A)709、鉸鏈710、光傳送材料部711、及光電轉換裝置712。可將本發明應用到光電轉換裝置712。16 illustrates a mobile phone including a main body (A) 701, a main body (B) 702, a casing 703, operation keys 704, an audio input unit 705, an audio output unit 706, a circuit board 707, a display panel (A) 708, A display panel (A) 709, a hinge 710, a light transmitting material portion 711, and a photoelectric conversion device 712. The present invention can be applied to the photoelectric conversion device 712.
光電轉換裝置712偵測經由光傳送材料部711所傳送之光，根據偵測到的外部光之亮度控制顯示面板(A)708及顯示面板(A)709的亮度，和根據光電轉換裝置712所獲得的照度來控制操作鍵704的照度。因此，可降低行動電話的電流消耗。The photoelectric conversion device 712 detects the light transmitted through the light transmitting material portion 711, and controls the brightness of the display panel (A) 708 and the display panel (A) 709 according to the detected brightness of the external light, and according to the photoelectric conversion device 712 The obtained illuminance controls the illuminance of the operation key 704. Therefore, the current consumption of the mobile phone can be reduced.
接著，圖17A及17B圖示行動電話的其他例子。在圖17A及17B中，參考號碼721表示主體；參考號碼722表示外殼；參考號碼723表示顯示面板；參考號碼724表示操作鍵；參考號碼725表示聲頻輸出部；參考號碼726表示聲頻輸入部；及參考號碼727及728表示光電轉換裝置。Next, FIGS. 17A and 17B illustrate other examples of the mobile phone. In FIGS. 17A and 17B, reference numeral 721 denotes a main body; reference numeral 722 denotes a casing; reference numeral 723 denotes a display panel; reference numeral 724 denotes an operation key; reference numeral 725 denotes an audio output portion; reference numeral 726 denotes an audio input portion; Reference numerals 727 and 728 denote photoelectric conversion devices.
在圖17所示之行動電話中，可藉由以設置在主體721中的光電轉換裝置727偵測外部光以控制顯示面板723和操作鍵724之亮度。In the mobile phone shown in FIG. 17, the brightness of the display panel 723 and the operation keys 724 can be controlled by detecting external light by the photoelectric conversion device 727 provided in the main body 721.
在圖17B所示之行動電話中，除了圖17A的結構之外，光電轉換裝置729也被設置在主體721內部。藉由光電轉換裝置728，可偵測提供給顯示面板723之背光的亮度。In the mobile phone shown in FIG. 17B, in addition to the structure of FIG. 17A, the photoelectric conversion device 729 is also disposed inside the main body 721. The brightness of the backlight provided to the display panel 723 can be detected by the photoelectric conversion device 728.
圖18A圖示一電腦，其包括主體731、外殼732、顯示部733、鍵盤734、外部連接埠735、定位裝置736等。FIG. 18A illustrates a computer including a main body 731, a housing 732, a display portion 733, a keyboard 734, an external port 735, a positioning device 736, and the like.
圖18B圖示一顯示裝置，及TV接收器等對應於此。顯示裝置包括外殼741、支撐基座742、顯示部734等。Fig. 18B illustrates a display device, and a TV receiver or the like corresponds to this. The display device includes a housing 741, a support base 742, a display portion 734, and the like.
圖19圖示將液晶顯示面板用於設置在圖18A的電腦中之顯示部733以及圖18B所示之顯示裝置的顯示部743的例子之特定結構。FIG. 19 illustrates a specific configuration of an example in which the liquid crystal display panel is used for the display portion 733 provided in the computer of FIG. 18A and the display portion 743 of the display device illustrated in FIG. 18B.
將圖19所示之液晶面板762結合在外殼761中，和包括基板751a及751b、夾置在基板751a和751b之間的液晶層752、偏極化濾波器752a及752b、背光753等。在外殼761中形成光電轉換裝置754。The liquid crystal panel 762 shown in FIG. 19 is incorporated in the casing 761, and includes a substrate 751a and 751b, a liquid crystal layer 752 interposed between the substrates 751a and 751b, polarization filters 752a and 752b, a backlight 753, and the like. A photoelectric conversion device 754 is formed in the outer casing 761.
使用本發明所製造的光電轉換裝置754偵測來自背光753的光量，及當反饋回其資訊時，調整液晶面板762的亮度。The amount of light from the backlight 753 is detected using the photoelectric conversion device 754 manufactured by the present invention, and the brightness of the liquid crystal panel 762 is adjusted when the information is fed back.
圖20A及20B各個圖示將本發明的光電轉換裝置結合在諸如數位相機等相機中之例子。圖20A為數位相機的正面立體圖，及圖20B為數位相機的背面立體圖。在圖20A中，數位相機包括快門開關按鈕801、主開關802、取景窗803、閃光燈部804、透鏡805、鏡筒806、和外殼807。20A and 20B each illustrate an example in which the photoelectric conversion device of the present invention is incorporated in a camera such as a digital camera. 20A is a front perspective view of a digital camera, and FIG. 20B is a rear perspective view of the digital camera. In FIG. 20A, the digital camera includes a shutter switch button 801, a main switch 802, a finder window 803, a flash unit 804, a lens 805, a lens barrel 806, and a housing 807.
此外，如圖20B所示，包括取景目鏡窗811、監視器812、及操作按鈕813。Further, as shown in FIG. 20B, a viewfinder eyepiece window 811, a monitor 812, and an operation button 813 are included.
當將快門開關按鈕801按下一半時，操作聚焦調整機構和曝光調整機構，及當將快門開關按鈕全部按下時，打開快門。When the shutter switch button 801 is pressed halfway, the focus adjustment mechanism and the exposure adjustment mechanism are operated, and when the shutter switch button is all pressed, the shutter is opened.
藉由按下或轉動，主開關802開關數位相機的電源之ON/OFF。The main switch 802 switches the ON/OFF of the power of the digital camera by pressing or turning.
將取景窗803設置在數位相機的正面之透鏡805上方，及其係為用以確認被拍攝或距圖20B所示之取景目鏡窗811的焦距位置之區域的裝置。The finder window 803 is disposed above the lens 805 on the front side of the digital camera, and is a device for confirming the area of the focal length position of the finder eyepiece window 811 that is photographed or viewed from FIG. 20B.
將閃光燈部804設置在數位相機的正面之上部位，及當物體的亮度是低的時，在按下快門開關按鈕並且打開快門的同時，發出輔助光。The flash unit 804 is disposed above the front surface of the digital camera, and when the brightness of the object is low, the auxiliary light is emitted while the shutter switch button is pressed and the shutter is opened.
將透鏡805設置在數位相機的正面。透鏡805包括聚焦透鏡、可變焦距透鏡等，及形成具有未圖示之快門和光圈的拍攝光學系統。此外，將諸如CCD(電荷耦合裝置)等攝像裝置設置在透鏡805的背面。The lens 805 is placed on the front side of the digital camera. The lens 805 includes a focus lens, a variable focal length lens, and the like, and a photographing optical system having a shutter and a diaphragm (not shown). Further, an image pickup device such as a CCD (Charge Coupled Device) is disposed on the back surface of the lens 805.
鏡筒806移動透鏡805的位置以調整聚焦透鏡、可變焦距透鏡等的焦距。在拍攝時，鏡筒806向外滑動出去以向前移動透鏡805。另外，當攜帶相機時，往回移動透鏡805並且使其緊密。需注意的是，雖然在此實施例模式中利用向外滑出鏡筒以便能夠放大和拍攝物體之結構，但是本發明並不侷限於此結構。亦可利用藉由使用外殼807內部的拍攝光學系統，無須將鏡筒向外滑出就可執行可變焦距拍攝之結構。The lens barrel 806 moves the position of the lens 805 to adjust the focal length of the focus lens, the variable focus lens, and the like. At the time of shooting, the lens barrel 806 slides outward to move the lens 805 forward. In addition, when carrying the camera, the lens 805 is moved back and made tight. It is to be noted that although the structure in which the lens barrel is slid outward is used in this embodiment mode so that the structure of the object can be enlarged and photographed, the present invention is not limited to this structure. It is also possible to use a photographing optical system inside the casing 807 to perform a zoomable photographing structure without sliding the lens barrel outward.
將取景目鏡窗811設置在數位相機的背面之上部位，及其係為當認出拍攝的區域或焦點時，用以看出去的窗口。The finder eyepiece window 811 is disposed at a position above the back of the digital camera, and is a window for observing when the captured area or focus is recognized.
操作按鈕813是設置在數位相機的背表面之用於各種功能的按鈕，及包括設定按鈕、功能表按鈕、顯示按鈕、功能按鈕、選擇按鈕等。The operation button 813 is a button for various functions provided on the back surface of the digital camera, and includes a setting button, a function table button, a display button, a function button, a selection button, and the like.
當將本發明的光電轉換裝置結合在圖20A及20B所示之相機時，光電轉換裝置能夠偵測光的存在或不存在以及光強度，使得能夠執行相機的曝光調整等。在本發明的光電轉換裝置中，能夠獲得幾乎與照度的對數成比例之輸出，及能夠加寬可應用於光電轉換裝置之照度範圍。When the photoelectric conversion device of the present invention is incorporated in the cameras shown in FIGS. 20A and 20B, the photoelectric conversion device can detect the presence or absence of light and the light intensity, so that exposure adjustment of the camera or the like can be performed. In the photoelectric conversion device of the present invention, it is possible to obtain an output which is almost proportional to the logarithm of the illuminance, and it is possible to widen the illuminance range applicable to the photoelectric conversion device.
此外，可將本發明的光電轉換裝置應用到諸如投影電視和導航系統等其他電子裝置。也就是說，可將本發明的光學感測器用於需要被偵測之任何裝置。Further, the photoelectric conversion device of the present invention can be applied to other electronic devices such as a projection television and a navigation system. That is, the optical sensor of the present invention can be used with any device that needs to be detected.
需注意的是，此實施例模式能夠與此說明書中的其他實施例模式之技術特徵組合。It should be noted that this embodiment mode can be combined with the technical features of other embodiment modes in this specification.
本申請案係依據日本專利局於2007、7、25所發表之日本專利申請案序號2007-193015，和日本專利局於2007、7、25所發表之日本專利申請案序號2007-193151，特此併入其全文做為參考。The present application is based on the Japanese Patent Application No. 2007-193015, the disclosure of which is hereby incorporated by reference. Into its full text as a reference.
101．．．電流鏡電路101. . . Current mirror circuit
102a．．．輸出產生電路102a. . . Output generation circuit
102b．．．輸出產生電路102b. . . Output generation circuit
102c．．．輸出產生電路102c. . . Output generation circuit
103．．．光電轉換元件103. . . Photoelectric conversion element
104．．．參考側電晶體104. . . Reference side transistor
105a．．．輸出側電晶體105a. . . Output side transistor
105b．．．輸出側電晶體105b. . . Output side transistor
105c．．．輸出側電晶體105c. . . Output side transistor
106a．．．內部電阻器106a. . . Internal resistor
106b．．．內部電阻器106b. . . Internal resistor
106c．．．內部電阻器106c. . . Internal resistor
107．．．負載電阻器107. . . Load resistor
108．．．高電位側電力供應線108. . . High potential side power supply line
109．．．低電位側電力供應線109. . . Low potential side power supply line
110．．．輸出終端110. . . Output terminal
111．．．光電轉換層111. . . Photoelectric conversion layer
111i．．．i型半導體111i. . . I-type semiconductor
111n．．．n型半導體111n. . . N-type semiconductor
111p．．．p型半導體111p. . . P-type semiconductor
113．．．薄膜電晶體113. . . Thin film transistor
121．．．終端電極121. . . Terminal electrode
122．．．終端電極122. . . Terminal electrode
211．．．第二電流鏡電路211. . . Second current mirror circuit
212．．．第二參考側電晶體212. . . Second reference side transistor
213．．．第二輸出側電晶體213. . . Second output side transistor
301．．．曲線301. . . curve
302．．．曲線302. . . curve
303．．．直線303. . . straight line
304．．．點304. . . point
305．．．點305. . . point
310．．．第一基板310. . . First substrate
312．．．基極絕緣膜312. . . Base insulating film
313．．．閘極絕緣膜313. . . Gate insulating film
314．．．佈線314. . . wiring
315．．．佈線315. . . wiring
316．．．第二中間層絕緣膜316. . . Second interlayer insulating film
317．．．第三中間層絕緣膜317. . . Third interlayer insulating film
318．．．保護電極318. . . Protective electrode
319．．．佈線319. . . wiring
320．．．連接電極320. . . Connecting electrode
324．．．密封層324. . . Sealing layer
331．．．島型半導體區331. . . Island semiconductor region
334．．．閘極電極334. . . Gate electrode
337．．．源極或汲極區337. . . Source or bungee
341．．．源極或汲極電極341. . . Source or drain electrode
345．．．保護電極345. . . Protective electrode
346．．．保護電極346. . . Protective electrode
348．．．保護電極348. . . Protective electrode
350．．．終端電極350. . . Terminal electrode
351．．．終端電極351. . . Terminal electrode
360．．．基板360. . . Substrate
361．．．電極361. . . electrode
362．．．電極362. . . electrode
363．．．焊料363. . . solder
364．．．焊料364. . . solder
501a．．．曲線501a. . . curve
501b．．．曲線501b. . . curve
501c．．．曲線501c. . . curve
503．．．薄膜電晶體503. . . Thin film transistor
511．．．金屬膜511. . . Metal film
512．．．閘極電極512. . . Gate electrode
514．．．閘極絕緣膜514. . . Gate insulating film
515．．．島型半導體區515. . . Island semiconductor area
518．．．遮罩518. . . Mask
521．．．源極或汲極區521. . . Source or bungee
531．．．源極或汲極電極531. . . Source or drain electrode
533．．．保護電極533. . . Protective electrode
536．．．保護電極536. . . Protective electrode
538．．．保護電極538. . . Protective electrode
551．．．外殼551. . . shell
552．．．外殼552. . . shell
553．．．外殼553. . . shell
554．．．外殼554. . . shell
601．．．電流鏡電路601. . . Current mirror circuit
602a．．．輸出產生電路602a. . . Output generation circuit
602b．．．輸出產生電路602b. . . Output generation circuit
602c．．．輸出產生電路602c. . . Output generation circuit
603．．．光電轉換元件603. . . Photoelectric conversion element
604．．．參考側電晶體604. . . Reference side transistor
605a．．．輸出側電晶體605a. . . Output side transistor
605b．．．輸出側電晶體605b. . . Output side transistor
605c．．．輸出側電晶體605c. . . Output side transistor
606a．．．內部電阻器606a. . . Internal resistor
606b．．．內部電阻器606b. . . Internal resistor
606c．．．內部電阻器606c. . . Internal resistor
607．．．負載電阻器607. . . Load resistor
608．．．高電位側電力供應線608. . . High potential side power supply line
609．．．低電位側電力供應線609. . . Low potential side power supply line
610．．．輸出終端610. . . Output terminal
611．．．第二電流鏡電路611. . . Second current mirror circuit
612．．．第二參考側電晶體612. . . Second reference side transistor
613．．．第二輸出側電晶體613. . . Second output side transistor
701．．．主體(A)701. . . Subject (A)
702．．．主體(B)702. . . Subject (B)
703．．．外殼703. . . shell
704．．．操作鍵704. . . Operation key
705．．．聲頻輸入部705. . . Audio input unit
706．．．聲頻輸出部706. . . Audio output
707．．．電路基板707. . . Circuit substrate
708．．．顯示面板(A)708. . . Display panel (A)
709．．．顯示面板(B)709. . . Display panel (B)
710．．．鉸鏈710. . . Hinge
711．．．光傳送材料部711. . . Optical transmission material department
712．．．光電轉換裝置712. . . Photoelectric conversion device
721．．．主體721. . . main body
722．．．外殼722. . . shell
723．．．顯示面板723. . . Display panel
724．．．操作鍵724. . . Operation key
725．．．聲頻輸出部725. . . Audio output
726．．．聲頻輸入部726. . . Audio input unit
727．．．光電轉換裝置727. . . Photoelectric conversion device
728．．．光電轉換裝置728. . . Photoelectric conversion device
731．．．主體731. . . main body
732．．．外殼732. . . shell
733．．．顯示部733. . . Display department
734．．．鍵盤734. . . keyboard
735．．．外部連接埠735. . . External connection埠
736．．．定位裝置736. . . Positioning means
741．．．外殼741. . . shell
742．．．支撐基座742. . . Support base
743．．．顯示部743. . . Display department
751a．．．基板751a. . . Substrate
751b．．．基板751b. . . Substrate
752．．．液晶面板752. . . LCD panel
752a．．．偏極化濾波器752a. . . Polarization filter
752b．．．偏極化濾波器752b. . . Polarization filter
801．．．快門開關按鈕801. . . Shutter switch button
802．．．主開關802. . . Main switch
803．．．取景窗803. . . Viewfinder window
804．．．閃光燈部804. . . Flash unit
805．．．透鏡805. . . lens
806．．．鏡筒806. . . Lens barrel
807．．．外殼807. . . shell
811．．．取景目鏡窗811. . . Viewfinder window
812．．．監視器812. . . Monitor
813．．．操作按鈕813. . . Operation button
1100．．．玻璃基板1100. . . glass substrate
1101．．．單晶半導體基板1101. . . Single crystal semiconductor substrate
1102．．．半導體膜1102. . . Semiconductor film
1103．．．削弱層1103. . . Weaken layer
1122．．．壓力接合材料1122. . . Pressure bonding material
在下面附圖中：In the following figures:
圖1為本發明的光電轉換裝置之電路組態圖；1 is a circuit configuration diagram of a photoelectric conversion device of the present invention;
圖2為本發明的光電轉換裝置中之輸出產生電路的組態圖；2 is a configuration diagram of an output generating circuit in the photoelectric conversion device of the present invention;
圖3為本發明的光電轉換裝置中之輸出產生電路的電壓電流特性圖；3 is a diagram showing voltage and current characteristics of an output generating circuit in the photoelectric conversion device of the present invention;
圖4為本發明的光電轉換裝置中之輸出產生電路的照度電流特性圖；4 is a illuminance current characteristic diagram of an output generating circuit in the photoelectric conversion device of the present invention;
圖5A為輸出產生電路的照度電流特性圖，圖5B為輸出產生電路的照度電流之總和圖，及圖5C為本發明的光電轉換裝置中之輸出產生電路的照度電壓特性之總和圖；5A is a illuminance current characteristic diagram of an output generation circuit, FIG. 5B is a sum total of illuminance currents of an output generation circuit, and FIG. 5C is a sum total of illuminance voltage characteristics of an output generation circuit in the photoelectric conversion apparatus of the present invention;
圖6為本發明的光電轉換裝置之電路組態圖；Figure 6 is a circuit configuration diagram of a photoelectric conversion device of the present invention;
圖7A為輸出產生電路的照度電流特性之總和圖，及7A is a sum total of illuminance current characteristics of an output generating circuit, and
圖7B為本發明的光電轉換裝置中之輸出產生電路的照度電壓特性之總和圖；7B is a view showing a sum total of illuminance voltage characteristics of an output generating circuit in the photoelectric conversion device of the present invention;
圖8A至8D為本發明的光電轉換電路之製造方法圖；8A to 8D are diagrams showing a method of manufacturing a photoelectric conversion circuit of the present invention;
圖9A至9C為本發明的光電轉換電路之製造方法圖；9A to 9C are diagrams showing a method of manufacturing a photoelectric conversion circuit of the present invention;
圖10A至10D為本發明的光電轉換電路之製造方法圖；10A to 10D are diagrams showing a method of manufacturing a photoelectric conversion circuit of the present invention;
圖11A至11E為本發明的光電轉換電路之製造方法圖；11A to 11E are diagrams showing a method of manufacturing a photoelectric conversion circuit of the present invention;
圖12A至12C為本發明的光電轉換電路之製造方法圖；12A to 12C are diagrams showing a method of manufacturing a photoelectric conversion circuit of the present invention;
圖13為本發明的光電轉換電路之橫剖面圖；Figure 13 is a cross-sectional view of the photoelectric conversion circuit of the present invention;
圖14A及14B為本發明的光電轉換電路之橫剖面圖；14A and 14B are cross-sectional views of a photoelectric conversion circuit of the present invention;
圖15A及15B為本發明的光電轉換電路之橫剖面圖；15A and 15B are cross-sectional views of a photoelectric conversion circuit of the present invention;
圖16為設置有本發明的光電轉換裝置之裝置圖；Figure 16 is a view showing a device provided with the photoelectric conversion device of the present invention;
圖17A及17B各個為設置有本發明的光電轉換裝置之裝置圖；17A and 17B are each a device diagram in which the photoelectric conversion device of the present invention is provided;
圖18A及18B各個為設置有本發明的光電轉換裝置之裝置圖；18A and 18B are each a device diagram in which the photoelectric conversion device of the present invention is provided;
圖19為設置有本發明的光電轉換裝置之裝置圖；Figure 19 is a view showing a device provided with the photoelectric conversion device of the present invention;
圖20A及20B為設置有本發明的光電轉換裝置之裝置圖；20A and 20B are views showing a device provided with the photoelectric conversion device of the present invention;
圖21為本發明的光電轉換裝置之電路組態圖；及Figure 21 is a circuit configuration diagram of a photoelectric conversion device of the present invention; and
圖22為本發明的光電轉換裝置之電路組態圖。Figure 22 is a circuit configuration diagram of a photoelectric conversion device of the present invention.
101．．．電流鏡電路101. . . Current mirror circuit
102a．．．輸出產生電路102a. . . Output generation circuit
102b．．．輸出產生電路102b. . . Output generation circuit
102c．．．輸出產生電路102c. . . Output generation circuit
103．．．光電轉換元件103. . . Photoelectric conversion element
104．．．參考側電晶體104. . . Reference side transistor
105a．．．輸出側電晶體105a. . . Output side transistor
105b．．．輸出側電晶體105b. . . Output side transistor
105c．．．輸出側電晶體105c. . . Output side transistor
106a．．．內部電阻器106a. . . Internal resistor
106b．．．內部電阻器106b. . . Internal resistor
106c．．．內部電阻器106c. . . Internal resistor
107．．．負載電阻器107. . . Load resistor
108．．．高電位側電力供應線108. . . High potential side power supply line
109．．．低電位側電力供應線109. . . Low potential side power supply line
110．．．輸出終端110. . . Output terminal
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007193015 | 2007-07-25 | ||
| JP2007193151 | 2007-07-25 |
| Publication Number | Publication Date |
|---|---|
| TW200925564A TW200925564A (en) | 2009-06-16 |
| TWI437214Btrue TWI437214B (en) | 2014-05-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097127970ATWI437214B (en) | 2007-07-25 | 2008-07-23 | Photoelectric conversion device and electronic device having photoelectric conversion device |
| Country | Link |
|---|---|
| US (2) | US8154480B2 (en) |
| JP (1) | JP5222649B2 (en) |
| TW (1) | TWI437214B (en) |
| WO (1) | WO2009014155A1 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8269562B1 (en)* | 2006-06-30 | 2012-09-18 | Ixys Ch Gmbh | Open-loop transimpedance amplifier for infrared diodes |
| US11339430B2 (en) | 2007-07-10 | 2022-05-24 | Life Technologies Corporation | Methods and apparatus for measuring analytes using large scale FET arrays |
| CA2672315A1 (en) | 2006-12-14 | 2008-06-26 | Ion Torrent Systems Incorporated | Methods and apparatus for measuring analytes using large scale fet arrays |
| US8262900B2 (en)* | 2006-12-14 | 2012-09-11 | Life Technologies Corporation | Methods and apparatus for measuring analytes using large scale FET arrays |
| US7923800B2 (en)* | 2006-12-27 | 2011-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
| KR101401528B1 (en)* | 2007-06-29 | 2014-06-03 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Photoelectric conversion device and electronic device provided with the photoelectric conversion device |
| WO2009014155A1 (en)* | 2007-07-25 | 2009-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and electronic device having the same |
| US8363365B2 (en)* | 2008-06-17 | 2013-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US20100137143A1 (en) | 2008-10-22 | 2010-06-03 | Ion Torrent Systems Incorporated | Methods and apparatus for measuring analytes |
| US20100301398A1 (en) | 2009-05-29 | 2010-12-02 | Ion Torrent Systems Incorporated | Methods and apparatus for measuring analytes |
| US8776573B2 (en) | 2009-05-29 | 2014-07-15 | Life Technologies Corporation | Methods and apparatus for measuring analytes |
| WO2011024629A1 (en)* | 2009-08-25 | 2011-03-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US8759917B2 (en)* | 2010-01-04 | 2014-06-24 | Samsung Electronics Co., Ltd. | Thin-film transistor having etch stop multi-layer and method of manufacturing the same |
| US8803063B2 (en)* | 2010-02-19 | 2014-08-12 | Semiconductor Energy Laboratory Co., Ltd. | Photodetector circuit |
| US8637802B2 (en)* | 2010-06-18 | 2014-01-28 | Semiconductor Energy Laboratory Co., Ltd. | Photosensor, semiconductor device including photosensor, and light measurement method using photosensor |
| TWI539172B (en) | 2010-06-30 | 2016-06-21 | 生命技術公司 | Methods and apparatus for testing isfet arrays |
| JP2013540259A (en) | 2010-06-30 | 2013-10-31 | ライフ テクノロジーズ コーポレーション | Array column integrator |
| WO2012003363A1 (en) | 2010-06-30 | 2012-01-05 | Life Technologies Corporation | Ion-sensing charge-accumulation circuits and methods |
| US11307166B2 (en) | 2010-07-01 | 2022-04-19 | Life Technologies Corporation | Column ADC |
| EP2589065B1 (en) | 2010-07-03 | 2015-08-19 | Life Technologies Corporation | Chemically sensitive sensor with lightly doped drains |
| WO2012036679A1 (en) | 2010-09-15 | 2012-03-22 | Life Technologies Corporation | Methods and apparatus for measuring analytes |
| US8796036B2 (en)* | 2010-09-24 | 2014-08-05 | Life Technologies Corporation | Method and system for delta double sampling |
| US9209209B2 (en) | 2010-10-29 | 2015-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and method for operating the same |
| JP5925475B2 (en)* | 2010-12-09 | 2016-05-25 | 株式会社半導体エネルギー研究所 | Photodetection circuit |
| US9793039B1 (en) | 2011-05-04 | 2017-10-17 | The Board Of Trustees Of The University Of Alabama | Carbon nanotube-based integrated power inductor for on-chip switching power converters |
| US9048788B2 (en)* | 2011-05-13 | 2015-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising a photoelectric conversion portion |
| MX2011008907A (en)* | 2011-08-24 | 2013-02-25 | Mexicano Inst Petrol | Enhancer system of the flow pattern of gas wells with liquid load problems. |
| JP5529203B2 (en)* | 2011-09-21 | 2014-06-25 | シャープ株式会社 | Optical sensor and electronic device |
| US9970984B2 (en) | 2011-12-01 | 2018-05-15 | Life Technologies Corporation | Method and apparatus for identifying defects in a chemical sensor array |
| JP5812959B2 (en)* | 2011-12-15 | 2015-11-17 | キヤノン株式会社 | Imaging device |
| JP5895504B2 (en) | 2011-12-15 | 2016-03-30 | ソニー株式会社 | Imaging panel and imaging processing system |
| JP5924924B2 (en) | 2011-12-15 | 2016-05-25 | キヤノン株式会社 | Electronic circuit |
| US9080968B2 (en) | 2013-01-04 | 2015-07-14 | Life Technologies Corporation | Methods and systems for point of use removal of sacrificial material |
| US9841398B2 (en) | 2013-01-08 | 2017-12-12 | Life Technologies Corporation | Methods for manufacturing well structures for low-noise chemical sensors |
| US8963216B2 (en) | 2013-03-13 | 2015-02-24 | Life Technologies Corporation | Chemical sensor with sidewall spacer sensor surface |
| US9590514B1 (en)* | 2013-03-15 | 2017-03-07 | The Board Of Trustees Of The University Of Alabama, For And On Behalf Of The University Of Alabama | Carbon nanotube-based integrated power converters |
| EP2972280B1 (en) | 2013-03-15 | 2021-09-29 | Life Technologies Corporation | Chemical sensor with consistent sensor surface areas |
| US9835585B2 (en) | 2013-03-15 | 2017-12-05 | Life Technologies Corporation | Chemical sensor with protruded sensor surface |
| JP6671274B2 (en) | 2013-03-15 | 2020-03-25 | ライフ テクノロジーズ コーポレーション | Chemical device with thin conductive element |
| US20140336063A1 (en) | 2013-05-09 | 2014-11-13 | Life Technologies Corporation | Windowed Sequencing |
| US10458942B2 (en) | 2013-06-10 | 2019-10-29 | Life Technologies Corporation | Chemical sensor array having multiple sensors per well |
| JP6384822B2 (en)* | 2013-11-07 | 2018-09-05 | Ｔｉａｎｍａ Ｊａｐａｎ株式会社 | Image sensor and manufacturing method thereof |
| US9312280B2 (en)* | 2014-07-25 | 2016-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP6598436B2 (en)* | 2014-08-08 | 2019-10-30 | キヤノン株式会社 | Photoelectric conversion device, imaging system, and method of manufacturing photoelectric conversion device |
| KR102593647B1 (en) | 2014-12-18 | 2023-10-26 | 라이프 테크놀로지스 코포레이션 | High data rate integrated circuit with transmitter configuration |
| US10077472B2 (en) | 2014-12-18 | 2018-09-18 | Life Technologies Corporation | High data rate integrated circuit with power management |
| GB2538258A (en)* | 2015-05-12 | 2016-11-16 | Nordic Semiconductor Asa | Reference voltages |
| JP6517664B2 (en)* | 2015-10-28 | 2019-05-22 | 浜松ホトニクス株式会社 | Readout circuit |
| US11166008B2 (en)* | 2016-01-15 | 2021-11-02 | Comcast Cable Communications, Llc | Methods and systems for displaying content |
| CN108170195B (en)* | 2016-12-07 | 2020-04-17 | 矽统科技股份有限公司 | Source follower |
| TWI602394B (en)* | 2016-12-07 | 2017-10-11 | 矽統科技股份有限公司 | Source follower |
| WO2018235817A1 (en)* | 2017-06-23 | 2018-12-27 | パイオニア株式会社 | Electromagnetic wave detector |
| WO2018235819A1 (en)* | 2017-06-23 | 2018-12-27 | パイオニア株式会社 | ELECTROMAGNETIC WAVE DETECTION DEVICE |
| CN107731952B (en)* | 2017-10-02 | 2022-11-25 | 深圳市雷克斯托通信有限公司 | radar sensor |
| US10374647B1 (en) | 2018-02-13 | 2019-08-06 | Texas Instruments Incorporated | Adjustable dynamic range signal detection circuit |
| CN109166892B (en)* | 2018-08-30 | 2022-11-25 | 京东方科技集团股份有限公司 | OLED display substrate and manufacturing method thereof, OLED display panel |
| EP3683649A1 (en)* | 2019-01-21 | 2020-07-22 | NXP USA, Inc. | Bandgap current architecture optimized for size and accuracy |
| CN113327542B (en) | 2021-05-27 | 2023-03-31 | Tcl华星光电技术有限公司 | Drive circuit and panel |
| TWI798767B (en)* | 2021-07-25 | 2023-04-11 | 袁知賢 | Photoelectric conversion element and manufacturing method thereof |
| CN114485928A (en)* | 2021-08-20 | 2022-05-13 | 荣耀终端有限公司 | Light detection method, light detection circuit, display screen and electronic equipment |
| CN113932919B (en)* | 2021-10-08 | 2024-07-26 | 杭州涂鸦信息技术有限公司 | Ambient light detection circuit, ambient light detection method, computer device, and readable storage medium |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56122123A (en)* | 1980-03-03 | 1981-09-25 | Shunpei Yamazaki | Semiamorphous semiconductor |
| USRE34658E (en)* | 1980-06-30 | 1994-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device of non-single crystal-structure |
| US4466018A (en)* | 1981-05-09 | 1984-08-14 | Sony Corporation | Image pickup apparatus with gain controlled output amplifier |
| JPS57184376A (en)* | 1981-05-09 | 1982-11-13 | Sony Corp | Signal output circuit of image pickup device |
| US4498001A (en)* | 1982-07-26 | 1985-02-05 | At&T Bell Laboratories | Transimpedance amplifier for optical receivers |
| JPS60198861A (en) | 1984-03-23 | 1985-10-08 | Fujitsu Ltd | Thin film transistor |
| JPH0770064B2 (en)* | 1987-06-30 | 1995-07-31 | 三菱電機株式会社 | Recording medium drive |
| US5004901A (en)* | 1987-06-04 | 1991-04-02 | Mitsubishi Denki Kabushiki Kaisha | Current mirror amplifier for use in an optical data medium driving apparatus and servo-circuit |
| NL194811C (en)* | 1986-01-16 | 2003-03-04 | Mitsubishi Electric Corp | Servo circuit. |
| USRE34769E (en)* | 1986-01-16 | 1994-11-01 | Mitsubishi Denki Kabushiki Kaisha | Current mirror amplifier for use in an optical data medium driving apparatus and servo-circuit |
| JPH0244256B2 (en) | 1987-01-28 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN2O5DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
| JPS63210023A (en) | 1987-02-24 | 1988-08-31 | Natl Inst For Res In Inorg Mater | Compound having a hexagonal layered structure represented by InGaZn↓4O↓7 and its manufacturing method |
| JPH0244258B2 (en) | 1987-02-24 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN3O6DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
| JPH0244260B2 (en) | 1987-02-24 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN5O8DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
| JPH0244262B2 (en) | 1987-02-27 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN6O9DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
| JPH0244263B2 (en) | 1987-04-22 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN7O10DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
| US4896121A (en)* | 1988-10-31 | 1990-01-23 | Hughes Aircraft Company | Current mirror for depletion-mode field effect transistor technology |
| US5241575A (en)* | 1989-12-21 | 1993-08-31 | Minolta Camera Kabushiki Kaisha | Solid-state image sensing device providing a logarithmically proportional output signal |
| JP2836147B2 (en) | 1989-12-21 | 1998-12-14 | ミノルタ株式会社 | Photoelectric conversion device |
| JPH05251705A (en) | 1992-03-04 | 1993-09-28 | Fuji Xerox Co Ltd | Thin-film transistor |
| US5381146A (en)* | 1993-07-06 | 1995-01-10 | Digital Equipment Corporation | Voltage-tracking circuit and application in a track-and-hold amplifier |
| IT1264817B1 (en) | 1993-07-28 | 1996-10-10 | Ciba Geigy Spa | POLYALKYL-4-PIPERIDINOL DERIVATIVES SUITABLE FOR POLYALKYL-4-PIPERIDINOL DERIVATIVES SUITABLE FOR USE AS STABILIZERS FOR ORGANIC MATERIALS IEGO AS STABILIZERS FOR ORGANIC MATERIALS |
| US5473467A (en) | 1994-07-08 | 1995-12-05 | At&T Corp. | Linear optical amplifier |
| JPH0888770A (en)* | 1994-09-16 | 1996-04-02 | Toshiba Corp | Image processing device |
| JP3203996B2 (en)* | 1994-11-01 | 2001-09-04 | 三菱電機株式会社 | Test circuit for current-voltage conversion amplifier |
| JP3479375B2 (en) | 1995-03-27 | 2003-12-15 | 科学技術振興事業団 | Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the same |
| FR2733098B1 (en)* | 1995-04-11 | 1997-07-04 | Sgs Thomson Microelectronics | CURRENT AMPLIFIER |
| JPH08289205A (en)* | 1995-04-13 | 1996-11-01 | Nissan Motor Co Ltd | Light receiving element and image input device using the same |
| KR100394896B1 (en) | 1995-08-03 | 2003-11-28 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | A semiconductor device including a transparent switching element |
| JP3625598B2 (en) | 1995-12-30 | 2005-03-02 | 三星電子株式会社 | Manufacturing method of liquid crystal display device |
| JPH09321548A (en)* | 1996-05-31 | 1997-12-12 | S I I R D Center:Kk | Semiconductor integrated circuit device |
| JP3444093B2 (en)* | 1996-06-10 | 2003-09-08 | 株式会社デンソー | Optical sensor circuit |
| JPH1188770A (en)* | 1997-09-03 | 1999-03-30 | Nissan Motor Co Ltd | Image sensor device |
| JP4044187B2 (en)* | 1997-10-20 | 2008-02-06 | 株式会社半導体エネルギー研究所 | Active matrix display device and manufacturing method thereof |
| US6287888B1 (en)* | 1997-12-26 | 2001-09-11 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and process for producing photoelectric conversion device |
| JP3783451B2 (en)* | 1999-03-12 | 2006-06-07 | 株式会社デンソー | Optical sensor |
| US6521882B1 (en)* | 1998-03-27 | 2003-02-18 | Denso Corporation | Optical sensor with directivity controlled |
| JP4170454B2 (en) | 1998-07-24 | 2008-10-22 | Ｈｏｙａ株式会社 | Article having transparent conductive oxide thin film and method for producing the same |
| JP2000150861A (en) | 1998-11-16 | 2000-05-30 | Tdk Corp | Oxide thin film |
| JP3276930B2 (en) | 1998-11-17 | 2002-04-22 | 科学技術振興事業団 | Transistor and semiconductor device |
| US6495816B1 (en)* | 1999-04-30 | 2002-12-17 | Lockheed Martin Corporation | Method and apparatus for converting the output of a photodetector to a log voltage |
| TW460731B (en) | 1999-09-03 | 2001-10-21 | Ind Tech Res Inst | Electrode structure and production method of wide viewing angle LCD |
| JP2001215550A (en)* | 2000-02-01 | 2001-08-10 | Canon Inc | Photoelectric conversion device, dimming circuit and CMOS sensor |
| US6995753B2 (en)* | 2000-06-06 | 2006-02-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method of manufacturing the same |
| US7030551B2 (en)* | 2000-08-10 | 2006-04-18 | Semiconductor Energy Laboratory Co., Ltd. | Area sensor and display apparatus provided with an area sensor |
| JP4089858B2 (en) | 2000-09-01 | 2008-05-28 | 国立大学法人東北大学 | Semiconductor device |
| KR20020038482A (en) | 2000-11-15 | 2002-05-23 | 모리시타 요이찌 | Thin film transistor array, method for producing the same, and display panel using the same |
| JP3997731B2 (en) | 2001-03-19 | 2007-10-24 | 富士ゼロックス株式会社 | Method for forming a crystalline semiconductor thin film on a substrate |
| JP2002289859A (en) | 2001-03-23 | 2002-10-04 | Minolta Co Ltd | Thin film transistor |
| JP4090716B2 (en) | 2001-09-10 | 2008-05-28 | 雅司 川崎 | Thin film transistor and matrix display device |
| JP3925839B2 (en) | 2001-09-10 | 2007-06-06 | シャープ株式会社 | Semiconductor memory device and test method thereof |
| EP1450341A4 (en)* | 2001-09-25 | 2009-04-01 | Panasonic Corp | ELECTROLUMINESCENT SCREEN AND ELECTROLUMINESCENT DISPLAY DEVICE COMPRISING THE SAME |
| WO2003040441A1 (en) | 2001-11-05 | 2003-05-15 | Japan Science And Technology Agency | Natural superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film |
| JP4164562B2 (en) | 2002-09-11 | 2008-10-15 | 独立行政法人科学技術振興機構 | Transparent thin film field effect transistor using homologous thin film as active layer |
| US6838654B2 (en)* | 2002-01-17 | 2005-01-04 | Capella Microsystems, Inc. | Photodetection system and circuit for amplification |
| JP4083486B2 (en) | 2002-02-21 | 2008-04-30 | 独立行政法人科学技術振興機構 | Method for producing LnCuO (S, Se, Te) single crystal thin film |
| CN1445821A (en) | 2002-03-15 | 2003-10-01 | 三洋电机株式会社 | Forming method of ZnO film and ZnO semiconductor layer, semiconductor element and manufacturing method thereof |
| JP3933591B2 (en) | 2002-03-26 | 2007-06-20 | 淳二 城戸 | Organic electroluminescent device |
| US7339187B2 (en) | 2002-05-21 | 2008-03-04 | State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University | Transistor structures |
| JP2004022625A (en) | 2002-06-13 | 2004-01-22 | Murata Mfg Co Ltd | Semiconductor device and method of manufacturing the semiconductor device |
| US7105868B2 (en) | 2002-06-24 | 2006-09-12 | Cermet, Inc. | High-electron mobility transistor with zinc oxide |
| US7067843B2 (en) | 2002-10-11 | 2006-06-27 | E. I. Du Pont De Nemours And Company | Transparent oxide semiconductor thin film transistors |
| US20040101309A1 (en)* | 2002-11-27 | 2004-05-27 | Beyette Fred R. | Optical communication imager |
| JP2004187168A (en)* | 2002-12-05 | 2004-07-02 | Sumitomo Electric Ind Ltd | Circuit configuration, optical receiver, and optical link |
| JP4166105B2 (en) | 2003-03-06 | 2008-10-15 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2004273732A (en) | 2003-03-07 | 2004-09-30 | Sharp Corp | Active matrix substrate and manufacturing method thereof |
| US6982406B2 (en)* | 2003-04-03 | 2006-01-03 | Pao Jung Chen | Simple CMOS light-to-current sensor |
| GB0307789D0 (en)* | 2003-04-04 | 2003-05-07 | Koninkl Philips Electronics Nv | Electroluminescent display devices |
| JP4108633B2 (en) | 2003-06-20 | 2008-06-25 | シャープ株式会社 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
| GB2403457A (en)* | 2003-06-30 | 2005-01-05 | Autoliv Dev | Improvements in or relating to an air-bag |
| US7262463B2 (en) | 2003-07-25 | 2007-08-28 | Hewlett-Packard Development Company, L.P. | Transistor including a deposited channel region having a doped portion |
| US7253391B2 (en)* | 2003-09-19 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Optical sensor device and electronic apparatus |
| JP2005129909A (en)* | 2003-09-19 | 2005-05-19 | Semiconductor Energy Lab Co Ltd | Optical sensor device and electronic apparatus |
| US7495272B2 (en)* | 2003-10-06 | 2009-02-24 | Semiconductor Energy Labortaory Co., Ltd. | Semiconductor device having photo sensor element and amplifier circuit |
| EP1523043B1 (en) | 2003-10-06 | 2011-12-28 | Semiconductor Energy Laboratory Co., Ltd. | Optical sensor and method for manufacturing the same |
| JP4481135B2 (en)* | 2003-10-06 | 2010-06-16 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| JP3691050B2 (en)* | 2003-10-30 | 2005-08-31 | 総吉 廣津 | Semiconductor image sensor |
| TWI236533B (en)* | 2003-11-07 | 2005-07-21 | Univ Nat Chiao Tung | Biochemical sensing method and its sensor |
| JP4295075B2 (en)* | 2003-12-05 | 2009-07-15 | 日本電信電話株式会社 | Photoelectric conversion circuit and electric field detection optical device |
| US7282782B2 (en) | 2004-03-12 | 2007-10-16 | Hewlett-Packard Development Company, L.P. | Combined binary oxide semiconductor device |
| CN1998087B (en) | 2004-03-12 | 2014-12-31 | 独立行政法人科学技术振兴机构 | Amorphous oxide and thin film transistor |
| US7297977B2 (en) | 2004-03-12 | 2007-11-20 | Hewlett-Packard Development Company, L.P. | Semiconductor device |
| US7145174B2 (en) | 2004-03-12 | 2006-12-05 | Hewlett-Packard Development Company, Lp. | Semiconductor device |
| KR101197084B1 (en)* | 2004-05-21 | 2012-11-07 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
| US7211825B2 (en) | 2004-06-14 | 2007-05-01 | Yi-Chi Shih | Indium oxide-based thin film transistors and circuits |
| JP4590974B2 (en)* | 2004-08-09 | 2010-12-01 | 住友電気工業株式会社 | Optical receiver circuit |
| US8704803B2 (en)* | 2004-08-27 | 2014-04-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic appliance using the display device |
| JP2006100760A (en) | 2004-09-02 | 2006-04-13 | Casio Comput Co Ltd | Thin film transistor and manufacturing method thereof |
| US7285501B2 (en) | 2004-09-17 | 2007-10-23 | Hewlett-Packard Development Company, L.P. | Method of forming a solution processed device |
| JP4817636B2 (en)* | 2004-10-04 | 2011-11-16 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| US7298084B2 (en) | 2004-11-02 | 2007-11-20 | 3M Innovative Properties Company | Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes |
| KR100953596B1 (en) | 2004-11-10 | 2010-04-21 | 캐논 가부시끼가이샤 | Light emitting device |
| EP2453481B1 (en) | 2004-11-10 | 2017-01-11 | Canon Kabushiki Kaisha | Field effect transistor with amorphous oxide |
| US7863611B2 (en) | 2004-11-10 | 2011-01-04 | Canon Kabushiki Kaisha | Integrated circuits utilizing amorphous oxides |
| US7829444B2 (en) | 2004-11-10 | 2010-11-09 | Canon Kabushiki Kaisha | Field effect transistor manufacturing method |
| US7453065B2 (en) | 2004-11-10 | 2008-11-18 | Canon Kabushiki Kaisha | Sensor and image pickup device |
| AU2005302964B2 (en) | 2004-11-10 | 2010-11-04 | Canon Kabushiki Kaisha | Field effect transistor employing an amorphous oxide |
| US7791072B2 (en) | 2004-11-10 | 2010-09-07 | Canon Kabushiki Kaisha | Display |
| US7579224B2 (en) | 2005-01-21 | 2009-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a thin film semiconductor device |
| TWI505473B (en) | 2005-01-28 | 2015-10-21 | Semiconductor Energy Lab | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
| TWI445178B (en) | 2005-01-28 | 2014-07-11 | Semiconductor Energy Lab | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
| US7858451B2 (en) | 2005-02-03 | 2010-12-28 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device, semiconductor device and manufacturing method thereof |
| US7948171B2 (en) | 2005-02-18 | 2011-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device |
| US7492028B2 (en)* | 2005-02-18 | 2009-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and manufacturing method of the same, and a semiconductor device |
| US20060197092A1 (en) | 2005-03-03 | 2006-09-07 | Randy Hoffman | System and method for forming conductive material on a substrate |
| US8681077B2 (en) | 2005-03-18 | 2014-03-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and display device, driving method and electronic apparatus thereof |
| US7220953B2 (en)* | 2005-03-18 | 2007-05-22 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | Photodiode circuit with improved response time |
| US7544967B2 (en) | 2005-03-28 | 2009-06-09 | Massachusetts Institute Of Technology | Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications |
| TWI395321B (en)* | 2005-03-31 | 2013-05-01 | Semiconductor Energy Lab | Semiconductor device and driving method thereof |
| US7645478B2 (en) | 2005-03-31 | 2010-01-12 | 3M Innovative Properties Company | Methods of making displays |
| US8300031B2 (en) | 2005-04-20 | 2012-10-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising transistor having gate and drain connected through a current-voltage conversion element |
| EP1724844A2 (en)* | 2005-05-20 | 2006-11-22 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device, manufacturing method thereof and semiconductor device |
| JP4809715B2 (en) | 2005-05-20 | 2011-11-09 | 株式会社半導体エネルギー研究所 | Photoelectric conversion device, manufacturing method thereof, and semiconductor device |
| CN100592358C (en) | 2005-05-20 | 2010-02-24 | 株式会社半导体能源研究所 | Display devices and electronic equipment |
| DE602006001686D1 (en)* | 2005-05-23 | 2008-08-21 | Semiconductor Energy Lab | Photoelectric conversion device and method for its production |
| JP2006344849A (en) | 2005-06-10 | 2006-12-21 | Casio Comput Co Ltd | Thin film transistor |
| US7691666B2 (en) | 2005-06-16 | 2010-04-06 | Eastman Kodak Company | Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby |
| US7402506B2 (en) | 2005-06-16 | 2008-07-22 | Eastman Kodak Company | Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby |
| US7507618B2 (en) | 2005-06-27 | 2009-03-24 | 3M Innovative Properties Company | Method for making electronic devices using metal oxide nanoparticles |
| JP2007059889A (en)* | 2005-07-27 | 2007-03-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| WO2007013534A1 (en)* | 2005-07-27 | 2007-02-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| KR100711890B1 (en) | 2005-07-28 | 2007-04-25 | 삼성에스디아이 주식회사 | OLED display and manufacturing method thereof |
| JP2007059128A (en) | 2005-08-23 | 2007-03-08 | Canon Inc | Organic EL display device and manufacturing method thereof |
| JP4429240B2 (en)* | 2005-09-05 | 2010-03-10 | シャープ株式会社 | Optical sensor circuit and light receiving module |
| JP5116225B2 (en) | 2005-09-06 | 2013-01-09 | キヤノン株式会社 | Manufacturing method of oxide semiconductor device |
| JP2007073705A (en) | 2005-09-06 | 2007-03-22 | Canon Inc | Oxide semiconductor channel thin film transistor and method for manufacturing the same |
| JP4850457B2 (en) | 2005-09-06 | 2012-01-11 | キヤノン株式会社 | Thin film transistor and thin film diode |
| JP4280736B2 (en) | 2005-09-06 | 2009-06-17 | キヤノン株式会社 | Semiconductor element |
| JP5100071B2 (en)* | 2005-09-27 | 2012-12-19 | 株式会社半導体エネルギー研究所 | Film forming apparatus, film forming method, and method for manufacturing photoelectric conversion apparatus |
| US7666766B2 (en) | 2005-09-27 | 2010-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Film formation apparatus, method for forming film, and method for manufacturing photoelectric conversion device |
| EP1770788A3 (en) | 2005-09-29 | 2011-09-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having oxide semiconductor layer and manufacturing method thereof |
| US20070090276A1 (en) | 2005-10-03 | 2007-04-26 | Jia Peng | Light detecting device |
| JP5037808B2 (en) | 2005-10-20 | 2012-10-03 | キヤノン株式会社 | Field effect transistor using amorphous oxide, and display device using the transistor |
| CN101577231B (en) | 2005-11-15 | 2013-01-02 | 株式会社半导体能源研究所 | Semiconductor device and method of manufacturing the same |
| KR101389808B1 (en)* | 2005-11-18 | 2014-04-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Photoelectric conversion device |
| TWI292281B (en) | 2005-12-29 | 2008-01-01 | Ind Tech Res Inst | Pixel structure of active organic light emitting diode and method of fabricating the same |
| US7867636B2 (en) | 2006-01-11 | 2011-01-11 | Murata Manufacturing Co., Ltd. | Transparent conductive film and method for manufacturing the same |
| JP4977478B2 (en) | 2006-01-21 | 2012-07-18 | 三星電子株式会社 | ZnO film and method of manufacturing TFT using the same |
| US7576394B2 (en) | 2006-02-02 | 2009-08-18 | Kochi Industrial Promotion Center | Thin film transistor including low resistance conductive thin films and manufacturing method thereof |
| US7977169B2 (en) | 2006-02-15 | 2011-07-12 | Kochi Industrial Promotion Center | Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof |
| US7504616B2 (en)* | 2006-04-10 | 2009-03-17 | Panasonic Corporation | Exposure device and image forming apparatus using the same |
| KR20070101595A (en) | 2006-04-11 | 2007-10-17 | 삼성전자주식회사 | ＺｎＯ ＴＦＴ |
| JP4159582B2 (en) | 2006-04-26 | 2008-10-01 | 松下電器産業株式会社 | Test circuit and test method for photoreceiver / amplifier circuit |
| JP4750070B2 (en)* | 2006-04-27 | 2011-08-17 | 株式会社半導体エネルギー研究所 | Semiconductor device and electronic apparatus using the same |
| KR101315282B1 (en)* | 2006-04-27 | 2013-10-08 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and electronic appliance using the same |
| US20070252928A1 (en) | 2006-04-28 | 2007-11-01 | Toppan Printing Co., Ltd. | Structure, transmission type liquid crystal display, reflection type display and manufacturing method thereof |
| DE602007002105D1 (en) | 2006-04-28 | 2009-10-08 | Semiconductor Energy Lab | Semiconductor device |
| JP5183956B2 (en)* | 2006-04-28 | 2013-04-17 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP5028033B2 (en) | 2006-06-13 | 2012-09-19 | キヤノン株式会社 | Oxide semiconductor film dry etching method |
| JP4609797B2 (en) | 2006-08-09 | 2011-01-12 | Ｎｅｃ液晶テクノロジー株式会社 | Thin film device and manufacturing method thereof |
| JP4999400B2 (en) | 2006-08-09 | 2012-08-15 | キヤノン株式会社 | Oxide semiconductor film dry etching method |
| JP4332545B2 (en) | 2006-09-15 | 2009-09-16 | キヤノン株式会社 | Field effect transistor and manufacturing method thereof |
| JP4274219B2 (en) | 2006-09-27 | 2009-06-03 | セイコーエプソン株式会社 | Electronic devices, organic electroluminescence devices, organic thin film semiconductor devices |
| JP5164357B2 (en) | 2006-09-27 | 2013-03-21 | キヤノン株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US7791012B2 (en) | 2006-09-29 | 2010-09-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising photoelectric conversion element and high-potential and low-potential electrodes |
| JP2008109110A (en)* | 2006-09-29 | 2008-05-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US7622371B2 (en) | 2006-10-10 | 2009-11-24 | Hewlett-Packard Development Company, L.P. | Fused nanocrystal thin film semiconductor and method |
| KR101447044B1 (en)* | 2006-10-31 | 2014-10-06 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US7772021B2 (en) | 2006-11-29 | 2010-08-10 | Samsung Electronics Co., Ltd. | Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays |
| JP2008140684A (en) | 2006-12-04 | 2008-06-19 | Toppan Printing Co Ltd | Color EL display and manufacturing method thereof |
| US8514165B2 (en)* | 2006-12-28 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| KR101303578B1 (en) | 2007-01-05 | 2013-09-09 | 삼성전자주식회사 | Etching method of thin film |
| US8207063B2 (en) | 2007-01-26 | 2012-06-26 | Eastman Kodak Company | Process for atomic layer deposition |
| KR100851215B1 (en) | 2007-03-14 | 2008-08-07 | 삼성에스디아이 주식회사 | Thin film transistor and organic light emitting display device using same |
| WO2008123119A1 (en)* | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and electronic device provided with the photoelectric conversion device |
| JP2008270757A (en)* | 2007-03-26 | 2008-11-06 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US7795613B2 (en) | 2007-04-17 | 2010-09-14 | Toppan Printing Co., Ltd. | Structure with transistor |
| KR101325053B1 (en) | 2007-04-18 | 2013-11-05 | 삼성디스플레이 주식회사 | Thin film transistor substrate and manufacturing method thereof |
| KR20080094300A (en) | 2007-04-19 | 2008-10-23 | 삼성전자주식회사 | Thin film transistors and methods of manufacturing the same and flat panel displays comprising thin film transistors |
| KR101334181B1 (en) | 2007-04-20 | 2013-11-28 | 삼성전자주식회사 | Thin Film Transistor having selectively crystallized channel layer and method of manufacturing the same |
| CN101663762B (en) | 2007-04-25 | 2011-09-21 | 佳能株式会社 | Oxynitride semiconductor |
| KR101345376B1 (en) | 2007-05-29 | 2013-12-24 | 삼성전자주식회사 | Fabrication method of ZnO family Thin film transistor |
| KR101401528B1 (en)* | 2007-06-29 | 2014-06-03 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Photoelectric conversion device and electronic device provided with the photoelectric conversion device |
| WO2009014155A1 (en)* | 2007-07-25 | 2009-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and electronic device having the same |
| US8202365B2 (en) | 2007-12-17 | 2012-06-19 | Fujifilm Corporation | Process for producing oriented inorganic crystalline film, and semiconductor device using the oriented inorganic crystalline film |
| JP4623179B2 (en) | 2008-09-18 | 2011-02-02 | ソニー株式会社 | Thin film transistor and manufacturing method thereof |
| JP5451280B2 (en) | 2008-10-09 | 2014-03-26 | キヤノン株式会社 | Wurtzite crystal growth substrate, manufacturing method thereof, and semiconductor device |
| JP7070064B2 (en)* | 2018-05-11 | 2022-05-18 | 株式会社デンソー | Rotating electric machine control device |
| Publication number | Publication date |
|---|---|
| US8913050B2 (en) | 2014-12-16 |
| JP2009047688A (en) | 2009-03-05 |
| US20120132965A1 (en) | 2012-05-31 |
| JP5222649B2 (en) | 2013-06-26 |
| WO2009014155A1 (en) | 2009-01-29 |
| US8154480B2 (en) | 2012-04-10 |
| TW200925564A (en) | 2009-06-16 |
| US20090027372A1 (en) | 2009-01-29 |
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| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |