本發明係有關於半導體裝置之封裝製造技術，特別係有關於一種非陣列凸塊之覆晶接合方法與構造。The present invention relates to a package fabrication technique for a semiconductor device, and more particularly to a flip chip bonding method and configuration for a non-array bump.
在半導體晶片之封裝製程中，已製作好積體電路的晶片必須與基板(substrate)或是導線架(leadframe)等晶片載體(chip carrier)做一電路聯結才能發揮電子訊號傳遞的功能。習知晶片至晶片載體的電性連接方法有打線接合(wire bonding)、捲帶自動接合(tape automated bonding;TAB)與覆晶接合(flip chip)等。其中，覆晶接合能縮短晶片與基板之間的傳輸距離，具有更優於打線連接的電性性能而逐漸普及。目前在覆晶接合製程所使用的晶片具有陣列排列之凸塊，利用重配置線路層使凸塊均勻分散在晶片的主動面上。近來，有人嘗試使用具非陣列凸塊之晶片進行覆晶接合，由於晶片之凸塊集中分佈在晶片主動面之某一特定區域，例如凸塊位置設在中央銲墊上。並以底部填充膠全面覆蓋晶片下的覆晶間隙。然在底部填充膠的填充過程中，底膠填充速度在凸塊密集區會相對變慢，此一底膠填充速度不一致的現象容易使底部填充膠內部產生氣泡(void)而造成氣阱(air trap)問題或稱之「包封現象(air trap effect)」，其將使半導體晶片的封裝品質大受影響且降低產品的可靠度。In the packaging process of a semiconductor wafer, a wafer in which an integrated circuit has been fabricated must be connected to a chip carrier such as a substrate or a lead frame to perform an electronic signal transmission function. Conventional methods for electrically connecting a wafer to a wafer carrier include wire bonding, tape automated bonding (TAB), and flip chip bonding. Among them, the flip-chip bonding can shorten the transmission distance between the wafer and the substrate, and has an electrical property superior to that of the wire bonding, and is gradually popularized. Currently, the wafers used in the flip chip bonding process have bumps arranged in an array, and the bumps are used to uniformly spread the bumps on the active surface of the wafer. Recently, attempts have been made to perform flip chip bonding using a wafer having non-array bumps, since the bumps of the wafer are concentratedly distributed in a specific region of the active surface of the wafer, for example, the bump is disposed on the center pad. The underfill gap under the wafer is completely covered by the underfill. However, during the filling process of the underfill, the filling speed of the underfill will be relatively slow in the dense area of the bump, and the inconsistent filling speed of the underfill tends to cause bubbles inside the underfill to cause air traps (air The trap problem, or "air trap effect", will greatly impair the package quality of the semiconductor wafer and reduce the reliability of the product.
如第1圖所示，一種習知的非陣列凸塊之覆晶接合構造100主要包含一基板110、一晶片130與一底部填充膠140。在例如印刷電路板之基板110之一上表面111設有複數個接墊112。該晶片130之一主動面131係朝向該基板110之該上表面111，並且該主動面131上設有複數個非陣列排列之凸塊133，其係對準於該些接墊112。具體而言，該些凸塊133係設置於該主動面131之複數個中央銲墊134。該底部填充膠140係先點塗在該基板110之該上表面111，並利用毛細作用填滿於該晶片130與該基板110之間的覆晶間隙，全面覆蓋該晶片130之主動面131，進而密封該些凸塊133。由於該些凸塊133分佈不均勻，都會造成該底部填充膠140之填充速度的變化。所以，使得該底部填充膠140通過該些凸塊133與未設有凸塊之區域的流速不一致，除了無法緊密地填滿該晶片130與該基板110之間，更容易於該底部填充膠140內部產生氣泡141，即氣阱問題，導致產品可靠度降低。特別是，由於該些凸塊133為非陣列排列，在覆晶接合時難以控制該晶片130相對於該基板110之水平度，一旦該晶片130傾斜，則氣阱問題將更為嚴重。As shown in FIG. 1 , a conventional non-array bump flip chip bonding structure 100 mainly includes a substrate 110 , a wafer 130 and an underfill 140 . A plurality of pads 112 are provided on an upper surface 111 of a substrate 110 such as a printed circuit board. The active surface 131 of the wafer 130 faces the upper surface 111 of the substrate 110, and the active surface 131 is provided with a plurality of non-array array bumps 133 aligned with the pads 112. Specifically, the bumps 133 are disposed on the plurality of central pads 134 of the active surface 131 . The underfill layer 140 is firstly applied to the upper surface 111 of the substrate 110, and is filled with a flip-chip gap between the wafer 130 and the substrate 110 by capillary action to completely cover the active surface 131 of the wafer 130. The bumps 133 are sealed. Due to the uneven distribution of the bumps 133, the filling speed of the underfill 140 changes. Therefore, the flow rate of the underfill layer 140 through the bumps 133 and the region where the bumps are not provided is inconsistent, except that the wafer 130 and the substrate 110 cannot be tightly filled, and the underfill 140 is more easily used. The bubble 141 is generated inside, that is, the gas trap problem, resulting in a decrease in product reliability. In particular, since the bumps 133 are non-array arrays, it is difficult to control the level of the wafer 130 relative to the substrate 110 during flip chip bonding. Once the wafer 130 is tilted, the gas trap problem will be more serious.
有鑒於此，本發明之主要目的係在於提供一種非陣列凸塊之覆晶接合方法與構造，除了可以避免非陣列凸塊之晶片傾斜，更能解決非陣列凸塊之覆晶接合製程中全面底膠填充速度不一致造成的氣阱問題。In view of this, the main object of the present invention is to provide a flip chip bonding method and structure for non-array bumps, which can avoid the tilt of the non-array bumps, and can better solve the full-coverage process of the non-array bumps. The air trap problem caused by the inconsistent filling speed of the primer.
本發明之次一目的係在於提供一種非陣列凸塊之覆晶接合方法與構造，節省非陣列凸塊之覆晶接合製程中底膠填充時間與底膠用量。A second object of the present invention is to provide a flip chip bonding method and structure for non-array bumps, which can save the underfill filling time and the amount of primer in the flip chip bonding process of non-array bumps.
本發明之再一目的係在於提供一種非陣列凸塊之覆晶接合方法與構造，方便檢視非陣列凸塊之晶片在覆晶接合後的水平度。A further object of the present invention is to provide a flip chip bonding method and structure for non-array bumps, which facilitates viewing the level of wafers of non-array bumps after flip chip bonding.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種非陣列凸塊之覆晶接合方法，主要包含以下步驟：提供一基板，其上表面係設有複數個接墊。形成複數個支撐膠體於該基板之該上表面，該些支撐膠體之間係形成為一底膠通道，以顯露出該些接墊。覆晶接合一晶片至該基板上，使該晶片之一主動面朝向該基板之該上表面並使該主動面之一凸塊空白區黏附於該些支撐膠體，該晶片之該主動面係設有複數個非陣列之凸塊，其係位於該底膠通道中並對準於該些接墊。施壓該晶片，以使得該些支撐膠體形成有一超出該晶片之擠料邊框，並使該些凸塊接合至該些接墊，其中該擠料邊框具有複數個連通該底膠通道之開口。之後，經由該擠料邊框之其中一開口提供一底部填充膠，直到該底部填充膠填滿該底膠通道，以密封該些凸塊。本發明另揭示依照上述方法所製成之構造。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a flip chip bonding method for non-array bumps, which mainly comprises the following steps: providing a substrate having a plurality of pads on the upper surface thereof. A plurality of supporting colloids are formed on the upper surface of the substrate, and the supporting colloids are formed as a primer channel to expose the pads. Bonding a wafer to the substrate such that an active surface of the wafer faces the upper surface of the substrate and a bump blank region of the active surface is adhered to the supporting colloids, and the active surface of the wafer is set There are a plurality of non-array bumps located in the primer channel and aligned with the pads. The wafer is pressed such that the support colloids form an extrusion frame beyond the wafer and the bumps are joined to the pads, wherein the extrusion frame has a plurality of openings that communicate with the primer passage. Thereafter, an underfill is provided through one of the openings of the extrusion frame until the underfill fills the primer passage to seal the bumps. The invention further discloses a construction made in accordance with the above method.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之覆晶接合方法中，該擠料邊框之高度係可超過該底膠通道，更包覆至該晶片之主動面角隅。In the foregoing flip chip bonding method, the height of the extrusion frame may exceed the primer channel and be coated to the active face angle of the wafer.
在前述之覆晶接合方法中，該些凸塊係可設置於該晶片在該主動面上的複數個中央銲墊。In the above flip chip bonding method, the bumps may be disposed on a plurality of central pads of the wafer on the active surface.
在前述之覆晶接合方法中，該些支撐膠體之形成高度係可大於該些凸塊之高度，並且在施壓該晶片之後，該底膠通道的高度係略小於該些凸塊之高度。In the above-mentioned flip chip bonding method, the formation height of the support colloids may be greater than the height of the bumps, and after the wafer is pressed, the height of the underfill channel is slightly smaller than the height of the bumps.
在前述之覆晶接合方法中，該些支撐膠體係可為B階黏膠。In the foregoing flip chip bonding method, the support adhesive systems may be B-stage adhesives.
在前述之覆晶接合方法中，該些支撐膠體的形成方法係可為先液態型態印刷在該基板之該上表面，再部分固化為B階狀態。In the above-described flip chip bonding method, the supporting colloids may be formed by printing on the upper surface of the substrate in a liquid state and then partially curing into a B-stage state.
由以上技術方案可以看出，本發明之非陣列凸塊之覆晶接合方法，具有以下優點與功效：It can be seen from the above technical solutions that the flip chip bonding method of the non-array bump of the present invention has the following advantages and effects:
一、可藉由在形成支撐膠體於基板之上表面、施壓晶片以使得支撐膠體形成超出晶片之擠料邊框以及經由擠料邊框之開口提供底部填充膠作為其中之一基本技術手段，除了可以避免非陣列凸塊之晶片傾斜，更可解決非陣列凸塊之覆晶接合製程中全面底膠填充速度不一致造成的氣阱問題。1. The basic technical means can be provided by forming a supporting colloid on the upper surface of the substrate, pressing the wafer to form the supporting colloid to form an extrusion frame beyond the wafer, and providing an underfill via the opening of the extrusion frame. The wafer tilt of the non-array bumps can be avoided, and the air trap problem caused by the inconsistent overall fill speed of the non-array bumps in the flip chip bonding process can be solved.
二、可藉由在形成支撐膠體於基板之上表面、施壓晶片以使得支撐膠體形成超出晶片之擠料邊框以及經由擠料邊框之開口提供底部填充膠作為其中之一基本技術手段，能夠節省非陣列凸塊之覆晶接合製程中底膠填充時間與底膠用量。Second, it can be saved by forming a supporting colloid on the upper surface of the substrate, pressing the wafer to form the supporting colloid to form an extrusion frame beyond the wafer, and providing the underfill through the opening of the extrusion frame as one of the basic technical means. The filling time and the amount of primer used in the flip chip bonding process of non-array bumps.
三、可藉由在形成支撐膠體於基板之上表面、施壓晶片以使得支撐膠體形成超出晶片之擠料邊框以及經由擠料邊框之開口提供底部填充膠作為其中之一基本技術手段，能夠方便檢視非陣列凸塊之晶片在覆晶接合後的水平度。3. It can be facilitated by forming the supporting colloid on the upper surface of the substrate, pressing the wafer to form the supporting colloid to form the extrusion frame beyond the wafer, and providing the underfill through the opening of the extrusion frame as one of the basic technical means. The level of the non-array bump wafer after flip chip bonding is examined.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之第一具體實施例，一種非陣列凸塊之覆晶接合方法舉例說明於第2圖之方塊流程圖與第3A至3G圖之各步驟中元件截面圖。該非陣列凸塊之覆晶接合方法根據第2圖，包含以下主要步驟：「提供一基板」之步驟1、「形成支撐膠體於基板之上表面」之步驟2、「覆晶接合晶片至基板」之步驟3、「施壓晶片」之步驟4以及「提供底部填充膠」之步驟5，在各步驟上表現出的元件請參閱第3A至3G圖，詳細說明如下所示。According to a first embodiment of the present invention, a flip chip bonding method of a non-array bump is exemplified in the block diagrams of the block diagram of FIG. 2 and the steps of the 3A to 3G diagram. According to FIG. 2, the flip chip bonding method of the non-array bump includes the following main steps: step 1 of "providing a substrate", "step 2 of forming a supporting colloid on the upper surface of the substrate", and "chip-bonding the wafer to the substrate" In step 3, step 4 of "pressing the wafer" and step 5 of "providing the underfill", the components shown in each step are referred to the drawings 3A to 3G, and the details are as follows.
首先，執行步驟1。請參閱第3A圖所示，提供一基板210，其上表面211係設有複數個接墊212。詳細而言，該些接墊212係可呈單或雙排排列於該上表面211之中央區域，以提供電性連接之作用。該基板210的主體係可使用硬性或軟性的基板，其他常用的基板包括雙馬來亞醯胺-三氮雜苯樹脂(BT)基板；環氧樹脂/玻璃纖維多層板，例如FR4板；及陶瓷基板，這些材料均是半導體業所知悉並使用的材料。基本上，該基板210可為一印刷電路板(printed circuit board,PCB)或是陶瓷電路板，作為半導體封裝結構內晶片承載與電性連接之主要媒介物。First, go to step 1. Referring to FIG. 3A, a substrate 210 is provided, and the upper surface 211 is provided with a plurality of pads 212. In detail, the pads 212 may be arranged in a single or double row in a central region of the upper surface 211 to provide an electrical connection. The main system of the substrate 210 may use a rigid or flexible substrate, and other commonly used substrates include a bismaleimide-triazole resin (BT) substrate; an epoxy/glass fiber multilayer board such as an FR4 board; Ceramic substrates, which are materials that are known and used by the semiconductor industry. Basically, the substrate 210 can be a printed circuit board (PCB) or a ceramic circuit board as a main medium for carrying and electrically connecting the wafers in the semiconductor package structure.
執行步驟2，請參閱第3B與4圖所示，形成複數個支撐膠體220於該基板210之該上表面211，該些支撐膠體220之間係形成為一底膠通道221，以顯露出該些接墊212。在本實施例中，該些支撐膠體220係可為B階(B-stage)黏膠。具體而論，該些支撐膠體220係可為部分固化之熱固性樹脂，例如可包含不同固化溫度的環氧化合物之成分組合。該些支撐膠體220的形成方法係可為先液態型態印刷在該基板210之該上表面211，再部分固化為B階狀態。在形成於該基板210上時可呈現為液態，在以加熱方式使其部分固化。在本步驟完成之後，該些支撐膠體220係可呈現膠稠態而不會隨意流動，並可提供一定的支撐效果，並維持黏著晶片的功用。細部來說，在印刷形成該些支撐膠體220之後，可藉由一低溫烘烤動作，使該些支撐膠體220從液態轉化為部分固化之B階狀態，進而使該些支撐膠體220附著於該基板210之該上表面211。在一較佳實施例中，該些支撐膠體220係可呈條狀而分佈於該些接墊212之兩側(如第4圖所示)，故該底膠通道221形成在該基板210之中央區域，並且該底膠通道221之方向係可平行於該些接墊212之排列方向。Step 2, as shown in FIGS. 3B and 4, a plurality of supporting colloids 220 are formed on the upper surface 211 of the substrate 210. The supporting colloids 220 are formed as a primer channel 221 to reveal the Some pads 212. In this embodiment, the supporting colloids 220 can be B-stage adhesives. In particular, the support colloids 220 can be partially cured thermosetting resins, such as a combination of ingredients that can include epoxy compounds at different curing temperatures. The method for forming the supporting colloids 220 may be printed on the upper surface 211 of the substrate 210 in a liquid state, and then partially cured to a B-stage state. When formed on the substrate 210, it may be in a liquid state and partially cured in a heated manner. After the completion of this step, the supporting colloids 220 can be in a colloidal state without flowing freely, and can provide a certain supporting effect and maintain the function of the adhesive wafer. In detail, after the printing of the supporting colloids 220, the supporting colloids 220 can be converted from a liquid state to a partially cured B-stage state by a low-temperature baking action, thereby allowing the supporting colloids 220 to adhere thereto. The upper surface 211 of the substrate 210. In a preferred embodiment, the supporting colloids 220 are distributed on the two sides of the pads 212 (as shown in FIG. 4 ), so that the primer channel 221 is formed on the substrate 210 . The central region, and the direction of the primer channel 221 can be parallel to the arrangement direction of the pads 212.
執行步驟3。請參閱第3C圖所示，覆晶接合一晶片230至該基板210上，使該晶片230之一主動面231朝向該基板210之該上表面211。如第3D圖所示，進一步使得該主動面231之一凸塊空白區232黏附於該些支撐膠體220。該晶片230之該主動面231係設有複數個非陣列之凸塊233，其係位於該底膠通道221中並對準於該些接墊212。詳細而言，該凸塊空白區232係指該晶片230之該主動面231上未形成有該些凸塊233之區域，該區域的長度與寬度應大於凸塊節距的兩倍以上。而「非陣列」則表示該些凸塊233的形成區域為區域化，小於該主動面231的二分之一。由於該些支撐膠體220所提供予該晶片230的支撐效果，使得該晶片230將先行黏附於該些支撐膠體220上，其後再使該晶片230之該些凸塊233接合至該些接墊212。也就是說，在本步驟中該底膠通道221之高度(即該些支撐膠體220的形成厚度)係可大於該些凸塊233之高度。詳細而言，該晶片230係已形成有積體電路(integrated circuit,IC)元件，例如記憶體、邏輯元件以及特殊應用積體電路(ASIC)，可由一晶圓(wafer)分割成顆粒狀。在本實施例中，該些凸塊233係可設置於該晶片230在該主動面231上的複數個中央銲墊234，以省略重配置線路層的製作。但在該些中央銲墊234與該些凸塊233之間則另可設置凸塊下金屬層(under bump metallurgy，UBM，圖中未繪出)，以防止該些凸塊233內成份的金屬擴散至該些中央銲墊234。更具體地，該些凸塊233之材質係可包含金、銅、鋁、錫或其合金，或可為錫鉛，可利用電鍍方式形成，並可利用研磨或表面平坦化技術，使得該些凸塊233之頂面為平坦而具有相同之高度。在本實施例中，該些凸塊233的成份係可為純錫或無鉛之錫合金。較佳地，在該步驟中，該些凸塊233與該些接墊212保持在微接觸狀態或留有一非接觸間隙，即表示在覆晶接合步驟中該些凸塊233與該些接墊212之間不形成金屬鍵合關係。倘若該晶片230發生傾斜之情況，可直接針對該晶片230之傾斜部位進行微調，以使該晶片230保持水平之狀態。因此，人員能夠輕易地控制該晶片230之水平度，毋須擔心該底部填充膠240充填於該晶片230與該基板210之間時會因該晶片230傾斜而導致氣阱問題。Go to step 3. Referring to FIG. 3C, a wafer 230 is flip-chip bonded to the substrate 210 such that an active surface 231 of the wafer 230 faces the upper surface 211 of the substrate 210. As shown in FIG. 3D, a bump blank region 232 of the active surface 231 is further adhered to the support colloids 220. The active surface 231 of the wafer 230 is provided with a plurality of non-array bumps 233 located in the primer channel 221 and aligned with the pads 212. In detail, the bump blank area 232 refers to the area of the active surface 231 of the wafer 230 where the bumps 233 are not formed, and the length and width of the area should be more than twice the bump pitch. The "non-array" indicates that the formation regions of the bumps 233 are regionalized, which is less than one-half of the active surface 231. Due to the supporting effect of the supporting colloids 220 on the wafer 230, the wafer 230 will be adhered to the supporting colloids 220 first, and then the bumps 233 of the wafer 230 are bonded to the pads. 212. That is, the height of the primer channel 221 (ie, the thickness of the support colloids 220) may be greater than the height of the bumps 233 in this step. In detail, the wafer 230 is formed with integrated circuit (IC) components such as a memory, a logic element, and an application specific integrated circuit (ASIC), which may be divided into a pellet by a wafer. In this embodiment, the bumps 233 can be disposed on the plurality of central pads 234 of the wafer 230 on the active surface 231 to omit the fabrication of the reconfigured wiring layer. However, between the central solder pads 234 and the bumps 233, an under bump metal layer (UBM, not shown) may be disposed to prevent metal components in the bumps 233. Diffused to the central pads 234. More specifically, the material of the bumps 233 may include gold, copper, aluminum, tin or alloys thereof, or may be tin-lead, may be formed by electroplating, and may be made by grinding or surface planarization techniques. The top surface of the bump 233 is flat and has the same height. In this embodiment, the components of the bumps 233 may be pure tin or a lead-free tin alloy. Preferably, in the step, the bumps 233 and the pads 212 are maintained in a micro-contact state or have a non-contact gap, that is, the bumps 233 and the pads are formed in the flip chip bonding step. No metal bonding relationship is formed between 212. If the wafer 230 is tilted, the tilted portion of the wafer 230 can be directly fine-tuned to maintain the wafer 230 in a horizontal state. Therefore, the level of the wafer 230 can be easily controlled by a person, and there is no fear that the underfill 240 will cause a gas trap problem due to the tilt of the wafer 230 when it is filled between the wafer 230 and the substrate 210.
執行步驟4。請參閱第3E圖所示，施壓該晶片230，以使得該些支撐膠體220形成有一超出該晶片230之擠料邊框222，並使該些凸塊233接合至該些接墊212，其中該擠料邊框222具有複數個連通該底膠通道221之開口223。所謂的「超出晶片」表示該擠料邊框222不在該晶片230下方之表面覆蓋區(footprint)內。具體而言，由於該些支撐膠體220係呈膠稠態，隨著覆晶接合溫度升高會變得稍有流動性，在受到該晶片230向下壓迫時，會稍微向兩側擴散而變形。當該些凸塊233接觸並接合至該些接墊212，便達成該晶片230與該基板210的電性連接關係，該些支撐膠體220則停止變形。該擠料邊框222之高度應超過該晶片230之主動面231，即較高於該些支撐膠體220在該晶片230下的厚度。該些開口223應對準在該些凸塊233的排列方向，而位於該底膠通道221之兩端。在一較佳實施例中，該擠料邊框222之高度係可超過該底膠通道221之高度，更包覆至該晶片230之主動面231角隅。因此，能夠避免該晶片230之主動面231角隅的應力施加至該基板210，以防止應力集中之情況發生。具體而言，該些擠料邊框222係可覆蓋至該晶片230側邊厚度之二分之一以上，以提供完善的支撐與固定效果。較佳地，在本步驟中，該些擠料邊框222之寬度若產生有不一致的現象時，其中一側變大表示該晶片230在該側係朝向該基板210之方向傾斜。因此，可在該基板210之該上表面211進行光學檢測該些擠料邊框222之寬度變化(檢測方向如第6圖所示)，即可輕易判斷該基板210上之該晶片230在覆晶接合後有無發生傾斜現象，能夠方便檢視非陣列凸塊之晶片在覆晶接合後的水平度。Go to step 4. Referring to FIG. 3E, the wafer 230 is pressed such that the support colloids 220 are formed with an extrusion frame 222 extending beyond the wafer 230, and the bumps 233 are bonded to the pads 212. The extrusion frame 222 has a plurality of openings 223 that communicate with the primer passage 221 . By "beyond the wafer" is meant that the extrusion frame 222 is not within the surface footprint below the wafer 230. Specifically, since the supporting colloids 220 are in a colloidal state, they become slightly fluid as the flip-chip bonding temperature increases, and are slightly diffused to the sides when the wafer 230 is pressed downward. . When the bumps 233 are in contact with and bonded to the pads 212, the electrical connection between the wafer 230 and the substrate 210 is achieved, and the support colloids 220 stop deforming. The height of the extrusion frame 222 should exceed the active surface 231 of the wafer 230, that is, higher than the thickness of the support colloids 220 under the wafer 230. The openings 223 should be aligned in the direction in which the bumps 233 are arranged, and located at both ends of the primer channel 221 . In a preferred embodiment, the height of the extrusion frame 222 can exceed the height of the primer channel 221 and be coated to the active surface 231 of the wafer 230. Therefore, it is possible to prevent the stress of the active surface 231 of the wafer 230 from being applied to the substrate 210 to prevent stress concentration from occurring. Specifically, the extrusion frame 222 can cover more than one-half of the thickness of the side of the wafer 230 to provide a perfect support and fixation effect. Preferably, if there is an inconsistency in the width of the extrusion frame 222 in this step, a larger one side indicates that the wafer 230 is inclined in a direction in which the side is oriented toward the substrate 210. Therefore, the width of the extrusion frame 222 can be optically detected on the upper surface 211 of the substrate 210 (the detection direction is as shown in FIG. 6), and the wafer 230 on the substrate 210 can be easily judged to be flipped. Whether or not tilting occurs after bonding can easily check the level of the wafer after non-array bumps after flip chip bonding.
特別是，該些支撐膠體220之形成高度係可大於該些凸塊233之高度，並且在施壓該晶片230之後，該底膠通道221的高度係略小於該些凸塊233之高度。因此，能確保該些凸塊233能接觸接合至該些接墊212，以達成該晶片230與該基板210之電性連接關係。此外，該些凸塊233接合至該些接墊212的方式有幾種，其中一種是以該些凸塊233之端面產生部分融熔或活化，以接合至該些接墊212，在接合後該些凸塊233的高度將稍微減少，該些凸塊233可選用金凸塊或錫凸塊；或者，可以利用銲料(圖中未繪出)焊接該些凸塊233之端面與該些接墊212，該些凸塊233可選用銅柱。在完成電性連接之後，該底膠通道221之高度係可略小於該些凸塊233之原來的高度。In particular, the height of the support colloids 220 may be greater than the height of the bumps 233, and the height of the primer channels 221 is slightly smaller than the height of the bumps 233 after the wafer 230 is pressed. Therefore, it can be ensured that the bumps 233 can be contact-bonded to the pads 212 to achieve an electrical connection relationship between the wafer 230 and the substrate 210. In addition, there are several ways for the bumps 233 to be joined to the pads 212, one of which is partially melted or activated by the end faces of the bumps 233 to be bonded to the pads 212 after the bonding. The height of the bumps 233 may be slightly reduced. The bumps 233 may be formed with gold bumps or tin bumps. Alternatively, the solder bumps (not shown) may be used to solder the end faces of the bumps 233 to the contacts. Pad 212, the bumps 233 may be selected from copper posts. After the electrical connection is completed, the height of the primer channel 221 may be slightly smaller than the original height of the bumps 233.
之後，執行步驟5，請參閱第3F、5及6圖所示，藉由一注射器241經由該擠料邊框222之其中一開口223提供一底部填充膠240(underfill material)。該注射器241持續補充該底部填充膠240，直到該底部填充膠240已確實填滿該底膠通道221，以密封該些凸塊233(如第3G圖所示)。當提供該底部填充膠240時，可由其中之一開口223開始充填，並且該底部填充膠240會因毛細作用原理而逐漸朝向該底膠通道221內填入，直到該底部填充膠240完全充滿於該底膠通道221，但非全面填滿該晶片230與該基板210之間的覆晶間隙。由於該底部填充膠240僅需要填滿凸塊密集區之該底膠通道221，不需要考慮底膠填充速度不一致的因素，故在填充過程中較佳地可傾斜該基板210，以加快該底部填充膠240之流動速度，進而提昇填充速率。Thereafter, step 5 is performed. As shown in FIGS. 3F, 5 and 6, an underfill material is provided via an opening 223 of the extrusion frame 222 by a syringe 241. The syringe 241 continues to replenish the underfill 240 until the underfill 240 has indeed filled the primer channel 221 to seal the bumps 233 (as shown in FIG. 3G). When the underfill 240 is provided, the filling may be started by one of the openings 223, and the underfill 240 may be gradually filled into the primer passage 221 due to the capillary action principle until the underfill 240 is completely filled. The primer channel 221 does not completely fill the gap between the wafer 230 and the substrate 210. Since the underfill 240 only needs to fill the underfill channel 221 of the bump dense region, it is not necessary to consider the inconsistency of the underfill filling speed, so the substrate 210 can be preferably tilted during the filling process to speed up the bottom portion. The flow velocity of the filler 240, which in turn increases the fill rate.
之後，可執行一後烘烤步驟，以加熱方式固化該底部填充膠240與該些支撐膠體220。在執行該後烘烤步驟之前，該些凸塊233與該些接墊212係已完成電性連接與機械連接之關係。具體而言，該底部填充膠240之固化溫度與該些支撐膠體220之固化溫度係可低於該些凸塊233與該些接墊212之接合溫度，以確保該底部填充膠240與該些支撐膠體220在完全固化過程中該些凸塊233與該些接墊212之間接合良好。Thereafter, a post-baking step may be performed to thermally cure the underfill 240 and the support colloids 220. Before the post-baking step is performed, the bumps 233 and the pads 212 have been electrically connected and mechanically connected. Specifically, the curing temperature of the underfill 240 and the curing temperature of the supporting colloids 220 may be lower than the bonding temperature of the bumps 233 and the pads 212 to ensure the underfill 240 and the The support colloid 220 is well joined between the bumps 233 and the pads 212 during the complete curing process.
在本發明中，可藉由在形成該些支撐膠體220於該基板210之該上表面211、施壓該晶片230以使得該些支撐膠體220形成超出該晶片230之該些擠料邊框222以及經由該些擠料邊框222之該些開口223提供該底部填充膠240作為其中之一基本技術手段，由於該些支撐膠體220能夠支撐該晶片230並維持一定的水平度，故可以避免非陣列凸塊之晶片傾斜的問題。並且，由於該些支撐膠體220的存在能佔去凸塊空白區的底膠填充空間，將使習知需要全面填充的覆晶間隙減縮為僅有凸塊密集區之該底膠通道221。該底部填充膠240僅需要以流道方式填入該晶片230與該基板210之間的凸塊密集區，故可解決非陣列凸塊之覆晶接合製程中全面底膠填充速度不一致造成的氣阱問題。此外，亦能夠節省該底部填充膠240之填充時間與用量。In the present invention, the wafer 230 can be pressed on the upper surface 211 of the substrate 210 by forming the supporting colloids 220 so that the supporting colloids 220 form the extrusion frame 222 beyond the wafer 230 and The underfill rubber 240 is provided as one of the basic technical means through the openings 223 of the extrusion frame 222. Since the supporting colloids 220 can support the wafer 230 and maintain a certain level, non-array convexity can be avoided. The problem of tilting the wafer of the block. Moreover, since the presence of the supporting colloids 220 can occupy the underfill filling space of the blank regions of the bumps, the conventionally filled flip-chip gaps need to be reduced to the underfill channels 221 having only the bump-dense regions. The underfill 240 only needs to fill the bump dense region between the wafer 230 and the substrate 210 in a flow path manner, so that the gas caused by the inconsistent filling speed of the full primer in the flip chip bonding process of the non-array bump can be solved. Well problem. In addition, the filling time and amount of the underfill 240 can also be saved.
本發明還揭示使用前述方法所製成之非陣列凸塊之覆晶接合構造舉例說明於第3G圖。該非陣列凸塊之覆晶接合構造200係主要包含一基板210、複數個支撐膠體220、一晶片230以及一底部填充膠240。The present invention also discloses a flip chip bonding structure using the non-array bumps produced by the foregoing method, as exemplified in FIG. 3G. The flip chip bonding structure 200 of the non-array bumps mainly comprises a substrate 210, a plurality of supporting colloids 220, a wafer 230, and an underfill 240.
該基板210之一上表面211係設有複數個接墊212。該些接墊212係設置於該上表面211之中央區域，且呈雙排排列。詳細而言，該基板210之下表面(即相對於該上表面211之表面)係可另設置有複數個外接端子(圖中未繪出)，以提供對外連接之作用。該些支撐膠體220係形成於該基板210之該上表面211，該些支撐膠體220之間係形成為一底膠通道221，以顯露出該些接墊212。也就是說，該些支撐膠體220與該些接墊212之間係可具有一定的距離，而不會覆蓋至該些接墊212。在本實施例中，該些支撐膠體220係可為B階(B-stage)黏膠。One of the upper surfaces 211 of the substrate 210 is provided with a plurality of pads 212. The pads 212 are disposed in a central region of the upper surface 211 and are arranged in a double row. In detail, the lower surface of the substrate 210 (ie, the surface relative to the upper surface 211) may be additionally provided with a plurality of external terminals (not shown) to provide an external connection. The support colloids 220 are formed on the upper surface 211 of the substrate 210. The support colloids 220 are formed as a primer channel 221 to expose the pads 212. That is to say, the supporting colloids 220 and the pads 212 may have a certain distance without covering the pads 212. In this embodiment, the supporting colloids 220 can be B-stage adhesives.
該晶片230係覆晶接合至該基板210上，使該晶片230之一主動面231朝向該基板210之該上表面211並使該主動面231之一凸塊空白區232黏附於該些支撐膠體220，該晶片230之該主動面231係設有複數個非陣列之凸塊233，其係位於該底膠通道221中並對準於該些接墊212，並且藉由施壓該晶片230，以使得該些支撐膠體220形成有一超出該晶片230之擠料邊框222，並使該些凸塊233接合至該些接墊212，其中該擠料邊框222具有複數個連通該底膠通道221之開口223。在一較佳實施例中，該擠料邊框222之高度係可超過該底膠通道221，更包覆至該晶片230之主動面231角隅。詳細而言，該些凸塊233係可設置於該晶片230在該主動面231上的複數個中央銲墊234。該底部填充膠240係經由該擠料邊框222之其中一開口223所提供，該底部填充膠240係填滿該底膠通道221，以密封該些凸塊233。The wafer 230 is flip-chip bonded to the substrate 210 such that an active surface 231 of the wafer 230 faces the upper surface 211 of the substrate 210 and a bump blank region 232 of the active surface 231 is adhered to the support colloids. The active surface 231 of the wafer 230 is provided with a plurality of non-array bumps 233 located in the primer channel 221 and aligned with the pads 212, and by pressing the wafer 230, The support frame 220 is formed with an extrusion frame 222 extending beyond the wafer 230, and the bumps 233 are joined to the pads 212. The extrusion frame 222 has a plurality of the primer channels 221 connected thereto. Opening 223. In a preferred embodiment, the height of the extrusion frame 222 can exceed the primer channel 221 and the angle of the active surface 231 of the wafer 230. In detail, the bumps 233 can be disposed on the plurality of central pads 234 of the wafer 230 on the active surface 231 . The underfill 240 is provided through one of the openings 223 of the extrusion frame 222. The underfill 240 fills the primer channel 221 to seal the bumps 233.
藉由該些支撐膠體220所提供的支撐作用，該晶片230與該基板210之間能維持一定的水平度，故可以避免非陣列凸塊之晶片傾斜的問題，並節省底部填充膠之用量。藉由該些支撐膠體220所提供的黏著作用，可省略黏晶材料。並且，該底部填充膠240僅是填入至該底膠通道221內，而不用全面填滿於該晶片230與該基板210之間，可解決非陣列凸塊之覆晶接合製程中全面底膠填充速度不一致造成的氣阱問題。此外，光學檢測該些擠料邊框222之寬度，即可輕易判斷該基板210上之該晶片230是否有傾斜現象產生，能夠方便檢視非陣列凸塊之晶片在覆晶接合後的水平度。With the support provided by the supporting colloids 220, the wafer 230 and the substrate 210 can maintain a certain level, so that the problem of tilting the wafers of the non-array bumps can be avoided, and the amount of the underfill can be saved. The viscous material can be omitted by the adhesive effect provided by the support colloids 220. Moreover, the underfill 240 is only filled into the primer channel 221 without completely filling the wafer 230 and the substrate 210, and can solve the comprehensive primer in the flip chip bonding process of the non-array bump. Air trap problems caused by inconsistent fill speeds. In addition, optically detecting the width of the extrusion frame 222, it can be easily determined whether the wafer 230 on the substrate 210 has a tilt phenomenon, and the level of the wafer after the flip chip bonding can be conveniently viewed.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
步驟1 提供一基板Step 1 provides a substrate
步驟2 形成支撐膠體於基板之上表面Step 2 Form a supporting colloid on the upper surface of the substrate
步驟3 覆晶接合晶片至基板Step 3 flip-chip bonding the wafer to the substrate
步驟4 施壓晶片Step 4 Pressure the wafer
步驟5 提供底部填充膠Step 5 Provide underfill
100．．．非陣列凸塊之覆晶接合構造100. . . Flip bonded structure of non-array bumps
110．．．基板110. . . Substrate
111．．．上表面111. . . Upper surface
112．．．接墊112. . . Pad
130．．．晶片130. . . Wafer
131．．．主動面131. . . Active surface
133．．．凸塊133. . . Bump
134．．．中央銲墊134. . . Central pad
140．．．底部填充膠140. . . Underfill
141．．．氣泡141. . . bubble
200．．．非陣列凸塊之覆晶接合構造200. . . Flip bonded structure of non-array bumps
210．．．基板210. . . Substrate
211．．．上表面211. . . Upper surface
212．．．接墊212. . . Pad
220．．．支撐膠體220. . . Support colloid
221．．．底膠通道221. . . Primer channel
222．．．擠料邊框222. . . Squeezing border
223．．．開口223. . . Opening
230．．．晶片230. . . Wafer
231．．．主動面231. . . Active surface
232．．．凸塊空白區232. . . Bump blank area
233．．．凸塊233. . . Bump
234．．．中央銲墊234. . . Central pad
240．．．底部填充膠240. . . Underfill
241．．．注射器241. . . syringe
第1圖：一種習知非陣列凸塊之覆晶接合構造之截面示意圖。Figure 1 is a schematic cross-sectional view showing a flip chip bonding structure of a conventional non-array bump.
第2圖：依據本發明之一具體實施例的一種非陣列凸塊之覆晶接合方法之方塊流程圖。2 is a block flow diagram of a flip chip bonding method of a non-array bump according to an embodiment of the present invention.
第3A至3G圖：依據本發明之一具體實施例的非陣列凸塊之覆晶接合方法在各步驟中之元件截面圖。3A to 3G are cross-sectional views of the elements in the respective steps of the flip chip bonding method of the non-array bump according to an embodiment of the present invention.
第4圖：依據本發明之一具體實施例繪示在基板上表面形成支撐膠體之示意圖。Figure 4 is a schematic view showing the formation of a supporting colloid on the upper surface of a substrate according to an embodiment of the present invention.
第5圖：依據本發明之一具體實施例繪示從支撐膠體間之開口提供底部填充膠以填充底膠通道之基板後視示意圖。Fig. 5 is a schematic rear view showing a substrate for providing an underfill from an opening between supporting colloids to fill a primer passage according to an embodiment of the present invention.
第6圖：依據本發明之一具體實施例從支撐膠體間之開口提供底部填充膠以填充底膠通道之基板上表面示意圖。Figure 6 is a schematic illustration of the upper surface of a substrate from which an underfill is provided from an opening between the support colloids to fill the underfill channel in accordance with an embodiment of the present invention.
200．．．非陣列凸塊之覆晶接合構造200. . . Flip bonded structure of non-array bumps
210．．．基板210. . . Substrate
211．．．上表面211. . . Upper surface
212．．．接墊212. . . Pad
220．．．支撐膠體220. . . Support colloid
221．．．底膠通道221. . . Primer channel
222．．．擠料邊框222. . . Squeezing border
230．．．晶片230. . . Wafer
231．．．主動面231. . . Active surface
232．．．凸塊空白區232. . . Bump blank area
233．．．凸塊233. . . Bump
234．．．中央銲墊234. . . Central pad
240．．．底部填充膠240. . . Underfill
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99112414ATWI429041B (en) | 2010-04-20 | 2010-04-20 | Flip-chip bonding method and structure for non-array bumps |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99112414ATWI429041B (en) | 2010-04-20 | 2010-04-20 | Flip-chip bonding method and structure for non-array bumps |
| Publication Number | Publication Date |
|---|---|
| TW201138037A TW201138037A (en) | 2011-11-01 |
| TWI429041Btrue TWI429041B (en) | 2014-03-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW99112414ATWI429041B (en) | 2010-04-20 | 2010-04-20 | Flip-chip bonding method and structure for non-array bumps |
| Country | Link |
|---|---|
| TW (1) | TWI429041B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI688017B (en)* | 2019-03-15 | 2020-03-11 | 南茂科技股份有限公司 | Chip package structure and manufacturing method thereof |
| Publication number | Publication date |
|---|---|
| TW201138037A (en) | 2011-11-01 |
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