本發明有關於一種薄膜電晶體(thin film transistor,TFT)裝置，特別是有關於一種用於主動式陣列平面顯示器中具有遮光層的多閘極薄膜電晶體(multi-gate TFT)裝置。The present invention relates to a thin film transistor (TFT) device, and more particularly to a multi-gate TFT device having a light shielding layer for use in an active array flat panel display.
近年來，主動式陣列平面顯示器的需求快速的增加，例如主動式陣列液晶顯示器(active matrix liquid crystal display,AMLCD)顯示器。主動式陣列液晶顯示器通常利用薄膜電晶體作為畫素及驅動電路的開關元件，而其可依據主動層所使用的材料分為非晶矽(a-Si)及多晶矽薄膜電晶體。In recent years, the demand for active array flat panel displays has increased rapidly, such as active matrix liquid crystal display (AMLCD) displays. Active array liquid crystal displays generally use a thin film transistor as a switching element of a pixel and a driving circuit, and can be classified into an amorphous germanium (a-Si) and a polycrystalline germanium thin film transistor according to materials used in the active layer.
上述薄膜電晶體裝置包括閘極電極及具有通道區、源極及汲極區的主動層，用以將影像資訊回應至顯示裝置的畫素電極。然而，當畫素區的薄膜電晶體裝置處於關閉的狀態(OFF state)且若光(例如，背光源)照射到主動層(例如，圖案化的半導體層)時，主動層內會產生電子電洞對而形成光漏電流(photo leakage current)，使得影像品質降低。The thin film transistor device includes a gate electrode and an active layer having a channel region, a source region and a drain region for responding to image information to a pixel electrode of the display device. However, when the thin film transistor device of the pixel region is in an OFF state and if light (for example, a backlight) is irradiated onto the active layer (for example, a patterned semiconductor layer), electron electricity is generated in the active layer. The hole pairs form a photo leakage current, which degrades the image quality.
本發明一實施例提供一種影像顯示系統。此系統包括一多閘極薄膜電晶體裝置，其包括：一基底、一主動層、第一及第二閘極結構以及第一及第二遮光層。基底具有一畫素區。主動層設置於基底的畫素區上，包括第一及第二源極/汲極區、第一及第二通道區以及一通道連接區。第一通道區鄰接第一源極/汲極區的一第一輕摻雜區與通道連接區的一第三輕摻雜區，且第二通道區鄰接第二源極/汲極區的一第二輕摻雜區與通道連接區的一第四輕摻雜區。第一及第二閘極結構設置於主動層上且分別對應於第一及第二通道區，其中第一及第二閘極結構彼此電性連接。第一及第二遮光層設置於基底與主動層之間。第一遮光層對應於第一輕摻雜區且橫向延伸至至少一部分的第一通道區下方，而第二遮光層對應於第二輕摻雜區且橫向延伸至至少一部分的第二通道區下方。An embodiment of the invention provides an image display system. The system includes a multi-gate thin film transistor device including: a substrate, an active layer, first and second gate structures, and first and second light shielding layers. The substrate has a pixel area. The active layer is disposed on the pixel area of the substrate, and includes first and second source/drain regions, first and second channel regions, and a channel connection region. The first channel region is adjacent to a first lightly doped region of the first source/drain region and a third lightly doped region of the channel connection region, and the second channel region is adjacent to one of the second source/drain regions a fourth lightly doped region and a fourth lightly doped region of the channel connection region. The first and second gate structures are disposed on the active layer and respectively correspond to the first and second channel regions, wherein the first and second gate structures are electrically connected to each other. The first and second light shielding layers are disposed between the substrate and the active layer. The first light shielding layer corresponds to the first lightly doped region and extends laterally to at least a portion of the first channel region, and the second light shielding layer corresponds to the second lightly doped region and extends laterally to at least a portion of the second channel region .
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明所提供的實施例僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。The making and using of the embodiments of the present invention are described below. However, the present invention is to be understood as being limited to the details of the present invention.
以下說明本發明實施例之影像顯示系統。第1圖繪示出根據本發明一實施例之影像顯示系統，特別是一種具有多閘極薄膜電晶體(TFT)裝置200的影像顯示系統，其中多閘極薄膜電晶體裝置200可為N型或P型且包括具有一畫素區P的一基底100。基底100可由石英、玻璃、或其他透明材料所構成。一緩衝層104可選擇性地設置於基底100上，以作為基底100與後續所形成的主動層之間的黏著層或是污染阻障層。緩衝層104可為一單層或多層結構。舉例而言，緩衝層104可由一氧化矽、一氮化矽、或其組合所構成。The image display system of the embodiment of the present invention will be described below. 1 is a view showing an image display system according to an embodiment of the present invention, and more particularly, an image display system having a multi-gate thin film transistor (TFT) device 200, wherein the multi-gate thin film transistor device 200 can be an N-type. Or P-type and including a substrate 100 having a pixel area P. Substrate 100 can be constructed of quartz, glass, or other transparent materials. A buffer layer 104 can be selectively disposed on the substrate 100 to serve as an adhesion layer or a contamination barrier layer between the substrate 100 and the subsequently formed active layer. The buffer layer 104 can be a single layer or a multilayer structure. For example, the buffer layer 104 may be composed of tantalum oxide, tantalum nitride, or a combination thereof.
一主動層106設置於基底100的畫素區P上。主動層106可由非晶矽或多晶矽所構成。在本實施例中，主動層106包括：一第一源極/汲極區107a、一第二源極/汲極區107b、一第一通道區106c、一第二通道區106g以及連接第一及第二通道區106c及106g的一通道連接區107c。在一實施例中，第一源極/汲極區107a係作為多閘極薄膜電晶體裝置200的源極而第二源極/汲極區107b則作為多閘極薄膜電晶體裝置200的汲極。在另一實施例中，第一源極/汲極區107a可作為多閘極薄膜電晶體裝置200的汲極而第二源極/汲極區107b則作為多閘極薄膜電晶體裝置200的源極。在本實施例中，第一源極/汲極區107a包括一第一重摻雜區106a及一第一輕摻雜區106b，而第二源極/汲極區107b包括一第二重摻雜區106i及一第二輕摻雜區106h。再者，通道連接區107c包括一第三重摻雜區106e、一第三輕摻雜區106d及一第四輕摻雜區106f。第一通道區106c鄰接第一輕摻雜區106b與第三輕摻雜區106d，且第二通道區106g鄰接第二輕摻雜區106h與第四輕摻雜區106f。An active layer 106 is disposed on the pixel area P of the substrate 100. The active layer 106 may be composed of amorphous germanium or polycrystalline germanium. In this embodiment, the active layer 106 includes a first source/drain region 107a, a second source/drain region 107b, a first channel region 106c, a second channel region 106g, and a first connection. And a channel connection region 107c of the second channel regions 106c and 106g. In one embodiment, the first source/drain region 107a serves as the source of the multi-gate thin film transistor device 200 and the second source/drain region 107b serves as the gate of the multi-gate thin film transistor device 200. pole. In another embodiment, the first source/drain region 107a can serve as the drain of the multi-gate thin film transistor device 200 and the second source/drain region 107b can serve as the multi-gate thin film transistor device 200. Source. In this embodiment, the first source/drain region 107a includes a first heavily doped region 106a and a first lightly doped region 106b, and the second source/drain region 107b includes a second heavily doped region. The impurity region 106i and a second lightly doped region 106h. Moreover, the channel connection region 107c includes a third heavily doped region 106e, a third lightly doped region 106d, and a fourth lightly doped region 106f. The first channel region 106c is adjacent to the first lightly doped region 106b and the third lightly doped region 106d, and the second channel region 106g is adjacent to the second lightly doped region 106h and the fourth lightly doped region 106f.
一第一閘極結構及一第二閘極結構設置於主動層106上且分別對應於第一及第二通道區106c及106g，其中第一及第二閘極結構彼此電性連接。第一閘極結構包括至少一閘極介電層及一閘極層114所構成的疊層。在一實施例中，閘極介電層可包括由氧化矽所構成的絕緣層108及位於其上方且由氮化矽所構成的絕緣層110。同樣地，第二閘極結構包括至少一閘極介電層(例如，絕緣層108及位於其上方且由氮化矽所構成的絕緣層112)及一閘極層116所構成的疊層。A first gate structure and a second gate structure are disposed on the active layer 106 and correspond to the first and second channel regions 106c and 106g, respectively, wherein the first and second gate structures are electrically connected to each other. The first gate structure includes a stack of at least one gate dielectric layer and a gate layer 114. In an embodiment, the gate dielectric layer may include an insulating layer 108 composed of hafnium oxide and an insulating layer 110 formed thereon and composed of tantalum nitride. Similarly, the second gate structure includes a stack of at least one gate dielectric layer (eg, insulating layer 108 and insulating layer 112 formed thereon and formed of tantalum nitride) and a gate layer 116.
在本實施例中，為了防止或降低因基底100下方背光源(未繪示)照射主動層106而引發的光漏電流，一遮光層102，設置在基底100與主動層106下方的緩衝層104之間，以遮蓋整個主動層106而避免光照射到主動層106。遮光層102可由金屬、半導體材料(例如，矽)或其他吸光材料所構成。In this embodiment, in order to prevent or reduce the light leakage current caused by the backlight (not shown) under the substrate 100, the light shielding layer 102, the buffer layer 104 disposed under the substrate 100 and the active layer 106 Between, to cover the entire active layer 106 to avoid light from illuminating the active layer 106. The light shielding layer 102 may be composed of a metal, a semiconductor material (eg, germanium) or other light absorbing material.
需注意的是上述實施例中具有二個閘極及二個通道區多閘極薄膜電晶體裝置200僅為範例說明，然而實際的閘極與通道區的數量可取於設計需求，並不以此為限。It should be noted that the multi-gate thin film transistor device 200 having two gates and two channel regions in the above embodiment is merely an example, but the actual number of gate and channel regions may be determined by design requirements. Limited.
接下來，請參照第2至7圖，其繪示出根據本發明其他不同實施例之具有多閘極薄膜電晶體裝置的影像顯示系統，其中相同於第1圖的部件係使用相同的標號並省略其說明。請參照第2圖中，不同於第1圖所示的實施例，多閘極薄膜電晶體裝置200具有分隔的第一遮光層102a及第二遮光層102b，其設置於基底100與主動層106之間。特別的是第一遮光層102a對應於第一輕摻雜區106b且橫向延伸至至少一部分的第一通道區106c下方，而第二遮光層102b對應於該第二輕摻雜區106h且橫向延伸至至少一部分的該第二通道區106g下方。第一及第二遮光層102a及102b可相同或相似於遮光層102(繪示於第1圖)。在本實施例中，第一及第二遮光層102a及102b完全遮蓋第一及第二輕摻雜區106b及106h及局部遮蓋第一及第二通道區106c及106g而露出通道連接區107c。由於位於第一源極/汲極區107a的第一輕摻雜區106b與第二源極/汲極區107b的第二輕摻雜區106h處容易引發較嚴重的光漏電流，因此本實施例中第一及第二遮光層102a及102b的排置可有效降低主動層106中的光漏電流。在其他實施例中，第一及第二遮光層102a及102b可進一步延伸，以完全遮蓋第一及第二通道區106c及106g。Next, please refer to FIGS. 2-7, which illustrate an image display system having a multi-gate thin film transistor device according to other different embodiments of the present invention, wherein components identical to those of FIG. 1 are labeled with the same reference numerals. The description is omitted. Referring to FIG. 2 , unlike the embodiment shown in FIG. 1 , the multi-gate thin film transistor device 200 has a first first light shielding layer 102 a and a second light shielding layer 102 b disposed on the substrate 100 and the active layer 106 . between. In particular, the first light shielding layer 102a corresponds to the first lightly doped region 106b and extends laterally to at least a portion of the first channel region 106c, and the second light shielding layer 102b corresponds to the second lightly doped region 106h and extends laterally. Up to at least a portion of the second channel region 106g. The first and second light shielding layers 102a and 102b may be the same or similar to the light shielding layer 102 (shown in FIG. 1). In this embodiment, the first and second light shielding layers 102a and 102b completely cover the first and second lightly doped regions 106b and 106h and partially cover the first and second channel regions 106c and 106g to expose the channel connection region 107c. Since the first lightly doped region 106b located in the first source/drain region 107a and the second lightly doped region 106h of the second source/drain region 107b are likely to cause a more serious light leakage current, the present implementation The arrangement of the first and second light shielding layers 102a and 102b in the example can effectively reduce the light leakage current in the active layer 106. In other embodiments, the first and second light shielding layers 102a and 102b can be further extended to completely cover the first and second channel regions 106c and 106g.
請參照第8圖，其繪示出汲極電流(Id)與閘極電壓(Vg)轉移特性曲線圖，其中曲線A及B為第1圖中多閘極薄膜電晶體裝置200分別在汲-源電壓(Vds)為0.1V及10V的轉移特性曲線，而曲線C及D為第2圖中多閘極薄膜電晶體裝置200分別在汲-源電壓為0.1V及10V的轉移特性曲線。由於遮光層102與主動層106(繪示於第1圖)之間的耦合效應(coupling effect)，使得起始電壓(Vth)在相對低汲-源電壓(Vds)與相對高汲-源電壓操作下產生偏移(如曲線A及B所示)。而分隔的第一及第二遮光層102a及102b降低了耦合效應，使得起始電壓在相對低汲-源電壓與相對高汲-源電壓操作下幾乎一樣(如曲線C及D所示)。Please refer to FIG. 8 , which shows a graph of the drain current (Id ) and the gate voltage (Vg ) transfer characteristic, wherein the curves A and B are the multi-gate thin film transistor device 200 in FIG. 1 respectively. The 汲-source voltage (Vds ) is a transfer characteristic curve of 0.1 V and 10 V, and the curves C and D are the transfer characteristics of the multi-gate thin film transistor device 200 of FIG. 2 at a 汲-source voltage of 0.1 V and 10 V, respectively. curve. Due to the coupling effect between the light shielding layer 102 and the active layer 106 (shown in FIG. 1), the starting voltage (Vth ) is relatively low 汲-source voltage (Vds ) and relatively high 汲- The source voltage operates with an offset (as shown by curves A and B). The separate first and second light-shielding layers 102a and 102b reduce the coupling effect such that the initial voltage is nearly the same under relatively low 汲-source voltage and relatively high 汲-source voltage operation (as shown by curves C and D).
請參照第3圖，不同於第2圖所示的實施例之處在於第二遮光層102b經由第二通道區106g下方橫向延伸至第四輕摻雜區106f下方，以完全遮蓋第二通道區106g及第四輕摻雜區106f。在另一實施例中，第一遮光層102a也經由第一通道區106c下方橫向延伸至第三輕摻雜區106d下方，以完全遮蓋第一通道區106c及第三輕摻雜區106d，如第4圖所示。Referring to FIG. 3, the embodiment shown in FIG. 2 is different in that the second light shielding layer 102b extends laterally below the second light-doped region 106f via the second channel region 106g to completely cover the second channel region. 106g and a fourth lightly doped region 106f. In another embodiment, the first light shielding layer 102a also extends laterally below the first light-doped region 106d via the first channel region 106c to completely cover the first channel region 106c and the third lightly doped region 106d, such as Figure 4 shows.
請參照第5圖，不同於第2圖所示的實施例之處在於多閘極薄膜電晶體裝置200更包括一分隔的第三遮光層102c，其位於第一與第二遮光層102a及102b之間、對應於第三輕摻雜區106d以及橫向延伸至至少一部分的第一通道區106c下方，以完全遮蓋第三輕摻雜區106d及局部遮蓋第一通道區106c。第三遮光層102c可相同或相似於第一與第二遮光層102a及102b。在另一實施例中，第三遮光層102c可對應於第四輕摻雜區106f以及橫向延伸至至少一部分的第二通道區106g下方，以完全遮蓋第四輕摻雜區106f及局部遮蓋第二通道區106g。又另一實施例中，第二遮光層102b經由第二通道區106g下方橫向延伸至第四輕摻雜區106f下方，以完全遮蓋第二通道區106g及第四輕摻雜區106f，如第6圖所示。Referring to FIG. 5, the embodiment shown in FIG. 2 is different in that the multi-gate thin film transistor device 200 further includes a separated third light shielding layer 102c located at the first and second light shielding layers 102a and 102b. Between, corresponding to the third lightly doped region 106d and laterally extending to at least a portion of the first channel region 106c to completely cover the third lightly doped region 106d and partially cover the first channel region 106c. The third light shielding layer 102c may be the same or similar to the first and second light shielding layers 102a and 102b. In another embodiment, the third light shielding layer 102c may correspond to the fourth lightly doped region 106f and laterally extend to at least a portion of the second channel region 106g to completely cover the fourth lightly doped region 106f and partially cover the surface. Two channel area 106g. In another embodiment, the second light shielding layer 102b extends laterally below the second light-doped region 106f via the second channel region 106g to completely cover the second channel region 106g and the fourth lightly doped region 106f. Figure 6 shows.
請參照第7圖，不同於第5圖所示的實施例之處在於多閘極薄膜電晶體裝置200更包括一分隔的第四遮光層102d，其位於第一與第二遮光層102a及102b之間、對應於第四輕摻雜區106f以及橫向延伸至至少一部分的第二通道區106g下方，以完全遮蓋第四輕摻雜區106f及局部遮蓋第二通道區106g。第四遮光層102d可相同或相似於第三遮光層102c。Referring to FIG. 7, the embodiment shown in FIG. 5 is different in that the multi-gate thin film transistor device 200 further includes a separated fourth light shielding layer 102d located at the first and second light shielding layers 102a and 102b. Between, corresponding to the fourth lightly doped region 106f and laterally extending to at least a portion of the second channel region 106g to completely cover the fourth lightly doped region 106f and partially cover the second channel region 106g. The fourth light shielding layer 102d may be the same or similar to the third light shielding layer 102c.
可以理解的是第3至7圖的實施例中，分隔的遮光層可降低了耦合效應，使得起始電壓在相對低汲-源電壓與相對高汲-源電壓操作下幾乎一樣。It will be appreciated that in the embodiments of Figures 3 through 7, the separate light shielding layers may reduce the coupling effect such that the starting voltage is nearly the same at relatively low 汲-source voltages and relatively high 汲-source voltage operation.
根據上述實施例，由於在主動層中源極區與汲極區的輕摻雜區下方對應設置了分隔的遮光層，因此可有效降低主動層內的光漏電流。再者，相較於完全遮蓋主動層的多閘極薄膜電晶體裝置，具有分隔的遮光層的多閘極薄膜電晶體裝置可降低遮光層與主動層之間的耦合效應，進而避免起始電壓在相對低汲-源電壓與相對高汲-源電壓操作下產生不必要的偏移而導致顯示裝置的顯示異常。According to the above embodiment, since the separated light shielding layer is disposed under the source region and the lightly doped region of the drain region in the active layer, the light leakage current in the active layer can be effectively reduced. Furthermore, the multi-gate thin film transistor device with the separated light shielding layer can reduce the coupling effect between the light shielding layer and the active layer, thereby avoiding the initial voltage, compared to the multi-gate thin film transistor device that completely covers the active layer. An unnecessary offset is generated under relatively low 汲-source voltage and relatively high 汲-source voltage operation, resulting in display abnormality of the display device.
第9圖係繪示出根據本發明另一實施例之具有影像顯示系統方塊示意圖，其可實施於一平面顯示(flat panel display,FPD)裝置300或電子裝置500，例如一筆記型電腦、一手機、一數位相機、一個人數位助理(personal digital assistant,PDA)、一桌上型電腦、一電視機、一車用顯示器、或一攜帶型DVD播放器。平面顯示裝置300可具有之前所述的多閘極薄膜電晶體裝置200，而平面顯示裝置300可為液晶顯示面板。如第9圖所示，平面顯示裝置300包括一多閘極薄膜電晶體裝置，如第1至7圖中的薄膜電晶體裝置200所示。在其他實施例中，電子裝置500可具有平面顯示裝置300。如第9圖所示，電子裝置500包括：一平面顯示裝置300及一輸入單元400。再者，輸入單元400係耦接至平面顯示器裝置300，用以提供輸入信號(例如，影像信號)至平面顯示裝置300以產生影像。FIG. 9 is a block diagram showing an image display system according to another embodiment of the present invention, which can be implemented in a flat panel display (FPD) device 300 or an electronic device 500, such as a notebook computer, A mobile phone, a digital camera, a personal digital assistant (PDA), a desktop computer, a television, a car display, or a portable DVD player. The flat display device 300 may have the multi-gate thin film transistor device 200 described above, and the flat display device 300 may be a liquid crystal display panel. As shown in Fig. 9, the flat display device 300 includes a multi-gate thin film transistor device as shown in the thin film transistor device 200 of Figs. In other embodiments, the electronic device 500 can have a flat display device 300. As shown in FIG. 9, the electronic device 500 includes a flat display device 300 and an input unit 400. Furthermore, the input unit 400 is coupled to the flat panel display device 300 for providing an input signal (eg, an image signal) to the flat display device 300 to generate an image.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．基底100. . . Base
102．．．遮光層102. . . Shading layer
102a．．．第一遮光層102a. . . First light shielding layer
102b．．．第二遮光層102b. . . Second light shielding layer
102c．．．第三遮光層102c. . . Third light shielding layer
102d．．．第四遮光層102d. . . Fourth light shielding layer
104．．．緩衝層104. . . The buffer layer
106．．．主動層106. . . Active layer
106a．．．第一重摻雜區106a. . . First heavily doped region
106b．．．第一輕摻雜雜區106b. . . First lightly doped region
106c．．．第一通道區106c. . . First passage area
106d．．．第三輕摻雜區106d. . . Third lightly doped region
106e．．．第三重摻雜區106e. . . Third heavily doped region
106f．．．第四輕摻雜區106f. . . Fourth lightly doped region
106g．．．第二通道區106g. . . Second passage zone
106h．．．第二輕摻雜區106h. . . Second lightly doped region
106i．．．第二重摻雜區106i. . . Second heavily doped region
107a．．．第一源極/汲極區107a. . . First source/drain region
107b．．．第二源極/汲極區107b. . . Second source/drain region
107c．．．通道連接區107c. . . Channel connection area
108、110、112．．．絕緣層108, 110, 112. . . Insulation
114、116．．．閘極層114, 116. . . Gate layer
200．．．多閘極薄膜電晶體裝置200. . . Multi-gate thin film transistor device
300．．．平面顯示裝置300. . . Flat display device
400．．．輸入單元400. . . Input unit
500．．．電子裝置500. . . Electronic device
P．．．畫素區P. . . Graphic area
第1至7圖係繪示出根據本發明各個實施例之具有多閘極薄膜電晶體裝置之影像顯示系統剖面示意圖；1 to 7 are schematic cross-sectional views showing an image display system having a multi-gate thin film transistor device according to various embodiments of the present invention;
第8圖係繪示出汲極電流與閘極電壓轉移特性曲線圖；Figure 8 is a graph showing the drain current and gate voltage transfer characteristics;
第9圖係繪示出根據本發明另一實施例之具有影像顯示系統方塊示意圖。Figure 9 is a block diagram showing an image display system in accordance with another embodiment of the present invention.
100．．．基底100. . . Base
102a．．．第一遮光層102a. . . First light shielding layer
102b．．．第二遮光層102b. . . Second light shielding layer
102c．．．第三遮光層102c. . . Third light shielding layer
102d．．．第四遮光層102d. . . Fourth light shielding layer
104．．．緩衝層104. . . The buffer layer
106．．．主動層106. . . Active layer
106a．．．第一重摻雜區106a. . . First heavily doped region
106b．．．第一輕摻雜雜區106b. . . First lightly doped region
106c．．．第一通道區106c. . . First passage area
106d．．．第三輕摻雜區106d. . . Third lightly doped region
106e．．．第三重摻雜區106e. . . Third heavily doped region
106f．．．第四輕摻雜區106f. . . Fourth lightly doped region
106g．．．第二通道區106g. . . Second passage zone
106h．．．第二輕摻雜區106h. . . Second lightly doped region
106i．．．第二重摻雜區106i. . . Second heavily doped region
107a．．．第一源極/汲極區107a. . . First source/drain region
107b．．．第二源極/汲極區107b. . . Second source/drain region
107c．．．通道連接區107c. . . Channel connection area
108、110、112．．．絕緣層108, 110, 112. . . Insulation
114、116．．．閘極層114, 116. . . Gate layer
200．．．多閘極薄膜電晶體裝置200. . . Multi-gate thin film transistor device
P．．．畫素區P. . . Graphic area
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