本發明是有關於一種積體電路封裝元件，特別是有關於一種具側邊接腳之積體電路封裝元件。The present invention relates to an integrated circuit package component, and more particularly to an integrated circuit package component having a side pin.
目前大多數的積體電路封裝元件(integrated circuit package component)被焊接於印刷電路板(printed circuit board)上，藉由許多接腳(pins)來實現此積體電路封裝元件與印刷電路板之間的電氣連接與機械(物理)連接。由於積體電路封裝元件與印刷電路板彈性模量和熱膨脹係數的差異，導致兩者於機械應力(例如安裝或搬運)或熱應力(例如焊接高溫)下所產生之彎曲程度不同，因此，介於積體電路封裝元件與印刷電路板之間的這些接腳可能因此而導致斷裂。At present, most integrated circuit package components are soldered on a printed circuit board, and a plurality of pins are used to realize the between the integrated circuit package components and the printed circuit board. Electrical connection to mechanical (physical) connection. Due to the difference in the modulus of elasticity and the coefficient of thermal expansion of the integrated circuit package component and the printed circuit board, the degree of bending of the two is different under mechanical stress (such as mounting or handling) or thermal stress (such as high temperature of welding). These pins between the integrated circuit package component and the printed circuit board may thus cause breakage.
舉例而言，傳統矩形扁平封裝(Quad Flat Package，QFP)技術下之積體電路封裝元件的寬度大致相同。如此，當此積體電路封裝元件焊接至印刷電路板，並承受到一定程度之應力時，此積體電路封裝元件之部份接腳將因無法承受應力而產生變形甚至斷裂，導致無法繼續實現積體電路封裝元件與印刷電路板之間的電氣連接與機械連接。如此，積體電路封裝元件便無法與印刷電路板進行訊號之傳遞，進而使得印製電路板元件因此失效。For example, the width of the integrated circuit package components under the conventional Quad Flat Package (QFP) technology is substantially the same. In this way, when the integrated circuit package component is soldered to the printed circuit board and subjected to a certain degree of stress, some of the pins of the integrated circuit package component may be deformed or even broken due to the inability to withstand the stress, thereby failing to continue. Electrical and mechanical connection between the integrated circuit package component and the printed circuit board. In this way, the integrated circuit package component cannot transmit signals to the printed circuit board, thereby causing the printed circuit board component to fail.
有鑑於此，如何研發出一種積體電路封裝元件，可有效改善上述所帶來的缺失及不便，實乃相關業者目前刻不容緩之一重要課題。In view of this, how to develop an integrated circuit package component can effectively improve the above-mentioned lack and inconvenience, which is an important issue that the relevant industry is currently unable to delay.
本發明揭露一種具側邊接腳之積體電路封裝元件，用以加強積體電路封裝元件之側邊接腳之抗應力能力，降低受到應力之彎曲而出現斷裂之機會。The invention discloses an integrated circuit package component with side pins for reinforcing the stress resistance of the side pins of the integrated circuit package component and reducing the chance of cracking due to stress bending.
此種具側邊接腳之積體電路封裝元件，用以安置於一電路板上，其包括一封裝本體、一中央接腳、一首位接腳及一末位接腳。封裝本體具有一側面。中央接腳排列於側面，具有用以焊接至電路板上之焊接區，首位接腳排列於側面，具有用以焊接至電路板上之焊接區，末位接腳排列於側面，具有用以焊接至電路板上之焊接區；中央接腳位於首位接腳以及末位接腳之間。中央接腳之焊接區具有第一面積，首位接腳之焊接區具有第二面積，末位接腳之焊接區具有第三面積，第一面積小於第二面積及第三面積。The integrated circuit package component with a side pin is disposed on a circuit board, and includes a package body, a center pin, a first pin and a last pin. The package body has a side. The central pins are arranged on the side surface and have soldering regions for soldering to the circuit board. The first pins are arranged on the side surfaces, and have soldering regions for soldering to the circuit board. The last pins are arranged on the side surfaces for soldering. To the soldering area on the board; the center pin is between the first pin and the last pin. The welding zone of the center pin has a first area, the welding zone of the first pin has a second area, and the welding zone of the last pin has a third area, the first area being smaller than the second area and the third area.
本發明之一實施例中，此些接腳之焊接區之面積依據從此些接腳中央位置之至少一接腳分別朝此些接腳最首位之接腳之方向，以及朝此些接腳最末位之接腳之方向依序遞增。In one embodiment of the present invention, the area of the pads of the pins is based on at least one of the pins from the center of the pins, respectively toward the first pin of the pins, and the most of the pins The direction of the last pin is sequentially incremented.
本發明之另一態樣，為一種具側邊接腳之積體電路封裝元件，用以安置於一電路板上。此積體電路封裝元件包括一封裝本體、一第一接腳群、一第二接腳群及一第三接腳群。封裝本體具有一側面。此側面包括一第一區、一第二區及一第三區。第一區位於第二區及第三區之間。第一接腳群包括多個第一接腳，此些第一接腳分別排列於第一區。此些第一接腳分別具一第一焊接區，且此些第一焊接區具有相同之面積。第二接腳群包括多個第二接腳，此些第二接腳分別排列於第二區。此些第二接腳分別具一第二焊接區，且此些第二焊接區彼此具有相同之面積。第三接腳群包括多個第三接腳，此些第三接腳分別排列於第三區。此些第三接腳分別具一第三焊接區，此些第三焊接區彼此具有相同之面積。其中任一第一焊接區的面積小於任一第二焊接區的面積及任一第三焊接區的面積。Another aspect of the present invention is an integrated circuit package component having side pins for placement on a circuit board. The integrated circuit package component includes a package body, a first pin group, a second pin group and a third pin group. The package body has a side. The side includes a first zone, a second zone and a third zone. The first zone is located between the second zone and the third zone. The first pin group includes a plurality of first pins, and the first pins are respectively arranged in the first region. The first pins each have a first bonding zone, and the first bonding zones have the same area. The second pin group includes a plurality of second pins, and the second pins are respectively arranged in the second region. The second pins each have a second land, and the second pads have the same area. The third pin group includes a plurality of third pins, and the third pins are respectively arranged in the third region. The third pins each have a third weld zone, and the third weld zones have the same area as each other. The area of any of the first weld zones is less than the area of any of the second weld zones and the area of any of the third weld zones.
如此，本發明藉由調整積體電路封裝元件各側邊接腳的焊接面積，使得積體電路封裝元件各側邊接腳接近角落之接腳具有較大之焊接面積，以便積體電路封裝元件之側邊接腳於焊接至印刷電路板後，可提升抗應力能力。In this way, the present invention adjusts the soldering area of each side pin of the integrated circuit package component, so that the pins of the side of the integrated circuit package component near the corner have a large soldering area, so as to integrate the circuit package component. The side pins are soldered to the printed circuit board to improve stress resistance.
以下將以圖示及詳細說明清楚說明本發明之精神，如熟悉此技術之人員在瞭解本發明之實施例後，當可由本發明所教示之技術，加以改變及修飾，其並不脫離本發明之精神與範圍。The present invention will be apparent from the following description and the detailed description of the embodiments of the present invention, which may be modified and modified by the teachings of the present invention without departing from the invention. The spirit and scope.
第1圖為積體電路封裝元件受到應力時之等應力線分佈圖。本發明發現積體電路封裝元件100焊接至印刷電路板後，在受到機械應力或熱應力時所呈現之等應力線p係以一幾何中心點c為圓心，朝積體電路封裝元件100邊緣之方向呈同心圓分佈，意即，積體電路封裝元件100越遠離其幾何中心點c之位置所承受應力越大。換句話說，當積體電路封裝元件100呈矩形時，其邊緣之角落r所承受的應力最大。Fig. 1 is a diagram showing the distribution of stress lines when an integrated circuit package component is subjected to stress. The present invention finds that after the integrated circuit package component 100 is soldered to the printed circuit board, the stress line p which is present when subjected to mechanical stress or thermal stress is centered on a geometric center point c, toward the edge of the integrated circuit package component 100. Concentrically distributed, that is, the greater the stress experienced by the integrated circuit package component 100 from the position of its geometric center point c. In other words, when the integrated circuit package component 100 has a rectangular shape, the stress at the corner r of the edge is the greatest.
有鑑於此，本發明揭露一種具側邊接腳之積體電路封裝元件，藉由調整積體電路封裝元件各側邊接腳的焊接面積，使得積體電路封裝元件各側邊接腳接近角落之接腳具有較大之焊接面積，以便積體電路封裝元件之側邊接腳於焊接至印刷電路板後，可提升抗應力能力。In view of the above, the present invention discloses an integrated circuit package component having side pins. By adjusting the soldering area of each side pin of the integrated circuit package component, the side pins of the integrated circuit package component are close to the corners. The pins have a large soldering area so that the side pins of the integrated circuit package components can be soldered to the printed circuit board to improve the stress resistance.
第2A圖繪示本發明具側邊接腳之積體電路封裝元件之一實施例下一四方形扁平封裝元件(quad flat package，QFP)之立體示意圖。第2B圖繪示第2A圖之一側視圖。FIG. 2A is a perspective view showing a quad flat package (QFP) according to an embodiment of the integrated circuit package component of the present invention. Figure 2B shows a side view of Figure 2A.
此積體電路封裝元件100包括一封裝本體200及多個接腳300。封裝本體200具有一安置面210及鄰接於安置面210周邊之多個側面220。此些接腳300分別線性地排列於至少一側面220。具體而言，此些接腳300之一端分別埋藏於此側面220中，另端分別自此側面220伸出，可朝外延伸(如第2B圖)或彎折至安置面210，其另端皆具有一焊接區301。The integrated circuit package component 100 includes a package body 200 and a plurality of pins 300. The package body 200 has a mounting surface 210 and a plurality of side surfaces 220 adjacent to the periphery of the mounting surface 210. The pins 300 are linearly arranged on at least one side 220, respectively. Specifically, one ends of the pins 300 are respectively buried in the side surface 220, and the other ends respectively protrude from the side surface 220, and may extend outward (as shown in FIG. 2B) or bend to the mounting surface 210, and the other end thereof Each has a weld zone 301.
當此積體電路封裝元件100安置於此電路板(圖中未示)時，封裝本體200之安置面210面對電路板，各接腳300之焊接區301接觸並焊接至此電路板上。When the integrated circuit package component 100 is disposed on the circuit board (not shown), the mounting surface 210 of the package body 200 faces the circuit board, and the solder pads 301 of the pins 300 are contacted and soldered to the circuit board.
第3圖繪示第2A圖之一仰視圖。本發明之一實施例中，此些接腳300之排列順序中具有一中央接腳311(例如具中位數角色之接腳)，一首位接腳312(即最外側之接腳)及一末位接腳313(即相對首位接腳312之最外側之接腳)，中央接腳311位於首位接腳312及末位接腳313之間。中央接腳311的焊接區301具有一第一面積；首位接腳312的焊接區301具有一第二面積；末位接腳313的焊接區301具有一第三面積。其中第二面積及第三面積皆大於第一面積，故積體電路封裝元件100接近角落之接腳312、313具有較大之焊接面積，使得積體電路封裝元件100具有更高之抗應力能力。Figure 3 is a bottom view of Figure 2A. In an embodiment of the present invention, the pins 300 have a central pin 311 (for example, a pin with a median character), a first pin 312 (ie, an outermost pin), and a first pin. The last pin 313 (ie, the outermost pin of the first pin 312) is located between the first pin 312 and the last pin 313. The land 301 of the center pin 311 has a first area; the land 301 of the first pin 312 has a second area; and the land 301 of the last pin 313 has a third area. The second area and the third area are both larger than the first area, so that the pins 312 and 313 of the integrated circuit package component 100 near the corner have a larger soldering area, so that the integrated circuit package component 100 has higher stress resistance. .
此實施例更進一步揭露此些接腳300對於其焊接區301面積之變化，可依據從此些接腳300中央之一接腳311分別朝二對應最外側之接腳312、313之方向，依序遞增其焊接區301之面積。This embodiment further discloses that the change of the area of the pads 300 for the pads 301 can be in accordance with the direction of one of the pins 311 from the center of the pins 300 toward the two outermost pins 312, 313, respectively. The area of its weld zone 301 is incremented.
當接腳300之數量為奇數時，此些接腳300中僅有一個中央接腳311。舉例而言，此積體電路封裝元件100之一側面220伸出11隻接腳時，依序命名為接腳一、接腳二、接腳三、...、接腳六，以此類推至接腳十一，接腳六即為此些接腳300之中央接腳311；接腳一及接腳十一分別即為此些接腳300之首位接腳312及末位接腳313。When the number of pins 300 is an odd number, there is only one center pin 311 among the pins 300. For example, when one side of the integrated circuit package component 100 protrudes from 11 pins, it is named as pin one, pin two, pin three, ..., pin six, and so on. To the pin eleven, the pin 6 is the center pin 311 of the pin 300; the pin one and the pin eleven are the first pin 312 and the last pin 313 of the pin 300 respectively.
如圖所示，此些接腳300對於其焊接區301面積之變化，可依據從接腳六至接腳十一之方向D1，以及從接腳六至接腳一之方向D2依序遞增其焊接區301之面積。As shown, the change of the area of the pads 300 for the pads 301 can be sequentially increased according to the direction D1 from the pin 6 to the pin eleven and the direction D2 from the pin 6 to the pin one. The area of the weld zone 301.
具體而言，中央接腳311之焊接區301之第一面積之寬度h舉例而言為0.22～0.32公釐(mm)(即為0.22,0.23,0.24,0.25,0.26,0.27,0.28,0.29,0.30,0.31及0.32其中之一)。首位接腳312之焊接區301之第二面積之寬度h舉例而言為0.28～0.38公釐(mm)(即為0.28,0.29,0.30,0.31,0.32,0.33,0.34,0.35,0.36,0.37,0.38其中之一)。末位接腳313之焊接區301之第三面積之寬度h舉例而言為0.28～0.38公釐(mm)(即為0.28,0.29,0.30,0.31,0.32,0.33,0.34,0.35,0.36,0.37,0.38其中之一)。此外，本實施例中當接腳300之數量為偶數時，差別僅在於此些接腳300中具有二個中央接腳311，此些接腳300中央之二接腳311仍分別朝二對應最外側之接腳312、313之方向，依序遞增其焊接區301之面積。以下將以接腳300之數量為偶數時之一實施例為說明。Specifically, the width h of the first area of the land 301 of the center pin 311 is, for example, 0.22 to 0.32 mm (ie, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, One of 0.30, 0.31 and 0.32). The width h of the second area of the land 301 of the first pin 312 is, for example, 0.28 to 0.38 mm (i.e., 0.28, 0.29, 0.30, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, One of 0.38). The width h of the third area of the land 301 of the last pin 313 is, for example, 0.28 to 0.38 mm (that is, 0.28, 0.29, 0.30, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37). , one of 0.38). In addition, in the embodiment, when the number of the pins 300 is an even number, the difference is that only the two pins 311 are present in the pins 300, and the two pins 311 in the center of the pins 300 are still facing the two respectively. The direction of the outer pins 312, 313 sequentially increases the area of the land 301. Hereinafter, an embodiment in which the number of pins 300 is an even number will be described.
第4圖繪示本發明具側邊接腳之積體電路封裝元件之一實施例下一四方形扁平無引腳封裝元件(quad flat non-leaded package，QFN)之仰視圖。4 is a bottom view of a quad flat non-leaded package (QFN) according to an embodiment of the integrated circuit package component of the present invention.
當接腳300之數量為偶數時，則有二個中央接腳311。舉例而言，此積體電路封裝元件100之一側面220具有10隻接腳時，依序命名為接腳一、接腳二、接腳三、...、接腳七以此類推至接腳十，接腳五及接腳六即為此些接腳300中之中央接腳311；接腳一及接腳十分別為此些接腳300之首位接腳312及末位接腳313。When the number of pins 300 is an even number, there are two center pins 311. For example, when one side 220 of the integrated circuit package component 100 has 10 pins, it is named as pin 1, pin 2, pin 3, ..., pin 7 and so on. The tenth pin, the pin five and the pin six are the center pin 311 of the pin 300; the pin one and the pin ten are the first pin 312 and the last pin 313 of the pin 300 respectively.
如圖所示，此些接腳300對於其焊接區301面積之變化，可依據從接腳六至接腳十之方向D1依序遞增其焊接區301之面積，以及從接腳五至接腳一之方向D2依序遞增其焊接區301之面積。As shown, the change in the area of the pads 300 for the pads 301 can be sequentially increased in accordance with the direction D1 from the pin 6 to the pin 10, and the area of the pads 301, and from the pins 5 to the pins. One direction D2 sequentially increments the area of its land 301.
具體而言，中央接腳311之焊接區301之第一面積之寬度h舉例而言為0.22～0.32公釐(mm)(即為0.22,0.23,0.24,0.25,0.26,0.27,0.28,0.29,0.30,0.31及0.32其中之一)。首位接腳312之焊接區301之第二面積之寬度h舉例而言為0.28～0.38公釐(mm)(即為0.28,0.29,0.30,0.31,0.32,0.33,0.34,0.35,0.36,0.37,0.38其中之一)。末位接腳313之焊接區301之第三面積之寬度h舉例而言為0.28～0.38公釐(mm)(即為0.28,0.29,0.30,0.31,0.32,0.33,0.34,0.35,0.36,0.37,0.38其中之一)。Specifically, the width h of the first area of the land 301 of the center pin 311 is, for example, 0.22 to 0.32 mm (ie, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, One of 0.30, 0.31 and 0.32). The width h of the second area of the land 301 of the first pin 312 is, for example, 0.28 to 0.38 mm (i.e., 0.28, 0.29, 0.30, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, One of 0.38). The width h of the third area of the land 301 of the last pin 313 is, for example, 0.28 to 0.38 mm (that is, 0.28, 0.29, 0.30, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37). , one of 0.38).
此些接腳300通常呈針腳狀、片狀或塊狀,由於此些接腳之長度及厚度皆一致，因此其寬度h之不同便決定了焊接區301面積之不同。The pins 300 are generally in the form of pins, sheets or blocks. Since the lengths and thicknesses of the pins are the same, the difference in the width h determines the difference in the area of the pads 301.
然而，首位接腳312之焊接區301之第二面積與末位接腳313之焊接區301之第三面積不限於相同或不同，只要大於中央接腳311之焊接區301之第一面積即可提供積體電路封裝元件100更高之抗應力能力。However, the second area of the land 301 of the first pin 312 and the third area of the land 301 of the last pin 313 are not limited to the same or different, as long as it is larger than the first area of the land 301 of the center pin 311. The integrated circuit package component 100 is provided with a higher resistance to stress.
第5圖繪示本發明具側邊接腳之積體電路封裝元件之一實施例下一小外型封裝元件(small outline package，SOP)之仰視圖。本發明之另一實施例中，各側面220可定義有一第一區231、一第二區232及一第三區233。第一區231位於第二區232及第三區233之間。FIG. 5 is a bottom view of a small outline package (SOP) of one embodiment of the integrated circuit package component of the present invention. In another embodiment of the present invention, each side surface 220 defines a first area 231, a second area 232, and a third area 233. The first zone 231 is located between the second zone 232 and the third zone 233.
此些接腳300包括多個第一接腳321、第二接腳322及第三接腳323。此些第一接腳321分別線性排列於此側面220且位於第一區231。此些第二接腳322分別線性排列於此側面220且位於第二區232。此些第三接腳323分別線性排列於此側面220且位於第三區233。The pins 300 include a plurality of first pins 321 , second pins 322 , and third pins 323 . The first pins 321 are linearly arranged on the side surface 220 and located in the first region 231, respectively. The second pins 322 are linearly arranged on the side 220 and located in the second region 232, respectively. The third pins 323 are linearly arranged on the side surface 220 and located in the third region 233, respectively.
此些第一接腳321可合稱一第一接腳群321a，此些第一接腳321分別具一第一焊接區331，此些第一焊接區331具有相同之面積。此些第二接腳322可合稱一第二接腳群322a，此些第二接腳322分別具一第二焊接區332，此些第二焊接區332彼此具有相同之面積。此些第三接腳323可合稱一第三接腳群323a，此些第三接腳323分別具一第三焊接區333，此些第三焊接區333彼此具有相同之面積。任一第一焊接區331的面積係小於任一第二焊接區332的面積及任一第三焊接區333的面積。The first pins 321 can be collectively referred to as a first pin group 321a. The first pins 321 respectively have a first pad 331. The first pads 331 have the same area. The second pins 322 can be collectively referred to as a second pin group 322a. The second pins 322 respectively have a second pad 332. The second pads 332 have the same area. The third pins 323 can be collectively referred to as a third pin group 323a. Each of the third pins 323 has a third pad 333. The third pads 333 have the same area. The area of any of the first pads 331 is smaller than the area of any of the second pads 332 and the area of any of the third pads 333.
由於第二焊接區332的面積及第三焊接區333的面積皆大於第一焊接區331的面積，故積體電路封裝元件100接近邊緣之接腳具有較大之焊接面積，使得積體電路封裝元件100具有更高之抗應力強度。Since the area of the second pad 332 and the area of the third pad 333 are both larger than the area of the first pad 331, the pin of the integrated circuit package component 100 near the edge has a large soldering area, so that the integrated circuit package Element 100 has a higher resistance to stress.
具體而言，任一第一焊接區331的面積之寬度h舉例而言可為0.22～0.32公釐(mm)(即為0.22,0.23,0.24,0.25,0.26,0.27,0.28,0.29,0.30,0.31及0.32其中之一)。任一第二焊接區332的面積之寬度h為0.28～0.38公釐(mm)(即為0.28,0.29,0.30,0.31,0.32,0.33,0.34,0.35,0.36,0.37,0.38其中之一)。任一第三焊接區333的面積之寬度h為0.28～0.38公釐(mm)(即為0.28,0.29,0.30,0.31,0.32,0.33,0.34,0.35,0.36,0.37,0.38其中之一)。此些接腳300通常呈針腳狀、片狀或塊狀，由於此些接腳之長度及厚度皆一致，因此其寬度h之不同便決定了焊接區面積之不同。Specifically, the width h of the area of any of the first lands 331 may be, for example, 0.22 to 0.32 mm (ie, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.30, One of 0.31 and 0.32). The width h of the area of any of the second weld zones 332 is 0.28 to 0.38 mm (i.e., one of 0.28, 0.29, 0.30, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38). The width h of the area of any of the third land 333 is 0.28 to 0.38 mm (i.e., one of 0.28, 0.29, 0.30, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38). The pins 300 are generally in the form of pins, sheets or blocks. Since the lengths and thicknesses of the pins are the same, the difference in the width h determines the difference in the area of the pads.
此實施例更進一步揭露封裝本體200更包括一第四區234及一第五區235。第四區234介於第一區231與第二區232之間。第五區235介於第一區231與第三區233之間。This embodiment further discloses that the package body 200 further includes a fourth region 234 and a fifth region 235. The fourth zone 234 is between the first zone 231 and the second zone 232. The fifth zone 235 is interposed between the first zone 231 and the third zone 233.
此些接腳300包括多個第四接腳324及第五接腳325。此些第四接腳324可合稱一第四接腳群324a，分別線性排列於此側面220且位於第四區234，此些第五接腳325可合稱一第五接腳群325a，分別線性排列於此側面220且位於第五區235。The pins 300 include a plurality of fourth pins 324 and fifth pins 325. The fourth pins 324 can be collectively referred to as a fourth pin group 324a, and are respectively linearly arranged on the side surface 220 and located in the fourth area 234. The fifth pins 325 can be collectively referred to as a fifth pin group 325a. They are linearly arranged on the side surface 220 and located in the fifth region 235, respectively.
此些第四接腳324分別具一第四焊接區334，此些第四焊接區334具有相同之面積，且任一第四焊接區334的面積大於任一第一焊接區331的面積，小於任一第二焊接區332的面積。The fourth pins 324 respectively have a fourth pad 334. The fourth pads 334 have the same area, and the area of any of the fourth pads 334 is larger than the area of any of the first pads 331. The area of any of the second weld zones 332.
此些第五接腳325分別具一第五焊接區335，此些第五焊接區335具有相同之面積，且任一第五焊接區335的面積大於任一第一焊接區331的面積，小於任一第三焊接區333的面積。The fifth pins 325 respectively have a fifth pad 335. The fifth pads 335 have the same area, and the area of any of the fifth pads 335 is larger than the area of any of the first pads 331. The area of any third weld zone 333.
依據上述各實施例中，此積體電路封裝元件100不限其外型、種類及規格，只要其接腳由側面所伸出，並符合上述之精神，均為本發明欲保護之技術手段。According to the above embodiments, the integrated circuit package component 100 is not limited to its appearance, type and specification, and as long as its pins extend from the side and conform to the spirit of the above, all of the technical means for protection of the present invention.
於一具體實施例中，積體電路封裝元件100之封裝本體200之外型可例如為矩形、圓形或多邊形。當封裝本體200呈圓形時，此些接腳300分別排列於周圍側面。當封裝本體200呈矩形時，此些接腳300係可分別線性地排列於至少二對應側面或全部四個側面上，而非限於上述實施例中之單一側面。In one embodiment, the package body 200 of the integrated circuit package component 100 may be, for example, rectangular, circular, or polygonal. When the package body 200 is circular, the pins 300 are respectively arranged on the surrounding sides. When the package body 200 is rectangular, the pins 300 can be linearly arranged on at least two corresponding sides or all four sides, respectively, instead of being limited to a single side in the above embodiment.
於一具體實施例中，積體電路封裝元件100可例如為一四方形扁平封裝元件(quad flat package，QFP)、一四方形扁平無引腳封裝元件(quad flat non-leaded package，QFN)或一四方形扁平I形引腳封裝元件(quad flat I-leaded package，QFI)。In one embodiment, the integrated circuit package component 100 can be, for example, a quad flat package (QFP), a quad flat non-leaded package (QFN), or A quad flat I-leaded package (QFI).
積體電路封裝元件100亦可例如為一小外型封裝元件(small outline package，SOP)、一小外型J型接腳封裝元件(Small Outline J-lead Package，SOJ)或一小外型I型接腳封裝元件(Small Outline I-lead Package，SOI)。The integrated circuit package component 100 can also be, for example, a small outline package (SOP), a small outline J-lead package (SOJ), or a small form factor I. Small Outline I-lead Package (SOI).
積體電路封裝元件100亦可例如為一帶引脚的陶瓷晶片載體(Ceramic Leaded Chip Carrier，CLCC)、一帶引脚的塑膠晶片載體(Plastic Leaded Chip Carrier，PLCC)或一J形引脚晶片載體(J-leaded chip carrier，JLCC)。The integrated circuit package component 100 can also be, for example, a ceramic leaded chip carrier (CLCC) with a lead, a plastic leaded chip carrier (PLCC) or a J-shaped lead wafer carrier ( J-leaded chip carrier, JLCC).
積體電路封裝元件100亦可例如為一單列直插式封裝元件(Single In-Line Package，SIP)、一雙列直插式封裝元件(Dual In-Line Package，DIP)或一交叉引腳封裝元件(Zigzag In-Line Package，ZIP)。The integrated circuit package component 100 can also be, for example, a single in-line package (SIP), a dual in-line package (DIP), or a cross-lead package. Component (Zigzag In-Line Package, ZIP).
需說明的是，此側面220上並無任何痕跡或提示而得知第一區231至第五區235之存在，本說明書定義第一區231至第五區235僅為方便說明各第一接腳321至第五接腳325之對應位置及關係，本發明所屬技術領域之人士可由各區中接腳之不同焊接面積而分辨出第一區231至第五區235的存在。It should be noted that there is no trace or prompt on the side 220 to know the existence of the first area 231 to the fifth area 235. The first area 231 to the fifth area 235 are defined in the present specification for convenience only. The corresponding positions and relationships of the feet 321 to the fifth pins 325, those skilled in the art can distinguish the presence of the first to fifth regions 231 to 235 by the different welding areas of the pins in the respective regions.
此外，第一接腳321、第二接腳322、第三接腳323、第四接腳324及第五接腳325皆屬於此些接腳300的其中之一。上述之接腳一至接腳十三或上述之接腳一至接腳十皆屬於此些接腳300的其中之一。In addition, the first pin 321 , the second pin 322 , the third pin 323 , the fourth pin 324 , and the fifth pin 325 belong to one of the pins 300 . The above-mentioned pin one to pin thirteen or the above-mentioned pin one to pin ten belong to one of the pins 300.
本說明書定義第一接腳群321a至第五接腳群325a僅為方便區分各對應接腳群中之接腳300，本發明所屬技術領域之人士可由各接腳300之不同焊接面積而分辨出第一接腳群321a至第五接腳群325a。The present specification defines the first pin group 321a to the fifth pin group 325a for the purpose of distinguishing the pins 300 in each corresponding pin group. The person skilled in the art can distinguish the different welding areas of the pins 300. The first pin group 321a to the fifth pin group 325a.
綜上所述，藉由發現積體電路封裝元件之同心圓受力分佈，本發明提供上述種種之技術手段，以補強此些接腳經歷應力彎曲之抗應力能力。如此，便可有效提升積體電路封裝元件於電路板上之結構強度，進而提高積體電路封裝元件的疲勞壽命以及整體可靠性。In summary, the present invention provides various technical means for reinforcing the stress resistance of the pins to undergo stress bending by finding the concentric circle force distribution of the integrated circuit package components. In this way, the structural strength of the integrated circuit package component on the circuit board can be effectively improved, thereby improving the fatigue life and overall reliability of the integrated circuit package component.
本發明所揭露如上之各實施例中，並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention is not limited to the embodiments of the present invention, and various modifications and refinements may be made without departing from the spirit and scope of the present invention. This is subject to the definition of the scope of the patent application.
100．．．積體電路封裝元件100. . . Integrated circuit package component
200．．．封裝本體200. . . Package body
210．．．安置面210. . . Placement surface
220．．．側面220. . . side
231．．．第一區231. . . First district
232．．．第二區232. . . Second district
233．．．第三區233. . . Third district
234．．．第四區234. . . Fourth district
235．．．第五區235. . . Fifth district
300．．．接腳300. . . Pin
301．．．焊接區301. . . Weld area
311．．．中央接腳311. . . Central pin
312．．．首位接腳312. . . First pin
313．．．末位接腳313. . . Last pin
321．．．第一接腳321. . . First pin
321a．．．第一接腳群321a. . . First pin group
322．．．第二接腳322. . . Second pin
322a．．．第二接腳群322a. . . Second pin group
323．．．第三接腳323. . . Third pin
323a．．．第三接腳群323a. . . Third pin group
324．．．第四接腳324. . . Fourth pin
324a．．．第四接腳群324a. . . Fourth pin group
325．．．第五接腳325. . . Fifth pin
325a．．．第五接腳群325a. . . Fifth pin group
331．．．第一焊接區331. . . First weld zone
332．．．第二焊接區332. . . Second weld zone
333．．．第三焊接區333. . . Third weld zone
334．．．第四焊接區334. . . Fourth weld zone
335．．．第五焊接區335. . . Fifth weld zone
p．．．應力線p. . . Stress line
c．．．幾何中心點c. . . Geometric center point
r．．．角落r. . . corner
h．．．寬度h. . . width
D1、D2．．．方向D1, D2. . . direction
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之詳細說明如下：The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.
第1圖為積體電路封裝元件受到應力時之應力線分佈圖。Fig. 1 is a diagram showing the stress line distribution when an integrated circuit package component is subjected to stress.
第2A圖繪示本發明具側邊接腳之積體電路封裝元件之一實施例下一四方形扁平封裝元件(QFP)之立體示意圖。FIG. 2A is a perspective view showing a fourth quad flat package element (QFP) according to an embodiment of the integrated circuit package component of the present invention.
第2B圖繪示第2A圖之一側視圖。Figure 2B shows a side view of Figure 2A.
第3圖繪示第2A圖之一仰視圖。Figure 3 is a bottom view of Figure 2A.
第4圖繪示本發明具側邊接腳之積體電路封裝元件之一實施例下一四方形扁平無引腳封裝元件(QFN)之仰視圖。4 is a bottom view of a quad flat no-lead package component (QFN) of one embodiment of the integrated circuit package component of the present invention.
第5圖繪示本發明具側邊接腳之積體電路封裝元件之一實施例下一小外型封裝元件(SOP)之仰視圖。FIG. 5 is a bottom view of the next small outline package component (SOP) of one embodiment of the integrated circuit package component of the present invention.
100．．．積體電路封裝元件100. . . Integrated circuit package component
200．．．封裝本體200. . . Package body
210．．．安置面210. . . Placement surface
220．．．側面220. . . side
300．．．接腳300. . . Pin
301．．．焊接區301. . . Weld area
311．．．中央接腳311. . . Central pin
312．．．首位接腳312. . . First pin
313．．．末位接腳313. . . Last pin
h．．．寬度h. . . width
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099109951ATWI405313B (en) | 2010-03-31 | 2010-03-31 | Integrated circuit package component with lateral conducting pins |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099109951ATWI405313B (en) | 2010-03-31 | 2010-03-31 | Integrated circuit package component with lateral conducting pins |
| Publication Number | Publication Date |
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| TW201133742A TW201133742A (en) | 2011-10-01 |
| TWI405313Btrue TWI405313B (en) | 2013-08-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099109951ATWI405313B (en) | 2010-03-31 | 2010-03-31 | Integrated circuit package component with lateral conducting pins |
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| TW (1) | TWI405313B (en) |
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