本發明是有關於一種靜電放電防護模組，特別是指一種防護來自一晶片外部或內部的靜電放電效應干擾該晶片之靜電放電防護模組。The present invention relates to an electrostatic discharge protection module, and more particularly to an electrostatic discharge protection module that protects the wafer from electrostatic discharge effects from the outside or inside of a wafer.
一般而言，靜電放電(Electrostatic Discharge,ESD)效應是造成大多數的電子元件或電子系統受到過度電性應力(Electrical Overstress,EOS)破壞的主要因素。這種破壞會導致半導體元件以及電腦系統等，形成一種永久性或非永久性(暫時性)的毀壞，因而影響一晶片或一電子產品的電路功能，而使得電子產品工作不正常。In general, the Electrostatic Discharge (ESD) effect is the main cause of most electronic components or electronic systems being damaged by Electrical Overstress (EOS). Such damage can result in permanent or non-permanent (temporary) damage to semiconductor components and computer systems, etc., thereby affecting the circuit function of a wafer or an electronic product, and causing the electronic product to malfunction.
現階段對於靜電放電防護相關技術皆是針對一電子裝置中或是一晶片中發生靜電放電效應所影響之對應的暫存器或是閂鎖器(latch)進行保護，如：中華民國專利號I296439、I300291、I302374等，此種技術需要針對該電子裝置或是該晶片中多數個暫存器或是閂鎖器分別加入對應的保護電路，此舉將增加該電子裝置或是該晶片的設計及生產成本，而且一旦發生靜電放電效應時，其僅能對於有加入保護電路設計之相關暫存器或是閂鎖器進行保護，對於其他該電子裝置或是該晶片中未受到保護電路保護之其餘電路元件可能會產生無法預期的影響，進而導致該電子裝置或該晶片產生錯誤動作或是執行錯誤的指令，這些都是現今技術仍無法解決的問題。At present, the related technologies for electrostatic discharge protection are for protecting the corresponding scratchpad or latch of an electronic device or an electrostatic discharge effect in a wafer, such as: Republic of China Patent No. I296439 , I300291, I302374, etc., such technology needs to add a corresponding protection circuit for the electronic device or a plurality of registers or latches in the chip, which will increase the design of the electronic device or the chip and Production cost, and once the electrostatic discharge effect occurs, it can only protect the relevant registers or latches that have been added to the protection circuit design, and the rest of the electronic device or the chip that is not protected by the protection circuit. Circuit components can have unpredictable effects, causing the electronic device or the chip to malfunction or execute erroneous instructions, which are still unresolved by today's technology.
因此，本發明之目的，即在提供一種靜電放電防護模組，適用於分別與一電子裝置之晶片模式選擇單元及一晶片電連接，以接收該晶片模式選擇單元輸出之一晶片模式選擇訊號，其包含：一靜電放電感測單元，與該電子裝置電連接用以感測該電子裝置中是否存在靜電放電效應，並據此輸出一靜電放電感測訊號；及一邏輯運算單元，分別與該晶片模式選擇單元及該靜電放電感測單元電連接，以接收該晶片模式選擇訊號與該靜電放電感測訊號，並將該等訊號進行一或運算或一及運算，以輸出一晶片模式控制訊號至該晶片中。Therefore, an object of the present invention is to provide an electrostatic discharge protection module, which is respectively adapted to be electrically connected to a chip mode selection unit and a chip of an electronic device to receive a wafer mode selection signal of the chip mode selection unit output. The method includes: an electrostatic discharge sensing unit electrically connected to the electronic device for sensing whether an electrostatic discharge effect exists in the electronic device, and outputting an electrostatic discharge sensing signal according to the signal; and a logic operation unit respectively The chip mode selection unit and the electrostatic discharge sensing unit are electrically connected to receive the chip mode selection signal and the electrostatic discharge sensing signal, and perform an OR operation or a sum operation on the signals to output a wafer mode control signal. Into the wafer.
此外，本發明更提供一種靜電放電防護模組，適用於與一晶片之控制模組電連接，以接收該控制模組輸出之一晶片重置訊號，其包含：一靜電放電感測單元，與該晶片電連接用以感測該晶片中是否存在靜電放電效應，並據此輸出一靜電放電感測訊號；及一邏輯運算單元，分別與該控制模組及該靜電放電感測單元電連接，以接收該晶片重置訊號與該靜電放電感測訊號，並將該等訊號進行一或運算或一及運算，以輸出一晶片模式控制訊號至該晶片中。In addition, the present invention further provides an electrostatic discharge protection module, which is adapted to be electrically connected to a control module of a chip to receive a wafer reset signal outputted by the control module, comprising: an electrostatic discharge sensing unit, and The chip is electrically connected to sense whether there is an electrostatic discharge effect in the wafer, and accordingly outputs an electrostatic discharge sensing signal; and a logic operation unit is electrically connected to the control module and the electrostatic discharge sensing unit, respectively. Receiving the wafer reset signal and the electrostatic discharge sensing signal, and performing an OR operation or a sum operation on the signals to output a wafer mode control signal to the wafer.
此外，本發明更提供一種靜電放電防護模組，適用於分別與一電子裝置之晶片模式選擇單元及一晶片電連接，其包含：一電源訊號感測器，與該電子裝置電連接並用以感測該電子裝置中一電源重置訊號；一靜電放電偵測器，與該電子裝置電連接並用以感測該電子裝置中是否存在靜電放電效應；及一或閘，與該電源訊號感測器及該靜電放電偵測器電連接，且其根據該電源訊號感測器及該靜電放電偵測器之輸出值進行一或運算，以得出一靜電放電感測訊號以切換該晶片之執行模式。In addition, the present invention further provides an ESD protection module, which is respectively adapted to be electrically connected to a chip mode selection unit and a chip of an electronic device, and includes: a power signal sensor electrically connected to the electronic device and used for sensing Detecting a power reset signal in the electronic device; an electrostatic discharge detector electrically connected to the electronic device and sensing whether an electrostatic discharge effect exists in the electronic device; and a thyristor and the power signal sensor And the ESD detector is electrically connected, and performs an OR operation according to the output values of the power signal sensor and the ESD detector to obtain an ESD sensing signal to switch the execution mode of the chip. .
此外，本發明更提供一種靜電放電防護模組，適用於與一晶片電連接，其包含：一電源訊號感測器，與該晶片電連接並用以感測該晶片中一電源重置訊號；一靜電放電偵測器，與該晶片電連接並用以感測該晶片中是否存在靜電放電效應；及一或閘，與該電源訊號感測器及該靜電放電偵測器電連接，且其根據該電源訊號感測器及該靜電放電偵測器之輸出值進行一或運算，以得出一靜電放電感測訊號以切換該晶片之執行模式。In addition, the present invention further provides an ESD protection module, which is adapted to be electrically connected to a chip, and includes: a power signal sensor electrically connected to the chip for sensing a power reset signal in the chip; An ESD detector electrically connected to the chip and configured to sense an electrostatic discharge effect in the wafer; and an OR gate electrically connected to the power signal sensor and the ESD detector, and according to the The output signal of the power signal sensor and the electrostatic discharge detector are ORed to obtain an electrostatic discharge sensing signal to switch the execution mode of the chip.
於是，本發明之靜電放電防護模組，其功效在於有效偵測一電子裝置或一晶片是否存在靜電放電效應，並於發生該靜電放電效應時將該晶片切換至一閒置模式或一睡眠模式，以有效隔離該靜電放電效應對於該晶片之傷害，同時，本發明利用簡單之邏輯電路即可達到上述目的，所以幾乎不會增加該晶片的設計及生產成本。Therefore, the electrostatic discharge protection module of the present invention has the effect of effectively detecting whether an electronic device or a wafer has an electrostatic discharge effect, and switching the wafer to an idle mode or a sleep mode when the electrostatic discharge effect occurs. In order to effectively isolate the electrostatic discharge effect from damage to the wafer, the present invention achieves the above object by using a simple logic circuit, so that the design and production cost of the wafer is hardly increased.
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之二個較佳實施例的詳細說明中，將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.
在本發明被詳細描述之前，要注意的是，在以下的說明內容中，類似的元件是以相同的編號來表示。Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.
參閱圖1，本發明靜電放電防護模組1之第一較佳實施例分別與一電子裝置9之晶片模式選擇單元91及一晶片8電連接，以接收該晶片模式選擇單元9輸出之一晶片模式選擇訊號(CSX)，其用以切換該晶片8目前的執行模式，，其包含：一靜電放電感測單元11及一邏輯運算單元12。Referring to FIG. 1, a first preferred embodiment of the ESD protection module 1 of the present invention is electrically connected to a chip mode selection unit 91 and a chip 8 of an electronic device 9 to receive a wafer output from the wafer mode selection unit 9. The mode selection signal (CSX) is used to switch the current execution mode of the chip 8, and includes: an electrostatic discharge sensing unit 11 and a logic operation unit 12.
該靜電放電感測單元11包括：一靜電放電偵測器(ESD detector)111、一電源訊號感測器112，與一或閘(OR gate)113。該靜電放電偵測器111、該電源訊號感測器112分別與該或閘113電連接，且該或閘113根據該靜電放電偵測器111、該電源訊號感測器112之輸出值進行一或運算以得到一靜電放電感測訊號(ESD_DET)，而該或閘113將該靜電放電感測訊號ESD_DET輸出至該邏輯運算單元12中，使得該邏輯運算單元12根據該晶片模式選擇訊號CSX與該靜電放電感測訊號ESD_DET進行一邏輯運算，以輸出一晶片模式控制訊號(CCX)至該晶片8中。其中，在本實施例中，該邏輯運算單元12是一或閘(圖未示)。The ESD sensing unit 11 includes an ESD detector 111, a power signal sensor 112, and an OR gate 113. The ESD detector 111 and the power signal sensor 112 are respectively electrically connected to the OR gate 113, and the OR gate 113 is configured according to the output values of the ESD detector 111 and the power signal sensor 112. Or the operation to obtain an electrostatic discharge sensing signal (ESD_DET), and the OR gate 113 outputs the electrostatic discharge sensing signal ESD_DET to the logic operation unit 12, so that the logic operation unit 12 selects the signal CSX according to the wafer mode. The ESD sensing signal ESD_DET performs a logic operation to output a wafer mode control signal (CCX) to the wafer 8. In this embodiment, the logic operation unit 12 is an OR gate (not shown).
該靜電放電偵測器111用以偵測該電子裝置9中是否發生靜電放電效應，若是，則其輸出值為1，若否，則其輸出值為0。而該電源訊號感測器112用以偵測該電子裝置9之總電源(Global power)是否受到靜電放電效應的影響，若是，則其輸出值為1，若否，則其輸出值為0。其中，在本實施例中，該電源訊號感測器112是用以感測該電子裝置9之電源重置訊號(Power On Reset signal,POR)，因為，當該電子裝置9受到靜電放電效應的干擾時，該電子裝置9之總電源訊號亦會受到影響而產生不規則突波，因此，該電源訊號感測器112可用以感測該電源重置訊號POR是否因靜電放電效應而產生不正常之誤動作。若該電源重置訊號POR受到靜電放電效應的影響時，則該電源訊號感測器112的輸出值為1，反之，該電源訊號感測器112的輸出值則為0。The ESD detector 111 is configured to detect whether an electrostatic discharge effect occurs in the electronic device 9, and if so, the output value is 1, and if not, the output value is 0. The power signal sensor 112 is configured to detect whether the global power of the electronic device 9 is affected by the electrostatic discharge effect. If yes, the output value is 1, and if not, the output value is 0. In this embodiment, the power signal sensor 112 is configured to sense a power on reset signal (POR) of the electronic device 9 because the electronic device 9 is subjected to an electrostatic discharge effect. When the interference occurs, the total power signal of the electronic device 9 is also affected to generate an irregular surge. Therefore, the power signal sensor 112 can be used to sense whether the power reset signal POR is abnormal due to the electrostatic discharge effect. Mistakes. If the power reset signal POR is affected by the electrostatic discharge effect, the output value of the power signal sensor 112 is 1, and vice versa, the output value of the power signal sensor 112 is zero.
換句話說，當該電子裝置9受到靜電放電效應影響時，藉由該靜電放電偵測器111與該電源訊號感測器112所對應的輸出值，經過該或閘113的運算之後，可使得該靜電放電感測訊號ESD_DET為1，而且無論該晶片模式選擇訊號CSX的值為何，該晶片模式控制訊號CCX亦為1，所以可使得該晶片8切換至一閒置模式(Idle mode)。In other words, when the electronic device 9 is affected by the electrostatic discharge effect, the output value corresponding to the power signal detector 112 by the electrostatic discharge detector 111 can be made after the operation of the OR gate 113. The ESD sensing signal ESD_DET is 1, and the chip mode control signal CCX is also 1, regardless of the value of the chip mode selection signal CSX, so that the wafer 8 can be switched to an Idle mode.
在本實施例中，該閒置模式之定義為該晶片8對於其輸入端所輸入之資料皆不進行儲存、處理、回應等任何動作，換句話說，當該晶片8切換至該閒置模式時，將忽略任何輸入資料且不接收或儲存之，以避免接收到任何因為該電子裝置9受到靜電放電效應影響而產生之錯誤訊號及錯誤資料，使得該晶片8執行錯誤的指令，因此，對於該晶片8而言可以有效隔離來自電子裝置9或是晶片外部的靜電放電效應所引起之間接干擾。In this embodiment, the idle mode is defined as any operation in which the data input by the chip 8 is not stored, processed, responded, etc., in other words, when the wafer 8 is switched to the idle mode, Any input data will be ignored and will not be received or stored to avoid receiving any error signals and erroneous data generated by the electrostatic discharge effect of the electronic device 9, so that the wafer 8 executes the wrong command, and therefore, for the wafer 8 can effectively isolate the interference caused by the electrostatic discharge effect from the electronic device 9 or the outside of the wafer.
此外，值得說明的是，本實施例之靜電放電防護模組1可以設置於該晶片8外部且與該晶片8電連接，或是可設置於該晶片8內部。且該邏輯運算單元12可以視該靜電放電感測訊號ESD_DET及該晶片模式選擇訊號CSX的特性為正緣觸發訊號或是負緣觸發訊號，做適當的等效修改之，舉例來說，當該靜電放電感測訊號ESD_DET為0時代表該電子裝置9中發生靜電放電效應，此時，該邏輯運算單元12可以變更設計為一及閘(AND gate)，使得該晶片模式控制訊號CCX為0，且將該晶片模式控制訊號CCX為0設計為切換該晶片8進入該閒置模式，因此，此等變更訊號特性以改變該邏輯運算單元12之設計的迴避方式，皆視為本領域具有專業知識之人士可輕易修改之等效設計，因此仍屬於本發明專利所涵蓋之專利範圍內。In addition, it should be noted that the ESD protection module 1 of the present embodiment may be disposed outside the wafer 8 and electrically connected to the wafer 8 or may be disposed inside the wafer 8. The logic operation unit 12 can perform appropriate equivalent modification according to the characteristics of the electrostatic discharge sensing signal ESD_DET and the chip mode selection signal CSX as a positive edge trigger signal or a negative edge trigger signal. For example, when When the ESD sensing signal ESD_DET is 0, the electrostatic discharge effect occurs in the electronic device 9. In this case, the logic operation unit 12 can be changed to an AND gate so that the wafer mode control signal CCX is 0. And the chip mode control signal CCX is set to 0 to switch the chip 8 into the idle mode. Therefore, the manner of changing the signal characteristics to change the design of the logic operation unit 12 is regarded as having expertise in the field. The equivalent design can be easily modified by a person and is therefore still within the scope of the patent covered by the present invention.
參閱圖2，本發明靜電放電防護模組1之第二較佳實施例，是與一晶片8之控制模組81電連接，以接收該控制模組81輸出之一晶片重置訊號(RSTN)，其用以重置該晶片8，其包含：一靜電放電感測單元11及一邏輯運算單元12。Referring to FIG. 2, a second preferred embodiment of the ESD protection module 1 of the present invention is electrically connected to a control module 81 of a chip 8 to receive a wafer reset signal (RSTN) output from the control module 81. It is used to reset the wafer 8, which comprises: an electrostatic discharge sensing unit 11 and a logic operation unit 12.
該靜電放電感測單元11包括：一靜電放電偵測器111、一電源訊號感測器112，與一或閘113。該靜電放電偵測器111、該電源訊號感測器112分別與該或閘113電連接，且該或閘113根據該靜電放電偵測器111、該電源訊號感測器112之輸出值進行一或運算以得到一靜電放電感測訊號ESD_DET，而該或閘113將該靜電放電感測訊號ESD_DET輸出至該邏輯運算單元12中，使得該邏輯運算單元12根據該晶片重置訊號RSTN與該靜電放電感測訊號ESD_DET進行一邏輯運算，以輸出一晶片模式控制訊號CCXN至該晶片8之中。其中，在本實施例中，該邏輯運算單元12包括：一及閘121與一反閘(inverter) 122。The ESD sensing unit 11 includes an ESD detector 111, a power signal sensor 112, and an OR gate 113. The ESD detector 111 and the power signal sensor 112 are respectively electrically connected to the OR gate 113, and the OR gate 113 is configured according to the output values of the ESD detector 111 and the power signal sensor 112. Or the operation to obtain an electrostatic discharge sensing signal ESD_DET, and the OR gate 113 outputs the electrostatic discharge sensing signal ESD_DET to the logic operation unit 12, so that the logic operation unit 12 resets the signal RSTN according to the wafer and the static electricity. The electrical inductance signal ESD_DET is subjected to a logic operation to output a wafer mode control signal CCXN to the wafer 8. In the embodiment, the logic operation unit 12 includes: a gate 121 and an inverter 122.
該靜電放電偵測器111用以偵測該晶片8中是否發生靜電放電效應，若是，則其輸出值為1，若否，則其輸出值為0。而該電源訊號感測器112用以偵測該晶片8之電源訊號是否受到靜電放電效應的影響，若是，則其輸出值為1，若否，則其輸出值為0。The ESD detector 111 is configured to detect whether an electrostatic discharge effect occurs in the wafer 8, and if so, the output value is 1, and if not, the output value is 0. The power signal sensor 112 is configured to detect whether the power signal of the chip 8 is affected by the electrostatic discharge effect. If yes, the output value is 1, and if not, the output value is 0.
值得說明的是，在本實施例中，該晶片重置訊號RSTN為一負緣觸發訊號，且該晶片8所接收之晶片模式控制訊號CCXN亦為一負緣觸發訊號，也就是說，當該晶片模式控制訊號CCXN為0時，該晶片8將切換至一睡眠模式(Sleeping mode)。It should be noted that, in this embodiment, the wafer reset signal RSTN is a negative edge trigger signal, and the chip mode control signal CCXN received by the chip 8 is also a negative edge trigger signal, that is, when When the chip mode control signal CCXN is 0, the chip 8 will switch to a sleep mode.
該或閘113輸出之該靜電放電感測訊號ESD_DET經由該反閘122進行反向運算後，再輸出至該及閘121與該晶片重置訊號RSTN做及運算。因此，當該晶片8受到靜電放電效應影響時，藉由該靜電放電偵測器111與該電源訊號感測器112所對應的輸出值，經過該或閘113的運算之後，可使得該靜電放電感測訊號ESD_DET為1，此時，不論該晶片重置訊號RSTN是否被觸發(亦即不論RSTN的值為何)，該邏輯運算單元12所輸出之晶片模式控制訊號CCXN會為0，以使得該晶片8切換至該睡眠模式。The electrostatic discharge sensing signal ESD_DET outputted by the OR gate 113 is reversely calculated via the reverse gate 122, and then output to the AND gate 121 for processing with the wafer reset signal RSTN. Therefore, when the wafer 8 is affected by the electrostatic discharge effect, the electrostatic discharge detector 111 and the output signal corresponding to the power signal sensor 112 can be electrostatically discharged after the operation of the OR gate 113. The sensing signal ESD_DET is 1. At this time, regardless of whether the wafer reset signal RSTN is triggered (that is, regardless of the value of the RSTN), the chip mode control signal CCXN output by the logic operation unit 12 is 0, so that the The wafer 8 is switched to the sleep mode.
在本實施例中，該睡眠模式之定義為該晶片8內部電路將暫停一切運作功能，換句話說，當該晶片8切換至該睡眠模式時，將停止該晶片之任何功能性處理，以避免因為該晶片8之內部電路受到靜電放電效應影響而產生之錯誤訊號及錯誤資料，使得晶片9執行錯誤的指令，因此，對於該晶片8而言可以有效防止因為晶片內部的靜電放電效應所產生之直接干擾。In the present embodiment, the sleep mode is defined as the internal circuit of the chip 8 will suspend all operational functions. In other words, when the wafer 8 is switched to the sleep mode, any functional processing of the wafer will be stopped to avoid Because the internal circuit of the chip 8 is affected by the electrostatic discharge effect, the error signal and the erroneous data are generated, so that the wafer 9 executes the wrong command, and therefore, the wafer 8 can be effectively prevented from being generated due to the electrostatic discharge effect inside the wafer. Direct interference.
補充說明的是，綜合前述二個較佳實施例，該邏輯運算單元12可根據所接收訊號的不同特性而以單一邏輯閘或是多數個邏輯閘的簡單組合以構成之，故該等簡單變化或修改之實施方式皆為本發明專利之涵蓋範圍。It should be noted that, in combination with the foregoing two preferred embodiments, the logic operation unit 12 can be configured by a single logic gate or a simple combination of a plurality of logic gates according to different characteristics of the received signals, so the simple changes The modified embodiments are all covered by the invention patent.
本發明之靜電放電防護模組可用以有效防護當一晶片內部或是與一晶片電連接之電子裝置發生靜電放電效應時對於該晶片所可能造成直接及間接的影響，同時，本發明可以將該晶片適當的切換至一閒置模式或是一睡眠模式，以有效避免靜電放電效應發生時所可能產生無法預期的錯誤動作或是執行錯誤指令，此外，本發明之靜電放電防護模組可以設置於該晶片外部與該晶片電連接，或是可設置於該晶片內部，然後經由精簡的數位邏輯運算方式以達成靜電放電防護的目的，所以幾乎不會增加該晶片的面積，當然也幾乎不會增加晶片的設計及生產成本，故確實能達成本發明之目的。The electrostatic discharge protection module of the present invention can be used to effectively protect the wafer from direct or indirect effects on the wafer when an electrostatic discharge effect occurs inside or between an electronic device electrically connected to a wafer, and the present invention can The chip is appropriately switched to an idle mode or a sleep mode to effectively prevent an unexpected malfunction or an incorrect command from being generated when the electrostatic discharge effect occurs, and the electrostatic discharge protection module of the present invention can be disposed on the The outside of the wafer is electrically connected to the wafer, or can be disposed inside the wafer, and then through the simplified digital logic operation to achieve the purpose of electrostatic discharge protection, so that the area of the wafer is hardly increased, and of course, the wafer is hardly increased. The design and production costs are such that the object of the invention can be achieved.
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.
1．．．靜電放電防護模組1. . . Electrostatic discharge protection module
11．．．靜電放電感測單元11. . . Electrostatic discharge sensing unit
111．．．靜電放電偵測器111. . . Electrostatic discharge detector
112．．．電源訊號感測器112. . . Power signal sensor
113．．．或閘113. . . Gate
12．．．邏輯運算單元12. . . Logical unit
121．．．及閘121. . . Gate
122．．．反閘122. . . Reverse gate
圖1是本發明之第一較佳實施例之示意圖；及Figure 1 is a schematic view of a first preferred embodiment of the present invention; and
圖2是本發明之第一較佳實施例之示意圖。Figure 2 is a schematic illustration of a first preferred embodiment of the present invention.
1．．．靜電放電防護模組1. . . Electrostatic discharge protection module
11．．．靜電放電感測單元11. . . Electrostatic discharge sensing unit
111．．．靜電放電偵測器111. . . Electrostatic discharge detector
112．．．電源訊號感測器112. . . Power signal sensor
113．．．或閘113. . . Gate
12．．．邏輯運算單元12. . . Logical unit
8．．．晶片8. . . Wafer
9．．．電子裝置9. . . Electronic device
91．．．晶片模式選擇單元91. . . Wafer mode selection unit
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99111242ATWI400009B (en) | 2010-04-12 | 2010-04-12 | Electrostatic discharge protection module |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99111242ATWI400009B (en) | 2010-04-12 | 2010-04-12 | Electrostatic discharge protection module |
| Publication Number | Publication Date |
|---|---|
| TW201136455A TW201136455A (en) | 2011-10-16 |
| TWI400009Btrue TWI400009B (en) | 2013-06-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW99111242ATWI400009B (en) | 2010-04-12 | 2010-04-12 | Electrostatic discharge protection module |
| Country | Link |
|---|---|
| TW (1) | TWI400009B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5407854A (en)* | 1994-01-19 | 1995-04-18 | General Signal Corporation | ESD protection of ISFET sensors |
| TW200717961A (en)* | 2005-10-21 | 2007-05-01 | Via Tech Inc | Protecting circuits from electrostatic discharge |
| US7583484B2 (en)* | 2003-08-20 | 2009-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for ESD protection |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5407854A (en)* | 1994-01-19 | 1995-04-18 | General Signal Corporation | ESD protection of ISFET sensors |
| US7583484B2 (en)* | 2003-08-20 | 2009-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for ESD protection |
| TW200717961A (en)* | 2005-10-21 | 2007-05-01 | Via Tech Inc | Protecting circuits from electrostatic discharge |
| Publication number | Publication date |
|---|---|
| TW201136455A (en) | 2011-10-16 |
| Publication | Publication Date | Title |
|---|---|---|
| CN102622150B (en) | Static eliminating method for touch screen | |
| US7503501B2 (en) | Abnormal condition detection circuit, integrated circuit card having the circuit, and method of operating CPU | |
| US6819539B1 (en) | Method for circuit recovery from overstress conditions | |
| US8896975B2 (en) | Voltage regulator over-voltage detection system, method and apparatus | |
| CN102541167A (en) | Electronic device | |
| CN102681739B (en) | Static elimination method for touch screen | |
| EP1952217A2 (en) | Automatic detection of a cmos circuit device in latch-up and reset of power thereto | |
| WO2019015301A1 (en) | Capacitance compensation module and method, and self-contained touch-control display panel and apparatus | |
| US10146370B2 (en) | Touch panel device having state restoration function | |
| US8315026B2 (en) | Semiconductor device and apparatus including semiconductor device | |
| US8179694B2 (en) | Magnetic induction grid as an early warning mechanism for space based microelectronics | |
| CN101488102B (en) | A Watchdog Control Circuit in Embedded System | |
| JP4670972B2 (en) | Integrated circuit device and electronic device | |
| JP6338943B2 (en) | Output circuit, detection sensor | |
| CN109992959A (en) | Fault injection defense method and device, chip and computer readable storage medium | |
| TWI400009B (en) | Electrostatic discharge protection module | |
| JP5096282B2 (en) | Transient noise detection circuit | |
| CN210898496U (en) | Electronic circuit and electronic device | |
| CN102347605A (en) | Electrostatic discharge protection module | |
| US20030196140A1 (en) | Semiconductor integrated circuit | |
| CN106992172A (en) | ESD protection integrated circuit and ESD detection circuit | |
| JP6797765B2 (en) | Capacitive touch switch module | |
| TWI412115B (en) | Electrostatic Discharge Protection Module for Integrated Circuit | |
| CN101387973B (en) | Device for preventing system misoperation | |
| Raina | Is the concern for soft-error overblown? |