本發明係有關於一多位元全文自適應二進制算術編碼的位元解碼器，尤指一種具有縮短的關鍵路徑的二決定位元的全文自適應二進制算術編碼解碼器。The present invention relates to a multi-bit full-text adaptive binary arithmetic coding bit decoder, and more particularly to a full-text adaptive binary arithmetic codec with two decision bits of a shortened critical path.
全文自適應二進制算術編碼(Context-adaptive Binary Arithmetic Coding,CABAC)解碼演算法是利用基本的連續運算去計算用於情境變數的範圍、偏移和查閱表。全文自適應二進制算術編碼解碼的資料相依特性，導致在即時處理高清晰度影像時，全文自適應二進制算術編碼解碼須做每秒30億次的運算，因此使全文自適應二進制算術編碼解碼很難達到高速解碼。基本上，全文自適應二進制算術編碼之位元解碼器包含一決定位元解碼器和一旁路位元解碼器，透過實驗，可知所有位元中的80%-90%位元被編碼成決定位元，而其餘位元被編碼成旁路位元。雖然Jahanghir等發明人的美國專利第7,262,722號已揭露使用利用平行架構改善全文自適應二進制算術編碼的效能的方法，但全文自適應二進制算術編碼解碼演算法不像其他H.264/AVC標準之視訊解碼工具，要利用平行架構去改善全文自適應二進制算術編碼的效能並不容易。因為全文自適應二進制算術編碼解碼係使用連續順序的解碼，然而連續順序的解碼會使得全文自適應二進制算術編碼解碼成為H.264/AVC標準主要的瓶頸。The Context-adaptive Binary Arithmetic Coding (CABAC) decoding algorithm uses basic continuous operations to calculate ranges, offsets, and look-up tables for context variables. Full-text adaptive binary arithmetic coding and decoding data dependent characteristics, resulting in full-time adaptive binary arithmetic coding decoding must be 3 billion operations per second when processing high-definition images in real time, thus making full-text adaptive binary arithmetic coding and decoding difficult Achieve high speed decoding. Basically, the bit-encoding decoder of full-text adaptive binary arithmetic coding includes a decision bit decoder and a bypass bit decoder. Through experiments, it is known that 80%-90% of all bits are encoded into decision bits. Yuan, and the remaining bits are encoded as bypass bits. Although the method of using parallel architecture to improve the performance of full-text adaptive binary arithmetic coding has been disclosed in U.S. Patent No. 7,262,722 to Jahanghir et al., the full-text adaptive binary arithmetic coding decoding algorithm is not like the video of other H.264/AVC standards. Decoding tools, it is not easy to use parallel architecture to improve the performance of full-text adaptive binary arithmetic coding. Because full-text adaptive binary arithmetic coding and decoding uses sequential sequential decoding, continuous sequential decoding makes full-text adaptive binary arithmetic coding decoding a major bottleneck in the H.264/AVC standard.
本發明的一實施例揭露一種多位元全文自適應二進制算術編碼的位元解碼器，包含一第一查閱表，具有一輸入端耦接於一第一暫存器的輸出端，用以接收該第一暫存器輸出的訊號；一第二查閱表，具有一輸入端耦接於該第一暫存器的輸出端，用以接收該第一暫存器輸出的訊號；一第三查閱表，具有一輸入端耦接於該第一查閱表的輸出端，用以接收該第一查閱表輸出的訊號；一第四查閱表，具有一輸入端耦接於該第二查閱表的輸出端，用以接收該第二查閱表輸出的訊號；一第一多工器，具有一第一輸入端耦接於該第三查閱表的輸出端，用以接收該第三查閱表輸出的訊號，一第二輸入端耦接於該第四查閱表的輸出端，用以接收該第四查閱表輸出的訊號；及一第二多工器，具有一第一輸入端耦接於該第一查閱表的輸出端，用以接收該第三查閱表輸出的訊號，一第二輸入端耦接於該第二查閱表的輸出端，用以接收該第二查閱表輸出的訊號；其中該第一多工器和該第二多工器皆由一第一訊號控制。該位元解碼器另包含串聯耦接的一第二暫存器、一第一加法器、一第二加法器和一第一比較模組，該第一比較模組係用以輸出該第一訊號。該位元解碼器另包含一第三多工器，具有一第一輸入端透過一第三暫存器耦接於該第二多工器的輸出端，用以接收該第二多工器輸出的訊號；一第五查閱表，具有一輸入端耦接於該第三多工器的輸出端，用以接收該第三多工器輸出的訊號；一第六查閱表，具有一輸入端耦接於該第三多工器的輸出端，用以接收該第三多工器輸出的訊號；一第七查閱表，具有一輸入端耦接於該第五查閱表的輸出端，用以接收該第五查閱表輸出的訊號；一第八查閱表，具有一輸入端耦接於該第六查閱表的輸出端，用以接收該第六查閱表輸出的訊號；一第四多工器，具有一第一輸入端耦接於該第七查閱表的輸出端，用以接收該第七查閱表輸出的訊號，一第二輸入端耦接於該第八查閱表的輸出端，用以接收該第八查閱表輸出的訊號；及一第五多工器，具有一第一輸入端耦接於該第五查閱表的輸出端，用以接收該第五查閱表輸出的訊號，一第二輸入端耦接於該第六查閱表的輸出端，用以接收該第六查閱表輸出的訊號；其中該第四多工器和該第五多工器皆由一第二訊號控制；其中該第一暫存器的輸入端係耦接於該第五多工器的輸出端，用以儲存該第五多工器輸出的訊號。該位元解碼器另包含串聯耦接的一第三加法器、一第四加法器和一第二比較模組，該第二比較模組係用以輸出該第二訊號。An embodiment of the present invention discloses a multi-bit full-text adaptive binary arithmetic coding bit decoder, comprising a first look-up table having an input coupled to an output of a first register for receiving a signal output by the first register; a second look-up table having an input coupled to the output of the first register for receiving a signal output by the first register; a third lookup The table has an input coupled to the output of the first lookup table for receiving the signal output by the first lookup table, and a fourth lookup table having an input coupled to the output of the second lookup table The first multiplexer has a first input coupled to the output of the third look-up table for receiving the signal output by the third look-up table. a second input end coupled to the output end of the fourth look-up table for receiving the signal output by the fourth look-up table; and a second multiplexer having a first input end coupled to the first The output of the lookup table is used to receive the output of the third lookup table a second input end coupled to the output end of the second look-up table for receiving the signal output by the second look-up table; wherein the first multiplexer and the second multiplexer are each connected by a first signal control. The bit decoder further includes a second register coupled in series, a first adder, a second adder, and a first comparison module, wherein the first comparison module is configured to output the first Signal. The bit decoder further includes a third multiplexer having a first input coupled to the output of the second multiplexer through a third register for receiving the second multiplexer output a fifth look-up table having an input coupled to the output of the third multiplexer for receiving a signal output by the third multiplexer; a sixth look-up table having an input coupled An output end of the third multiplexer for receiving the signal output by the third multiplexer; a seventh look-up table having an input coupled to the output of the fifth look-up table for receiving The signal output by the fifth look-up table; an eighth look-up table having an input coupled to the output of the sixth look-up table for receiving the signal output by the sixth look-up table; a fourth multiplexer, The first input end is coupled to the output end of the seventh look-up table for receiving the signal output by the seventh look-up table, and the second input end is coupled to the output end of the eighth look-up table for receiving a signal output by the eighth look-up table; and a fifth multiplexer having a first input coupled The output of the fifth look-up table is configured to receive the signal output by the fifth look-up table, and the second input end is coupled to the output end of the sixth look-up table for receiving the signal output by the sixth look-up table; The fourth multiplexer and the fifth multiplexer are both controlled by a second signal; wherein the input end of the first register is coupled to the output end of the fifth multiplexer for storing the The signal output by the fifth multiplexer. The bit decoder further includes a third adder, a fourth adder and a second comparison module coupled in series, and the second comparison module is configured to output the second signal.
第1圖是決定多位元的位元解碼器(bin decoder)的視訊處理系統10之示意圖。視訊處理系統10包含一視訊源11、一視訊處理器12和一視訊顯示器13。視訊源11可以是已利用H.264/AVC標準進行壓縮及/或編碼的重製或傳輸的視訊訊號，其中H.264/AVC標準是採用全文自適應二進制算術編碼(context-based adaptive binary arithmetic coding,CABAC)技術進行壓縮及/或編碼。視訊源11輸出H.264/AVC訊號至視訊處理器12進行解碼和重組成原始視訊訊號，完成後再藉由視訊處理器12輸出至視訊顯示器13以供使用者觀看。Figure 1 is a schematic diagram of a video processing system 10 that determines a multi-bit bin decoder. The video processing system 10 includes a video source 11, a video processor 12, and a video display 13. The video source 11 may be a reproduced or transmitted video signal that has been compressed and/or encoded using the H.264/AVC standard, wherein the H.264/AVC standard uses context-based adaptive binary arithmetic coding (context-based adaptive binary arithmetic coding). The coding, CABAC) technique performs compression and/or coding. The video source 11 outputs the H.264/AVC signal to the video processor 12 for decoding and reconstitution of the original video signal, and then outputs the video signal to the video display 13 for viewing by the user.
視訊處理器12可包含一處理器、一解碼器20和一記憶體。該處理器用以控制視訊處理器12的操作；解碼器20用以對傳來的視訊訊號進行解碼；記憶體用以暫存視訊訊號、用以儲存在解碼過程中所使用的資料及/或查閱表，以及用以當作工作區，除此之外，記憶體也用作匯流區和視訊處理器12中不同部分的聯結。另外，解碼器20可包含一或多個暫存器25、40，一決定位元解碼器(decision bin decoder) 35，以及一旁路位元解碼器(bypass bin decoder) 30。The video processor 12 can include a processor, a decoder 20, and a memory. The processor is configured to control the operation of the video processor 12; the decoder 20 is configured to decode the transmitted video signal; the memory is used to temporarily store the video signal, to store the data used in the decoding process, and/or to view The table is used as a work area, and in addition, the memory is also used as a junction between the sink area and different parts of the video processor 12. Additionally, decoder 20 may include one or more registers 25, 40, a decision bin decoder 35, and a bypass bin decoder 30.
第2圖是視訊處理系統10的每時脈處理一個位元(bin-per-cycle)的位元解碼器100。位元解碼器100可包含一偏移暫存器101，一範圍暫存器102，一狀態指數暫存器103，一參考最不可能狀態(reference least probable state,rLPS)查閱表104，一最不可能狀態(least probable state,LPS)查閱表105，一最可能狀態(most probable state,MPS)查閱表106，多個加法器108、109，多個多工器107、110、111、112，一比較模組113，一重新規化模組114，一狀態指數暫存器115，一範圍暫存器116，一偏移暫存器117，和一輸入位元流118。儲存於偏移暫存器101、範圍暫存器102和狀態指數暫存器103的資訊可由第1圖的解碼器20的暫存器25的輸出端輸入，或是在一些實施例中，偏移暫存器101、範圍暫存器102和狀態指數暫存器103是第1圖的暫存器35的部份成份。2 is a bit-per-cycle bit decoder 100 that processes a clock per clock of the video processing system 10. The bit decoder 100 can include an offset register 101, a range register 102, a state index register 103, and a reference least probable state (rLPS) lookup table 104, one of the most A less probable state (LPS) lookup table 105, a most probable state (MPS) lookup table 106, a plurality of adders 108, 109, and a plurality of multiplexers 107, 110, 111, 112, A comparison module 113, a re-regulation module 114, a state index register 115, a range register 116, an offset register 117, and an input bit stream 118. The information stored in the offset register 101, the range register 102, and the status index register 103 can be input from the output of the register 25 of the decoder 20 of FIG. 1, or in some embodiments, The shift register 101, the range register 102, and the status index register 103 are partial components of the register 35 of Fig. 1.
rLPS查閱表104的輸入端、MPS查閱表106的輸入端及LPS查閱表105的輸入端耦接於狀態指數暫存器103的輸出端，狀態指數暫存器103的輸出端輸出目前的全文狀態(context state)，而目前的全文狀態可用來從rLPS查閱表104、MPS查閱表106、LPS查閱表105擷取適當的值。MPS查閱表106的輸出端耦接於多工器112的第一輸入端，LPS查閱表105的輸出端耦接於多工器112的第二輸入端，而多工器112的第一輸入端用以接收MPS查閱表106輸出的最可能狀態，多工器112的第二輸入端用以接收LPS查閱表105輸出的最不可能狀態。多工器107的輸入端耦接於rLPS查閱表104的輸出端，多工器107的控制輸入端耦接於範圍暫存器102的輸出端，多工器107的輸入端用以接收rLPS查閱表104所輸出的可能的參考狀態，多工器107的控制輸入端用以接收範圍暫存器102輸出的訊號，而範圍暫存器102輸出的訊號用以控制多工器107。多工器107的輸出端耦接於加法器108的第一輸入端和多工器110的第一輸入端，加法器108的第二輸入端耦接於範圍暫存器102的輸出端。在加法器108中，加法器108的第二輸入端所接收之範圍暫存器102輸出的訊號將扣除來自加法器108的第一輸入端所接收之多工器107的輸出的訊號。加法器108的輸出端耦接於多工器110的第二輸入端及加法器109的第一輸入端，加法器109的第二輸入端耦接於偏移暫存器101的輸出端。在加法器109中，加法器109的第二輸入端所接收之偏移暫存器101輸出的訊號將扣除來自加法器109的第一輸入端所接收之加法器108的輸出的訊號。多工器111的第一輸入端耦接於偏移暫存器101的輸出端，多工器111的第二輸入端耦接於加法器109的輸出端，多工器111的第一輸入端用以接收偏移暫存器101輸出的訊號，多工器111的第二輸入端用以接收加法器109輸出的差值。The input end of the rLPS lookup table 104, the input end of the MPS lookup table 106, and the input end of the LPS lookup table 105 are coupled to the output of the state index register 103, and the output of the state index register 103 outputs the current full text state. (context state), and the current full text state can be used to retrieve appropriate values from the rLPS lookup table 104, the MPS lookup table 106, and the LPS lookup table 105. The output end of the MPS look-up table 106 is coupled to the first input end of the multiplexer 112. The output end of the LPS look-up table 105 is coupled to the second input end of the multiplexer 112, and the first input end of the multiplexer 112. To receive the most probable state of the output of the MPS lookup table 106, the second input of the multiplexer 112 is used to receive the least likely state of the output of the LPS lookup table 105. The input end of the multiplexer 107 is coupled to the output end of the rLPS look-up table 104. The control input end of the multiplexer 107 is coupled to the output end of the range register 102, and the input end of the multiplexer 107 is configured to receive the rLPS lookup. The possible reference states output by the table 104 are used by the control input of the multiplexer 107 for receiving the signal output by the range register 102, and the signal output by the range register 102 is used to control the multiplexer 107. The output of the multiplexer 107 is coupled to the first input of the adder 108 and the first input of the multiplexer 110, and the second input of the adder 108 is coupled to the output of the range register 102. In adder 108, the signal output by range register 102 received by the second input of adder 108 will subtract the signal from the output of multiplexer 107 received by the first input of adder 108. The output of the adder 108 is coupled to the second input of the multiplexer 110 and the first input of the adder 109. The second input of the adder 109 is coupled to the output of the offset register 101. In adder 109, the signal output by offset register 101 received by the second input of adder 109 will subtract the signal from the output of adder 108 received by the first input of adder 109. The first input end of the multiplexer 111 is coupled to the output end of the offset register 101, and the second input end of the multiplexer 111 is coupled to the output end of the adder 109, and the first input end of the multiplexer 111 For receiving the signal output by the offset register 101, the second input of the multiplexer 111 is configured to receive the difference output by the adder 109.
另外，加法器109的輸出端也耦接於比較模組113的輸入端，而比較模組113的輸出端耦接於多工器111、110和112的控制輸入端。比較模組113用以接收加法器109輸出的差值，並判斷加法器109的差值輸出是否小於零。而比較模組113輸出的判斷結果係用以控制多工器111、110和112。此外，多工器112的輸出端耦接於狀態指數暫存器115的輸入端，多工器112輸出的訊號用以更新狀態指數暫存器115。In addition, the output of the adder 109 is also coupled to the input of the comparator module 113, and the output of the comparator 113 is coupled to the control inputs of the multiplexers 111, 110, and 112. The comparison module 113 is configured to receive the difference output by the adder 109 and determine whether the difference output of the adder 109 is less than zero. The judgment result output by the comparison module 113 is used to control the multiplexers 111, 110, and 112. In addition, the output of the multiplexer 112 is coupled to the input of the state index register 115, and the signal output by the multiplexer 112 is used to update the state index register 115.
重新規化模組114的第一輸入端用以接收輸入位元流118，重新規化模組114的第二輸入端耦接於多工器111的輸出端，用以接收多工器111輸出的訊號，重新規化模組114的第三輸入端耦接於多工器110的輸出端，用以接收多工器110輸出的訊號，重新規化模組114的第一輸出端耦接於偏移暫存器117的輸入端，重新規化模組114的第二輸入端耦接於範圍暫存器116的輸入端，其中重新規化模組114輸出的訊號係用以輪流更新偏移暫存器117和範圍暫存器116。偏移暫存器117輸出更新值119和範圍暫存器116輸出更新值120。其中更新值119、更新值120將和更新的狀態指數暫存器115同時使用在下一次解碼循環中。The first input end of the re-regulation module 114 is configured to receive the input bit stream 118, and the second input end of the re-regulation module 114 is coupled to the output end of the multiplexer 111 for receiving the output of the multiplexer 111. The third input end of the re-regulation module 114 is coupled to the output end of the multiplexer 110 for receiving the signal output by the multiplexer 110. The first output end of the re-regulation module 114 is coupled to the signal. The input end of the re-synchronization module 117 is coupled to the input end of the range register 116, wherein the signal output by the re-regulation module 114 is used to update the offset in turn. The register 117 and the range register 116. The offset register 117 outputs an update value 119 and the range register 116 outputs an update value 120. The updated value 119, the updated value 120 will be used simultaneously with the updated status index register 115 in the next decoding cycle.
第3圖的位元解碼器300係為第2圖的位元解碼器100包含關鍵路徑的示意圖。在第3圖中，位元解碼器300說明每時脈處理一個位元(bin-per-cycle)的位元解碼器的關鍵路徑(critical path)如何成為一個設計議題。如第3圖所示，每時脈處理一個位元(bin-per-cycle)的位元解碼器300的關鍵路徑從狀態指數暫存器103的輸出端開始經rLPS查閱表104、多工器107、加法器108、加法器109、比較模組113、多工器111、重新規化模組114而至偏移暫存器117。多工器107的控制輸入端所接收之範圍暫存器102輸出的訊號係用以決定rLPS查閱表104之輸出的多個訊號中哪一個訊號需經由多工器107傳遞至加法器108。在加法器108中，加法器108的第二輸入端所接收之範圍暫存器102輸出的訊號將扣除來自加法器108的第一輸入端所接收之多工器107所輸出的訊號。在加法器109中，加法器109的第二輸入端所接收之偏移暫存器101輸出的訊號將扣除來自加法器109的第一輸入端所接收之加法器108的輸出的訊號。比較模組113的輸入端係用以接收加法器109輸出的差值，而比較模組113的判斷結果則用以控制多工器111。多工器111輸出的訊號提供給重新規化模組114用以更新偏移暫存器117，由偏移暫存器117輸出的更新值119將用在下一次解碼循環中。因此，第3圖的位元解碼器300的關鍵路徑結束於偏移暫存器117的輸出端。然而，每時脈處理一個位元(bin-per-cycle)的位元解碼器300的處理能力是不足以高到能用以即時解碼H.264/AVC視訊，特別是在處理高解析度影像時，位元解碼器300的處理能力更顯不足。The bit decoder 300 of Fig. 3 is a schematic diagram in which the bit decoder 100 of Fig. 2 includes a critical path. In Fig. 3, bit decoder 300 illustrates how a critical path of a bin-per-cycle bit decoder per clock processing becomes a design issue. As shown in FIG. 3, the key path of the bin-per-cycle bit decoder 300 is processed from the output of the state index register 103 via the rLPS look-up table 104, multiplexer. 107, adder 108, adder 109, comparison module 113, multiplexer 111, re-regulation module 114 to offset register 117. The signal output by the range register 102 received by the control input of the multiplexer 107 is used to determine which of the plurality of signals of the output of the rLPS look-up table 104 is to be passed to the adder 108 via the multiplexer 107. In the adder 108, the signal output by the range register 102 received by the second input of the adder 108 subtracts the signal output from the multiplexer 107 received from the first input of the adder 108. In adder 109, the signal output by offset register 101 received by the second input of adder 109 will subtract the signal from the output of adder 108 received by the first input of adder 109. The input end of the comparison module 113 is for receiving the difference output by the adder 109, and the judgment result of the comparison module 113 is used to control the multiplexer 111. The signal output from the multiplexer 111 is supplied to the rescaling module 114 for updating the offset register 117, and the updated value 119 output by the offset register 117 is used in the next decoding cycle. Therefore, the critical path of the bit decoder 300 of FIG. 3 ends at the output of the offset register 117. However, the processing capability of the bin-per-cycle bit decoder 300 per clock is not high enough to be able to decode H.264/AVC video in real time, especially in processing high resolution images. At the time, the processing capability of the bit decoder 300 is even more insufficient.
為了增加處理能力，如第4圖所示的每時脈處理二個位元的位元解碼器400除了可被用來每時脈解碼一個位元，亦可每時脈解碼二個位元。第4圖係本發明的一實施例所揭露之每時脈處理二個位元的位元解碼器400的示意圖。位元解碼器400包含一暫存器405、一第一決定位元解碼器407、二多工器415、409及一第二決定位元解碼器420。暫存器405耦接於第一決定位元解碼器407和多工器409。第一決定位元解碼器407耦接於多工器415、多工器409及第二決定位元解碼器420。第一決定位元解碼器407的輸出端輸出Offset1、Range1和伴隨更新狀態的RLPS1訊號，其中Offset1和Range1由第二決定位元解碼器420接收，但RLPS訊號則伴隨著外部的CTX2 RLPS/CTX2 State訊號輸入至多工器415。多工器415受一Source select訊號所控制並輸出選擇結果至第二決定位元解碼器420。第二決定位元解碼器420的輸出端輸出訊號Offset2、Range2、RLPS2和NextST，其中第二決定位元解碼器420輸出的訊號Offset2、Range2、RLPS2和NextST會與來自第一決定位元解碼器407的RLPS1訊號一併輸入多工器409。多工器409輸出的訊號則回傳到暫存器405，因此可開始另一循環。In order to increase the processing power, the bit decoder 400 which processes two bits per clock as shown in Fig. 4 can decode two bits per clock, in addition to being used to decode one bit per clock. FIG. 4 is a schematic diagram of a bit decoder 400 for processing two bits per clock according to an embodiment of the present invention. The bit decoder 400 includes a register 405, a first decision bit decoder 407, two multiplexers 415, 409, and a second decision bit decoder 420. The register 405 is coupled to the first decision bit decoder 407 and the multiplexer 409. The first decision bit decoder 407 is coupled to the multiplexer 415, the multiplexer 409, and the second decision bit decoder 420. The output of the first decision bit decoder 407 outputs Offset1, Range1 and the RLPS1 signal accompanying the update state, wherein Offset1 and Range1 are received by the second decision bit decoder 420, but the RLPS signal is accompanied by the external CTX2 RLPS/CTX2. The State signal is input to the multiplexer 415. The multiplexer 415 is controlled by a Source select signal and outputs the selection result to the second decision bit decoder 420. The output of the second decision bit decoder 420 outputs signals Offset2, Range2, RLPS2 and NextST, wherein the signals Offset2, Range2, RLPS2 and NextST output by the second decision bit decoder 420 are associated with the decoder from the first decision bit. The RLPS1 signal of 407 is input to the multiplexer 409. The signal output by multiplexer 409 is passed back to register 405 so that another cycle can begin.
雖然，對於H.264/AVC標準的高解析度視訊，每時脈處理二個位元的位元解碼器具有可以接受的處理能力，但是其關鍵路徑依舊是設計的議題，但經過重新安排解碼流程以及移動查閱表到前一級的方式可有效縮短每時脈處理二個位元的位元解碼器的關鍵路徑。根據第5圖的架構可實現每時脈處理二個位元的位元解碼器。Although for the high-resolution video of the H.264/AVC standard, a bit decoder that processes two bits per clock has acceptable processing power, its critical path is still a design issue, but is rearranged and decoded. The flow and the way the mobile lookup table goes to the previous level can effectively shorten the critical path of the bit decoder that processes two bits per clock. According to the architecture of Figure 5, a bit decoder that processes two bits per clock can be implemented.
請參照第5圖及第6圖。第5圖說明第一決定位元解碼器500，第6圖說明第二決定位元解碼器600，以及第一決定位元解碼器500和第二決定位元解碼器600之間的連結關係。在第5圖中，第一決定位元解碼器500包含一偏移暫存器501、一範圍暫存器502、一rLPS暫存器550、一狀態指數暫存器503、一MPS狀態查閱表506、一LPS狀態查閱表505、一第一rLPS查閱表552、一第二rLPS查閱表555、多工器515-519、加法器508-509、一狀態指數暫存器530、一比較模組513及一重新規化模組514。在第6圖中，第二決定位元解碼器600包含多個多工器610、616、623、618、620、621、622，一重新規化模組635，多個加法器641、643，一rLPS查閱表652，一MPS狀態查閱表612，一LPS狀態查閱表611，一第一rLPS查閱表614，一第二rLPS查閱表613，及一比較模組630。MPS狀態查閱表506的輸入端和LPS狀態查閱表505的輸入端耦接於狀態指數暫存器503的輸出端，MPS狀態查閱表506和LPS狀態查閱表505用以接收狀態指數暫存器503輸出的目前狀態。第一rLPS查閱表552的輸入端和多工器515的第一輸入端耦接於MPS狀態查閱表506的輸出端，用以接收MPS狀態查閱表506所選擇的最可能狀態。多工器516的第一輸入端耦接於第一rLPS查閱表552的輸出端，用以接收第一rLPS查閱表552輸出的一32位元訊號。第二rLPS查閱表555的輸入端和多工器515的第二輸入端耦接於LPS狀態查閱表505的輸出端，用以接收LPS狀態查閱表505所選擇的最不可能狀態，多工器516的第二輸入端耦接於第二rLPS查閱表555的輸出端，用以接收第二rLPS查閱表555輸出的一32位元訊號。Please refer to Figure 5 and Figure 6. Fig. 5 illustrates a first decision bit decoder 500, and Fig. 6 illustrates a second decision bit decoder 600, and a connection relationship between the first decision bit decoder 500 and the second decision bit decoder 600. In FIG. 5, the first decision bit decoder 500 includes an offset register 501, a range register 502, an rLPS register 550, a state index register 503, and an MPS status lookup table. 506, an LPS status lookup table 505, a first rLPS lookup table 552, a second rLPS lookup table 555, a multiplexer 515-519, an adder 508-509, a state index register 530, a comparison module 513 and a re-regulation module 514. In FIG. 6, the second decision bit decoder 600 includes a plurality of multiplexers 610, 616, 623, 618, 620, 621, 622, a re-regulation module 635, and a plurality of adders 641, 643, one. The rLPS lookup table 652, an MPS status lookup table 612, an LPS status lookup table 611, a first rLPS lookup table 614, a second rLPS lookup table 613, and a comparison module 630. The input of the MPS state lookup table 506 and the input of the LPS state lookup table 505 are coupled to the output of the state index register 503, and the MPS state lookup table 506 and the LPS state lookup table 505 are used to receive the state index register 503. The current state of the output. The input of the first rLPS lookup table 552 and the first input of the multiplexer 515 are coupled to the output of the MPS status lookup table 506 for receiving the most probable state selected by the MPS status lookup table 506. The first input end of the multiplexer 516 is coupled to the output of the first rLPS lookup table 552 for receiving a 32-bit signal output by the first rLPS lookup table 552. The input end of the second rLPS lookup table 555 and the second input end of the multiplexer 515 are coupled to the output of the LPS status lookup table 505 for receiving the least likely state selected by the LPS status lookup table 505, the multiplexer The second input end of the 516 is coupled to the output of the second rLPS lookup table 555 for receiving a 32-bit signal output by the second rLPS lookup table 555.
加法器508的第一輸入端和多工器517的第一輸入端耦接於rLPS暫存器550的輸出端，加法器508的第二輸入端耦接於範圍暫存器502的輸出端，多工器517的第一輸入端和加法器508的第一輸入端係用以接收rLPS暫存器550輸出的訊號，加法器508的第二輸入端係用以接收範圍暫存器502輸出的訊號。在加法器508中，範圍暫存器502輸出的訊號將扣除來自rLPS暫存器550輸出的訊號，加法器508的輸出端耦接於多工器517的第二輸入端和加法器509的第二輸入端，加法器509的第二輸入端及多工器517的第二輸入端用以接收加法器508輸出的訊號。偏移暫存器501的輸出端耦接於加法器509的第一輸入端和多工器518的第一輸入端，而多工器518的第一輸入端和加法器509的第一輸入端係用以接收偏移暫存器501輸出的訊號。在加法器509中，偏移暫存器501輸出的訊號將扣除來自加法器508輸出的訊號。多工器518的第二輸入端耦接於加法器509的輸出端，用以接收加法器509輸出的差值。加法器509的輸出端也耦接於比較模組513的輸入端，比較模組513的輸入端係用以接收加法器509輸出的差值，而比較模組513判斷加法器509的差值輸出是否小於零。比較模組513的輸出端耦接於多工器518、517、516和515的控制輸入端，其中比較模組113的判斷結果係用以控制多工器518、517、516和515。The first input end of the adder 508 and the first input end of the multiplexer 517 are coupled to the output end of the rLPS register 550, and the second input end of the adder 508 is coupled to the output end of the range register 502. The first input of the multiplexer 517 and the first input of the adder 508 are configured to receive the signal output by the rLPS register 550, and the second input of the adder 508 is configured to receive the output of the range register 502. Signal. In the adder 508, the signal output from the range register 502 will be deducted from the signal output from the rLPS register 550. The output of the adder 508 is coupled to the second input of the multiplexer 517 and the adder 509. The second input terminal of the adder 509 and the second input terminal of the multiplexer 517 are configured to receive the signal output by the adder 508. The output of the offset register 501 is coupled to the first input of the adder 509 and the first input of the multiplexer 518, and the first input of the multiplexer 518 and the first input of the adder 509 It is used to receive the signal output by the offset register 501. In the adder 509, the signal output from the offset register 501 will subtract the signal output from the adder 508. The second input end of the multiplexer 518 is coupled to the output of the adder 509 for receiving the difference output by the adder 509. The output of the adder 509 is also coupled to the input of the comparison module 513. The input of the comparison module 513 is used to receive the difference output by the adder 509, and the comparison module 513 determines the difference output of the adder 509. Whether it is less than zero. The output of the comparison module 513 is coupled to the control inputs of the multiplexers 518, 517, 516, and 515, wherein the determination result of the comparison module 113 is used to control the multiplexers 518, 517, 516, and 515.
另外，多工器515的輸出端耦接於狀態指數暫存器530的輸入端，多工器515輸出的訊號用以更新狀態指數暫存器530。狀態指數暫存器530可輪流輸出更新的狀態至第二決定位元解碼器600的多工器610的第一輸入端(如第6圖所示)。同樣地，多工器519的第一輸入端耦接於多工器516的輸出端，多工器519的第二輸入端耦接於另一rLPS查閱表，多工器519接收來自多工器516和另一rLPS查閱表輸出的訊號後，將輸出一32位元訊號至第二決定位元解碼器600的多工器616的第一輸入端。重新規化模組514的第一輸入端用以接收輸入位元流520，第二輸入端用以接收多工器518輸出的訊號，第三輸入端用以接收多工器517輸出的訊號，然後多工器623的第一輸入端和加法器641的第一輸入端接收重新規化模組514的第一輸出端輸出的偏移訊號，加法器643的第二輸入端接收重新規化模組514的第二輸出端輸出的範圍訊號，重新規化模組635接收重新規化模組514的第三輸出端輸出的移位位元流(shifted bitstream)，以及多工器618的控制輸入端接收重新規化模組514的第二輸出端輸出的範圍訊號中的2最高有效位元(Most Significant Bit,MSB)做為其控制訊號(如第6圖所示)。In addition, the output of the multiplexer 515 is coupled to the input of the state index register 530, and the signal output by the multiplexer 515 is used to update the state index register 530. The state index register 530 can alternately output the updated state to the first input of the multiplexer 610 of the second decision bit decoder 600 (as shown in FIG. 6). Similarly, the first input end of the multiplexer 519 is coupled to the output end of the multiplexer 516, the second input end of the multiplexer 519 is coupled to another rLPS lookup table, and the multiplexer 519 receives the input from the multiplexer. After the signal output by the 516 and another rLPS lookup table, a 32-bit signal is output to the first input of the multiplexer 616 of the second decision bit decoder 600. The first input end of the re-regulation module 514 is configured to receive the input bit stream 520, the second input end is configured to receive the signal output by the multiplexer 518, and the third input end is configured to receive the signal output by the multiplexer 517. Then, the first input end of the multiplexer 623 and the first input end of the adder 641 receive the offset signal outputted by the first output end of the renormalization module 514, and the second input end of the adder 643 receives the renormalization mode. The range signal outputted by the second output of the group 514, the recalibration module 635 receives the shifted bitstream output by the third output of the renormalization module 514, and the control input of the multiplexer 618 The 2 most significant bit (MSB) of the range signal outputted by the second output end of the receiving re-regulation module 514 is used as its control signal (as shown in FIG. 6).
多工器610的第二輸入端和rLPS查閱表652的輸入端接收一StateIndex2訊號。多工器616的第二輸入端耦接於rLPS查閱表652的輸出端，用以接收rLPS查閱表652輸出的訊號(多工器616的第一輸入端耦接於多工器519，用以接收來自多工器519輸出的rLPS訊號)。多工器610和多工器616的控制輸入端則接收一Stage2_Source_Sel訊號，而Stage2_Source_Sel訊號係用來做為多工器610和多工器616的控制訊號。The second input of multiplexer 610 and the input of rLPS lookup table 652 receive a StateIndex2 signal. The second input end of the multiplexer 616 is coupled to the output of the rLPS lookup table 652 for receiving the signal output by the rLPS lookup table 652. The first input end of the multiplexer 616 is coupled to the multiplexer 519 for Receiving the rLPS signal from the output of the multiplexer 519). The control inputs of multiplexer 610 and multiplexer 616 receive a Stage2_Source_Sel signal, and the Stage2_Source_Sel signal is used as a control signal for multiplexer 610 and multiplexer 616.
MPS狀態查閱表612的輸入端和LPS狀態查閱表611的輸入端耦接於多工器610的輸出端，用以接收多工器610輸出的訊號。第一rLPS查閱表614的輸入端和多工器620的第一輸入端耦接於MPS狀態查閱表612的輸出端，用以接收MPS狀態查閱表612所選擇的最可能狀態。多工器621的第一輸入端耦接於第一rLPS查閱表614的輸出端，用以接收第一rLPS查閱表614輸出的一32位元訊號。第二rLPS查閱表613的輸入端和多工器620的第二輸入端耦接於LPS狀態查閱表611的輸出端，用以接收LPS狀態查閱表611所選擇的最不可能狀態。多工器621的第二輸入端耦接於第二rLPS查閱表613的輸出端，用以接收第二rLPS查閱表613輸出的32位元訊號。The input end of the MPS status look-up table 612 and the input end of the LPS status look-up table 611 are coupled to the output end of the multiplexer 610 for receiving the signal output by the multiplexer 610. The input of the first rLPS lookup table 614 and the first input of the multiplexer 620 are coupled to the output of the MPS state lookup table 612 for receiving the most probable state selected by the MPS state lookup table 612. The first input end of the multiplexer 621 is coupled to the output of the first rLPS lookup table 614 for receiving a 32-bit signal output by the first rLPS lookup table 614. The input of the second rLPS lookup table 613 and the second input of the multiplexer 620 are coupled to the output of the LPS status lookup table 611 for receiving the least likely state selected by the LPS status lookup table 611. The second input end of the multiplexer 621 is coupled to the output of the second rLPS lookup table 613 for receiving the 32-bit signal output by the second rLPS lookup table 613.
多工器618的輸入端耦接於多工器616的輸出端；根據Stage2_Source_Sel訊號的選擇，多工器618會接收多工器616輸出的1組8位元訊號，而多工器618則受到來自重新規化模組514的2最高有效位元訊號所控制，輸出1組8位元訊號至加法器643的第一輸入端和多工器622的第一輸入端。多工器622的第二輸入端以及加法器641的第二輸入端耦接於加法器643的輸出端。在加法器643中，加法器643將來自重新規化模組514輸出的範圍訊號扣除來自多工器618輸出的1組8位元訊號後，輸出差值至多工器622以及加法器641。在加法器641中，加法器641將來自重新規化模組514輸出的偏移訊號扣除來自加法器643輸出的差值訊號。多工器623的第二輸入端耦接於加法器641的輸出端，用以接收加法器641輸出的差值。加法器641的輸出端也耦接於比較模組630的輸入端，比較模組630的輸入端係用以接收加法器641輸出的差值，而比較模組630判斷加法器641的差值輸出是否小於零。比較模組630的輸出端耦接於多工器623、622、621和620的控制輸入端，其中比較模組630的判斷結果係用以控制多工器623、622、621和620。重新規化模組635的第一輸入端用以接收來自第一決定位元解碼器500的重新規化模組514的移位位元流，第二輸入端耦接於多工器623的輸出端，用以接收多工器623輸出的訊號，第三輸入端耦接於多工器622的輸出端，用以接收多工器622輸出的訊號，第一輸出端輸出一偏移訊號至第一決定位元解碼器500的偏移暫存器501和第二輸出端輸出一範圍訊號至第一決定位元解碼器500的範圍暫存器502。而偏移暫存器501和範圍暫存器502將在下一循環使用來自重新規化模組635的偏移訊號和範圍訊號。同樣地，多工器621輸出的訊號送至rLPS暫存器550以及多工器620輸出的訊號送至狀態指數暫存器503，讓第一決定位元解碼器500在下一循環使用。The input end of the multiplexer 618 is coupled to the output of the multiplexer 616; according to the selection of the Stage2_Source_Sel signal, the multiplexer 618 receives a set of 8-bit signals output by the multiplexer 616, and the multiplexer 618 receives Controlled by the 2 most significant bit signals from the renormalization module 514, a set of 8 bit signals is outputted to the first input of the adder 643 and to the first input of the multiplexer 622. The second input of the multiplexer 622 and the second input of the adder 641 are coupled to the output of the adder 643. In the adder 643, the adder 643 subtracts the range of signals output from the renormalization module 514 by a set of 8-bit signals from the output of the multiplexer 618, and outputs a difference to the multiplexer 622 and the adder 641. In the adder 641, the adder 641 subtracts the offset signal output from the adder 643 by the offset signal output from the renormalization module 514. The second input end of the multiplexer 623 is coupled to the output of the adder 641 for receiving the difference output by the adder 641. The output of the adder 641 is also coupled to the input of the comparison module 630, the input of the comparison module 630 is used to receive the difference output by the adder 641, and the comparison module 630 determines the difference output of the adder 641. Whether it is less than zero. The output of the comparison module 630 is coupled to the control inputs of the multiplexers 623, 622, 621, and 620, wherein the determination results of the comparison module 630 are used to control the multiplexers 623, 622, 621, and 620. The first input end of the re-regulation module 635 is configured to receive the shift bit stream from the re-regulation module 514 of the first decision bit decoder 500, and the second input end is coupled to the output of the multiplexer 623. The terminal is coupled to the output of the multiplexer 623, and the third input is coupled to the output of the multiplexer 622 for receiving the signal output by the multiplexer 622, and the first output outputs an offset signal to the first The offset register 501 and the second output of the decision bit decoder 500 output a range signal to the range register 502 of the first decision bit decoder 500. The offset register 501 and the range register 502 will use the offset signal and range signal from the renormalization module 635 in the next cycle. Similarly, the signal output from the multiplexer 621 to the rLPS register 550 and the multiplexer 620 is sent to the status index register 503 for use by the first decision bit decoder 500 in the next cycle.
第7圖和第8圖係說明位元解碼器500和位元解碼器600之間的關鍵路徑。如第7圖和第8圖所示，位元解碼器500和位元解碼器600之間有一關鍵路徑開始從範圍暫存器502的輸出端經加法器508，再由加法器508的輸出端延伸至加法器509，繼續從加法器509的輸出端延伸至比較模組513，其後經多工器517的輸出端，再經由重新規化模組514的輸出端至加法器643，從加法器643的輸出端繼續延伸至加法器641，再接著到比較模組630，最後，由比較模組630輸出的訊號去控制多工器623經由重新規化模組635輸出下一循環所須的偏移訊號。7 and 8 illustrate the critical path between the bit decoder 500 and the bit decoder 600. As shown in Figures 7 and 8, a critical path between the bit decoder 500 and the bit decoder 600 begins with the adder 508 from the output of the range register 502 and the output of the adder 508. Extending to the adder 509, continuing from the output of the adder 509 to the comparison module 513, and then passing through the output of the multiplexer 517, and then through the output of the re-regulation module 514 to the adder 643, from the addition The output of the 643 continues to the adder 641, and then to the comparison module 630. Finally, the signal output by the comparison module 630 controls the multiplexer 623 to output the next cycle via the renormalization module 635. Offset signal.
總結來說，比起傳統設計，每時脈處理二個位元的位元解碼器之關鍵路徑比每時脈處理一個位元的位元解碼器來的長。但本發明提出的重新安排解碼流程以及移動查閱表的方式降低了關鍵路徑的長度。本發明的設計顯示出在時間需求上降低33%。例如，未經本發明改善前，每時脈處理二個位元的位元解碼器的頻率為150MHz(Fujitsu 90nm製程)，但採用本發明所提出的重新安排解碼流程後，每時脈處理二個位元的位元解碼器的頻率可提升至225MHz。In summary, the critical path of a bit decoder that processes two bits per clock is longer than the bit decoder that processes one bit per clock, compared to conventional designs. However, the manner of rescheduling the decoding process and moving the lookup table proposed by the present invention reduces the length of the critical path. The design of the present invention shows a 33% reduction in time requirements. For example, before the improvement of the present invention, the frequency of the bit decoder for processing two bits per clock is 150 MHz (Fujitsu 90 nm process), but after the re-arrangement decoding process proposed by the present invention, two processes are processed per clock. The bit decoder's frequency can be increased to 225MHz.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
10．．．視訊處理系統10. . . Video processing system
11．．．視訊源11. . . Video source
12．．．視訊處理器12. . . Video processor
13．．．視訊顯示器13. . . Video display
20．．．解碼器20. . . decoder
25、40、405．．．暫存器25, 40, 405. . . Register
35．．．決定位元解碼器35. . . Decision bit decoder
30．．．旁路位元解碼器30. . . Bypass bit decoder
100、300、400．．．位元解碼器100, 300, 400. . . Bit decoder
102、116、502．．．範圍暫存器102, 116, 502. . . Range register
103、503、115、530．．．狀態指數暫存器103, 503, 115, 530. . . State index register
104、652．．．rLPS查閱表104, 652. . . rLPS lookup table
105、505、611．．．LPS查閱表105, 505, 611. . . LPS lookup table
106、506、612．．．MPS查閱表106, 506, 612. . . MPS lookup table
107、110、111、112、415、409、515、516、517、518、519、610、616、623、618、620、621、622．．．多工器107, 110, 111, 112, 415, 409, 515, 516, 517, 518, 519, 610, 616, 623, 618, 620, 621, 622. . . Multiplexer
108、109、508、509、641、643．．．加法器108, 109, 508, 509, 641, 643. . . Adder
113、513、630．．．比較模組113, 513, 630. . . Comparison module
114、514、635．．．重新規化模組114, 514, 635. . . Recalibration module
117、501、101．．．偏移暫存器117, 501, 101. . . Offset register
118、520．．．輸入位元流118, 520. . . Input bit stream
119、120．．．更新值119, 120. . . Update value
407、500、700．．．第一決定位元解碼器407, 500, 700. . . First decision bit decoder
420、600、800．．．第二決定位元解碼器420, 600, 800. . . Second decision bit decoder
552、614．．．第一rLPS查閱表552, 614. . . First rLPS lookup table
555、613．．．第二rLPS查閱表555, 613. . . Second rLPS lookup table
550．．．rLPS暫存器550. . . rLPS register
第1圖係視訊處理系統之示意圖。Figure 1 is a schematic diagram of a video processing system.
第2圖係第1圖的視訊處理系統的決定位元解碼器之示意圖。Figure 2 is a schematic diagram of a decision bit decoder of the video processing system of Figure 1.
第3圖係說明第2圖的決定位元解碼器的關鍵路徑。Figure 3 is a diagram showing the critical path of the decision bit decoder of Figure 2.
第4圖係本發明的一實施例所揭露之決定位元解碼器的示意圖。Figure 4 is a schematic diagram of a decision bit decoder disclosed in an embodiment of the present invention.
第5圖和第6圖係說明第4圖的決定位元解碼器的詳細架構。Figures 5 and 6 illustrate the detailed architecture of the decision bit decoder of Figure 4.
第7圖和第8圖係說明第5圖和第6圖的決定位元解碼器的關鍵路徑。Figures 7 and 8 illustrate the critical paths of the decision bit decoders of Figures 5 and 6.
400．．．位元解碼器400. . . Bit decoder
405．．．暫存器405. . . Register
407．．．第一決定位元解碼器407. . . First decision bit decoder
409、415．．．多工器409, 415. . . Multiplexer
420．．．第二決定位元解碼器420. . . Second decision bit decoder
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99107130ATWI396450B (en) | 2010-03-11 | 2010-03-11 | Binary arithmetic decoding device with high operation frequency |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99107130ATWI396450B (en) | 2010-03-11 | 2010-03-11 | Binary arithmetic decoding device with high operation frequency |
| Publication Number | Publication Date |
|---|---|
| TW201132127A TW201132127A (en) | 2011-09-16 |
| TWI396450Btrue TWI396450B (en) | 2013-05-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW99107130ATWI396450B (en) | 2010-03-11 | 2010-03-11 | Binary arithmetic decoding device with high operation frequency |
| Country | Link |
|---|---|
| TW (1) | TWI396450B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6856701B2 (en)* | 2001-09-14 | 2005-02-15 | Nokia Corporation | Method and system for context-based adaptive binary arithmetic coding |
| US20060294174A1 (en)* | 2005-06-27 | 2006-12-28 | Haque Munsi A | Hardware-based CABAC decoder |
| US7262722B1 (en)* | 2006-06-26 | 2007-08-28 | Intel Corporation | Hardware-based CABAC decoder with parallel binary arithmetic decoding |
| US7557740B1 (en)* | 2008-04-18 | 2009-07-07 | Realtek Semiconductor Corp. | Context-based adaptive binary arithmetic coding (CABAC) decoding apparatus and decoding method thereof |
| US7592937B1 (en)* | 2008-06-02 | 2009-09-22 | Mediatek Inc. | CABAC decoding unit and method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6856701B2 (en)* | 2001-09-14 | 2005-02-15 | Nokia Corporation | Method and system for context-based adaptive binary arithmetic coding |
| US20060294174A1 (en)* | 2005-06-27 | 2006-12-28 | Haque Munsi A | Hardware-based CABAC decoder |
| US7262722B1 (en)* | 2006-06-26 | 2007-08-28 | Intel Corporation | Hardware-based CABAC decoder with parallel binary arithmetic decoding |
| US7557740B1 (en)* | 2008-04-18 | 2009-07-07 | Realtek Semiconductor Corp. | Context-based adaptive binary arithmetic coding (CABAC) decoding apparatus and decoding method thereof |
| US7592937B1 (en)* | 2008-06-02 | 2009-09-22 | Mediatek Inc. | CABAC decoding unit and method |
| Publication number | Publication date |
|---|---|
| TW201132127A (en) | 2011-09-16 |
| Publication | Publication Date | Title |
|---|---|---|
| US8306125B2 (en) | 2-bin parallel decoder for advanced video processing | |
| US7710296B2 (en) | N-bin arithmetic coding for context adaptive binary arithmetic coding | |
| CN101600104B (en) | Decoding unit and decoding method of context-adaptive binary arithmetic coding | |
| JP3224164B2 (en) | decoder | |
| KR101240058B1 (en) | Decoding system and method | |
| EP1014589A2 (en) | A variable length codeword decoder | |
| US9001882B2 (en) | System for entropy decoding of H.264 video for real time HDTV applications | |
| US7557740B1 (en) | Context-based adaptive binary arithmetic coding (CABAC) decoding apparatus and decoding method thereof | |
| CN102186075B (en) | An Entropy Encoder and Its Implementation Method | |
| CN1135846C (en) | Variable length decoder and method for decoding two codes per clock cycle | |
| US10264264B2 (en) | Multi-bin decoding systems and methods | |
| CN104378634A (en) | Method for binarizing input symbols and method for generating index values from codewords | |
| CN100440979C (en) | Context-based adaptive two-dimensional variable-length decoding method and device | |
| JPH09191456A (en) | Device and method for decoding encoding bit stream, bit stream supplier and device for variable length decoder | |
| CN101277444A (en) | A device and method for decoding Columbus code | |
| CN103248896A (en) | MQ arithmetic coder | |
| TWI396450B (en) | Binary arithmetic decoding device with high operation frequency | |
| US11431978B2 (en) | Video decoding method and video decoding device for improving decoding efficiency | |
| CN100433560C (en) | Programmable variable length decoder including interface of cpu processor | |
| CN102201815B (en) | Binary operation decoding device with high operation frequency | |
| CN102201816B (en) | Parallel five-bypass-bit full-text adaptive binary arithmetic codec | |
| CN101267559A (en) | General entropy decoding method and device for video decoder | |
| Ong et al. | A high throughput low cost context-based adaptive arithmetic codec for multiple standards | |
| Tsai et al. | Highly efficient cavlc encoder for mpeg-4 avc/h. 264 | |
| US7978102B1 (en) | Multi-bin CABAC decision bin decoder |
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |