1360746 % 九、發明說明： 【發明所屬之技術領域】 本發明涉及一種信號中繼裝置及利用該信號中繼裝 置訪問外部記憶體之方法。 【先前技術】 外部記憶體也稱作輔助記憶體，如軟碟、硬碟、光碟、 u现等，以其谷量大、價格低廉且系統掉電時資料不丟失 之優點被廣泛用於儲存資料。CPU不能像訪問内部記憶體 那樣’直接訪問外部記憶體，外部記憶體要與CPU進行資 料傳輸’必須透過内部記憶體，通常内部記憶體與外部記 憶體進行資料傳輸是透過外部記憶體控制器完成之。 當内部記憶體透過外部記憶體控制器向外部記憶體 ::個讀/寫命令後’必須等到該讀/寫命令完成後，才 =出下-個命令’當需要發送大量命令時，速度緩慢， 邛§己憶體之帶寬未得到充分利用。 【發明内容】 W2 乂上内今’有必要提供—種信號中繼裝置及利用 ===置訪問外部記憶體之方法，用於連接外部記 憶體向外:記，可以處理積體電路晶片中記 部記憶體之存取速度。 /寫命令，提高記憶體對外 控制供一種信號中繼農置，用於連接外部記憶體 對外部儲存器具有讀/寫資料需求之功能模組及 6 存資料之記憶體區塊。 及存取控制器。所述匯流二C裝置包括匯流排仲裁器 組向外部記憶體發出之—=用於接收所述功能模 所述存取控制器輸出所述#寫貧料命令之信號，向 之記憶體位址信號。所述存;述命令信號對應 述匯流排仲裁器輸出之命’用於接收亚儲存所 據接收之命令信號和 2遽及記憶體位址信號，並根 控制器對外部記位址信號透過所述外部記憶體 本發嶋 體之方法。該方法包&下置訪問外部記憶 置連接外部記憶體控制器及積體電言號中繼農 置包括匯流排仲裁器制=片，該信號中繼裂 括-個或多個對外部儲Γ器具;;;;^ 裁器接收所述功_=^塊’（5)利用所述匯流排仲 寫資料命令之===記憶體發出之至少-條讀/ 及與所述命令H對k 2取控制器輸出所述命令信號 4 P 7乜唬對應之記憶體位址信 述存取㈣n純麵存所賴流排 二= 號及記憶體位址信號，並根據接收之命 寫資料操作。己匕體控制益對外部記憶體進行讀/ 相較於習知技術，本發明提供 連接外部記憶體控制器及積體電路晶片，== 裝置對外部記㈣進㈣作可財現純及處理^體= 1360746 達之抵里項/寫命令’提高記憶體對外部記憶體之存取速 度。 【實施方式】 如圖1所不’係本發明信號中繼裝置較佳實施例之應 用環境圖。信號中繼裝置2㈣於透過隨排23將一個或 多個主控設備，如圖i中所示之10:晶片1〇 (圖中僅示出 個）’與外部記憶體控制器3〇建立通訊連接。外部記憶 體控制器3〇透過資料線34連接外部記憶體4〇。 每個1C曰曰片10包括—個或多個功能模組湖。每個 ^月b模la 1GG為-個用於完成—定任務之硬體，並且對外 :儲存器具有讀/寫資料之需求。每個功能模組咖包括一 二憶體區塊用於儲存資料。於其他實施例中，記 ^體區塊m也可以位於功能模组1〇〇之外。 各IC晶片1()之功能模組動透過匯流排23與 艇裝置20相連接。 二述信號中繼裝置2〇包括匯流排仲裁器別及存取 ^益22G。匯流排仲裁器21()及存取控制 迷匯流排23相連接。甘, 町所 器训取得匯流能模組100透過匯流排仲裁 及外部權後，透過存取控制器220 Γ上制窃30向外部記憶體40發送讀寫命令， 進仃資料讀寫操作。 如圖2所示，传pg、έ 之具體結構圖。匯;!=i：r裁器210及存取控制器220 接腳用於完成特定^功! G包括多個接腳’每—個 力月b ’如圖中所示：閃控接腳2；q、 8 1360746 ’傳达命令接腳212、記憶體位址輸出接腳213、記情體寫入 .致能接腳2M、接收資料接腳215、記憶體位址輸入接腳 216、傳送資料接腳217及認可接腳218。存取控制哭2汾 主要包括批量存取狀態機⑵、命令詞FIF〇 ^1360746% Nine, the invention relates to: [Technical Field] The present invention relates to a signal relay device and a method for accessing an external memory using the signal relay device. [Prior Art] External memory, also called auxiliary memory, such as floppy disk, hard disk, optical disk, u-present, etc., is widely used for storage because of its large volume, low price, and no loss of data when the system is powered off. data. The CPU cannot directly access the external memory as if accessing the internal memory, and the external memory must transmit data with the CPU. It must pass through the internal memory. Usually, the internal memory and the external memory are transferred through the external memory controller. It. When the internal memory passes through the external memory controller to the external memory:: After a read/write command, 'you must wait until the read/write command is completed, then = the next command' is slow when you need to send a large number of commands. , 邛§ The bandwidth of the body has not been fully utilized. SUMMARY OF THE INVENTION W2 乂上上今 'necessary to provide a kind of signal relay device and use === to access the external memory method for connecting external memory to the outside: remember, can process the integrated circuit chip The access speed of the memory. /Write command to improve memory external control for a signal relay farm, for connecting external memory to the external memory with read/write data requirements of the function module and 6 memory data block. And access controllers. The sinking two C device includes a bus arbitrator group for sending to the external memory -= for receiving the function mode, the access controller outputs the signal of the # write poor material command, and the memory address signal is sent thereto . The command signal corresponds to the command output of the bus arbitrator for receiving the command signal received by the sub-storage and the memory address signal, and the root controller transmits the external address signal The method of external memory. The method package & access to the external memory is connected to the external memory controller and the integrated circuit relay farm includes a bus arbitrator system = slice, the signal relay splits one or more pairs of external storage The device receives the work _=^ block '(5) uses the bus bar to write data command === at least the memory is issued by the memory / and the command H The k 2 controller outputs the memory address of the command signal 4 P 7 存取 to access (4) n pure surface memory, the second row and the memory address signal, and operates according to the received data.匕 控制 控制 对 对 对 对 对 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部^ Body = 1360746 The arrival of the item / write command 'improves the access speed of the memory to the external memory. [Embodiment] FIG. 1 is a diagram showing an application environment of a preferred embodiment of the signal relay device of the present invention. The signal relay device 2 (4) establishes communication with the external memory controller 3 by one or more master devices, as shown in FIG. i, 10: wafer 1 (shown only in the figure) through the row 23 connection. The external memory controller 3 is connected to the external memory via the data line 34. Each 1C cymbal 10 includes one or more functional module lakes. Each ^ month b modulo la 1GG is a hardware for completing the task, and external: the storage has the need to read/write data. Each functional module includes a two-memory block for storing data. In other embodiments, the body block m may also be located outside the function module 1〇〇. The functional module of each IC chip 1 () is connected to the boat device 20 through the bus bar 23. The second signal relay device 2 includes a bus arbitrator and an access 22G. The bus arbitrator 21 () and the access control sneaker 23 are connected. After the martial arts module 100 obtains the bus arbitrating and external rights, the access controller 220 sends a read/write command to the external memory 40 through the access controller 220 to read and write data. As shown in Fig. 2, the specific structure diagram of pg and έ is transmitted. Sink;!=i:r cutter 210 and access controller 220 pins are used to complete the specific ^ function! G includes multiple pins 'every-force month b' as shown in the figure: flash control pin 2 ;q, 8 1360746 'Communication command pin 212, memory address output pin 213, record body write. Enable pin 2M, receive data pin 215, memory address input pin 216, transfer data connection Foot 217 and approval pin 218. Access Control Cry 2汾 Mainly includes batch access state machine (2), command word FIF〇 ^
FirSt〇Ut，先進先出佇列）222、記憶體位址FIF〇 223、返 回資料FIFO 224及傳送資料FIFO 225。 需要指出的是，圖2中匯流排仲裁器210、存取控制 鲁器220及外部記憶體控制器30之間帶箭頭之連線不僅表示 資料流向’也代表匯流排23。 -批里存取狀態機221用於接收匯流排仲裁器21〇輸出 之讀/寫資料之信號’進行相應分析處理後，發送至向外部 圮憶體控制器30。批量存取狀態機221還用於接收外部記 憶體控制器30返回之信號，並透過匯流排仲裁器21〇發送 至相應之功能模組100。上述4個FIF〇分別為一個儲存相 應指令資訊之記憶體件，各FIF〇中之指令按序執行，先 鲁進入之指令先執行並隱退，然後執行下一條指令。 接下來以向外部記憶體4〇寫資料、讀資料為例具體 忒明匯流排仲裁器210各個接腳及存取控制器22〇具備之 功能。 當功能模組100向匯流排仲裁器210發出對外部記憶 體40進行操作之命令請求後，如從外部記憶體4〇讀資料， 閃控接腳211發送一個準備信號至批量存取狀態機221， 由批量存取狀態機221通知外部記憶體控制器3〇所述功能 模組100將要對外部記憶體4〇進行讀資料操作。寫資料與 9 1360746FirSt〇Ut, FIFO, 222, memory address FIF 223, return data FIFO 224, and transfer data FIFO 225. It should be noted that the line connecting the arrow between the bus arbitrator 210, the access control unit 220 and the external memory controller 30 in Fig. 2 not only indicates that the data flow direction 'also represents the bus bar 23. The batch access state machine 221 is configured to receive the signal of the read/write data outputted by the bus arbitrator 21 ’ and perform corresponding analysis processing, and then transmit it to the external memory controller 30. The batch access state machine 221 is further configured to receive the signal returned by the external memory controller 30 and transmit it to the corresponding function module 100 through the bus arbitrator 21A. The above four FIFs are respectively a memory device for storing corresponding instruction information, and the instructions in each FIF file are executed in order, and the instructions that are first entered are executed first and then retired, and then the next instruction is executed. Next, the data is written to the external memory 4, and the data is read as an example to describe the functions of the respective pins of the bus arbitrator 210 and the access controller 22. After the function module 100 issues a command request to the bus arbitrator 210 to operate the external memory 40, if the data is read from the external memory 4, the flash pin 211 sends a ready signal to the batch access state machine 221 The batch memory state machine 221 notifies the external memory controller 3 that the function module 100 is to perform a data reading operation on the external memory. Write information with 9 1360746
讀資料類似。 傳送命令接腳2U用於向批量存取狀態機22ι輸出向 外部記憶體40進行操作之命令，命令中所包含之資訊包括 操作類型為讀還是寫’命令之數量及儲存相應操作資=之 外部記憶體40之通訊地址。傳送命令接腳212可以一次輪 出 條命令’也可以一次輸出一批命令 例如 set length:·” & “read”表示-次性輸出⑽條讀資料之命 令。批量存取狀態機221接收所述命令後依次將命令儲^ 至命令資料FIFO 222提供給外部記憶體控制器3〇。Reading materials is similar. The transfer command pin 2U is used to output a command to the batch access state machine 22 to operate on the external memory 40, and the information contained in the command includes the operation type of reading or writing 'the number of commands and storing the corresponding operation capital = external The communication address of the memory 40. The transfer command pin 212 can issue a round command at a time 'or output a batch of commands such as set length:·" & "read" to indicate - a sub-output (10) read command. The batch access state machine 221 receives the command. After the command is executed, the command storage FIFO 222 is sequentially supplied to the external memory controller 3A.
記憶體位址輸出接腳213，用於輸出存放資料之記憔 體區塊11〇之位址資訊。例如，當傳送命令接腳212 —次 輸出一個“read”或“write”命令時，記憶體位址輸出^ 腳213輸出addrja]”，表示向記憶體區塊11〇中儲存位 址為“a”之區域寫入資料或從記憶體區塊11()中儲存位 址為“a”之區域讀取資料。當傳送命令接腳212 一次輸出 一批“ read ’’或“ write，，命令時，例如“⑽ length=100 ’’ ，記憶體位址輸出接腳216輸出 addr_[a] ’此時表示的是一個起始位址：第一個命令從 外部記憶體40讀取之資料將要寫入記憶體區塊n〇中儲存 位址為“a”之區域或將要從記憶體區塊11〇中儲存位址 為“a”之區域讀取第一筆資料，該批命令中其他命令對應 之記憶體區塊110中之儲存位址根據該起始位址確定。批 量存取狀態機221接收到上述位址資訊後，將其儲存至記 憶體位址FIFO 223。 1360746 ' 當功能模組10〇向外部記憶體40請求之操作為讀資 • 料時’批量存取狀悲機221根據命令資料fifq 222申儲存 之命令資訊透過外部記憶體控制器30從外部記憶體4〇依 次讀取資料，並將讀取之資料依次儲存至返回資料j?IF〇 224。返回資料FIFO 224準備好後，外部記憶體控制器3〇 向批量存取狀態機221發送一個控制信號，通知批量存取 狀態機221外部記憶體控制器30已準備好向記憶體區塊 110寫資料。 •鲁 批量存取狀態機221，還用於接收外部記憶體控制器 30回復之控制信號，並且當該控制信號為準備好向記憶體 區塊110寫資料時’發送一個通知信號至記憶體寫入致能 接腳214。 記憶體寫入致能接腳214’用於接收批量存取狀態機 221發送之通知信號。 接收^'料接腳215 ’用於接收返回資料fif〇 224中儲 % 存之資料。當記憶體寫入致能接腳214接收到批量存取狀 態機221發送之通知信號後，記憶體位址輪入接腳216根 據記憶體位址FIFO 223中儲存之記憶體位址資訊將返回 資料FIFO 224中儲存之資料寫入記憶體區塊11()中相應之 儲存區域。 虽δ己憶體寫入致能接腳214未接收到所述通知信號 時’匯流排仲裁器21〇默認為外部記憶體控制器30要對記 憶體區塊110進行讀資料操作。 δ己憶體位址輪入接腳216，還用於當記憶體寫入致能 11 1360746 接腳214未接收到所述通知信號時，根據記憶體位址FIFO 223中儲存之記憶體位址資訊從記憶體區塊110中相應儲 存區域讀取資料。 傳送資料接腳217用於將記憶體位址輸入接腳216從 記憶體區塊110中相應儲存區域讀取之資料依次儲存至傳 送資料FIFO 225。之後，批量存取狀態機221根據命令資 料FIFO 222中儲存之向外部記憶體40寫資料之命令依次 將傳送資料FIFO 225中儲存之資料透過外部記憶體控制 器30寫入外部記憶體40之相應位址空間。 認可接腳218用於接收批量存取狀態機221輸出之完 成讀/寫資料操作之回復信號。 以上所述僅為本發明之較佳實施例而已，且已達廣泛 之使用功效，凡其他未脫離本發明所揭示之精神下所完成 之均等變化或修飾，均應包含在下述之申請專利範圍内。 【圖式簡單說明】 圖1係本發明信號中繼裝置較佳實施例之應用環境 圖。 圖2係圖1中信號中繼裝置之模組圖。 【主要元件符號說明】 1C晶片 10 信號中繼裝置 20 匯流排 23 外部記憶體控制器 30 資料線 34 12 1360746The memory address output pin 213 is used for outputting the address information of the data block 11存放 storing the data. For example, when the transfer command pin 212 outputs a "read" or "write" command, the memory address output pin 213 outputs addrja]", indicating that the address is stored in the memory block 11A as "a". The area is written to the data or the data is read from the area stored in the memory block 11() with the address "a". When the transfer command pin 212 outputs a batch of "read '' or "write" commands at a time, For example, "(10) length=100 '', the memory address output pin 216 outputs addr_[a] ' At this time, it represents a start address: the data read by the first command from the external memory 40 is to be written into the memory. The body block n〇 stores the address of the address "a" or the first data to be read from the memory block 11〇 where the address is "a", and the memory corresponding to other commands in the batch command The storage address in body block 110 is determined based on the starting address. After receiving the above address information, the batch access state machine 221 stores it in the memory address FIFO 223. 1360746 'When the function module 10 requests the operation to the external memory 40 as the reading resource, the batch access trajectory 221 stores the command information stored according to the command data fifq 222 from the external memory through the external memory controller 30. The body 4 reads the data in turn, and stores the read data in sequence to the return data j?IF〇224. After the return data FIFO 224 is ready, the external memory controller 3 sends a control signal to the bulk access state machine 221 informing the bulk access state machine 221 that the external memory controller 30 is ready to write to the memory block 110. data. The Lu batch access state machine 221 is further configured to receive a control signal replied by the external memory controller 30, and to send a notification signal to the memory write when the control signal is ready to write data to the memory block 110. The enable pin 214 is inserted. The memory write enable pin 214' is for receiving a notification signal transmitted by the bulk access state machine 221. The receiving material pin 215' is configured to receive the data stored in the return data fif 224. After the memory write enable pin 214 receives the notification signal sent by the batch access state machine 221, the memory address wheel pin 216 returns to the data FIFO 224 according to the memory address information stored in the memory address FIFO 223. The data stored in is written in the corresponding storage area in the memory block 11 (). Although the δ hexadecimal write enable pin 214 does not receive the notification signal, the bus arbitrator 21 〇 defaults to the external memory controller 30 to perform a read data operation on the memory block 110. The δ hexenary address is inserted into the pin 216, and is also used to read from the memory address information stored in the memory address FIFO 223 when the memory write enable 11 1360746 pin 214 does not receive the notification signal. The corresponding storage area in the body block 110 reads the data. The transfer data pin 217 is used to sequentially store the data read from the corresponding storage area of the memory block 110 by the memory address input pin 216 to the transfer data FIFO 225. Then, the batch access state machine 221 sequentially writes the data stored in the transfer data FIFO 225 to the external memory 40 through the external memory controller 30 according to the command to write data to the external memory 40 stored in the command data FIFO 222. Address space. The acknowledge pin 218 is configured to receive a reply signal from the batch access state machine 221 to complete the read/write data operation. The above is only the preferred embodiment of the present invention, and has been used in a wide range of applications. Any other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Inside. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing an application environment of a preferred embodiment of a signal relay device of the present invention. 2 is a block diagram of the signal relay device of FIG. 1. [Main component symbol description] 1C chip 10 Signal relay device 20 Bus bar 23 External memory controller 30 Data line 34 12 1360746
外部記憶體 40 功能模組 100 記憶體區塊 110 匯流排仲裁器 210 存取控制器 220 閃控接腳 211 傳送命令接腳 212 記憶體位址輸出接腳 213 記憶體寫入致能接腳 214 接收貢料接腳 215 記憶體位址輸入接腳 216 傳送資料接腳 217 認可接腳 218 批量存取狀態機 221 命令資料FIFO 222 記憶體位址FIFO 223 返回資料FIFO 224 傳送資料FIFO 225 13External Memory 40 Function Module 100 Memory Block 110 Bus Arbiter 210 Access Controller 220 Flash Control Pin 211 Transfer Command Pin 212 Memory Address Output Pin 213 Memory Write Enable Pin 214 Receive Feed pin 215 Memory address input pin 216 Transfer data pin 217 Approved pin 218 Bulk access state machine 221 Command data FIFO 222 Memory address FIFO 223 Return data FIFO 224 Transfer data FIFO 225 13