TWI314819B - Real number encoding method and apparatus thereof - Google Patents

Description

Translated fromChinese

1314819 七、指定代表圖： (一） 本案指定代表圖為：第（一）圖。 (二） 本代表圖之元件符號簡單說明： 10〜12 :步驟流程。 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式: 九、發明說明： · 【發明所屬之技術領域】 本發明是有關於一種實數編碼方法及其裝置，特別是有關 於一種利用不同實數間之位元關係之實數編碼方法及其裝置。 【先前技術】 目前，電腦的應用已普遍應用於日常生活中，無論是 通訊、資料處理或娛樂，皆帶來極大的便利性。而在此資 訊時代中，經常需要儲存、傳送大量且複雜的數據。然而 傳輸媒介的頻寬不斷在增大，也仍無法應付不斷暴增的資 料量。為了減缓通訊頻道的負荷，便發展出數據的編碼技 術，在維持原資料訊息之條件下，減少此資料所須的儲存 空間。在傳統的編碼/解碼應用中，幾乎是針對整數來進行 編解碼；如果是碰到實數（real number )的編解碼，特別 是浮點數，通常都會將其近似為整數後才進行編解碼，因 而造成數據精確度的降低。尤其是做3D座標運算，若對浮 點數進行編碼而造成資料損耗，則其3D效果便不盡正確。 4 1314819 - 目前，缺少一個有效且簡易的方法或系統來直接對實數進 - 行編碼/解編碼，又不會降低其精確度。因此，亟需提出一 種簡易又具面編碼比的實數編碼/解編碼方法及系統，不但 能減緩通訊頻道的負荷，還能達到即時的通訊目的。 有鑑於習知技藝之各項問題，為了能夠兼顧解決之， 本發明人基於多年從事資料編碼技術之研究開發與諸多實 務經驗，提出一種實數編碼方法及其裝置，以作為改善上述 缺點之實現方式與依據。 • 【發明内容】 有鑑於此，本發明之目的就是在提供一種實數編碼方 法及其裝置，以提高實數之編碼效果且防止其資料損耗。 根據本發明之目的，提出一種實數編碼方法，包含下 列步驟：接收複數個實數，每一該些實數皆由複數個位元所 組成；以及自每一實數中選擇出一符合特定條件之位元，並 對該所選之複數個位元以進行一第一編碼動作，以產生一第 一編碼輸出資料。此特定條件可為每一實數中相同位置之位 元或是此些實數排成一陣列後此陣列同一行之位元。 • 此外，本發明更提出一種實數編碼裝置，其包含一接 收單元、一選擇單元及一第一編碼單元。接收單元用以接收 複數個實數，每一該些實數皆由複數個位元所組成。選擇單 元自每一該些實數中選擇出一符合特定條件之位元，而第一 編碼單元，係對該所選之複數個位元以進行一第一編碼動 作，以產生一第一編碼輸出資料。 此外，本發明所提出之實數編碼裝置更包含一邏輯運算單 元，用以在進行該第一編碼動作之前，對該所選之複數個位元或該 陣列之行之該些位元進行一邏輯運算。 5 1314819 再者，本發明所提出之實數編碼裝置更包含一第二編碼單 元，係用以對選自每一該些實數中複數個由複數個位元所組成 之數字，進行一第二編碼動作，以產生一第二編碼輸出資料。 茲為使貴審查委員對本發明之技術特徵及所達到 之功效有更進一步之瞭解與認識，謹佐以較佳之實施例 及配合詳細之說明如後。 【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之 實數編碼方法及其裝置，為使便於理解，下述實施例中之 相同元件係以相同之符號標示來說明。 請參閱第一圖及第二圖，第一圖繪示本發明之實數編 碼方法之實施例之步驟流程圖，而第二圖繪示第一圖之陣 列之範例示意圖。第一圖中，此方法包含下列步驟： 步驟10 :接收複數個實數21，每一實數21皆由複數個 位元22所組成； 步驟11 :將此些實數21配置成一陣列20，每一實數21係 形成該陣列之一列，該些實數之相同位置之位元係形成該陣列 之一行23 ; 步驟12:選擇陣列20之一行23之位元進行第一編碼動作， 以產生一第一編碼輸出資料。 此外，本發明之方法視需要可在進行該第一編碼動作之 前，對陣列之行之位元進行一邏輯運算。此邏輯運算較佳的是 XOR運算。如第三圖所示，其為陣列20以向下方向31對陣 列20之每一行之位元進行一 XOR運算之結果，接著，再對陣列 30之一行33之位元進行第一編碼動作，以產生一第一編碼輸出 資料。請注意，上述之實施例係以陣列為說明範例，但並 1314819 不以此為限，凡包含自每一實數中選擇出一符合特定條件 之位元，並對該所選之複數個位元以進行第一編碼動作，以 產生此第一編碼輸出資料之方法，皆在此發明之保護範圍。 請參閱第四圖、第五A圖及第五B圖，其繪示本發 明之另一實施例之步驟流程圖及相對應之實數陣列範例 圖。第四圖中，此方法包含下列步驟： 步驟40 :接收複數個實數51，每一實數51皆由複數個 位元52所組成； 步驟41 :將此些實數51配置成一陣列50，每一實數51係 • 形成該陣列之一列，該些實數51之相同位置之位元係形成該 陣列之一行53 ; 步驟42:自每一實數51中選擇出由複數個連續行所組 成之部分54(如第五A圖所示）； 步驟43 :計算此陣列部分54之每一行之複數個位元 所組成之數字55(如第五B圖所示），並對該所選之複數個數 字55以進行一第二編碼動作，以產生一第二編碼輸出資料； 步驟44 :對陣列50中未被選擇之行53之位元進行第一編 碼動作，以產生一第一編碼輸出資料。 ® 此外，此方法更包含在進行該第二編碼動作之前，對 所選之複數個數字55進行一減法運算，藉此以減少編碼資料 量。再者，此方法更包含對每一實數中，未被選擇之位元進 行一第三編碼動作。藉此可提高此編碼方法對不同格式資料 之操作彈性。以第五B圖之陣列50為例，陣列50之第一行 至第四行（位於陣列50左侧）係以同一行之位元進行第一編 碼動作，以產生一第一編碼輸出資料，而第五行至第九行（陣 列部分54)係先計算位元所組成之數字55，再對複數個數字 55進行一第二編碼動作，以產生一第二編碼輸出資料。接 !314819 二笛1每列未被選擇之位元56進行一第三編碼動作，產生 罘二編竭輸出資料。 圖。閱^六圖，其繪示本發明之實數編碼裝置之方塊 61及 > 只數編碼裝置6包含一接收單元60、一選擇單元 63, 第—編碼單元62。接收單元60用以接收複數個實數 選擇时母—實數63皆由複數個位元所組成（如第二圖所示）， 元。61 ΐ自每一實數63中選擇出一符合特定條件之位 編瑪動、為碼單元⑽用以對所選之複數個位元以進行一第一 條件之，L以產生一第一編碼輸出資料64。其中，符合特定 擇單开^兀係為位於每一實數中相同位置之位元。此外，選 列之κ亦可切此些實數配置成一_，每—實數係形成陣 元係形成所示之實數21)，該些實數之相同位置之位 編竭動Hi ’且對該陣列之行之該些位元進行該第一 可根據所接收之二’選擇單元61 別進行編石馬。 式將只數/刀成多個部分，以分 例之方塊圖第^ 二:數編碼裴置之實施 選擇單元71、* 扁:馬袭置7包含一接收單元6。、- 第三編碼單元：弟：=早元72、一第二編碼單元73及- 實數63，選擇單元71去凡6〇接收複數個由位元所組成之 數係形成陣列之_列，如第』f實數63配置成—陣列，每-實 71鐘而丨 列弟五B圖之陣列5〇。接著，潠摆适- 元72，行至第四行（陣列5〇之左側行)傳送至第二編^ 編碼動作，產生-第-編碼輪出資料75 ::關係，進行第-計算，分陣列54之同—列位元所組成之U二擇單元71 個數字55傳送至第二編碼單元73，進 &再對複數 1丁乐一編碼動作， 1314819 生一第二編碼輸出資料76。接著，選擇單元7ι 被選擇之位元56傳送至第三編碼料74，進 2 作，產生一第三編碼輸出資料77。 、‘"、動 例如’若接收之資料為浮點數資料，其包含—符號 s slgn blt)、滅 t# e (exp〇nent)及底數資料旧 (mantissa)’則根據其資料特性，可將符號位元s :編碼單元72，將指數資料e傳送至第二編碼單元 貧料m傳送至第三編碼單元74以進行編碼。 -數 "上f之第一編碼動作、第二編碼動作及第三編碼動作 乂佳的是使用-長度編碼法（run lengthcQding)、__ difference c〇ding)或預測編碼法（predictive ⑻ ，執:丁。此些編碼法之運用皆為熟悉編碼技術領域 ) 知，在此便不再贅述。 卬无、 已上所述僅為舉例性，轉為限制性者。任何未 :本神與範疇’而對其進行之等效修改或變 更，均應包含於後附之申請專利範 乂更 % 【圖式簡單說明】 明之實數編碼方法之實施例之步驟流程圖； 第一圖係為本發明之實數陣列之範例； 為本發明之第二圖所示之陣列經過縱向X0R運算後 實f·_之另—實施例之步驟細 第二H 目縣本細之實數陣列之範例； ϊίίΓ之實數編碼襄置之實施例之方塊圖；以及 第七圖係為本發明之實數編碼襄置之另一實施例之方塊圖。 1314819 【主要元件符號說明】 10〜12 :步驟流程； 20 :陣列； 21 :實數； 22 :位元； 23 :行； 30 :陣列； 31 :方向； 33 :行； 40〜44 :步驟流程； 50 :陣列； 51 :實數； 52 :位元； 53 :行； 54 :陣列部分； 55 :數字； 56 :未被選擇之位元； 6:實數編碼裝置； 60 :接收單元； 61 :選擇單元； 62 :第一編碼單元； 63 :實數； 6 4 :第一編碼輸出貢料； 7:實數編碼裝置； 71 :選擇單元； 72 :第一編碼單元； 73 :第二編碼單元； 7 4 :第二編瑪早元， 7 5 :第一編瑪輸出資料； 76 :第二編碼輸出資料；以及 7 7 :第三編碼輸出賁料。1314819 VII. Designated representative map: (1) The representative representative of the case is: (1). (2) A brief description of the component symbols of this representative figure: 10~12: Step flow. 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: IX. Description of the invention: · Technical field of the invention The present invention relates to a real number encoding method and apparatus thereof, and in particular to a utilization Real number coding method and device for bit relationship between different real numbers. [Prior Art] At present, the application of computers has been widely used in daily life, and it is extremely convenient for communication, data processing or entertainment. In this era of information, it is often necessary to store and transmit large and complex data. However, the bandwidth of transmission media continues to increase, and it is still unable to cope with the ever-increasing amount of data. In order to slow down the load on the communication channel, data coding techniques have been developed to reduce the storage space required for the data while maintaining the original data message. In traditional encoding/decoding applications, encoding and decoding are almost done for integers; if it is a real number codec, especially a floating-point number, it will usually be approximated as an integer before encoding and decoding. This results in a reduction in data accuracy. In particular, when doing 3D coordinate operations, if the floating point number is encoded and the data is lost, the 3D effect is not correct. 4 1314819 - Currently, there is a lack of an efficient and simple method or system to directly encode/decode real numbers without reducing their accuracy. Therefore, it is urgent to propose a simple and face-to-face ratio real coding/decoding method and system, which can not only slow down the load of the communication channel, but also achieve the purpose of instant communication. In view of the problems of the prior art, in order to be able to solve the problem, the inventor has proposed a real number coding method and its device based on the research and development of data coding technology and many practical experiences for many years, as an implementation method for improving the above disadvantages. And basis. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a real coding method and apparatus thereof for improving the coding effect of real numbers and preventing data loss thereof. According to an object of the present invention, a real number encoding method is provided, comprising the steps of: receiving a plurality of real numbers, each of the real numbers being composed of a plurality of bits; and selecting a bit from each real number that meets a specific condition And performing a first encoding operation on the selected plurality of bits to generate a first encoded output data. This particular condition can be a bit in the same position in each real number or a bit in the same row of the array after the real numbers are arranged in an array. In addition, the present invention further provides a real encoding apparatus including a receiving unit, a selecting unit, and a first encoding unit. The receiving unit is configured to receive a plurality of real numbers, each of the real numbers being composed of a plurality of bits. The selecting unit selects a bit that meets a specific condition from each of the real numbers, and the first coding unit performs a first encoding operation on the selected plurality of bits to generate a first encoding output. data. In addition, the real coding apparatus of the present invention further includes a logic operation unit for performing a logic on the selected plurality of bits or the bits of the array row before performing the first encoding operation. Operation. 5 1314819 Furthermore, the real coding apparatus proposed by the present invention further includes a second coding unit for performing a second coding on a plurality of numbers consisting of a plurality of bits selected from each of the real numbers. Action to generate a second encoded output material. For a better understanding of the technical features of the present invention and the efficacies of the present invention, the preferred embodiments and the detailed description are as follows. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the accompanying drawings, and the same reference numerals are used to illustrate the same elements in the following embodiments. Please refer to the first figure and the second figure. The first figure shows the flow chart of the steps of the embodiment of the real number encoding method of the present invention, and the second figure shows the example diagram of the array of the first figure. In the first figure, the method comprises the following steps: Step 10: receiving a plurality of real numbers 21, each real number 21 consisting of a plurality of bits 22; Step 11: Configuring the real numbers 21 into an array 20, each real number The 21 series forms one column of the array, and the bits of the same position of the real numbers form one row 23 of the array; Step 12: Select one of the rows 23 of the array 20 to perform a first encoding operation to generate a first encoded output data. In addition, the method of the present invention can perform a logic operation on the bits of the rows of the array before performing the first encoding operation as needed. This logical operation is preferably an XOR operation. As shown in the third figure, the array 20 performs the XOR operation on the bits of each row of the array 20 in the downward direction 31, and then performs the first encoding operation on the bits of the row 33 of the array 30. To generate a first encoded output data. Please note that the above embodiment is an example of an array, but 1314819 is not limited thereto, and includes a bit selected from each real number that meets a specific condition, and the selected plurality of bits are selected. The method for performing the first encoding operation to generate the first encoded output data is within the scope of the invention. Referring to FIG. 4, FIG. 5A and FIG. 5B, a flow chart of steps of another embodiment of the present invention and a corresponding real array example are shown. In the fourth figure, the method includes the following steps: Step 40: Receive a plurality of real numbers 51, each real number 51 is composed of a plurality of bits 52; Step 41: Configure the real numbers 51 into an array 50, each real number 51 series • forming one column of the array, the bits of the same position of the real number 51 form one row 53 of the array; Step 42: selecting a portion 54 composed of a plurality of consecutive rows from each real number 51 (eg Step 53: Step 43: Calculate the number 55 of the plurality of bits of each row of the array portion 54 (as shown in FIG. 5B), and select the plurality of numbers 55 for the selected number 55. Performing a second encoding operation to generate a second encoded output data; Step 44: performing a first encoding operation on the bits of the unselected row 53 of the array 50 to generate a first encoded output data. In addition, the method further includes performing a subtraction on the selected plurality of numbers 55 prior to performing the second encoding operation, thereby reducing the amount of encoded data. Moreover, the method further includes performing a third encoding operation on the unselected bits in each real number. This can improve the operational flexibility of this encoding method for different format data. Taking the array 50 of the fifth B diagram as an example, the first row to the fourth row of the array 50 (on the left side of the array 50) perform the first encoding operation with the bits of the same row to generate a first encoded output data. The fifth row to the ninth row (array portion 54) first calculate the number 55 composed of the bits, and then perform a second encoding operation on the plurality of numbers 55 to generate a second encoded output data. Connected to !314819 two flutes 1 each column unselected bit 56 performs a third encoding action, resulting in the second output of the output. Figure. Referring to Fig. 6, there is shown a block 61 of the real coding apparatus of the present invention and > the number-only coding apparatus 6 includes a receiving unit 60, a selecting unit 63, and a first encoding unit 62. The receiving unit 60 is configured to receive a plurality of real numbers. The parent-real number 63 is composed of a plurality of bits (as shown in the second figure). 61 ΐ Selecting, from each real number 63, a bit coding that meets a specific condition, and the code unit (10) is used to perform a first condition on the selected plurality of bits, L to generate a first coded output. Information 64. Among them, the specific order opening is the same position in each real number. In addition, the selected κ may also be configured such that the real numbers are configured as a _, each real number forms an array element forming the real number 21), and the bits of the same position of the real numbers are exhausted by Hi 'and the array The first of these bits can be used to perform the first selection according to the received two selection unit 61. The equation will be divided into several parts, and the block diagram of the example will be implemented. The selection unit 71, * flat: the horse striking 7 includes a receiving unit 6. - a third coding unit: brother: = early element 72, a second coding unit 73 and - real number 63, the selection unit 71 to receive a plurality of bits consisting of bits form an array of arrays, such as The _f real number 63 is configured as an array, each of which is 71 clocks and the array of 5 B diagrams is 5 〇. Then, 潠 适 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - The U-selection unit 71 number 55 composed of the same-column bit of the array 54 is sent to the second encoding unit 73, and the second encoding output data 76 is generated by the 131819. Next, the selection unit 7i is transferred to the third coded material 74 by the selected bit 56, and a third encoded output material 77 is generated. , '", for example, if the received data is floating point data, which contains the - symbol s slgn blt), the extinction t# e (exp〇nent) and the base data old (mantissa), according to its data characteristics, The symbol bit s: encoding unit 72 may transmit the index data e to the second encoding unit lean m to be transmitted to the third encoding unit 74 for encoding. -Number" The first encoding action, the second encoding action, and the third encoding action of f are preferably using length-length coding (run lengthcQding), __ difference c〇ding, or predictive coding (predictive (8), Ding. The use of these coding methods is familiar with the field of coding technology. I will not repeat them here.卬无, has been described above for illustrative purposes only, and is restricted. Any equivalent modification or modification of the present invention and the scope of the present invention shall be included in the attached patent application. Further, the following is a flowchart of the steps of the embodiment of the real number encoding method; The first figure is an example of a real array of the present invention; the array shown in the second figure of the present invention is subjected to a vertical X0R operation, and the other steps of the embodiment are fine second H. An example of an array; a block diagram of an embodiment of a real code encoding device; and a seventh block is a block diagram of another embodiment of a real code encoding device of the present invention. 1314819 [Description of main component symbols] 10~12: Step flow; 20: Array; 21: Real number; 22: Bit; 23: Line; 30: Array; 31: Direction; 33: Line; 40~44: Step flow; 50: array; 51: real number; 52: bit; 53: line; 54: array part; 55: number; 56: unselected bit; 6: real coding device; 60: receiving unit; 61: selection unit 62: first coding unit; 63: real number; 6 4: first code output tribute; 7: real coding device; 71: selection unit; 72: first coding unit; 73: second coding unit; The second series is Ma Yuanyuan, 7 5: the first code output data; 76: the second code output data; and 7 7: the third code output data.

Claims (1)

Translated fromChinese

9和月1 q --------- 申請專利範圍： ~~ ' 〜種實數編碼方法，包含下列步驟： 接收複數個實數，每-該些實數皆由複數個位元所組 成；以及 自每—該些貫數中選擇出_符合特定條件之位元 ，並對 二所選之複數個位减進彳亍―第—編碼動作，以產生一第 〜編瑪輸出資料。 ^申請專利細第1項所述之實數編碼方法，其中該符合特 、Γΐ件之位元係為位於每—該些實數中相同位置之位元。 t請專利細第1項所述之實數編碼方法，其中更包含將 3些實數配置成—_，每—該些實數係形成該陣列之-些實狀相同位置之位元係形成該陣列之一行，且 編^輸17料之該些位元進行該第—編碼動作’以產生該第一 項所述之實數編碼方法，其中 之該些位=之_=該算所選之複數個位元 算係為實數編碼方法，其帽邏輯運 ί 所選之複數個數字ΐ元所組成 如申請專利範園第第二6編項==。仃一弟二編瑪動 減法運it—’對該所cm在 1314819 8、 如申請專利範圍第1項或第3項所述之實數編碼方法，其中 該第一編碼動作係使用一長度編碼法（run length coding)、一差值編碼法（difference coding)或預測編碼 法（predictive coding)來執行。 9、 如申請專利範圍第6項所述之實數編碼方法，其中該第二編 碼動作係使用一長度編碼法、一差值編碼法或預測編碼 法。 10、 如申請專利範圍第1項或第3項所述之實數編碼方法， 其中更包含對每一實數中，未被選擇之位元進行一第三編 碼動作，以產生一第三編碼輸出資料。 11、 如申請專利範圍第10項所述之實數編碼方法，其中該第 三編碼動作係使用一長度編碼法、一差值編碼法或預測編 碼法。 12、 如申請專利範圍第6項所述之實數編碼方法，其中更包 含對每一實數中，未被選擇之位元進行一第三編碼動作， 以產生一第三編碼輸出資料。 13、 如申請專利範圍第12項所述之實數編碼方法，其中該第 三編碼動作係使用一長度編碼法、一差值編碼法或預測編籲 碼法。 14、 一種實數編碼裝置，其包含·. 一接收單元，用以接收複數個實數，每一該些實數皆由複 數個位元所組成； 一選擇單元，係自每一該些實數中選擇出一符合特定條件 之位元； 一第一編碼單元，係對該所選之複數個位元以進行一第 一編碼動作，以產生一第一編碼輸出資料。 12 •1314819 、如ΐ請專利範圍第14項所述之實數 f，其中該符 =定條件之位元係為位於每—讀些實= 中相同位置之 、如申請專利範圍第U項所述之實 其中該選 列之-列，該些實數之相同位置 形成該陣列 行’且對該_之行之該些位 動作，以 產生該第一編碼輸出資料。 仃°亥弟 、如申請專利範圍第14項所述之實數編碼裝置’其十更包 :-邏—輯運算單元，用以在進行該第—編石馬動作之前，對該所 =之複數個位元或該陣列之行之該些位元進行一邏輯運 算。 18 睛專利範圍第17項所述之實數編碼裝置，其中該邏 輯運具係為一互斥邏輯運算(X〇R)。 19 中複數偏、弟早凡以對選自每一該些實數 :複數個由碰錄元所組成之數字 作，以產生-第二編碼輸出資料。第-編碼動 申請3細们9顿狀實數編 -、為碼早7G在進行該第二編碼 ，亥苐 個數字進行一減法運算。 ⑴對该所選之複數 預測編碼法。 差值編碼法或 、如申請專利範圍第19項所述之實數 一編碼動作係使用-長度編碼法、-差值’其中該第 碼法。 值、·扁碼法或預測編 15 16 17 20 21 13 22 1314819 23、 如申請專利範圍第14項或第17項所述之實數編碼裝置，·： 其中更包含一第三編碼單元，用以對每一實數中未被選擇之 -位元進行一第三編碼動作。 24、 如申請專利範圍第23項所述之實數編碼裝置，其中該第 三編碼動作係使用一長度編碼法、一差值編碼法或預測編 碼法。 25、 如申請專利範圍第第19項所述之實數編碼裝置，其中更 包含一第三編碼單元，用以對每一實數中未被選擇之位元進 行一第三編碼動作。 26、 如申請專利範圍第25項所述之實數編碼裝置，其中該第® 三編碼動作係使用一長度編碼法、一差值編碼法或預測編 碼法。9 and month 1 q --------- Patent application scope: ~~ ' ~ kind of real number encoding method, including the following steps: Receive a plurality of real numbers, each - the real numbers are composed of a plurality of bits; And selecting, from each of the plurality of bits, a bit that meets a specific condition, and subtracting the plurality of bits selected by the second into a first-encoding operation to generate a first-matrix output data. The real number encoding method described in the first item of the patent application, wherein the bit that conforms to the special item is a bit located at the same position in each of the real numbers. The real number encoding method described in the first item of the patent, wherein the method further comprises: configuring the three real numbers into -_, each of the real numbers forming the array of the real positions at the same position to form the array One row, and the bits of the 17 material are subjected to the first encoding operation to generate the real encoding method of the first item, wherein the bits=== the selected plurality of bits The meta-calculation system is a real number coding method, and the plurality of digital units selected by the cap logic operation is composed of the second and sixth edits of the patent application garden.仃一弟二编马动减法运it-'the cm in 1314819 8. The real coding method as described in claim 1 or 3, wherein the first coding action uses a length coding method (run length coding), a difference coding method or predictive coding is performed. 9. The real number encoding method of claim 6, wherein the second encoding operation uses a length encoding method, a difference encoding method or a predictive encoding method. 10. The real number encoding method according to Item 1 or Item 3 of the patent application, further comprising performing a third encoding operation on the unselected bits in each real number to generate a third encoded output data. . 11. The real number encoding method of claim 10, wherein the third encoding operation uses a length encoding method, a difference encoding method, or a predictive encoding method. 12. The real number encoding method of claim 6, wherein the third encoding operation is performed for each unnumbered bit in each real number to generate a third encoded output data. 13. The real number encoding method of claim 12, wherein the third encoding operation uses a length encoding method, a difference encoding method, or a predictive encoding method. 14. A real number encoding apparatus, comprising: a receiving unit, configured to receive a plurality of real numbers, each of the real numbers being composed of a plurality of bits; a selecting unit, selecting each of the real numbers a bit that meets a specific condition; a first coding unit performs a first encoding operation on the selected plurality of bits to generate a first encoded output data. 12 • 1314819, the real number f as described in item 14 of the patent scope, where the symbol = the conditional element is located at the same position in each of the real = as described in the U of the patent application Wherein the selected column-column, the same position of the real numbers forms the array row' and the bit operations of the row of the _ to generate the first encoded output data.仃°海弟, as in the real number encoding device described in claim 14 of the patent application, the ten-package:-logical-competition unit is used to perform the first-stitching horse action before the plural The bits or the bits of the row of the array perform a logical operation. The real number encoding device according to item 17 of the patent scope, wherein the logic carrier is a mutually exclusive logical operation (X〇R). In the middle of the plural, the younger brother is selected from each of the real numbers: a plurality of numbers consisting of the hitting elements to generate a second encoded output. The first-encoded application 3 is a 9-bit real number--, the code is early 7G, the second code is performed, and the number is subtracted. (1) The predictive coding method for the selected complex number. The difference encoding method or the real number encoding operation described in claim 19 of the patent application system uses a -length coding method, - a difference value, wherein the code method. The value, the flat code method or the prediction code 15 16 17 20 21 13 22 1314819 23, the real number encoding device according to claim 14 or 17, wherein: further comprising a third coding unit for A third encoding action is performed on the unselected bits in each real number. 24. The real encoding apparatus of claim 23, wherein the third encoding operation uses a length encoding method, a difference encoding method, or a predictive encoding method. 25. The real encoding apparatus of claim 19, further comprising a third encoding unit for performing a third encoding operation on the unselected bits in each real number. 26. The real encoding apparatus of claim 25, wherein the third encoding operation uses a length encoding method, a difference encoding method, or a predictive encoding method.1414