TWI247412B - Plasma damage protection circuit - Google Patents

Abstract

A plasma damage protection circuit includes a word line driver circuit with plasma damage protection features. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the word line drivers to the semiconductor substrate. Another plasma-based protection circuit includes a device coupled to multiple word line drivers. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the device to the semiconductor substrate. Thus, these plasma-based protection circuits save space while protecting the integrated circuit from plasma process-based damage.

Description

Translated fromChinese

1247412 九、發明說明： 【發明所屬之技術領域】 、本發明是有關於一種積體電路元件，且特別是有關於一種 避免積體電路在製造過程中遭受電浆損害之元件。 【先前技術】 保護積體電路免於遭受錢損害係許乡從事保護元件間 電路設計者所熱衷之課題。積體電路之製造過程通常包括電聚 處理製程。例如金屬_之baekend處理、光阻剝除(价咖㈣ 以及介電質沉積等都會使用電漿在欲處理之結構表面感應電 何。由電漿感應產生之電荷會破壞元件本身與工作效益有關之 基本結構。例如使用於快閃記憶體之通道介電質以及閘極介電 質就會遭受電漿感應電荷之破壞。另外，使用於N位元記憶體 SONOS (可捕捉電荷捕捉結構不同位置電荷之電荷捕捉記憶元） 以及PHINES之電荷儲存結構特別容易遭受電漿感應製程之破 壞。 電漿感應電荷可以是正電荷或者是負電荷，而電漿感應電 荷的型態不同所造成之積體電路破壞程度也不同。 如第1圖所示，在習知之半導體記憶體積體電路中，每一 個字元線（Word Line)驅動器ιοί包括個別之保護電路，例如是 CMOS電晶體對1〇2。字元線驅動器1〇1在記憶體操作過程中 提供字元線106不同之操作電壓。CMOS電晶體對1〇2包括 PMOS 103及NMOS 105，可將電漿感應電荷傳導至半導體基 板。正電荷係透過PMOS 103來傳導，而負電荷則透過NM〇s 105傳導。字元線驅動器之每一條字元線具有保護電路，例如 是CMOS電晶體對。然而，這種設計方式將佔用大量晶片體積1247412 IX. Description of the Invention: [Technical Field to Be Described] The present invention relates to an integrated circuit component, and more particularly to an element which avoids the plasma damage of the integrated circuit during the manufacturing process. [Prior Art] Protecting integrated circuits from damage by money is a topic that Xuxiang is passionate about among circuit designers. The manufacturing process of the integrated circuit usually includes an electropolymerization process. For example, metal_baekend processing, photoresist stripping (price coffee (4), and dielectric deposition) use plasma to induce electricity on the surface of the structure to be treated. The charge generated by plasma sensing destroys the component itself and is related to work efficiency. The basic structure, for example, the channel dielectric used in the flash memory and the gate dielectric are subject to the destruction of the plasma induced charge. In addition, it is used in the N-bit memory SONOS (capable of capturing different positions of the charge trapping structure). The charge-capturing memory element of charge) and the charge storage structure of PHINES are particularly vulnerable to the destruction of the plasma induction process. The plasma induced charge can be positive or negative, and the integrated circuit caused by the different types of plasma induced charge The degree of damage is also different. As shown in Fig. 1, in the conventional semiconductor memory volume circuit, each Word Line driver ιοί includes an individual protection circuit, such as a CMOS transistor pair 1 〇 2. The line driver 101 provides different operating voltages for the word line 106 during memory operation. The CMOS transistor pair 1 〇 2 includes PMOS 103 and NMOS 1 05, the plasma induced charge can be conducted to the semiconductor substrate. The positive charge is conducted through the PMOS 103, and the negative charge is conducted through the NM 〇s 105. Each word line of the word line driver has a protection circuit, such as a CMOS. Transistor pair. However, this design will take up a lot of wafer volume

TW1488PA 5 1247412 並降低電路密度。因此，這種電漿保護電路設計將有礙於積體 電路尺寸持續小型化之趨勢。 【發明内容】 有鑑於此’本發明的目的就是在提供一種電漿損害保護電 路’用以保護積體電路避免於製造過程中遭受電漿損害。 根據本發明的目的，提出一種積體電路，包括半導體基 板、記憶體陣列、多條字元線以及多個字元線驅動器。記憶體 陣列連接於半導體基板。各字元線連接於記憶體陣列。各字元 線驅動器包括一元件，且在記憶體操作中此元件耦接一電壓到 這些字元線驅動器之至少一字元線。其中當製造中電荷產生於 字元線時，此元件連接至半導體基板，且電荷係由字元線透過 元件傳導至半導體基板。 根據本發明的目的，提出一種積體電路，包括半導體基 板、記憶體陣列、多條字元線、多個字元線驅動器以及一元件。 記憶體陣列連接半導體基板。各字元線連接記憶體陣列。多個 字元線驅動器係連接這些字元線。此元件則連接字元線驅動 器。其中當製造中電荷產生於字元線時，電荷係由這些字元線 透過至少此元件傳導至半導體基板。 根據本發明的目的，提出一種積體電路，包括半導體基 板、記憶體陣列、多條字元線、多個字元線驅動器以及一元件。 記憶體陣列連接半導體基板。各字元線連接記憶體陣列。各字 元線驅動器包括一字元線驅動器元件，於記憶體操作中字元線 驅動器元件搞接一電壓到至少這些字元線驅動器之一字元線， 且字元線驅動器元件連接半導體基板以及其中至少一字元線。 元件則連接這些字元線驅動器。其中當製造中電荷產生於字元 TW1488PA 6 1247412 線時，電荷係由字元線透過至少此元件及字元線驅動器元件其 中之一傳導至半導體基板。 根據本發明的目的，提出一種製造積體電路元件之方法， 包括提供一半導體基板；形成一記憶體陣列，以連接半導體基 板；形成多條字元線，以連接記憶體陣列；形成多個字元線驅 動器’以連接這些字元線，其中各字元線驅動器包括一元件， 且於δ己憶體操作中此元件搞接一電壓到這些字元線驅動器之至 少一字元線；以及當製造中電荷產生於字元線時，將電荷由這 些字元線透過此元件傳導至半導體基板。 根據本發明的目的，提出一種製造積體電路元件之方法， 包括挺供一半導體基板；形成一記憶體陣列，以連接半導體基 板；形成多條字元線，以連接記憶體陣列；形成多個字元線驅 動器’以連接這些字元線；形成一元件，以連接這些字元線驅 .動器，以及當製造中電荷產生於這些字元線時，將電荷由這政 字元線透過至少此元件傳導至半導體基板。 根據本發明的目的，提出一種製造積體電路元件之方法， 包括提供一半導體基板；形成一記憶體陣列，以連接半導體基 板’形成多條字元線’以連接記憶體陣列；形成多個字元線驅 動器’以連接這些字元線’各字元線驅動器包括一字元線驅動 益元件。其中於§己憶體插作中字元線驅動器元件麵接一電壓到 這些子元線驅動恭之至少"子元線，形成一元件，以連接這此 子元線驅動器；當製造中電荷產生於這些字元線時，將電荷由 這些字元線透過至少字元線驅動器元件傳導至半導體基板；以 及當製造中電荷產生於這些字元線時，將電荷由這些字元線驅 動器之各字元線透過至少此元件傳導至半導體基板。 某些實例中每個字元線驅動器包括連接半導體基板及字 TW1488PA 7 1247412 元線之α件，例如是一電晶體。透過此電晶體電荷可由字元 線傳=至半導體基板。藉由使用字元線驅動器之—電晶體，可 有效節省積體電路之使用空間。例如在正常的記憶體操作中， ，晶體將-供應電壓耦接至字元線。電晶體具有某—種電荷型 態’且傳導同—型態之電荷。例如產生於字元線之電洞由字元 線透過字^線驅動器中至少―p型電晶體傳導至半導體基板。 而產生於子元線之電子由字元線透過字元線驅動器中至少—N 型電晶體傳導至半導體基板。其中_實例中電晶體形成於連接 半導體基板之-半導體井中，且電晶體之電流負載端，例如是 源極或汲極，則連接至字元線。 某些實例中，電荷透過兩個字元線驅動器以及連接字元線 驅動器之-元件傳導。某一實例中，同一型態之電透過字元線 驅動器以及連接字元線驅動器之元件來傳導。藉由提供由字元 線至半導體基板之不同傳導電荷路徑，本發明可對積體電路提 供更多的保護，且使用到較少之積體電路空間。在另一實例中， 某-型態電荷透過此元件傳導，而另一型態電荷則透過字元線 驅動器傳導，$而縮小積體電路的使用空間。例如，產生於字 元線之電子透過至少此元件傳導至半導體基板，而產生於字元 $之電洞則透過至少字元線驅動器傳導至半導體基板。在另一 貫例中，產生於字元線之電洞透過至少此元件傳導至半導體基 板，而產生於字元線之電子則透過至少字元線驅動器 ς 導體基板。 千 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下 文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：TW1488PA 5 1247412 and reduce circuit density. Therefore, the design of such a plasma protection circuit will hinder the continued miniaturization of the integrated circuit size. SUMMARY OF THE INVENTION It is an object of the present invention to provide a plasma damage protection circuit for protecting integrated circuits from plasma damage during manufacturing. In accordance with the purpose of the present invention, an integrated circuit is provided that includes a semiconductor substrate, a memory array, a plurality of word lines, and a plurality of word line drivers. The memory array is connected to the semiconductor substrate. Each word line is connected to a memory array. Each word line driver includes an element, and in memory operation the element is coupled to a voltage to at least one word line of the word line drivers. Where the charge is generated in the word line during fabrication, the element is connected to the semiconductor substrate and the charge is conducted by the word line transmission element to the semiconductor substrate. In accordance with the purpose of the present invention, an integrated circuit is provided that includes a semiconductor substrate, a memory array, a plurality of word lines, a plurality of word line drivers, and an element. The memory array is connected to the semiconductor substrate. Each word line is connected to the memory array. Multiple word line drivers connect these word lines. This component is connected to the word line driver. Wherein, when charge is generated in the word line, the charge is conducted by the word lines through at least the element to the semiconductor substrate. In accordance with the purpose of the present invention, an integrated circuit is provided that includes a semiconductor substrate, a memory array, a plurality of word lines, a plurality of word line drivers, and an element. The memory array is connected to the semiconductor substrate. Each word line is connected to the memory array. Each word line driver includes a word line driver component, wherein in the memory operation, the word line driver component engages a voltage to at least one of the word line drivers, and the word line driver component is coupled to the semiconductor substrate and At least one word line. The components are connected to these word line drivers. Wherein the charge is generated during the manufacturing of the word TW1488PA 6 1247412 line, the charge is conducted by the word line through at least one of the element and the word line driver element to the semiconductor substrate. According to an object of the present invention, a method of fabricating an integrated circuit component is provided, comprising: providing a semiconductor substrate; forming a memory array to connect the semiconductor substrate; forming a plurality of word lines to connect the memory array; forming a plurality of words a line driver 'to connect the word lines, wherein each word line driver includes an element, and in the delta memory operation the element engages a voltage to at least one word line of the word line drivers; and When charge is generated in the word line, charge is conducted from the word line through the element to the semiconductor substrate. According to an object of the present invention, a method for fabricating an integrated circuit component is provided, comprising: providing a semiconductor substrate; forming a memory array to connect the semiconductor substrate; forming a plurality of word lines to connect the memory array; forming a plurality of a word line driver 'to connect the word lines; form a component to connect the word line drivers, and to transmit charge from the political word line when the charge is generated in the manufacturing word line This element is conducted to the semiconductor substrate. According to an object of the present invention, a method for fabricating an integrated circuit component is provided, comprising: providing a semiconductor substrate; forming a memory array to connect the semiconductor substrate 'forming a plurality of word lines' to connect the memory array; forming a plurality of words The meta-line driver 'to connect these word lines' each word line driver includes a word line drive benefit element. Wherein the § memory is inserted into the word line driver component to connect a voltage to the sub-line drive to at least the "sub-line, forming a component to connect the sub-line driver; when manufacturing the charge is generated The word lines are electrically conducted from the word lines through the at least word line driver elements to the semiconductor substrate; and when charge is generated in the word lines during manufacture, the charge is transferred from the characters of the word line drivers The wire is conducted to the semiconductor substrate through at least the component. In some instances, each word line driver includes an alpha component that connects the semiconductor substrate to the word TW1488PA 7 1247412, such as a transistor. The charge through this transistor can be transmitted from the word line to the semiconductor substrate. By using a word line driver-transistor, the use space of the integrated circuit can be effectively saved. For example, in normal memory operation, the crystal couples the supply voltage to the word line. The transistor has a certain charge type and conducts the same type of charge. For example, a hole generated in the word line is conducted by the word line to at least the "p-type transistor" in the word line driver to the semiconductor substrate. The electrons generated in the sub-line are transmitted from the word line to the semiconductor substrate through at least the -N type transistor in the word line driver. Wherein the transistor is formed in a semiconductor well connected to a semiconductor substrate, and the current carrying end of the transistor, such as a source or drain, is connected to the word line. In some instances, charge is transmitted through the two word line drivers and the elements connected to the word line drivers. In one example, the same type of electricity is conducted through the word line driver and the elements connected to the word line driver. By providing different conductive charge paths from the word lines to the semiconductor substrate, the present invention provides more protection for the integrated circuit and uses less integrated circuit space. In another example, a certain type of charge is conducted through the element, and another type of charge is conducted through the word line driver, thereby reducing the space used by the integrated circuit. For example, electrons generated in the word line are conducted to the semiconductor substrate through at least the element, and holes generated in the word $ are conducted to the semiconductor substrate through at least the word line driver. In another example, the holes generated in the word lines are conducted to the semiconductor substrate through at least the element, and the electrons generated in the word lines are transmitted through at least the word line driver 导体 conductor substrate. The above described objects, features, and advantages of the present invention will become more apparent and understood.

TW1488PA 8 1247412 【實施方式】 接下來就以實施例來對本發明進行詳細說明。值得注意的 是，所參考之圖式係以簡化的形式呈現而非實際之尺寸。 雖然接下來係參考實施例來揭露本發明，然而當知所描述 之實施例僅是用以舉例說明之目的，不應用以限制本發明。而 接下來以實施例來敘述之詳細說明内容可包括任何之更動與潤 飾以及等效之實施例，此皆落入本發明所定義之專利範圍及精 神中。 請參照第2圖，其繪示依照本發明一較佳實施例具有字元 線的一種電路圖。字元線驅動器201包括兩顆NMOS電晶體220 及240以及一顆PMOS電晶體230。NMOS電晶體220中源極/ 汲極之一端205連接接地參考點250，以作為記憶體操作中電 壓供應之參考點。NMOS電晶體220中源極/汲極之另一端207 則連接至字元線209 〇 NMOS電晶體220之閘極連接至電壓NDIS 261，用以於操 作過程中開啟或關閉NMOS電晶體220。NMOS電晶體220之 P井211於操作過程中連接至電壓WLDRVSS 262。NMOS電晶 體220之N井213則連接至電壓AVX 263，以避免在操作過程 中產生PN接合（junction)效應。 PMOS電晶體230中源極/汲極之一端215連接字元線 209°PMOS電晶體230中源極/汲極之另一端217連接電壓GWL 264以進行例如是程式化、删除及讀取之記憶體操作。PMOS 電晶體230之N井透過導線221連接至NMOS電晶體240之N 井。PMOS電晶體230之閘極則連接電壓PP 265以於記憶體操 作中開啟/關閉PMOS電晶體230。 NMOS電晶體240中源極及汲極之一端223連接PMOS電 TW1488PA 9 1247412 ，晶體230中源極/汲極之一端217。NMOS電晶體240中源極/ 汲極之另一端225連接字元線209。如上所述，NMOS電晶體 240之N井透過導線221連接PMOS電晶體230之N井。NM0S 電晶體240之P井於記憶體操作中耦接電壓WLDRVSS 262。 NMOS電晶體240之閘極連接電壓NP 266，以於記憶體操作過 程中開啟/關閉NMOS電晶體240。 PMOS電晶體103連接每一個字元線驅動器，並將電漿感 應電荷傳導至半導體基板。 在製造過程中，電壓PP 265、NDIS 261以及NP 266為浮 接，因此NMOS電晶體220及240以及PMOS電晶體230之閘 極係為浮接。在製程中，電漿感應電荷由字元線傳導至半導體 基板。負電荷由字元線209透過NMOS電晶體220傳導至半導 體基板。因為在記憶體操作中負電荷係通過作為字元線驅動電 路201部份電路之NMOS電晶體220而不是通過用以保護字元 線驅動器受電漿損害之額外NMOS電晶體105，於是可以節省 大量之積體電路使用空間。正電荷由字元線209透過PMOS電 晶體103傳導至半導體基板。半導體基板係為整個積體電路之 接地參考點250。因此，本發明可避免具有字元線驅動電路之 積體電路遭受具有正負兩種極性之電漿電荷破壞。 當進行例如是讀取、刪除以及程式化之記憶體操作時，字 元線驅動器具有下列之電壓特性。 TW1488PA 10 1247412TW1488PA 8 1247412 [Embodiment] Next, the present invention will be described in detail by way of examples. It is to be noted that the drawings referred to are presented in a simplified form rather than actual dimensions. While the invention has been described with reference to the embodiments thereof, the embodiments of the invention are not intended to limit the invention. The detailed description, which is set forth in the accompanying drawings, and claims Referring to Figure 2, a circuit diagram having word lines in accordance with a preferred embodiment of the present invention is shown. The word line driver 201 includes two NMOS transistors 220 and 240 and a PMOS transistor 230. The source/drain one end 205 of the NMOS transistor 220 is coupled to the ground reference point 250 as a reference point for voltage supply during memory operation. The other end 207 of the source/drain in NMOS transistor 220 is coupled to word line 209. The gate of NMOS transistor 220 is coupled to voltage NDIS 261 for turning NMOS transistor 220 on or off during operation. P well 211 of NMOS transistor 220 is coupled to voltage WLDRVSS 262 during operation. The N well 213 of the NMOS transistor 220 is then coupled to the voltage AVX 263 to avoid a PN junction effect during operation. The source/drain one end 215 of the PMOS transistor 230 is connected to the word line 209. The other end 217 of the source/drain in the PMOS transistor 230 is connected to the voltage GWL 264 for memory such as stylization, deletion and reading. Body operation. The N well of the PMOS transistor 230 is connected to the N well of the NMOS transistor 240 via the wire 221. The gate of the PMOS transistor 230 is connected to the voltage PP 265 to turn on/off the PMOS transistor 230 during the memory gymnastics. The source and drain terminals 223 of the NMOS transistor 240 are connected to a PMOS TW1488PA 9 1247412, one of the source/drain terminals 217 of the crystal 230. The other end 225 of the source/drain in NMOS transistor 240 is connected to word line 209. As described above, the N well of the NMOS transistor 240 is connected to the N well of the PMOS transistor 230 through the wire 221. The P-well of the NM0S transistor 240 is coupled to the voltage WLDRVSS 262 in memory operation. The gate of NMOS transistor 240 is coupled to voltage NP 266 to turn NMOS transistor 240 on/off during memory operation. A PMOS transistor 103 is connected to each of the word line drivers and conducts the plasma inductive charge to the semiconductor substrate. During the manufacturing process, voltages PP 265, NDIS 261, and NP 266 are floating, so the gates of NMOS transistors 220 and 240 and PMOS transistor 230 are floating. In the process, the plasma induced charge is conducted by the word line to the semiconductor substrate. Negative charges are conducted by word line 209 through NMOS transistor 220 to the semiconductor substrate. Since the negative charge passes through the NMOS transistor 220 which is part of the circuit of the word line driver circuit 201 instead of the additional NMOS transistor 105 for protecting the word line driver from plasma damage in the memory operation, a large amount of savings can be achieved. The integrated circuit uses space. Positive charges are conducted by word line 209 through PMOS transistor 103 to the semiconductor substrate. The semiconductor substrate is the ground reference point 250 of the entire integrated circuit. Therefore, the present invention can prevent the integrated circuit having the word line driving circuit from being damaged by the plasma charge having both positive and negative polarities. The word line driver has the following voltage characteristics when performing memory operations such as reading, deleting, and staging. TW1488PA 10 1247412

刪除 程式化 讀取 GWL -4V 10V 2.7V AVX VDD 10V 2.7V PP 0V 0V 0V NDIS -4V 0V 0V NP VDD VDD VDD WLDRVSS -4V 0V 0V WL -4V 10V 2.7V 在刪除模式中，由於NMOS電晶體220之閘極偏壓 NDIS=_4V，因此NMOS電晶體220不導通。 請參照第3圖，其繪示第2圖部份線路剖面圖。NMOS電 晶體220中源極/汲極之一端205連接接地參考點250，作為記 憶體操作過程之供應電壓參作點。NMOS電晶體220中源極/ 汲極之另一端207連接字元線209。NMOS電晶體220係形成 於P井211中。P井211又形成於N井213中，而N井213則 形成於作為接地點250之P型基板。在製造過程中，電漿感應 負電荷係由字元線209透過NMOS電晶體220傳導至作為接地 點250之半導體基板。在字元線209上之電漿感應負電荷造成 字元線209之電壓低於P井211之電壓。而P井211之電壓係 相對於端點205為負值。因此，N+源極/汲極端205及207與P 井211藉由少量之載子注入傳導電流，猶如一顆操作於主動模 式之雙載子接合電晶體（bipolar junction transistor) 〇 請參照第4圖，其繪示依照本發明一較佳實施例包括分別 連接於不同字元線之兩顆字元線驅動器線路圖。字元線驅動器 401及402之線路與第2圖之字元線驅動器201之線路相似。 然而，在第4圖中，字元線209及208係分別連接於電漿保護 NMOS電晶體105A及105B。在製造過程中，電漿感應負電荷 TW1488PA 11 1247412 係由字元線209透過NMOS電晶體105A傳導至作為接地點250 之半導體基板。 在第4圖中，多個字元線驅動器，例如是字元線驅動器401 及402，係同時連接至一顆保護用PMOS電晶體210。PMOS電 晶體210中源極/汲極之一端231連接至導線221之結點235。 PMOS電晶體210中源極/汲極之另一端233連接至作為接地點 250之半導體基板。PMOS電晶體210之閘極連接至PMOS電 晶體210之N井，且PMOS電晶體210之閘極輸入AVX1電壓 以於記憶體操作中關閉PMOS電晶體210。 在製造過程中，電壓AVX1係浮接，因此保護用PMOS電 晶體210之閘極也是浮接的。電漿感應正電荷係由字元線209 透過PMOS電晶體230、導線211以及保護用PMOS電晶體 210，傳導至作為接地點250之半導體基板。而且在記憶體操作 過程中正電荷係通過字元線驅動電路401部份電路，並通過作 為多條字元線電漿保護線路之PMOS電晶體210。因此，相對 於每一個字元線驅動器皆使用額外一顆電漿保護NMOS電晶體 (例如是105A或105B)，本發明之積體電路設計可節省大量之 使用空間。 請參照第5圖，其繪示第4圖部份線路剖面圖。PMOS電 晶體230中源極/汲極之一端連接至字元線209。保護用PMOS 電晶體230中源極/汲極之一端231連接結點235，而結點235 又連接至PMOS電晶體230之N井。PMOS電晶體210中源極/ 汲極之另一端233連接至作為接地點250之半導體基板。在製 造過程中，保護用PMOS電晶體210之閘極係浮接。電漿感應 正電荷係由字元線209透過PMOS電晶體230、導線221及保 護用PMOS電晶體210傳導至作為接地點250之半導體基板。 TW1488PA 12 1247412 字元線209之電漿感應正電荷使得字元線209之電壓高於N井 232之電壓，並導通由P+端234與N井232形成之P-N接合區。 因此，P+端234與N井232便可以二極體方式導通電流。類似 於第3圖之NMOS電晶體220，PMOS電晶體210係透過少數 載子注入傳遞電洞產生電流。在結點235之電漿感應正電荷使 得P+端231之電壓高於N井237,並導通由P+端231與N井 237形成之P-N接合區。而且N井237之電壓相對於P+端233 為正值。因此，P+源極/汲極231及233與N井237猶如操作於 主動模式之雙載子接合電晶體可透過少量載子注入來傳導電 流。 請參照第6圖，其繪示依照本發明較佳實施例連接不同字 元線之兩個字元字元線驅動器線路圖。字元線驅動器601及602 線路類似於第4圖之字元線驅動器401線路。然而在製造過程 中，電漿感應負電荷係由字元線209透過NMOS電晶體220傳 導至半導體基板。因為在記憶體操作中負電荷係通過作為字元 線驅動器電路601之部份電路之NMOS電晶體220，並非通過 用以保護每個字元線驅動器遭電漿損害之額外NMOS電晶體， 因此可節省大量積體電路之使用空間。電漿感應正電荷係由字 元線209透過PMOS電晶體230、導線221及保護用PMOS電 晶體210傳導至作為接地點250之半導體基板。 請參照第7圖繪示具有保護多個字元線驅動器及字元線之 保護裝置740之積體電路部份線路平面圖。多條字元線，例如 是字元線709及710彼此平行排列。這些字元線分別連接至字 元線驅動器線路，例如是字元線驅動器701及702。字元線驅 動器電路形成於半導體井720中。字元線709連接字元線驅動 器701，而字元線710連接字元線驅動器702。第一導電型態之 TW1488PA 13 1247412 ，電漿感應電荷由字元線709及710分別透過字元線驅動器701 及702再經由導線705傳導至基板。 電漿保護裝置740形成於半導體井730中，並透過作為 well pick up之深度摻雜區（deep doped region)711連接至包括字 元線驅動器701及702之每一個字元線驅動器。第二導電型態 之電漿感應電荷由字元線709及710分別透過字元線驅動器701 及702,經由深度摻雜區711及電漿保護裝置740傳導至基板。 在積體電路製造過程中，字元線709及710、字元線驅動 器701及702、深度摻雜區711、電漿保護裝置740以及基板彼 此間之連接係形成於第一金屬連接層之前。積體電路可避免遭 受正或負極性電漿電荷之破壞。 請參照第8圖，其繪示依照本發明較佳實施例積體電路之 簡化方塊圖。積體電路850包括記憶體陣列（array)800，且記憶 體陣列800利用區域性電荷捕捉記憶元來執行。供應電壓808 提供積體電路850所需之電源。列解碼器（raw decoder)/字元線 驅動器801連接記憶體陣列800中呈列狀排列之多個字元線 802。排解碼器803連接至於記憶體陣列800中呈排狀排列之多 條位元線804。位址由匯流排805提供至排解碼器803以及列 解碼器/字元線驅動器801。方塊806之檢測放大器/資料輸入 (sense amplifier/data in)結構透過資料匯流排807連接至排解碼 器803。資料係透過資料輸入線811由積體電路850之輸入/輸 出埠，或積體電路850内部或外部之其它資料源提供給方塊806 之資料輸入結構。資料透過資料輸出線812由方塊806之檢測 放大器提供至積體電路850之輸入/輸出埠或積體電路850内部 或外部之其它資料標的元件。電漿損害保護線路810連接於列 解碼器/字元線驅動器801。 TW1488PA 14 1247412 本發明上述實施例所揭露電漿損害保護電路之優點在於 不同於習知必須於每個字元線驅動器上設置個別之保護用電晶 體’而改為在記憶體操作中由屬於字元線驅動器部份電路之電 晶體來傳導電漿感應產生之電荷，以有效避免積體電路遭受電 漿損害，同時可節省大量積體電路之使用空間。 綜上所述，雖然本發明已以一較佳實施例揭露如上，然其 並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖繪示習知之半導體記憶體積體電路圖。 第2圖繪示依照本發明一較佳實施例具有字元線的一種電 路圖。 第3圖緣示第2圖部份線路剖面圖。 第4圖緣示依照本發明一較佳實施例包括分別連接於不同 字元線之兩顆字元線驅動器線路圖。 第5圖繪示第4圖部份線路剖面圖。 第6圖繪示依照本發明較佳實施例連接不同字元線之兩個 字元字元線驅動器線路圖。 第7圖繪不具有保護多個字元線驅動器及字元線之保護裝 置之積體電路部份線路平面圖。 第8圖緣示依照本發明較佳實施例積體電路之簡化方塊 圖。Delete stylized read GWL -4V 10V 2.7V AVX VDD 10V 2.7V PP 0V 0V 0V NDIS -4V 0V 0V NP VDD VDD VDD WLDRVSS -4V 0V 0V WL -4V 10V 2.7V In the delete mode, due to NMOS transistor 220 The gate bias voltage NDIS=_4V, so the NMOS transistor 220 is not turned on. Please refer to FIG. 3, which is a cross-sectional view of a portion of the circuit in FIG. The source/drain one end 205 of the NMOS transistor 220 is connected to the ground reference point 250 as a supply voltage reference point for the memory operation. The other end 207 of the source/drain in the NMOS transistor 220 is connected to the word line 209. The NMOS transistor 220 is formed in the P well 211. The P well 211 is again formed in the N well 213, and the N well 213 is formed in the P-type substrate as the grounding point 250. During the manufacturing process, the plasma induced negative charge is conducted by word line 209 through NMOS transistor 220 to the semiconductor substrate as ground point 250. The plasma induced negative charge on word line 209 causes the voltage of word line 209 to be lower than the voltage of P well 211. The voltage of the P well 211 is negative relative to the terminal 205. Therefore, the N+ source/汲 terminals 205 and 207 and the P well 211 inject a conduction current by a small amount of carriers, as if a bipolar junction transistor operating in an active mode, please refer to FIG. FIG. 2 illustrates a diagram of two word line driver drivers respectively connected to different word lines in accordance with a preferred embodiment of the present invention. The lines of word line drivers 401 and 402 are similar to the lines of word line driver 201 of FIG. However, in Fig. 4, word lines 209 and 208 are connected to plasma protection NMOS transistors 105A and 105B, respectively. During the manufacturing process, the plasma induced negative charge TW1488PA 11 1247412 is conducted by word line 209 through NMOS transistor 105A to the semiconductor substrate as ground point 250. In Fig. 4, a plurality of word line drivers, such as word line drivers 401 and 402, are simultaneously connected to one protection PMOS transistor 210. The source/drain one end 231 of the PMOS transistor 210 is connected to the junction 235 of the wire 221 . The other end 233 of the source/drain in the PMOS transistor 210 is connected to a semiconductor substrate as a ground point 250. The gate of PMOS transistor 210 is coupled to the N well of PMOS transistor 210, and the gate of PMOS transistor 210 is input to the AVX1 voltage to turn off PMOS transistor 210 during memory operation. During the manufacturing process, the voltage AVX1 is floating, so the gate of the protection PMOS transistor 210 is also floating. The plasma induced positive charge is transmitted from the word line 209 through the PMOS transistor 230, the wire 211, and the protective PMOS transistor 210 to the semiconductor substrate as the ground point 250. Moreover, during memory operation, the positive charge passes through a portion of the circuit of the word line driver circuit 401 and passes through the PMOS transistor 210 which acts as a plurality of word line plasma protection lines. Therefore, an additional plasma protection NMOS transistor (e.g., 105A or 105B) is used with respect to each word line driver, and the integrated circuit design of the present invention can save a lot of space. Please refer to FIG. 5, which is a cross-sectional view of a portion of the circuit in FIG. One of the source/drain terminals of the PMOS transistor 230 is connected to the word line 209. The source/drain one end 231 of the protection PMOS transistor 230 is connected to the node 235, which in turn is connected to the N well of the PMOS transistor 230. The other end 233 of the source/drain in the PMOS transistor 210 is connected to a semiconductor substrate as a ground point 250. During the manufacturing process, the gate of the protection PMOS transistor 210 is floated. The plasma induced positive charge is conducted by the word line 209 through the PMOS transistor 230, the wire 221, and the protective PMOS transistor 210 to the semiconductor substrate as the ground point 250. TW1488PA 12 1247412 The plasma of word line 209 induces a positive charge such that the voltage of word line 209 is higher than the voltage of N well 232 and turns on the P-N junction formed by P+ terminal 234 and N well 232. Therefore, the P+ terminal 234 and the N well 232 can conduct current in a diode manner. Similar to the NMOS transistor 220 of Fig. 3, the PMOS transistor 210 generates a current through a small number of carrier injection transfer holes. The plasma induced positive charge at junction 235 causes the voltage at P+ terminal 231 to be higher than N well 237 and conducts the P-N junction region formed by P+ terminal 231 and N well 237. Moreover, the voltage of the N-well 237 is positive relative to the P+ terminal 233. Thus, the P+ source/drain electrodes 231 and 233 and the N-well 237 act as a bi-carrier bonded transistor operating in an active mode to conduct current through a small amount of carrier injection. Referring to Figure 6, there is shown a circuit diagram of two character word line drivers connecting different word lines in accordance with a preferred embodiment of the present invention. The word line drivers 601 and 602 are similar in line to the word line driver 401 lines of FIG. However, during the manufacturing process, the plasma induced negative charge is conducted by word line 209 through NMOS transistor 220 to the semiconductor substrate. Since the negative charge passes through the NMOS transistor 220, which is a part of the circuit of the word line driver circuit 601, in the memory operation, it does not pass through an additional NMOS transistor for protecting each word line driver from plasma damage. Save a lot of space for the use of integrated circuits. The plasma induced positive charge is conducted by the word line 209 through the PMOS transistor 230, the wire 221, and the protective PMOS transistor 210 to the semiconductor substrate as the ground point 250. Referring to FIG. 7, a plan view of a portion of an integrated circuit having a protection device 740 for protecting a plurality of word line drivers and word lines is shown. A plurality of word lines, for example, word lines 709 and 710 are arranged in parallel with each other. These word lines are connected to word line driver lines, such as word line drivers 701 and 702, respectively. A word line driver circuit is formed in the semiconductor well 720. The word line 709 is connected to the word line driver 701, and the word line 710 is connected to the word line driver 702. The first conductivity type TW1488PA 13 1247412, the plasma induced charge is conducted by the word lines 709 and 710 through the word line drivers 701 and 702 and via the wires 705 to the substrate, respectively. A plasma protection device 740 is formed in the semiconductor well 730 and connected to each of the word line drivers including the word line drivers 701 and 702 through a deep doped region 711 as a well pick up. The plasma induced charge of the second conductivity type is conducted by the word lines 709 and 710 through the word line drivers 701 and 702, respectively, to the substrate via the deep doped region 711 and the plasma protection device 740. In the integrated circuit fabrication process, the word lines 709 and 710, the word line drivers 701 and 702, the deep doped region 711, the plasma protection device 740, and the substrate are connected to each other before the first metal connection layer. The integrated circuit can be protected from damage by positive or negative plasma charges. Referring to Figure 8, a simplified block diagram of an integrated circuit in accordance with a preferred embodiment of the present invention is shown. The integrated circuit 850 includes a memory array 800, and the memory array 800 is implemented using regional charge trapping memory elements. Supply voltage 808 provides the power required by integrated circuit 850. The raw decoder/word line driver 801 is connected to a plurality of word lines 802 arranged in a column in the memory array 800. The row decoder 803 is coupled to a plurality of bit lines 804 arranged in a row in the memory array 800. The address is provided by bus bar 805 to bank decoder 803 and column decoder/word line driver 801. The sense amplifier/data in structure of block 806 is coupled to the bank decoder 803 via data bus 807. The data is supplied to the data input structure of block 806 via the data input line 811 by the input/output port of the integrated circuit 850, or other sources internal or external to the integrated circuit 850. The data is supplied through the data output line 812 from the sense amplifier of block 806 to the input/output of integrated circuit 850 or to other data elements within or external to integrated circuit 850. The plasma damage protection line 810 is coupled to the column decoder/word line driver 801. TW1488PA 14 1247412 The advantage of the plasma damage protection circuit disclosed in the above embodiments of the present invention is that it is different from the prior art that it is necessary to provide an individual protection transistor on each word line driver and instead to belong to the word in the memory operation. The transistor of the partial circuit driver circuit conducts the charge generated by the plasma induction to effectively avoid the plasma damage of the integrated circuit, and at the same time saves a lot of space for the integrated circuit. In view of the above, the present invention has been described above in terms of a preferred embodiment, and is not intended to limit the invention, and various modifications may be made without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a conventional semiconductor memory volume. Figure 2 is a circuit diagram of a word line in accordance with a preferred embodiment of the present invention. Figure 3 is a cross-sectional view of a portion of the line in Figure 2. Figure 4 illustrates a circuit diagram of two word line drivers connected to different word lines, respectively, in accordance with a preferred embodiment of the present invention. Figure 5 is a partial cross-sectional view of the circuit of Figure 4. Figure 6 is a circuit diagram of two character word line drivers connecting different word lines in accordance with a preferred embodiment of the present invention. Fig. 7 is a plan view showing a portion of an integrated circuit portion of a protection device which does not have a plurality of word line drivers and word lines. Figure 8 is a simplified block diagram of an integrated circuit in accordance with a preferred embodiment of the present invention.

TW1488PA 15 1247412 【主要元件符號說明】 101、201、401、402 :字元線驅動器 601、602、701、702 :字元線驅動器 102 : CMOS電晶體對TW1488PA 15 1247412 [Explanation of main component symbols] 101, 201, 401, 402: Word line driver 601, 602, 701, 702: Word line driver 102: CMOS transistor pair

103 ： PMOS 105 ： NMOS 106、208、209、709、710、802 :字元、線 205、215、223、231 :源極/汲極之一端 207、217、225、233 ··源極/汲極之另一端 211 : P 井 213 : N 井 220、240 : NMOS 電晶體 221 :導線 230 : PMOS電晶體 235 :結點 250 :接地參考點103: PMOS 105: NMOS 106, 208, 209, 709, 710, 802: word, line 205, 215, 223, 231: source/drain one end 207, 217, 225, 233 · source/汲The other end of the pole 211: P Well 213: N Well 220, 240: NMOS transistor 221: Wire 230: PMOS transistor 235: Node 250: Ground reference point

261 :電壓 NDIS261: Voltage NDIS

262 :電壓 WLDRVSS262: Voltage WLDRVSS

263 :電壓 AVX263: Voltage AVX

264 :電壓 GWL264: Voltage GWL

265 :電壓PP265: Voltage PP

266 :電壓NP 105A及105B :保護用NMOS電晶體 210 :保護用PMOS電晶體 705 :導線 711 :深度摻雜區 16266: Voltage NP 105A and 105B: Protection NMOS transistor 210: Protection PMOS transistor 705: Conductor 711: Deeply doped region 16

TW1488PA 1247412 720、730 :半導體井 740 :電漿保護裝置 800 :電荷捕捉元陣列 801 :列解碼器/字元線驅動器 803 :排解碼器 804 :位元線 805 :匯流排 806 ··檢測放大器/資料輸入結構 807 :資料匯流排 808 :偏壓設置供應電壓 809 :偏壓設置狀態機構 810 :電漿損害保護裝置 811 :資料輸入線 812 :資料輸出線 850 :積體電路 17TW1488PA 1247412 720, 730: Semiconductor Well 740: Plasma Protection Device 800: Charge Capture Element Array 801: Column Decoder/Word Line Driver 803: Row Decoder 804: Bit Line 805: Bus 806 · · Sense Amplifier / Data input structure 807: data bus 808: bias setting supply voltage 809: bias setting state mechanism 810: plasma damage protection device 811: data input line 812: data output line 850: integrated circuit 17

TW1488PATW1488PA

Claims (1)

Translated fromChinese

1247412 十、申請專利範園·· 1· 一種積體電路，包括·· 一半導體基板； 一記憶體㈣卜連接於料導體基板； 複數條字元線，連接於該記億體陣列；以及 複數個字元線驅動器，各該些字元線驅㈣包括一元件， 八中在δ己憶體操作中，該元件輕 之至少-字元線； # I[到該些字元線驅動器 導體製造巾電荷產纽該料料，Μ件連接至該半 =基板，且該電錢由該字元線透㈣元件傳導至該半導體 連接二 牛導體基板及该子讀之—電晶體，且該電荷錢過電 j之源極及祕間之雙載子電晶體仙，通過該電晶體之源 極及汲極之間區域。 1 3.如中請專利範圍第i項所述之電路，其中該元件係連 接该半導體基板及該字元線之一電晶體。 4·如申明專利圍第1項所述之電路，其中該元件包括 :有第電荷型悲之一電晶體，且具有該第一電荷型態之電 何由該字元線透過至少該電晶體傳導至該半導體基板。 5 ·如申请專利範圍第1項所述之電路，其中該元件包括 一 N型電晶體，連接至該半導體基板及該字元線，且該電荷包 括電子，並由該字元線透過至少該N型電晶體傳導至該半導體 基板。 6·如申請專利範圍第1項所述之電路，其中該元件包括 P型電晶體，連接至該半導體基板及該字元線，且該電荷包 TW1488PA 18 1247412 括電洞’亚由該字元線透過至少該p型電晶體傳導至該半導體 基板。 7·、如中請專利範圍第i項所述之電路，其中該元件包括 於半導體井中之電晶體，該半導體井連接至該半導體基 ，’該：晶體具有一第一電流負載端，用以連接該字元線，電 何由該字元線透過至少該電晶體傳導至該半導體基板，且於記 憶體操作中，該電晶體係耦接一供應電壓至該字元線。 8· 一種積體電路，包括·· 一半導體基板； 一記憶體陣列，連接該半導體基板； 複數條字元線，連接該記憶體陣列； 複數個字元線驅動器，連接該些字元線；以及 一元件’連接該些字元線驅動器； —其中，當製造中電荷產生於該些字元線時，該電荷係由該 些予7G線透過至少該元件傳導至該半導體基板。 9·如申請專利範圍第8項所述之電路，其中該元件係連 接至各該些字元線驅動器之一電晶體，且該電荷係透過至少該 電晶體及該元件傳導至該半導體基板。 10·如申請專利範圍第8項所述之電路，其中該元件係連 接至各該些子元線驅動器之一電晶體，且該電荷係透過至少該 電曰曰體及忒元件傳導至該半導體基板，且於記憶體操作中該電 晶體耗接一供應電壓至該字元線。 11·如申請專利範圍第8項所述之電路，其中各該些字元 線驅動器包括具有一第一電荷型態之一電晶體，用以連接該元 件，該疋件具有一第一電荷型態，且該第一電荷型態之電荷由 該字元線透過至少該電晶體及該元件傳導至該半導體基板。 TW1488PA 19 1247412 12.如申請專利範圍第8項 線驅動器包括一 p型電晶體、 電路、、中各該些字元 p型電晶體，且該電二該元件，該元件係另- 晶體及該元件傳導至該半導體基板並由該字元線透過至少該電 ^如申請專利範@第8項所述之電路，其中㈣些字元 線驅動器包括一 N型電晶I#，田、 一 N…牌 i電曰曰體，用以連接該元件，該元件係另一 曰體及^株^電荷包括電子’並由該字元線透過至少該電 日日體及忒7L件傳導至該半導體基板。 請專利範圍第8項所述之㈣，其中該元件包括 ^一電机負載端’各該些字元線驅動器包括位於—半導體井 2 -電晶體，且該第—電流負載端連接於該電日日日體之該半導體 井，且該電荷係透過至少該電晶體及該元件傳導至該半導體基 15· —種積體電路，包括： 一半導體基板； 一記憶體陣列，連接該半導體基板； 複數條字元線，連接該記憶體陣列； 複數個子元線驅動器，其中各該些字元線驅動器包括一字 元線驅動器元件’於記憶體操作中該字元線驅動器元件麵接一 電壓到至4㈣字π線驅動ϋ之—字元線，且該字元線驅動器 兀件連接該半導體基板以及該些字元線之其中至少一字元線；σ 一元件’連接該些字元線驅動器； 一其中，當製造中電荷產生於該字元線時，該電荷係由該字 元線透過至少該元件及字元線驅動器元件其中之一 導體基板。 TW1488PA 20 1247412 16.如申請專利範圍第15項所述之電路，其中該電荷包 括一第=電荷型態以及一第二電荷型態，具有該第一電荷型態 之該電荷由該字元線透過至少該元件傳導至該半導體基板，且 具有該第二電荷型態之該電荷由該字元線透過至少該字元線驅 動器元件傳導至該半導體基板。 17·如申请專利範圍第15項所述之電路，其中該電荷包 括，洞及電子，該些電洞由該字元線透過至少該元件傳導至該 半導體基板’且該些電子電該字元線透過至少該字元線驅動器 元件傳導至該半導體基板。 18·如申靖專利範圍苐15項所述之電路，其中該電荷包 括電洞及電子，該些電子由該字元線透過至少該元件傳導至該 半導體基板，且該些電洞電該字元線透過至少該字元線驅動器 元件傳導至該半導體基板。 19·如申睛專利範圍第！5項所述之電路，其中該電荷包 括一第一電荷型態，部份之具有該第一電荷型態之該電荷由該 字元線透過至少該元件傳導至該半導體基板，且 部份之具有該第一電荷型態之該電荷由該字元線透過至少該字 元線驅動器元件傳導至該半導體基板。 2〇· —種製造一積體電路元件之方法，包括·· 提供一半導體基板； 形成一記憶體陣列，以連接該半導體基板； 形成複數條字元線，以連接該記憶體陣列； 形成複數個字元線驅動器，以連接該些字元線，其中各該 些字元線驅動器包括一元件，且於記憶體操作中，該元件耦接 一電壓到該些字元線驅動器之至少一字元線；以及 當製造中電荷產生於該字元線時，將電荷由該些字元線透 TW1488PA 21 1247412 過該元件傳導至該半導體基板。 21·如申請專利範圍第2〇項所述之方法，其中傳導電荷 至該半導體基板之該步驟包括一電晶體之源極及汲極間之雙載 子接合電晶體作用。 22·如申請專利範圍第2〇項所述之方法，其中該元件包 括一電晶體。 23·如申請專利範圍第20項所述之方法，其中該元件包 括具有一第一電荷型態之一電晶體，且該具有該第一電荷型態 之該電荷係由該字元線透過至少該電晶體傳導至該半導體基 板0 24·如申請專利範圍第2〇項所述之方法，其中該元件包 括N型電aa體，且該電荷包括電子，並由該字元線透過至少 該N型電晶體傳導至該半導體基板。 25·如申請專利範圍第20項所述之方法，其中該元件包 括一 P型電晶體，且該電荷包括電洞，並由該字域透過至少 該P型電晶體傳導至該半導體基板。 26·如申請專利範圍第2〇項所述之方法，更包括於該半 導體基板中形成-半導體井，其中該元件包括位於該半導體 之一電晶體。 27· —種製造一積體電路元件之方法，包括·· 提供一半導體基板； 形成一記憶體陣列，以連接該半導體基板； 形成複數條字元線，以連接該記憶體陣列； 形成複數個字元線驅動器，以連接該些字元線； 形成一元件，以連接該些字元線驅動器；以及 當製造中電荷產生於該些字元線時，將電荷由該些字元線 TW1488PA 22 1247412 透過至少該元件傳導至該半導體基板。 28.如申請專利範圍第27項所述之方法，其中形成該些 字元線驅動器之該步驟包括於各該些字元線驅動器令形成一電 晶體，該電晶體連接該元件，且該電荷係透過至少該電晶體及 該元件傳導至該半導體基板。 29·如申請專利範圍第27項所述之方法，其中形成該些 字元線驅動器之該步驟包括於各該些字元線驅動器中形成一電 晶體’該電晶體連接該元件’該電荷係、透過至少該電晶體及該 兀件傳導至該半導體基板，且於記憶體操作巾該電晶體搞接一 供應電壓至該字元線。 30·如申請專利範圍第27項所述之方法，其中形成 該些字元線驅動器之該步驟包括於料些字元線驅動器中形成 具有一第一電荷型態之一電晶體，具有該第一電荷型態之該 晶體連接該s件，該元件係具有—第—電荷型態，且具有該第 電荷型恶之该電荷係由該字元線透過至少該電晶體及該元件 傳導至該半導體基板。 31.如申請專利範圍第27項所述之方法，其中形成 該些字元線驅動器之該步驟包括於各該些字元線驅動器中形成 -:型電晶體，該P型電晶體連接該元件，該元件係另一 p型 電晶體’且該電荷包括電洞，並由該字元線透過至少該p型電 晶體及該元件傳導至該半導體基板。 32·如申請專利範圍第27項所述之方法，其中形成 該些字疋線驅動器之該步驟包括於各該些字元線驅動器中形成 -：型電晶體，該N型電晶體連接該元件，該元件係另一 n型 ，晶體，且該電荷包括電子，並由該字元線透過至少該n型電 晶體及該元件傳導至該半導體基板。 TW1488PA 23 1247412 墓二.Γ申請專利範圍第27項所述之方法，更包括於該半 It 成—半導體井，其中形成該些字元線驅動器之該 二"G括於各δ亥些字π線驅動器以及該半導體井中形成一電晶 曾該7G件包括-第_電流負載端用以連接該電晶體之該半 V體井’且該電荷係透過至少該電晶體及該元件傳導 體基板。 f 34_ -種製造一積體電路元件之方法，包括： 提供一半導體基板； 形成-記憶體陣歹，卜以冑接該半導體基板； 形成複數條字元線，以連接該記憶體陣列； -形成複數個字元線驅動器，以連接該些字元線，各該些字 70線驅動器包括-子疋線驅動器元件，其中於記憶體操作中該 字元線驅動器元件_-電壓到該些字域驅動器之至少 元線； 形成一元件，以連接該些字元線驅動器； 、、當製造中電荷產生於該些字元線時，將電荷由該些字元線 透過至少該字元線驅動器元件傳導至該半導體基板；以及 當製造中電荷產生於該些字元線時，將電荷由該些字元線 驅動器之各字元線透過至少該元件傳導至該半導體基板。 35. 如申請專利範圍第34項所述之方法，其中傳導電荷 至該半導體基板之該步驟包括一電晶體之源極及汲極間之雙載 子接合電晶體作用。 36. 如申請專利範圍帛34項所述之方法，其中該電荷包 括一第一電荷型態及一第二電荷型態，具有該第一電荷型態之 该電荷係由該字元線透過至少該元件傳導至該半導體基板，且 具有該第二電荷型態之該電荷係由該字元線透過至少該字元線 TW1488PA 24 1247412 驅動器元件傳導至該半導體基板。 37·如申請專利範圍第34項所述之方法，其中該電荷包 括電子以及電洞，該些電洞係由該字元線透過至少該元件傳導 至該半導體基板，且該些電子係由該字元線透過至少該字元線 驅動器元件傳導至該半導體基板。 38.如申請專利範圍第34項所述之方法，其中該電荷包 括電子以及電洞，該些電子係由該字元線透過至少該元件傳導 至該半導體基板，且該些電洞係由該字元線透過至少該字元線 驅動器元件傳導至該半導體基板。 39·如申請專利範圍第34項所述之方法，其中該電荷包 括-第-電荷型態，部份具有該第—電荷型態之該電荷由該字 元線透過至少該元件傳導至該半導體基板，且部份具有該第二 電荷型態之該電荷由該字元線透過至少該字元線驅動器元件 導至該半導體基板。 TW1488PA 251247412 X. Application for Patent Fan Park··1. An integrated circuit comprising: a semiconductor substrate; a memory (4) connected to the material conductor substrate; a plurality of word lines connected to the array; and a plurality a word line driver, each of the word line drivers (4) comprising a component, in the δ memory operation, the component is at least a word line; # I[to the word line driver conductor manufacturing The charge is connected to the material, the element is connected to the half=substrate, and the electric money is conducted by the word line through (four) element to the semiconductor connected two-conductor substrate and the sub-reading-transistor, and the electric charge Money over the source of the j and the double-carrier transistor of the secret, through the region between the source and the drain of the transistor. The circuit of claim i, wherein the component is connected to the semiconductor substrate and one of the word lines. 4. The circuit of claim 1, wherein the component comprises: a transistor having a first charge type, and wherein the first charge type is electrically transmitted by the word line through at least the transistor Conducted to the semiconductor substrate. 5. The circuit of claim 1, wherein the component comprises an N-type transistor coupled to the semiconductor substrate and the word line, and the charge comprises electrons and is transmitted by the word line at least An N-type transistor is conducted to the semiconductor substrate. 6. The circuit of claim 1, wherein the component comprises a P-type transistor connected to the semiconductor substrate and the word line, and the charge package TW1488PA 18 1247412 includes a hole _ by the character The wire is conducted to the semiconductor substrate through at least the p-type transistor. 7. The circuit of claim i, wherein the component comprises a transistor in a semiconductor well, the semiconductor well being connected to the semiconductor substrate, 'the crystal has a first current load terminal for The word line is connected to the semiconductor substrate through which the word line is transmitted through at least the transistor, and in the memory operation, the transistor system is coupled to a supply voltage to the word line. 8. An integrated circuit comprising: a semiconductor substrate; a memory array connected to the semiconductor substrate; a plurality of word lines connected to the memory array; a plurality of word line drivers connecting the word lines; And an element 'connecting the word line drivers; wherein, when a charge is generated in the word lines, the charge is conducted to the semiconductor substrate through the at least the elements through the predetermined 7G lines. 9. The circuit of claim 8, wherein the component is coupled to one of the plurality of word line drivers, and the charge is transmitted to the semiconductor substrate through at least the transistor and the component. 10. The circuit of claim 8, wherein the component is connected to one of the plurality of sub-line drivers, and the charge is conducted to the semiconductor through at least the electrical and germanium elements The substrate, and in the memory operation, the transistor consumes a supply voltage to the word line. 11. The circuit of claim 8, wherein each of the word line drivers comprises a transistor having a first charge pattern for connecting the element, the element having a first charge type And the charge of the first charge pattern is conducted by the word line through at least the transistor and the element is conducted to the semiconductor substrate. TW1488PA 19 1247412 12. The line driver of claim 8 includes a p-type transistor, a circuit, and a p-type transistor of each of the characters, and the element is a component, the component is another crystal and the The element is conducted to the semiconductor substrate and is transmitted by the word line to at least the circuit of the invention as disclosed in claim 8, wherein the (four) word line drivers comprise an N-type electro-crystal I#, Tian, and N a card i-connected to connect the component, the component is another body and the charge includes an electron 'and is conducted by the word line through at least the electric solar cell and the 7L piece to the semiconductor Substrate. Please refer to (4) of claim 8 , wherein the component includes a motor load end, and each of the word line drivers includes a semiconductor well 2 - a transistor, and the first current load terminal is connected to the electric a semiconductor well of a day and a day, and the charge is transmitted to the semiconductor substrate through at least the transistor and the element, comprising: a semiconductor substrate; a memory array connected to the semiconductor substrate; a plurality of word line lines connected to the memory array; a plurality of sub-line driver, wherein each of the word line drivers includes a word line driver element 'in the memory operation, the word line driver element is connected to a voltage to Up to 4 (four) word π line driving the word line, and the word line driver element is connected to the semiconductor substrate and at least one word line of the word lines; σ a component 'connects the word line drivers And wherein, when a charge is generated in the word line, the charge is transmitted from the word line through at least one of the element and the word line driver element. The circuit of claim 15 wherein the charge comprises a first charge pattern and a second charge pattern, the charge having the first charge pattern being the word line Conducted by the at least the component to the semiconductor substrate, and the charge having the second charge pattern is conducted by the word line through at least the word line driver component to the semiconductor substrate. 17. The circuit of claim 15 wherein the charge comprises a hole and an electron, the holes being conducted by the word line through at least the component to the semiconductor substrate and the electronic characters are A line is conducted to the semiconductor substrate through at least the word line driver component. 18. The circuit of claim 1, wherein the charge comprises a hole and an electron, the electrons being conducted by the word line through at least the component to the semiconductor substrate, and the holes are electrically The line is conducted to the semiconductor substrate through at least the word line driver component. 19·If the scope of the patent application is the first! The circuit of claim 5, wherein the charge comprises a first charge pattern, and a portion of the charge having the first charge pattern is conducted by the word line through at least the component to the semiconductor substrate, and the portion is The charge having the first charge pattern is conducted by the word line to at least the word line driver element to the semiconductor substrate. 2) a method of manufacturing an integrated circuit component, comprising: providing a semiconductor substrate; forming a memory array to connect the semiconductor substrate; forming a plurality of word lines to connect the memory array; forming a plurality a word line driver for connecting the word lines, wherein each of the word line drivers includes an element, and in the memory operation, the element is coupled to a voltage to at least one of the word line drivers a line of light; and when charge is generated in the word line, the charge is conducted from the word line through the element to the semiconductor substrate through TW1488PA 21 1247412. The method of claim 2, wherein the step of conducting a charge to the semiconductor substrate comprises a bipolar junction transistor between a source and a drain of the transistor. The method of claim 2, wherein the component comprises a transistor. The method of claim 20, wherein the element comprises a transistor having a first charge pattern, and the charge having the first charge pattern is transmitted through the word line at least The method of claim 2, wherein the device comprises an N-type electrical aa body, and the charge comprises electrons, and the word line transmits at least the N The type transistor is conducted to the semiconductor substrate. The method of claim 20, wherein the component comprises a P-type transistor, and the charge comprises a hole and is conducted by the word domain to the semiconductor substrate through at least the P-type transistor. 26. The method of claim 2, further comprising forming a semiconductor well in the semiconductor substrate, wherein the component comprises a transistor located in the semiconductor. 27) A method of manufacturing an integrated circuit component, comprising: providing a semiconductor substrate; forming a memory array to connect the semiconductor substrate; forming a plurality of word lines to connect the memory array; forming a plurality of a word line driver for connecting the word lines; forming an element to connect the word line drivers; and charging a charge from the word lines TW1488PA when the manufacturing charge is generated in the word lines 1247412 is conducted to the semiconductor substrate through at least the component. 28. The method of claim 27, wherein the step of forming the word line drivers comprises forming a transistor with each of the word line drivers, the transistor connecting the device, and the charge Conducted through the at least the transistor and the component to the semiconductor substrate. The method of claim 27, wherein the step of forming the word line drivers comprises forming a transistor in each of the word line drivers 'the transistor is connected to the element' And transmitting the voltage to the semiconductor substrate through at least the transistor and the component, and the transistor is connected to the memory cell to supply a voltage to the word line. 30. The method of claim 27, wherein the step of forming the word line drivers comprises forming a transistor having a first charge pattern in the word line drivers, having the a crystal of a charge type connected to the s element, the element having a -first charge type, and the charge having the first charge type is transmitted from the word line through at least the transistor and the element is conducted to the Semiconductor substrate. 31. The method of claim 27, wherein the step of forming the word line drivers comprises forming a -: type transistor in each of the word line drivers, the P-type transistor connecting the element The component is another p-type transistor 'and the charge includes a hole, and the word line passes through at least the p-type transistor and the element is conducted to the semiconductor substrate. 32. The method of claim 27, wherein the step of forming the word line drivers comprises forming a -: type transistor in each of the word line drivers, the N type transistor connecting the element The element is another n-type, crystal, and the charge comprises electrons and is conducted by the word line through at least the n-type transistor and the element is conducted to the semiconductor substrate. TW1488PA 23 1247412 Tomb II. The method described in claim 27, further comprising the semi-It-semiconductor well, wherein the two "G forming the word line drivers are included in each of the characters a π-line driver and an electron crystal formed in the semiconductor well, wherein the 7G device includes a -first current load terminal for connecting the half V body well of the transistor and the charge is transmitted through at least the transistor and the component conductor substrate . f 34_ - A method of manufacturing an integrated circuit component, comprising: providing a semiconductor substrate; forming a memory matrix, to connect the semiconductor substrate; forming a plurality of word lines to connect the memory array; Forming a plurality of word line drivers to connect the word lines, each of the 70 line drivers comprising a sub-pull driver component, wherein the word line driver component _-voltages to the words during memory operation At least a line of the domain driver; forming an element to connect the word line drivers; and, when a charge in the manufacturing is generated in the word lines, transmitting charges from the word lines through at least the word line driver The element is conducted to the semiconductor substrate; and when charge is generated in the word lines during fabrication, charge is transmitted from the word lines of the word line drivers to at least the element to the semiconductor substrate. 35. The method of claim 34, wherein the step of conducting a charge to the semiconductor substrate comprises a bipolar junction transistor between a source and a drain of a transistor. 36. The method of claim 34, wherein the charge comprises a first charge pattern and a second charge pattern, the charge having the first charge pattern being transmitted by the word line at least The element is conducted to the semiconductor substrate, and the charge having the second charge pattern is conducted by the word line to at least the word line TW1488PA 24 1247412 to the semiconductor substrate. 37. The method of claim 34, wherein the charge comprises electrons and holes, the holes being conducted by the word line through at least the element to the semiconductor substrate, and the electrons are A word line is conducted to the semiconductor substrate through at least the word line driver component. 38. The method of claim 34, wherein the charge comprises electrons and holes, the electrons being conducted by the word line through at least the element to the semiconductor substrate, and the holes are A word line is conducted to the semiconductor substrate through at least the word line driver component. 39. The method of claim 34, wherein the charge comprises a -first charge type, and a portion of the charge having the first charge type is conducted by the word line through at least the element to the semiconductor The substrate, and the portion of the charge having the second charge pattern is conducted by the word line to at least the word line driver component to the semiconductor substrate. TW1488PA 25