574746 五、發明說明（2) '一^ - 效能變差’甚至使得金氧半場效應電晶體無法運， 技術之缺失由此可見一般。 發明内容： 鑒於習知技術之缺失，本發明的目的就是在提供一種具 凹陷通道之金氧半場效應電晶體之製造方法，避免發生^ 極與凹陷通道無法對準的問題。 ^ 本發明的另一目的就是在提供一種具凹陷通道之金氧半574746 V. Description of the invention (2) '一 ^-Poor performance' even makes the metal-oxygen half-field effect transistor inoperable, and the lack of technology can be seen from this. SUMMARY OF THE INVENTION In view of the lack of conventional technology, the purpose of the present invention is to provide a method for manufacturing a metal-oxygen half-field effect transistor with a recessed channel to avoid the problem of misalignment of the pole and the recessed channel. ^ Another object of the present invention is to provide a metal-oxygen halide with a recessed channel.
場效應電晶體之製造方法，可以提昇金氧半場效應電晶 之效能。 根據上述目的，本發明提供一種具凹陷通道之金氧 KUC方法，此製造方法先形成一第一犧牲/ 一 土材上方，然後形成一源/汲極於未覆蓋有第 牲層之半導體基材，再形成一第二犧牲層於源/汲極The manufacturing method of the field effect transistor can improve the performance of the metal-oxide half field effect transistor. According to the above object, the present invention provides a metal oxide KUC method with a recessed channel. This manufacturing method first forms a first sacrificial / over a soil material, and then forms a source / drain on a semiconductor substrate not covered with a first layer. , And then form a second sacrificial layer at the source / drain
一 ’移除第一犧牲層與其下方之部分半導體基材以形J 二孔’形成一犧牲間隙壁於開孔側壁，形成一閘極介1 二僅f孔底部:形成一閘極導體層而填滿開孔，移除該jA 'remove the first sacrificial layer and a part of the semiconductor substrate underneath to form a J-hole' to form a sacrificial gap wall on the side wall of the opening to form a gate dielectric 1 2 Only the bottom of the f-hole: forming a gate conductor layer and Fill the opening and remove the j
#兮皇ί i忒犧牲間隙壁，最後，形成一輕摻雜源/汲極 於邊平導體基材。 本發明所製造之金氧半場效應電晶體具有凹陷通道結# 曦 皇 ί i 忒 Sacrifice the spacer, and finally, form a lightly doped source / drain to the side-flat conductor substrate. The metal-oxygen half-field effect transistor manufactured by the present invention has a recessed channel junction
第8頁 574746Page 8 574746
五、發明說明（3) 構，且並不會發生閘極與凹陷通道無法對準的問題 實施方式： 請參照第2A〜2L圖，為繪示本發明製作具凹陷通道之_ 金氧半場效應電晶體之剖面結構流程示意圖。以下將以N 型金氧半場效應電晶體為例，說明本發明技術内容。 首先，如第2A圖所示，先於具有一隔離區21之一半導谱 基材20 ( P型矽）上沉積一蝕刻終止層22與一第一犧牲層V. Description of the invention (3) structure, and the problem of misalignment between the gate electrode and the recessed channel will not occur. Implementation: Please refer to Figures 2A ~ 2L, for the purpose of illustrating the production of the recessed channel of the present invention. Schematic diagram of the cross-section structure of a transistor. The technical content of the present invention will be described below using an N-type metal-oxygen half-field effect transistor as an example. First, as shown in FIG. 2A, an etch stop layer 22 and a first sacrificial layer are deposited on a semiconducting substrate 20 (P-type silicon) having an isolation region 21 first.
I3離ϊ ^ Ξ ΐ區！1可？習知技術形成之淺溝渠隔離區， ^氮i化3 f I為二氧化石夕，而餘刻終止層22之材質巧 矽。 虱化矽，第一犧牲層23之材質可為二氧价 製 然後’第2B圖 程與蝕刻技術 中’再圖案化第一犧牲層2 3，例如以微影 圖案化第一犧牲層。 第2 C圖中，^ 可如習知離二半導體基材2 0形成一源/汲極2 5。其中，I3 away from ϊ Ξ ΐ ΐ! 1 OK? In the shallow trench isolation area formed by the conventional technology, the nitrogen oxide 3 f I is SiO 2, and the material of the termination layer 22 is silicon. In the case of silicon, the material of the first sacrificial layer 23 may be made of dioxygen, and then the first sacrificial layer 23 may be patterned again in the "2B pattern and etching technique", for example, the first sacrificial layer may be patterned by lithography. In FIG. 2C, ^ can form a source / drain electrode 25 from the two semiconductor substrates 20 as is conventionally known. among them,
形成此源/¾托直入24技術摻雜磷或砷於半導體基材20，以 ^ m 2 5 〇 第2D圖中， 、 ^ 上方填入—箸」未被覆蓋有第一犧牲層23之半導體基材20 一犧牲層2 6。例如可如習知技術先沉積第二This source is formed by doping 24 into the semiconductor substrate 20 with doped phosphorous or arsenic, and filled with ^ m 2 50 in the 2D figure, 箸 箸 "semiconductor not covered with the first sacrificial layer 23 Substrate 20-a sacrificial layer 2 6. For example, a second
574746 五、發明說明（4) 犧牲層26，再化學機械研磨第二犧牲層2 6而停止於第一犧 牲層2 3來予以達成。其中，第二犧牲層2 6之材質可為氮化 石夕〇 第2E圖中，移除第一犧牲層23與其下方之蝕刻終止層22 與部分半導體基材2 0，以形成一開孔2 7。其中，可利用蝕 刻技術移除來予以達成，移除部分半導體基材2 〇之多募可 決定凹陷通道之深度。 第2 F圖中，於以 蝕刻終止層2 2與部 化步驟，而於開孔 此一氧化石夕層之厚 之半導體基材2〇表 蝕刻技術移除第一犧 分半導體基材2 0之後 2 7底部形成一二氧化 度為100A。此步驟是 面，因此，此步驟並 牲層2 3與其下方之 ，可再進行一熱氧 石夕層2 8，較佳者， 為了修復經蝕刻後 非絕對必要。574746 V. Description of the invention (4) The sacrificial layer 26 is chemically and mechanically ground to the second sacrificial layer 26 and stopped at the first sacrificial layer 23 to achieve it. Wherein, the material of the second sacrificial layer 26 may be nitride nitride. In FIG. 2E, the first sacrificial layer 23 and the etch stop layer 22 below it and a part of the semiconductor substrate 20 are removed to form an opening 27. . Among them, it can be achieved by using the etching technology removal, and the removal of as much as 20% of the semiconductor substrate can determine the depth of the recessed channel. In FIG. 2F, the etching stop layer 22 and the step of forming the semiconductor substrate 20 with the thickness of the oxide layer in the hole are removed to remove the first semiconductor substrate 20. At the bottom of 2 7 a degree of dioxide of 100A was formed. This step is a surface. Therefore, this step can be performed with a thermal oxygen stone layer 28 next to the layer 2 3 and below. Preferably, it is not absolutely necessary to repair after etching.
底部形I 一网於孔27形成一犧牲間隙壁29，並於開孔 式，可先於:極氧化層3 〇。其中，形成犧牲間隙壁2 9之 -二氧化欲μ 一犧牲層2 6表面與開孔2 7之側邊及底部沉 隙壁29。II，再回蝕刻此二氧化矽層，以形成此犧牲 佳者，閘i ί以熱氧化技術形成此閘極氧化層30，The bottom shape I forms a sacrifice gap wall 29 in the hole 27, and in the opening type, it can precede the polar oxide layer 30. Among them, the sacrificial spacer wall 29 is formed, and the sacrifice layer 26 is formed on the surface of the sacrificial layer 26 and the side and bottom of the opening hole 27. II, and then etch back the silicon dioxide layer to form the sacrificer, and the gate i is formed by the thermal oxidation technology to form the gate oxide layer 30,
閘極氧化層3〇之厚度為ι2〜7〇α。 第2 Η圖中， 由一離子植 於開孔27中形成一閘 入技術摻雜磷或砷於 經 極導體層31，接著，再 閘極導體層31中。其The thickness of the gate oxide layer 30 is ι2˜70α. In the second figure, a gate technique is doped with an ion implanted in the opening 27 to dope phosphorus or arsenic into the conductor conductor layer 31, and then the gate conductor layer 31. its
第10頁 574746Page 10 574746
中，形成閘極導體層3丨之方式，可先於第 與？孔27中沉積-多晶石夕| (未顯示於圖 此夕晶矽層而停止於第二犧牲層26。 二犧牲層2 6表面 中），再回蝕刻 第2 I圖中’以姓刻技術移除二 ;26用f Ϊ ίΐ ί ΐ ’以含有熱磷酸之蝕刻液移除第二犧‘ f々目。丨右t田 層22與犧牲間隙壁29之材質為二氧化 =則可使用Μ蝕刻方 <，以含有氫氟酸之 =止層22與犧牲間隙壁29，或者亦可使用乾 除蝕刻終止層22與犧牲間隙壁29。 弋移 第2 J圖中，於該半導體基材2 〇形成一輕摻雜汲極 (lightly doped drain, LDD)區 32。其中，可如習知雜 子植入3 3技術摻雜磷或砷於半導體基材2 〇，以形成此 雜源/汲極3 2。當然，可於離子植入後再進行一快速加1熱多 回火（rapid thermal anneai，RTA)步驟，以修復經^ 次離子植入（第2C圖與第2 J圖）被破壞之晶格結構。、 第2 K圖中，於閘極導體層3丨之側壁形成一矽化遮蔽間 ，34。其中’形成石夕化遮蔽間隙壁34之方式可先沉積—遮 蔽層（未顯示於圖中），再回蝕刻此遮蔽層以形成此石夕^ 遮蔽間隙壁34，遮蔽層之材質可為二氧化矽或氮化矽。 574746 五、發明說明（6) 最後，如第2L圖所示，為了降低閘極導體層3 1與源/汲 極2 5之阻值，以矽化遮蔽間隙壁3 4為遮罩進行自行對準矽 化物（self-aligned silicide，salicide)製程，以於 閘極導體層3 1表面與源/汲極2 5表面形成一金屬矽化物層 3 5，金屬矽化物層3 5之材質可為矽化鈷、矽化鎳或矽化 鈦，至此，則完成N型金氧半場效應電晶體之製作。 由於本發明僅以一道光罩定義出閘極區域（第2B圖）， 然後於此閘極區域形成開孔2 7 (並同時形成凹陷通道） (第2 E圖），再於開孔2 7中形成閘極氧化層3 0與閘極導體 層3 1 (第2H圖），而非如習知技術分別以兩道光罩形成閘 極與凹陷通道，因此，本發明可避免發生閘極與凹陷通道 無法對準的問題。 而且’習知技術係單以微影製程與蝕刻技術就決定了閘 極寬度。然而，本發明形成開孔27 (第2E圖）後，於開孔 27中形成犧牲間隙壁29 (第2G圖），再於開孔27中形成閘 極導體層3 1 (第2 Η圖），最後移除犧牲間隙壁2 9 (第2 I圖 \ =僅留下閘極導體層31。因此，本發明最初是藉由微影 製程與餘刻技術形成開孔2 7寬度，而最後形成之閘極導體 ^ 3 或閘極）寬度則小於開孔27寬度，對於不斷往線寬 縮小進化的半導體技術而言，本發明相對於習知方式不需 要較高的微影製程與蝕刻技術的解析度，本發明相對於習 矣方式在製程控制上較為簡易。, The way to form the gate conductor layer 3 丨 can be preceded by and? Deposition of polycrystalline stone in hole 27 | (not shown in the figure here the crystalline silicon layer stops at the second sacrificial layer 26. The second sacrificial layer 26 is in the surface), and then etch back to the 2I picture 'etched with the last name Technology Removal II; 26 Use f Ϊ ίΐ ί ΐ 'remove the second sacrifice' with an etchant containing hot phosphoric acid.丨 The material of the right field layer 22 and the sacrificial gap wall 29 is oxidized = you can use the M etching method < with hydrofluoric acid = stop layer 22 and the sacrificial gap wall 29, or you can use dry removal etching to stop Layer 22 and sacrificial spacer 29. Migration In FIG. 2J, a lightly doped drain (LDD) region 32 is formed on the semiconductor substrate 20. Among them, the conventional dopant implantation 3 3 technique can be used to dope phosphorus or arsenic to the semiconductor substrate 20 to form the heterosource / drain 32. Of course, a rapid thermal anneai (RTA) step can be performed after ion implantation to repair the damaged lattice of ion implantation (Figures 2C and 2J). structure. In Fig. 2K, a silicided shielding space is formed on the side wall of the gate conductor layer 3, 34. The method of forming the Shixihua shielding barrier 34 can be first deposited-a masking layer (not shown in the figure), and then the etching layer is etched back to form this Shixi ^ The shielding barrier 34 can be made of two materials. Silicon oxide or silicon nitride. 574746 V. Description of the invention (6) Finally, as shown in Fig. 2L, in order to reduce the resistance value of the gate conductor layer 31 and the source / drain electrode 25, the silicide is used to shield the partition wall 34 as a mask for self-alignment. A silicide (self-aligned silicide, salicide) process is used to form a metal silicide layer 3 5 on the surface of the gate conductor layer 31 and the source / drain 25 surface. The material of the metal silicide layer 35 may be cobalt silicide. , Nickel silicide or titanium silicide, at this point, the production of N-type metal-oxygen half-field effect transistor is completed. Since the present invention only defines a gate region with a photomask (FIG. 2B), then an opening 2 7 is formed in the gate region (and a recessed channel is formed at the same time) (FIG. 2E), and then an opening 2 7 is formed. The gate oxide layer 30 and the gate conductor layer 3 1 are formed in FIG. 2 (FIG. 2H), instead of using two photomasks to form the gate and the recessed channels as in the conventional technology, therefore, the present invention can avoid the occurrence of the gates and the recesses. Channel misalignment problem. Moreover, the conventional technique simply determines the gate width by the lithography process and the etching technique. However, after the opening 27 (FIG. 2E) is formed in the present invention, a sacrificial spacer 29 (FIG. 2G) is formed in the opening 27, and the gate conductor layer 3 1 is formed in the opening 27 (FIG. 2). Finally, the sacrificial spacer 2 9 is removed (Fig. 2 I \ = only the gate conductor layer 31 is left. Therefore, the present invention initially forms the width of the opening 2 7 by the lithography process and the etching technique, and finally forms The width of the gate conductor ^ 3 or gate) is smaller than the width of the opening 27. For the semiconductor technology that continues to shrink and evolve toward the line width, the present invention does not require a higher lithography process and etching technology than the conventional method. Resolution, the present invention is relatively simple in terms of process control compared with the conventional method.
574746 五、發明說明（7) 、另外，習知技術是先進行 次離子 , 極側邊形成間隙Λ第—再次進 =熱 最後進行第二次植 本發明先進行第一次離子植人24以形成源、H5(然而; K 29^=間極導體層3“或閑極）側邊之犧牲間 隙土 29 (、第21圖）後，才進行第二次離子植入33以形成 摻雜源/汲極3 2 (第2 J圖），最後進行快速加熱回火步工 驟，因此本發明進行了兩次離子植入與一次快速加熱回火 步驟。習知方式進行兩次快速加熱回火步驟，而本發明僅 進行一次快速加熱回火步驟，本發明相對於習知技術更能 避免摻雜後之區域因為進行快速加熱回火步驟而擴散的問 題，對於不斷往線寬縮小進化的半導體技術而言，本發明 比習知技術較能避免短通道效應問題。 近幾年發展之矽覆絕緣層晶圓 Λ θ ^ (Silic〇n-〇n-inSulat〇r，S〇I)，产主要疋在石夕晶圓下添 七，戚免電氣效應，以降低電源消 增-氧化物的絕緣層，的處理速度：覆絕緣層 耗’減少電〉!的流源消耗的設備上（如行動電 晶圓技術可應用在需要杈t ί半導體基材2 〇除了可以為一 話、：t)二因此么本3 L絕緣層晶圓。當半導體基材20 矽晶圓外，亦可以為一矽覆、& 574746 五、發明說明（8) 為一矽覆絕緣層晶圓時，則可藉由移除部分半導體基材2 0 (第2 E圖）之多寡來決定凹陷通道之深度，以控制金氧半 場效應電晶體之臨界電壓（threshold voltage)。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明之 較佳實施例而已，並非用以限定本發明之申請專利範圍； 凡其它未脫離本發明所揭示之精神下所完成之等效改變或 修飾，均應包含在下述之申請專利範圍内。574746 V. Description of the invention (7) In addition, the conventional technique is to perform a secondary ion first, and a gap is formed on the pole side Λ first-re-entry = heat and finally a second implantation The present invention first performs the first ion implantation of 24 to After forming the source, H5 (however; K 29 ^ = intermediate conductor layer 3 "or the free electrode) side of the sacrificial interstitial soil 29 (Figure 21), the second ion implantation 33 is performed to form the doped source / Drain 3 2 (Figure 2 J), and finally the rapid heating and tempering step is performed, so the present invention performs two ion implantation and one rapid heating and tempering steps. The conventional method performs two rapid heating and tempering steps. Step, and the present invention performs only one rapid heating and tempering step. Compared with the conventional technology, the present invention can avoid the problem of diffusion of the doped region due to the rapid heating and tempering step. Technically, the present invention can avoid the short-channel effect problem more than the conventional technology. Silicon-clad insulating layer wafers developed in recent years Λ θ ^ (Silic〇n-〇n-inSulat〇r, S〇I), production Mainly add 7 under Shi Xi wafer, avoiding electrical effects, Reduce the power supply increase-the insulating layer of the oxide, the processing speed: the insulating layer consumes' reduced electricity>! The current source consumes equipment (such as mobile wafer technology can be applied to semiconductor substrates 2). In addition, it can be one word: t) so this is a 3 L insulation layer wafer. When the semiconductor substrate is a 20 silicon wafer, it can also be a silicon cover. &Amp; 574746 V. Description of the invention (8) is a silicon When the wafer is covered with an insulating layer, the depth of the recessed channel can be determined by removing a part of the semiconductor substrate 20 (Fig. 2E) to control the threshold voltage of the metal-oxygen half field effect transistor. As will be understood by those familiar with this technology, the above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below.
第14頁 574746 圖式簡單說明 本發明的較佳實施例於前述之說明文字中輔以下列圖形做 更詳細的闡述，其中： 第1圖為繪示習知技術製作之具凹陷通道之金氧半場效 應電晶體之剖面結構示意圖；以及 第2 A〜2L圖為繪示本發明製作具凹陷通道之N型金氧半場 效應電晶體之剖面結構流程示意圖。 圖式標記說明： 10 半導體基材11 源/汲極 1 2 閘極1 3 間隙壁 1 4 凹陷通道 20 半導體基材21 隔離區 2 2 I虫刻終止層2 3第一犧牲層 24 離子植入25 源/汲極 2 6第二犧牲層2 7開孔 2 8 二氧化矽層2 9犧牲間隙壁 3 0閘極氧化層3 1閘極導體層 3 2 輕摻雜源/汲極3 3 離子植入 34矽化遮蔽間隙壁35 金屬矽化物層Page 574746 The diagram simply illustrates the preferred embodiment of the present invention. In the foregoing explanatory text, the following figures are used to explain in more detail, of which: Fig. 1 shows the metal oxide with a recessed channel made by conventional techniques. Schematic diagram of the cross-sectional structure of a half-field effect transistor; and Figures 2A to 2L are schematic diagrams showing the cross-sectional structure of a N-type metal-oxygen half-field effect transistor with a recessed channel according to the present invention. Description of graphical symbols: 10 semiconductor substrate 11 source / drain 1 2 gate 1 3 gap wall 1 4 recessed channel 20 semiconductor substrate 21 isolation region 2 2 I etch stop layer 2 3 first sacrificial layer 24 ion implantation 25 source / drain 2 6 second sacrificial layer 2 7 opening 2 8 silicon dioxide layer 2 9 sacrificial spacer 3 0 gate oxide layer 3 1 gate conductor layer 3 2 lightly doped source / drain 3 3 ions Implant 34 silicide to shield the bulkhead 35 metal silicide layer
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW91136749ATW574746B (en) | 2002-12-19 | 2002-12-19 | Method for manufacturing MOSFET with recessed channel |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW91136749ATW574746B (en) | 2002-12-19 | 2002-12-19 | Method for manufacturing MOSFET with recessed channel |
| Publication Number | Publication Date |
|---|---|
| TW574746Btrue TW574746B (en) | 2004-02-01 |
| TW200411832A TW200411832A (en) | 2004-07-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW91136749ATW574746B (en) | 2002-12-19 | 2002-12-19 | Method for manufacturing MOSFET with recessed channel |
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| TW (1) | TW574746B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100390947C (en)* | 2004-03-18 | 2008-05-28 | 台湾积体电路制造股份有限公司 | Metal oxide semiconductor field effect transistor and its manufacturing method |
| US7700441B2 (en) | 2006-02-02 | 2010-04-20 | Micron Technology, Inc. | Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates |
| US7772632B2 (en) | 2006-08-21 | 2010-08-10 | Micron Technology, Inc. | Memory arrays and methods of fabricating memory arrays |
| US7825462B2 (en) | 2004-09-01 | 2010-11-02 | Micron Technology, Inc. | Transistors |
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