TW567452B - Liquid crystal scan line driver circuit having fault detection-and-correction function - Google Patents

Abstract

A kind of liquid crystal scan line driver circuit having fault detection-and-correction function contains the followings: the first detection apparatus, which corresponds to the stuck-at-zero fault of the first delay flip-flop (DFF) and generates the first logic level at the first DFF; The second detection apparatus, which corresponds to the fixed logic error inside the first DFF to generate the first logic level; and the control signal generation apparatus, which generates the first control signal when the entire input terminals are at the second logic level and generates the second control signal when one input terminal is at the first logic level. The output terminals of the first and the second detection apparatuses are connected to the input terminal of the control signal generation apparatus. The transmission control apparatus makes the first DFF transmit signal to the second DFF and the scan line due to the first control signal, and breaks the electric connection among the first, the second DFF and the scanning line due to the second control signal so as to transmit the signal of the third DFF at the other side to the second DFF through the scanning line.

Description

Translated fromChinese

567452 A7 B7 五、發明説明（） 5_1發明領域 (請先閲讀背面之注意事項再填寫本頁) 本發明係有關於一種液晶顯示器（Liquid Crystal Display: LCD)的掃描線驅動器，特別是有關於一種具錯 誤偵測暨更正功能（fault detection-and-correction function)之液晶顯示器掃描線躁動電路。 5-2發明背景 在製造液晶顯示器（Liquid Crystal Display : LCD) 時，多是以薄膜電晶體（Thin Film Transistor : TFT)液晶 顯示器最常見，並且近來經常使用的技術是低溫複晶矽 (LTPS : Low Temperature Polycrystalline Silicon)製 程》通常在一般的LTPS薄膜電晶體製程中，掃描線驅 動器（scand river)是被形成在玻璃底材上，並且薄膜電晶 體液晶顯示器也是形成在此玻璃底材上。然而因為現今 的製程良率尚不穩定，所以在液晶顯示器中的掃描線軀 動器（scan driver)的製作上，最關鍵的移位暫存器（shift register)常常需要製作額外的錯誤偵測暨更正電路，以 免製作出來的面板因為一個移位暫存器損壞而導致整個 面板不能使用。 經濟部智慧財產局員工消費合作社印製 在習知技術中，所有的錯誤偵測暨更正電路都是建 立在一單邊驅動的模式下，換句話說，掃描線驅動器是 形成在玻璃底材上的單一邊上（左邊或右邊）。即使是將掃 描線驅動器形成在玻璃底材的左邊和右邊上，以企囷由 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 567452 A7 B7 五、發明說明（） (請先閲讀背面之注意事項再填寫本頁) 兩邊同時驅動薄膜電晶體陣列的閘極匯流排，習知技術 仍然沒有辦法由兩邊同時駆動掃描線（或閘極匯流排），本 發明的目的是要提出一種具錯誤偵測暨更正功能之電 路，使其可以由透明底材（例如玻璃）上的一邊或是兩邊同 時驅動掃描線（閘極匯流排）。 在傳統的薄膜電晶體液晶顯示器中，用以製造在面 板上的薄膜電晶體之非晶矽（amorphous silicon)的載子 之移動率（mobility)，遠低於用於一般結晶矽（crysta| silicon)内的載子之移動率。所以非晶矽製程僅用來製造 面板上的薄膜電晶體，但是上述製程不能被用來製作資 料驅動器（data driver)或是掃描線驅動器（scan driver), 經濟部智慧財產局員工消費合作社印製 因此，資料驅動器以及掃描線驅動器只能被製造在以梦 為底材而非以玻璃為底材的積體電路上。薄膜電晶艘液 晶顯示器的結構顯示在圖一中，其中面板10是由玻璃所 形成，並且薄膜電晶體陣列是形成在面板10上。掃描線 驅動器11和資料驅動器積體電路12都是用來驅動薄膜 電晶體陣列中的電晶體的。上述的薄膜電晶體陣列包含 許多電晶體（薄膜電晶體：TFT)14，每個電晶體都連接到 一透明電極16。在囷一所示的習知技術中，因為位於玻 璃底材10上的掃描線驅動器11和資料驅動器12都是形 成在玻璃底材以外的底材上，所以必須將已經製造好的 掃描線驅動器11和資料駆動器12黏貼到面板1〇上。 隨著技術的進步，發展出低溫複晶矽製程（LTPS) 以製造薄膜電晶體液晶顯示器’並且不僅是囷素（pixel) 3 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 567452 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁} 中的開關是由複晶矽所構成，掃描線驅動器電路以及資料 驅動電路中的電晶體也都是由複晶矽所構成。換句話 說，藉由低溫多晶矽製程，掃描線驅動器和資料驅動器 可以被形成在面板（玻璃底材）上，並且所製造出來的液晶 顯示器之成本也大為降低，上述的液晶顯示器知結構顯 示在圖二中。其中面板20是由玻璃所形成，並且薄膜電 晶艘陣列是形成在面板20上，掃描線驅動器21和資料 驅動器22都是用來驅動薄膜電晶體陣列中的電晶體的。 上述的薄膜電晶體陣列包含許多電晶體（薄膜電晶體： TFT) 24，每個電晶體都連接到一透明電極26。在圖二所 示的習知技術中，掃描線驅動器21和資料駆動器22都 形成在面板（玻璃底材）20上。如囷二所示，掃描線驅動 器21是在面板20的一個側邊上，並且被用來依序地媒 動電性麵合到每一個薄膜電晶艘的閘極之閘極匯流排 (掃描線）。掃描線驅動器的任何錯誤都會使面板特性不佳 並且降低面板的良率，以致成本提高。 經濟部智慧財產局員工消費合作社印製 為了要完全地利用掃描線驅動器中的錯誤偵測暨更 正電路，並且快速地驅動面板上的掃描線（閘極匯流排）， 因此提出了一種在面板兩側上都具有掃描線驅動器的結 構，如圖三所示，薄膜晶體陣列是形成在面板30上，其 中面板30是由玻璃所形成，並且掃描線驅動器31和資 料驅動器積體電路32都是用來軀動薄膜電晶體陣列中的 電晶體的。上述的薄膜電晶體陣列包含許多電晶體（薄膜 電晶體：TFT)34，每個電晶體都連接到一透明電極36。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 567452 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 在圖三所示的習知技術中，掃描線驅動器31和資料驅動 器積體電路32都形成在玻璃底材30上，並且就結構而 言，掃描線驅動器31是形成在玻璃底材30的兩個側邊 上。因為位於玻璃底材30的兩個側邊上的掃描線媒動器 31都可以驅動閘極匯流排（掃描線），所以也較易於驅動 耦合到掃描線上的每一個電晶體。 顯示在圖一、圖二與圖三中的掃描線驅動器所用之 電路結構是傳統的電路，其是由串聯的延遲型正反器 (Delay-type FlipFlop: DFF)所構成的，並且顯示在圖四 A中，其輸入端IN被耦合到第一 DFF: Q1，此外CK端 提供計時脈波到第一 DFF: Q1、第二DFF: Q2以及第三 DFF : Q3…等❶在IN端、CK端、第一 DFF Q1輸出端、 第二DFF Q2以及第三DFF: Q3上的訊號之波形顯示在 圖四B中。因為每一個移位暫存器的輸出端上的脈波， 掃描線上的所有電晶體（薄膜電晶體）都會被啟動。 當以低溫複晶矽製程來製造掃描線駆動器之移位暫 存器時，其所製造出來的移位暫存器常常會失敗，並且因 此經常導致了移位暫存器的輸出端上發生了固定邏輯 零錯誤（st uck-at-zero fault)或是固定邏輯一錯誤（st uck· at-zero fault)。為了要解決此問題，所以製造的不只是 一組移位暫存器，而是使用了三組相同的移位暫存器， 並且以此三組中的輸出佔多數者，用來代表這三組移位 暫存器的輸出。用於解決前述問題的其他方法是利用雷 射以切斷並隔離失敗的區域，此種方法經常見於單邊驅 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) .....•裝.........訂·.........參 (請先閲讀背面之注意事項再填寫本頁) A7 B7 567452 五、發明説明（） 動模式的液晶顯示器中，也就是說掃描線驅動器是形成 在液晶顯示器的面板之一個側邊上，例如圓二所示。 在製造液晶顯示器的技術剛發展之初，為了要克服 低良率所造成的問題’通常會將三組串接的延遲型正反 器（DFF)並接到一個或閘（〇R gate)上，上述的或閘是用 以傳遞正確的訊號到後續的數組串接之延遲型正反器 中，如圖五A所示，其中顯而易見的是在任何一組串接 的延遲型正反器中’若是有任何一個發生固定邏輯零錯 誤（stuck-at-zero fault)，即使只有一組串接之延遲型正 反器正確的動作，但是正確的訊號仍然會傳遞到後續的 數組串接之延遲型正反器中。另一方面，當在任何一組 串接的延遲型正反器中發生固定邏輯一錯誤（stuck-at-one fault)時，或閘40的輸出也會固定於邏輯一。當此 遮j況發生時，會經由測試墊片來進行偵測，以偵測出數 組串接的延遲型正反器中，哪一組串接的延遲型正反器 的輸出發生了固定邏輯一錯誤（stuck-at-onefault)。在發 現了哪一組串接的延遲型正反器，例如串接的延遲型正 反器41，的輸出發生固定於邏輯一的錯誤之後，就使用 雷射以將串接的延遲型正反器41之輸出切斷。例如可以 將雷射聚焦於點P1，以切斷串接的延遲型正反器41。所 以或閘40的輸入端中固定於邏輯一者會被切斷，以避免 所發生的邏輯一錯誤被輸入或閘40中，並且其浮接 (floating)現象也會因為或閘40的每一個輸入端都被以 電阻耦合接地而消除。然而要在每兩個延遲型正反器中 6 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再塡寫本頁) 、tr. # 經濟部智慧財產局員工消費合作社印製 567452 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 間都製作一個測試墊片可以說是不可能的，因為其測試 成本會因此而增加到無法接受的程度。如果習知技術的 具有冗i功能之掃描線驅動器是如囷五A所示的結構， 則其缺點即如上所述。 此外，為了避免液晶顯示器因為一個單一的移位暫 存器之失敗而變成不能使用，所以習知技術提出了一種 不必使用測試整片和雷射的電路。上述電路之結構顯示 在囷五B中，其相似於顯示於囷五a中者。依據顯示於 圖五Β中的電路囷，多數決電路49被置於相鄰的兩級之 延遲型正反器之間，以取代測試墊片和接地之電阻。此 外，當任何一個移位暫存器發生錯誤時，因為有多數決 電路49所以不需要使用雷射將移位暫存器切斷。依據囷 五Β，若是點A、Β與C中多數具有邏輯零，多數決電路 49的輸出即是邏輯零。反之，若是點α、Β與C中多數 具有邏輯一，多數決電路49的輸出即是邏輯一。即使是 一個延遲型正反器壞掉，多數決電路49仍然會輸出正確 的訊號到下一級的延遲型正反器。 經濟部智慧財產局員工消費合作社印製 上述的兩種習知的移位暫存器是以單邊驅動的，就 圖三所示的雙邊驅動模式而言，一旦有一邊的移位暫存 器失敗（fail)，亦即有一邊的移位暫存器之輸出不同於面 板上另外一端的移位暫存器之輸出，在故陣的移位暫存 器之後的掃描線上的電壓大小會由面板的/端逐漸變化 到到另一端，亦會導致直流電流經掃描線，並且使得面 板無法被利用。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 567452 A7 B7 五、發明説明（） 5·3發明目的及概述 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 鑒於上述之發明背景中，傳統的液晶顯示器有其各 種缺點，本發明提出一種具錯誤偵測暨更正功能之液晶 顯示器（Liquid Crystal Display : LCD)之驅動裝置，上 述依據本發明的具錯誤偵測暨更it功能之液晶顯示器軀 動裝置可以由掃描線的一邊，或是同時由掃描線的兩邊 同時媒動，此媒動裝置包含下列元件。其中第一堪動元 件係用於將訊號由第一驅動元件内的前一級延遲型正反 器（Delay-type Flip Flop : DFF)傳送到第一驅動元件内的 本級延遲型正反器再傳送到第一軀動元件内的後一級延 遲型正反器。而第二驅動元件係用於將訊號由第二駆動 元件内的前一級延遲型正反器傳送到第二媒動元件内的 本級延遲型正反器再傳送到第二軀動元件内的後一級延 遲型正反器。而複數個掃描線係用於電性耦合第一驅動 元件内與第二驅動元件内同一級的延遲型正反器，第一 驅動元件以及第二驅動元件分別都包含複數個延遲型正 反器以及複數個錯誤偵測暨更正電路，這些複數個錯誤 偵測暨更正電路的每一個之輸入端被耦合到複數個延遲 型正反器中本級延遲型正反器以及前一級延遲型正反器 的輸出端。此複數個錯誤偵測暨更正電路的每一個輸出 端被電性耦合到複數個掃描線中的其中一條掃描線以及 複數個正反器中位於後一級其中一個正反器。上述之錯 誤偵測暨更正電路係用於決定是否由本級的第一延遲型 正反器（Delay-type Flip Flop : DFF)傳送訊號到後一級的 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 567452 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 第二延遲型正反器的輸入端，或是由本級的第三延遲型 正反器傳送訊號到第二延遲型正反器。 上述依據本發明所提出之錯誤偵測暨更正電路包含 下列元件，其中第一偵測裝置係用以相應於發生在第一 延遲型正反器的固定邏輯零錯誤（stuck-at-zero fault)， 而於此第一偵測裝置的輸出端產生第一邏輯準位。此第 一延遲型正反器、第二延遲型正反器、第三延遲型正反 器以及掃描線係形成於一底材上，前一級的第四延遲型 正反器之輸出端被耦合到此第一偵測裝置之輸入端。上 述的底材可以是矽底材或是透明底材（例如玻璃等）。 第二偵測裝置係用以相應於發生在第一延遲型正 反器的固定邏輯一錯誤（stuck-at-one fault)而於第二偵 測裝置的輸出端產生第一邏輯準位。控制訊號產生裝置 係用於在控制訊號產生裝置的所有輸入端呈現第二邏輯 準位時產生第一控制訊號。在此控制訊號產生裝置的其 中一輸入端呈現第一邏輯準位時產生第二控制訊號，上 述之第一偵測裝置以及第二偵測裝置的輸出端被電性耦 合到控制訊號產生裝置的輸入端。 傳輸控制裝置係用以相應於第一控制訊號而由第 一延遲型正反器傳送訊號到該第二延遲型正反器以及掃 描線。此傳輸控制裝置相應於第二控制訊號而將第一延 遲型正反器和第二延遲型正反器及掃描線之間的電性麵 合切斷，然後由第三延遲型正反器而來的訊號被經由掃 描線而傳送到第二延遲型正反器。此掃描線的一邊被電 本紙張及度適用中國國家標準(CNS)A4規格(210X 297公釐) ......·¥.........、町.........參 (請先閲讀背面之注意事項再填寫本頁) 567452 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 性麵合到位於此底材的一個側邊上的第一延遲型正反 器’掃描線的另一邊被電性耦合到位於底材的另一個側 邊上的第二延遲型正反器。上述的固定邏輯零錯誤係被 定義為當前一級的第四延遲型正反器之輸出端由第二邏 輯準位變換到第一邏輯準位時，此第一延遲型正反器的 輸出端仍保持在第一邏輯準位。總之不論正反器之輸入 為何’當其輸出的邏輯值恆為邏輯零時，則定義此正反 器發生了固定邏輯零錯誤。另一方面，上述的固定邏輯 一錯誤係被定義為當全部的延遲型正反器皆由第二邏輯 準位被切換成第一邏輯準位時，第一延遲型正反器的輸 出端仍固定在第二邏輯準位之情形。換句話說，不論正 反器之輸入為何，當其輸出的邏輯值恆為邏輯一時，則 定義此正反器發生了固定邏輯一錯誤。而上述複數個薄 膜電晶體（Thin Film Transistor : TFT)之狀態係由掃描線 上的訊號所控制，而此複數個薄膜電晶體的電性控制位 於此底材上的液晶之分子的極化方向。 經濟部智慧財產局員工消費合作社印製 上述之複數個掃描線的一邊之端點被電性耦合到第 一驅動裝置的輸出端，而且此複數個掃描線的另一邊之 端點被電性耦合到第二驅動裝置的輸出端。上述之第一 偵測裝置、第二偵測裝置、控制訊號產生裝置以及傳輸 控制裝置係以低溫複晶矽（Low Temperature Po lycrysta Mine Silicon: LTPS)製程所製造。上述之掃描 線被電性耦合到複數個薄膜電晶體。上述之第一偵測裝 置包含：第一反及閘（NAN D gate)、第一電晶體、第二電 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公爱) 567452 A7 B7 五、發明説明（） 晶體、第三電晶體、第四電晶體、第五電晶體、第一反 相器以及第二反相器。上述之第二偵測裝置包含··第六 電晶體、第七電晶體以及第二反及閘。 (請先閲讀背面之注意事項再填寫本頁) 上述之控制訊號產生裝置包含第三反及閘以及第三 反相器，此控制訊號產生裝置的輸出端被電性耦合到上 述傳輸控制裝置，以對此傳輸控制裝置提供第一控制訊 號以及第二控制訊號。上述之第一控制訊號以及第二控 制訊號其中的任何一個包含一高邏輯準位以及一低邏輯 準位。上述之傳輸控制裝置係為一傳輸閘，其包含具有 第一控制閘、第一控制閘、一輸入端以及一輸出端的互 補式金氧半場效電晶體（CMOS)傳輸閘。並且在同一時間 中只有第一控制訊號或第二控制訊號的其中一個會被電 性耦合到此傳輸控制裝置的第一控制閘以及第二控制閉 上。 經濟部智慧財產局員工消費合作社印製 上述之互補式金氧半場效電晶體（CMOS)傳輸閉在 第一控制訊號被耦合到第一控制閘以及第二控制閘時， 於互補式金氧半場效電晶艘傳輸閉的輸入端和輸出端之 間呈現電性導通。而上述之互補式金氧半場效電晶艘 (CMOS)傳輸閘在上述第二控制訊號被麵合到第一控制 閘以及第二控制閘時，於互補式金氧半場效電晶艘傳輸 閘的輸入端和輸出端之間呈現電性絕緣。上述之第一邏 輯準位係為一低邏輯準位，而第二邏輯準位係為一高邏 輯準位。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 567452 經濟部智慧財產局員工消費合作社印製 A7 B7 發明説明（） 5·4圓式簡單說明 將後續的說明配合下列囷式，將可以對於本&567452 A7 B7 V. Description of the invention () 5_1 Field of invention (please read the precautions on the back before filling this page) The present invention relates to a scan line driver for a liquid crystal display (Liquid Crystal Display: LCD). Scanning line agitation circuit of LCD monitor with fault detection-and-correction function. 5-2 Background of the Invention When manufacturing a liquid crystal display (Liquid Crystal Display: LCD), a thin film transistor (TFT) liquid crystal display is the most common, and a technology often used recently is low temperature polycrystalline silicon (LTPS: Low Temperature Polycrystalline Silicon) Generally, in a general LTPS thin film transistor process, a scan line driver (scand river) is formed on a glass substrate, and a thin film transistor liquid crystal display is also formed on this glass substrate. However, because the current production yield is still unstable, the most critical shift register in the production of scan drivers in LCD monitors often requires additional error detection. Correct the circuit to prevent the panel from being made unusable due to the damage of a shift register. In the consumer technology cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, all error detection and correction circuits are built in a unilateral driving mode. In other words, the scanning line driver is formed on a glass substrate. On a single side (left or right). Even if the scan line driver is formed on the left and right sides of the glass substrate, in order to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) to this paper size 567452 A7 B7 V. Description of the invention () (Please read first Note on the back, please fill in this page again.) The gate buses of the thin film transistor array are driven simultaneously on both sides. There is still no way in the conventional technology to simultaneously sweep the scanning lines (or gate buses) from both sides. The object of the present invention is to propose a Circuit with error detection and correction function, which can drive scanning line (gate bus) from one or both sides of transparent substrate (such as glass) at the same time. In traditional thin-film transistor liquid crystal displays, the mobility of carriers of amorphous silicon used to make thin-film transistors on the panel is much lower than that used for crysta | silicon. The carrier mobility in). Therefore, the amorphous silicon process is only used to manufacture thin film transistors on the panel, but the above process cannot be used to make data drivers or scan drivers. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, data drivers and scan line drivers can only be manufactured on integrated circuits that use dreams as substrates rather than glass. The structure of the thin film transistor liquid crystal display is shown in FIG. 1, where the panel 10 is formed of glass, and the thin film transistor array is formed on the panel 10. Both the scan line driver 11 and the data driver integrated circuit 12 are used to drive transistors in a thin film transistor array. The thin-film transistor array described above includes a plurality of transistors (thin-film transistors: TFTs) 14 each of which is connected to a transparent electrode 16. In the conventional technique shown in the first one, since the scan line driver 11 and the data driver 12 on the glass substrate 10 are formed on a substrate other than the glass substrate, the scan line driver that has been manufactured must be manufactured. 11 and the data actuator 12 are adhered to the panel 10. With the advancement of technology, the development of low-temperature polycrystalline silicon process (LTPS) to manufacture thin-film transistor liquid crystal displays' and not only pixel (pixel) 3 This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm) ) 567452 A7 B7 V. Description of the invention () (Please read the notes on the back before filling out this page} The switch in the figure is composed of polycrystalline silicon, and the transistors in the scan line driver circuit and the data driver circuit are also made of It is composed of polycrystalline silicon. In other words, through the low-temperature polycrystalline silicon process, the scanning line driver and data driver can be formed on the panel (glass substrate), and the cost of the manufactured liquid crystal display is greatly reduced. The known structure of the liquid crystal display is shown in Figure 2. The panel 20 is formed of glass, and the thin film transistor array is formed on the panel 20. The scan line driver 21 and the data driver 22 are used to drive the thin film transistor array. The above-mentioned thin-film transistor array contains many transistors (thin-film transistors: TFT) 24, each transistor is connected to a transparent Pole 26. In the conventional technique shown in FIG. 2, the scanning line driver 21 and the data actuator 22 are formed on a panel (glass substrate) 20. As shown in FIG. 2, the scanning line driver 21 is on the panel 20. On one side, and is used to sequentially energize the gate buses (scan lines) of the gates of each thin film transistor. Any error in the scan line driver will make the panel characteristics poor. And the yield of the panel is reduced, so that the cost is increased. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to fully utilize the error detection and correction circuit in the scan line driver, and quickly drive the scan line (gate on the panel) Bus), so a structure with scan line drivers on both sides of the panel is proposed. As shown in Figure 3, the thin film crystal array is formed on the panel 30, where the panel 30 is formed of glass and the scan line driver 31 and the data driver integrated circuit 32 are used to actuate the transistors in the thin film transistor array. The thin film transistor array described above contains many transistors (thin film transistors) : TFT) 34, each transistor is connected to a transparent electrode 36. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 567452 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Explanation () In the conventional technique shown in FIG. 3, the scan line driver 31 and the data driver integrated circuit 32 are both formed on a glass substrate 30, and in terms of structure, the scan line driver 31 is formed on a glass substrate 30 on both sides. Since the scan line mediator 31 on both sides of the glass substrate 30 can drive the gate bus (scan line), it is also easier to drive each of the couplings to the scan line. A transistor. The circuit structure of the scan line driver shown in Figures 1, 2, and 3 is a traditional circuit, which is composed of a delay-type flip-flop (DFF) in series. And shown in Figure 4A, its input terminal IN is coupled to the first DFF: Q1, and the CK terminal provides timing pulses to the first DFF: Q1, the second DFF: Q2, and the third DFF: Q3 ... etc. IN, CK, first DFF Q1 output The waveforms of the signals at the end, the second DFF Q2 and the third DFF: Q3 are shown in Figure 4B. Because of the pulse wave at the output of each shift register, all transistors (thin-film transistors) on the scan line will be activated. When the shift register of the scan line actuator is manufactured by a low-temperature polycrystalline silicon process, the shift register manufactured by the scan line actuator often fails, and therefore the output of the shift register is often caused. A fixed logic zero error (stuck-at-zero fault) or a fixed logic one error (stuck · at-zero fault). In order to solve this problem, not only one set of shift registers is manufactured, but three sets of the same shift register are used, and the output of the three sets is the majority, which is used to represent the three Output of bank shift register. The other method used to solve the aforementioned problem is to use laser to cut and isolate the failed area. This method is often found in unilateral driving. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ... . • Install ......... Order ......... Refer to (Please read the precautions on the back before filling in this page) A7 B7 567452 5. Description of the invention () LCD in motion mode In the display, that is, the scan line driver is formed on one side of the panel of the liquid crystal display, as shown by circle two, for example. At the beginning of the development of liquid crystal display technology, in order to overcome the problems caused by low yields, three sets of delay type flip-flops (DFF) connected in series are usually connected to one OR gate. The above-mentioned OR gate is used to transmit the correct signal to the subsequent arrayed flip-flops, as shown in Figure 5A. It is obvious that in any group of delayed-type flip-flops connected in series, 'If any stuck-at-zero fault occurs, even if only a set of serially connected delay-type flip-flops operate correctly, the correct signal will still be passed to the subsequent array serialization delay Type flip-flop. On the other hand, when a stuck-at-one fault occurs in any of a series of delayed flip-flops connected in series, the output of the OR gate 40 is also fixed at logic one. When this masking condition occurs, detection will be performed through a test pad to detect which set of serially connected delay-type flip-flops in the array has a fixed logic. One fault (stuck-at-onefault). After finding out which set of serially connected delay-type flip-flops, such as the serially-connected delay-type flip-flop 41, an error occurs in which the logic one is fixed, a laser is used to reverse the serially-connected delay type The output of the device 41 is cut off. For example, the laser can be focused on the point P1 to cut off the delay type flip-flop 41 connected in series. So the input of OR gate 40 fixed to logic one will be cut off to avoid the occurrence of a logic one error being input into OR gate 40, and its floating phenomenon will be caused by each of OR gates 40. The inputs are eliminated by resistive coupling to ground. However, 6 paper sizes in every two delay type flip-flops are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before writing this page), tr. # 经济 部Printed by the Intellectual Property Bureau employee consumer cooperative 567452 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling out this page) It can be said that it is impossible to make a test pad because the test cost will be And increased to an unacceptable level. If the conventional scanning line driver with redundant functions has a structure as shown in Fig. 5A, its disadvantages are as described above. In addition, in order to prevent the liquid crystal display from becoming unusable due to the failure of a single shift register, the conventional technique proposes a circuit which does not have to use a whole chip and a laser. The structure of the above circuit is shown in Fig. 25B, which is similar to that shown in Fig. 25a. According to the circuit shown in Fig. 5B, the majority circuit 49 is placed between the delay type flip-flops of two adjacent stages to replace the resistance of the test pad and ground. In addition, when an error occurs in any of the shift registers, it is not necessary to use a laser to cut off the shift registers because there is a majority circuit 49. According to 囷 5B, if the majority of points A, B, and C have logic zeros, the output of majority decision circuit 49 is a logic zero. Conversely, if the majority of the points α, B, and C have a logic one, the output of the majority decision circuit 49 is a logic one. Even if a delay type flip-flop is broken, the majority circuit 49 will still output the correct signal to the delay type flip-flop of the next stage. The above-mentioned two conventional shift registers are printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which are driven unilaterally. As far as the bilateral drive mode shown in Figure 3 is concerned, once there is one shift register, Failure, that is, the output of the shift register on one side is different from the output of the shift register on the other end of the panel. The voltage on the scan line after the shift register of the old array is determined by The / end of the panel gradually changes to the other end, which will also cause the DC current to pass through the scan line and make the panel unusable. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 567452 A7 B7 V. Description of the invention () 5.3 Purpose and summary of the invention (please read the notes on the back before filling this page) Intellectual property of the Ministry of Economic Affairs In view of the above background of the invention, the traditional liquid crystal display has various disadvantages. The present invention proposes a driving device for a liquid crystal display (LCD) with error detection and correction functions. The invented liquid crystal display body moving device with error detection and more it function can be moved by one side of the scanning line or both sides of the scanning line at the same time. The medium moving device includes the following components. The first movable element is used to transmit a signal from a previous-stage delay-type flip-flop (DFF) in the first drive element to the current-stage delay-type flip-flop in the first drive element. Delayed flip-flop in the first stage transmitted to the first torso element. The second driving element is used to transmit a signal from the previous-stage delay type flip-flop in the second moving element to the second-stage delay type flip-flop in the second medium-motion element and then to the second body-moving element. Post-stage delay type flip-flop. The plurality of scanning lines are used to electrically couple the delay type flip-flops at the same level in the first driving element and the second driving element. The first driving element and the second driving element each include a plurality of delay type flip-flops. And a plurality of error detection and correction circuits, the input of each of these plurality of error detection and correction circuits is coupled to a plurality of delay type flip-flops, a delay type flip-flop of this stage and a delay type flip-flop of a previous stage Output of the controller. Each output terminal of the plurality of error detection and correction circuits is electrically coupled to one of the plurality of scan lines and one of the plurality of flip-flops located in a subsequent stage. The above-mentioned error detection and correction circuit is used to determine whether the first delay-type flip flop (DFF) of this stage sends a signal to the next stage. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification. (210X297 mm) 567452 A7 B7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Input terminal of the second delay type flip-flop, or the third delay type flip-flop of this level sends the signal to Second delay type flip-flop. The above-mentioned error detection and correction circuit according to the present invention includes the following components. The first detection device is used to correspond to a stuck-at-zero fault of a first delay flip-flop. A first logic level is generated at the output of the first detection device. The first delay type flip-flop, the second delay type flip-flop, the third delay type flip-flop, and the scanning line are formed on a substrate, and the output terminals of the fourth delay type flip-flop in the previous stage are coupled. Go to the input of this first detection device. The substrate can be a silicon substrate or a transparent substrate (such as glass). The second detection device is configured to generate a first logic level at the output of the second detection device in response to a stuck-at-one fault of the first delay type flip-flop. The control signal generating device is used for generating a first control signal when all the input terminals of the control signal generating device present a second logic level. A second control signal is generated when one of the input terminals of the control signal generating device presents the first logic level, and the output terminals of the first detecting device and the second detecting device are electrically coupled to the control signal generating device. Input. The transmission control device is used for transmitting a signal from the first delay type flip-flop to the second delay type flip-flop and the scanning line corresponding to the first control signal. This transmission control device cuts off the electrical connection between the first delay type flip-flop, the second delay type flip-flop and the scanning line in response to the second control signal, and then comes from the third delay type flip-flop. The signal is transmitted to the second delay type flip-flop through the scanning line. One side of this scanning line is printed on paper and the degree is in accordance with the Chinese National Standard (CNS) A4 specification (210X 297 mm) ... ¥ ........., machi ... .... Refer to (Please read the notes on the back before filling this page) 567452 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) The other side of the first delay type flip-flop 'scan line on the side is electrically coupled to a second delay type flip-flop located on the other side of the substrate. The above-mentioned fixed logic zero error is defined as that when the output terminal of the fourth delay flip-flop of the current stage is changed from the second logic level to the first logic level, the output of the first delay flip-flop is still Stay at the first logical level. In short, regardless of the input of the flip-flop ', when the logic value of its output is always a logic zero, then a fixed logic zero error has been defined for this flip-flop. On the other hand, the above-mentioned fixed logic one error is defined as that when all the delay type flip-flops are switched from the second logic level to the first logic level, the output of the first delay type flip-flop is still Fixed at the second logical level. In other words, regardless of the input of the flip-flop, when the logic value of its output is always a logic one, a fixed logic-one error has occurred in defining the flip-flop. The state of the plurality of thin film transistors (TFTs) is controlled by the signals on the scanning lines, and the electrical properties of the plurality of thin film transistors control the polarization direction of the molecules of the liquid crystal on the substrate. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed one end of one of the plurality of scanning lines described above to be electrically coupled to the output end of the first driving device, and the other end of the plurality of scanning lines was electrically coupled to each other. To the output of the second drive. The first detection device, the second detection device, the control signal generating device, and the transmission control device are manufactured by a process of Low Temperature Polycrysta Mine Silicon (LTPS). The scanning lines described above are electrically coupled to a plurality of thin film transistors. The above-mentioned first detection device includes: a first counter-current gate (NAN D gate), a first transistor, and a second electronic paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public love) 567452 A7 B7 V. Description of the Invention () A crystal, a third transistor, a fourth transistor, a fifth transistor, a first inverter, and a second inverter. The above-mentioned second detection device includes a sixth transistor, a seventh transistor, and a second inverter gate. (Please read the precautions on the back before filling this page) The above control signal generating device includes a third inverter and a third inverter. The output of this control signal generating device is electrically coupled to the above transmission control device. A first control signal and a second control signal are provided to the transmission control device. Any one of the first control signal and the second control signal includes a high logic level and a low logic level. The above transmission control device is a transmission gate, which includes a complementary metal-oxide-semiconductor field-effect transistor (CMOS) transmission gate having a first control gate, a first control gate, an input terminal, and an output terminal. And at the same time, only one of the first control signal or the second control signal will be electrically coupled to the first control gate and the second control of the transmission control device. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned complementary CMOS half-effect transistor (CMOS) transmission. When the first control signal was coupled to the first control gate and the second control gate, the complementary CMOS half-field There is electrical continuity between the input terminal and the output terminal of the power-effect crystal ship. When the above-mentioned complementary metal-oxide-semiconductor half-field-effect transistor (CMOS) transmission gate is connected to the first and second control gates, the complementary metal-oxide-semiconductor half-field-effect transistor transmission gate There is electrical insulation between the input and output terminals. The above-mentioned first logic level is a low logic level, and the second logic level is a high logic level. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 567452 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Invention description () 5.4 Round type brief description The following description will be matched with the following formula, Will be available for this &

特徵有更為清楚之了解，其中： W 圓一顯示的是非晶矽薄膜電晶體形成在液_ 器的面板上，掃描線驅動器製作在矽底材上，而尤β不 个是在 液晶顯示器面板上的習知液晶顯示器面板之結構圖； 圖二顯示的是習知的一種液晶顯示器之結構圖，& 中複晶矽所製作的掃描線驅動器是形成於底材的單—側 邊上，並且液晶顯示器也形成於此底材上； 圖三顯示的是一種液晶顯示器之結構圖，其中複晶 矽所製作的掃描線驅動器是形成於底材的雙側邊上，並 且液晶顯示器也形成於此底材上； 囷四 Α顯示的是包含一列串接的延遲型正反器 (Delay-type Flip Flop: DFF)之移位暫存器的結構囷，其 構成了傳統的掃描線驅動器； 囷四B顯示的是習知的移位暫存器中的延遲型正 反器每一端點的波形圖； 圖五A顯示的是習知掃描線驅動器，其具有錯誤偵 測暨更正功能，並且是利用雷射切斷已經發生固定邏輯 零錯誤或固定邏輯一錯誤之串接的正反器； 圖五B顯示的是習知掃描線驅動器，其具有錯誤偵 測暨更正功能，並且是利用多數表決功能以防止發生固 定邏輯零錯誤或固定邏輯一錯誤； 圊六顯示的是本發明所提出的錯誤偵測暨更正電 12 本紙張尺度適用中國國家標準(CNS)A4規格(210Χ 297公楚) ···::'......·裝.........一叮.........Φ τ>靖先閱讀背面之注意事項再填寫本頁) 567452 A7The characteristics have a clearer understanding, among them: W circle one shows that the amorphous silicon thin film transistor is formed on the liquid crystal panel, the scan line driver is made on the silicon substrate, and especially β is not on the liquid crystal display panel. The structure of a conventional LCD panel is shown in Figure 2. Figure 2 shows the structure of a conventional LCD display. The scan line driver made by & polycrystalline silicon is formed on the single side of the substrate. And the liquid crystal display is also formed on this substrate; Figure 3 shows the structure of a liquid crystal display, in which the scan line driver made of polycrystalline silicon is formed on both sides of the substrate, and the liquid crystal display is also formed on On this substrate; 囷 IVA shows the structure of a shift register including a series of delay-type flip flops (DFF), which constitutes a traditional scan line driver; 囷Figure 4B shows waveforms of each end point of the delay flip-flop in the conventional shift register. Figure 5A shows the conventional scan line driver, which has error detection and correction functions, and is Profit Laser cut-off has occurred with a fixed logic zero error or a fixed logic one error serially connected flip-flop; Figure 5B shows a conventional scan line driver, which has error detection and correction functions, and uses the majority voting function To prevent the occurrence of a fixed logic zero error or a fixed logic one error; 26 shows the error detection and correction proposed by the present invention. 12 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297). · :: '... · Install ......... One bite ......... Φ τ > Jing first read the precautions on the back before filling in this page) 567452 A7

五、發明説明（） 經濟部智慧財產局員工消費合作社印製 提，的 的邏 出的準 出反個 出器個 出誤 出 所式明·，出的 提級輯 提正一 提反一 提錯I提 中方發上提上 所一邏 所的每 所正每 所，Μ所 例接本邊所點 中前的 中級上 中的上 中時t中 施連在側中節 例到點 例一路 例級路 例生改例 實的成-Ϊ例個 施送節 施前電 施本電 施發之施 佳間形同施一 實傳個 實由正 實由正 實誤位實 較之是之實每 佳位一 佳位更 佳位更 佳錯&佳 一列列上佳， 較準每 較準暨 較準暨 較零輯較 的器器板較下 一壓上 一壓測 一壓測 一輯邏一 明反反面一態 的電路 的電偵 的電偵 的邏的的 發正正器的狀 明高電 明高誤·，明高誤·，明定點明 U 本和與示明始 發將正 發將錯形發將錯形發固節發 據路路顯發起 本在更 本在，情本在，情本在個本 依電電晶本在 據路暨 據路時變據路時變據路一據 是正正液據路；依電測 依電器改依電器改依電每依 •，的更更的依電形明正憤 明正反之明正反之明正上明 圖示暨暨中明正情說更誤；說更正位說更正位說更路說 構顯測測例說更變A暨錯形B暨級準C暨級準A暨電B 結七偵偵施/\§暨改九測，情九測本輯九測一輯十測正十 路圖誤誤實I測之囷债時變圖债到邏圖债後邏圖摘更圖 電 錯錯佳 偵位 誤器改 誤送的 誤到的 誤暨 之 的中較 誤準 錯反之 錯傳點 錯送點 錯測 路出其 一 錯輯 的正位 的器節 的傳節 的偵 ·裝.......：、可.........Φ (請先閲讀背面之注意事項再填寫本頁} 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 經濟部智慧財產局員工消費合作社印製 567452 A7 - B7 五、發明説明（） 的錯誤偵測暨更正電路在固定邏輯一錯誤發生時，錯誤 摘測暨更正電路上每一個節點的邏輯準位之改變情形； 以及 囷十一說明具有依據本發明的一較佳實施例中所 提出的錯誤偵測暨更正電路之掃描線駆動器内，當有兩 個正反器發生錯誤時，在掃描線（掃描線匯流排）中資料傳 遞的情形。 5·5發明詳細說明 因為在一般習知的TFT之具有錯誤偵測暨更正功 能之移位暫存器都是基於單邊腰動模式下的，並且因為 使用低溫複晶矽製程所製造的晶體良率不穩定，會導致 其產生嚴重的問題。本發明的一較佳實施例提出不使用 單邊驅動模式，而具錯誤偵測暨更正功能的液晶顯示器 之掃描線媒動器，其電路圖如圖六所顯示。本發明的一 較佳實施例所提出具有錯誤偵測暨更正功能的液晶顯示 器使用的是，例如，雙邊驅動模式。其中由本發明的一 較佳實施例所提出的具有錯誤偵測暨更正功能之移位暫 存器在掃描線驅動器之中，而具有此種掃描線驅動器的 液晶顯示器之結構顯示在囷三中，雖然此種結構與習知 技術者相同，可是因為如圖六所示的本發明所提出之具 有錯誤偵測暨更正功能的移位暫存器，使其可以由兩個 掃描線驅動器同時驅動一個掃描線。 依據本發明的一較佳實施例之錯誤偵測暨更正電 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) .....•裝.........訂.........Φ (請先閲讀背面之注意事項再填寫本頁) 567452 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 路D11，其電路圖顯示在圖七中，D11是針對Q12的輸 出發生固定邏輯一錯誤或固定邏輯零錯誤之錯誤偵測更 正電路。另外，其電路圖亦包含在圖六中，其中固定邏 輯零（stuck-at-zero)偵測裝置60與固定邏輯一（stuck-at-one) >(貞測裝置 61的輸出被電性耦合到反及閘 (NAND)65。其中固定邏輯零偵測裝置60的其中一個輸 入端（P r e Q輸入端），可以被電性耦合到前一級錯誤偵測 暨更正電路之輸出端，而固定邏輯一偵測裝置61的其中 一個輸入端被電性耦合到正反器Q12(圖七）的Q端。反 及閘65的輸出端被饋入到反相器（inverter)66，此外， 反相器（inverter)66以及反及閘65的輸出端都提供控制 電壓傳輸閘（transmission gate)67。當反及閘65的輸出 端在第一邏輯準位（例如高邏輯準位）時，由本級的正反器 (例如正反器Q12)之Q端所輸出的訊號，除了被傳送到 後一級的正反器（例如正反器 Q13)之D端作為輸入之 外，並且也被傳送到連接至正反器Q12的Q端之掃描線 驅動器。 不論正反器之輸入為何，當其輸出的邏輯值恆為邏 輯零時，則定義此正反器發生了固定邏輯零錯誤。另一 方面，不論正反器之輸入為何，當其輸出的邏輯值恆為 邏輯一時，則定義此正反器發生了固定邏輯一錯誤 經濟部智慧財產局員工消費合作社印製 在本發明的一較佳實施例中，參考圖六，傳輸閘67 決定正反器Q12之Q端的輸出端，，是對連接到掃描線的 端點70作充/放電。當正反器Q12有故障時，例如若是 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) A7 B7 567452 五、發明説明（） ......#裝： (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 發生固定邏輯一錯誤（stuck-at-one fault)或是固定邏輯 零錯誤（stuck-at-zerofault)時，傳輸閘67會被關掉，所 以正反器Q 1 2與連接到端點7〇的掃描線無關。相反地’ 正反器Q13的輸入訊號是由連接到錯誤偵測暨更正電路 D11,的掃描線所提供的，並且錯誤偵測暨更正電路D11’ 是被耦合到前一級錯誤偵測暨更正電路之輸出端與正反 器Q12,的輸出端。所以輸入到正反器Q13的訊號是由位 於面板30(圖三）另一側邊上的正反器Q12’（前一級）所提 供《為了簡短的說明起見，錯誤偵測暨更正電路D11的 電路圖與錯誤偵測暨更正電路D11’（圖七）和其他錯誤偵 測暨更正電路（未顯示）的電路圖相同’參考圖七’前一級 前一級錯誤偵測暨更正電路之輸出以及本級D型正反器 (正反器 Q1 2)之輸出被饋入到錯誤偵測暨更正電路（例如 錯誤偵測暨更正電路D 1 1)。另外，若是錯誤偵測暨更正 電路（例如D11)並沒有任何故障，則本級的D型正反器 (例如正反器 Q1 2)的輸出被饋入到掃描線以及下一級正 反器（例如正反器CM 3)的〇端。換句話說，本級錯誤偵 測暨更正電路的輸出須視依據本發明的一較佳實施例之 錯誤偵測暨更正電路對本級正反器和前一級正反器輸出 所伯測的結果而定。依據本發明，在面板的一個側邊上 的掃描線驅動器内之每兩個正反器之間，都具有一個錯 誤偵測暨更正電路。 為了要簡潔地說明依據本發明的錯誤偵測暨更正 電路如何偵測出固定邏輯零錯誤以及固定邏輯一錯誤， 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 567452 A7 B7 五、發明説明（） 圖八說明了依據本發明的一較佳實施例中所提出的錯誤 偵測暨更正電路在起始狀態下，每一個節點上的邏輯準 位之改變情形。首先在每一個節點上的邏輯準位變化被 顯示在圖八中，其中數字0代表在本週期中的零邏輯準 位，並且數字1代表在本週期中的一邏輯準位，此外箭 號代表的是由前一個週期的邏輯準位變化到其後續週期 的邏輯準位。假設所有的正反器具有重設（reSet)功能， 亦即，所有的正反器可以同時被設成低邏輯準位，並且 所有的錯誤偵測暨更正電路都在穩定狀態，使得所有的 正反器可以對掃描線充/放電，同時也可以提供後一級的 正反器之輸入。 當一個高邏輯準位由上而下依序經過正反器，而傳 輸到連接到液晶顯示器内的薄膜電晶體陣列的掃描線 時，在端點Pre-Q(前一級）以及端點q(本級）上的邏輯準 位，分別依序的由低邏輯準位到高邏輯準位，再到低邏 輯準位。在一般的狀態下，亦即，在由正反器傳輸訊號 沒有錯誤發生時，依據囷九A-囷九C中的傳輸閘67之 控制閘的邏輯準位，錯誤偵測暨更正電路的邏輯準位變 化並不會對掃描線和下一級正反器的端點D產生影響。 依據本發明的錯誤偵測暨更正電路因為具有本發 明的一較佳實施例所提出的固定邏輯零偵測裝置以及固 定邏輯一偵測裝置，所以可偵測出固定邏輯零錯誤以及 固定邏輯一錯誤，並且其原理是如下所說明。若是前一 級的正反器之輸出是高邏輯準位，則錯誤偵測暨更正電 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) .......·裝 — (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 567452 A7 B7 五、發明説明（） 路會停止在一個中間狀態之下，然後如果本級正反器的 輸出在後續的計時脈波輸入本級正反器時並不是高邏輯 準位，則定義為本級正反器中發生了固定邏輯零錯誤。 如果本級正反器的輸出是高邏輯準位，而此時其 RESET(重置）端也是高邏輯準位時，此則定義為本級正 反器中發生了固定邏輯一錯誤。另一方面而言，當本級 正反器在其正常狀況下時，固定邏輯零该測裝置以及固 定邏輯一偵測裝置的輸出都會是高邏輯準位，使得反及 閘65(參照回囷八）的輸出是低邏輯準位。若是發生了前 述一種錯誤，亦即發生了固定邏輯零錯誤或是固定邏輯 一錯誤，反及閘65的輸出會是高邏輯準位，並且此會永 久地切斷本級正反器與連接到掃描線的端點7〇之間的電 性耦合。依據前面敘述，很清楚的是當本級的正反器之 中沒有錯誤發生時，錯誤偵測暨更正電路對連接到錯誤 偵測暨更正電路的正反器之輸出並不會有任何的影響。 換句話說，儘管加上了本發明所提出的錯誤偵測暨更正 電路，正反器仍然可以正確地對於掃描線充/放電，然而 在本級正反器中發生固定邏輯零錯誤或是固定邏輯一錯 誤時，正反器與掃描線之間的電性會被隔絕。 參考囷十A ’當錯誤偵測暨更正電路的端點q 由邏輯一變成邏輯零，而端點q固定於邏輯零，就無法 由囷九B變化到圖九C,此外，在圖十a中顯示了固定 邏輯零偵測裝置60内的所有節點之邏輯準位變化情形。 藉由觀察傳輸閘67的控制閘上的邏輯準位，很明顯的 18 本紙張尺度適用中國國家標準(CNS)A4規格(21〇χ297公楚) I —Ί I I --------•裝· I (請先閲讀背面之注意事項再填寫本頁} 訂· 經濟部智慧財產局員工消費合作社印製 567452 A7 B7 五、發明説明（） 是，耦合到圖十A的錯誤偵測暨更正電路之端點 級正反器被與耦合到掃描線的端點70 · 、 j;點7 ◦電性隔絕開來。反 .......·裝·· (請先閲讀背面之注意事項再填寫本頁} 之，當錯誤摘測登更正電路的端點Q固定於邏輯一時， 亦即，當在重置（⑽t)過程進行時，即已經啟動固 輯一摘測裝置61(圖十B)，則本級正反器不能约對麵A 到端點70的掃描線進行充/放電。參照圓i〇b，很明^ 的是，下一級正反器的端點D只能由連接到端點7〇的掃 描線獲得訊號，而端點70是被連接到位於面板3〇上的 另一端之掃描線驅動器31(參照圖三）上。換句話說，在 本發明中，若是前一級正反器内發生固定邏輯零錯誤或 是固定邏輯一錯誤時，饋入到本級正反器的訊號，是由 面板上的另一側邊上之前一級正反器所提供。 經濟部智慧財產局員工消費合作社印製 例如當錯誤偵測暨更正電路被用在液晶顯示器面 板中，以電性耦合到正反器時，為了簡單說明起見，在 圖^ 中並未顯示錯誤摘測暨更正電路的細部，並且左 列正反器是在位於面板一個側邊上的掃描線驅動器之 中，而右列正反器是在位於面板另一個側邊上的另_個 掃描線驅動器之中。假設在左側掃描線驅動器中的第三 延遲型正反器，以及在右側掃描線驅動器甲的第五發生 故障’其訊號流即為顯示在圖十一中的訊號流。然而當 沒有使用錯誤偵測暨更正電路時，或者是使用習知的錯 誤偵測暨更正電路時，則在右邊的訊號流會在第六個掃 描線上中斷掉，並且其後績掃描線會因為在使用習知錯 誤偵測暨更正電路的情況下，訊號不能由右邊第五個正 19 —--- 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 567452 A7 B7 五、發明説明（） 反器傳輸到左邊第六個正反器，以致整個液晶顯示器無 法使用而報廢。總之，因為本發明所提出的錯誤偵測暨 更正電路被用來耦合到正反器和掃描線，並且具有錯誤 偵測暨更正電路和正反器的掃描線驅動器是被放置於掃 描線（掃描線匯流排）的兩端上，所以掃描線驅動器内所傳 輸之資料，可以跳過發生了固定邏輯一或是固定邏輯零 錯誤的正反器，而繼續往下級傳輸。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭 示之精神下所完成之等效改變或修飾，例如在本發明的 較佳實施例中，耦合到一掃描線兩端點的掃描線驅動器 之改變或修飾，均應包含在下述之申請專利範圍内。 元件符號說明： (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 10 面板 20 面板 30 面板 34 薄膜電晶體 36 透明電極 40 或閘 41 串接的延遲型正反器 49 多數決電路 60 固定邏輯零偵測裝置 61 固定邏輯一 偵測裝置 65 反及閘 66 反相器 67 傳輸閘 70 端點 20V. Description of the invention () The printouts made by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the logical output, the false output, the false output, the false output, and the correct version are clearly stated. I mentioned that the Chinese side sent each and every one of the above-mentioned logic schools, and the example of M and the middle of the middle and the upper and middle schools, and the middle and the middle of the middle and the middle and the middle of the middle. Achievement of the first class of road-level modification-an example of a gift festival before the application of electricity This application of electricity is the same as the one given by Shi Jia, and the truth is true and true A better position, a better position, a better position, a better position, a better position, a better position, a more accurate position, a more accurate position, and a more accurate position. The state of the electrical detection of the circuit of the opposite side of the Ming is the logic of the positive detection of the positive detection device. The wrong hair will be the wrong hair, the wrong hair will be sent according to the road. Lu Xian's original version is more, the love is there, the love is in this version. Road time change data Road one data is Zhengzheng liquid data path; according to the electricity test, change the appliance to the appliance, change the appliance to the electricity, and the more according to the electricity, the shape of the indignation, the positive and the negative, the positive and the negative, and the positive and negative illustrations cum and the Ming The sentiment is more wrong; the correction is correct, the correction is correct, the test case is changed, and the test case is changed A cum malformation B cum class C cum class A cum power B The test, the love nine test, the nine test, the ten test, the positive ten road map, the false map, the false test, the time-varying debt, the logical debt, the logical map, the logical map, the electrical error, the best detection, and the wrong device. Mistakes of misunderstanding and misalignment of misalignment, misinterpretation, mistransmission, misdelivery, mismeasurement, and detection of the miscellaneous miscellaneous devices .......: 、、 Yes ......... Φ (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X 297 mm) Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs Printed 567452 A7-B7 V. The error detection and correction circuit of the invention description () When the fixed logic 1 error occurs, the error extraction and correction of the logic level of each node on the circuit And the eleventh description of a scan line actuator having an error detection and correction circuit proposed in a preferred embodiment of the present invention, when two flip-flops are in error, the scan line (scanning Line bus). The invention of 5.5 is explained in detail because the conventionally known TFT shift registers with error detection and correction functions are based on the unilateral waist motion mode, and because The crystal yield produced by using the low temperature polycrystalline silicon process is unstable, which will cause serious problems. A preferred embodiment of the present invention proposes a liquid crystal display with error detection and correction functions without using a unilateral driving mode. For the scan line mediator, its circuit diagram is shown in Figure 6. A liquid crystal display having an error detection and correction function according to a preferred embodiment of the present invention uses, for example, a bilateral driving mode. The shift register with error detection and correction function proposed by a preferred embodiment of the present invention is in a scan line driver, and the structure of a liquid crystal display with such a scan line driver is shown in FIG. Although this structure is the same as that of the skilled artisan, it is because the shift register with error detection and correction function proposed by the present invention as shown in FIG. 6 enables it to be driven by two scan line drivers simultaneously. Scan line. According to a preferred embodiment of the present invention, the error detection and correction of the paper size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) ... Order ......... Φ (Please read the notes on the back before filling this page) 567452 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) Road D11, which The circuit diagram is shown in Figure 7. D11 is an error detection and correction circuit for a fixed logic one error or a fixed logic zero error in the output of Q12. In addition, its circuit diagram is also included in FIG. 6, in which a stuck-at-zero detection device 60 and a stuck-at-one > (the output of the chastity device 61 is electrically coupled To NAND 65. One of the inputs of the fixed logic zero detection device 60 (P re Q input) can be electrically coupled to the output of the previous level error detection and correction circuit and fixed. One input terminal of the logic-one detection device 61 is electrically coupled to the Q terminal of the flip-flop Q12 (Figure 7). The output terminal of the inverse gate 65 is fed to the inverter 66. The inverter 66 and the output of the inverting gate 65 both provide a control voltage transmission gate 67. When the output of the inverting gate 65 is at the first logic level (such as a high logic level), The signal output from the Q terminal of the first-stage flip-flop (such as the Q12) is transmitted to the D-terminal of the next-stage flip-flop (such as the Q13) as an input, and is also transmitted to Scan line driver connected to the Q terminal of the flip-flop Q12. Regardless of the input of the flip-flop When the logic value of its output is constant to logic zero, a fixed logic zero error has been defined for this flip-flop. On the other hand, regardless of the input of the flip-flop, when the logic value of its output is constant to logic one, it is defined This flip-flop has a fixed logic. An error is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In a preferred embodiment of the present invention, referring to FIG. 6, the transmission gate 67 determines the output of the Q end of the flip-flop Q12. Charge / discharge the terminal 70 connected to the scanning line. When the flip-flop Q12 is faulty, for example, if this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) A7 B7 567452 5. Invention Explanation () ...... # Packing: (Please read the precautions on the back before filling this page) A stuck-at-one fault has been printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs or When stuck-at-zerofault is fixed, the transmission gate 67 is turned off, so the flip-flop Q 1 2 has nothing to do with the scan line connected to the terminal 70. On the contrary, the input signal of the flip-flop Q13 Is connected to error detection and correction Provided by the scanning line of the circuit D11, and the error detection and correction circuit D11 'is coupled to the output of the previous level error detection and correction circuit and the output of the flip-flop Q12, so it is input to the flip-flop. The signal of Q13 is provided by the flip-flop Q12 '(previous stage) located on the other side of the panel 30 (Figure 3). "For short explanation, the circuit diagram and error detection of the error detection and correction circuit D11. The circuit diagram of the cum correction circuit D11 '(Figure 7) is the same as that of other error detection and correction circuits (not shown).' Refer to Figure VII ' The output of the flip-flop Q1 2) is fed to an error detection and correction circuit (for example, the error detection and correction circuit D 1 1). In addition, if the error detection and correction circuit (such as D11) is not faulty, the output of the D-type flip-flop of this stage (such as Q1 2) is fed to the scan line and the next-stage flip-flop ( For example, the 0 terminal of the flip-flop CM 3). In other words, the output of the error detection and correction circuit of this stage must be based on the results of the error detection and correction circuit according to a preferred embodiment of the present invention on the outputs of the current stage and the previous stage. set. According to the present invention, there is an error detection and correction circuit between every two flip-flops in the scanning line driver on one side of the panel. In order to succinctly explain how the error detection and correction circuit according to the present invention detects a fixed logic zero error and a fixed logic one error, this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 567452 A7 B7 V. Description of the Invention (8) FIG. 8 illustrates the change of the logic level of each node in the initial state of the error detection and correction circuit according to a preferred embodiment of the present invention. First, the change of the logic level at each node is shown in Fig. 8, where the number 0 represents the zero logic level in the cycle, and the number 1 represents a logic level in the cycle, and the arrow represents What is changed from the logic level of the previous cycle to the logic level of the subsequent cycle. It is assumed that all the flip-flops have a reset function, that is, all the flip-flops can be set to a low logic level at the same time, and all the error detection and correction circuits are in a stable state, making all the flip-flops The inverter can charge / discharge the scanning line, and can also provide the input of the flip-flop in the latter stage. When a high logic level passes through the flip-flops from top to bottom, and is transmitted to the scan line connected to the thin film transistor array in the liquid crystal display, at the endpoint Pre-Q (previous stage) and the endpoint q ( The logic level on this level) is sequentially from low logic level to high logic level, and then to low logic level. Under normal conditions, that is, when no error occurs in the transmission signal from the flip-flop, according to the logic level of the control gate of the transmission gate 67 in 囷 A- 囷 9C, the logic of the error detection and correction circuit is corrected. The level change does not affect the scan line and the end point D of the next level flip-flop. Since the error detection and correction circuit according to the present invention has the fixed logic zero detection device and the fixed logic one detection device provided by a preferred embodiment of the present invention, the fixed logic zero error and the fixed logic one can be detected. Is wrong, and its principle is explained as follows. If the output of the flip-flop in the previous stage is a high logic level, the error detection and correction of the paper size of the paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives 567452 A7 B7 V. Invention Description () The road will stop in an intermediate state, and then if this level of flip-flops The output of is not a high logic level when the subsequent timing pulse is input to the flip-flop of this stage, it is defined that a fixed logic zero error has occurred in the flip-flop of this stage. If the output of the flip-flop at this stage is at a high logic level, and its RESET (reset) terminal is also at a high logic level at this time, this is defined as a fixed logic-fault in the flip-flop at this stage. On the other hand, when this level of flip-flop is in its normal condition, the output of the fixed logic zero detection device and the fixed logic one detection device will both be at high logic levels, making the reverse gate 65 (refer back to 8) The output is a low logic level. If one of the foregoing errors occurs, that is, a fixed logic zero error or a fixed logic one error occurs, the output of the gate 65 will be a high logic level, and this will permanently cut off the flip-flops of this level and connect to Electrical coupling between the ends 70 of the scan lines. According to the foregoing description, it is clear that the error detection and correction circuit will not have any effect on the output of the flip-flop connected to the error detection and correction circuit when no error occurs in the flip-flop of this stage. . In other words, although the error detection and correction circuit provided by the present invention is added, the flip-flop can still charge / discharge the scan line correctly. However, a fixed logic zero error or fixed error occurs in this level of flip-flop. When logic one is wrong, the electrical property between the flip-flop and the scan line is isolated. Refer to 囷 十 A 'When the end point q of the error detection and correction circuit changes from logic one to logic zero, and the end point q is fixed at logic zero, it cannot change from 囷 9B to Figure 9C. In addition, in Figure 10a The figure shows the logic level changes of all nodes in the fixed logic zero detection device 60. By observing the logic level on the control gate of the transmission gate 67, it is obvious that the 18 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (21〇297297) I —Ί II -------- • Equipment · I (Please read the precautions on the back before filling out this page} Order · Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 567452 A7 B7 V. Description of the invention () Yes, the error detection coupled to Figure 10A and The terminal-level flip-flop of the correction circuit is electrically isolated from the terminal 70 ·, j; point 7 of the scanning line.… ............. (read the first Note: Please fill in this page again.} When the end point Q of the error detection and correction circuit is fixed at logic one, that is, when the resetting (⑽t) process is performed, the fixed-phase detection device 61 has been activated ( (Figure 10B), then the flip-flop of this stage cannot charge / discharge the scanning line from the surface A to the end point 70. With reference to circle i0b, it is clear that the end point D of the next-level flip-flop can only The signal is obtained by the scanning line connected to the terminal 70, and the terminal 70 is connected to the scanning line driver 31 (refer to FIG. 3) located on the other end of the panel 30. In other words, in the present invention, if a fixed logic zero error or a fixed logic one error occurs in the flip-flop of the previous stage, the signal fed to the flip-flop of this stage is from the other side of the panel Provided by the previous level flip-flop. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, when the error detection and correction circuit is used in a liquid crystal display panel and is electrically coupled to the flip-flop, in order to simplify the description See, the details of the error extraction and correction circuit are not shown in Figure ^, and the flip-flops on the left column are in the scan line driver located on one side of the panel, while the flip-flops on the right column are located on the other side of the panel. Among the other scan line drivers on one side. Suppose the third delay type flip-flop in the left scan line driver and the fifth failure of the scan line driver A on the right. Its signal flow is shown in The signal flow in Figure 11. However, when the error detection and correction circuit is not used, or when the conventional error detection and correction circuit is used, the signal flow on the right will be scanned in the sixth scan. The line is interrupted, and the subsequent scan line will be used because the conventional error detection and correction circuit is used, and the signal cannot be changed from the fifth on the right. 19 ----This paper standard applies to China National Standard (CNS) A4. Specifications (210X 297 mm) 567452 A7 B7 V. Description of the invention () The inverter is transmitted to the sixth flip-flop on the left, which makes the entire LCD display unusable and scrapped. In short, because of the error detection and correction proposed by the present invention The circuit is used to couple the flip-flop and scan line, and the scan line driver with error detection and correction circuit and flip-flop is placed on both ends of the scan line (scan line bus), so the scan line driver The data transmitted inside can skip the flip-flops with fixed logic one or fixed logic zero error, and continue to transfer to the lower level. The above descriptions are merely preferred embodiments of the present invention and are not intended to limit the scope of patent application for the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention, such as the In a preferred embodiment, changes or modifications of the scanning line driver coupled to the two ends of a scanning line should be included in the scope of the following patent applications. Component symbol description: (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 Panel 20 Panel 30 Panel 34 Thin film transistor 36 Transparent electrode 40 or gate 41 Delay type positive Inverter 49 Majority circuit 60 Fixed logic zero detection device 61 Fixed logic one detection device 65 Reverse gate 66 Inverter 67 Transmission gate 70 End point 20

Claims (1)

Translated fromChinese

ABCD 567452 六、申請專利範圍 申請專利範圍 1· 一種錯誤偵測暨更正電路，係用於決定是否由本級的第 一延遲型正反器（Delay-type FlipFlop: DFF)，傳送訊號 到後一級的第二延遲型正反器的輸入端，或是由本級的第 三延遲型正反器傳送訊號到該第二延遲型正反器，該錯誤 偵測暨更正電路包含： 零 第一偵測裝置，係用以相應於發生在該第一延遲型 正反器的固定邏輯零錯誤（stuck_at-zero fault)，而於該 第一偵測裝置的輸出端產生第一邏輯準位，該第一延遲型 正反器、該第二延遲型正反器該第三延遲型正反器以及該 掃描線係形成於一底材上，前一級的第四延遲型正反器之 輸出端被耦合到該第一偵測裝置之輸入端； 第二偵測裝置，係用以相應於發生在該第一延遲型 正反器的固定邏輯一錯誤（stuck-at-one fault)，而於該第 一偵測裝置的輸出端產生該第一邏輯準位； 控制訊號產生裝置，係用於在該控制訊號產生裝置 的所有輸入端呈現第二邏輯準位時，產生第一控制訊號， 在該控制訊號產生裝置的其中一輸入端呈現該第一邏輯 準位時產生第二控制訊號，該第一偵測裝置以及該第二偵 測裝置的輸出端被電性耦合到該控制訊號產生裝置的輸 入端；以及 傳輸控制裝置，係用以相應於該第一控制訊號而由 本紙張尺度適用中國國家標準(CNS)A4規格(210Χ 297公釐) ! ‘ .......·裝： (請先閲讀背面之注意事項再填寫本頁) -^τ. 經濟部智慧財產局員工消費合作社印製 567452 A8 B8ABCD 567452 6. Scope of patent application Scope of patent application 1. An error detection and correction circuit is used to determine whether the first delay-type flip-flop (DFF) of this stage sends a signal to the next stage The input terminal of the second delay type flip-flop, or the third delay type flip-flop of this level sends a signal to the second delay type flip-flop. The error detection and correction circuit includes: a zero first detection device Is to correspond to a fixed logic zero error (stuck_at-zero fault) occurring in the first delay type flip-flop, and a first logic level is generated at the output of the first detection device, the first delay Type flip-flop, the second delay-type flip-flop, the third delay-type flip-flop, and the scanning line are formed on a substrate, and the output terminal of the fourth delay-type flip-flop of the previous stage is coupled to the The input end of the first detection device; the second detection device is used to correspond to a fixed logic-error of the first delay flip-flop, The output of the test device generates the first logic Level; the control signal generating device is used to generate a first control signal when all the input terminals of the control signal generating device present a second logic level, and present the first control signal at one of the input terminals of the control signal generating device; A second control signal is generated when the logic level is reached, and the first detection device and the output terminal of the second detection device are electrically coupled to the input terminal of the control signal generation device; and the transmission control device is corresponding to This first control signal applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) from this paper size! '....... · Installation: (Please read the precautions on the back before filling this page)- ^ τ. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 567452 A8 B8六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) 該第一延遲型正反器傳送訊號到該第二延遲型正反器以 及該掃描線’該傳輸控制裝置相應於該第二控制訊號而將 該第一延遲型正反器和該第二延遲型正反器及該掃描線 之間的電性麵合切斷，然後由該第三延遲型正反器而來的 訊號被經由掃描線被傳送到該第二延遲型正反器，該擇描 線的一邊被電性耦合到位於該底材的一個側邊上的該第 一延遲型正反器’該掃描線的另一邊被電性耦合到位於該 底材的另一個侧邊上的該第二延遲型正反器，該固定邏輯 零錯誤係被定義為不論正反器之輸入為何，其輸出的邏輯 值恆為邏輯零，該固定邏輯一錯誤係被定義為不論正反器 之輸入為何，當其輸出的邏輯值恆為邏輯一，則定義此正 反器發生了固定邏輯一錯誤，複數個薄膜電晶體（Thin Film Transistor: TFT)之狀態係由該掃描線上的訊號所控 制’而該複數個薄膜電晶體的電性控制位於該底材上的畫 素内的液晶之分子的極化方向。 2·如申請專利範圍第1項之錯誤偵測暨更正電路，其中上 述之第一偵測裝置、該第二偵測裝置、該控制訊號產生裝 置以及該傳輸控制裝置形成於該底材上，該底材係為下列 其中之一：矽底材以及透明底材。 經濟部智慧財產局員工消費合作社印製 3_如申請專利範圍第2項之錯誤偵測暨更正電路，其中上 述之第一偵測裝置、該第二偵測裝置、該控制訊號產生裝 置以及該傳輸控制裝置係以低溫複晶矽（L〇w Temperature Polycrystalline Silicon : LTPS)製程所整合 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ABCD 567452 六、申請專利範圍 製造於該透明底材上。 4. 如申請專利範圍第1項之錯誤偵測暨更正電路，其中上 述之掃描線被電性耦合到該複數個薄膜電晶體。 5. 如申請專利範圍第1項之錯誤偵測暨更正電路，其中上 述之第一偵測裝置包含：第一反及閘（NAND gate)、第一 電晶體、第二電晶體、第三電晶體、第四電晶體、第五電 晶體、第一反相器以及第二反相器。 6. 如申請專利範圍第1項之錯誤偵測暨更正電路，其中上 述之第二偵測裝置包含：第六電晶體、第七電晶體以及第 二反及閘。 (請先閲讀背面之注意事項再填寫本頁) 專 請制 申控 如之 7.述 利 第 訊 上相 中反 其三 路第 電及 正以 更閘 暨及 測反 偵三 誤第 錯含 之包 項置 1裝 生 圍t f ^ 制 控 該 器 置 裝二 制第 以 控該 輸及 傳以 該號 到訊 合制 耦控 性一 被該 端供 出提 輸置 的裝 置制 裝控 生輸 產傳 號該 訊對 號 訊 制 控 經濟部智慧財產局員工消費合作社印製 路 正 更 暨 測 誤控位 錯二準 之第輯 項該邏 7及低 第以一 圍號及 範訊以 利制位 專控準 請一輯 申第邏 如之高 8述一 中 其 的 號 訊 制 上含 中包 其個 上 中 其 路 Anil ^g 正 更 暨 測 摘 誤 錯 之 項 1 第 圍 範 利 專 請 申 如 23 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 567452 8 8 8 8 1 ABCD 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 述之傳輸控制裝置係為一傳輸閘，其包含具有第一控制 閘、第二控制閘、一輸入端以及一輸出端的互補式金氧半 場效電晶體（CMOS)傳輸閘，在同一時間中只有該第一控 制訊號或該第二控制訊號的其中一個，會被電性耦合到該 傳輸控制裝置的該第一控制閘以及該第二控制閘上。 10. 如申請專利範圍第9項之錯誤偵測暨更正電路，其中 上述之互補式金氧半場效電晶體（CM〇S)傳輸閘在該第一 控制訊號被耦合到該第一控制閘以及該第二控制閘時，於 該互補式金氧半場效電晶體傳輪閘的輸入端和輸出端之 間呈現電性導通。 11. 如申請專利範圍第9項之錯誤偵測暨更正電路，其中 上述之互補式金氧半場效電晶體（CM0S)傳輸閘在該第二 控制訊號被耦合到該第一控制閘以及該第二控制閘時，於 該互補式金氧半場效電晶體傳輸閘的輸入端和輸出端之 間呈現電性絕緣。 12. 如申請專利範圍第1項之錯誤偵測暨更正電路，其中 上述之第一邏輯準位係為一低邏輯準位，該第二邏輯準位 係為一高邏輯準位。 13. —種具錯誤偵測暨更正功能之液晶顯示器（Ljquid Crystal Display ·· LCD)之驅動裝置，該驅動裝置包含： 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁} 裝 567452 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 ------------ 、申請專利範圍 第一驅動元件，係用於將訊號由前一級延遲型正反 器傳送到本級延遲型正反器再傳送到後一級延遲型正反 器； 第二獎動元件，係用於將訊號由前一級延遲型正反 器傳送到本級延遲型正反器再傳送到後一級延遲型正反 器； 複數個掃描線，係用於電性耦合該第一驅動元件内 與該第二驅動元件内同一級的延遲型正反器，該第一驅動 元件以及該第二驅動元件的任何一個都包含複數個延遲 型正反器以及複數個錯誤偵測暨更正電路，該複數個錯誤 偵測暨更正電路的每一個輸入端被耦合到該複數個延遲 型正反器中本級延遲型正反器以及前一級延遲型正反器 的輸出端，該複數個錯誤偵測暨更正電路的每一個輸出端 被電性耦合到該複數個掃描線中的其中一條掃描線以及 複數個正反器中位於後一級其中一個正反器，該錯誤偵測 暨更正電路係用於決定是否由本級的第一延遲型正反器 (Delay-type FlipF lop: DFF)，傳送訊號到後一級的第二 延遲型正反器的輸入端，或是由本級的第三延遲型正反器 傳送訊號到該第二延遲型正反器，該錯誤偵測暨更正電路 包含： 第一偵測裝置，係用以相應於發生在該第一 延遲型正反器的固定邏輯零錯誤（stuck-at-zero fault), 而於該第一偵測裝置的輸出端產生箄一邏輯準位，該第一 延遲型正反器、該第二延遲型正反器該第三延遲型正反器 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公~' -- (請先閲讀背面之注意事項再填寫本頁) 567452 A8 B8 C8 D8 六、申請專利範圍 以及該掃描線係形成於一底材上，前一級的第四延遲型正 反器之輸出端被耦合到該第一偵測裝置之輸入端； 第二偵測裝置，係用以相應於發生在該第一 延遲型正反器的固定邏輯一錯誤（stuck-at-one fault)，而 於該第二偵測裝置的輸出端產生該第一邏輯準位； 控制訊號產生裝置，係用於在該控制訊號產 生裝置的所有輸入端呈現第二邏輯準位時，產生第一控制 訊號，在該控制訊號產生裝置的其中一輸入端呈現該第一 邏輯準位時產生第二控制訊號，該第一偵測裝置以及該第 二偵測裝置的輸出端被電性耦合到該控制訊號產生裝置 的輸入端；以及 經濟部智慧財產局員工消費合作社印製 :·· ..........·裝丨· - - (請先閲讀背面之注意事項再填寫本頁) 傳輸控制裝置，係用以相應於該第一控制訊 號而由該第一延遲型正反器傳送訊號到該第二延遲型正 反器以及該掃描線’該傳輸控制裝置相應於該第二控制訊 號而將該第一延遲型正反器和該第二延遲型正反器及該 掃描線之間的電性耦合切斷，然後由該第三延遲型正反器 而來的訊號被經由掃描線被傳送到該第二延遲型正反 器’該掃描線的一邊被電性耦合到位於該底材的一個側邊 上的該第一延遲型正反器’該掃描線的另一邊被電性耦合 到位於該底材的另一個側邊上的該第二延遲型正反器，該 固定邏輯零錯誤係被定義為不論正反器之輸入為何，其輸 出的邏輯值怪為邏輯零’該固定邏輯一錯誤係被定義為不 論正反器之輸入為何，當其輸出的邏輯值恆為邏輯一，則 定義此正反器發生了固定邏輯一錯誤，複數個薄膜電晶體 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公复) 567452 8 8 8 8 1 ABCD 六 »ΗΊ 3 ^ 二相 專 反 請？ 一 申體第 圍 β. If第 量 晶、 器 t&sD ignr 三 第 器 相 反 體器 晶相 電反 五四 第第 、 及 體以 晶器 電相 四反 第三 體第 晶、 19. 如申請專利範圍第13jR之驅動裝置，其中上述之第 二偵測裝置包含··帛六電晶體、第七電晶體、第五反相器 以及第二反及閘。 20. 如申請專利範圍第13項之媒動裝置，其中上述之控 制訊號產生裝置包含第三反及閘以及第三反相器，該控制 訊號產生裝置的輸出端被電性耦合到該傳輸控 對該傳輸控制裝置提供該第一炝制却祙” ^ 捉供涊第控制訊號以及該第二控制 訊號。 21. 如申請專利範圍第2Q$之堪動裝置，其中上述 一控制訊號以及該第二控制訊號的其中一 輯準位以及一低邏輯準位。 包含高邏 22. 如申請專利範圍第13項之驅動裝置，其中上述之 輸控制裝置係為一傳輸閑，其包含具#卜控㈣、第2 控制閘、一輸入端以及一輸出端的互補式金氧半場效 體(CMOS)傳輸閘’在同一時間中只有該第一控制訊號： 該第二控制訊號的其中一個，會被電性耦合到該傳輪控制 裝置的該第一控制閘以及該第二控制閘上。 23. 如申請專利範圍第22項之驅動裝置，其中上述之互 28 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) !^μψ — — — — — — I #· (請先閲讀背面之注意事項再填寫本頁) ·. 經濟部智慧財產局員工消費合作社印製Sixth, the scope of patent application (please read the precautions on the back before filling this page) The first delay type flip-flop sends signals to the second delay type flip-flop and the scanning line 'The transmission control device corresponds to the first Two control signals to cut off the electrical plane between the first delay type flip-flop, the second delay type flip-flop and the scan line, and then the signal from the third delay type flip-flop is It is transmitted to the second delay type flip-flop via a scanning line, and one side of the selective line is electrically coupled to the first delay type flip-flop located on one side of the substrate. The other side of the scanning line Is electrically coupled to the second delay type flip-flop located on the other side of the substrate, the fixed logic zero error is defined as the logic value of the output is constant regardless of the input of the flip-flop Zero, the fixed logic-one error is defined as a fixed logic-one error that occurs in the flip-flop, regardless of the input of the flip-flop. Film Transistor: TFT) The state is controlled by a signal on the scanning line, and the electrical properties of the plurality of thin film transistors control the polarization direction of the molecules of the liquid crystal in the pixels on the substrate. 2. If the error detection and correction circuit of item 1 of the patent application scope, wherein the first detection device, the second detection device, the control signal generating device and the transmission control device are formed on the substrate, The substrate is one of the following: a silicon substrate and a transparent substrate. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3_If the patent application scope of the second error detection and correction circuit, the above-mentioned first detection device, the second detection device, the control signal generation device and the The transmission control device is integrated with the Low Temperature Polycrystalline Silicon (LTPS) process. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 567452 6. The scope of the patent application is manufactured in this transparent On the substrate. 4. For example, the error detection and correction circuit of the scope of patent application, wherein the scanning line is electrically coupled to the plurality of thin film transistors. 5. For example, the error detection and correction circuit of the first patent application range, wherein the above-mentioned first detection device includes: a first NAND gate, a first transistor, a second transistor, and a third transistor. A crystal, a fourth transistor, a fifth transistor, a first inverter, and a second inverter. 6. For the error detection and correction circuit of the first patent application scope, the second detection device mentioned above includes a sixth transistor, a seventh transistor, and a second inverter and a gate. (Please read the precautions on the back before filling out this page.) Please apply for the application control as described in the 7th. The package item is set to 1 to install the surrounding tf ^ to control the device to install the second system to control the input and pass the number to the coupling system. The product number is the number of the item that is controlled by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative of the Ministry of Economic Affairs. The control of position control is strictly required to apply for a series of applications, such as the 8th part of the signal system, including the signal system, including the middle of the road, Anil ^ g is correct, and the wrong item 1 is measured. Please apply specifically for 23 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 567452 8 8 8 8 1 ABCD Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The transmission control device described in the scope of patent application Is a transmission gate including A control gate, a second control gate, an input terminal and an output terminal of a complementary metal-oxide-semiconductor field-effect transistor (CMOS) transmission gate. At the same time, only one of the first control signal or the second control signal will be transmitted. Electrically coupled to the first control gate and the second control gate of the transmission control device. 10. If the error detection and correction circuit of item 9 of the patent application scope, wherein the complementary metal-oxide-semiconductor field-effect transistor (CMOS) transmission gate is coupled to the first control gate at the first control signal, and During the second control gate, there is electrical conduction between the input terminal and the output terminal of the complementary metal-oxide-semiconductor half-field-effect transistor wheel brake. 11. If the error detection and correction circuit of item 9 of the patent application scope, wherein the above-mentioned complementary metal-oxide-semiconductor field-effect transistor (CM0S) transmission gate is coupled to the first control gate and the first When the two control gates are used, electrical insulation is present between the input end and the output end of the complementary metal-oxide-semiconductor half-field-effect transistor transmission gate. 12. For the error detection and correction circuit of the first patent application range, wherein the first logic level is a low logic level and the second logic level is a high logic level. 13. —A driving device for a liquid crystal display (Ljquid Crystal Display ·· LCD) with error detection and correction functions. The driving device contains: This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) (Please Please read the notes on the back before filling in this page} Installed 567452 Printed by A8 B8 C8 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The signal is transmitted from the delay-type flip-flop of the previous stage to the delay-type flip-flop of the current stage and then to the delay-type flip-flop of the latter stage; the second moving element is used to transmit the signal from the delay-type flip-flop of the previous stage The delay-type flip-flops to the current stage are then transmitted to the delay-type flip-flops of the subsequent stage; the plurality of scanning lines are used to electrically couple the delay-type flip-flops of the same stage in the first driving element and in the second driving element. Each of the first driving element and the second driving element includes a plurality of delay type flip-flops and a plurality of error detection and correction circuits, and each input of the plurality of error detection and correction circuits Terminals are coupled to the output terminals of the delay-type flip-flops of the plurality of delay-type flip-flops and the delay-type flip-flops of the previous stage, and each output terminal of the plurality of error detection and correction circuits is electrically coupled To one of the plurality of scanning lines and one of the plurality of flip-flops located in the latter stage, the error detection and correction circuit is used to determine whether the first delay flip-flop of this stage is used (Delay-type FlipF lop: DFF), send the signal to the input terminal of the second delay type flip-flop in the latter stage, or send the signal to the second delay type flip-flop by the third delay type flip-flop in this stage The error detection and correction circuit includes: a first detection device for responding to a stuck-at-zero fault of the first delay-type flip-flop; The output end of the detection device generates a first logic level, the first delay type flip-flop, the second delay type flip-flop, and the third delay type flip-flop. The paper size applies to the Chinese National Standard (CNS) A4 specification. (210x297 male ~ '-(Please read the back first Please fill in this page again) 567452 A8 B8 C8 D8 6. The scope of patent application and the scanning line are formed on a substrate, the output of the fourth delay type flip-flop in the previous stage is coupled to the first detection The input end of the device; the second detection device is used to correspond to the fixed logic-error of the first delay type flip-flop, and the output of the second detection device The control signal generating device is used to generate a first control signal when all the input terminals of the control signal generating device present a second logic level. One of the control signal generating devices is When the input terminal presents the first logic level, a second control signal is generated, and the first detection device and the output terminal of the second detection device are electrically coupled to the input terminal of the control signal generation device; and the wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau: ................. Equipment 丨---(Please read the precautions on the back before filling this page) The transmission control device is used to correspond to the Control message The first delay-type flip-flop transmits a signal to the second delay-type flip-flop and the scan line. The transmission control device corresponds to the first delay-type flip-flop and the first delay-type flip-flop corresponding to the second control signal. The electrical coupling between the two delay type flip-flops and the scanning line is cut off, and then the signal from the third delay type flip-flop is transmitted to the second delay type flip-flop through the scanning line. One side of the scan line is electrically coupled to the first delay type flip-flop on one side of the substrate. The other side of the scan line is electrically coupled to the other side of the substrate. For the second delay type flip-flop, the fixed logic zero error is defined as the logic value of the output is strangely zero regardless of the input of the flip-flop. The fixed logic one error is defined as the flip-flop. What is the input? When the logic value of the output is constant to logic one, a fixed logic one error has occurred in the flip-flop. Multiple thin-film transistors are used. The paper size is in accordance with China National Standard (CNS) A4 (210X297). 567452 8 8 8 8 1 ABCD VI » ΗΊ 3 ^ Two Phases Special Reverse Please? The first body around β. If the amount of crystal, the device t & sD ignr the third body opposite the crystal phase of the electric phase of the May Fourth Phase, and the body of the crystal phase the fourth phase of the third body crystal, 19. Such as The driving device with the scope of application for patent No. 13jR, in which the above-mentioned second detection device includes a six-transistor, a seventh transistor, a fifth inverter, and a second inverter gate. 20. For example, the media motion device of the scope of application for patent No. 13, wherein the above-mentioned control signal generating device includes a third inverter and a third inverter, and the output end of the control signal generating device is electrically coupled to the transmission control device. The first control signal and the second control signal are provided to the transmission control device. ^ The control signal and the second control signal are provided for the transmission control device. 21. For example, the above-mentioned one control signal and the first control signal and the first control signal One of a series of control signals and a low logic level. Includes high logic 22. If the driving device of the 13th patent application scope, the above-mentioned output control device is a transmission idle, which contains # 卜 控㈣, the second control gate, an input terminal and an output terminal of a complementary metal-oxide-semiconductor half field effect (CMOS) transmission gate 'only the first control signal at the same time: one of the second control signal will be electrically To the first control gate and the second control gate of the wheel control device. 23. If the driving device of the scope of patent application No. 22, wherein the above-mentioned 28 paper sizes are suitable ! Chinese National Standard (CNS) A4 size (210X297 public Chu) ^ μψ - - - - - - I # · (Please read the Notes on the back to fill out this page) · Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed.567452 A8 B8 C8 ___D8 申請專利範圍 補式金氧半場效電晶體（CM OS)傳輸閘在該第一控制訊號 被耦合到該第一控制閘以及該第二控制閘時，於該互補式 金氧半場效電晶體傳輸閘的輸入端和輸出端之間呈現電 性導通。 24·如申請專利範圍第22項之驅動裝置，其中上述之互 補式金氧半場效電晶體（CMOS)傳輸閘在該第二控制訊號 被耦合到該第一控制閘以及該第二控制閘時，於該互補式 金氧半場效電晶體傳輸閘的輸入端和輸出端之間呈現電 性絕緣。 25.如申請專利範圍第13項之驅動裝置，其中上述之第 一邏輯準位係為一低邏輯準位，該第二邏輯準位係為一高 邏輯準位。 • r 1 --------裝 I I t-· {請先閱讀背面之注意事項再填寫本ί -訂· 經濟部智慧財產局員工消費合作社印製567452 A8 B8 C8 ___D8 Patent Application Complementary Metal Oxide Half Field Effect Transistor (CM OS) Transmission Gate When the first control signal is coupled to the first control gate and the second control gate, the complementary metal oxide The input terminal and the output terminal of the half field effect transistor transmission gate are electrically connected. 24. The driving device according to item 22 of the patent application, wherein the complementary metal-oxide-semiconductor field-effect transistor (CMOS) transmission gate is coupled when the second control signal is coupled to the first control gate and the second control gate. Electrical insulation is present between the input end and the output end of the complementary metal-oxide-semiconductor half-field-effect transistor transmission gate. 25. The driving device according to item 13 of the patent application, wherein the first logic level is a low logic level and the second logic level is a high logic level. • r 1 -------- install I I t- · {Please read the precautions on the back before filling in this order.29 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)29 This paper size applies to China National Standard (CNS) A4 (210X297 mm)