512653 A7 B7 五、發明說明（ 技術領域 本發明係關於一種有利於超高密度配線的多層電路基板 或在其多層電路基板上再形成積層配線層的多層印刷配線 板及包含裝載於這些板上的半導體零件的半導體裝置，特 別是提出一種藉由將有充填通路孔的單面電路基板多數片 或以兩面電路基板爲核心而在其兩面分別層疊單面電路基 板，將其所層疊的電路基板彼此透過黏接劑一併加熱加壓 所形成的多層電路基板，或者在其多層電路基板的至少一 面形成積層配線層的多層印刷配線板及使用這些板的半導 體裝置。 一 背景技術 近幾件封裝1C晶片的封裝基板與伴隨電子工業進步的電 子機器小型化或鬲速化對應，要求精細圖案高密化及可靠 性高者。 作烏這種封裝基板，在1997年i月號的「表面封裝技 術」揭π 了在多層核心基板兩面形成積層多層配線層的技 術。 然而，在關於上載習知技術的封裝基板，多層核心基板 内的導體層和積層配線層的連接係在多層核心基板表面設 置k通孔配線的内層焊接點，使此内層焊接點連接通路孔 而進仃。因此，通孔的焊接區（land)形狀成爲圓形或鐵製 亞鈐形，其内層焊接點區域阻礙通孔配置密度的提高，在 通孔开成數有一足限度。因此，爲謀求配線高密度化而使 核心基板多層化，就有外層的積層配線層不能和多層核心 (請先閱讀背面之注意事項再填寫本頁) .· 經濟部智慧財產局員工消費合作社印製 a — — — — — — — — I ΙΙ1Ι1ΙΙΙΙΙΙΙΙ1 — — — — — — — — — -4- 512653 A7 B7 五、發明說明（2 ) 基板内的導體層確保充分電氣連接的問題。 又，關於這種問題點，本發明等以前作爲特願平第1〇_15346 號（特開平1 1-214846號），提出了其改善方法。 根據這種改善提案的多層印刷配線二，係在内層有導體 層的多層核心基板上形成交互疊層間樹脂絕緣層和導體層 而以通路孔連接各導體層間的積層配線層而成，係下述結 構在夕層核〜基板形成通孔，在該通孔充填填料，同時 覆蓋該填料從通孔的露出面而形成導體層，在該導體層連 接通路孔；藉此，通孔的配置密度提高，透過高密度化的 通孔可確保和多層化的核心基板内的導體電路的連接。 然而，這種結構的多層印刷配線板的通孔係在多層化的 核心基板用穿孔器等開貫通孔，在該貫通孔壁面及基板表 面施以無電鍍所形成，所以考慮其開口性或經濟性，可形 成的通孔開口徑下限爲3〇〇//m程度，要實現滿足現在電子 產業界要求之類的超高密度配線，期望開發爲了得到 50〜250 Am程度的更小開口徑和更窄的通孔焊接區間距的 技術。 於疋’本發明者們思索到：若互相層疊多數片電路基 板，該電路基板在由硬質材料構成的芯材單面或兩面有導 體電路，、形成從其單面貫通芯材而達到導體電路的充填通 路孔而成，透過黏接劑藉由一併加熱加壓形成多層核心基 板丨不必在夕層核心基板設置通孔，透過形成於多層核 “基板的充填通路孔和形成於其正上方的積層配線層内的 通路孔，可充分確保和多層核心基板内的導體電路彼此及 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) ·# 經濟部智慧財產局員工消費合作社印製 訂---------線 ---------A-------------- 512653 五、發明說明（3 形成於多層核心基板内的導體電路和多層核心基板上的積 層配線層的電氣連接。 此外，在沒種多層電路基板最外側的表面裝載⑶晶片等 f種私子零件’就裝載其電子零件的方法而言，可列舉腳 * (pin)封裝万<··先在形成於最外㈣面的導體電路上的 預足位置使爲了插入電子零件端子部的零件孔或在包圍該 零件孔之處具有比零件孔直徑稍大的直徑的連接用焊接區 形成:在此處利用焊接連接電子零件的引線群；或，表面 封裝方式··在使其形成於導體電路上的預定位置的焊接區 上預先塗佈焊糊’電子零件端子部接觸於焊糊般地載置 後，藉由在保持於焊錫熔化的溫度範圍内的氣氛内使其回 流，連接電子零件等。 然而，右是如上述的方法，在導體電路上設置有適度大 ^直徑的焊接區是不可缺少的。可是，隨著近幾年電子機 益小型化、高功能化的要求，電子零件裝載數變多，焊接 區總面積就不可忽視程度變大，成爲高密度化的阻礙要 因。 此外，爲了連接電子零件的焊接作業時，預先塗佈爲了 防止焊錫流到不必要處，發生短路、斷線的抗焊劑也是不 可缺少的。因此，需要考慮抗焊劑印刷時的位移誤差，在 配線間估計餘裕設計，此亦成爲高密度化的阻礙要因。 發明之揭示 本發明係爲了解決習知技術具有的上述課題所開發的， 作爲其目的之處在於提出可高密度配線化及高密度封裝化 -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) if. 訂---------線- 經濟部智慧財產局員工消費合作社印製 512653 體 A7 五、發明說明（4 ) 的夕層電路基板或多層印刷配線板及使用這些板的半 裝置。 子 發明者們對實現上述目的專心研究的杜 於下的db〜 九]、、口果，想到以顯示 於下的内各爲構成要旨的發明。即， ⑴本發明之多層電路基板’係透過黏接劑層層疊多數片 基板’該電路基板在絕緣性硬質基材單面或兩面有導 =電路’在貫通此絕緣性硬質基材而達料體電路的開口 :无填導電性物質而成的通路孔’由_併加熱加 成，其特徵在於： y 上述所層疊的多數電路基板中，在位於最外侧的—方兩 路基板表面形成位於上述通路孔正上方而電氣連接於其二 路^的導電性突起，而在位於最外侧的他方電路基板表面 配位於上述通路孔正上方而電氣連接於其通路孔的導 性腳端或球者。 (2)此外，本發明之多層電路基板，係透過黏接劑層分別 層疊多數片單面電路基板：在絕緣性硬質基材單面有導體 電路，在貫通此絕緣性硬質基材而達到前述導體電路的^ 口有充填導電性物質而成的通路孔；&，單面電路基板： 在絕緣性硬質基材單面有導體電路，有貫通此絕緣性硬質 基材而達到前述導體電路的開口；由一併加熱加壓所形 成’其特徵在於： 前述所層疊的多數電路基板中，在位於最外側的一方電 路基板表面形成位於上述通路孔正上方而電氣連接於其通 路孔的導電性突起，在位於最外側的他方電路基板開口内 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 11.---U---------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 512653 A7 五、發明說明（5 ) =設電氣連接於其電路基板的導體電路的導電性腳端或球 在上述⑴所載之多層電路基板，最好前述多數電路基板 !署=最外側的一方電路基板表面覆蓋其導體電路而 〜抗绛層’在通路孔正上方形成連接於從形成於立抗 層的開口露出的導體層/通路孔之類的導電性突起/，、而 位於最外側的他方電路基板表面也覆蓋其導體電路而設置 =層，在通路孔正上方配設連接於從形成於其 開口露出的導體層/通路孔之類的導電性腳端或球。 在上述⑴或(2)所載之多層電路基板，最好形成於各電路 基板的鄰接通路孔間的距離係隨著從前述—方電路基板向 他方電路基板變大般地所形成。 。 (3) 本發明之半導體裝置，其特徵在於：包含上述⑴ f載之多層電路基板和電氣連接於形成於其多層電路基板 最外侧-彳電路|板的導電十生突起《電子零件而成者。 在上述（3)所載〈半導體裝置，最好在裝載電子零件的電 路基，的周邊部配置加強條，同時形成於與其電路基㈣ 向的取外側電路基板的通路孔中，對於在於與電予零件裝 載位置對向的位置的通路孔電氣連接片狀電容器。 (4) 此外’本發明之半導體裝置，係包含多層電路基板： 透㈣接f層層叠多數片電路基板，該電路基板在絕緣性 硬質基材單面或兩面有導體電路，在貫通此絕緣性硬質基 材而達到前述導體電路的開口有充填電解鍍層而成的通路 孔，與其通路孔位置對應，有電氣連接於其通路孔的突起 (請先閱讀背面之注意事項再填寫本頁) 訂---------線- 經濟部智慧財產局員工消費合作社印製 -8- M2653 五、發明說明（6 ) 2導併加熱加壓所形成；及，lsi晶片等電子零 牛·：：連接於位於其多層電路基板最外側的電路基板而 成，其特徵在於： 在位於前述最外側的一方電路基板表面形成位於前述通 路孔正上万而電氣連接於其通路孔的導電性突起，同時對 於其導電性突起電氣連接前述電子零件， 在位於和裝載前述電子零件的電路基板在於相反側的最 外側的電路基板表面，對於在於前電子零件正下方的通路 孔電氣連接片狀電容器者。 在上述（4)所載之半導體裝置，最好在裝載零子零件的電 路基板周邊部黏接、固定爲了防止基板勉曲的加強條。 (5)本發明之多層電路基板，係在内層有導體電路的多層 核心基板單面或兩面交互層疊層間樹脂絕緣層和導體層， 形成以通路孔連接各導體層間的積層配線層而成，其特徵 在於·· 上述多層核心基板係透過黏接劑層層疊多數片電路基 板，该電路基板在絕緣性硬質基材兩面或單面有導體電 路，在5通此絕緣性硬質基材而達到前述導體電路之孔有 充填導電性物質而成的通路孔，由一併加熱加壓所形成 者。 在上述（5)所載之多層電路基板，最好在多層核心基板兩 面形成積層配線層，在構成積層配線層一方的最外側導體 層表面設置焊錫突起，同時在構成上述積層配線層他方的 最外側導體層表面設導電性腳端或球。 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 · I ϋ I I ϋ n H 一-04» I ϋ I I I I I I n n u I I n n I I Γ I 1 I I I I I n 1 n u 1 512653 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（7 、此外，提供一種多層印刷配線板·1由以抗烊層覆蓋構 成積層配線層的最外側導體層，將從設於其抗烊的開口露 出的最外側導體層形成於導體烊接區（或連接用端子形 態），適合作爲母板。 而y在上述（5)所载之多層電路基板，最好在多層核心 土才單面/成積層配線I，在積層酉己線層i外側的導體層 表面配設位於通路孔正上方、連接於包含LSI等半導體晶 片的電子零件的焊錫突起，而在露出於多層化核心基板他 万表面的導體電路上配設位於前述充填通路孔正上方、連 接於母板的導電性腳端或球。此外，最好以抗焊層覆蓋構 成積層配線層的最外側導體層及多層核心基板他面，在從 設於其抗焊層的開口露出的最外側導體層一方形成導體焊 接區：在露出於多層核心基板他方表面的導體電路上形成 位於前述域it路孔正W、連接的母板的導諸腳端或 球。 在上述⑴〜⑺所載之多層電路基板，最好導電性物質是 由電解電艘處理所形成的鏡金屬層或由金屬粒子和熱硬化 性樹脂或熱可塑性樹脂構成的導電性糊。 在上述⑴〜⑺所載之多層電路基板，最好構成多層核心 :板的各電路基板形成與其通路孔位置對應、電氣連接於 ”通路孔的突起狀導體，而且最好該突起狀導體 糊形成。 再者，在上述（1H5)所載之多層電路基板，最好積層配 線層的通路孔-部分位㈣成0層核心基板的通路孔正 (請先閱讀背面之注意事項再填寫本頁) · I I I I — I I ^ ' — — — III — — · -10- 512653512653 A7 B7 V. Description of the Invention (Technical Field) The present invention relates to a multilayer circuit board that is advantageous for ultra-high density wiring or a multilayer printed wiring board on which a multilayer wiring layer is further formed, and a multilayer printed wiring board including these boards. In particular, a semiconductor device for a semiconductor component is proposed, in particular, a single-sided circuit board is laminated on both sides of the single-sided circuit board with a plurality of single-sided circuit boards or via two-sided circuit boards as cores, and the stacked circuit boards are mutually A multilayer circuit substrate formed by applying heat and pressure together through an adhesive, or a multilayer printed wiring board in which a multilayer wiring layer is formed on at least one side of the multilayer circuit substrate, and a semiconductor device using these plates. BACKGROUND ART A few packages 1C The package substrate of the chip corresponds to the miniaturization or acceleration of electronic equipment accompanying the advancement of the electronics industry, and requires a fine pattern with high density and high reliability. As a package substrate of this type, the "surface packaging technology" of the 1997 issue The technique of forming a multilayer multilayer wiring layer on both sides of a multilayer core substrate is disclosed. On the packaging substrate of the conventional technology, the connection between the conductor layer and the multilayer wiring layer in the multilayer core substrate is provided by the inner layer solder joints of the k through-hole wiring on the surface of the multilayer core substrate, so that the inner layer solder joints are connected to the via holes. Therefore, the shape of the land of the through hole is circular or iron-shaped, and the inner joint area of the through hole hinders the increase of the density of the through hole. There is a limit on the number of through holes. Therefore, in order to achieve high wiring Density makes the core substrate multi-layered, and there is an outer multilayer wiring layer that cannot be combined with the multi-layered core (please read the precautions on the back before filling out this page). · Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs a — — — — — — — — I ΙΙ11Ι1ΙΙΙΙΙΙΙΙΙΙ1 — — — — — — — — — — 512 653 A7 B7 V. Description of the invention (2) The problem that the conductor layer in the substrate ensures sufficient electrical connection. Furthermore, regarding this problem, the present invention According to the previous Japanese Patent Application No. 10-15346 (Japanese Patent Application No. 1-214846), an improvement method has been proposed. Multi-layer printing based on this improvement proposal Wiring 2, which is formed by forming an interlayer resin insulation layer and a conductor layer on a multilayer core substrate with a conductor layer on the inner layer, and connecting the conductor layers between the conductor layers with via holes. The following structure is formed from the core to the substrate. A via hole is filled with filler in the via hole, while covering the exposed surface of the filler from the via hole to form a conductor layer, and a via hole is connected to the conductor layer; thereby, the arrangement density of the via hole is increased, and the via hole having a higher density is transmitted. The connection to the conductor circuit in the multilayer core substrate can be ensured. However, the through hole of the multilayer printed wiring board having such a structure is a through hole formed in the multilayer core substrate with a perforator or the like, and the through hole wall surface and the substrate The surface is formed by electroless plating, so considering its openness or economy, the lower limit of the opening diameter of the through-holes that can be formed is about 300 // m. To achieve ultra-high-density wiring that meets the requirements of the current electronics industry, It is desired to develop a technology for obtaining a smaller opening diameter of 50 to 250 Am and a narrower pitch of through-hole pads. Yu Yu's inventors thought that if a plurality of circuit substrates are stacked on each other, the circuit substrate has a conductor circuit on one or both sides of a core material made of a hard material, and a conductor circuit is formed through the core material through the single surface. The multi-layer core substrate is formed by heating and pressing together through the adhesive. It is not necessary to set a through-hole in the core core substrate, and it is through the filling via hole formed on the multi-layer core substrate and formed directly above it. The via holes in the multilayer wiring layer can fully ensure that the conductor circuits in the multi-layer core substrate and each other and the paper size are applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 public love) (Please read the note on the back first Please fill in this page for matters) · # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --------- line --------- A ------------ -512653 V. Description of the invention (3 Electrical connection between the conductor circuit formed in the multi-layer core substrate and the multilayer wiring layer on the multi-layer core substrate. In addition, f kinds of private materials such as ⑶ chips are mounted on the outermost surface of the multi-layer circuit substrate. Sub-parts' then load their electronics In terms of the method of the component, a pin * (pin) package can be listed. First, at a pre-foot position on the conductor circuit formed on the outermost surface, a component hole for inserting a terminal portion of an electronic component or surrounding the component is provided. The hole where the hole has a diameter slightly larger than the hole diameter of the part is formed: Here, the lead group of the electronic part is connected by soldering; or, the surface-mount method is formed at a predetermined position on the conductor circuit Solder paste is applied to the soldering area in advance. The terminal parts of the electronic components are placed in contact with the solder paste, and the electronic parts are connected by reflow in an atmosphere maintained within the temperature range in which the solder melts. However, the right is As described above, it is indispensable to provide a moderately large welding area on the conductor circuit. However, with the requirements of miniaturization and high functionality of electronic machines in recent years, the number of electronic component loadings has increased, and welding has been performed. The total area of the area must not be neglected, and it becomes a factor hindering the increase in density. In addition, during soldering operations to connect electronic parts, it is pre-coated to prevent solder from flowing to unnecessary places. It is also indispensable for the solder resist to be short-circuited or disconnected. Therefore, it is necessary to consider the displacement error during solder resist printing and estimate the margin design in the wiring room. This has also become a hindrance factor for high density. DISCLOSURE OF THE INVENTION The present invention aims to solve the problem. Developed by the above-mentioned subject of conventional technology, the purpose is to propose high-density wiring and high-density encapsulation-6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) if. Order --------- Line-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 512653 Body A7 V. The description of the invention (4) Circuit board or multilayer printed wiring board and half device using these boards. The inventors have devoted themselves to the above research to achieve the above-mentioned objectives of the following db ~ 9], and the fruit, and thought of the invention which consists of the contents shown below. That is, the multi-layer circuit substrate of the present invention is “a plurality of substrates are laminated through an adhesive layer. The circuit substrate has a conductive layer on one or both sides of the insulating hard substrate = circuits” and passes through the insulating hard substrate to achieve the material. Opening of the bulk circuit: Via holes made of non-filled conductive material are added by heating and are characterized by: y Among the majority of the above-mentioned stacked circuit boards, the outermost-square two-way substrate surfaces are formed on The conductive protrusion directly above the via hole is electrically connected to the conductive protrusion of the second circuit, and the conductive leg or ball that is directly above the via hole and is electrically connected to the via hole is arranged on the outermost circuit board surface. . (2) In addition, the multi-layer circuit substrate of the present invention is composed of a plurality of single-sided circuit substrates each laminated through an adhesive layer: a conductive circuit is provided on one side of the insulating rigid substrate, and the insulating rigid substrate is penetrated to achieve the foregoing. A through hole of a conductive circuit is filled with a conductive substance; &, single-sided circuit board: There is a conductive circuit on one side of an insulating rigid substrate, and there is a through-insulating rigid substrate to reach the aforementioned conductive circuit. Opening; formed by simultaneous heating and pressure, characterized in that: in most of the above-mentioned stacked circuit boards, the surface of the circuit board located on the outermost side is formed with a conductivity directly above the via hole and electrically connected to the via hole. Protrusion, the size of the private paper inside the opening of the other circuit board on the outermost side applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 11 .--- U ------------- --Order --------- line (please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 512653 A7 V. Description of the invention (5) = Set the electrical connection at The conductor of the circuit board The multi-layered circuit board carried by the conductive pins or balls on the ⑴ mentioned above, preferably the majority of the above-mentioned circuit boards! Department = the outermost circuit board surface covers its conductor circuit, and the 绛 anti-layer 'forms a connection directly above the via hole. It is provided on the conductive layer such as a conductive layer / via hole exposed from the opening formed in the resist layer, and the other circuit board surface located on the outermost side is also covered with the conductive circuit and is provided as a layer, which is arranged directly above the via hole. It is provided to be connected to a conductive pin or a ball such as a conductive layer / via hole exposed from an opening formed thereon. In the multilayer circuit board described in (2) or (2) above, the distance between adjacent via holes formed in each circuit board is preferably formed as the distance from the square circuit board to the other circuit board increases. . (3) The semiconductor device of the present invention is characterized by comprising the above-mentioned multi-layer circuit board and the electrically conductive ten protrusions "electronic parts made of" which are electrically connected to the outermost side of the multi-layer circuit board- 彳 circuit | board . In the semiconductor device described in (3) above, it is preferable that a reinforcing strip be arranged on the peripheral portion of the circuit substrate on which the electronic components are mounted, and formed at the same time in the via hole of the outer circuit substrate facing the circuit substrate. The chip capacitor is electrically connected to the via hole at a position opposite to the component loading position. (4) In addition, the semiconductor device of the present invention includes a multilayer circuit substrate: a plurality of circuit substrates are laminated through f layers, and the circuit substrate has a conductor circuit on one or both sides of an insulating hard substrate, and penetrates through the insulation. The opening of the hard substrate to reach the aforementioned conductor circuit has a via hole filled with electrolytic plating, corresponding to the position of the via hole, and a protrusion electrically connected to the via hole (please read the precautions on the back before filling this page). Order- -------- Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-8- M2653 V. Description of the invention (6) It is formed by heating and pressing; and, electronic zero-chips such as lsi chips: : It is connected to the circuit board located at the outermost side of the multilayer circuit board, and is characterized in that: a conductive protrusion is formed on the surface of the circuit board located at the outermost side and is electrically connected to the via hole, and is electrically connected to the via hole. At the same time, the conductive protrusions are electrically connected to the aforementioned electronic parts. On the outermost surface of the circuit board on the opposite side to the circuit board on which the electronic parts are mounted, Vias directly below the front electronic parts are used to electrically connect chip capacitors. In the semiconductor device described in (4) above, it is preferable that a reinforcing bar is adhered and fixed to the peripheral portion of the circuit board on which the sub-components are mounted in order to prevent the substrate from warping. (5) The multilayer circuit substrate of the present invention is formed by laminating an interlayer resin insulation layer and a conductor layer on one or both sides of a multilayer core substrate having a conductor circuit in the inner layer, and forming a laminated wiring layer connecting the conductor layers with via holes. It is characterized in that the multi-layered core substrate is composed of a plurality of circuit substrates laminated through an adhesive layer. The circuit substrate has conductor circuits on both or one side of an insulating hard substrate, and the insulating hard substrate is passed through to the conductor in five passes. The circuit hole has a via hole filled with a conductive substance, and is formed by heating and pressing together. In the multilayer circuit board carried in the above (5), it is preferable to form multilayer wiring layers on both sides of the multilayer core substrate, and to provide solder bumps on the surface of the outermost conductor layer that constitutes the multilayer wiring layer. Surfaces of the outer conductor layer are provided with conductive feet or balls. -9- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back? Matters before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs · I ϋ II H n H -04 »I ϋ IIIIII nnu II nn II Γ I 1 IIIII n 1 nu 1 512653 A7 B7 Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (7. In addition, a multilayer printed wiring board is provided · 1 The outermost conductor layer of the build-up wiring layer is covered with an anti-corrosion layer, and the outermost conductor layer exposed from the anti-corrosion opening is formed in the conductor junction area (or connection terminal form), which is suitable as a mother The multilayer circuit board y contained in (5) above should preferably be single-sided / laminated wiring I on the multilayer core soil, and the conductor layer outside the laminated conductor layer i should be located directly above the via hole. And solder bumps connected to electronic components including semiconductor wafers such as LSIs, and conductor circuits exposed on the other surfaces of the multilayer core substrate are provided directly above the filling via holes and connected to the motherboard. Conductive pins or balls. In addition, it is preferable to cover the outermost conductor layer constituting the build-up wiring layer and the other surface of the multilayer core substrate with a solder resist, and form the outermost conductor layer exposed from the opening provided in the solder resist layer. Conductor soldering area: On the conductor circuit exposed on the other surface of the multilayer core substrate, the lead pins or balls of the mother board connected to the positive hole of the above-mentioned it are formed. In the multilayer circuit substrates described in ⑴ ~ ⑴ above, The conductive material is preferably a mirror metal layer formed by an electrolytic treatment or a conductive paste composed of metal particles and a thermosetting resin or a thermoplastic resin. In the multilayer circuit board described in ⑴ to ⑴, it is preferable Constitute a multilayer core: Each circuit board of the board is formed with a protruding conductor corresponding to the position of its via hole and electrically connected to the "via hole", and it is preferable that the protruding conductor paste is formed. Furthermore, the multilayer circuit described in (1H5) above Substrate, it is better to stack the via holes of the wiring layer-partly the via holes of the 0-layer core substrate (please read the precautions on the back before filling this page) · IIII — II ^ ' - - III - - · -10- 512653
經濟部智慧財產局員工消費合作社印製 五、發明說明（8 ) 上方’直接連接於其通路孔。 、此外，在上述（1)〜(5)所載之多層電路基板，最好作爲構 成所^層化的核心基板的基本單位的單面/兩面電路基板 由硬貝基材形成，該硬質基材係由玻璃布環氧樹脂基材、玻 璃布必斯馬爾二氮雜苯（Bismaleimide 樹脂基材、 玻璃布聚苯醚（p〇lyphenylene ether)樹脂基材、芳族聚醯胺 (aramid)不織布-環氧樹脂基材、芳族聚醯胺不織布-聚醯 亞胺樹脂基材所選擇的任何一種，最好由厚度2〇〜1〇〇靖的 玻璃布裱氧樹脂基材形成，充填通路孔直徑爲5〇〜25〇Am。 再者，取好各電路基板的通路孔在脈衝能量〇 5〜i〇〇 、 脈衝寬度1〜1〇〇"S、脈衝間隔〇.5mS以上、發射數u的條 件下，對於由照射於玻璃布環氧樹脂基材表面的二氧化碳 氣體雷射所形成的開口所形成。 圖式之簡單説明 圖1爲顯示構成本發明的單面電路基板一層疊狀態之 圖’圖2爲顯示構成本發明的單面電路基板其他層叠狀態 ，圖二圖3 a顯示構成本發明的單面電路基板另外其他層 璺狀怨=圖，圖4爲顯示構成本發明的單面電路基板另外 :他層$狀悲〈圖，圖5⑷〜(g)爲顯示構成本發明的兩面 板製程一部分之圖，圖6⑷〜⑴爲顯示構成本發明的 =%路基板製程一部分之圖，圖7爲顯示關於本發明的 义層電路基板—實施形態（由單面電路基板和兩面電路基 板構成）之圖，圖8良翻-防、人士 土 —、 口 151 8馬顯不關於本發明的多層電路基板其他 貫％您、（只由早面電路基板構成）之圖，圖9爲説明圖$所 -11 - t _ 格（2^^公楚7 -----Γ------ΦΜ,--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 512653Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (8) The upper part is directly connected to its access hole. In addition, in the multilayer circuit substrates described in (1) to (5) above, it is preferable that the single-sided / double-sided circuit substrate, which is a basic unit constituting the layered core substrate, is formed of a hard shell substrate, and the hard substrate The material is made of glass cloth epoxy resin substrate, glass cloth bismal benzene (Bismaleimide resin substrate, glass cloth polyphenylene ether (polyolene ether) resin substrate, aromatic polyamide (aramid) nonwoven fabric -Epoxy resin substrate, aromatic polyimide non-woven fabric-Polyimide resin substrate, whichever is selected, it is best to be formed of glass cloth with a thickness of 20 ~ 100. The hole diameter is 50 ～ 25〇Am. In addition, the via holes of each circuit board are taken at a pulse energy of 0 ~ 50, a pulse width of 1 ~ 100, " S, a pulse interval of 0.5 mS or more, and emission. Under the condition of several u, it is formed by the opening formed by the carbon dioxide gas laser irradiated on the surface of the glass cloth epoxy resin substrate. Brief Description of the Drawings FIG. 1 shows a laminated state of a single-sided circuit board constituting the present invention. Figure 'FIG. 2 shows a unit constituting the present invention Other stacked states of circuit substrates, Figures 2 and 3a show the other layers constituting the single-sided circuit substrate of the present invention. Fig. 4 is a diagram showing the single-sided circuit substrates of the present invention. Figures 5⑷ ~ (g) are diagrams showing a part of the two-panel manufacturing process of the present invention, and Figures 6⑷ ~ ⑴ are diagrams showing a part of the =% circuit board manufacturing process of the present invention. Substrate-a diagram of an embodiment (consisting of a single-sided circuit substrate and a double-sided circuit substrate), FIG. 8 Good translation-defense, human soil-, mouth 151 (Consisting of the early circuit board), Figure 9 is an illustration of Figure -11-t _ lattice (2 ^^ 公 楚 7 ----- Γ ------ ΦΜ, ------ --Order --------- Line · (Please read the precautions on the back before filling this page) 512653
第0S9124881號專利申請案 中文說明書修正頁（91年6月） 五、發明説明（ ） 9 所示的實施形態的充填通路孔位置之圖，圖1 〇為顯示關 於本發明的半導體裝置之圖，圖為顯示本發明其他實 施形態之圖，圖12(a)〜(f)為顯示關於本發明另外其他實施 形態（在多層化核心基板單面形成積層配線層的形態）的多 層電路基板製程一部分之圖，圖13(a)〜(c)為顯示同多層電 路基板製程一部分之圖，圖14(a)及（b)為顯示同多層電路 基板製程一部分之圖，圖15(a)〜(f)為顯示關於本發明多層 電路基板其他實施形態（在多層化核心基板兩面形成積層 配線層）的多層電路基板製程一部分之圖，圖l6(a)〜(为為 顯示同多層電路基板製程一部分之圖，圖n(a)〜(b)為顯示 同多層電路基板製程一部分之圖，圖18為顯示除了圖17(b) 所示的實施形態之外再加上配設BGA或PGA的另外其他實 施形態之圖。 元件符號說明 10絕緣性基材 68 抗鍍層 12銅箔 69 電解電鍍膜 14保護薄膜 70 單面電路基板 16開口 72 單面電路基板 18電解銅鍍層 74 單面電路基板 20充填通路孔 76 單面電路基板 22導電性糊 80 多層化基板 24突起狀導体 82 電子零件 26黏接劑層 83 抗焊層 28銅箔 84 鮮锡球 30導體電路 86 片狀電容器 32導體電路 88 加強條 34兩面電路基板 90 抗焊成分物 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 512653 第089124881號專利申請案 kl ^ ^ ^ 中文說明書修正頁（91年6月)_B7 |1_ 五 、發明説明（ ) 9a 40導體電路 44突起狀導体 46黏接劑層 50早面電路基板 52單面電路基板 54單面電路基板 60多層化基板 62導電性突起 63粗化層 64導電性腳端 65層間樹脂絕緣層(黏接劑層) 65a開口部 65b粗化面 66導電性球 67無電鍍膜 實施發明之最佳形態 91開口 92鎳層 94金層 95銲錫墊 96銲錫突出 98導電性腳端 100導電性球 102通路孔 104上層導體電路 106粗化層 108層間樹脂絕緣膜(黏接劑層) 110最上層導體電路 112粗化層 114通路孔 (1)本發明在下述之點有特徵：使用多層化基板作為封 裝基板，該多層化基板係以在絕緣性硬質基材單面或兩面 有導體電路，在貫通此絕緣性硬質基材而達到前述導體電 路的開口有充填導電性物質而成的通路孔的單面/兩面電Revised page of Chinese Specification for Patent Application No. 0S9124881 (June 91) V. Map of the filled via hole of the embodiment shown in the description of the invention (9), FIG. 10 is a diagram showing a semiconductor device of the present invention, The figure is a view showing another embodiment of the present invention, and FIGS. 12 (a) to (f) are part of a multilayer circuit board manufacturing process showing another embodiment of the present invention (a form in which a multilayer wiring layer is formed on one side of a multilayer core substrate) 13 (a) ~ (c) are diagrams showing a part of the same multilayer circuit board manufacturing process, and FIGS. 14 (a) and (b) are diagrams showing a part of the same multilayer circuit board manufacturing process, and FIGS. 15 (a) ~ ( f) A diagram showing a part of a multilayer circuit substrate manufacturing process related to another embodiment of the multilayer circuit substrate of the present invention (a multilayer wiring layer is formed on both sides of the multilayer core substrate). Figures n (a) ~ (b) are diagrams showing a part of the manufacturing process of the same multilayer circuit board, and FIG. 18 is a diagram showing the addition of the BGA or PGA in addition to the embodiment shown in FIG. 17 (b) Other implementation forms Description of component symbols 10 Insulating base material 68 Anti-plating layer 12 Copper foil 69 Electrolytic plating film 14 Protective film 70 Single-sided circuit board 16 opening 72 Single-sided circuit board 18 Electrolytic copper plating 74 Single-sided circuit board 20 Filling via holes 76 Single-sided circuit board 22 conductive paste 80 multilayer substrate 24 protruding conductor 82 electronic component 26 adhesive layer 83 solder resist layer 28 copper foil 84 fresh tin ball 30 conductor circuit 86 chip capacitor 32 conductor circuit 88 reinforcement bar 34 on both sides Circuit Board 90 Solder Resistant Composition-12- This paper is scaled to Chinese National Standard (CNS) A4 (210X297 mm) 512653 Patent Application No. 089124881 kl ^ ^ ^ Chinese Manual Correction Page (June 91) _B7 | 1_ 5. Description of the invention () 9a 40 conductor circuit 44 protruding conductor 46 adhesive layer 50 early circuit substrate 52 single-sided circuit substrate 54 single-sided circuit substrate 60 multilayer substrate 62 conductive protrusion 63 roughened layer 64 conductivity Pin end 65 Interlayer resin insulation layer (adhesive layer) 65a Opening 65b Roughened surface 66 Conductive ball 67 Non-plated film The best form for implementing the invention 91 Opening 92 Nickel layer 94 Gold layer 95 Solder 96 solder protrusion 98 conductive feet 100 conductive ball 102 via hole 104 upper conductor circuit 106 roughened layer 108 interlayer resin insulation film (adhesive layer) 110 uppermost conductor circuit 112 roughened layer 114 via hole (1) The invention is characterized in that a multilayer substrate is used as a package substrate. The multilayer substrate has a conductor circuit on one or both sides of an insulating rigid substrate, and passes through the insulating rigid substrate to reach the conductor circuit. Single-sided / double-sided electrical openings with vias filled with conductive material
裝 訂Binding
路基板為構成單位，適當組合多數片這些基板，或者按照 需要，除了這些單面或兩面電路基板之外，再組合雖有在 開口充填導電性物質的通路孔但沒有導體電路之類的電路 基板，透過黏接劑層層疊後，由一併加熱加壓所成形。 即，在下述之點有特徵：層疊、一併加壓成形的多數電 路基板中，在位於最外侧的一方電路基板表面為連接於電 子零件的連接用端子而形成位於通路孔正上方、電氣連接 -12a- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) A7 """" ——' -------B7 ____ 五、發明說明（1〇 ) 万:通路孔的導電性突起，而在位於最外側的他方電路基板 於=馬連接於母板上的連接用孔或連接用焊接區而配設位 通路孔正上方、電氣連接於其通路孔的導電性腳端（PC5A) 或球（BGA)。 ① 使用例如四片單面電路基板A〜D構成上述多層化基板 :。彳丨如如圖1所示，成爲下述構造：在位於最外側的一 万電路基板A表面導體電路露出，在位於最外側的他方電 路基板D表面連接於通路孔的突起狀導體露出；而如圖2 所不，成爲下述構造：在位於最外側的電路基板A及〇表 面導體電路露出。 ② 此外，使用三片單面電路基板A、B、c和一片兩面電 路基板E構成上述多層化基板時，例如如圖3所示，成爲下 … ^ 在仏於取外側的電路基板A、C表面導體電路分 別露出。 ③ 再者’使用三片單面電路基板A、B、C和一片沒有導 體電路的電路基板下構成上述多層化電路基板時，例如如 圖4所tf，成爲下述構造：在位於最外側的電路基板a、ρ 表面分別連接於通路孔的突起狀導體露出。 上述①〜③之類的組合以外亦可構成多層化基板，但位 方、構成這種多層化基板的最外側電路基板的導體電路的通 路孔正上方的郅分形成於導體焊接區，而露出於最外側電 f 土板表面的突起狀導體形成於其露出部分於加熱加壓時 溶化而在絕緣性硬質基材表面上大致圖形擴大的導體焊接 區’形成多層電路基板。 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注音？事項再填寫本頁) — — — — — — — ^ ·11111111 . 經濟部智慧財產局員工消費合作社印製 A7 B7 經濟部智慧財產局員工消費合作社印製 發明說明（11 根據如ι所示的組合’在露出 的導體電路上爲連接人 《私路基板表面 包含LSI等半導體晶片的電子零件 而供應適當的焊錫體形 τ件 的通路孔位置在由突起狀層電路基板 接於母板上的連：；=體所形成的導體焊接區上爲連 錫球是較佳的實施形態。.要用知接區而配設1形腳端或焊 上=;二可二在露出於最外側電路基板表面的導體電路 弟二u '八田的焊锡體連接丁形腳端或焊錫球，在最下 ==板的通路孔位置在由突起狀導體㈣成的導 接區开> 成焊錫突起。 任=合的結構都是上述料突起形成於導體焊接區 喊焊接區形成於位於最外侧的—方電路基板的導 H秘彳分’或者由通路孔正上方的突起狀導體所形成 的導：焊接區上，T形腳端或焊錫球分別配設於由露出於 2取外側的他万電路基板表面的通路孔正上方的突起狀 缸所元成的導體焊接區上或者形成於導體電路一部分 導體焊接區上。 就其他實施形態而言，也可以在位於最外側的一方電路 基板表面覆盖其導體電路而設置抗焊層，在通路孔正上方 形成連接於由形成於其抗焊層的開口露出的導體層/通路 、潁的導％性突起，而在位於最外側的他方電路基板表 面也覆蓋其導體電路而設置抗焊層，在通路孔正上方形成 連接於由形成於其抗焊層的開口露出的導體層/通路孔之 類的導電性腳端或球。 -14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----^-------,ΦΜ--------訂---------線» (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 五、發明說明（12 ) ^據這種結構，由於在多層電路基板内高 ㈣孔’如此所高密度化的通路孔中，位於露出於位 =側的電路基板表面的通路孔正上方配設導電性突起或者 導=性腳端或球，所以多層電路基板内的配線層透過這種 導電性突起、導電性腳端或球以最短的配線長連接於 LSI等半導體晶片的電子零件或母板，可高密度配線化。- 而且根據本發明之多層電路基板，由於是以同一材料 成成爲基本的單面或兩面電路基板、層疊這些基板的構 ^所以難以發生以起因於熱膨脹的界面爲起點的裂紋或 剝離，因此對於溫度周期試驗的可靠性也提高。 此外，只用單面電路基板構成多層電路基板的實施形態 時’有下述有益性：不管有無形成配線都難以發生翹曲。 再者，在上述實施形態，由於導電性突起、導電性腳端 及球係位於露出於位於多層電路基板最外側的電路基板表 面的通路孔正上方所形成，所以不一定需要如習知技術那 樣形成抗焊層。因爲位於最外側的電路基板的絕緣層起抗 焊層的作用。 (2)此外，本發明之多層電路基板在下述之點有特徵： 由所層疊的多數電路基板構成的多層化基板中，在位於最 外側的一方電路基板表面形成位於通路孔正上方、電氣連 接於其通路孔的導電性突起，而在位於最外側的他方電路 基板開口内不充填導電性物質，配設電氣連接於其導體電 路的導電性腳端或球。 根據這種結構，位於構成多層化基板的單面電路基板最 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----^----------------^--------- (請先閱讀背面之注意事項再填寫本頁) 512653 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（13 ) 外侧的電路基板之一起作用作爲沒有充填通路孔的補强 板。因爲通路孔比内層的通路焊接區小，所以形成通路時 的狀態就由最外側電路基板的絕緣層壓住通路焊接區周 圍。而且，在設於這種電路基板的開口内如和導體電路電 氣連接般地配設導電性腳端或球，所以不需要抗焊層。 (3)本發明其特徵在於··係在形成於上述（〗）或（2)所载之 多層電路基板最外側的電路基板的導電性突起電氣連接 LSI晶片等電子零件而成的半導體裝置者。 根據這種結構，由於保持導電性突起的平坦性，所以沒 有其突起和電子零件間的未連接或連接不良。 义 在上述半導體裝置，最好在裝載電子零件的電路基板將 加強條配置於包圍電子零件的其周邊部，同時形成於和裝 載電子零件的電路基板對向的最外側f路基板的通路孔 中，將片狀電容器直接連接於位於與電子零件裝載位置對 向的位置的通路孔。 根據這種結構，可使LSI晶片等電子零件和片狀電容器間 的距離最短化，可縮小兩者間的環路電感。 ⑷再者’本發明係包含多層化基板:將利用電解電艘 ^成无填通路孔的多數單面電路基板層疊、—併加壓形 成⑶晶片等電子零件：電氣連接於位於其多層化 基板最外側的電路基板而成之半導體裝置，其 · 在位於前述^卜側的—方電路基板表面形成位於前述通 路孔正上万、電乳連接於其通路孔的導電性 於該導電性突起透過焊錫球電氣連接 冋寺 卞零件，在位於和 (請先閱讀背面之注咅J事項再填寫本頁) 訂---------線· -16- A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（14 =載前述電子零件的電路基板在於相反側的最外側的 土板表面對於在於前述電子零件正下方的通路孔，電^ 接片狀電容器者。 、 f據這種結構，可使LSI等電子零件和片狀電容器間的距 離取短化，可縮小兩者間的環路電感。 、在上述半導體裝置，在裝載電子零件的電路基板周邊部 黏接、固疋爲了防止起因於構成電路基板的各材料熱膨脹 率差/、的基板全體趣曲的加強條是最佳的實施形態。 、:好此加強條係由例如BT、FR4、FR5之類的破璃_樹脂 複合材料或銅等金屬材料所形成，如包圍裝載於 的電子零件般地所配設。 土扳 (5)本發明之多層電路基板在下述之點有特徵：以電路 基板爲構成單位，該電路基板在絕緣性硬質基材單面或兩 2有導體電路，在貫通此絕緣性硬質基材而達到前述導體 私路的開口有充填導電性物質而成的通路孔；以將多數這 些基板層疊、一併加壓而成的多層化基板的核心，在其多 層化核心基板單面或兩面形成積層配線層。 、>在將上述積層配線層形成於多層化核心基板兩面的一實 她形態’係下述構造：對於多層化核心基板兩面交互層叠 間樹脂絕緣層和導體電路，利用通路孔電氣連接各導體電 路間；構成如下：將位於積層配線層最外側的一方導體電 路表面的至少一部分分別形成於導體焊接區，在這些導體 焊接區上形成焊錫突起等導電性突起而連接於電子零件的 連接用端子或者導電性腳端或球，將位於最外側的他方導 ---Ϊ-----------------!訂---------線 i^w. (請先閱讀背面之注意事項再填寫本頁)The circuit substrate is a constituent unit, and a plurality of these substrates are appropriately combined, or in addition to these single-sided or double-sided circuit substrates, circuit substrates having via holes filled with a conductive substance but having no conductive circuits are assembled as required. After being laminated through the adhesive layer, it is formed by heating and pressing together. That is, it is characterized in that, in most circuit boards that are laminated and press-molded together, the outermost circuit board is formed on the surface of the outermost circuit board as a connection terminal for connection to an electronic component, and is formed directly above the via hole for electrical connection. -12a- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) A7 " " " " —— '------- B7 ____ V. Description of the invention (1〇 ) Wan: The conductive protrusion of the via hole, and the other circuit board located on the outermost side is arranged directly above the via hole and electrically connected to the via in the connection hole or connection pad connected to the motherboard. Hole's conductive pin end (PC5A) or ball (BGA). ① The above-mentioned multilayer substrate is formed using, for example, four single-sided circuit substrates A to D :.彳 丨 As shown in FIG. 1, it has a structure in which the conductor circuit is exposed on the surface of the 10,000 circuit board A located on the outermost side, and the protruding conductor connected to the via hole on the surface of the other circuit board D located on the outermost side is exposed; As shown in FIG. 2, it has a structure in which the conductor circuits on the outermost circuit boards A and 0 surface conductors are exposed. ② In addition, when three layers of single-sided circuit substrates A, B, and c and one double-sided circuit substrate E are used to form the multilayer substrate described above, for example, as shown in FIG. 3, it becomes the bottom ... ^ Take the outside circuit substrates A, C Surface conductor circuits are exposed separately. ③ Furthermore, when three layers of single-sided circuit boards A, B, and C and one circuit board without conductor circuits are used to construct the multilayer circuit board, for example, as shown in tf in FIG. 4, the following structure is formed: The projecting conductors connected to the via holes on the surfaces of the circuit substrates a and ρ are exposed. Multilayer substrates can also be constituted by combinations other than the above ① to ③, but the squares, directly above the via holes of the conductor circuit of the conductor circuit constituting the outermost circuit substrate of this multilayer substrate, are formed in the conductor pads and exposed. The protruding conductors on the outermost surface of the electric soil plate are formed on the conductor pads of the conductors, which have an exposed portion that melts when heated and pressurized, and have a substantially enlarged pattern on the surface of the insulating hard substrate to form a multilayer circuit board. -13- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) (Please read the note on the back? Matters before filling out this page) — — — — — — — — ^ · 11111111. Ministry of Economic Affairs Wisdom Printed by the Consumer Cooperative of the Property Bureau A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Office (11 According to the combination shown in the figure 'is the connector on the exposed conductor circuit' The surface of the private circuit board contains semiconductor chips such as LSI The appropriate via hole position for supplying the appropriate solder body-shaped τ pieces to the electronic parts is to connect the bump-shaped circuit board to the mother board: a solder ball on the conductor bonding area formed by the body is a preferred embodiment. .. 1-shaped leg ends or soldered joints must be provided with the known junction area. Two or two solder conductors on the conductor circuit exposed on the outermost circuit board surface are connected to the T-shaped leg ends or solder balls. At the bottom of the == board, the via hole is opened in the conductive area formed by the protruding conductors and formed into solder bumps. The structure of any combination is that the above-mentioned material bumps are formed in the conductor soldering area. Outside -Guides of square circuit substrates or guides formed by protruding conductors directly above the vias: On the soldering area, T-shaped foot ends or solder balls are respectively arranged on the other side exposed from the outside of 2 The conductor land formed by the protruding cylinder directly above the via hole on the surface of the circuit board or formed on the conductor land of a part of the conductor circuit. In other embodiments, the outermost circuit board surface may be covered. The conductor circuit is provided with a solder resist layer, and conductive protrusions connected to the conductor layer / via exposed by the opening formed in the solder resist layer are formed directly above the via hole, and the outermost circuit board surface is located on the outermost surface. A solder resist is also provided to cover the conductor circuit, and a conductive pin or ball connected to the conductor layer / via hole exposed from the opening formed in the solder resist is formed directly above the via hole. -14 Paper Size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ----- ^ -------, ΦM -------- order --------- line »(Please read the notes on the back before filling out this page) Ministry of Economic Affairs Printed by the members of the Production Bureau and Consumer Cooperatives 5. Description of the invention (12) ^ According to this structure, the high-density via holes in the multilayer circuit board are located on the surface of the circuit board exposed at the position = side. Conductive protrusions or conductive pins or balls are arranged directly above the via holes, so the wiring layer in the multilayer circuit board is connected to semiconductors such as LSI through the conductive protrusions, conductive pins or balls with the shortest wiring length. Electronic components or motherboards of wafers can be wired at high density.-Furthermore, the multilayer circuit board according to the present invention is a single-sided or double-sided circuit board made of the same material, and it is difficult to produce these layers. Due to cracks or peeling at the interface caused by thermal expansion, the reliability for the temperature cycle test is also improved. In addition, when an embodiment in which a single-sided circuit substrate is used to construct a multilayer circuit substrate has the following advantages, warping is difficult to occur regardless of the presence or absence of wiring formation. Furthermore, in the above-mentioned embodiment, since the conductive protrusion, the conductive pin end, and the ball are formed directly above the via hole exposed on the surface of the circuit board located on the outermost side of the multilayer circuit board, it does not necessarily need to be a conventional technique. Formation of solder resist. This is because the insulating layer of the outermost circuit board functions as a solder resist. (2) In addition, the multilayer circuit board of the present invention is characterized by the following: Among the multilayer substrates composed of a plurality of stacked circuit boards, an outermost circuit board surface is formed directly above a via hole and electrically connected. The conductive protrusion of the via hole is not filled with a conductive substance in the opening of the other circuit substrate located at the outermost side, and a conductive pin or ball electrically connected to the conductor circuit is provided. According to this structure, the single-sided circuit board that constitutes the multilayer substrate is the most -15-. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---- ^ ------- --------- ^ --------- (Please read the notes on the back before filling out this page) 512653 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description ( 13) One of the outer circuit boards functions as a reinforcing plate without filling the via hole. Since the via hole is smaller than the via pad of the inner layer, the state when the via is formed is that the periphery of the via pad is laminated with the insulation of the outermost circuit board. In addition, since a conductive pin or ball is disposed in the opening provided in such a circuit board as electrically connected to a conductor circuit, a solder resist is not required. (3) The present invention is characterized in that ... is a semiconductor device formed by electrically connecting an electronic part such as an LSI chip with conductive protrusions formed on the outermost circuit board of the multilayer circuit board carried in (()) or (2) above. . According to this structure, since the flatness of the conductive protrusion is maintained, there is no disconnection or poor connection between the protrusion and the electronic component. In the above-mentioned semiconductor device, it is preferable that a reinforcing strip be arranged on the circuit board on which the electronic component is mounted to surround the peripheral portion of the electronic component, and formed in the via hole of the outermost f-way substrate facing the circuit board on which the electronic component is mounted. , The chip capacitor is directly connected to the via hole located at a position opposite to the electronic component loading position. According to this structure, the distance between the electronic component such as the LSI chip and the chip capacitor can be minimized, and the loop inductance between the two can be reduced. ⑷Further, the present invention includes a multilayer substrate: a plurality of single-sided circuit substrates that are formed by electrolytic cells to form unfilled via holes are stacked and pressed to form electronic components such as CD chips: electrically connected to the multilayer substrate The semiconductor device formed by the outermost circuit board is formed on the surface of the square circuit board located on the side of the aforementioned circuit board, which is located directly above the via hole, and the electrical conductivity of the electric milk connected to the via hole is transmitted through the conductive protrusion. Solder ball electrical connection to temples and parts, located in and (please read the note on the back side of J before filling out this page) Order --------- Line · -16- A7 B7 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a consumer cooperative. 5. Description of the invention (14 = The outermost surface of the circuit board on which the aforementioned electronic parts are located on the opposite side. For the via holes directly below the aforementioned electronic parts, the chip capacitors are electrically connected. This structure can shorten the distance between electronic components such as LSI and chip capacitors, and can reduce the loop inductance between the two. In the above semiconductor device, the peripheral portion of the circuit board on which the electronic components are mounted In order to prevent the thermal expansion coefficient of each material constituting the circuit board from being bonded and fixed, the reinforcing strip of the entire substrate is the best implementation form. For example, the reinforcing strip is made of BT, FR4, FR5, etc. It is made of metallic materials such as resin-reinforced composite materials or copper, and is arranged as if it surrounds the electronic components loaded on it. (5) The multilayer circuit board of the present invention is characterized by the following points: circuit boards As a constituent unit, the circuit board has a conductor circuit on one side or both sides of the insulating hard substrate, and a via hole filled with a conductive substance is filled in the opening penetrating the insulating hard substrate to reach the conductor's private path; A core of a multilayer substrate obtained by laminating and pressing a plurality of these substrates together, and forming a multilayer wiring layer on one or both sides of the multilayer core substrate. ≫ Forming the multilayer wiring layer on both surfaces of the multilayer core substrate The real form of the structure is the following structure: For the multilayered core substrate, the resin insulation layer and the conductor circuit are alternately laminated between the two sides of the core substrate, and the conductor circuits are electrically connected by via holes; Bottom: At least a part of the conductor circuit surface on the outermost side of the multilayer wiring layer is formed in the conductor pads, and conductive bumps such as solder bumps are formed on these conductor pads to connect to the connection terminals or conductive pins of electronic parts. End or ball, will be located at the outermost other guide --- Ϊ -----------------! Order --------- line i ^ w. (Please (Read the notes on the back before filling out this page)
A7 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（15 ) 骨豆電路表面的至少一部分形成於 接區上配設導電性腳端或球，連接==導體轉 ⑼接W或連接用焊接區。㈣接μ 體電路：ΐ ;::恐’猎由覆Α位於積層配線層最外側的導 d:層’將由形成於其抗焊層的開口露出的 區上配設導電性突起或料電 焊接 電子零件的封裝基板用多“::切’形成適於裝載 二二在上述實施形態，#由覆蓋位於積層配線層最外 露出的導體電路一部分分別二=焊 ㈣多層電路基板的形態。在這種實㈣態，最 氣連接區上設置爲了按照需要進行和封裝基板的電 乳連接的連接器。 二地，在將上述積層配線層形成於多層化核 =施形態，構成如下··將位於積層配線層最外側的一 万導fa電路表面的至少_部分形成於導料接區，在 體焊接區上形成焊錫突起等導電性突起而連接於電子則 m子或導電性腳端或球，另—方面，將不形：多 層化核心基板的積層酉己線層㈣導體電路表面的至少 分形成科體焊接區’在其㈣焊接區上配設導電性腳端 或球，連接於#板上的連接用孔（連接器）或連接用焊接 區0 根據如上述各實施形態的結構，由於不要在多層化核心 -18 -A7 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics B7 V. Description of the invention (15) At least a part of the surface of the osteoblast circuit is formed on the connection area with a conductive pin or ball, and the connection == the conductor is connected to the W or Welding area for connection. Connected to the μ body circuit: ΐ; :: The fear is that the 猎: layer A is located on the outermost side of the build-up wiring layer. The d: layer 'will be provided with conductive protrusions or electrical welding on the area exposed by the opening formed in the solder resist layer. In the above-mentioned embodiment, the packaging substrates for electronic parts are formed with multiple ":: cuts". In the above embodiment, the parts of the conductor circuits exposed at the outermost layers of the multilayer wiring layer are respectively two = the form of a soldering multilayer circuit board. Here In this state, a connector is provided on the most gas connection area for electrical milk connection with the package substrate as needed. Second, the above-mentioned multilayer wiring layer is formed in a multi-layered core structure, and the structure is as follows: At least _ part of the 10,000-conductor fa circuit surface of the outermost layer of the multilayer wiring layer is formed in the conductive material contact area, and conductive bumps such as solder bumps are formed on the body bonding area, and the electrons are connected to the electrons or conductive pins or balls. On the other hand, it will not be shaped: the multilayer core substrate is laminated, its wires are layered, and at least the conductor circuit surface is formed to form a body soldering zone. On its soldering zone, a conductive foot or ball is arranged and connected to # 板Up Contact holes (connector) or pads connected to the structure of 0 as the above-described embodiment, since the multilayered core 18 in not -
--------^---------線' (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） A7-------- ^ --------- Line '(Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Love) A7
五、發明說明（16 ) (請先閱讀背面之注意事項再填寫本頁) 基板設置通孔，所以焊接區等焊接區配設的自由度提高。 其結果，可高密度設置充填通路孔，透過如此所高密度化 的通路孔，外層的積層配線層可和多層化核心基板内的導 體電路確保充分的連接，可高密度配線化。此外，在多層 核心化基板内亦可配線更高密度化。 再者’在積層配線層内高密度設置通路孔，如此所高密 度化的通路孔中，在由形成於位於最外側的層間樹脂絕緣 層的開口露出的導體焊接區上配設導電性突起或者導電性 腳端或導電性球，所以多層電路基板内的積層配線層透過 這種導電性突起、導電性腳端或導電性球以最短的配線長 連接於包含LSI等半導體晶片的電子零件或母板，可高密 度配線化及電子零件的高密度封裝化。 經濟部智慧財產局員工消費合作社印製 在如上述的（1)〜(5)所載之多層電路基板及半導體裝置， 使用於構成多層化基板的兩面/單面電路基板的絕緣性基 材不是半硬化狀態的半固化片，而是由完全硬化的樹脂材 料所形成的硬質絕緣性基材，藉由使用這種材料，使銅箔 以加熱加壓壓接於絕緣性基材上時，沒有因加壓壓力而絕 緣性基材最後厚度的變動，所以可將通路孔的位移抑制在 最小限度，縮小通路焊接區直徑。因此，可縮小配線間距 而使配線密度提高。此外，可將基材厚度實質保持於一 定，所以利用雷射加工形成充填通路孔形成用的開口時， 其雷射照射條件的設定容易。 就這種絕緣性樹脂基材而言，使用由玻璃布環氧樹脂基 材、玻璃布必斯馬爾三氮雜苯（Bismaleimide Triazine)樹脂 -19- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 512653 五、發明說明（17 ) ΐ二：璃布聚苯酿樹脂基材、芳族聚醯胺不織布-環氧 :二材、芳族聚醯胺不織布-聚醯亞胺樹脂基材所選擇 的硬質基材較佳，玻璃布環氧樹脂基材最佳。才斤選擇 此外，上述絕緣性基材厚度希望是〜刪㈣ :了：保絕緣性。因爲若是不滿2一的厚度，則強= 低而處理困難，同時對於電氣絕緣性的可靠性降低，若超 則細微通路孔形成用開口變成困難，同時基板 本身變厚。 最好形成於具有上述範園厚度的玻璃環氧基板上的通路 孔形成用開口係由二氧化碳氣體雷射所形成，該二氧化碳 氣體雷射係在脈衝能量〇.5〜1〇〇 mJ、脈衝寬度卜刚"s、脈 衝間隔0.5 ms以上、發射數μ的條件下所照射，最好其開 口直徑爲50〜250辣的範圍。其理由是因爲若是不滿·m， 則在開口難以充填導電性物質，同時連接可靠性降低，若 超過250//m，則高密度化困難。 最好在用這種二氧化碳氣體雷射形成開口之前，使和絕 緣性基材的導體電路形成面相反側之面黏接樹脂薄膜，從 其樹脂薄膜上進行雷射照射。 此樹脂薄膜係將通路孔形成用的開口内反拖尾Μ··) 處理，起作用作爲在其反拖尾處理後的開口内利用電解電 鍍處理充填金屬鍍層時的保護罩，並且起作用作爲在通路 孔的金屬鍍層正上方形成突起狀導體的印刷用罩幕。 最好上述樹脂薄膜係由PET薄膜所形成，該pET薄膜係例 如黏接劑層厚度爲1〜20em，薄膜本身厚度爲1〇〜5㈧m。 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 五 、發明說明（18 ) 产其理由是因爲取決於pET薄膜厚度來決定突起狀導體高 所以若是不滿10 "m的厚度，則突起狀導體 =變，連接不良，反之若是超過5〇_的厚度，則在連接 |面哭起狀導體過度擴大，所以不能形成精細圖案。 =充填於月通上述絕緣性基材的開口内部的導電性物質 ’最好是導電性糊或由電解電鍍處理所形成的金屬鍍 層0 、气了使充填製程單純、使製造成本減低、使良率提高， 无填導電性糊合適，但在連接可#性之點，由電解電錢處 :里所形成的金屬鍍層，例如錫、銀、焊錫、銅/錫、銅/銀 等金屬鍍層較佳，特別是電解銅鍍層最適當。 經濟部智慧財產局員工消費合作社印製 雖然如A充填導電性物質的@口„電^連接形成於絕 緣性基材的導體電路彼此的通路孔，但按照根據本發明的 作爲封裝基板的多層電路基板及使用其之半導體裝置的實 施形態，最好形成於所層疊的各電路基板的通路孔係其鄰 f通路孔間的距離對於在於裝載LSI晶片等電子零件側的 最外側電路基板最小，對於在於連接於母板側的最外側其 他電路基板最大般地所形成，即形成於所層疊的各電路基 板的通路孔配置密度係隨著從裝載L s j晶片等電子零件^ 的電路基板向連接於母板側的電路基板變小般地所二成: 根據這種結構，配線的迂迴性提高。 最好形成於上述絕緣性基材單面或兩面的導體電路係將 厚度5〜18 # m的銅络透過被保持半硬化狀態的樹脂黏接劑 層加熱加壓後，由進行適當的蝕刻處理所形成。 21 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） M2653 A7 B7 經濟部智慧財產局員工消費合作社印製 、發明說明（19 ) 二種加煞加壓係在適當溫度及加壓力之下所進行，更好 硬化減Ϊ: I斤進仃’藉由只使半硬化狀態的樹脂黏接劑層 更=’可將銅n對㈣緣性基材牢固黏接，所以比使用習 、口半固化片的電路基板可縮短製造時間。 在絶緣性基材兩面形成這種導體電路之類的電路基板可 ^作多層化基板的核心、，最好在與各通路孔對應的基板表 、’作爲導體電路一部分的通路焊接區㈣)將其口徑形成 於50〜250 em的範圍。 此外，在絕緣性基材單面形成導體電路之類的單面電路 基板不但可用作可和兩面電路基板共同層疊的電路基板， 而且也可以只層疊單面電路基板而形成多層化基板。 在這種單面電路基板，最好在充填通路孔正上方 起狀導體。 ，最好上述突起狀導體係由導電性糊或低熔點金屬所形 成在層疊各電路基板而一併加熱加壓的製程，導電性糊 或低熔點金屬會熱變形，所以可吸收充填於前述通路孔内 的導電性物質或金屬鍍層的高度偏差，因此可得到防止連 接不良且連接可靠性佳的多層電路基板。 上述突起狀導體是和充填於通路孔内的導電性物質，例 如導電性糊相同的材料，並且也可以利用同一充填製程形 成。 、 7 由上述層疊、加熱加壓所形成的多層化基板的位於最外 側的電路基板中，位於通路孔正上方而形成於在於裝載 LSI晶片等電子零件側的電路基板表面的導電性突起例如 22- 表紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） --------訂---------線· (請先閱讀背面之注意事項再填寫本頁) M2653 A7 —------— B7________ 五、發明說明（2〇 ) 开J成點矩阵狀或從其稍微移動的矩陣狀。 (請先閱讀背面之注咅心事項再填寫本頁) 此外，位於最外側的電路基板中，位於通路孔正上方而 形成於在於連接於母板側的其他電路基板表面的導電性腳 端或導電性球例如和上述導電性突起同樣，形成點矩陣狀 或從其稍微移動的矩陣狀。 以下，就製造本發明多層電路基板及使用其之半導體裝 置之方法，參照附圖加以具體説明。 (A)層疊用電路基板的形成 (1)當製造關於本發明的多層電路基板時，成爲構成其之 基本的電路基板使用在絕緣性基材丨〇單面貼上銅箔i 2者 作爲原材料。 此絕緣性基材1 〇可使用例如由玻璃布環氧樹脂基材、玻 璃布必斯馬爾三氮雜苯（Bismaleimide Triazine)樹脂基材、 玻璃布聚苯醚樹脂基材、芳族聚醯胺不織布·環氧5脂基 材、芳族聚醯胺不織布-聚醯亞胺樹脂基材所選擇的硬質 層疊基材，但玻璃布環氧樹脂基材最好。 ,上>述絕緣性基材10的厚度希望是20〜600"m。其理由是因 爲若是不滿20 的厚度，則強度降低而處理困難，同時 經濟部智慧財產局員工消費合作社印製 對於電氣絕緣性的可靠性降低，若超過6〇〇 的厚度，則 形成細微通路孔及充填導電性糊變成困難，同時基板本身 變厚。 此外，銅箔1 2的厚度希望是5〜丨8 " m。其理由是因爲使 用如後述的雷射加工在絕緣性基材形成通路孔形成用的開 口時’若過薄則貫通’反之若過厚則利用蚀刻難以形成細 —1 - 23 - 本紙張尺度適財關家標準（CNS)^i^2i() χ 297公楚） A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（21 ) 微線寬的導體電路圖案。 就上述絕緣性基材10及銅搭12而言，最好特別使用單面 鍵銅膜層登板··由層疊、加熱加壓使玻璃布浸潰環氧樹脂 而成爲半溶階段的半固化片和㈣所得到。其理由是因爲 銅落12如後述被蚀刻後的處理中，配線圖案或通路孔的位 置不會移動，位置精度佳。 (2) 其次，製造在兩面形成導體電路的電路基板時，在和 這種絕緣性基材10貼上銅搭12的表面相反侧的表面貼上 保瘦薄膜14 (參照圖5(a))。 此保護薄膜14用作形成後述突起狀導體的導電性糊的印 刷用罩幕，可使用例如在表面設置黏接層的聚對苯二甲酸 乙二醇酯（PET)薄膜。 前述P E T薄膜1 4使用黏接劑層厚度丨〜2 〇 一 m、薄膜本身厚 度10〜50//m之類者。 (3) 其次，從貼在絕緣性基材1 〇上的pET薄膜1 4上進行二 氧化碳氣體雷射照射，貫通PET薄膜丨4形成從絕緣性基材 1 0表面達到銅箔1 2 (或導體電路圖案）的開口 i 6 (參照圖 5(b))。 此雷射加工係由脈衝振盪型二氧化碳氣體雷射加工裝置 所進行，最好其加工條件是脈衝能量OH 〇〇 mJ、脈衝寬 度1〜100W、脈衝間隔0·5 ms以上、發射數卜咒的範圍内。 最好在這種加工條件之下可形成的通路口徑是5〇〜25〇" m。 (4) 爲了除去殘留於在前述製程所形成的開口 1 6側面及 底面的树爿曰殘〉查’進行反拖尾（desrnear)處理。 --------^---------^ (請先閱讀背面之注意事項再填寫本頁) -24- 512653V. Description of the invention (16) (Please read the precautions on the back before filling in this page) The substrate is provided with through holes, so the degree of freedom in the configuration of the soldering zone such as the soldering zone is increased. As a result, filled via holes can be provided at a high density, and through the via holes thus densified, the laminated wiring layer in the outer layer can ensure sufficient connection with the conductor circuit in the multilayer core substrate, and high-density wiring can be achieved. In addition, wiring can be made denser in a multilayer core substrate. Furthermore, 'via holes are provided in the laminated wiring layer at a high density. In such a high-density via hole, conductive protrusions or conductive protrusions are exposed on the conductor pads exposed from the openings formed on the outermost interlayer resin insulating layer. Conductive pins or conductive balls, so the multilayer wiring layer in a multilayer circuit board is connected to electronic parts or motherboards containing semiconductor chips such as LSIs with the shortest wiring length through such conductive protrusions, conductive pins or conductive balls. Board for high-density wiring and high-density packaging of electronic parts. Printed on the multilayer circuit board and semiconductor devices contained in (1) to (5) above by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the insulating substrate used for the double-sided / single-sided circuit board constituting the multilayer substrate is not A semi-hardened prepreg is a hard insulating base material made of a completely hardened resin material. By using this material, copper foil is heated and pressed to the insulating base material without heating. Variations in the final thickness of the insulating substrate due to pressure, so that the displacement of the via hole can be minimized and the diameter of the via pad can be reduced. Therefore, the wiring pitch can be reduced and the wiring density can be increased. In addition, since the thickness of the substrate can be kept substantially constant, it is easy to set the laser irradiation conditions when the opening for forming the via hole is formed by laser processing. For this kind of insulating resin substrate, glass cloth epoxy resin substrate and glass cloth Bisaleimide Triazine resin-19 are used.- This paper is in accordance with China National Standard (CNS) A4. (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 512653 V. Description of the invention (17) ΐ2: Glass cloth polystyrene resin base material, aromatic polyamide non-woven cloth-epoxy: two materials, Aromatic polyimide non-woven fabric-polyimide resin substrate is preferably used as the hard substrate, and glass cloth epoxy resin substrate is the best. Choosing a choice In addition, the thickness of the above-mentioned insulating base material is desirably to be deleted. If the thickness is less than 2 to 1, it will be strong = low and difficult to handle. At the same time, the reliability of electrical insulation will be reduced. If it is too high, openings for fine via hole formation will be difficult and the substrate itself will become thick. It is preferable that the opening for forming the via hole formed on the glass epoxy substrate having the above-mentioned fan thickness is formed by a carbon dioxide gas laser having a pulse energy of 0.5 to 100 mJ and a pulse width. Bu Gang's, pulse interval of 0.5 ms or more, the number of shots under the conditions of irradiation, the opening diameter is preferably in the range of 50 ~ 250 spicy. The reason for this is that if it is less than m, it will be difficult to fill the opening with a conductive substance and the connection reliability will decrease. If it exceeds 250 // m, it will be difficult to increase the density. Before forming an opening with such a carbon dioxide gas laser, it is preferable that a resin film is adhered to a surface opposite to the conductor circuit forming surface of the insulating base material, and laser irradiation is performed from the resin film. This resin film is processed by anti-tailing M ··) in the opening for forming the via hole, and functions as a protective cover when the metal plating layer is filled by electrolytic plating treatment in the anti-tailing opening, and functions as a protective cover. A printing mask for forming a protruding conductor is formed directly above the metal plating of the via hole. Preferably, the resin film is formed of a PET film, and the pET film is, for example, an adhesive layer having a thickness of 1 to 20 em, and the film itself has a thickness of 10 to 5 μm. -20- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ---------------------- Order ----- ---- Wire (Please read the precautions on the back before filling this page) 5. Description of the invention (18) The reason for the production is because the height of the protruding conductor is determined by the thickness of the pET film, so if the thickness is less than 10 " m If the thickness of the protruding conductor is changed, the connection is poor. On the other hand, if the thickness exceeds 50 °, the conductor on the connection surface will expand excessively, so a fine pattern cannot be formed. = The conductive substance filled in the opening of the insulating base material of Yuetong is preferably a conductive paste or a metal plating layer formed by electrolytic plating. The filling process is simple, the manufacturing cost is reduced, and the quality is good. The rate is improved, and the non-filled conductive paste is suitable, but at the point of connection availability, the metal plating layer formed by the electrolytic cell: for example, tin, silver, solder, copper / tin, copper / silver, etc. Good, especially electrolytic copper plating is most suitable. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, although A is filled with a conductive material such as @ 口 „电 ^ to connect via holes formed in conductive circuits of an insulating substrate, but according to the present invention, a multilayer circuit as a package substrate In the embodiment of the substrate and the semiconductor device using the same, it is preferable that the distance between the via holes formed in each of the stacked circuit substrates is adjacent to the f via hole. The other circuit boards are formed at the outermost side connected to the motherboard. The via hole formation density formed in each of the stacked circuit boards is formed from the circuit board on which electronic components such as L sj wafers are mounted. The circuit board on the mother board side is reduced in size: According to this structure, the routing of the wiring is improved. It is preferable that the conductor circuit formed on one or both sides of the insulating base material has a thickness of 5 to 18 # m. The copper network is formed by subjecting the resin adhesive layer which has been kept in a semi-hardened state to heat and pressure, and then performing an appropriate etching treatment. 21-This paper applies China National Standard (CNS) A4 Specification (210 X 297 mm) M2653 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed and invented (19) The two types of braking pressure are under appropriate temperature and pressure. Progress, better hardening and reducing: I Jinjin 仃 'By making only the resin adhesive layer in the semi-hardened state more =' copper n can be firmly adhered to the edge of the base material, so it is more stable than using conventional, oral prepregs The circuit board can shorten the manufacturing time. A circuit board such as a conductor circuit formed on both sides of an insulating substrate can be used as the core of a multilayer substrate. It is best to use the circuit board corresponding to each via hole as the conductor circuit. A part of the via pad ㈣) is formed in a range of 50 to 250 em. In addition, a single-sided circuit board such as a conductor circuit formed on one side of an insulating substrate can be used as a laminate that can be laminated with both side circuit boards. The circuit board may also be formed by laminating a single-sided circuit board to form a multilayer substrate. In such a single-sided circuit board, it is preferable to form a conductor directly above the filled via hole. A process in which conductive pastes or low-melting-point metals are laminated on circuit boards and heated and pressed together. The conductive pastes or low-melting-point metals are thermally deformed, so they can absorb conductive substances or metals filled in the via holes. The height of the plated layer is uneven, so that a multilayer circuit board with excellent connection reliability and prevention of poor connection can be obtained. The above-mentioned protruding conductor is the same material as the conductive substance filled in the via hole, such as a conductive paste, and the same material can be used. It is formed by the filling process. 7 The outermost circuit board of the multilayer substrate formed by the above-mentioned lamination, heating and pressure is located directly above the via hole and is formed on the surface of the circuit board on the side where the electronic components such as the LSI chip are mounted. Sexual protrusions such as 22- sheet paper size applies Chinese National Standard (CNS) A4 specifications (21〇X 297 public love) -------- order --------- line · (Please read the back first Please pay attention to this page and fill in this page again) M2653 A7 ———----— B7________ V. Description of the invention (2) Open J to form a matrix of dots or a matrix that moves slightly from it. (Please read the note on the back before filling in this page.) In addition, the outermost circuit board is located directly above the via hole and is formed on the conductive foot or other surface of the circuit board connected to the motherboard. The conductive ball is, for example, in the form of a dot matrix or a matrix shape slightly moved from the conductive bumps, as in the above-mentioned conductive protrusions. Hereinafter, a method for manufacturing the multilayer circuit substrate of the present invention and a semiconductor device using the same will be specifically described with reference to the drawings. (A) Formation of a laminated circuit board (1) When a multilayer circuit board according to the present invention is manufactured, a basic circuit board constituting the same is used as a raw material in which an insulating base material is attached to one side of a copper foil i 2 . The insulating substrate 1 can be made of, for example, a glass cloth epoxy resin substrate, a glass cloth bisaleimide triazine resin substrate, a glass cloth polyphenylene ether resin substrate, or an aromatic polyamide. The non-woven epoxy 5 base material and the rigid polyimide resin-polyimide resin base material are selected as the rigid laminated base material, but the glass cloth epoxy resin base material is the best. The thickness of the insulating base material 10 is preferably 20 to 600 m. The reason is that if the thickness is less than 20, the strength is reduced and the handling is difficult. At the same time, the reliability of the electrical insulation printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is reduced. If the thickness exceeds 600, fine via holes are formed. And it becomes difficult to fill the conductive paste, and at the same time, the substrate itself becomes thick. In addition, the thickness of the copper foil 12 is preferably 5 to 8 m. The reason for this is because the laser processing as described later is used to form the opening for the formation of the via hole in the insulating base material. Financial standards (CNS) ^ i ^ 2i () 297 Gongchu) A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (21) Micro-line width conductor circuit pattern. For the above-mentioned insulating base material 10 and copper layer 12, it is preferable to use a single-sided bond copper film layer for boarding. The glass cloth is impregnated with epoxy resin by lamination, heat and pressure, and becomes a semi-soluble prepreg and a semi-dissolved sheet. Got. The reason for this is because the position of the wiring pattern or the via hole does not move during the process after the copper drop 12 is etched as described later, and the position accuracy is good. (2) Next, when manufacturing a circuit board having conductor circuits formed on both sides, a thin film 14 is attached to the surface opposite to the surface on which the copper substrate 12 is attached to such an insulating base material 10 (see FIG. 5 (a)). . This protective film 14 is used as a printing screen for forming a conductive paste of a conductive conductor which will be described later. For example, a polyethylene terephthalate (PET) film having an adhesive layer on the surface can be used. The aforementioned P E T film 14 uses an adhesive layer with a thickness of 1 to 2 m and a thickness of the film itself of 10 to 50 // m. (3) Next, a carbon dioxide gas laser is irradiated from the pET film 14 attached to the insulating substrate 10, and the PET film is penetrated to form a copper foil 12 (or a conductor from the surface of the insulating substrate 10). Circuit pattern) opening i 6 (see FIG. 5 (b)). This laser processing is performed by a pulse oscillation type carbon dioxide gas laser processing device. The processing conditions are preferably pulsed energy OH 00mJ, pulse width 1 ~ 100W, pulse interval 0. 5 ms or more. Within range. The diameter of the passage that can be formed under such processing conditions is preferably 50 to 25 m. (4) In order to remove the tree residues remaining on the side and bottom of the openings formed in the aforementioned process, the process of anti-tailing (desrnear) is performed. -------- ^ --------- ^ (Please read the notes on the back before filling this page) -24- 512653
第089124881號專利申請案 |/9/ / # ^ 中文說明書修正頁（91年6月） B7 l\ n\〇^] 五、發明説明（ ) U 22 f 丨·喊·〜一 .…·一 ·" "丨丨 / 此反拖尾處理係由氣電漿放電處理 、電暈放電處理、紫 外線雷射處理或準分子雷射處理等所進行。特別是從確保 連接可靠性的觀點，最好在開口内藉由照射紫外線雷射或 準分子雷射進行反拖尾處理。 利用例如使用YAG第三諧波的紫外線雷射照射進行此反 拖尾處理時的雷射照射條件，希望是發送頻率3〜15 KHz、脈衝能量0.1〜5 mJ、發射數5〜30的範圍。 (5)其次，對於被反拖尾處理過的基板在如下的條件施以 以銅箔1 2為電鍍導線的電解銅鍍層處理，在開口 1 6内充 填電解銅鍍層1 8，形成充填通路孔2 0 (參照圖5(c))。利用 此鍍層處理在開口 1 6上部留下充填後述導電性糊2 2的微 小間隙而充填電解銅鍍層1 8。 [電解電鍍水溶液] 硫酸銅、五水合物 65 g/1 均 4匕齊J (ATOTEC製、HL) 20 ml/1 硫酸 220 g/1 光澤劑（ATOTEC製、UV) 0.5 ml/1 氯離子 40 ppm [電解電鍍條件] 發泡 ：3 . 0公升/分 電流密度 ：0.5 A/dm2 設定電流值 ：0.18 A 電鍍時間 ：130分 (6)對於在上述（5 )未充填電解銅鍍層1 8的開口 1 6的間隙或 -25- 裝 訂 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 A7 '"""" -----— B7 ___ 五、發明說明（23 ) 凹處，以保護薄膜1 4爲印刷用罩幕而充導電性糊2 2，形 成從絕緣性基材1 0表面僅相當於保護薄膜1 4厚度的部分 哭出的導體部分24(以下稱爲「突起狀導體」）(參照圖5(d))。 (7) 其次，在包含突起狀導體2 4的絕緣性基材丨〇表面形成 黏接劑層2 6 (參照圖5(e))。此黏接劑2 6爲半硬化狀態，即 ^落階段的黏接劑’係爲了黏接要形成導體電路圖案的銅 泊者’使用例如環氧樹脂清漆，其層厚最好是1〇〜5〇 的 範圍。 (8) 將銅箔28以加熱加壓壓接於在上述（7)製程設置黏接劑 層2 6的絶緣性基材丨〇表面，使黏接劑層2 6硬化（參昭圖 5(f))。 ' 當時，銅箔2 8透過硬化的黏接劑層2 6黏接於絕緣性基材 1〇，電氣連接突起狀導體24和銅箔28。此銅箔28厚度希 望是5〜1 8 jum。 (9) 其次，在貼在絕緣性基材丨〇兩面的銅箔i 2及2 8上分別 貼上蚀刻保護薄膜，以預定電路圖案罩幕覆蓋後，進行蝕 刻處理，形成導體電路3 〇及3 2 (包含通孔焊接區）（參照圖 5(g))。 在此處理製程，先在銅箔丨2及2 8表面貼上感光性乾膜抗 蝕劑後，沿著預定電路圖案曝光、顯影處理而形成蝕刻保 護膜，蝕刻不形成蝕刻保護膜部分的金屬層，形成包含通 路焊接區的導體電路圖案3 〇及3 2。 就钱刻液而言，希望是由硫酸-過氧化氫、過硫酸鹽、 氯化銅、氯化鐵的水溶液所選擇的至少一種水溶液。 -26- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） I*-------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 512653 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（24 ) 作爲蝕刻上述銅箔1 2及2 8而形成導體電路3 〇及3 2的前 處理，爲了容易形成精細圖案，可預先蝕刻銅箔表面全面 而使厚度變薄到l〜10"m，更好是2〜程度。 作馬導體電路一部分的通路焊接區其内徑和通路孔口徑 大致同樣，但其外徑最好形成在5〇〜25〇em的範圍。 U〇)其’人’將在前述（8)製程形成的導體電路3 〇及3 2表面 按照需要進行粗化處理（粗化層的顯示省略），形成兩面電 路基板34。 此粗化處理係爲了多層化時，改善和黏接劑層的密合 性’防止剝離（層離）。 就粗化處理方法而言，有例如軟蚀刻處理或黑化（氧化）_ 逆原處理、由銅-鎳-磷構成的針狀合金鍍層（荏原EudiHght 製··商品名Interplate)形成、Meek公司製造的商品名 「Mecketchbond」的蝕刻液表面粗化。 在此實施形態，形成上述粗化層最好使用蝕刻液形成， 可例如藉由從正銅絡合物和有機酸的混合水溶液使用蝕刻 液蝕刻處理導體電路表面而形成。這種蝕刻液可在噴射或 發泡等氧共存條件下使銅導體電路圖案溶解，推測反應係 如下進行：Patent Application No. 089124881 | / 9 / / # ^ Chinese manual amendment page (June 91) B7 l \ n \ 〇 ^] V. Description of the invention () U 22 f · &Quot; " 丨 丨 / This anti-tailing treatment is performed by gas plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment or excimer laser treatment. In particular, from the viewpoint of ensuring connection reliability, it is preferable to perform an anti-smearing treatment by irradiating an ultraviolet laser or an excimer laser in the opening. The laser irradiation conditions when performing this anti-smearing process using, for example, ultraviolet laser irradiation using the third harmonic of YAG is desirably in a range of a transmission frequency of 3 to 15 KHz, a pulse energy of 0.1 to 5 mJ, and a number of emissions of 5 to 30. (5) Next, the substrate subjected to the anti-tailing treatment is subjected to an electrolytic copper plating treatment using copper foil 12 as a plating lead under the following conditions, and an electrolytic copper plating layer 18 is filled in the opening 16 to form a filling via hole. 2 0 (see Fig. 5 (c)). With this plating treatment, an electrolytic copper plating layer 18 is filled with a small gap filled with a conductive paste 22 which will be described later on the opening 16. [Aqueous solution for electrolytic plating] Copper sulfate, pentahydrate 65 g / 1, all 4 J (ATOTEC, HL) 20 ml / 1 sulfuric acid 220 g / 1 gloss agent (ATOTEC, UV) 0.5 ml / 1 chloride ion 40 ppm [Electrolytic plating conditions] Foam: 3.0 liters / minute Current density: 0.5 A / dm2 Set current value: 0.18 A Plating time: 130 minutes (6) For the above (5) unfilled electrolytic copper plating layer 1 8 Gap of opening 16 or -25- The size of the bound paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). Printed A7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. ----— B7 ___ V. Description of the invention (23) The protective film 1 4 is filled with a conductive paste 2 2 for the printing screen, and the insulating substrate 10 is formed from the surface of the insulating substrate 10, which is equivalent to the protective film 1 only. A conductor portion 24 (hereinafter referred to as a "protruded conductor") with a thickness of 4 parts (refer to FIG. 5 (d)). (7) Next, an adhesive layer 26 is formed on the surface of the insulating base material including the protruding conductor 24 (see FIG. 5 (e)). This adhesive 26 is in a semi-hardened state, that is, the adhesive in the falling stage 'is used for bonding copper copper to form a conductor circuit pattern.' For example, epoxy varnish is used, and its thickness is preferably 10- 50% range. (8) The copper foil 28 is pressure-bonded to the surface of the insulating substrate provided with the adhesive layer 26 in the above-mentioned (7) process by heat and pressure, and the adhesive layer 26 is hardened (see FIG. 5 ( f)). 'At that time, the copper foil 28 was bonded to the insulating base material 10 through the hardened adhesive layer 26, and the protruding conductor 24 and the copper foil 28 were electrically connected. The thickness of this copper foil 28 is desirably 5 to 18 jum. (9) Next, etch protective films are respectively attached to the copper foils i 2 and 2 8 attached to both sides of the insulating substrate, covered with a predetermined circuit pattern, and then subjected to an etching treatment to form a conductor circuit 3 and 3 2 (including through-hole pads) (see Figure 5 (g)). In this processing process, first, a photosensitive dry film resist is pasted on the surfaces of the copper foils 2 and 28, followed by exposure and development along a predetermined circuit pattern to form an etching protection film, and etching the metal that does not form an etching protection film Layer to form conductor circuit patterns 30 and 32 including via pads. In the case of a coin solution, it is desirable to use at least one aqueous solution selected from aqueous solutions of sulfuric acid-hydrogen peroxide, persulfate, copper chloride, and ferric chloride. -26- This paper size is applicable to Chinese National Standard (CNS) A4 (21〇X 297mm) I * ------------------- Order ----- ---- Line (Please read the precautions on the back before filling this page) 512653 A7 B7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (24) It is formed by etching the above-mentioned copper foils 1 2 and 2 8 For the pretreatment of the conductor circuits 3 0 and 32, in order to easily form a fine pattern, the entire surface of the copper foil can be etched in advance to reduce the thickness to 1 to 10 " m, and more preferably 2 to approximately. The inner diameter of the via soldering area, which is part of the horse conductor circuit, is approximately the same as the diameter of the via hole, but its outer diameter is preferably formed in the range of 50 to 25 μm. U〇) The "person" will roughen the conductor circuits 30 and 32 formed in the aforementioned (8) process as necessary (the display of the roughened layer is omitted) to form a double-sided circuit board 34. This roughening treatment is to improve the adhesion with the adhesive layer when multilayering is performed, and to prevent peeling (delamination). The roughening treatment method includes, for example, soft etching treatment or blackening (oxidation) _ inverse treatment, formation of a needle-like alloy plating layer (made by Kashihara EudiHght ·· brand name Interplate) composed of copper-nickel-phosphorus, Meek Corporation The surface of the etching solution manufactured under the trade name "Mecketchbond" is roughened. In this embodiment, it is preferable to form the roughened layer using an etchant. For example, the roughened layer can be formed by etching the surface of a conductor circuit using an etchant from a mixed aqueous solution of a normal copper complex and an organic acid. This etching solution can dissolve the copper conductor circuit pattern under the conditions of coexistence of oxygen such as spraying or foaming. The reaction system is presumed to be as follows:
Cu+Cu (II) An->2 Cu (I) An/2 2 Cu (I) An/2 + n/4 〇2 + nAH (充氣） —2 Cu (II) An + n/2 H20 式中，A表示配位劑（起作用作爲螯合劑），n表示配位數。 如上式所不’產生的亞銅絡合物因酸的作用而溶解，和 丨 *-------------------訂---------線 (請先閱讀背面之注音？事項再填寫本頁) -27 - 本紙張尺度適用中國國家標準("5^)A4規格（21^ x 297公釐）Cu + Cu (II) An- > 2 Cu (I) An / 2 2 Cu (I) An / 2 + n / 4 〇2 + nAH (aerated) — 2 Cu (II) An + n / 2 H20 Formula Here, A represents a complexing agent (functioning as a chelating agent), and n represents a complexing number. The cuprous complex produced by the above formula does not dissolve due to the action of acid, and 丨 * ------------------- Order -------- -Line (please read the note on the back? Matters before filling out this page) -27-This paper size applies to the Chinese National Standard (" 5 ^) A4 size (21 ^ x 297 mm)
消 費 合 作 社 印 製 氧、、去合成爲正銅絡合物，再有助於銅的氧化。在本發明所 使用的正銅、絡合物最好是嗅類的正銅絡合⑼。由此有機酸 -二正鋼絡合物構成的蝕刻液可將唑類的正鋼絡合物及有機 故（按照需要_離子）溶解於水而調製。 、 廷種蝕刻液係由例如混合咪唑銅（11)絡合物i 0重量份、 乙醇酸7重量份、氯化鉀5重量份的水溶液所形成。刀、 構成關於本發明的多層電路基板的兩面電路基板係按照 上述（1)〜（1〇)製程所製造。 (1 )八/人，當對於這種兩面電路基板表面或背面分別所層 疊=單面電路基板製造時，先在貼在絕緣性基材1〇單面二 =泊1# 2 (參照圖6(a))上貼上蝕刻保護薄膜，以預定電路圖 案罩幕覆蓋後’進行姓刻處理，形成導體電路4()(包含通 路焊接區）（參照圖6(b))。 ^在此處理製程，先在銅箔丨2表面貼上感光性乾膜抗蝕劑 後，沿著預定電路圖案曝光、顯影處理而形成蝕刻保護 ，’蝕刻不形成蝕刻保護膜部分的金屬層，形成包含通路 焊接區的導體電路圖案4 〇。 产就蝕刻液而言，希望是由硫酸一過氧化氫、過硫酸鹽、 虱化銅、氯化鐵的水溶液所選擇的至少一種水溶液。 一作爲蝕刻上述銅箔12而形成導體電路4〇的前處理，爲了 容易形成精細圖案，可預先蝕刻銅箔表面全面而使厚度變 薄到1〜10 "m，更好是2〜8；um程度。 (12)在絶緣性基材i 〇單面形成導體電路* 〇後，進行按照 上述（2)〜(6)製程的處理，其後使pET薄膜丨4從絕緣性基材 -28- 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公爱 (請先閱讀背面之注意事項再填寫本頁) 訂---------線一 512653 A7Consumer cooperatives print oxygen and synthesize it into n-copper complexes, which in turn contributes to the oxidation of copper. The orthocopper and complex used in the present invention are preferably olfactory orthocopper complexes. The etching solution composed of the organic acid-di-n-steel complex can be prepared by dissolving the azole-based ortho-steel complex and organic (as needed) ions in water. The etching solution is formed by, for example, mixing an aqueous solution of imidazole copper (11) complex i 0 parts by weight, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride. The knives and the double-sided circuit boards constituting the multilayer circuit board according to the present invention are manufactured according to the processes (1) to (10) described above. (1) Eight / person, when the surface or back of such two-sided circuit substrates are laminated separately = single-sided circuit substrates are manufactured, firstly affixed to the insulating substrate 10 single-sided two = po 1 # 2 (refer to Figure 6 (a)) An etch protection film is pasted on, and then covered with a predetermined circuit pattern cover, and then a last name engraving process is performed to form a conductor circuit 4 () (including a via pad) (see FIG. 6 (b)). ^ In this process, first, a photosensitive dry film resist is pasted on the surface of the copper foil, and then exposed and developed along a predetermined circuit pattern to form an etching protection. 'Etching does not form a metal layer of the etching protection film portion. A conductor circuit pattern 40 including a via pad is formed. In terms of an etching solution, it is desirable to use at least one aqueous solution selected from aqueous solutions of sulfuric acid monohydrogen peroxide, persulfate, copper lice, and ferric chloride. As a pretreatment for etching the copper foil 12 to form the conductor circuit 40, in order to easily form a fine pattern, the entire surface of the copper foil can be etched in advance to reduce the thickness to 1 to 10 " m, more preferably 2 to 8; um degree. (12) After forming a conductive circuit on one side of the insulating base material i 〇, perform the process according to the above (2) to (6), and then pET film 丨 4 from the insulating base material -28- This paper Standards apply to China National Standard (CNS) A4 specifications (210 X 297 public love (please read the precautions on the back before filling out this page) Order --------- line one 512653 A7
五、發明說明（26 ) 1 0表面剝離（參照圖6(c))〜圖6(e))。 從按照上述（6)製程形成的突起狀導體44(爲和兩面電路 (請先閱讀背面之注意事項再填寫本頁) 基板的突起狀導體24區別而以符號44表示）的絕緣性基材 10表面的突出高度與保護薄膜14厚度大致相等，希望是 5〜30 的範圍。 其理由是因爲若不滿5/^m，則容易招致連接不良，若超 過30 Am，則電阻値變高，同時在加熱加壓製程突起狀導體 2 4 A夂形時，沿著絕緣性基板表面過度擴大，所以不能形 成精細圖案。 此外，最好上述突起狀導體44被預固化（precure)。其理 由是因爲突起狀導體44在半硬化狀態也硬，在層疊加壓的 階段黏接劑層軟化之前，可和所層疊的其他電路基板的導 月豆逆路（導體焊·接區）電氣接觸。 這種突起狀導體44在加熱加壓時變形而接觸面積增大， 所以可降低導通電阻，並可矯正突起狀導體44高度的偏 差。 (13)其次，在包含絕緣性基材1 〇的突起狀導體4 4的表面 塗佈樹脂黏接劑4 6 (參照圖6(f))。 經濟部智慧財產局員工消費合作社印製 這種樹脂黏接劑塗佈於例如包含絕緣性基材1 〇的突起狀 導體44的表面全體或不含突起狀導體44的表面，形成作 爲被乾燥化狀態的由未硬化樹脂構成的黏接劑層。此黏著 劑層因處理容易而最好預固化，其厚度希望是5〜50以㈤的 範圍。 前述黏接劑層4 6最好由有機系黏接劑構成，就有機系黏 -29- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 A7 ^^------- ---- 五、發明說明（27 ) =而言，最好是由環氧樹脂、聚醯亞胺樹脂、熱硬化型 1 ^_(PPE)、環氧樹脂和熱可塑性樹脂的複合樹脂、環氧 树脂和石夕樹脂的複合樹脂、Βτ樹脂所選擇的至少一種樹 脂。 馬有機系黏接劑的未硬化樹脂的塗佈方法可使用幕式塗 f機、旋轉塗佈機、滾筒塗佈機、噴射塗佈、絲網印刷 等。此外，形成黏接劑層也可以藉由層疊黏接劑片。 上述單面電路基板5 〇係在絕緣性基材丨〇的一方表面有導 體電路40，在他方表面有導電性糊一部分露出所形成的突 起狀導體44，並且在包含突起狀導體以的絕緣性基材1〇 表面有黏接劑層46所形成，互相層疊黏接多數片這些基板 或層疊黏接於所預先製造的兩面電路基板34，形成多層化 基板6 0，最好樹脂黏接劑4 6在這種層疊階段被使用。 (B)多層化基板的製作 在按照上述（A)之各處理製程所製造的兩面電路基板34 兩面層璺二片單面電路基板5〇、52及54而成的四層基板 在加熱溫度150〜200Ό、加壓力1M〜4M pa的條件下，爲一 /人加壓成形所一體化，形成多層化基板6 〇 (參照圖7 )。 在如上述的條件下，因和加壓同時加熱而各單面電路基 板的黏接劑層4 6硬化，在和鄰接單面電路基板之間進行堅 固的黏接。又，就加熱加壓而言，適合使用眞空熱加壓。 在上述實施形態，雖然使用一層兩面電路基板和三層單 面電路基板地四層多層化，但也可以適用於超過五層或六 層的多層化。 -30- 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公髮） --------^---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 512653 A7 -------^-------- - 五、發明說明（28 ) (Ή性突起或導電性腳端、導電性球的配設 :…、上述（B)之各處理製程所形成的多層化電路基板中， f位，最外側的電路基板設置導電性突起，直接裝載lsi 片等％子零件，而在位於最外側的他方電路基板配設導 %随腳⑽或導電性球’可直接連接於母板上的連接用端子 (連接器）或導電性球，構成作爲封裝基板。 例如如圖7所7JT的多層化基板6 〇係位於最外側的電路基 板5 0及54的導體電路40分別露出於外側的構造，這種多 層化基板的情況，構成如下：在各導體電路4〇上設置於通 路孔正上方的適當焊錫焊接部，供應適當焊錫體給這些焯 錫焊接部上而形成導電性突起62或配設導電性腳端64或 導電性球6 6。 又，就形成導電性突起62的焊錫體而言，使用熔點比較 低的錫/鉛焊錫（熔點1831)或錫/銀焊錫（熔點22〇ό)，就連 接導電性腳端6 4或導電性球6 6的焊錫體而言，使用溶點 230 C〜270 C的溶點比較高的錫/銻焊錫、錫/銀焊錫、錫/ 銀/銅焊錫較佳。 此外，使用使依次層疊如圖8所示的四片單面電路基板 70、72、74及76而成的四層基板在適當加熱、加壓條件 下以一次加壓成形一體化的多層化基板8 〇時，成爲下述構 造：位於最外側的一方電路基板7 0係在於其通路孔正下方 的突起導體溶化而在絕緣性基材1 〇表面上形成大致圓形的 導體焊接區，他方電路基板7 6係將其導體電路4 〇的通路 孔正上方部分形成於導體焊接區。 -31 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 512653 五、發明說明（¾ ) (請先閲讀背面之注咅？事項再填寫本頁) 這種多層化基板80的情況’構成如下：最下層電路基板 7〇係在其通路孔正下方的導體焊接區上連接導電性腳端或 導電性球66，連接於母板（省略圖式）的連接用端子或焊錫 球，而最上層電路基板76係在形成於其導體電路4〇一部 分的導體焊接區上形成導電性突起62，連接於lsi晶片等 電子零件8 2的焊錫球8 4。 、如在圖8以虛線所示，在最外侧電路基板”及”表面形 成抗焊層83亦可。這種情況，塗佈抗焊成分物，使其塗膜 乾燥後’藉由在此㈣載£騎開口部的光罩薄膜而曝 光、顯影處S，導體電路40中，形成使焊錫焊接區部分露 出的開口，在其露出的焊錫焊接區部分設置導電性突起 62、導電性腳端64或導電性球66。 在上述實施形態包含|電性焊接區或f電性腳端、 導電性球的多層化基板80和裝載於該多層化基板8〇上的 電子零件82構成半導體裝置，而作爲包含含有這種電子愛 件的多層化基板80和安裝其的母板的全體也構成半導體裝 置。 圖顯示其他半導體裝置：對於位於多層化基板8〇最外 側的一方電路基板70連接、固定片狀電容器 經濟部智慧財產局員工消費合作社印製 condenser) 86，沿著他方電路基板7 6外周邊固定爲了防止 翹曲的加強條8 8。 在這種半導體裝置，片狀電容器86係由陶瓷、鈦酸鋇等 高介電質所形成，電氣連接於位於所裝載的電子零件叨正 下方的通路孔，可謀求環路電感（loop inductance) ^減低。 -32- M2653V. Description of the invention (26) 10 Surface peeling (refer to FIG. 6 (c)) to FIG. 6 (e)). Insulating base material 10 which is formed from the protruding conductor 44 formed in accordance with the above-mentioned (6) process (different from the double-sided circuit (please read the precautions on the back before filling in this page) and the protruding conductor 24 of the substrate is indicated by the symbol 44) The protruding height of the surface is approximately equal to the thickness of the protective film 14, and it is desirable to be in the range of 5 to 30. The reason is that if it is less than 5 / ^ m, it will easily lead to poor connection. If it exceeds 30 Am, the resistance 値 will increase. At the same time, when the protruding conductor 2 4 A 夂 is heated and pressed, it will run along the surface of the insulating substrate. It is excessively enlarged so that a fine pattern cannot be formed. In addition, it is preferable that the protruding conductor 44 is precure. The reason is that the protruding conductor 44 is also hard in the semi-hardened state. Before the adhesive layer is softened during the lamination and pressurization phase, it can be electrically reversed from the other conductors of the circuit board (conductor welding and connection area). contact. The protrusion-shaped conductor 44 is deformed during heating and pressure to increase the contact area, so that the on-resistance can be reduced, and deviations in the height of the protrusion-shaped conductor 44 can be corrected. (13) Next, a resin adhesive 4 6 is coated on the surface of the projecting conductor 44 including the insulating base material 10 (see Fig. 6 (f)). This resin adhesive is printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and is coated on, for example, the entire surface of the protruding conductor 44 including the insulating base material 10 or the surface without the protruding conductor 44 and is formed to be dried. A state of an adhesive layer composed of an uncured resin. This adhesive layer is preferably pre-cured because it is easy to handle, and its thickness is preferably in the range of 5 to 50 ㈤. The aforementioned adhesive layer 46 is preferably composed of an organic adhesive, and in the case of organic adhesive-29- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) for consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed A7 ^^ ------- ---- V. Description of the invention (27) = In terms of, it is best to use epoxy resin, polyimide resin, thermosetting type 1 ^ _ (PPE ), A composite resin of an epoxy resin and a thermoplastic resin, a composite resin of an epoxy resin and a stone resin, and at least one resin selected from the Bτ resin. As the method for applying the uncured resin of the horse organic adhesive, a curtain coater, a spin coater, a roll coater, spray coating, screen printing, or the like can be used. In addition, the adhesive layer may be formed by laminating an adhesive sheet. The single-sided circuit board 50 has a conductive circuit 40 on one surface of the insulating substrate, and a protruding conductor 44 formed on the other surface by a portion of the conductive paste exposed, and the insulating property including the protruding conductor is provided. The substrate 10 is formed with an adhesive layer 46 on the surface, and a plurality of these substrates are laminated and bonded to each other or laminated to a pre-manufactured two-sided circuit substrate 34 to form a multi-layered substrate 60, preferably a resin adhesive 4 6 is used in this layering stage. (B) Fabrication of multilayer substrates A four-layer substrate made of two-sided circuit substrates 34 manufactured in accordance with each of the processing processes of (A) above, two-layered single-sided circuit substrates 50, 52, and 54 at a heating temperature of 150. Under a condition of ~ 200 Torr and a pressure of 1M to 4M pa, it is integrated into a one-person press molding station to form a multilayer substrate 60 (see FIG. 7). Under the conditions as described above, the adhesive layer 46 of each single-sided circuit board is hardened due to simultaneous heating under pressure, and strong adhesion is made to the adjacent single-sided circuit board. In addition, in the case of heating and pressurization, it is suitable to use air-heating pressurization. In the above-mentioned embodiment, although a four-layer multilayer is formed using one double-sided circuit substrate and three single-sided circuit substrates, it can be applied to multilayers having more than five or six layers. -30- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297) -------- ^ --------- ^ (Please read the precautions on the back before (Fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 512653 A7 ------- ^ ---------V. Description of the invention (28) Configuration of conductive balls: ... In the multilayer circuit board formed by each of the processing processes of (B) above, the f-th place, the outermost circuit board is provided with conductive protrusions, and the% sub-components such as lsi chips are directly loaded. The other circuit board located on the outermost side is provided with a conductive lead or a conductive ball, which can be directly connected to a connection terminal (connector) or a conductive ball on the motherboard to form a package substrate. For example, as shown in FIG. 7 and 7JT The multilayer substrate 60 is a structure in which the conductor circuits 40 of the circuit substrates 50 and 54 located at the outermost side are exposed to the outside, respectively. In the case of such a multilayer substrate, the structure is as follows: each conductor circuit 40 is provided in a via hole. Appropriate solder joints directly above, supply appropriate solder bodies to these solder joints to form conductive bumps 62 or provided with a conductive pin 64 or a conductive ball 66. For the solder body forming the conductive protrusion 62, a relatively low melting point tin / lead solder (melting point 1831) or tin / silver solder (melting point) is used. 22〇), for the solder body connected to the conductive pin 64 or the conductive ball 66, the use of tin / antimony solder with a relatively high melting point of 230 C ~ 270 C, tin / silver solder, tin / Silver / copper solder is preferred. In addition, a four-layer substrate formed by sequentially stacking four single-sided circuit substrates 70, 72, 74, and 76 as shown in FIG. 8 is applied at one time under appropriate heating and pressure conditions. When the integrated multilayer substrate 80 is formed by press forming, it has a structure in which the outermost circuit substrate 70 is formed by melting a protruding conductor directly below a via hole and forming a substantially circular shape on the surface of the insulating base material 10. The shape of the conductor welding area of the other circuit board 7 6 is formed in the conductor welding area directly above the via hole of the conductor circuit 40. -31-This paper size applies to China National Standard (CNS) A4 (210 X 297 male) Li) -------- Order --------- line (Please read the notes on the back first (Fill in this page again) 512653 V. Description of the invention (¾) (Please read the note on the back? Matters before filling in this page) The case of such a multilayer substrate 80 is constituted as follows: the lowermost circuit substrate 70 is in its path A conductive pad or conductive ball 66 is connected to the conductor soldering area directly below the hole, and a connection terminal or solder ball connected to the motherboard (omitted from the drawing), and the uppermost circuit board 76 is formed on the conductor circuit 4 〇 A conductive bump 62 is formed on a part of the conductor pad, and is connected to a solder ball 84 of an electronic component 82 such as a lsi wafer. As shown by a dotted line in Fig. 8, a solder resist layer 83 may be formed on the outermost circuit board "and" surface. In this case, after applying the solder resist composition and drying the coating film, the solder mask is exposed and developed at the opening S by loading the mask film on the opening portion, and the conductor circuit 40 forms a solder pad portion. The exposed opening is provided with a conductive protrusion 62, a conductive leg end 64, or a conductive ball 66 in the exposed solder pad portion. The above-mentioned embodiment includes a multilayered substrate 80 including an electrical pad or an electrical pin, a conductive ball, and an electronic component 82 mounted on the multilayered substrate 80. The semiconductor device is configured to include such electrons. The entire multilayer substrate 80 and the motherboard on which it is mounted also constitute a semiconductor device. The figure shows other semiconductor devices: for the circuit board 70 located at the outermost side of the multilayer substrate 80, chip capacitors are connected and fixed to the chip capacitors 86 (printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the consumer cooperative), and fixed along the other circuit board 76 To prevent warping of the strip 8 8. In such a semiconductor device, the chip capacitor 86 is formed of a high dielectric material such as ceramics or barium titanate, and is electrically connected to a via hole located directly below the electronic component to be mounted, so that loop inductance can be obtained. ^ Reduced. -32- M2653
、發明說明（3〇 此外，加強條88係由BT、FR4、FR5之類的玻璃環氧複合 材料或銅等金屬材料所形成，防止起因於構成電路基板的 各材料熱膨脹量差的翹曲。 再者，如圖1 1所示，也可以是下述構造：構成多層化基 板8 0的最外側電路基板一方在形成於其導體電路4〇的導 恤绰接區上形成導電性突起6 2，他方電路基板（此處是最 :層電路基板70)係在設於絕緣性基材1〇的開口 16不充填 私解鍍銅層 < 類的結構，供應適當焊錫體給形成於露出於 其開口 16内的導體電路4〇的導體焊接部而使導電性腳端 6 4連接。 這種構造因導電性腳端64爲絕緣性基材1〇所包圍其周圍 而無需再設置抗焊層。 在上述實施形態，最好在各焊錫焊接部上形成由「鎳_ 金」構成的金屬層，鎳層希望是，金層最好是 0.01〜〇.〇6"m。此理由是因爲鎳層若過厚則招致電阻値辦 過薄則容易剝離。另—方面是因爲金層若過厚則成 本增兩，若過薄則和焊錫體的密合效果降低。 全=1錫體Π於這種焊錫焊接部上的由錄-金構成的 至屬層上’精由此焊錫體的熔化、固化形成導電性 腳端或導電性球與坪錫焊接部接合，形成多 刷^述焊錫體的供應方法而言’可使用焊锡轉印法或印 此處’焊錫轉印法係下述方法：在半固化片貼上焊錫 (請先閱讀背面之注意事項再填寫本頁) --------訂---------線一 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 Λ -33- 512653(3) In addition, the reinforcing strip 88 is formed of a glass epoxy composite material such as BT, FR4, and FR5 or a metal material such as copper to prevent warping caused by a difference in thermal expansion of each material constituting the circuit board. Further, as shown in FIG. 11, a structure in which the outermost circuit substrate constituting the multilayer substrate 80 may be formed with a conductive protrusion 6 2 on a guide-contact area formed on the conductor circuit 40 thereof. The other circuit board (here: the layer circuit board 70) is provided in the opening 16 provided on the insulating substrate 10 without filling the copper-plated layer < structure, and supplies a suitable solder body to the exposed substrate. The conductive soldering portion of the conductive circuit 40 in the opening 16 connects the conductive pins 64. This structure eliminates the need for a solder resist because the conductive pins 64 are surrounded by the insulating base material 10. In the above embodiment, it is preferable to form a metal layer made of "nickel_gold" on each soldered portion. The nickel layer is desirably, and the gold layer is preferably 0.01 to 0.06 " m. This reason is because of nickel If the layer is too thick, it will cause resistance. If it is too thin, it will be easy to peel. Another aspect is that if the gold layer is too thick, the cost will increase by two, and if it is too thin, the adhesion effect with the solder body will be reduced. On the metal layer, 'the solder body is melted and solidified to form a conductive foot end or a conductive ball is connected to the soldering portion of the flat solder to form a multi-brush. As for the supply method of the solder body', a solder transfer method or printing Here, the solder transfer method is the following method: Paste solder on the prepreg (please read the precautions on the back before filling this page) -------- Order --------- Line 1 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ -33- 512653
第089124881號專利申請案 M 中文說明書修正頁（91年6月)_B7 五、發明説明（ ） 31 箔，藉由只留下相當於開口部分之處地蝕刻此焊錫箔，形 成焊錫圖案而成為載膜，在基板的抗焊層開口部分塗佈焊 劑（flux)後，焊錫圖案接觸於焊接區般地層疊此焊錫載 膜，將此加熱而轉印。 另一方面，印刷法係下述方法：將在相當於焊接區之處 設置開口的印刷罩幕（金屬罩幕）載置於基板上，印刷焊糊 而加熱處理。就焊錫而言，可使用錫-銀、錫-錮、錫-辞、錫-站等。 (D1)單面積層（Build-up)配線層的形成 茲就在由上述（A)及(B)製程所形成的多層化基板6 0的單 面形成積層配線層的實施形態加以說明。構成多層化基板 60的兩面及單面電路基板的圖示因簡化的目的而全部省 略（參照圖12(a))。 ①在位於多層化基板60單面的導體電路40表面形成由銅-鎳-磷構成的粗化層63 (參照圖12(b))。 此粗化層6 3係由無電鍍所形成。最好此無電鍍水溶液 的液成分係銅離子濃度、鎳離子濃度、次磷酸離子濃度分 別為 2·2 X 10·2〜4·1 X 10·2 m〇m、2·2 X 10·3〜4.1 X 10·3 mol/1、 0·20〜0.25 mol/卜 是因為在此範圍析出的覆膜的結晶構造成為針狀構造， 所以緊固效果佳。此無電鍍水溶液中除了上述化合物之 外，再添加配位劑或添加劑亦可。 就粗化層的形成方法而言，如前述，有用銅-鍊-鱗針狀 合金鍍層處理、氧化-還原處理、沿著晶粒邊界蝕刻銅表 -34- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐）Patent Application No. 089124881 M Chinese Manual Correction Sheet (June 91) _B7 V. Description of the Invention () 31 The foil is formed by etching the solder foil only to leave a portion corresponding to the opening to form a solder pattern. After the flux is applied to the opening portion of the solder resist layer of the substrate, the solder carrier film is laminated so that the solder pattern is in contact with the soldering area, and this is heated and transferred. On the other hand, the printing method is a method in which a printing mask (metal mask) provided with an opening at a position corresponding to a soldering land is placed on a substrate, a solder paste is printed, and heat treatment is performed. For soldering, tin-silver, tin-rhenium, tin-word, tin-station, etc. can be used. (D1) Formation of single-area layer (Build-up) wiring layer An embodiment in which a multilayer wiring layer is formed on one side of the multilayer substrate 60 formed by the above (A) and (B) processes will be described. The illustration of the double-sided and single-sided circuit boards constituting the multilayer substrate 60 is omitted for simplification purposes (see FIG. 12 (a)). ① A roughened layer 63 made of copper-nickel-phosphorus is formed on the surface of the conductor circuit 40 on one side of the multilayer substrate 60 (see FIG. 12 (b)). The roughened layer 63 is formed by electroless plating. The liquid composition of the electroless plating solution is preferably copper ion concentration, nickel ion concentration, hypophosphite ion concentration of 2 · 2 X 10 · 2 ~ 4 · 1 X 10 · 2 m0m, 2 · 2 X 10 · 3 ~ 4.1 X 10 · 3 mol / 1 and 0 · 20 ~ 0.25 mol / b are because the crystal structure of the coating deposited in this range becomes a needle-like structure, so the fastening effect is good. In addition to the above compounds, an electroless plating solution may be added with a complexing agent or an additive. As for the method of forming the roughened layer, as mentioned above, it can be treated with copper-chain-scale needle-like alloy plating, oxidation-reduction treatment, and etching copper along the grain boundary. ) Α4 size (210X 297mm)
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512653 五、發明説明（ 第〇89124881號專利申請案 中文說明書修正頁（91年6月）512653 V. Description of the Invention (Patent Application No. 089124881, Chinese Specification Revision Page (June 91)
32 面的處理形成粗化面的方法等。 ②其次，在有前述①製作的粗化層63的多層化基板60上 形成層間樹脂絕緣層65 (圖12(c))。 形成層間樹脂絕緣層6 5，可進行以下方法：利用幕式 塗佈機、滾筒塗佈機、印刷等塗佈製成預先調整黏度等的 液狀的樹脂而形成；在成為半硬化的B階狀態的薄膜上貼 上製好者，或’签接成為板狀的樹脂膜’加熱壓接而使其 形成。 就形成上述層間絕緣樹脂層的樹脂而言，最好使用由熱 硬化性樹脂、熱可塑性樹脂、感光性樹脂（也是意味著紫 外線硬化性樹脂等）、使熱硬化性樹脂一部分丙烯化的樹 脂、熱硬化性樹脂和熱可塑性樹脂的樹脂複合體、感光性 樹脂和熱可塑性樹脂的樹脂複合體所選擇的至少一種以 上。這些以外也可以使硬化劑、反應促進劑、光反應聚合 劑、添加劑、溶劑等含有。 就上述熱硬化性樹脂而言，可使用環氧樹脂、g分駿樹 月θt酿亞胺樹脂、必斯馬爾（Bismaieimide)樹脂、聚苯 醚樹脂、聚烯烴樹脂、氟樹脂等。 就上述環乳樹脂而言，可使用線型盼駿型、線型紛駿甲 酚型等酚醛型環氧樹脂、雙環戊二烯變質的脂環族環氧樹 脂等。 就上述感光性樹脂而言，使丙烯酸樹脂或熱硬化性樹脂 感光化時，使熱硬化性樹脂的熱硬化基和甲基丙烯酸或丙 烯酸等丙烯化反應。 -35- 本紙張尺度適用中國國豕標準(CNS) A4規格(210><297公|) 512653 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（33 ) 就熱可塑性樹脂而言，可使用苯氧基樹脂、聚醚砜 (PES)、聚观（PSF)、聚亞苯基砜（pps)、聚苯硫醚（ppES)、聚 苯醚（PPE)、聚駿亞胺（pj)等。 就上述樹脂複合體而言，有熱硬化性樹脂和熱可塑性樹 脂、感光性樹脂和熱可塑性樹脂的結合。 就上述熱硬化性樹脂和熱可塑性樹脂的組合而言，有酚 醛樹脂和聚醚砜、聚醯亞胺樹脂和聚颯、環氧樹脂和聚醚 石風、環氧樹脂和苯氧基樹脂等。 "就上述感光性樹脂和熱可塑性樹脂的組合而言，有使環 ，基了部=丙烯化的環氧樹脂和聚醚砜、丙烯酸樹脂和苯 氧基树知等，树脂複合體的混合比例最好是熱硬化性樹脂 (感光性樹脂）/熱可塑性樹脂=95/5〜5〇/5〇。是因爲無損 耐熱性’可確保高的靭性値。 上述層間樹脂絕緣層是兩層結構以上亦可。，利用兩 層不同的樹脂從樹脂層形成亦可。例如也可以是下述社 少填充物成分而使絕緣性提高，在上層藉由對於酸 ，氧化劑使可溶性填充物浸潰，和無電鍍膜提高密合性。 2 t ^成的树脂層厚度在2〇〜7〇請之間使其形成。特 之=% r25’m之間’是因爲若是其厚度則在絕緣性 在和鍍膜的密合性之點都可容易通過。 對酸或氧化劑可溶性 於對酸或氧化劑難溶性的樹脂二二 ==二二f的「難溶性」「可 、口心/貝於由同一酸或氧化劑構成的溶 --------t---------^ _ (請先閱讀背面之注意事項再填寫本頁) -36 - 297 512653 A7 ----*----- 五、發明說明（34 ) 液時，將相對地溶解速度快者爲了方便起見稱爲「可溶 性」，將相對地溶解速度慢者爲了方便起見稱爲「難溶 性」。 就上述可溶性粒子而言，例如可舉對酸或氧化劑可溶性 的樹脂粒子(以下可溶性樹脂粒子）、對酸或氧化劑可溶性 的無機粒子（以下可溶性無機粒子）、對酸或氧化劑可溶性 的，屬粒子（以下可溶性金屬粒子）等。這些可溶性粒子可 以單獨使用，也可以兩種以上併用。 上述可溶性粒子形狀不特別限定，可舉球狀、破碎狀 寺。此外，最好上述可溶性粒子形狀是—樣的形狀。是因 馬可形成有均勻粗糙度的凹凸的粗化面。 上述可溶性粒子的平均粒徑而言，希望是〇1〜1〇#瓜。 若是此粒徑範圍，則含有兩種以上不同粒徑者亦可。即，是 含有平均粒徑〇·1〜0.5/^m的可溶性粒子和平均 的可溶性粒子等。藉此，可形成更複雜的粗化面^〜導： 電路的密合性亦佳。又，在本發明所謂可溶性粒子的： 徑’係可溶性粒子最長部分的長度。 經濟部智慧財產局員工消費合作社印製 就上述可溶性樹脂粒子而言，可舉由熱硬化性樹脂、熱 可塑性樹脂等構成者，浸潰於由酸或氧化劑構成的溶:夜 =，若是比上述難溶性樹脂溶解速度快者，則不特別限 定。 就上述可溶性樹脂粒子的具體例而言，例如可舉由環# ㈣脂、㈣亞胺樹脂、聚苯樹脂、聚缔= 月曰、氟樹脂等構成者，可以是由這些樹脂一種構成者， -37- 512653 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（35 ) 可以是由兩種以上的樹脂混合物構成者。 此外，作爲上述可溶性樹脂粒子，也可以使用由橡膠構 成的樹脂粒子。就上述橡膠而言，例如可舉聚丁二烯橡 膠、環氧改性、聚氨酉旨改性、（間）丙缔骑改性等各種改性 聚丁二晞橡膠、含有羧基的（間）丙埽腈-丁二埽橡膠等。 藉由使用這些橡膠，可溶性樹脂粒子容易溶解於酸或氧化 劑。即，使用酸溶解可溶性樹脂粒子時，即使強酸以外的 酸料溶解，使用氧化劑溶解可溶性樹脂粒子時，即使氧 化力比較弱的高鐘酸亦可溶解。此外，使用路酸時亦可以 低濃度溶解。因此，酸或氧化劑不會殘留在樹脂表面，如 後述，形成粗化面後，给與氣化紅等觸媒時，不會不达斑 觸媒或使觸媒氧化。 "〃 就上述可隸錢粒子而言，例如可舉由下述的 一 :構成的粒子等：由包含銘化合物、約化合物、卸化合 物、鎂化合物及梦化合物之群所選擇。 、就上述鋁化合物而言，例如可舉氧化鋁、氫氧 就上述鈣化合物而言，例如可舉碳酸鈣、氫氧化鈣等 士述鉀'合物而言’可舉碳酸鉀等，就上述鎂化合二 二：舉ί 白雲石：驗ί碳酸鎂等，就上述；化合 »。—氧化#、滞石等。這些化合物可以 用，也可以兩種以上併用。 早獨使 就上述可溶性金屬粒子而言，例如可舉由下 ，構成的粒子等：由包含鋼、鎳、鐵、鋅、、二- 呂、錢、約及碎之群所選擇。此外，這些可溶性金^子 本紙張尺度適用中國國家標準（CNS)A4規 • 38 - 完Γ公釐） 裝--------tr---------線· (請先閱讀背面之注意事項再填寫本頁) 512653 A7 五、發明說明（36 ) 爲確保絕緣性而由樹脂等所覆蓋表層亦可。 *兩種以上混合使用上述可溶性粒子時，就混合的兩種可 =丨生粒子、.且„而5，希望是樹脂粒子和無機粒子的組合。 是因爲兩者都導電性低而可確保樹脂薄膜的絕緣性，同時 在和難溶性樹脂之間熱膨脹的調整容易謀求，在由樹脂薄 =成的層間樹脂絕緣層不發生龜裂，在層間樹脂 和導體電路之間不發生剝離。 訂 ，上述難溶性樹脂而言，在層間樹脂絕緣層使用酸或氧 化劑形成粗化面時，若是可保持粗化面形狀者，則不特別 ^ ’例如可舉熱硬化性樹脂、熱可塑性樹脂、這些複合 =等—此外’也可以是給與這些樹脂感光性的感光性樹 月曰。精由使用感光性樹脂，可在層間樹脂絕緣層使用曝 光、顯影處理形成通路孔用開口。 在這些之中，希望是含有熱硬化性樹脂的。是因爲藉 此’利用電鍍液或各種加熱處理亦可保持粗化面的形狀。 線 就上述難♦性樹脂的具體例而言，例如可舉環氧樹脂、 ::樹脂：聚醯亞胺樹脂、聚苯樹脂、聚埽烴樹脂、氣樹 知寺。這些樹脂可以單獨使用，也可以併用兩種以上。 r而且好是在一分子中有兩個以上的環氧基的環氧樹 田疋、局不但可形成前述的粗化面，而且耐熱性等亦 佳，所以在熱循環條件下也在金屬層不發生應力集中 以發生金屬層剥離等。 、 就上述環氧樹脂而言，例如可舉線型㈣甲酚 脂、雙紛A型環氧樹脂、雙紛F型環氧樹脂、線型：= -39 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 五、發明說明（37 ) 裱氧樹脂、烷基線型酚醛 脂、茶型環氧樹脂、雙 衣二树二苯紛F型環氧掏 酚式羥基的芳香族乙膝:型裱氧樹脂、苯酚類和有 秩乙趁的縮合物 _ 異氰尿酸醋、脂環族環氧樹脂等獨：:水甘油 以併用兩種以上。夢此，占， 延二了早獨使用，也可 猎此成為耐熱性等佳者。 在本發明所用的樹 田 勻分散於上述難溶性樹脂中广上述可溶性粒子大致均 的凹凸的粗化面，即使在^ ^因馬可形成有均勾粗链度 可確保形成於其上的成通路孔或通孔’亦 ,^ 7等月且^路的金屬層的密合性。此外， 也可以只在形成粗化面的表 |7表面4使用含有可溶性粒子的樹 二:：、：树脂薄膜的表層部以外不會曝露於酸或氧 二’尸以可確^持透過層間樹脂絕緣層的導體電路 絶緣性。 f上述樹脂薄膜，分散㈣溶性樹脂中的可溶性粒子添 加！:對於樹脂薄膜最好是3〜4G重量％。若是可溶性粒子 添加！不滿3重量。/〇’貝,!有時會不能形成有所希望凹凸的 粗化面，若超過40重量％，則有時在使用酸或氧化劑溶解 y溶性粒子時’會溶解到樹脂薄膜深部，不能維持透過由 經濟部智慧財產局員工消費合作社印製 树月a薄膜構成的層Μ樹脂絕緣層的導體電路間的絕緣性， 成爲短路的原因。 上述樹脂薄膜除了上述可溶性粒子'上述難溶性樹脂之 外，最好含有硬化劑、其他的成分等。 就上述硬化劑而言，例如可舉咪唑系硬化劑、氨絡物系 硬化劑、胍系硬化劑、這些硬化劑的環氧加合物或使這些 -40- ‘紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） 512653 A7 B732-face treatment, etc. ② Next, an interlayer resin insulating layer 65 is formed on the multilayer substrate 60 having the roughened layer 63 produced in the above step ① (Fig. 12 (c)). The interlayer resin insulation layer 65 can be formed by the following methods: coating with a curtain coater, a roll coater, printing, etc. to form a liquid resin with a previously adjusted viscosity and the like; and forming a semi-hardened B-stage The prepared film is affixed to the prepared film, or 'resin-attached to form a plate-like resin film' is heated and pressure-bonded to form it. As the resin for forming the interlayer insulating resin layer, a thermosetting resin, a thermoplastic resin, a photosensitive resin (which also means an ultraviolet curable resin, etc.), a resin obtained by acrylizing a part of the thermosetting resin, At least one selected from a resin composite of a thermosetting resin and a thermoplastic resin, and a resin composite of a photosensitive resin and a thermoplastic resin. Other than these, a hardening agent, a reaction accelerator, a photoreactive polymerization agent, an additive, a solvent, etc. may be contained. As for the above thermosetting resin, epoxy resin, g-type resin, bismuth resin, Bismaieimide resin, polyphenylene ether resin, polyolefin resin, fluororesin, and the like can be used. Examples of the above-mentioned cycloemulsions include phenolic epoxy resins, such as linear pancho type and linear cresol type, dicyclopentadiene-modified alicyclic epoxy resins, and the like. In the case of the photosensitive resin, when the acrylic resin or the thermosetting resin is photosensitized, the thermosetting group of the thermosetting resin is reacted with acrylization such as methacrylic acid or acrylic acid. -35- This paper size is in accordance with China National Standard (CNS) A4 specification (210 > < 297g |) 512653 A7 B7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (33) Regarding thermoplastic resin In other words, phenoxy resin, polyethersulfone (PES), polycondensate (PSF), polyphenylene sulfone (pps), polyphenylene sulfide (ppES), polyphenylene ether (PPE), and polyimide can be used. (Pj) and so on. The resin composite includes a combination of a thermosetting resin and a thermoplastic resin, a photosensitive resin and a thermoplastic resin. As for the combination of the above thermosetting resin and thermoplastic resin, there are phenol resin and polyethersulfone, polyimide resin and polyfluorene, epoxy resin and polyether stone, epoxy resin and phenoxy resin, etc. . " As for the combination of the above-mentioned photosensitive resin and thermoplastic resin, there is a mixture of resin composites such as epoxy resin and polyether sulfone, acrylic resin and phenoxy tree, which make the ring and base = acrylic The ratio is preferably thermosetting resin (photosensitive resin) / thermoplastic resin = 95/5 to 50/50. This is because non-destructive heat resistance 'ensures high toughness. The interlayer resin insulating layer may have a two-layer structure or more. Alternatively, it may be formed from a resin layer using two different resins. For example, the following filler components may be added to improve the insulation properties. The soluble fillers may be impregnated with an acid or an oxidant on the upper layer, and the adhesion may be improved with an electroless plated film. The thickness of the resin layer formed by 2 t is between 20 and 70, so that it is formed. It is particularly equal to% r25'm 'because if it is thick, it can pass easily from the point of insulation and adhesion to the plating film. Resin that is soluble in acid or oxidant is difficult to dissolve in acid or oxidizer. Resin == 222 is `` hardly soluble ''. t --------- ^ _ (Please read the notes on the back before filling out this page) -36-297 512653 A7 ---- * ----- V. Description of the invention (34) For the sake of convenience, the person with a relatively fast dissolution rate is called "soluble", and for the convenience, the person with a relatively slow dissolution rate is called "hardly soluble". The above-mentioned soluble particles include, for example, resin particles that are soluble in acids or oxidants (hereinafter soluble resin particles), inorganic particles that are soluble in acids or oxidants (hereinafter soluble inorganic particles), and those that are soluble in acids or oxidants, and are particles ( The following soluble metal particles) and so on. These soluble particles may be used alone or in combination of two or more. The shape of the soluble particles is not particularly limited, and examples thereof include a spherical shape and a broken shape. In addition, it is preferable that the shape of the above-mentioned soluble particles is the same. This is because Marco has a roughened surface with uneven roughness. As for the average particle diameter of the said soluble particle, it is desirable that it is 〇1〜10〇〜. If it is this particle size range, you may contain two or more different particle sizes. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 / ^ m, average soluble particles, and the like. Thereby, a more complicated roughened surface can be formed. The circuit adhesion is also good. The term "diameter" of the soluble particles in the present invention refers to the length of the longest portion of the soluble particles. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As for the above-mentioned soluble resin particles, those made of thermosetting resins, thermoplastic resins, etc. may be immersed in a solution made of acid or oxidizing agent: night =, if it is more than the above The poorly soluble resin has a high rate of dissolution, and is not particularly limited. Specific examples of the above-mentioned soluble resin particles include, for example, those composed of ring # ㈣ lipid, fluorene imine resin, polyphenyl resin, polystyrene, fluororesin, and the like, and may be composed of one of these resins. -37- 512653 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (35) It may be composed of a mixture of two or more resins. In addition, as the soluble resin particles, resin particles made of rubber may also be used. Examples of the above-mentioned rubbers include various modified polybutadiene rubbers such as polybutadiene rubber, epoxy modification, polyurethane modification, and (m) acrylic riding modification, and (m) acrylic containing carboxyl groups. Nitrile-butadiene rubber and so on. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when the soluble resin particles are dissolved with an acid, even if an acidic material other than a strong acid is dissolved, when the soluble resin particles are dissolved with an oxidizing agent, even the bellows acid having a relatively weak oxidizing power can be dissolved. In addition, it can be dissolved at a low concentration when using road acid. Therefore, acid or oxidant does not remain on the resin surface. As described later, when a roughened surface is formed, when a catalyst such as vaporized red is given, it does not reach the spot catalyst or oxidize the catalyst. " 〃 As for the above-mentioned particles that can be used for money, for example, particles composed of the following can be mentioned: selected from the group consisting of compound, compound, compound, magnesium compound, and dream compound. For the above-mentioned aluminum compounds, for example, alumina and hydroxide may be mentioned. For the above-mentioned calcium compounds, for example, a potassium compound such as calcium carbonate and calcium hydroxide may be mentioned. For example, potassium carbonate may be mentioned. Magnesium compound 22: Example: Dolomite: Examination of magnesium carbonate, etc., as above; Compound ». —Oxidation #, stagnant stones, etc. These compounds may be used singly or in combination. Early alone As far as the above-mentioned soluble metal particles are concerned, for example, particles composed of the following can be cited: selected from the group consisting of steel, nickel, iron, zinc, di-Lu, Qian, Yue and broken. In addition, these soluble gold ^ paper sizes are subject to the Chinese National Standard (CNS) A4 Rule • 38-End Γ mm) Packing -------- tr --------- line · (Please (Please read the notes on the back before filling this page) 512653 A7 V. Description of the invention (36) The surface layer covered with resin or the like may be used to ensure insulation. * When two or more kinds of soluble particles are used in combination, the two kinds that can be mixed are: raw particles, and, and 5 is a combination of resin particles and inorganic particles. Because both of them have low conductivity, the resin can be ensured. It is easy to adjust the insulation properties of the film and adjust the thermal expansion between the resin and the insoluble resin, so that no cracks occur in the interlayer resin insulation layer made of thin resin, and no peeling occurs between the interlayer resin and the conductor circuit. In the case of poorly soluble resins, when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer, it is not particularly special if it can maintain the shape of the roughened surface. Etc.-In addition, it can also be a photosensitive tree that gives the sensitivity of these resins. The use of photosensitive resin can be used to form openings for via holes in the interlayer resin insulation layer by exposure and development. Among these, it is desirable It contains a thermosetting resin. Because of this, the shape of the roughened surface can also be maintained by using a plating solution or various heat treatments. The above-mentioned difficult resin Specific examples include epoxy resins, :: resins: polyimide resins, polyphenylene resins, polyalkylene resins, and Kishu Chisa. These resins may be used alone or in combination of two or more. R Fortunately, epoxy tree field tincture with two or more epoxy groups in one molecule can not only form the aforementioned roughened surface, but also has good heat resistance, so it does not occur in the metal layer under thermal cycling conditions. Stress is concentrated to cause metal layer peeling, etc. As for the above-mentioned epoxy resin, for example, linear cresol resin, bivariate A-type epoxy resin, bivariate F-type epoxy resin, linear type: = -39-This Paper size applies to China National Standard (CNS) A4 (210 X 297 mm. V. Description of the invention (37) Mounting oxygen resin, alkyl novolac, tea-type epoxy resin, double-coat di-tree diphenylene F-ring Oxygenated phenolic hydroxyl group of aromatic ethyl knee: type oxygen resin, phenols, and condensates of rank _ isocyanuric acid vinegar, alicyclic epoxy resin, etc. unique: water glycerol in combination of two or more. Dream this, account, postponed early alone use, can also hunt this to become heat-resistant Rough surface of unevenness unevenly dispersed in the insoluble resin widely used in the present invention. The rough surface of the unevenness of the above-mentioned soluble particles is uniform. The formation of via holes or vias thereon, such as the adhesion of metal layers such as ^ 7 and ^. In addition, it is also possible to use a tree 2 containing soluble particles only on the surface forming the rough surface | 7 surface 4 ::,: The surface of the resin film will not be exposed to acid or oxygen to ensure the insulation of the conductor circuit through the interlayer resin insulation layer. F The resin film is added to dissolve the soluble particles in the soluble resin. ！: For resin film, it is best to be 3 to 4% by weight. If soluble particles are added! Less than 3% by weight. / 〇 ′ 贝,! Sometimes the rough surface with desired unevenness may not be formed. If it exceeds 40% by weight, then When dissolving y-soluble particles with an acid or oxidant, they sometimes dissolve deep in the resin film and cannot maintain the conductor circuit of the layer M resin insulation layer made of the tree moon a film printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Insulation properties cause the short circuit. The resin film preferably contains a hardener, other components, and the like in addition to the soluble particles and the poorly soluble resin. As for the above-mentioned hardeners, for example, imidazole-based hardeners, ammonia complex-based hardeners, guanidine-based hardeners, epoxy adducts of these hardeners, or these -40- 'paper sizes can be applied to Chinese national standards CNS) A4 specification (210 X 297 public) 512653 A7 B7
38 第089124881號專利申請案 中文說明書修正頁（91年6月） 五、發明説明（ 硬化劑微膠囊化者、三苯膦、四苯基銹、四苯基硼酸鹽等 有機磷化氫系化合物等。 上述硬化劑含有量最好是對於樹脂薄膜為0.05〜10重量 %。若是不滿0.05重量％，則因樹脂薄膜硬化不充分而酸 或氧化劑侵入樹脂薄膜的程度變大，有時樹脂薄膜的絕緣 性會受損。另一方面，若超過1 〇重量％，則過剩的硬化 劑成分有時會使樹脂的成分變性，有時會招致可靠性降 低。 就上述其他成分而言，例如可舉不影響粗化面形成的無 機化合物或樹脂等填充物。就上述無機化合物而言，例如 可舉二氧化矽、氧化鋁、白雲石，就上述樹脂而言，例如 可舉聚醯亞胺樹脂、聚丙烯樹脂、聚醯胺亞胺樹脂、聚苯 樹脂、黑素樹脂、聚烯烴系樹脂等。藉由使這些填充物含 有，謀求熱膨脹係數整合或耐熱性、耐藥品性提高等，可 使印刷配線板的性能提高。 此外，上述樹脂薄膜也可以含有溶劑。就上述溶劑而 言，例如可舉丙酮、甲乙酮、環己酮等酮類、醋酸乙酯、 醋酸丁酯、醋酸酯溶纖劑或甲苯、二甲苯等芳烴等。這些 溶劑可單獨使用，也可以兩種以上併用。 特別是在本發明，作為形成後述通路孔1 0 2的層間樹脂 絕緣材料，最好使用以熱硬化性樹脂和熱可塑性樹脂的複 合體為樹脂基體的無電鍍用黏接劑。此外，也可以層疊使 用半硬化狀態的樹脂薄膜。 ③使在前述②形成的無電鍍用黏接劑層後，設置通路孔形 成用的開口部65 a(圖12(d))。 -41 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂 51265338 Revised page of Chinese Specification for Patent Application No. 089124881 (June 91) V. Description of the Invention The content of the hardener is preferably 0.05 to 10% by weight for the resin film. If the content is less than 0.05% by weight, the degree of acid or oxidant intrusion into the resin film increases due to insufficient curing of the resin film. Insulation properties are impaired. On the other hand, if it exceeds 10% by weight, an excessive amount of the hardener component may sometimes cause the resin component to be denatured, and sometimes the reliability may be lowered. Fillers such as inorganic compounds and resins that do not affect the formation of the roughened surface. Examples of the inorganic compounds include silicon dioxide, alumina, and dolomite. Examples of the resins include polyimide resin, Polypropylene resins, polyimide resins, polyphenylene resins, melanin resins, polyolefin resins, etc. By including these fillers, the thermal expansion coefficient can be integrated or heat-resistant And chemical resistance can improve the performance of the printed wiring board. In addition, the resin film may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, ethyl acetate, Butyl acetate, acetate cellosolve, aromatic hydrocarbons such as toluene, xylene, etc. These solvents can be used alone or in combination of two or more. Especially in the present invention, it is used as an interlayer resin insulating material for forming via holes 102 described below It is preferable to use an adhesive for electroless plating using a composite of a thermosetting resin and a thermoplastic resin as a resin matrix. In addition, a resin film in a semi-hardened state may be laminated and used. ③ The electroless plating formed in the above ② After the adhesive layer, an opening 65 a for forming a via hole is provided (Fig. 12 (d)). -41-This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm).
第089124881號專利申請案 中文說明書修正頁(91年6月） 4 年( JLPatent Application No. 089124881 Patent Specification Revised Page (June 91) 4 years (JL
39 發明説明（ 感光性樹脂的情況，藉由曝光、顯影之後熱硬化，而熱 硬化性樹脂的情況，藉由熱硬化之後雷射加工，在前述黏 接劑層6 5設置通路孔形成用的開口部6 5 a。 ④ 其次，將存在於硬化的前述黏接劑層6 5表面的環氧（樹 脂粒子利用酸或氧化劑分解或溶解而除去，在黏接劑層表 面施以粗化處理而形成粗化面6 5 b (圖12(e))。 此處，作為上述酸，有磷酸、鹽酸、硫酸或者曱酸或醋 酸等有機酸，但最好特別使用有機酸。是因為粗化處理 時，難以使通路孔露出的金屬導體層腐蝕。 另一方面，作為上述氧化劑，最好使用鉻酸、高錳酸鹽 (高錳酸鉀等）。 "°" ⑤ 其次’給與黏接劑層6 5表面的粗化面6 5 b觸媒核。 給與觸媒核最好使用貴金屬離子或貴金屬膠體等，一般 使用氯化鈀或鈀膠體。又，為了固定觸媒核，最好進行加 熱處理。就這種觸媒核而言，最好是鈀。 ⑥ 再者，在（無電鍍用）黏接劑層6 5表面施以無電鍍，如 跟隨粗化面整個區域般地形成無電鍍膜67(圖12(士。^ 時’無電鍍膜67厚度最好是〇·ι〜5//m的範圍，更好是〇5〜3 〇 其次，在無電鍍膜67上形成抗鍍層68(圖n(a))。就抗 鍍層成分物而言，最好特別使用由線型酚醛甲酚型環氧^ 脂或線型酚醛型環氧樹脂的丙烯酸酯和咪唑硬化劑^成的 成分物，但其他也可以使用市售品的乾膜。 ⑦ 再者，在無電鍍膜67上的抗鍍層非形成部施以電解電 鍍，設置為了形成上層導體電路丨04的導體層，同時在開= -42-39 Description of the invention (In the case of a photosensitive resin, thermal curing is performed after exposure and development, and in the case of a thermosetting resin, laser processing is performed after thermal curing. A via hole is formed in the adhesive layer 65. The opening 6 5 a. ④ Next, the epoxy (resin particles are decomposed or dissolved with an acid or an oxidant and removed on the surface of the hardened adhesive layer 65, and the surface of the adhesive layer is roughened. The roughened surface 6 5 b is formed (FIG. 12 (e)). Here, as the above-mentioned acid, there are organic acids such as phosphoric acid, hydrochloric acid, sulfuric acid, or osmic acid, or acetic acid, but it is preferable to use organic acids in particular. This is because of the roughening treatment. In this case, it is difficult to corrode the exposed metal conductor layer of the via hole. On the other hand, as the oxidizing agent, chromic acid and permanganate (potassium permanganate, etc.) are preferably used. &Quot; ° " Rough surface 6 5 b catalyst core on the surface of the contact layer 65. It is best to use noble metal ions or noble metal colloids for the catalyst core. Generally, palladium chloride or palladium colloid is used. In addition, in order to fix the catalyst core, the most Ready for heat treatment. In particular, palladium is preferred. ⑥ Furthermore, electroless plating is applied to the surface of the adhesive layer 65 (for electroless plating), and an electroless plated film 67 is formed as follows the entire area of the roughened surface (FIG. 12 (±. ^). The thickness of the electroless plated film 67 is preferably in the range of 0.5 to 5 // m, and more preferably 0.05 to 30. Second, an anti-plating layer 68 is formed on the electroless plated film 67 (FIG. N (a)). As the component, it is preferable to particularly use a composition composed of a novolac cresol epoxy resin or a novolac epoxy resin acrylate and an imidazole hardener. However, a commercially available dry film may also be used. ⑦ Furthermore, electrolytic plating is applied to the non-plating layer non-forming portion on the electroless plating film 67, and it is set to form a conductor layer of the upper-layer conductor circuit 04, and at the same time = -42-
512653 第089124881號專利申請案 中文說明書修正頁（91年6月） 五、發明説明（ ） 40 65a内部充填電解電鍍膜69而形成通路孔102(圖13(b))。 此時，露出於開口 6 5 a外侧的電解電鍍膜6 9厚度希望是 5〜30卿。此處，就上述電解電鍍而言，最好使用鍍銅。 ⑧ 再者，除去抗鍍層6 8後，用硫酸和過氧化氫混合液或 過硫酸鈉、過硫酸銨等蝕刻液溶解除去抗鍍層下的無電鍍 膜，形成獨立的上層導體電路104和充填通路孔102。 ⑨ 其次，在上層導體電路104表面形成粗化層106。 就粗化層106的形成方法而言，有蚀刻處理、研磨處 理、氧化還原處理、電鍍處理。 這些處理中，氧化還原處理NaOH (20 g/1)、NaC102 (50 g/1)、NaP04 (15.0 g/1)為氧化浴（黑化浴），以 NaOH (2·7 g/1)、NaBH4 (1.0 g/1)為還原浴。 此外，由銅-鎳-磷合金層構成的粗化層由無電鍍處理的 析出所形成。 就此合金的無電鍍液而言，最好使用由硫酸銅1〜40 g/Ι、硫酸鎳0.1〜6.0 g/Ι、檸檬酸10〜20 g/Ι、次磷酸鹽10〜100 g/Ι、硼酸10〜40 gM、界面活性劑0.01〜10 g/Ι構成的液成分 的電鍍浴。 再者，以離子化傾向比銅大、鈦以下的金屬或貴金屬層 覆蓋此粗化層1 0 6表面。 錫的情況，使用氟硼化錫-硫脲、氯化錫-硫脲液。此 時，藉由銅-錫取代反應形成0.1〜2 程度的錫層。貴金 屬的情況，可採用濺鍍或蒸鍍等方法。 ⑩ 其次，在此基板上形成無電鍍用黏接劑層1 0 8作為層間樹 -43- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 512653 A7 B7 年月512653 Patent Application No. 089124881 Chinese Specification Correction Page (June 91) V. Description of the Invention () 40 65a The electrolytic plating film 69 is filled inside to form the via hole 102 (Fig. 13 (b)). At this time, the thickness of the electrolytic plating film 6 9 exposed outside the opening 65 a is desirably 5 to 30 mm. Here, for the above-mentioned electrolytic plating, copper plating is preferably used. ⑧ Furthermore, after removing the anti-plating layer 68, the electroless plating film under the anti-plating layer is dissolved and removed by using a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate to form an independent upper-layer conductor circuit 104 and fill via holes 102. ⑨ Next, a roughened layer 106 is formed on the surface of the upper conductor circuit 104. The method for forming the roughened layer 106 includes an etching process, a polishing process, a redox process, and a plating process. Among these treatments, the oxidation-reduction treatment NaOH (20 g / 1), NaC102 (50 g / 1), NaP04 (15.0 g / 1) is an oxidation bath (blackening bath), and NaOH (2 · 7 g / 1), NaBH4 (1.0 g / 1) is a reduction bath. In addition, a roughened layer composed of a copper-nickel-phosphorus alloy layer is formed by precipitation of an electroless plating treatment. For the electroless plating solution of this alloy, it is best to use copper sulfate 1 to 40 g / 1, nickel sulfate 0.1 to 6.0 g / 1, citric acid 10 to 20 g / 1, hypophosphite 10 to 100 g / 1, Electroplating bath with liquid components consisting of boric acid 10 to 40 gM and surfactant 0.01 to 10 g / 1. The surface of this roughened layer 106 is covered with a metal or noble metal layer having a higher ionization tendency than copper and less than titanium. In the case of tin, tin fluoboride-thiourea and tin chloride-thiourea solutions were used. At this time, a tin layer of about 0.1 to 2 is formed by a copper-tin substitution reaction. In the case of precious metals, sputtering or vapor deposition can be used. ⑩ Secondly, an adhesive layer for electroless plating 108 is formed on this substrate as an interlayer tree. -43- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) 512653 A7 B7
第089124881號專利申請案 _中文說明書修正頁（91年6月） 五、發明説明（ ） 41 脂絕緣層。 ⑪再者’反覆前述製程③〜⑨，在通路孔102正上方設置 其他通路孔（省略圖示），同時在比上層導體電路104更外 侧設置上層導體電路1 1 〇 (參照圖13(c))，將此上層導體電 路110的表面及包含省略圖示的通路孔内壁的表面粗化處 理而設置粗化層1 1 2。 ⑫其次’覆蓋如此所得到的積層配線層最外侧表面，塗佈 抗焊成分物90，將其塗膜乾燥後，藉由在此塗膜載置描 输開口部的光罩薄膜而曝光、顯影處理，形成導體層中使 為了成為焊錫焊接區的導體部分（包含導體焊接區、通路 孔）露出的開口 9 1 (參照圖14(a))。 此處，露出的開口 9 1的開口徑可比為了成為焊錫焊接 區的導體部分的直徑加大，並且使其導體部分完全露出亦 可。此外，反之前述開口 9 1的開口徑可比為了成為上述 焊錫焊接區的導體部分的直徑縮小，可用抗焊層9〇覆蓋 導體部分的周邊。這種情況，最好構成如下：卩用抗^ 9〇抑制為了成為焊錫焊接區的部分，最後可防止焊^ 接區的剝離。 似丹耆，在從前述抗焊層90的開口部91露出的前述導體 =上形成由「鎳·金」構成的金屬層’形成焊锡坪接區。 、層92希望是，金屬最好是〇〇ι〜。此理 易為：層92若過厚則招致電阻值増大，若過薄則容 若I 面，是因為金層94若過厚則成本增高， 匕薄則和焊錫體的密合效果降低。Patent application No. 089124881 _ Chinese manual amendment page (June 91) V. Description of invention () 41 Grease insulation layer. ⑪Further, repeat the aforementioned processes ③ to ⑨, and provide other via holes (not shown) directly above the via hole 102, and at the same time, an upper conductor circuit 1 1 〇 is provided outside the upper conductor circuit 104 (see FIG. 13 (c)). ), Roughening the surface of the upper conductor circuit 110 and the surface including the inner wall of the via hole (not shown) to provide a roughened layer 1 1 2. ⑫Secondly, the outermost surface of the multilayer wiring layer thus obtained is coated, the solder resist component 90 is applied, and the coating film is dried, and then exposed and developed by placing a mask film depicting openings on the coating film. This process forms an opening 9 1 (see FIG. 14 (a)) in the conductor layer in which a conductor portion (including a conductor pad and a via hole) to be a solder pad is exposed. Here, the opening diameter of the exposed opening 91 may be larger than the diameter of the conductor portion for forming a solder pad, and the conductor portion may be completely exposed. In addition, the opening diameter of the above-mentioned opening 91 can be made smaller than the diameter of the conductor portion to be the solder pad, and the periphery of the conductor portion can be covered with the solder resist layer 90. In this case, it is preferable to constitute as follows: (1) The resistance to the solder pad is suppressed by resistance to 90 °, and finally the peeling of the solder pad can be prevented. Like a dagger, a metal layer composed of "nickel · gold" is formed on the aforementioned conductor exposed from the opening 91 of the solder resist layer 90 to form a solder bump. The layer 92 is preferably made of metal. This reason is as follows: if the layer 92 is too thick, the resistance value will be large, and if it is too thin, the surface will be I, because the gold layer 94 is too thick, the cost will increase, and the thinner the effect of the adhesion with the solder body will be reduced.
第089124881號專利申請案 中文說明書修正頁Γ91年6月、 五 、發明説明（ 42 ⑭再者，供應焊錫體給導體電路（焊錫焊接區）上，該導體 f路係由形成於位於形成於多層化基板單面的積層配線層 最外侧的抗焊層一方的開口部9 (位於上方的開口部）露 出，而形成焊錫突出96，同時供應焊錫體給導體電路52 (焊錫焊接區）上，該導體電路11〇係露出於不形成多層化 基板的積層配線層侧的表面，而形成丁腳端98或焊錫球 1〇〇 ’藉此製造多層電路基板（參照圖。 就知錫體的供應方法而言，可使用焊錫轉印法或印刷 法。 斤此處，焊錫轉印法係下述方法：在半固化片貼上焊錫 油，藉由只留下相當於開口部分之處而蝕刻化焊錫箔，形 成坪锡圖案而成為焊錫載膜，將此焊錫載膜如在基板的抗 焊層開口部分塗佈焊劑（fluxM^，焊錫圖案接觸於焊接區 般地層疊，將此加熱而轉印。另一方面，印刷法係下述方 法··將在相當於焊接區之處設置貫通孔的印刷罩幕（金屬 罩幕）載置於基板上，印刷焊錫糊而加熱處理。就焊錫而 言，可使用錫-銀、錫-銦、錫-鋅、錫-站等。 又’就形成導電性突起9 6的焊錫體而言，使用熔點比 較低的錫/鉛焊錫（熔點183t:)或錫/銀焊錫（熔點220艺），就 連接導電性腳端9 8或導電性球100的焊錫體而言，使用熔 點230T：〜270°C的熔點比較高的錫/銻焊錫、錫/銀焊錫、錫 /銀/銅焊錫較佳。 (D2)兩面積層配線層的形成 關於在由上述（A)及（B)製程所形成的多層化核心基板6〇 -45- 512653 第089124881號專利申請案 中文說明書修正頁（91年6月） 五、發明説明（ ） 43 兩面形成積層配線層的實施形態，係進行按照上述（D丨）的 單面積層配線層形成製程①〜⑫的處理後（參照圖丨7(a))， 在積層配線層最外侧的導體電路n〇 一部分形成包含鎳層 92和金屬94而成的焊錫焊接區95，藉此製造適於用作母 板的多層電路基板（參照圖17(b))。 再者’供應焊錫體給形成於構成上述兩面積層配線層一 方的最外側導體電路！丨〇上的焊錫焊接區9 5上而形成焊錫 突起96，同時供應焊錫體給形成於構成他方積層配線層 的取外侧導體電路8 2上的焊錫焊接區9 5上而配設T腳端 98或焊錫球1〇〇，藉此製造適於用作可高密度封裝電子零 件的封裝基板的多層電路基板（參照圖1 8 )。 以下’以實施例為基礎加以說明。 [實施例] (實施例1 ) (1)首先，製作構成多層化基板的兩面電路基板。此電路 基板使用單面鍍銅膜層疊板作為原材料，該單面鍍銅膜層 疊板係由層疊且加熱加壓使玻璃布浸潰環氧樹脂而成為B 階的半固化片和銅箔所得到。 此絕緣性基材1 〇厚度為75 ，銅箔丨2厚度為12 ，在 和此層疊板的銅箔形成面相反侧的表面層疊有厚度1〇 的黏接劑層、並且薄膜本身厚度為12_之類的似薄膜 14° ⑺其次，從PET薄膜14上進行二氧化碳氣體雷射照射，形 成貫通PET薄膜14及絕緣性基材1〇而到達鋼落12的通路No. 089124881 Patent Application Chinese Specification Revised Page Γ June, 91, V. Description of the Invention (42) Furthermore, the solder body is supplied to a conductor circuit (soldering area), and the conductor path is formed in a multilayer The opening 9 (on the upper opening) on the outermost side of the solder resist layer of the multilayer wiring layer on one side of the substrate is exposed to form a solder protrusion 96, and at the same time, a solder body is supplied to the conductor circuit 52 (solder pad). The conductor circuit 110 is exposed on the surface of the build-up wiring layer side where the multilayer substrate is not formed, and a toe end 98 or a solder ball 100 ′ is formed to manufacture a multilayer circuit substrate (refer to the figure. The method for supplying a tin body is known). For example, a solder transfer method or a printing method can be used. Here, the solder transfer method is a method in which a solder oil is affixed to a prepreg, and a solder foil is etched by leaving only a portion corresponding to an opening, A solder pattern is formed to form a solder carrier film. This solder carrier film is coated with a flux (fluxM ^) at the opening portion of the solder resist layer of the substrate, and the solder pattern is stacked in contact with the soldering area. On the other hand, the printing method is the following method: placing a printing mask (metal mask) with through-holes corresponding to the soldering area on a substrate, printing a solder paste, and heating. For the solder, tin-silver, tin-in, tin-zinc, tin-station, etc. can be used. For the solder body forming the conductive protrusion 9 6, a tin / lead solder having a relatively low melting point (melting point 183t) is used. :) or tin / silver solder (melting point 220), for the solder body connected to the conductive pin 98 or the conductive ball 100, use a melting point 230T: ~ 270 ° C, a relatively high melting point tin / antimony solder, Tin / silver solder and tin / silver / copper solder are preferred. (D2) Formation of a two-area layer wiring layer Regarding the multilayer core substrate formed by the above-mentioned (A) and (B) processes 60-45-512653 089124881 Revised Page of Chinese Specification for Patent Application No. (June 91) V. Description of Invention () 43 The embodiment of forming a laminated wiring layer on both sides is a single-area wiring layer forming process according to the above (D 丨). After processing (refer to Figure 丨 7 (a)), the outermost conductor in the multilayer wiring layer A solder pad 95 including a nickel layer 92 and a metal 94 is formed in a part of the circuit n0, thereby manufacturing a multilayer circuit board suitable for use as a motherboard (see FIG. 17 (b)). Solder bumps 96 are formed on the outermost conductor circuits constituting one of the above-mentioned two-area wiring layers! At the same time, a solder body is supplied to the outer conductor circuits 8 2 formed on the other multilayer wiring layers. A multi-layer circuit board (refer to FIG. 18) suitable for use as a package substrate capable of high-density packaging of electronic components is provided with a solder pin 98 or a solder pin 100 on the solder pad 95 (see FIG. 18). The following ' The description will be based on the examples. [Examples] (Example 1) (1) First, a double-sided circuit board constituting a multilayer substrate was prepared. This circuit board uses a single-sided copper-clad laminate as a raw material. The single-sided copper-clad laminate is obtained by laminating, heating, and pressing a glass cloth to impregnate an epoxy resin to form a B-stage prepreg and copper foil. This insulating substrate 10 has a thickness of 75 Å and a copper foil 丨 2 has a thickness of 12 Å. An adhesive layer with a thickness of 10 is laminated on the surface opposite to the copper foil formation surface of the laminated board, and the thickness of the film itself is 12 _ And the like like a film 14 ° 二氧化碳 Secondly, a carbon dioxide gas laser is irradiated from the PET film 14 to form a path through the PET film 14 and the insulating substrate 10 to reach the steel drop 12.
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經濟部智慧財產局員工消費合作社印製 512653 A7 ----------B7__ 五、發明說明（44 ) 孔形成用開口 16，並將其開口 16内利用紫外線雷射照射 進行反拖尾（desmear)處理。 在此實施例，形成通路孔形成用的開口使用三菱電機製 的南峰値短脈衝振盪型二氧化碳氣體雷射加工機，在樹脂 面層疊全體厚度22靖的PET薄膜的基材厚度乃㈣的玻璃 布環氧樹脂基材用光罩影像法從PET薄膜側進行雷射束照 射且以100孔/秒的速度开）成丨5〇 ^ m必的通路孔形成用開 口 〇 此外，使用反拖尾（desmear)處理用的YAG第三增你 t 外線雷射裝置使用三菱電機公司製的GT 605 LD7,爲了其 ^拖尾處理的雷射照射條件係發送頻率爲5 KHz、脈衝能 量爲0.8 mJ、發射數爲1 〇。 (3) 對於結束反拖尾處理的基板施以以銅箔丨2爲電鍍導線 的電解鍍銅處理，在開口 16上部留下微小的間隙，^其開 口 16内充填電解銅鍰層18而形成通路孔2〇。 (4) 再者，以PET薄膜14爲印刷罩幕，在充填於開口 “的 銅鍍層18上充填導電性糊22，形成從絕緣性基材1〇表面 大约僅PET薄膜14厚度部分突出的突起狀導體24。 (5) 其次，使PET薄膜14從絕緣性基材10表面剥離後，將 環氧樹脂黏接劑塗佈於突起狀導體2 4側的全面，以i 進行3 0分敲的乾燥而形成厚度2 〇 # m的黏接劑層2 6上。 (6) 將厚度12"m的銅箔28在加熱溫度180°C、加熱時間7〇 分鐘、壓力2 MPa、眞空度2·5 X103 Pa的條件下加熱加壓於 在上述（5)形成的黏接劑層2 6上。 -47- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------I---^^裂--------訂---------線^^- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（45 ) (7) 其後，對基板兩面的銅箔丨2及2 8施以適當的蝕刻處 理，形成導體電路30及32(包含通路焊接區），製作兩面 電路基板3 4。 (8) 其次，製作層疊用單面電路基板。此電路基板使用和 兩面電路基板34同樣的單面鍍銅膜層疊板作爲原材料。 先對絕緣性基材1 〇上的銅箔丨2施以適當的蝕刻處理，形 成導體電路40，再在和導體電路4〇位於相反側的絕緣性 基材1 0表面層疊PET薄膜1 4。 (9) 其後，藉由按照上述（2)〜(5)製程進行處理，在絕緣性 基材1 0方表面形成導體電路4 0，在從絕緣性基材丨〇他 方面達到導體電路40的開口内充填電解銅鍍層18，同時 在其電解銅鍍層18上形成突起狀導體44,再在包含突起 狀導，44的絕緣性基材1〇表面塗佈環氧樹脂黏接劑46。 此環氧樹脂黏接劑被預固化（precure)，形成爲了多層化 的黏接劑層，製作三片這種單面電路基板5〇。 (_1〇)，由上述（1)〜(9)處理所形成的一片兩面電路基板34和 三片單面電路基板50、52及54堆積於如圖3所示的預定位 置，藉由使用眞空熱加壓以18(rc&溫度層疊一併加壓， 製成多層化基板6〇。 (、11)構成這種多層電路基板6〇的最外側電路基板中，在一 方％路基板50(下層基板）的導體電路4〇上利用熔化溫度 約23〇°C的錫/銻焊錫連接τ腳端64或焊錫球的，在他方電路 基板5 4 (上層基板）的導體電路4 〇上供應溶化溫度約1 $ 31 的由錫/鉛焊錫構成的焊錫體，形成焊錫突起62而製作多 -48- 本紙張尺度週用中國國家標準（CNS)A4規格（210 X 297公爱） --------^--------- (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（46 ) =電路基板，再在將電予零件82載置於此多層電路基板的 層電路基板的狀態，在錫/鉛焊錫熔點附近的氣氛内使 其回流，藉由使焊錫突起62熔化固定電子零件82的焊錫 球84,製造由多層電路基板和電子零件構成的半導體裝 置。 (實施例2) 將四層單面電路基板層疊於如圖丨所示的預定位置，藉 =一併加熱加壓形成多層化基板，對於位於最外側的一 ^ 電路基板的導體電路（導體焊接區）形成焊錫突起，對於加 熱加壓露出於他方電路基板外側的突起狀導體所形成的焊 錫焊接區黏接T腳端或焊錫球，除此之外，和實施例丨同樣 製造多層電路基板及半導體裝置。 (實施例3 ) 如圖2所示，形成如下述的結構：四層單面電路基板 中，將位於最外側的電路基板一方在形成於其導體電路的 焊錫焊接區上形成焊錫突起，將位於最外侧的電路基板他 方在設於絕緣性基材的開口不充填電解銅鍍層；形成下述 構造：在形成於露出於其開口内的導體電路的焊錫焊接區 供應焊錫體而使T腳端連接·，除此之外，和實施例1同樣製 造多層電路基板及半導體裝置。 (實施例4) 如圖2所示，四層單面電路基板中，在位於最外側的表 面及背面的電路基板上設置抗焊層，在由形成於其抗焊層 的開口露出的焊錫焊接區上形成焊錫突起，除此之外，和 -49- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) A7 A7 經濟部智慧財產局員工消費合作社印製 ~-------— B7_____ 五、發明說明（47 ) 貫施例3同樣製造多層電路基板及半導體裝置。 (實施例5 ) 如圖1所示，四層單面電路基板中，在位於最外側的表 面及背面的電路基板上設置抗焊層，在由形成於其抗焊層 口露出的焊錫焊接區上形成焊錫突起，除此之外，和 實施例3同樣製造多層電路基板及半導體裝置。 (貫施例6) (1) 進行按照實施例1的製程（1)〜（1〇)的處理，製造L/S=75"m /75"m、焊接區直徑爲25〇"m、通路孔口徑爲15〇"爪、導體 層厚度爲12απι、並且絕緣層厚度爲75//111的多層化核心基 板6 0。 (2) 其次，將在兩面形成導體電路4〇的多層核心基板6〇參 照圖15a))浸潰於由硫酸銅8 g/i、硫酸鎳〇·6 g、擰檬酸15 g/Ι、次磷酸鈉29 g/Ι、硼酸31 g/Ι、界面活性劑〇1 g/1構成的 PH=9的無電鍍液，在該導體電路4〇表面形成厚度3"^^^ 由銅-鎳-磷構成的粗化層62。其次，將其基板水洗，以5〇χ： 一小時浸潰於由0.1 mol/1氟硼化錫-丨.0 m〇1/1硫脲液構成的 播電解錫取代電鍍浴’在前述粗化層6 3表面設置〇 · 3 ^ m的 錫層（參照圖15(b)，但關於錫層則不圖示）。 (3) 混合授掉在下述①〜③得到的成分物，調製無電錢用黏 接劑。 ①攪拌混合線型酚醛甲酚型環氧樹脂（日本化藥製、分 子量2500) 25%丙烯化物3 5重量份（固體成分8〇%)、感光性 單體（東亞合成製、ALONICSM 315 ) 4重量份、消泡劑 -50- 本紙張尺度適用中國國家標準（cns)a4規格（210 x 297公釐） -----------4^裳--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 512653 第089124881號專利申請案 中文說明書修正頁（91年6月）五、發明説明（ ） 48 A7 B7 年月 g修it 補充 (SANNOPUCO製、S-65) 0.5重量份、NMP 3.6重量份。 ② 混合聚醚颯（PES) 8重量份、環氧樹脂粒子（三洋化成 製、POLYMER POLL)平均粒徑0.5 "m者7.245重量份後， 再添加NMP 20重量份攪:拌混合。 ③ 攪拌混合咪唑硬化劑（四國化成製、2E4MZ-CN) 2重量 份、光開始劑（TIBAGEIGI 製、IRGACURE 1_907) 2 重量 份、光敏劑（日本化藥製、DETX-S) 0.2重量份、NMP 1.5 重量份。 (4) 在施以上述（2)處理的基板60上塗佈在前述（3)調製的 無電鍍用黏接劑（參照圖1 5(c))，在使其乾燥而形成黏接劑 層的其基板6 0兩面使印刷有85 /zm p黑圓的光罩薄膜密合， 利用超高壓水銀燈以500 mJ/cm2曝光。將此用DMDG (二甘 醇二甲醚)溶液噴射顯影，藉此在黏接劑層形成成為85 p 的通路孔的開口 65a。再將該基板利用超高壓:水銀燈以3000 mJ/cm2曝光，藉由進行以l〇〇°C —小時、其後以150°C五小 時的加熱處理，形成有相當於光罩薄膜的尺寸精度佳的開 口的厚度35 的層間絕緣材層6 5 (黏接劑層）（參照圖 15(d))。又，使成為通路孔的開口 65a部分地露出鍍錫 層。 (5) 將形成通路孔形成開口 6 5的基板浸潰於鉻酸二十分 鐘’溶解除去存在於黏接劑層表面的環氧樹脂粒子，使該 黏接劑層65表面以Rmax=l〜5 //m程度的深度粗化而形成粗 化面65b，其後浸潰於中和溶液（SIPLEY公司製）之後水 洗。 (6) 對於黏接劑層表面的粗化層65 b(粗化深度3.5 # m)給與 鈀觸媒（A丁丁製），藉此給與黏接劑層05及通路孔形成用開 -51 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 512653Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 512653 A7 ---------- B7__ V. Description of the invention (44) The opening 16 for hole formation, and the inside of the opening 16 is reversed by ultraviolet laser irradiation. Tail (desmear) processing. In this embodiment, the opening for forming the via hole is formed using a Mitsubishi Electric short pulse oscillation type carbon dioxide gas laser processing machine of Mitsubishi Electric, and a PET film having a thickness of 22 Å and a thickness of 22 Å is laminated on the resin surface. The epoxy substrate was irradiated with a laser beam from the PET film side using a mask image method and opened at a rate of 100 holes / second) to form a necessary opening for forming a via hole of 50 μm. In addition, anti-tailing ( desmear) YAG third booster. The external laser device uses GT 605 LD7 manufactured by Mitsubishi Electric Corporation. For the laser irradiation conditions of the tailing treatment, the transmission frequency is 5 KHz, the pulse energy is 0.8 mJ, and the emission The number is 10. (3) The substrate that has been subjected to the anti-tailing treatment is subjected to electrolytic copper plating treatment using copper foil 2 as a plating wire, leaving a slight gap in the upper part of the opening 16, and the opening 16 is formed by filling the electrolytic copper rhenium layer 18 Via hole 20. (4) Furthermore, using the PET film 14 as a printing mask, a conductive paste 22 is filled on the copper plating layer 18 filled in the openings to form protrusions that protrude from the surface of the insulating substrate 10 only about the thickness portion of the PET film 14 (5) Next, after the PET film 14 is peeled from the surface of the insulating substrate 10, an epoxy resin adhesive is applied to the entire surface of the protruding conductor 24, and 30 minutes are tapped with i. It is dried to form an adhesive layer 26 having a thickness of 20 mm. (6) A copper foil 28 having a thickness of 12 " m is heated at a temperature of 180 ° C, a heating time of 70 minutes, a pressure of 2 MPa, and a porosity of 2 · 5 X103 Pa under heat and pressure on the adhesive layer 2 6 formed in the above (5). -47- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- ----- I --- ^^ Crack -------- Order --------- Line ^^-(Please read the precautions on the back before filling this page) Ministry of Economy Wisdom Printed by A7 in the Consumer Cooperative of the Property Bureau V. Description of the invention (45) (7) After that, the copper foils 2 and 2 8 on both sides of the substrate were appropriately etched to form conductor circuits 30 and 32 (including via soldering areas) ), Making Double-sided circuit board 34. (8) Next, a single-sided circuit board for lamination is produced. This circuit board uses the same single-sided copper-plated laminated board as the double-sided circuit board 34 as a raw material. The copper foil 2 is subjected to an appropriate etching process to form a conductor circuit 40, and then a PET film 14 is laminated on the surface of the insulating substrate 10 on the opposite side to the conductor circuit 40. (9) Thereafter, by following (2) ~ (5) The process is processed to form a conductor circuit 40 on the surface of the insulating substrate 10, and an electrolytic copper plating layer 18 is filled into the opening of the conductor circuit 40 from the insulating substrate, and at the same time, A protruding conductor 44 is formed on the electrolytic copper plating layer 18, and an epoxy adhesive 46 is coated on the surface of the insulating substrate 10 including the protruding conductor 44. This epoxy adhesive is pre-cured ( precure) to form an adhesive layer for multilayering, and make three such single-sided circuit substrates 50. (_10), one of the two-sided circuit substrates 34 and three formed by the processes (1) to (9) above. The single-sided circuit boards 50, 52, and 54 are stacked in a predetermined shape as shown in FIG. The multilayer circuit board 60 is formed by laminating and pressing at a temperature of 18 (rc & temperature) by using air heat pressure. (1, 11) One of the outermost circuit boards constituting such a multilayer circuit board 60 The conductor circuit 40 of the circuit board 50 (lower substrate) is connected to the conductor circuit of the τ foot 64 or the solder ball by tin / antimony solder having a melting temperature of about 23 ° C, and the conductor circuit of the other circuit substrate 5 4 (the upper substrate) A solder body composed of tin / lead solder with a melting temperature of about $ 31 is supplied on 4.0, and the solder protrusions 62 are formed to make more than -48. This paper is based on Chinese National Standard (CNS) A4 specifications (210 X 297). ) -------- ^ --------- (Please read the notes on the back before filling out this page) A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ) = Circuit board, and in the state where the electric component 82 is placed on the layer circuit board of the multilayer circuit board, it is reflowed in an atmosphere near the melting point of tin / lead solder, and the solder protrusion 62 is melted to fix the electronic part. 82 solder balls 84 to manufacture semiconductors composed of multilayer circuit boards and electronic parts Device. (Example 2) A four-layer single-sided circuit board is laminated at a predetermined position as shown in FIG. 丨, and a multilayer substrate is formed by heating and pressing together. For a conductor circuit (conductor welding) of a circuit board located at the outermost side Area) to form solder bumps. T-ends or solder balls are bonded to the solder pads formed by the protruding conductors exposed to the outside of the other circuit substrate by heating and pressure. Except for this, a multilayer circuit substrate is manufactured in the same manner as in Example 丨 and Semiconductor device. (Embodiment 3) As shown in FIG. 2, a structure is formed as follows: In a four-layer single-sided circuit board, a solder bump formed on a solder pad formed on a conductor circuit of the circuit board on the outermost side of the circuit board is formed on the circuit board on the outermost side. The outermost circuit board is not filled with an electrolytic copper plating layer in an opening provided on an insulating substrate; the following structure is formed: a solder body is supplied to a solder pad of a conductor circuit formed in the opening exposed to connect the T pin end; · Other than that, a multilayer circuit board and a semiconductor device were manufactured in the same manner as in Example 1. (Embodiment 4) As shown in FIG. 2, in a four-layer single-sided circuit board, a solder resist is provided on the circuit board located on the outermost surface and the back, and solder is exposed by solder exposed from the opening formed in the solder resist. Solder bumps are formed on the area, in addition, and -49- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ install --- ----- Order --------- line (Please read the notes on the back before filling this page) A7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ~ -------— B7_____ V. Description of the Invention (47) In the third embodiment, a multilayer circuit substrate and a semiconductor device are also manufactured. (Embodiment 5) As shown in FIG. 1, in a four-layer single-sided circuit board, a solder resist layer is provided on a circuit board located on the outermost surface and the back surface, and a solder pad is exposed from a solder resist formed on the circuit board. A multilayer circuit board and a semiconductor device were manufactured in the same manner as in Example 3 except that a solder bump was formed thereon. (Example 6) (1) The processes (1) to (10) according to Example 1 were performed to produce L / S = 75 " m / 75 " m, and the diameter of the welding zone was 25. " m, The multilayer core substrate 60 has a via hole diameter of 15 °, a claw, a conductor layer thickness of 12αm, and an insulation layer thickness of 75 // 111. (2) Next, the multilayer core substrate 60 on which conductor circuits 40 are formed on both sides (see FIG. 15a)) is immersed in copper sulfate 8 g / i, nickel sulfate 0.6 g, citric acid 15 g / 1, An electroless plating solution having a pH of 9 composed of sodium hypophosphite 29 g / 1, boric acid 31 g / 1, and a surfactant 〇1 g / 1, and a thickness of 3 is formed on the surface of the conductor circuit 40. ^^^ Made of copper-nickel -A roughened layer 62 made of phosphorus. Next, the substrate was washed with water and immersed at 50 × for one hour in a plating bath consisting of 0.1 mol / 1 tin borofluoride- 丨 .0 m〇1 / 1 thiourea solution instead of the plating bath. A 0.3 μm tin layer is provided on the surface of the chemical layer 63 (see FIG. 15 (b), but the tin layer is not shown). (3) The components obtained in the following ① to ③ are mixed and mixed to prepare an adhesive for non-power money. ① Stir and mix novolac cresol-type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) 25% acryl 3 5 parts by weight (80% solids), photosensitive monomer (manufactured by Toa Kosei, ALONICSM 315) 4 weight Servings, antifoaming agent-50- This paper size applies to Chinese national standard (cns) a4 specification (210 x 297 mm) ----------- 4 ^ 衣 -------- Order --------- Line (Please read the notes on the back before filling this page) 512653 Revised Page of Chinese Specification for Patent Application No. 089124881 (June 91) V. Description of Invention () 48 A7 B7 years It is supplemented with 0.5 parts by weight (SNO65, manufactured by SANNOPUCO) and 3.6 parts by weight of NMP. ② After mixing 8 parts by weight of polyether ether (PES) and epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd., POLYMER POLL) with an average particle size of 0.5 " m, 7.245 parts by weight, and then adding 20 parts by weight of NMP, stir and mix. ③ Stir and mix 2 parts by weight of imidazole hardener (manufactured by Shikoku Kasei, 2E4MZ-CN), 2 parts by weight of photoinitiator (manufactured by TIBAGEIGI, IRGACURE 1_907), 0.2 parts by weight of photosensitizer (manufactured by Nippon Kayaku, DETX-S), NMP 1.5 parts by weight. (4) The substrate 60 subjected to the above (2) treatment is coated with the electroless plating adhesive prepared in the above (3) (see FIG. 15 (c)), and dried to form an adhesive layer. On both sides of the substrate 60, a mask film printed with a black circle of 85 / zm p was adhered, and exposed at 500 mJ / cm2 using an ultra-high pressure mercury lamp. This was spray-developed with a DMDG (diethylene glycol dimethyl ether) solution, thereby forming an opening 65a forming a via hole of 85 p in the adhesive layer. This substrate was then exposed to 3000 mJ / cm2 with an ultra-high pressure: mercury lamp, and subjected to a heat treatment at 100 ° C for one hour, and then at 150 ° C for five hours to form a dimensional accuracy equivalent to a mask film. The interlayer insulating material layer 6 5 (adhesive layer) having a preferable opening thickness of 35 (see FIG. 15 (d)). The opening 65a serving as a via hole partially exposes a tin plating layer. (5) The substrate forming the via hole forming opening 65 is immersed in chromic acid for twenty minutes to dissolve and remove the epoxy resin particles existing on the surface of the adhesive layer, and make the surface of the adhesive layer 65 with Rmax = l ~ The roughened surface is formed to a depth of 5 // m to form a roughened surface 65b, and then immersed in a neutralization solution (manufactured by SIPLEY) and washed with water. (6) For the roughened layer 65 b (roughened depth 3.5 # m) on the surface of the adhesive layer, a palladium catalyst (made of butadiene) is given, thereby opening the adhesive layer 05 and forming via holes- 51-This paper size applies to China National Standard (CNS) A4 (210X297 mm) 512653
第089124881號專利申請案 ^ Η ' η 中文說明書修正頁（91年6月)_Bj_勸 五、發明説明（ ） 49 口 65a表面觸媒核。 (7)將基板浸潰於以下成分的無電解鍍銅浴中，在粗化面 全體形成0.6 的無電解鍍銅膜67(參照圖15(f))。此時， 其無電解鍍膜67薄而在其膜表面觀察到追隨黏接劑層65 的粗化面6 5 b的凹凸 0 [無電鍍水溶液] NiS04 0.003 mol/1 酒石酸 0.20 mol/1 硫酸銅 0.03 mol/1 HCHO 0.05 mol/1 NaOH 0.10 mol/1 ^α -二氮苯基 40 mg/1 聚乙二醇 （PEG) ·· 0·1 g/1 [無電鍍條件] 3 3 °C的液溫度 (8)將市售的感光性乾膜貼於在前述（7)形成的無電解鍍銅 膜67上，載置光罩， 以100 mJ/cm2曝光，以0.8%碳酸鈉顯 影處理，設置厚度15/zm的抗鍍層68(參照圖16(a))。 (9)其次，按照以下條件在抗鍍層非形成部分施以電解電 鍍，設置厚度20/zm的電解電鍍膜69而設置為了形成上層 導體電路104的導體層，同時將開口部内用電鍍膜69充填 而形成通路孔1 02(參照圖16(b))。 [電解電鍍水溶液] 硫酸銅、五水合物 :60 g/1 -52- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)Patent application No. 089124881 ^ Η 'η Chinese Manual Correction Page (June 91) _Bj_Persuade 5. Description of Invention () 49 65a Surface Catalyst Core. (7) The substrate was immersed in an electroless copper plating bath having the following composition, and an electroless copper plating film 67 of 0.6 was formed on the entire roughened surface (see Fig. 15 (f)). At this time, the electroless plating film 67 was thin, and unevenness following the roughened surface 6 5 b of the adhesive layer 65 was observed on the film surface. 0 [electroless plating solution] NiS04 0.003 mol / 1 tartaric acid 0.20 mol / 1 copper sulfate 0.03 mol / 1 HCHO 0.05 mol / 1 NaOH 0.10 mol / 1 ^ α-diazophenyl 40 mg / 1 polyethylene glycol (PEG) ·· 0 · 1 g / 1 [No plating conditions] 3 3 ° C Temperature (8) A commercially-available photosensitive dry film was affixed to the electroless copper-plated film 67 formed in the above (7), a photomask was placed thereon, exposed at 100 mJ / cm2, and developed with 0.8% sodium carbonate. A plating resist 68 having a thickness of 15 / zm (see FIG. 16 (a)). (9) Next, electrolytic plating is applied to the non-plated portion of the anti-plating layer in accordance with the following conditions, and an electrolytic plating film 69 having a thickness of 20 / zm is provided to form a conductor layer for forming the upper conductor circuit 104, and the opening is filled with the plating film 69 Via holes 102 are formed (see FIG. 16 (b)). [Aqueous electrolytic plating solution] Copper sulfate, pentahydrate: 60 g / 1 -52- This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)
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512653 第089124881號專利申請案 中文說明書修正頁（91年6月)_B7; …：:… ,_ 五、發明説明（ ） 50 均 4匕齊J (ATOTEC製、HL) : 40 ml/1 硫酸 ：190 g/1 光澤劑（ATOTEC製、UV) ： 0.5 ml/1 氯離子 ：40 ppm [電解電鍍條件] 發泡 ：3.0公升/分 電流密度 ：0.5 A/dm2512653 No. 089124881 Patent Application Chinese Specification Revised Page (June 91) _B7;… ::…, _ V. Description of the Invention () 50 All 4 DJ (ATOTEC, HL): 40 ml / 1 sulfuric acid: 190 g / 1 gloss agent (manufactured by ATOTEC, UV): 0.5 ml / 1 chloride ion: 40 ppm [electrolytic plating conditions] foaming: 3.0 liters / minute current density: 0.5 A / dm2
設定電流值 ：0.18 A 電鍍時間 ：130分 (10) 剝離、除去抗鍍層6 8後，用硫酸和過氧化氫混合液 或過硫酸納、過硫酸铵等姓刻液溶解、除去抗鍍層下的無 電鍍膜67，形成由無電鍍膜67和電解鍍銅膜69構成的厚 度約20 、L/S=25 /zm/25 的上述導體電路104。此 時，通路孔102表面為平坦，導體電路表面和通路孔表面 的水平面相同。 (11) 在此基板和上述（2)同樣形成粗化層1 12，再反覆上述 (3)〜（10)的程序，再形成上層的層間樹脂絕緣層1 08和導 體電路110(包含通路孔80)，在多層化基板60兩面形成 積層配線層。 又，此處雖然在導體電路110表面設置由銅-鎳-磷構成 的粗化層1 1 2，但在此粗化層1 1 2表面不形成錫取代電鍍 層。 (12) 另一方面，混合將其溶解於DMDG的60重量％的線型 酚醛甲酚型環氧樹脂（曰本化藥製）的環氧基50%丙烯化的給 與光敏性的低聚物（分子量4000) 46.67重量份、使其溶解 -53- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 512653Set current value: 0.18 A Plating time: 130 minutes (10) After stripping and removing the anti-plating layer 6 8, use a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate to dissolve and remove the under plating layer. The electroless plated film 67 forms the conductor circuit 104 having a thickness of about 20 and an L / S = 25 / zm / 25 composed of the electroless plated film 67 and the electrolytic copper plated film 69. At this time, the surface of the via hole 102 is flat, and the horizontal plane of the surface of the conductor circuit and the surface of the via hole is the same. (11) On this substrate, the roughened layer 1 12 is formed in the same manner as in (2) above, and the procedures of (3) to (10) are repeated, and then the upper interlayer resin insulation layer 108 and the conductor circuit 110 (including via holes) are formed. 80). Laminated wiring layers are formed on both sides of the multilayer substrate 60. Here, although a roughened layer 1 12 made of copper-nickel-phosphorus is provided on the surface of the conductor circuit 110, no tin-plated layer is formed on the surface of the roughened layer 1 12 here. (12) On the other hand, 60% by weight of a novolac cresol-type epoxy resin (manufactured by Honwa Pharmaceutical Co., Ltd.) dissolved in DMDG and mixed with 50% of an epoxy group to give a photosensitive oligomer (Molecular weight 4000) 46.67 parts by weight to make it dissolve -53- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 512653
經濟部智慧財產局員工消費合作社印製 五、發明說明（51 )Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (51)
万；甲乙酮的8 0重量％的雙酚A型環氧樹脂（油化殼製、 EPIKOTE 1001) 14.121重量份、咪唑硬化劑（四國化成製、 2E4MZ-CN) 1.6重量份、爲光敏性單體的多價丙烯酸單體 (日本化藥製，R 604) 1.5重量份、同多價丙烯酸單體（共榮 社製、DPE6A) 30重量份？由丙烯酸酯聚合物構成的均化 劑（共榮社製、POLYFLOW No· 75) 0.36重量份，對此混合 物添加作爲光開始劑的苯酮（關東化學製）2 〇重量份、作爲 光敏劑的EAB (保土十谷化學製）0.2重量份，再添加DMDG (二甘醇二甲醚）1〇重量份，得到將黏度在25。〇調整到1·4± 0 · 3 p a · s的抗焊成分物。 又，黏度測量用B型黏度計（東京計器、DVL-B型）進 行’ 60 rpm的情況根據轉子No· 4，6 rpm的情況根據轉子 No· 3 〇 (13) 將在前述（12)得到的抗焊成分物以2〇//rn厚度塗佈於在 上述（11)得到的積層配線層的兩面。其次，進行在7〇〇c 2〇 分鐘、在70°C 30分鐘的乾燥處理後，將用鉻層描繪抗焊層 開口 α卩的圓圖案（光罩圖案）的厚度$ mm的驗石灰玻璃使形 成鉻層側與抗焊層密合而以1〇〇〇 mj/cm2的紫外線曝光，進 行DMTG顯影處理。再在80°C !小時、1〇〇Ό i小時、12〇t>c 1小時、1 5 0 °C 3小時的條件下加熱處理，形成焊接部分開 口（開口直徑200 #m)的抗焊層90 (厚度2〇辣）。 (14) 其次，將形成抗焊層90的基板浸潰於由氣化鎳30 g/卜 次磷酸鈉10 g/卜檸檬酸鈉10 g/1構成的pH=5的無電解鍍鎳 液二十分鐘，在開口部形成厚度5 A m的鍍鎳層9 2。再將該基 -54- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) __ 裝--------訂---------線· 512653 第089124881號專利申請案 A7 年月日修立下‘ 中文說明書修正頁（91年6月)_B7 — 補斧· 五I發明説明（ ) 52 板在93°C的條件浸潰於由氰化金鉀2 g/Ι、氯化銨75 g/1、擰 檬酸鈉50 g/Ι、次磷酸鈉10 g/Ι構成的無電解鍍金液二十三 秒鐘，藉此在鍍鎳層92上形成厚度〇.〇3//瓜的鍍金層94。 藉此，在上層導體電路112上形成包鍍鎳層92和鍍金屬 94的焊錫焊接區95，製作適合用於單面三層、兩面六層 的母板的多層電路基板（參照圖17(b))。 在如此製造的多層電路基板，可以多層化核心基板的通 路孔的焊接區形狀為正圓，可以焊接區間距為6〇〇 程 度’所以可密集形成通路孔，可容易達成通路孔的高密度 化。而且，可增加多層化核心基板中的通路孔數，所以可 充分確保多層核心基板内的導體電路和積層配線層内的導 體電路的電氣連接。 此外’對於設於積層配線層最外侧的焊錫焊接區9 5連 接裝載包含LSI等半導體晶片的電子零件的封裝基板的導 電性球（焊球），所以有利於封裝基板的封裝。 (實施例7 ) 在形成於按照實施例6製造的多層電路基板位於最外側 的一方上層導體電路112上的焊錫焊接區95上形成焊錫突 起96，在形成於位於最外侧的他方上層導體電路η]上的 焊錫焊接區95上配設τ腳端98或焊錫球1〇〇，製造適合封 裝基板的多層電路基板（參照圖8 )。 在如此所製造的多層電路基板，由於透過焊錫突起96連 接於[51晶片等電子零件，該焊錫突起96配設於從設於積 層配線層上方的抗焊層9〇開口露出的鍍金層94(焊錫焊接10,000; 80% by weight of methyl ethyl ketone, bisphenol A type epoxy resin (made by oleochemical shell, EPIKOTE 1001) 14.121 parts by weight, imidazole hardener (manufactured by Shikoku Kasei, 2E4MZ-CN), 1.6 parts by weight, is a photosensitive monomer 1.5 parts by weight of polyvalent acrylic monomer (manufactured by Nippon Kayaku Co., Ltd., R 604) and 30 parts by weight of polyvalent acrylic monomer (manufactured by Kyoeisha, DPE6A)? 0.36 parts by weight of a leveling agent (manufactured by Kyoeisha, POLYFLOW No. 75) composed of an acrylate polymer, and 20 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Ltd.) as a photoinitiator and 0.2 parts by weight of EAB (manufactured by Hodogaya Toku Chemical Co., Ltd.), and 10 parts by weight of DMDG (diethylene glycol dimethyl ether) were added to obtain a viscosity of 25. 〇Adjust the solder resist composition to 1-4 ± 0 · 3 p a · s. In addition, the viscosity measurement was performed with a B-type viscometer (Tokyo meter, DVL-B type) in the case of '60 rpm according to the rotor No. 4, and in the case of 6 rpm according to the rotor No. 3 (13) will be obtained in (12) above. The solder resist component was applied to both sides of the laminated wiring layer obtained in the above (11) at a thickness of 20 // rn. Next, after performing a drying treatment at 70 ° C for 20 minutes and 70 ° C for 30 minutes, a circle pattern (mask pattern) with a thickness of $ mm of the lime-inspecting glass will be drawn with a chromium layer to describe the opening pattern of the solder resist layer α 卩. The side where the chromium layer was formed was brought into close contact with the solder resist layer and exposed to ultraviolet light at 1000 mj / cm 2 to perform a DMTG development process. Heat treatment was performed at 80 ° C for 1 hour, 100 hours, 120 hours, and 1 hour, and 1 hour at 150 ° C to form a solder resist with openings (opening diameter 200 #m) at the welding part. Layer 90 (thickness 20). (14) Next, the substrate on which the solder resist layer 90 is formed is immersed in an electroless nickel plating solution of pH = 5 composed of 30 g of vaporized nickel / sodium hypophosphite 10 g / sodium citrate 10 g / 1 In ten minutes, a nickel plating layer 92 having a thickness of 5 A m was formed in the opening portion. Then the base-54- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page) __ Install -------- Order --------- Line · 512653 Patent Application No. 089124881 Revised on the 7th of '7' Chinese Manual Revised Page (June 91) _B7 — Supplementary Axes · Five I Inventions () 52 Impregnated at 93 ° C in an electroless gold plating solution composed of 2 g / l of gold cyanide, 75 g / 1 of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite. For three seconds, a gold plating layer 94 having a thickness of 0.03 // melon was formed on the nickel plating layer 92. Thereby, a solder pad 95 with a nickel-plated layer 92 and a metal-plated layer 94 is formed on the upper-layer conductor circuit 112, and a multilayer circuit board suitable for a single-sided three-layer and two-sided six-layer motherboard is produced (see FIG. 17 (b). )). In the multilayer circuit board manufactured in this way, the shape of the bonding pads of the via holes of the core substrate can be rounded, and the pitch of the bonding pads can be about 600 °. Therefore, the via holes can be densely formed, and the density of via holes can be easily achieved. . In addition, since the number of via holes in the multilayer core substrate can be increased, the electrical connection between the conductor circuit in the multilayer core substrate and the conductor circuit in the multilayer wiring layer can be sufficiently ensured. In addition, the solder pads 95 provided on the outermost side of the build-up wiring layer are connected to the conductive balls (solder balls) of a package substrate on which electronic components including semiconductor chips such as LSIs are mounted, which is advantageous for package substrate packaging. (Embodiment 7) A solder bump 96 is formed on the solder pad 95 formed on the outermost upper-layer conductor circuit 112 of the multilayer circuit board manufactured according to Embodiment 6, and the other upper-layer conductor circuit η formed on the outermost side Τ foot end 98 or solder ball 100 is arranged on the solder pad 95 on the upper side to manufacture a multilayer circuit board suitable for a package substrate (see FIG. 8). The multilayer circuit board manufactured in this manner is connected to electronic components such as [51 wafers] through solder bumps 96. The solder bumps 96 are disposed on the gold-plated layer 94 exposed from the opening of the solder resist layer 90 provided above the multilayer wiring layer ( Soldering
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-55--55-
A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（53 ) ^ >透過導電性腳端9 8或導電性球100連接於母板上的連 r 等 4導廷性腳端9 8或導電性球1 〇〇設於從設於積 -泉層下方的柷焊層9 〇開口露出的鍍金層9 4 (焊錫焊接 區），所以可高密度封裝電子零件。 (實施例8 ) 在構成夕層化基板的兩面電路基板及單面電路基板的通 y成用的非貫通孔充填導電性糊而形成通路孔，同時 =和开y成孩通路孔同一製程在通路孔上充填導電性糊而 盆突起狀導體，除此之外，和實施例6同樣製造多層電 路基板。 (實施例9 ) 精由使厚度2〜m的環氧樹脂薄膜熱壓接形成層間樹脂絕 、《層’照射二氧化碳氣體雷射而設置直徑6G /zm的通路孔 v成：開口 ’ ~包含其開口内壁面的層間樹脂絕緣層表面 矛用咼錳酸溶液進行粗化處理，@此之外，和實施例6同 樣製造多層電路基板。 最好上述環氧樹脂薄膜是和苯氧基樹脂的樹脂複合體， 使粗化層形成用的粒子含有。 (實施例1 0 ) 在構成夕層化核心基板的兩面電路基板及單面電路基板 勺I路孔形成用的非貫通孔充填導電性糊而形成通路孔， 同時利用和形成該通路孔同_製程在通路孔上充填導電性 糊而形成突起狀導體，除此之外，和實施例9同樣製作多 層電路基板。 -56 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公髮） -----------_ 裝--------訂---------線·- (請先閱讀背面之注意事項再填寫本頁) 512653 第089124881號專利申請案A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (53) ^ > Connected to the motherboard through conductive feet 9 8 or conductive balls 100 etc. 4 Guide feet 9 8 Or the conductive ball 100 is provided on the gold-plated layer 9 4 (soldering pad) exposed from the opening of the solder layer 90 provided below the product-spring layer, so that electronic components can be packaged at high density. (Embodiment 8) The conductive paste is filled in the non-through holes for the through-hole formation of the double-sided circuit board and the single-sided circuit board constituting the multilayer substrate, and via holes are formed. A multilayer circuit board was produced in the same manner as in Example 6 except that the via hole was filled with a conductive paste to form a protruding conductor. (Example 9) An interlayer resin insulation was formed by thermocompression-bonding an epoxy resin film having a thickness of 2 to m, and a via hole having a diameter of 6G / zm was formed by irradiating a layer with a carbon dioxide gas laser. The surface of the interlayer resin insulation layer on the inner wall surface of the opening was roughened with a rhenium manganic acid solution. Other than that, a multilayer circuit board was produced in the same manner as in Example 6. The epoxy resin film is preferably a resin composite with a phenoxy resin, and contains particles for forming a roughened layer. (Example 10) The two-sided circuit substrate and the single-sided circuit substrate that constitute the layered core substrate are filled with a conductive paste to form a via hole, and a via hole is filled with a conductive paste. In the manufacturing process, a conductive paste was filled in the via hole to form a protruding conductor, and a multilayer circuit board was produced in the same manner as in Example 9. -56 This paper size is applicable to China National Standard (CNS) A4 specification (21〇X 297 issued) -----------_ Packing -------- Order ----- ---- Line ·-(Please read the notes on the back before filling this page) 512653 Patent Application No. 089124881
(實施例1 1 ) 精由使厚度20 的聚婦烴樹脂薄膜熱壓接形成屉 脂絕緣層，照射二氧化碳氣體雷射而設置直徑6〇二二： 路孔形成用開口，其後取代形成無電鍍膜，不施以粗化^ 理而利用濺鍍在包含開口内壁面的層間樹脂絕緣層表面: 成厚度Ο.Ι/zm的銅濺鍍膜或鋼_鎳濺鍍膜，除此之外，= 實施例6同樣製造多層電路基板。 (實施例1 2 ) 在構成多層化核心基板的兩面電路基板及單面電路基板 的通路孔形成用的非貫通孔充填導電性糊而形成通路孔， 同時利用和形成該通路孔同一製程在通路孔上充填導電性 糊而形成大起狀導體，除此之外，和實施例丨丨同樣製作 多層電路基板。 (實施例1 3 ) (1) 進行按照實施例！的製程⑴〜（1〇)的處理，製造L/s = 75 # m/ 75 //m、焊接區直徑250 、通路孔口徑15〇 、導體層 厚度12μχη、並且絕緣層厚度75//111的多層化核心基板6Q。 (2) 其次，對於在兩面形成導體電路* 〇的多層化核心基板 6〇 (參照圖12(a))單面施以實施例6的製程（2)〜（14)的處 理’在多層化核心基板60單面形成積層配線層，形成露 出於復盍其上層導體電路1丨2上的抗焊層90的開口 91内 的包含鍍鎳層92和鍍金層94的焊錫焊接區95。 (3) 在上述桿錫焊接區95上形成焊錫突起96，在不形成積 層配線層的多層化基板60的導體電路40上配設T腳端98 ______ -57- 本紙張尺度適用中國國家標準(CNS) A4規格(21〇χ 297公釐)(Example 1 1) A 20-mm-thick polyethylene resin film was thermocompression-bonded to form a drawer grease insulation layer, and a carbon dioxide gas laser was irradiated to set a diameter of 6022. An opening for hole formation was formed, which was then replaced to form a non-electricity. Plating film, without roughening ^, by sputtering on the surface of the interlayer resin insulation layer including the inner wall surface of the opening: a copper sputtered film or steel_nickel sputtered film having a thickness of 0.1 / zm, other than, implemented Example 6 A multilayer circuit board was produced in the same manner. (Example 1 2) A non-through hole for forming a via hole of a double-sided circuit substrate and a single-sided circuit substrate constituting a multilayer core substrate was filled with a conductive paste to form a via hole, and a via hole was formed in the via using the same process as the formation of the via hole. The hole was filled with a conductive paste to form a large raised conductor, and a multilayer circuit board was produced in the same manner as in Example 丨 丨. (Example 1 3) (1) Perform according to the example! The process （~ (1〇), L / s = 75 # m / 75 // m, the diameter of the solder joint 250, the diameter of the via hole 150, the thickness of the conductor layer 12μχη, and the thickness of the insulation layer 75 // 111 Multi-layered core substrate 6Q. (2) Next, the multi-layered core substrate 60 (see FIG. 12 (a)) on which conductor circuits are formed on both sides (see FIG. 12 (a)) is subjected to the processing (2) to (14) of Example 6 on one side. The core substrate 60 forms a laminated wiring layer on one side, and forms a solder pad 95 including a nickel-plated layer 92 and a gold-plated layer 94 exposed in the opening 91 of the solder resist layer 90 on the upper conductor circuit 1-2. (3) A solder bump 96 is formed on the above-mentioned rod-soldering pad 95, and a T-terminal 98 is arranged on the conductor circuit 40 of the multilayer substrate 60 without forming a laminated wiring layer. ______ -57- This paper size applies to Chinese national standards ( CNS) A4 size (21〇χ 297 mm)
裝 訂Binding
、發明說明（55 卞锡球1 00 ’製造適合封裝基板的單面三層的多層電路 基板（參照圖14(b))。 (實施例1 4 ) 在構成多層化基板的兩面電路基板及單面電路基板的通 經濟部智慧財產局員工消費合作社印製 路孔形成用的非貫通孔充填導電性糊而形成通路孔，同時 利用和形成該通路孔同一製程在通路孔上充填導電性糊而 形成突起狀導體，除此之外，和實施例丨3同樣製造多層電 路基板。 (實施例1 5 ) 全藉由使厚度20//m的環氧樹脂薄膜熱壓接形成層間樹脂絕 、彖層，照射二氧化碳氣體雷射而設置直徑6〇 "瓜的通路孔 /成用開口，將包含其開口内壁面的層間樹脂絕緣層表面 利用鬲錳酸溶液進行粗化處理，除此之外，和實施例丨3同 樣製造多層電路基板。 取好上述環氧樹脂薄膜是和苯氧基樹脂的樹脂複合體， 使粗化層形成用的粒子含有。 (實施例1 6 ) 在構成多層化核心基板的兩面電路基板及單面電路基板 的通路孔形成用的非貫通孔充填導電性糊而形成通路1， 同時利用和形成該通路孔同一製程在通路孔上充填導電性 糊而形成突起狀導體，除此之外，和實施例丨5同樣製 層電路基板。 (實施例1 7 ) 藉由使厚度20ym的聚晞烴樹脂薄膜熱壓接形成層間樹脂 (請先閱讀背面之注意事項再填寫本頁) ---------訂---- I I I I I · -58- 五、發明說明（56 經濟部智慧財產局員工消費合作社印製 層’照射二氧化碳氣體雷射而設置直徑―的通路 二成用開口’其後取代形成無電鍍膜’不施以粗化處理 麻用濺鍍在包含開口内壁面的層間樹脂絕緣層表面形成 与度O.bm的銅濺鍍膜或銅_鎳濺鍍膜，除此之外，和實施 例1 3同樣製造多層電路基板。 (實施例1 8 ) 在構成多層化核心基板的兩面電路基板及單面電路基板 的通路孔形成用的非貫通孔充填導電性糊而形成通路孔， 同時利用和形成該通路孔同一製程在通路孔上充填導電性 糊而开y成突起狀導體，除此之外，和實施例丨7同樣製作多 層電路基板。 (比較例） (1) 以由厚度O.bm的兩面鍍銅膜層疊板構成的絕緣基板爲 核心基板，在該核心基板用鑽孔器鑽直徑3〇〇jum的貫通 孔，其後施以無電鍍、電解電鍍處理而形成包含通孔的導 體層，再在包含通孔的導體層全表面設置粗化層，在通孔 内充填非導電性填孔用充填材料，使其乾燥、硬化。 (2) 其/人，去掉從通孔露出的充填材料而平坦化，在其表 面施以無電鍍、電解電鍍處理賦與厚度而形成導體電路及 成爲覆蓋充填於通孔的充填材料的導體層的部分。 (3) 在形成導體電路及成爲覆蓋充填於通孔的充填材料的 導體層的部分的基板表面形成抗蚀層，蚀刻除去其抗蚀層 非形成部分的電鍍膜，再剝離除去抗蝕層，形成獨立的導 體電路及覆蓋充填材料的導體層。 -59- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 一裝 ----訂----- 線邊 512653 A7 B7 五、發明說明（57 ) 板再按照和實施例4的(2)〜(14)同樣的製程製造多層電路基 關於上述實施例卜5，調查從LSI晶片等電子零件 突起、BGA (球格陣列）或舰（針格陣列）的配線長、焊接 :形：數及焊接區總面積的結果，與習知印刷配線板相 比’在配線長度成爲8/1〇〜1/2，焊接區形成數是！ Η 〇 倍，焊接區面積成爲2/3〜_，可高密度配線，關於實施 例4及5，t確認了作爲封裝基板的絕緣性提高。 訂 關於實施例6〜18 ’調查從LSI晶片等電子零件到焊錫突 起、BGA (球格睁列）或PGA (針格陣列）的配線長及核心焊 接區形成數的結果’與比較例相比，可使配線長縮短 H)〜25% ’使每單位面積（em2)的核心焊接區數增加1()〜观， 未確認到帶給電氣特性或可靠性不良影響。 產業上的利用可能性 如以上説明’根據本發明之多層電路基板，由於以單面 或兩电路基板馬基本結構，該單面或兩面電路基板在硬質 絕緣性基材單面或兩面有導體電路，在從和導體電路形成 面相反側之面由雷射照射所形成的細微開口有充填導電性 物質的通路孔，藉由將這些基板適當組合層疊而一併熱壓 形成的f層化基板可大幅提高基板内的配線密度，不必設 置如以往的通孔，電路基板間的電氣連接透過充填通路孔 可无分確保’所以可適當利用作爲裝載lsi晶片等電子零 件的封裝基板。 再者以這種夕層化基板爲核心，在該多層化核心基板 -60.(Explanation of the invention (55 卞 solder ball 100 ') One-sided, three-layer, multilayer circuit board suitable for package substrates (see Fig. 14 (b)). (Example 1 4) Two-sided circuit boards and single-sided circuits constituting a multilayer substrate The substrate of the Ministry of Economic Affairs, Intellectual Property Bureau, employee consumer cooperative, printed non-through holes for forming via holes, filled with conductive paste to form via holes, and used the same process as the formation of the via holes to fill the via holes with conductive paste to form protrusions. Except for the conductor, a multilayer circuit board was manufactured in the same manner as in Example 3. (Example 1 5) An interlayer resin insulation layer was formed by thermal compression bonding of an epoxy resin film with a thickness of 20 // m. Carbon dioxide gas laser is irradiated to provide a via hole with a diameter of 60, and the opening of the melon is formed. The surface of the interlayer resin insulating layer including the inner wall surface of the opening is roughened with a rhenium manganic acid solution. Example 丨 3 A multilayer circuit board was manufactured in the same manner. The resin composite of the epoxy resin film and a phenoxy resin was taken, and the particles for forming a roughened layer were included. (Example 16) Structure The non-through holes for forming via holes of the double-sided circuit board and the single-sided circuit board of the core substrate are filled with a conductive paste to form the via 1, and the vias are filled with the conductive paste by the same process as the formation of the via holes. Except for the protruding conductor, a circuit board was formed in the same manner as in Example 丨 5. (Example 17) An interlaminar resin was formed by thermal compression bonding of a polyalkylene resin film with a thickness of 20 μm (please read the notes on the back first) Please fill in this page again for matters) --------- Order ---- IIIII · -58- V. Description of the invention (56 Printed layer of the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, set up to irradiate with carbon dioxide gas laser The diameter ― 20% of the via is used to open the opening and then replace it to form an electroless plated film without roughening. Hemp is sputtered on the surface of the interlayer resin insulation layer containing the inner wall surface of the opening to form a copper sputter film or copper with an O.bm_ Except for the nickel sputter coating, a multilayer circuit board was manufactured in the same manner as in Example 13. (Example 18) Non-through holes for forming via holes on the double-sided circuit substrate and the single-sided circuit substrate constituting the multilayer core substrate. A conductive paste is filled to form a via hole, and a conductive paste is filled in the via hole in the same process as the formation of the via hole to form a y-shaped conductor. Except for this, a multilayer circuit board is produced in the same manner as in Example 1.7. (Comparative example) (1) An insulating substrate composed of a double-sided copper-clad laminate with a thickness of O.bm was used as a core substrate, and a through-hole with a diameter of 300jum was drilled through the core substrate with a drill, and then applied. A conductor layer including through-holes is formed by electroless plating and electrolytic plating, and a roughened layer is provided on the entire surface of the conductor layer including through-holes. The through-holes are filled with a filler material for non-conductive hole filling, which is dried and hardened. (2) The person / person is flattened by removing the filling material exposed from the through hole, and applying electroless plating and electrolytic plating treatment to the surface to give a thickness to form a conductor circuit and a conductive layer covering the filling material filled in the through hole. part. (3) forming a resist layer on the surface of the substrate on which the conductor circuit is formed and a portion covering the conductor layer of the filling material filled in the through-hole, and the plating film on the non-forming portion of the resist layer is removed by etching, and the resist layer is peeled off, Form an independent conductor circuit and a conductor layer covering the filling material. -59- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) A7 B7 V. Description of the invention (57) The board was then manufactured in accordance with the same process as (2) to (14) of Example 4 to produce a multilayer circuit substrate. Regarding Example 5 above, investigation was made on the protrusions of electronic parts such as LSI chips, BGA (balls) Grid array) or ship (pin grid array) wiring length, welding: shape: number and the total area of the soldering area results, compared with the conventional printed wiring board 'when the wiring length is 8 / 1〇 ~ 1/2, soldering District formation number is! Η 〇 times, the pad area is 2/3 ~ _, and high-density wiring is possible. Regarding Examples 4 and 5, t confirmed that the insulation of the package substrate is improved. Comparison of Examples 6 to 18 'Results of investigation of wiring length and number of core pads from electronic parts such as LSI chips to solder bumps, BGA (ball grid array) or PGA (pin grid array)' compared with comparative examples , Can shorten the wiring length H) ~ 25% 'increase the number of core pads per unit area (em2) by 1 () ~ view, no adverse effect on electrical characteristics or reliability has been confirmed. The industrial possibility is as described above. The multilayer circuit board according to the present invention has a single-sided or two-sided circuit board structure, and the single-sided or double-sided circuit board has a conductor circuit on one or both sides of a rigid insulating substrate Via holes filled with a conductive substance are formed in the fine openings formed by laser irradiation from the surface opposite to the conductor circuit formation surface. The f-layered substrates formed by heat-pressing the substrates by appropriately combining and laminating them can be used. The wiring density in the substrate is greatly improved, and it is not necessary to provide conventional through holes. The electrical connection between circuit substrates can be ensured through the filling via holes. Therefore, it can be appropriately used as a packaging substrate for mounting electronic components such as lsi chips. Furthermore, with this layered substrate as the core, the multilayer core substrate is -60.
本紙張尺度_ t關雜準（CNS)A4規格(21〇Tiif^T 512653 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（58 單面或兩面設置積層配線層的多層電路基板不但可作爲封 裝基板，而且可適當利用作爲裝載封裝基板的母板。 在位於多層電路基板最外側的一方電路基板形成導電性 突起，在位於最外側的他方電路基板配設導電性腳端或導 電性球的結構適合作爲封裝基板，可高密度配置做和電子 零件或母板的電氣的導電性突起、導電性腳端或導電性 球，所以高密度配線及電子零件的高密度封裝成爲可能。 此外，是也可緩和應力的構造，所以在配線也沒有趣曲， 也可以確保τ腳端或導電性突起的平坦性。 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁}Specifications of this paper _ tS miscellaneous standard (CNS) A4 specification (21〇Tiif ^ T 512653 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (58 Multi-layer circuit board with laminated wiring layer on one or both sides It can be used not only as a package substrate, but also as a motherboard for mounting package substrates. Conductive protrusions are formed on the outermost circuit board of the multilayer circuit board, and conductive pins or conductives are provided on the outermost circuit board. The structure of the sex ball is suitable as a packaging substrate. It can be configured with high density as electrical conductive protrusions, conductive pins or conductive balls of electronic parts or motherboards, so high density wiring and high density packaging of electronic parts are possible. In addition, the structure can also relieve stress, so there is no fun song in the wiring, and the flatness of the τ foot end or the conductive protrusion can be ensured. This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) ) (Please read the notes on the back before filling this page}
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33553499 | 1999-11-26 | ||
| JP2000245650AJP4592890B2 (en) | 1999-11-26 | 2000-08-14 | Multilayer circuit board |
| JP2000245648AJP2001217356A (en) | 1999-11-26 | 2000-08-14 | Multilayer circuit board and semiconductor device |
| JP2000245656AJP4592891B2 (en) | 1999-11-26 | 2000-08-14 | Multilayer circuit board and semiconductor device |
| JP2000245649AJP4592889B2 (en) | 1999-11-26 | 2000-08-14 | Multilayer circuit board |
| Publication Number | Publication Date |
|---|---|
| TW512653Btrue TW512653B (en) | 2002-12-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089124881ATW512653B (en) | 1999-11-26 | 2000-11-23 | Multilayer circuit board and semiconductor device |
| Country | Link |
|---|---|
| US (1) | US6534723B1 (en) |
| EP (2) | EP1760778A3 (en) |
| KR (1) | KR100763692B1 (en) |
| CN (1) | CN1319157C (en) |
| TW (1) | TW512653B (en) |
| WO (1) | WO2001039267A1 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7563342B2 (en) | 2005-04-26 | 2009-07-21 | Tdk Corporation | Method of manufacturing laminated substrate |
| TWI396493B (en)* | 2008-03-28 | 2013-05-11 | Ngk Spark Plug Co | Multi-layer wiring board and method of manufacturing the same |
| TWI513393B (en)* | 2010-07-22 | 2015-12-11 | Ngk Spark Plug Co | Multilayer wiring board and manufacturing method thereof |
| TWI793139B (en)* | 2017-10-20 | 2023-02-21 | 南韓商三星電機股份有限公司 | Printed circuit board |
| TWI813580B (en)* | 2017-10-20 | 2023-09-01 | 南韓商三星電機股份有限公司 | Printed circuit board |
| Publication number | Priority date | Publication date | Assignee | Title |
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