TW502380B - Shielded interconnect for an integrated circuit device - Google Patents

Abstract

A shielded interconnect for reducing capacitive coupling between interconnect wires in an integrated circuit device having interconnect wires separated by an interlevel dielectric and wherein the interconnect wires are provided with thin sidewall conductive shields separated from the interconnect wire by a thin sidewall dielectric. The sidewall shielding reduces cross talk between adjacent wires within an interconnect level. The thin sidewall dielectric material can be chosen to provide reduced capacitance between the sidewall shields and the interconnect wire. The interlevel dielectric can be chosen to provide improved defect resistance and mechanical strength during device fabricating Also described are methods for fabricating the shielded interconnect.

Description

Translated fromChinese

502380 A7 B7 五、發明說明（） 發明領域： 本發明係關於積體電路元件，特別是有關於訊號線與 電源線之電性防護化内連線。 發明背景： 當積體電路元件日漸密集與精巧以滿足升高的速度 需求，内連線之間的距離，不論是訊號線與訊號線間，或 是訊號線與電源線間的距離都變得更為細小。此一導線間 距的縮小將造成訊號線與訊號線，或是訊號線與電源線之 間電谷I禺合效應（Capacitive Coupling)的增強。電容竊合效 應所造成的現象稱之為交談（Cr〇ss-Talk)，此一現象將造成 訊號線上傳輸的訊號發生錯誤，並於訊號傳輸間造成阻抗 電容延遲（Resistive-Capacitive Delay)。 第1圖為一傳統内連線之部分截面圖。下方介電層1〇 承載下層導線12。第一導線22、第二導線24、與第三導 線26則為層間介電層20所覆蓋。層間介電層可由兩層或 兩層以上的水平層所構成。第一内連線22具有頂面22A、 底面22B、與侧面22C。第二内連線24具有頂面24A、底 面24B、與側面24C。第三内連線26具有頂面26A、底面 26B、與侧面26C。層間介電層20的上方則有一由上方介 電層40所覆蓋之上層導線42 ^附帶一提的是，此處的内 連線架構（下層導線12、内連線22、24、26、與上層導線 42)並非特定的内連線結構，而僅是用以說明三層相連之 内連線結構而已。 . 第2頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） {請先閱讀背面之注意事項再填寫本頁) ·· 經濟部智慧財產局員工消費合作社印製 502380 A7 __— B7 五、發明說明（） 為了簡化描述方程式，第一内連線與第三内連線與第 二内連線之距離以及其材質皆假定為相同，同時其邊緣的 場效應亦予以忽略。因此，位於第二内連線24上的電容 元件將包含位於第二内連線24與第一及第三内連線22、 26之間的電容組件ci，與第二内連線24與上層導線42 之間的電容元件C2，以及第二内連線24與下層導線12 之間的電容元件C3。第一内連線22與第二内連線24之 間的交談現象可由公式1所表示。 (1) CL1L2 E 2Cll{2Cl^C1^C3) 位於第二内連線24上的等效電容則可由公式2所表示。 (2) CeffL2 = 2(2C1+C2 + C3) 為了降低訊號線的電容，一些低介電常數的材料被陸 續提出以取代傳統的介電材料如二氧化矽（Si〇2)、四乙基 矽酸鹽氧化物（TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃 (PSG)、硼磷矽玻璃（BPSG) 〇這些傳統材料的等效介電常 數的因次約在4-5次方之間。而新介電材料材料，如有機 發泡材料或有機玻璃之因次則小於4次方，一般而言約介 於1·5-3之間。舉例而言，低介電常數材料包括含氫矽酸 鹽（Hydrogen Silsesquoixane，HSQ)、甲基梦酸鹽（Methyl502380 A7 B7 V. Description of the invention () Field of the invention: The present invention relates to integrated circuit components, and in particular, to the electrical protective interconnection of signal lines and power lines. Background of the Invention: As integrated circuit components become denser and more sophisticated to meet increased speed requirements, the distance between interconnects, whether it is between the signal line and the signal line, or the distance between the signal line and the power line becomes More subtle. The reduction of the distance between the wires will result in an increase in the capacitive coupling effect between the signal line and the signal line, or between the signal line and the power line. The phenomenon caused by the combination of capacitance theft is called Cr0ss-Talk. This phenomenon will cause errors in the signal transmitted on the signal line and cause a resistive-capacitive delay between signal transmissions. Figure 1 is a partial cross-sectional view of a conventional interconnect. The lower dielectric layer 10 carries a lower-layer wire 12. The first conductive line 22, the second conductive line 24, and the third conductive line 26 are covered by the interlayer dielectric layer 20. The interlayer dielectric layer may be composed of two or more horizontal layers. The first interconnecting line 22 has a top surface 22A, a bottom surface 22B, and a side surface 22C. The second interconnecting line 24 has a top surface 24A, a bottom surface 24B, and a side surface 24C. The third interconnector 26 has a top surface 26A, a bottom surface 26B, and a side surface 26C. Above the interlayer dielectric layer 20 is an upper layer conductor 42 covered by the upper dielectric layer 40 ^ Incidentally, the interconnection structure here (the lower layer conductor 12, the interconnection 22, 24, 26, and The upper wire 42) is not a specific interconnection structure, but is only used to explain the interconnection structure of three layers. . Page 2 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) {Please read the notes on the back before filling out this page) ·· Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 502380 A7 __— B7 V. Explanation of the invention () In order to simplify the description of the equation, the distances and materials of the first and third interconnects and the second interconnect are assumed to be the same, and the field effects at the edges are ignored. . Therefore, the capacitor element on the second interconnector 24 will include a capacitor component ci between the second interconnector 24 and the first and third interconnectors 22 and 26, and the second interconnector 24 and the upper layer. The capacitive element C2 between the conductive lines 42 and the capacitive element C3 between the second interconnecting line 24 and the lower conductive line 12. The conversation phenomenon between the first interconnection 22 and the second interconnection 24 can be expressed by Equation 1. (1) CL1L2 E 2Cll {2Cl ^ C1 ^ C3) The equivalent capacitance on the second inner wiring 24 can be expressed by Equation 2. (2) CeffL2 = 2 (2C1 + C2 + C3) In order to reduce the capacitance of the signal line, some materials with low dielectric constant have been proposed to replace traditional dielectric materials such as silicon dioxide (SiO2), tetraethyl Silicate oxide (TEOS-Oxide), silicon nitride (SiN), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) 〇 The equivalent dielectric constant of these traditional materials is about 4-5 Between powers. The factors of new dielectric materials, such as organic foamed materials or organic glass, are less than 4 powers, and generally between about 1.5-3. For example, low dielectric constant materials include Hydrogen Silsesquoixane (HSQ), Methyl Methyl Salt

Silsesquoixane，MSQ)、聚芳基醚（Polyarylene Ether) (SILK TM Dow Chemical，Midland Michigan)、二氧化碎空氣凝膠 (Silica Aerogel)。然而此類材料皆為多孔狀結構，具有較 傳統介電材料更小的機械強度，並在某些情況下，此類材 料無法作為氧的阻障層。應用於積體電路内連線技術的半· 第3頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) I -------訂---------線 1' 經濟部智慧財產局員工消費合作社印製 ο 8 3 25. 五 經濟部智慧財產局員工消費合作社印製 A7 B7 - - ---1 —---- 發明說明（） 導體製程時，如形成連接通路、單層或雙層鑲嵌技術製程 中的蝕刻與化學機械研磨步驟，將會於積體電路中造成好 期或長期的缺陷。 發明目的及概述= 本發明描述了一防護化内連線，用以降低積體電路内 連線間的電容耦合效應。内連線之間被層間介電層予以分 隔。此外，内連線之側邊具有受介電材料間隙壁所區隔的 導體間隙壁。此一防護間隙壁的設計降低了在同一内連線 層中，相鄰導線的交談現象。而位於侧壁上的薄介電層， 可用以降低導體間隙壁與内連線之間的電容。而適當的選 用層間介電層，則可以改善電阻缺陷以及增強製造過程中 元件的機械強度。 防護導體係透過形成間隙壁的步騾而得。而防護介電 層則可透過形成間隙壁的步騾，或是均勻的塗佈製程而得 到。 圖式簡單說明： 本發明之新穎的特徵可參見專利申請範圍所示。而本 發明所提出之較佳實施例與其優點，將詳述於發明詳細說 明，並對照下列圖示予以描述： 第1圖為習知技藝中内連線之部份剖面示意圖。 第2圖為本發明中内連線之部份剎面示意圖。 第3圖為部份導線的頂視圖，以描述本發明之電性連接防 第4頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) ·!#--------訂---------線 1' 經濟部智慧財產局員工消費合作社印製 502380 A7 _B7_ 五、發明說明（） 護導體的方法。 第4圖為沿著第3圖之軸線4-4所展開的剖面圖，以描述 本發明之電性連接防護導體的方法。 第5圖至第1 1圖為半導體結構剖面圖，用以說明本發明 之第一實施例的製程方法。 第12圖至第1 7圖為半導體結構剖面圖，用以說明本發明 之第二實施例的製程方法。 第1 8圖至第24圖為半導體結構剖面圖，用以說明本發明 之第三實施例的製程方法。 圖號對照說明： 10 下方介電層 12 下層導線 20 層間介電層 22 第一内連線 24 第二内連線 26 第三内連線 32A 防護介電層 32B 防護導體 34A 防護介電層 34B 防護導體 36A 防護介電層 36B 防護導體 38 防護延伸區域 39 連接通道 40 上方介電層 42 上層導線 44 地線 50 層間介電層 52 溝渠 54 導電層 56 導體間隙壁 60 介電材料間隙壁 62 導電層 64 内連線 70 層間介電層 80 導線 第5頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Silsesquoixane (MSQ), Polyarylene Ether (SILK TM Dow Chemical, Midland Michigan), Silica Aerogel. However, these materials have a porous structure and have less mechanical strength than traditional dielectric materials. In some cases, such materials cannot serve as a barrier to oxygen. The semi-pitch applied to the interconnection technology of integrated circuits. Page 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back? Matters before filling out this page) I- ------ Order --------- Line 1 'Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 3 25. Five Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7--- --1 —---- Description of the invention () During the process of forming conductors, such as the formation of connection paths, single-layer or double-layer damascene technology, the etching and chemical mechanical polishing steps will cause good or long-term in integrated circuits. Defects. Purpose and summary of the invention = The present invention describes a shielded interconnect to reduce the effect of capacitive coupling between interconnects in an integrated circuit. Interconnects are separated by interlayer dielectric layers. In addition, the side of the interconnect has a conductive barrier wall separated by a dielectric material barrier wall. The design of this protective barrier reduces the conversation between adjacent wires in the same interconnect layer. A thin dielectric layer on the sidewall can reduce the capacitance between the conductor gap and the interconnect. The appropriate selection of an interlayer dielectric layer can improve resistance defects and enhance the mechanical strength of the component during the manufacturing process. The protective guide system is obtained through the steps that form the partition wall. The protective dielectric layer can be obtained through the steps of forming the barrier wall or through a uniform coating process. Brief description of the drawings: The novel features of the present invention can be seen in the scope of patent applications. The preferred embodiment of the present invention and its advantages will be described in detail in the detailed description of the invention and described with reference to the following drawings: FIG. 1 is a schematic cross-sectional view of a part of an interconnecting line in the conventional art. FIG. 2 is a schematic view of a part of the brake surface of the inner wiring in the present invention. Figure 3 is a top view of some wires to describe the electrical connection prevention of the present invention. Page 4 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back first? Please fill in this page for more details) ·! # -------- Order --------- Line 1 'Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 502380 A7 _B7_ V. Description of the invention () Conductor method. Fig. 4 is a sectional view taken along the axis 4-4 of Fig. 3 to describe the method for electrically connecting the protective conductor of the present invention. 5 to 11 are cross-sectional views of a semiconductor structure, which are used to explain the manufacturing method of the first embodiment of the present invention. 12 to 17 are cross-sectional views of a semiconductor structure, which are used to explain a manufacturing method of a second embodiment of the present invention. 18 to 24 are cross-sectional views of a semiconductor structure, which are used to explain a manufacturing method of a third embodiment of the present invention. Comparative description of drawing numbers: 10 Lower dielectric layer 12 Lower conductor 20 Interlayer dielectric layer 22 First interconnect 24 Second interconnect 26 26 Third interconnect 32A Protective dielectric layer 32B Protective conductor 34A Protective dielectric layer 34B Protective conductor 36A Protective dielectric layer 36B Protective conductor 38 Protective extension area 39 Connection channel 40 Upper dielectric layer 42 Upper conductor 44 Ground wire 50 Interlayer dielectric layer 52 Trench 54 Conductive layer 56 Conductor barrier wall 60 Dielectric material barrier wall 62 Conductive Layer 64 Inner connection 70 Interlayer dielectric layer 80 Conductor Page 5 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)

I n I n n n n n n n ""*** "**"*"***** 曹 I- n -n n n n n n I n ϋ n I— n t I n n n I» n I 經濟部智慧財產局員工消費合作社印製 502380 A7 —— B7 五、發明說明（） 82 介電層 84 導電層 8 6 導體間隙壁 88 層間介電層 崧明詳細說明： 在金屬内連線的技術中，常利用鑲嵌於層間的導電插 塞連接不同層的導線。為了更清楚的描述本發明的優點， 除非顯示插塞可以更完整的描述本發明的特徵，否則插塞 將不會予以描述。 第2圖為依據本發明所顯示之内連線的部份剖面示意 圖。下方介電層10支撐下層導線12。第一内連線22、第 二内連線24、與第三内連線26則為層間介電層20所覆 蓋。層間介電層20可由兩層或雨層以上的水平層所構成， 如50nm之氮化矽層與500nm之摻氟氧化矽層（FSG)之組 合。第一内連線22具有頂面22A、底面22B、與側面22C。 防護介電層32A、32B則毗鄭於側面22C。第二内連線24A 具有頂面24A、底面24B、與侧面24C。防護介電層34A、 34B則毗鄰於侧面24C。第三内連線26A具有頂面26A、 底面26B、與側面26C。防護介電層36A、36B則毗鄰於 側面260第二内連線24、防護介電層34A、34B組成了 防護内連線3 7。相似地，第一内連線2 2、防護介電層3 2 A、 3 4b，以及第三内連線26、防護介電層36A、36B，則形 成了部份的額外防護内連線。上層導線42則形成於層間 介電層20的上方，並由上方層間介電層40所覆蓋。下方、 層間、與上方介電層10、20、與40可由8丨〇2、丁£〇3-〇义丨(16、- 第6貫 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -#------- •訂---------線 --一-------------------- 502380 A7 B7 五、發明說明（)I n I nnnnnnn " " *** " ** " * " ***** Cao I- n -nnnnnn I n ϋ n I— nt I nnn I »n I Intellectual Property Office employee, Ministry of Economic Affairs Printed by the Consumer Cooperative 502380 A7 —— B7 V. Description of the invention () 82 Dielectric layer 84 Conductive layer 8 6 Conductor spacer 88 Interlayer dielectric layer Song Ming Detailed description: In the technology of metal interconnection, it is often used to embed Conductive plugs between layers connect wires of different layers. In order to describe the advantages of the present invention more clearly, the plug will not be described unless it is shown that the plug can more fully describe the features of the present invention. Fig. 2 is a schematic cross-sectional view of a part of an interconnector shown in accordance with the present invention. The lower dielectric layer 10 supports the lower-layer wires 12. The first interconnect 22, the second interconnect 24, and the third interconnect 26 are covered by an interlayer dielectric layer 20. The interlayer dielectric layer 20 may be composed of two or more horizontal layers, such as a combination of a 50-nm silicon nitride layer and a 500-nm fluorine-doped silicon oxide layer (FSG). The first interconnecting line 22 has a top surface 22A, a bottom surface 22B, and a side surface 22C. The protective dielectric layers 32A and 32B are adjacent to the side 22C. The second interconnecting line 24A has a top surface 24A, a bottom surface 24B, and a side surface 24C. The protective dielectric layers 34A, 34B are adjacent to the side 24C. The third interconnecting line 26A has a top surface 26A, a bottom surface 26B, and a side surface 26C. The protective dielectric layers 36A and 36B are adjacent to the second interconnector 24 on the side 260, and the protective dielectric layers 34A and 34B form the protective interconnector 37. Similarly, the first interconnects 22, the protective dielectric layers 3 2 A, 3 4b, and the third interconnects 26, the protective dielectric layers 36A, 36B, form part of the additional protective interconnects. The upper conductive line 42 is formed above the interlayer dielectric layer 20 and is covered by the upper interlayer dielectric layer 40. The lower, interlayer, and upper dielectric layers 10, 20, and 40 can be 8 丨 02, 丁 〇3-〇 义 丨 (16,-6th paper standard applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page)-# ------- • Order --------- line-- 一 -------- ------------ 502380 A7 B7 V. Description of the invention ()

SiN、PSG、BPSG、FSG、HSQ、MSQ、SILK、SiOxCyHz 等材料所構成，其中FSG或數種材質之複合層則為較佳的 選擇。形成層間介電材料與防護介電層的製程包含化學氣 相沉積法（CVD)、電漿強化化學氣相沉積法（PECVD)、高 密度電漿化學氣相沉積法、旋塗製程、物理氣相沉積法 等。防護介電層 32A、34A、與 36A 可由 Si02、TEOS-Oxide、 SiN、PSG、BPSG、FSG、HSQ、MSQ、SILK、SiOxCyHz 等材料所構成，其中SILK或數種材質之複合層則為較佳 的選擇。防護導體32B、34B、與36B則可為耐火金屬氮 化物、耐火金屬矽化物，或其組合物。適用的耐火金屬包 含 Ti、Zr、Hf、Vd、Nb、Ta、Cr、Mo 與 W。另外，防護 導體32B、34B、與36B可由任何低電阻之金屬所構成， 如A1、Cu、AlCu等。受防護導體與内金屬連線則可以使 用習知的方法形成，如物理氣相沉積法、化學氣相沉積 法、無電電鍍（Electroless Plating)、電鍍（Electro Plating) 等製程。 為了簡化描述方程式，第一内連線、第三内連線與第 二内連線之距離及其材質皆設定為相同，同時其邊緣的場 效應亦予以忽略。因此，第二内連線24包含兩個電容元 件C!，分別位於第二内連線24與防護導體34B之間。此 外，還包含位於第二内連線24與上層導線42之間的電容 元件Cr以及位於第二内連線24與下層導線12之間的電 容元件C3。不論防護介電材料之材質為何，第一内連線 22與第二内連線24之間的交談現象為〇(當邊緣場效應忽- 第7頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） (請先閱讀背面之注意事項再填寫本頁) 0 經濟部智慧財產局員工消費合作社印製 一-口*· * H ϋ n n I n ϋ I .1« n al~ n n n n n n n ϋ n n ϋ n n n n I n n d - 502380 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 略時）。第一内連線24與第二内連線22之間的交談現象. 則可以由公式3所表示。 (3) CL1L2 E 2(^/(2(^ + 2(^ + 0:2 + 0:3) S 〇 當 Cl<<Ci， 位於第二内連線24上的等效電容則可由公式4所表示。 (4) CeffL2=:2(2C !' + C2 + C3) 藉由使用低介電常數材料作為防護介電層32A、34A ' 36八 之材質’ ceffL2值可以進一步的降低。雖然CeffL2對於防 護導體之值可較傳統材料為大或為小，但其交談現象 CL1L2則可予以忽略。 很明顯的，在一個具有多層金屬内連缘的積體電路元 件中，多於一層的内連線層，亦可藉由本發明之防護内連 線結構而形成。 一個用以形成如第3圖與第4圖所示之防護導體將於 後文中加以說明。任何數目的傳統插塞結構，將可用以連 接不同的金屬内連線層。第3圖為一部份導線的頂視圖， 描述了依照本發明以電性連接防護導體之方法。第4圖為 沿第3圖之4-4軸線展開之截面圖，描述了電性連接防護 導體之方法連接上述之内連綠24之結構將用以說明本 發明V防護導體34B具有水平延伸之防護延伸區域38。 此延伸區域的寬度則取決於所使用的積體電路製程技 術。舉例而言，在鑲嵌技術中，使用於延伸區域3 8的溝 渠應該窄到足夠造成掐陷（pinch 〇ff)於防護金屬的沉積製 程中。對於〇·5微米深的鑲嵌溝渠而言，用於形成延伸區 域38的溝渠約為0·2微米寬，而防護導體34Β則填入约 第8頁 本紙張尺度適用中國國家標準(CNS)A4規ά (210x 297公釐]---- _____—,1 一-1—I --------^---------^ J I (請先閱讀背面之注意事項再填寫本頁) 502380 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 0 · 1微米的導電材料。相似的，連接通道3 9則為所使用之 半導體製程的函數。其可包含插塞以連接於地線44，或於 雙重鑲嵌技術中，形成積集垂直向下之延伸地線44。 接著討論本發明中製作防護化導線的製程。第5圖至 第1 1圖為部份的半導體結構剖面圖，用以說明本發明之 製私。如第5圖所示，首先形成溝渠52於層間介電層5〇 之中。層間介電層50的材質可以是Si02、TEOS-Oxide、It is composed of SiN, PSG, BPSG, FSG, HSQ, MSQ, SILK, SiOxCyHz and other materials. Among them, FSG or a composite layer of several materials is a better choice. The processes for forming the interlayer dielectric material and the protective dielectric layer include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition, spin coating process, physical gas Phase deposition and so on. The protective dielectric layers 32A, 34A, and 36A can be composed of Si02, TEOS-Oxide, SiN, PSG, BPSG, FSG, HSQ, MSQ, SILK, SiOxCyHz and other materials. Among them, SILK or a composite layer of several materials is preferred. s Choice. The shield conductors 32B, 34B, and 36B may be refractory metal nitrides, refractory metal silicides, or combinations thereof. Suitable refractory metals include Ti, Zr, Hf, Vd, Nb, Ta, Cr, Mo and W. In addition, the protective conductors 32B, 34B, and 36B may be made of any metal having a low resistance, such as A1, Cu, AlCu, and the like. The connection between the shielded conductor and the inner metal can be formed by conventional methods, such as physical vapor deposition, chemical vapor deposition, electroless plating, and electroplating. In order to simplify the description of the equations, the distances and materials of the first, third, and second interconnects are set to be the same, and the field effects at their edges are ignored. Therefore, the second inner wiring 24 includes two capacitive elements C !, which are respectively located between the second inner wiring 24 and the protective conductor 34B. In addition, it also includes a capacitive element Cr located between the second interconnecting line 24 and the upper layer lead 42 and a capacitive element C3 located between the second interconnecting line 24 and the lower layer lead 12. Regardless of the material of the protective dielectric material, the conversation phenomenon between the first interconnect 22 and the second interconnect 24 is 0 (when the fringe field effect is ignored-page 7 This paper applies Chinese National Standard (CNS) A4 Specifications (210 X 297 meals) (Please read the precautions on the back before filling out this page) 0 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-* * * H ϋ nn I n ϋ I .1 «n al ~ nnnnnnn ϋ nn ϋ nnnn I nnd-502380 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 Β7 V. Description of the invention () omitted). The conversation phenomenon between the first interconnector 24 and the second interconnector 22 can be expressed by Equation 3. (3) CL1L2 E 2 (^ / (2 (^ + 2 (^ + 0: 2 + 0: 3) S 〇 When Cl < & Ci, the equivalent capacitance on the second internal wiring 24 can be calculated by the formula (4) CeffL2 =: 2 (2C! '+ C2 + C3) The value of ceffL2 can be further reduced by using a low dielectric constant material as the protective dielectric layer 32A, 34A '36 eight's material. Although The value of CeffL2 for the protective conductor can be larger or smaller than that of traditional materials, but its conversation phenomenon CL1L2 can be ignored. Obviously, in a integrated circuit component with multiple layers of metal internal edges, more than one layer of internal The connection layer can also be formed by the protective interconnection structure of the present invention. One to form a protective conductor as shown in Figures 3 and 4 will be described later. Any number of conventional plug structures, It will be used to connect different metal interconnect layers. Figure 3 is a top view of a portion of the wire, describing the method of electrically connecting a protective conductor in accordance with the present invention. Figure 4 is 4-4 along Figure 3 A cross-sectional view of the axis expansion, describing the method of electrically connecting the protective conductor. The structure connecting the above-mentioned inner green 24 will be used to say The V-shielding conductor 34B of the present invention has a horizontally extending protective extension region 38. The width of this extension region depends on the integrated circuit process technology used. For example, in the mosaic technology, the trenches used in the extension region 38 should be Narrow enough to cause a pinch 〇ff to be deposited in the protective metal deposition process. For a 0.5 micron deep mosaic trench, the trench used to form the extension region 38 is about 0.2 micron wide, and the protective conductor For 34B, fill in about 8 pages. The paper size applies the Chinese National Standard (CNS) A4 Regulation (210x 297 mm) ---- _____—, 1 -1—I -------- ^- -------- ^ JI (Please read the precautions on the back before filling out this page) 502380 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs V. Description of Invention () 0 · 1 micron conductive material. Similarly, the connection channel 39 is a function of the semiconductor process used. It may include a plug to connect to the ground line 44 or, in the dual damascene technology, the accumulation ground line 44 extending vertically downwards is formed. Process for producing a shielded wire in the present invention. FIGS. 5 to 11 A cross-sectional view of a part of the semiconductor structure is used to illustrate the manufacturing process of the present invention. As shown in FIG. 5, a trench 52 is first formed in the interlayer dielectric layer 50. The material of the interlayer dielectric layer 50 can be Si02, TEOS -Oxide,

SiN、PSG、BPSG、FSG、HSQ、MSQ、SILK、SiOxCyHz 等材料所構成，其中FSG或數種材質之複合層則為較佳的 選擇。相鄰溝渠之深度、寬度、與間距則為所欲製造之防 濩導線之特徵、所使用的製程技術、以及所選用的材料及 其厚度的參數。溝渠的深度、寬度、與間距則隨著導線與 不同的内連線層而有所不同。在第6圖中，沉積一層薄而 均勻之導電層54。均勻導電層54可以包含f方護導體32B、 34B、3 6B，而其材質則可以是耐火金屬氮化物、耐火金屬 碎化物’或其組合物。合適的耐火金屬包含丁卜Zr、Hf、 Vd、Nb、Ta、Cr、Mo與W。參閱第7圖，使用非等向性 之反應離子蚀刻（RIE)製程，以形成導體間隙壁5 6。一般 習知的反應氣體，如SF6、Ch、BCU等，皆可適用於反應 離子蝕刻製程。如第8圖所示，接著沉積一層薄而均勻之 介电層58。若溝渠52之深度為5〇〇nm，則此一介電層的 厚度則約為1 OOnm。均勻介電層58的材質可以是si〇2、 TEOS-Oxide、SiN、PSG、BPSG、FSG、HSQ、MSQ、SILK、It is composed of SiN, PSG, BPSG, FSG, HSQ, MSQ, SILK, SiOxCyHz and other materials. Among them, FSG or a composite layer of several materials is a better choice. The depth, width, and spacing of the adjacent trenches are the characteristics of the anti-corrosion conductors to be manufactured, the process technology used, and the parameters of the selected materials and their thickness. The depth, width, and spacing of trenches vary with the conductor and the different interconnect layers. In Figure 6, a thin and uniform conductive layer 54 is deposited. The uniform conductive layer 54 may include f-square protective conductors 32B, 34B, 36B, and the material thereof may be refractory metal nitride, refractory metal fragments', or a combination thereof. Suitable refractory metals include Dinbu Zr, Hf, Vd, Nb, Ta, Cr, Mo and W. Referring to FIG. 7, an anisotropic reactive ion etching (RIE) process is used to form the conductive spacers 56. Commonly known reactive gases, such as SF6, Ch, BCU, etc., can be applied to the reactive ion etching process. As shown in Figure 8, a thin, uniform dielectric layer 58 is then deposited. If the depth of the trench 52 is 500 nm, the thickness of this dielectric layer is about 100 nm. The material of the uniform dielectric layer 58 may be SiO2, TEOS-Oxide, SiN, PSG, BPSG, FSG, HSQ, MSQ, SILK,

SiOxCyHz等材料所構成，其中FSG或數種材質之複合層. 第9頁 本紙張尺度適用中國國家標準（CNS)A4規格(210 X 297公餐了 __till I IK I Aw------I I · I I--I---^ J Aw- I, (請先閱讀背面之注意事項再填寫本頁) 502380 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 則為較佳的選擇。參閱第9圖，進料 $仃非等向性反應離子蚀 刻以形成由介電材料間隙壁60’以覆蓋導體間隙壁56。 合適的反應氣體包含氟碳化物，如CF4、c2F6等，或氮氣 碳化物，以蝕刻而形成間隙壁。參 ^ 参閱第10圖，沉積形成 -厚導電層62。導電層62可為錮基導體，如丁續心 (5-nm/4〇-nm/1-miCr〇n)，或銘基導體 Ti/TiN/A1Cu(5-nmMO-nmn-micron)，或其他合適的導體。參閱第"圖， 進行化學機械研磨製程以形成内連線6心使用反應離子蚀 刻製程，則可用以曝露出部份位於溝渠頂端的導體間隙壁 56。因此受控制的研磨深度將不僅及於曝露於導線64之 間的介電材料50 ,更包含曝露出足夠的間隙壁6〇以隔離 導線64與導線56。接著可於此半導體結構上形成另一層 間介電層’並重複上述的製程而形成金屬内連線。 第12圖至第17圖為部份之半導體結構剖面圖，用以 描述本發明之第二實施例。本發明第一實施例之材料與步 驟可以等同應用於第二實施例。參閱第12圖，導線8〇形 成於内層間介電層70的上方，而形成的製程包含沉積金 屬層、形成光阻層、蚀刻金屬層、剥除光阻層，或於介電 層中形成鑲嵌導線，並回蝕介電層，等習知之技術。導線 80可為任何導體，或任何導體之組合，如Ti/TiN/AlCu (0·5_3 atomic %Cu) (20-nm/20-nm/l- micron)，並可將其厚 度控制於50-5000nm之間。為了方便描述第12-17圖起 見，其中導體的高度將設定為5 00nm。參閱第13圖，沉 積形成一薄而均勻之介電層82以覆蓋層間介電層70以及 第10貰 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公t ) H 1 i H 1 n n n n 1· n n I n n I n K n '.1 一5J n n n n I I I · -1.1¾ I 二 (請先閱讀背面之注意事項再填寫本頁) Α7 Β7 五、 發明說明（ 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 導線80。均勻介電層82的材質可以是Si02、TE0S-0xide、 SiN、PSG、BPSG、FSG、HSQ、MSQ、SILK、SiOxCyHz 等材料所構成，其中FSG或數種材質之複合層則為較佳的 選擇。若導體80的高度約為500-nm，那麼介電層82的厚 度則約為1 OOnm。參閱第14圖，沉積一薄而均勻之導電 層84於介電層82之上。均勻導電層84的材質可以是耐 火金屬氮化物、耐火金屬矽化物，或其組合物。合適的耐 火金屬包含 Ti、Zr、Hf、Vd、Nb、Ta、Cr、Mo、與 W。 然而附帶一提的是，耐火材料的材質則不限定於上述之材 料。另外，此均勻導電層84可以是任何低電阻的金屬， 如A卜Cu、AlCu等。參閱第15圖，進行一個或多個反應 離子蝕刻製程以形成導體間隙壁86，其製程則如第一實施 例中第6圖-第9圖所表示。參閱第16圖，沉積形成層間 介電層88。參閱第17圖，利用化學機械研磨製程以曝露 出導線80。接著可於此半導體結構上形成另一層間介電 層，並重複上述的製程而形成金屬内連線。在第Η圖中， 均句介電層82並非一定得予以去除，因此介電層82可留 在導線8 0或内層間介電層的 丨电增的上万0此外，均勻介電層間 隙壁82亦可形成於製作阶罐 机、表邪防遠導體間隙壁86之前，其製程 將於第18圖至第24圖中予以說明。 弟18圖至第24圖為部八士·於 國為邵知疋+導體結構剖面圖，用以 描述本發明。本發明第一會、 貫施例疋材料與步驟可以等同應 用於本實施例。參閲第^ 阔罘18圖，導線80首先形成於層間介 電廣70的上方。參閱篦 弟19圖’沉積形成一薄而均勻之介 第11頁 (請先閱讀背面之注意事項再填寫本頁) *SiOxCyHz and other materials, including FSG or a composite layer of several materials. Page 9 This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 meals __till I IK I Aw ------ II · I I--I --- ^ J Aw- I, (Please read the precautions on the back before filling out this page) 502380 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs See Figure 9 for the feedstock. Anisotropic reactive ion etching is used to form a dielectric spacer wall 60 'to cover the conductor spacer wall 56. Suitable reaction gases include fluorocarbons, such as CF4, c2F6, etc. , Or nitrogen carbide, to form a partition wall by etching. Refer to Figure 10 for deposition to form a thick conductive layer 62. The conductive layer 62 may be a fluorene-based conductor such as Ding Xuxin (5-nm / 4〇-nm / 1-miCrOn), or Ming-based conductor Ti / TiN / A1Cu (5-nmMO-nmn-micron), or other suitable conductors. Refer to Figure " for a chemical mechanical polishing process to form the inner conductor 6 cores Using a reactive ion etching process, it can be used to expose a part of the conductor gap wall 56 at the top of the trench. Therefore, controlled grinding The depth will not only be exposed to the dielectric material 50 exposed between the wires 64, but also to expose enough spacers 60 to isolate the wires 64 from the wires 56. Then another interlayer dielectric layer can be formed on this semiconductor structure ' The above-mentioned processes are repeated to form metal interconnects. Figures 12 to 17 are partial cross-sectional views of the semiconductor structure to describe the second embodiment of the present invention. The materials and steps of the first embodiment of the present invention can be The same applies to the second embodiment. Referring to FIG. 12, a conductive line 80 is formed over the inner interlayer dielectric layer 70, and the forming process includes depositing a metal layer, forming a photoresist layer, etching a metal layer, and stripping the photoresist layer. , Or forming a damascene wire in the dielectric layer, and etching back the dielectric layer, and other conventional techniques. The wire 80 may be any conductor, or any combination of conductors, such as Ti / TiN / AlCu (0 · 5_3 atomic% Cu) (20-nm / 20-nm / l- micron), and its thickness can be controlled between 50-5000nm. In order to facilitate the description of Figures 12-17, the height of the conductor will be set to 500 nm. See page Figure 13: Deposition of a thin and uniform dielectric layer 82 to cover the layer The dielectric layer 70 and the 10th paper size are applicable to the Chinese National Standard (CNS) A4 specification (210x 297mm t) H 1 i H 1 nnnn 1 · nn I nn I n K n '.1-5J nnnn III ·- 1.1¾ I II (Please read the precautions on the back before filling out this page) Α7 Β7 V. Description of the invention (conductor 80 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs). The material of the uniform dielectric layer 82 can be made of Si02, TE0S-0xide, SiN, PSG, BPSG, FSG, HSQ, MSQ, SILK, SiOxCyHz and other materials, among which FSG or a composite layer of several materials is a better choice . If the height of the conductor 80 is about 500-nm, the thickness of the dielectric layer 82 is about 100 nm. Referring to Fig. 14, a thin and uniform conductive layer 84 is deposited on the dielectric layer 82. The material of the uniform conductive layer 84 may be refractory metal nitride, refractory metal silicide, or a combination thereof. Suitable refractory metals include Ti, Zr, Hf, Vd, Nb, Ta, Cr, Mo, and W. Incidentally, the material of the refractory is not limited to the above-mentioned materials. In addition, the uniform conductive layer 84 may be any metal having a low resistance, such as Cu, AlCu, and the like. Referring to FIG. 15, one or more reactive ion etching processes are performed to form the conductive spacer 86, and the process is as shown in FIGS. 6 to 9 in the first embodiment. Referring to Fig. 16, an interlayer dielectric layer 88 is deposited. Referring to Fig. 17, a chemical mechanical polishing process is used to expose the wires 80. Then, another interlayer dielectric layer can be formed on the semiconductor structure, and the above-mentioned process is repeated to form a metal interconnect. In the second figure, the uniform dielectric layer 82 does not have to be removed, so the dielectric layer 82 can remain on the wires 80 or the tens of thousands of digits of the interlayer dielectric layer. In addition, the uniform dielectric layer gap The wall 82 can also be formed before the step tank machine and the surface-proof remote conductor gap wall 86, and the manufacturing process will be described in FIGS. 18 to 24. Figures 18 through 24 are cross-sections of Bu Baishi · Yu Guowei Shao Zhizheng + Conductor Structure to describe the present invention. The materials and steps of the first meeting, the embodiments of the present invention can be applied to this embodiment. Referring to FIG. 18, the conductive line 80 is first formed over the interlayer dielectric 70. Refer to Figure 19 of the younger brother 'for the deposition of a thin and uniform medium. Page 11 (Please read the precautions on the back before filling this page) *

訂·丨 n «1 ·1 n H 11 I H- ϋ· i··^ n el I ϋ fi t— ϋ n If n ϋ· n ft—· 1 1- Is— n ϋ I 502380 A7 ____B7 五、發明說明（） 電層82以覆蓋層間介電層7〇以及導線80。參閱第20圖， 進行非等向性反應離子蚀刻以形成介電間隙壁8 3。參閱第 21圖，形成一薄而均勻之導電層84以覆蓋内層間介電層 70、導線80以及介電間隙壁83。參閱第22圖，進行非等 向性反應離子蝕刻以形成導體間隙壁8 6，並覆蓋介電間隙 壁83。參閱第23圖，沉積形成内層間介電層88。參閱第 24圖’進行化學機械研磨製程，以曝露出導線8〇。使用 反應離子#刻製程，則可用以縮減導體間隙壁8 2的高度， 或疋允终導體間隙壁8 2與導線8 0接觸。因此受控制的研 磨深度將不僅及於曝露導線80,更包含曝露出足夠的間隙 壁83以隔離導線80與導體間隙壁86。接著可於此半導f 結構上形成另一層間介電層，並重複上述的製程而形成金 屬内連線。 本發明所提出之較佳實施例僅用於插述本發明之精 神。而上述之說明並非本發明之特定實祐 貝碼例，而在不脫離 本發明之精神下，上述之實施例亦可做等 ’政的替換，至於 本發明之範圍則如後述之申請專利範圍所定 ί — I — — — — --------訂---I I---•線—♦ - (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 格 規 Α4 ls)A N (c 準 標 家 國 一國 中 用 適 度 尺 張 紙 本 第12頁 X 10Order 丨 n «1 · 1 n H 11 I H- ϋ · i ·· ^ n el I ϋ fi t— ϋ n If n ϋ · n ft— · 1 1- Is— n ϋ I 502380 A7 ____B7 5. DESCRIPTION OF THE INVENTION The electrical layer 82 covers the interlayer dielectric layer 70 and the conductive line 80. Referring to FIG. 20, anisotropic reactive ion etching is performed to form a dielectric spacer 83. Referring to FIG. 21, a thin and uniform conductive layer 84 is formed to cover the interlayer dielectric layer 70, the conductive line 80, and the dielectric spacer 83. Referring to Fig. 22, anisotropic reactive ion etching is performed to form a conductor spacer 86 and cover the dielectric spacer 83. Referring to FIG. 23, an inner interlayer dielectric layer 88 is formed. Referring to FIG. 24 ', a chemical mechanical polishing process is performed to expose the wires 80. Using the reactive ion # engraving process, it can be used to reduce the height of the conductor gap wall 82, or allow the final conductor gap wall 82 to contact the wire 80. Therefore, the controlled grinding depth will not only be exposed to the conductive wire 80, but also include a sufficient gap wall 83 to isolate the conductive wire 80 from the conductor gap wall 86. Then, another interlayer dielectric layer can be formed on the semiconductor f structure, and the above-mentioned process is repeated to form a metal interconnect. The preferred embodiment of the present invention is only used to interpolate the spirit of the present invention. The above description is not a specific example of the present invention. Without departing from the spirit of the present invention, the above embodiments can also be replaced by equivalent policies. As for the scope of the present invention, the scope of patent application is described later. Order I — I — — — — -------- Order --- I I --- • line— ♦-(Please read the precautions on the back before filling this page) Employees ’Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Cooperative prints the standard A4 ls) AN (c quasi-standard home country and one country with moderate ruled paper on page 12 X 10

Claims (1)

Translated fromChinese

502380 A8 B8 號專利案守/年7月修正 六 申請專利範圍 修正 1.一種積體電路元件之内連線’該内連線^ 一基板， 一内層間介電層，形成於該基板之上表面· 一受防護内連線’具有形成於該内層間介電層内的 間隙壁，該受防護内連線包含： 一導線，具有間隙壁； 一防護介電層，緊鄰於該導線之間隙壁；以及 一防護導體，緊鄰於該防護介電層。 2·如申請專利範園第1項所述之内連線，其中上述之内層 間介電層包含氧化矽（SiCh)、四乙基矽酸鹽氧化物 (TEOS-Oxide)、氮化碎（SiN)、磷碎玻璃（psg)、硼磷矽 玻璃（BPSG)、含氫矽酸鹽（Hydrogen Silsesquoixane)、 甲基梦酸鹽（Methyl Silsesquoixane)、聚芳基醚 (Polyarylene Ether)、二氧化矽空氣凝膠（silica Aerogel)、或 SiOxCyHz(0<x<l 0，0<y<3，0<z< 10)。 3.如申請專利範園第2項所述之内連線，其中上述之防護 介電層包含氧化矽（Si02)、四乙基矽酸鹽氧化物（TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃（PSG)、硼磷矽玻璃 (BPSG)、含氫硬酸鹽（Hydrogen Silsesquoixane)、甲基 砍酸鹽（Methyl Silsesquoixane)、聚芳基醚（Polyarylene Ether)、二氧化矽空氣凝膠（silica Aerogel)、或 SiOxCyHz(〇<x<i〇 ， 〇<y<3 ， 〇<z<10) 〇 第13頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 請 先 閲 讀 背 面 之 注 意 事 項 I裝 1 訂 經濟部智慧財產局員工消費合作社印製 80 3 2 ο 5 六 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 P8_ 申請專祕目 4如申請專利範圍第3項所述之内連線，其中上述之防護 導體包含耐火金屬、耐火金屬氮化物、耐火金屬矽化 物，或其組合物。 5如申請專利範圍第3項所述之内連線，其中上述之耐火 金屬包含 Ti、Zr、Hf、Vd、Nb、Ta、Cr、Mo、或 W。 6如申請專利範圍第3項所述之内連線，其中上述之防護 導體包含Al、Cu、或AlCu。 7 /種用以於積體電路元件中形成内連線的方法，該方法 至少包含下列步驟： 提供一基板； 沉積一層間介電層於該基板之表面，該層間介電層 具有一上表面； 形成溝渠於該層間介電層之中，該溝渠具有侧壁； 形成導體間隙壁於該溝渠之該侧壁上； 形成介電材質間隙壁於該導體間隙壁上； 沉積一導電層；以及 除去部份之該導電層與該層間介電層，以曝露出該 導體間隙壁與該介電材料間隙壁。 8·如申請專利範園第7項所述之方法，其中上述形成導體 間隙壁之步騾，更包含沉積一均勻導電層之步驟，與非 第14貫 本紙張尺度適用中國國家標準(CNS)A4規格(21〇X297公釐) (請先閲讀背面之注意事項再填寫本頁) 裝· ο 8 3 ί、 ' Ν 經濟部智慧財產局員工消費合作社印製 A8 B8 . C8 -----— D8__— 申請專利範圍 等向性反應離子蚀刻步驟。 9·如申請專利範園第8項所述之方法，其中上述形成介電 材質間隙壁之步驟，更包含沉積一均勻介電層之步驟， 與非等向性反應離子蝕刻步驟。 10·如申請專利範圍第7項所述之方法，其中上述除去部份 之該導電層之步驟，包含化學機械研磨製程。 1 1.如申請專利範圍第7項所述之方法，其中上述之内層間 介電層包含氧化矽（Si〇2)、四乙基矽酸鹽氧化物（TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃（PSG)、硼磷矽玻璃 (BPSG)、含氫珍酸鹽（Hydrogen Silsesquoixane)、甲基 硬酸鹽（Methyl Silsesquoixane)、聚芳基醚（Polyarylene Ether)、二氧化矽空氣凝膠（Silica Aerogel)、或 SiOxCyHz(0<x<l 0，0<y<3，0<ζ<10) 〇 1 2.如申請專利範圍第7項所述之方法，其中上述之介電材 料間隙壁包含氧化矽（Si02)、四乙基矽酸鹽氧化物 (TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃（PSG)、硼磷矽 玻璃（BPSG)、含氫秒酸鹽（Hydrogen Silsesquoixane)、 甲基珍酸鹽（Methyl Silsesquoixane)、聚芳基醚 (Polyarylene Ether)、二氧化梦空氣凝膠（Silica Aerogel)、或 SiOxCyHz(0<x<10，0<y<3，0<z<10)。 第15頁 本紙張尺度適用中國國家標準(CNS)A4規格(21〇Χ 297公爱) :·ί…：…·裝.........訂---------· (請先閱讀背面之注意事項再填寫本頁) 502380 ABCD 六、申請專利範圍 13.如申請專利範園第7項所述之方法，其中上述之導體間 隙壁包含耐火金屬、财火金屬氮化物、耐火金屬梦化 物，或其組合物。 1 4 ·如申請專利範園第1 3項所述之方法，其中上述之耐火 金屬包含 Ti、Zr、Hf、Vd、Nb、Ta ' Cr、M〇、或 w。 l5·如申請專利範園第1;2所述之方法，其中上述之導體間 隙壁包含A卜Cu、或AlCu。 16·—種用以於積體電路元件中形成内連線的方法，該方法 至少包含下列步驟： 提供一基板； 形成導線於該基板的表面，該導線具有上表面與侧 壁； 沉積一介電層’該介電層之-部份於該導線之側壁 上形成侧壁介電層； 形成導體間隙壁於該侧壁介電層上；以及 沉積層間介電層。 17.如申請專利範圍第16所述之方法， ..... 尺匕令—步騾以移 除位於該導線上方以及未受該間 土復基板上方 的該介電層與該導體。 (請先閲讀背面之注意事項再填寫本頁) 裝· -、一：& 經濟部智慧財產局員工消費合作社印製 第16頁Patent No. 502380 A8 B8 / July Amendment 6 Application for Patent Scope Amendment 1. An interconnect of an integrated circuit element 'the interconnect ^ a substrate, an inner interlayer dielectric layer formed on the substrate Surface · A shielded interconnect has a gap wall formed in the interlayer dielectric layer. The shielded interconnect includes: a wire with a gap; a shielded dielectric layer next to the gap of the wire A wall; and a protective conductor next to the protective dielectric layer. 2. The interconnect as described in item 1 of the patent application park, wherein the inner interlayer dielectric layer includes silicon oxide (SiCh), tetraethyl silicate oxide (TEOS-Oxide), and nitride ( SiN), psg, borophosphosilicate glass (BPSG), Hydrogen Silsesquoixane, Methyl Silsesquoixane, Polyarylene Ether, Silicon dioxide Silica Aerogel, or SiOxCyHz (0 < x < l 0,0 < y < 3,0 < z < 10). 3. The interconnect as described in item 2 of the patent application park, wherein the protective dielectric layer includes silicon oxide (Si02), tetraethyl silicate oxide (TEOS-Oxide), and silicon nitride (SiN ), PSG, BPSG, Hydrogen Silsesquoixane, Methyl Silsesquoixane, Polyarylene Ether, Silica Air Gel (silica aerogel), or SiOxCyHz (〇 < x < i〇, 〇 < y < 3, 〇 < z < 10) 〇 page 13 This paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) Please read the precautions on the back I. Order 1 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 80 3 2 ο 5 Six Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 P8_ Application for Special Head 4 The inner wiring as described in item 3 of the scope of the patent application, wherein the above-mentioned protective conductor comprises a refractory metal, a refractory metal nitride, a refractory metal silicide, or a combination thereof. 5 The inner wiring according to item 3 of the scope of patent application, wherein the refractory metal includes Ti, Zr, Hf, Vd, Nb, Ta, Cr, Mo, or W. 6 The inner wiring according to item 3 of the scope of patent application, wherein the above-mentioned protective conductor comprises Al, Cu, or AlCu. 7 / A method for forming interconnects in integrated circuit elements, the method comprising at least the following steps: providing a substrate; depositing an interlayer dielectric layer on the surface of the substrate, the interlayer dielectric layer having an upper surface Forming a trench in the interlayer dielectric layer, the trench having a sidewall; forming a conductor gap on the sidewall of the trench; forming a dielectric material barrier on the conductor gap; depositing a conductive layer; and A portion of the conductive layer and the interlayer dielectric layer are removed to expose the conductor spacer and the dielectric material spacer. 8. The method according to item 7 of the patent application park, wherein the step of forming the conductor gap wall further includes a step of depositing a uniform conductive layer, and the Chinese paper standard (CNS) is applied to the non-14th paper size. A4 specifications (21 × 297 mm) (Please read the precautions on the back before filling out this page) Packing · ο 8 3 ί, 'Ν Printed by A8 B8. C8 ----- — D8 __— Patent application scope Isotropic reactive ion etching step. 9. The method according to item 8 of the patent application park, wherein the step of forming a spacer of a dielectric material further includes a step of depositing a uniform dielectric layer, and a step of anisotropic reactive ion etching. 10. The method according to item 7 of the scope of patent application, wherein the step of removing a part of the conductive layer includes a chemical mechanical polishing process. 1 1. The method according to item 7 of the scope of the patent application, wherein the inner interlayer dielectric layer includes silicon oxide (SiO2), tetraethyl silicate oxide (TEOS-Oxide), silicon nitride ( SiN), Phosphor-Silicon Glass (PSG), Borophospho-Silicon Glass (BPSG), Hydrogen Silsesquoixane, Methyl Silsesquoixane, Polyarylene Ether, Silicon Dioxide Air gel (Silica Aerogel), or SiOxCyHz (0 < x < l 0,0 < y < 3,0 < ζ < 10) 〇1 2. The method according to item 7 of the scope of patent application, wherein the above-mentioned Electrical material spacers include silicon oxide (Si02), tetraethyl silicate oxide (TEOS-Oxide), silicon nitride (SiN), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), hydrogen-containing seconds Hydrogen Silsesquoixane, Methyl Silsesquoixane, Polyarylene Ether, Silica Aerogel, or SiOxCyHz (0 < x < 10,0 < y < 3, 0 < z < 10). Page 15 This paper standard is applicable to China National Standard (CNS) A4 specification (21〇 × 297 public love): · ί…:… ......... Order --------- · (Please read the precautions on the back before filling out this page) 502380 ABCD VI. Application scope of patent 13. The method described in item 7 of the patent application park, where the above-mentioned conductor partition wall contains refractory metal, wealth fire metal nitrogen Compounds, refractory metal dream compounds, or combinations thereof. 14. The method according to item 13 of the patent application park, wherein the refractory metal comprises Ti, Zr, Hf, Vd, Nb, Ta'Cr, Mo, or w. l5. The method described in Patent Application Park No. 1; 2, wherein the above-mentioned conductor gap wall comprises Al, Cu, or AlCu. 16. · A method for forming interconnects in integrated circuit components, the method includes at least the following steps: providing a substrate; forming a wire on the surface of the substrate, the wire having an upper surface and a sidewall; and depositing a dielectric An electrical layer-a portion of the dielectric layer forms a sidewall dielectric layer on a sidewall of the wire; a conductor gap is formed on the sidewall dielectric layer; and an interlayer dielectric layer is deposited. 17. The method as described in claim 16 of the scope of patent application, ..... ruler-steps to remove the dielectric layer and the conductor located above the wire and unsupported by the interlayer substrate. (Please read the precautions on the back before filling out this page.) 装 ·-一 ： Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Page 16502380 A8 B8 C8 D8 六、申請專利範圍 18.如申請專利範園第16所述之方法，其中上述形成導體 間隙壁的步驟，更包含沉積一均勻導電層之步騾，與反 應離子蝕刻步驟。 1 9.如申請專利範圍第1 6項所述之方法，其中上述之層間 介電層包含氧化矽（Si02)、四乙基矽酸鹽氧化物（TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃（PSG)、硼磷矽玻璃 (BPSG)、含氫咬酸鹽（Hydrogen Silsesquoixane)、甲基 珍酸鹽（Methyl Silsesquoixane)、聚芳基醚（p〇lyarylene Ether)、二氧化珍空氣凝膠（Silica Aerogel)、或 SiOxCyHz(0<x<l〇，〇<y<3，〇<ζ<1〇)。 20.如申請專利範圍第19項所述之方法，其中上述之均勻 介電層包含氧化矽（Si02)、四乙基矽酸鹽氧化物（TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃（PSG)、硼磷矽玻璃 (BPSG)、含氫梦酸鹽（Hydrogen Silsesquoixane)、甲基 珍酸鹽（Methyl Silsesquoixane)、聚芳基酸（p〇lyaryiene Ether)、二氧化梦空氣凝膠（Silica Aerogel)、或 SiOxCyHz(0<x<10，〇<y<3，0<z<10)。 2 1 ·如申請專利範圍第1 6項所述之方法，其中上述導體間 隙壁包含耐火金屬、耐火金屬氮化物、耐火金屬碎化 物，或其組合物。 第17頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝· 經濟部智慧財產局員工消費合作社印製502380 A8 B8 C8 D8 6. Scope of Patent Application 18. The method described in the patent application park No. 16, wherein the step of forming a conductor gap wall further includes a step of depositing a uniform conductive layer, and a reaction ion etching step. 19. The method according to item 16 of the scope of patent application, wherein the interlayer dielectric layer includes silicon oxide (Si02), tetraethyl silicate oxide (TEOS-Oxide), and silicon nitride (SiN) , Phospho-Silicon Glass (PSG), Boro-Phospho-Silicon Glass (BPSG), Hydrogen Silsesquoixane, Methyl Silsesquoixane, Polyarylene Ether, Dioxin Silica Aerogel or SiOxCyHz (0 < x < 10, 〇 < y < 3, 〇 < ζ < 1〇). 20. The method according to item 19 of the scope of patent application, wherein the uniform dielectric layer comprises silicon oxide (Si02), tetraethyl silicate oxide (TEOS-Oxide), silicon nitride (SiN), phosphorus Silicate glass (PSG), borophosphosilicate glass (BPSG), Hydrogen Silsesquoixane, Methyl Silsesquoixane, Polyaryene Ether, Dream Air Condensation Silica Aerogel, or SiOxCyHz (0 < x < 10, 0 < y < 3,0 < z < 10). 2 1. The method as described in item 16 of the scope of the patent application, wherein the conductor gap comprises refractory metal, refractory metal nitride, refractory metal fragment, or a combination thereof. Page 17 This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page)申請專利範園 22·如申請專利範園第21項所述之方法，其中上述之耐火 金屬包含 Ti、Zr、Hf、vd、勘、Ta、Cr、％。或 w。 3.一種用以於積體電路元件中形成内連線的方法，該方法 至少包含下列步驟： V丨 提供一基板； 形成導線於該基板的表面，該導線具有上表面與侧 壁； /、 形成一介電材料間隙壁於該導線之侧壁；以及 形成導體間隙壁於該介電材料間隙壁上。 4.如申請專利範園第23項所述之方法，其中上述形成該 介電材料間隙壁之步驟，更包含沉積一均勻介電層之步 驟，與非等向性反應離子蝕刻步騾。 25 ·如申請專利範圍第24項所述之方法，其中上述形成該 介電材料間隙壁之步驟，更包含沉積一均勻導電層之步 驟，與非等向性反應離子蝕刻步騾。 -I «ί I I L----_ 裝丨· (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 步 列 下 含 包 更 法 方 之 述 所 項 3 2 第 圍 A0^ 利 專 請 中 如 驟 積去 沉除 壁 隙 間 體 導 該 線 該 出 露 曝 以。 ，壁 及層隙 以電 ~ t料•， /ο,間材 J 電 電 層 W之ί 層份# κ 8ml 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公楚) 502380 ABCD 六、申請專利範圍 27·如申請專利範園第26項所述之方法，其中上述除去部 份之該導電層與部份之該層間介電層之步騾，包含化學 機械研磨製程。 28·如申請專利範圍第22項所述之方法，其中上述之介電 材料間隙壁包含氧化矽（Si〇2)、四乙基矽酸鹽氧化物 (TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃（PSG)、硼磷矽 玻璃（BPSG)、含氫矽酸鹽（Hydrogen Silsesquoixane)、 甲基矽酸鹽（Methyl Silsesquoixane)、聚芳基醚 (Polyarylene Ether)、二氧化矽空氣凝膠（Silica Aerogel)、或 SiOxCyHz(0<x<l〇，（Xyd，0<z<10)。 29·如申請專利範圍第22項所述之方法，其中上述之導體 間隙壁包含耐火金屬、耐火金屬氮化物、耐火金屬矽化 物，或其組合物。 3 0·如申請專利範圍第29項所述之方法，其中上述之耐火 金屬包含 Ti、Zr、Hf、vd、Nb、Ta、Cr、Mo 或 W。 3 1 ·如申請專利範圍第27所述之方法，其中上述之導體間 隙壁包含Al、Cu或AlCu ° 32·如申請專利範圍第27項所述之方法，其中上述之内層 間介電層包含氧化矽（Si〇2)、四乙基矽酸鹽氧化物 第19頁 本紙張尺度賴中關_WNS)A4規格(21GX 297公變) (請先閲讀背面之注意事項再填寫本頁) 裝. -訂· 經濟部智慧財產局員工消費合作社印製 502380 A8 B8 C8 D8 六、申請專利範圍 (TEOS-Oxide)、氮化矽（SiN)、磷矽玻璃（PSG)、硼磷矽 玻璃（BPSG)、含氫矽酸鹽（Hydrogen Silsesquoixane)、 甲基梦酸鹽（Methyl Silsesquoixane)、聚芳基醚 (Polyarylene Ether)、二氧化矽空氣凝膠（Silica Aerogel)、或 SiOxCyHz(0<x<10，0<y<3，0<z<10)。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第20頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)Patent application park 22. The method according to item 21 of the patent application park, wherein the above refractory metals include Ti, Zr, Hf, vd, Kan, Ta, Cr, and%. Or w. 3. A method for forming interconnects in integrated circuit components, the method comprising at least the following steps: providing a substrate; forming a wire on a surface of the substrate, the wire having an upper surface and a side wall; Forming a dielectric material spacer on the side wall of the wire; and forming a conductor spacer on the dielectric material spacer. 4. The method according to item 23 of the patent application park, wherein the step of forming the dielectric material spacer further includes a step of depositing a uniform dielectric layer and an anisotropic reactive ion etching step. 25. The method according to item 24 of the scope of patent application, wherein the step of forming the spacer of the dielectric material further includes a step of depositing a uniform conductive layer and an anisotropic reactive ion etching step. -I «ί II L ----_ 装 丨 · (Please read the precautions on the back before filling out this page) Printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, including the items described in the French 3 2nd round A0 ^ Lee Zhuan asked to accumulate and remove the interstitial body to guide the line to expose. The wall and the interstitial space are made of electricity ~, / ο, interlayer material J Electric layer W of the layer # κ 8ml This paper size is applicable to China National Standard (CNS) A4 specification (210x297 Gongchu) 502380 ABCD VI. Application Patent Scope 27. The method described in item 26 of the patent application park, wherein the steps of removing a part of the conductive layer and a part of the interlayer dielectric layer include a chemical mechanical polishing process. 28. The method according to item 22 of the scope of patent application, wherein the above-mentioned dielectric material barrier comprises silicon oxide (SiO2), tetraethyl silicate oxide (TEOS-Oxide), silicon nitride (SiN ), Phosphor-Silicon Glass (PSG), Borophospho-Silicon Glass (BPSG), Hydrogen Silsesquoixane, Methyl Silsesquoixane, Polyarylene Ether, Silica Air Gel (Silica Aerogel), or SiOxCyHz (0 < x < 10, (Xyd, < z < 10). 29. The method according to item 22 of the scope of patent application, wherein the above-mentioned conductor gap comprises a refractory metal , Refractory metal nitride, refractory metal silicide, or a combination thereof. 30. The method according to item 29 of the scope of patent application, wherein the above-mentioned refractory metal includes Ti, Zr, Hf, vd, Nb, Ta, Cr , Mo or W. 3 1 · The method as described in the scope of the patent application No. 27, wherein the above-mentioned conductor gap comprises Al, Cu or AlCu ° 32 · The method as described in the scope of the patent application No. 27, wherein Interlayer dielectric layer contains silicon oxide (SiO2), tetraethyl silicate Chemicals page 19 This paper is based on Zhongguanguan_WNS) A4 specification (21GX 297 public variable) (Please read the notes on the back before filling out this page).-Order · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 502380 A8 B8 C8 D8 VI. Patent application scope (TEOS-Oxide), silicon nitride (SiN), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), hydrogen silicate (Hydrogen Silsesquoixane), methyl dream Methyl Silsesquoixane, Polyarylene Ether, Silica Aerogel, or SiOxCyHz (0 < x < 10,0 < y < 3,0 < z < 10). (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Page 20 This paper size applies to China National Standard (CNS) A4 (210X297 mm)