488041 五、發明說明（1) 【發明領域】 本發明係有關於一種在覆晶與電路基板之結合空隙填 充方法〔underfilling method for the gap between f 1 ip-chip and circuit board〕，特別係有關於一種覆 曰曰封裝構造之底墊材填充過程〔underfilling method f〇r flip-chip package 〕 〇 【先前技術】 在半導體晶片與基板之電性連接領域中，「覆晶結 合」〔flip-chip mounting〕技術係先進於打線技術 〔wire bonding〕，其係在半導體晶片之一表面〔焊墊〕 形成複數個導電性凸塊〔bump〕，再將晶片反轉結合至一 基板，如BGA基板或印刷電路基板，一次完成晶片與基板 之電性連接’不但具有更快之處理過程，更可作為高密度 電子元件之結合。 然而叉:制於半導體晶片與基板兩者之間熱膨脹係數之 不匹配〔mi smatch〕，在晶片運轉過程，位於晶片與基板 之間的凸塊承受極大應力，導致凸塊之熱疲勞〔thermal f a t i gue〕及電性連接失敗，因此，在晶片與基板之間之 空隙〔gap〕填充一種絕緣熱固性底墊材〔underf丨n material〕’如液態環氧化合物，可減少凸塊承受之應力 而改進半導體裝置之使用壽命。 關於底塾材填充於在晶片與基板間空隙之方法，目前 已有多種習用之方法，其中一種為美國發明專利案第 6, 0 66, 5 0 9號「凸塊化晶片之底墊填充方法」〔託讣“488041 V. Description of the invention (1) [Field of the invention] The present invention relates to an underfilling method for the gap between f 1 ip-chip and circuit board. An underfilling method of a packaging structure [underfilling method f〇r flip-chip package] 〇 [prior art] In the field of electrical connection between a semiconductor wafer and a substrate, "flip-chip mounting" [flip-chip mounting] ] Technology is advanced than wire bonding, which forms a plurality of conductive bumps on one surface of a semiconductor wafer [pad], and then inversely combines the wafer to a substrate, such as a BGA substrate or printing The circuit substrate can complete the electrical connection between the wafer and the substrate at one time, which not only has a faster processing process, but also can be used as a combination of high-density electronic components. Fork: Mismatch between the thermal expansion coefficient between the semiconductor wafer and the substrate. During the operation of the wafer, the bumps between the wafer and the substrate are subjected to extreme stress, resulting in thermal fatigue of the bumps. gue] and electrical connection failure, so the gap [gap] between the chip and the substrate is filled with an insulating thermosetting underlay material [underf 丨 n material] 'such as a liquid epoxy compound, which can reduce the stress on the bumps and improve Lifetime of semiconductor devices. Regarding the method for filling the base material into the space between the wafer and the substrate, there have been many conventional methods, one of which is US Pat. No. 6, 0 66, 5 0 9 "Bottom pad filling method for bumped wafers" [Thompson "
第5頁 488041 五、發明說明（2) ----- and apparatus for underfill 〇f bumped or raise d i e〕，如第1圖所示，其係將該利用凸塊丨3結合晶片丨2與 電路基板11之組合構造放置於一傾斜面，在晶片丨2與電路 基板11間之空隙上邊緣處提供一注膠嘴1 5，由注膠嘴1 $注 射一底塾材14，因毛細現象與地心引力之作用，使底墊材 1 4填充於在晶片1 2與電路基板丨丨間之空隙，但其填充時間 亦相當長，不適於大量生產。 曰 另 種底塾材之填充方法係揭不於美國發明專利荦第 6, 081，997號「使用封膠射出法之積體電路封裝方法」Page 5 488041 V. Description of the invention (2)-and and apparatus for underfill 〇f bumped or raise die], as shown in Figure 1, it is the use of the bump 丨 3 combined with the chip 丨 2 and the circuit The combined structure of the substrate 11 is placed on an inclined surface, and a glue injection nozzle 15 is provided at the upper edge of the gap between the wafer 2 and the circuit substrate 11. The glue injection nozzle 1 is used to inject a base material 14. Because of the capillary phenomenon and The effect of gravity causes the bottom mat material 14 to fill the gap between the wafer 12 and the circuit substrate, but its filling time is also quite long, which is not suitable for mass production. Said another filling method of the bottom material is not disclosed in U.S. Invention Patent No. 6, 081,997 "Integrated Circuit Packaging Method Using Sealant Injection Method"
Csystem and method for packaging an integrated circuit using encapsulant injection 〕，如第2 圖所 示，一晶片2 2係以複數個凸塊2 3結合至一具有開口 2 11之 電路基板21，並將該晶片22與電路基板21之組合構造置入 於一個由上模具26與下模具25所構成之模穴内，其中下模 具25係具有一注膠孔251，其中該注膠孔251係對準於電路 基板21之開口 211，且由上模具26與下模具25之結合邊緣 形成複數個逃料通槽261，當底墊材24由注膠孔251射出， 經由該開口 2 11可填充於在晶片2 2與電路基板2 1間之空 隙’以達到快速填充之目的，但由於必須在電路基板2丨之 中心形成一足夠供底墊材2 4流動之開口 2 11，使得景{響到 在晶片2 2上之凸塊2 3配置，無法作為高密度端點之晶片結 合’局限了可結合晶片之種類以及變更晶片之凸塊〔焊 塾〕分佈，此外，在由下往上射出底墊物24之過程，.亦對 晶片2 2形成一推離開電路基板2 1之力量，故在上模具2 6與Csystem and method for packaging an integrated circuit using encapsulant injection], as shown in Figure 2, a chip 2 2 is bonded to a circuit substrate 21 having an opening 2 11 by a plurality of bumps 2 3, and the chip 22 and The combined structure of the circuit substrate 21 is placed in a cavity formed by an upper mold 26 and a lower mold 25. The lower mold 25 has a glue injection hole 251, and the glue injection hole 251 is aligned with the circuit substrate 21. The opening 211 is formed with a plurality of material escape slots 261 by the combined edges of the upper mold 26 and the lower mold 25. When the bottom mat material 24 is ejected from the injection hole 251, the wafer 2 2 and the circuit can be filled through the opening 2 11 The gap between the substrates 21 is used for rapid filling, but since an opening 2 11 sufficient for the base mat 2 4 to flow must be formed in the center of the circuit substrate 2 丨, the scene {sounds out on the wafer 2 2 The configuration of the bumps 2 and 3 cannot be used as a high-density end-point wafer bonding. This limits the types of wafers that can be combined and changes the distribution of the bumps (soldering pads) of the wafers. In addition, the process of shooting the substrate 24 from bottom to top, .Also on wafer 2 2 Form a force to push away from the circuit board 21, so the upper mold 2 6 and
488041 五、發明說明（3) 下模具25之模六高度必須精準地匹配於該晶片22與電路基 ，21之組合構造之厚度，否則將導致凸塊23對電路基板？！ 或:曰曰：22之分離，但實際上，不同之晶片22與電路基板21 之，、且δ構造均要求一致之結合厚度是相當困難。 【發明目的及概要】 f發明之主要目的在於提供一種在覆晶與電路基板之 二5 ς隙填充方法，其中作為與晶片結合之電路基板.具有 〆上^面、下表面及複數個導通孔，利用部份之導通孔 2形成貫穿上表面與下表面之通氣孔，使一底墊材受吸力 k入至該晶片與電路基板之間之空隙並阻塞上述之導通 孔’達到快速填充底墊材之功效。 曰ΪΪ明：次一目的在於提供一種覆晶封裝結構，其中-=片=以覆晶結合至一電路基板，該電路基板具有一上表 ΐ二了I表面及複數個導通孔，利用部份之導通孔係形成 貝牙，面與下表面之通氣孔，以供底墊材阻塞或填充。 依t發明之在覆晶肖㈣基板之結合空 方法， 其至少包含有： = :覆晶型態連接至一電路基板之上表面，使該 ^ _ 土板之間形成有一空隙，其中該電路基板具有 i二下表面及複數個導通孔，而部份之導通孔係 形成貝牙上表面與下表面之通氣孔；及 $曰基板之上表面提供—底墊材，使該底墊材流至 路基板之間之空隙並阻塞上述之導通孔。 【發明砰細說明】 f、 第7頁 488041 五、發明說明（4) “1 請參閱所附圖式’本發明將列舉以下之實施例說明： 如第3 a至3 c圖所不，其係為本發明之第一具體實施例 之底墊材之填充過程，如第3a圖所示，首先提供一電路基 板3 1，該電路基板3 1係為一印刷電路板或球格陣列基板 〔BGA substrate〕，在本實施例中，該電路基板31係為 一種由FR4〔環氧樹脂玻璃纖維布〕或訂樹脂 jB^ismaleimide Triazine resin，雙順丁烯二酸醯亞胺 二氮井〕混合玻璃纖維布製備之球格陣列基板，該電路基 板31係具有一上表面312、一下表面313及複數個導通孔 311〔via hole〕，習知地該電路基板31在上表面312與下 表面313均具有適當之電路圖案〔circuit pattern〕，例 如在上表面312具有複數個連接墊〔c〇nnecti〇n pad〕 〔，未繪出〕，用以電性連接晶片32,在下表面313另具 有複數個連接墊〔connecti〇n pad〕〔圖未繪出〕，用以 電性連接焊球37，並以導通孔311〔via hole〕電性導接 上表面312與下表面313之連接墊，其中部份之導通孔311 係未被電鑛填滿而形成貫穿上表面312與下表面313之通氣 孔’以供氣體流動。 曰曰曰^ 3 2係為一半導體晶片，如微處理器晶片、記憶體 =或系統單晶片，其材質可為矽或砷化鎵，在晶片3 2之 、面係包含有積體電路及複數個焊墊〔圖未繪出〕，在 、曰曰，上分別形成有一凸塊33〔bump〕，如金材質，藉此， H加2係呈覆晶型態〔f 1 ip —chip conf iguraH011〕以複 凸塊33電性連接電路基板31之上表面312〔連接488041 V. Description of the invention (3) The height of the mold 6 of the lower mold 25 must accurately match the thickness of the combined structure of the wafer 22 and the circuit substrate 21, otherwise the bump 23 will cause the circuit substrate? !! Or: Say: Separation of 22, but in fact, it is quite difficult to combine the different thicknesses of different wafers 22 and circuit substrates 21 with a δ structure. [Objective and Summary of the Invention] The main object of the invention is to provide a method for filling a gap between a flip chip and a circuit substrate, which is a circuit substrate combined with a wafer. It has a top surface, a bottom surface, and a plurality of via holes. By using a part of the through hole 2 to form a vent hole penetrating the upper surface and the lower surface, a bottom mat material is sucked into the gap between the chip and the circuit substrate and blocks the above-mentioned via hole to achieve rapid filling of the bottom mat. Effect of wood. Yue Ming: The purpose of the next is to provide a flip-chip package structure, in which-= chip = is bonded to a circuit substrate with a flip-chip, the circuit substrate has an I surface and a plurality of vias on the surface, using parts The through-holes form vent holes on the front and bottom surfaces for the bottom mat to block or fill. The method for bonding air on a flip chip substrate according to the invention t includes at least: =: the flip chip type is connected to the upper surface of a circuit substrate, so that a gap is formed between the ^ _ soil plates, wherein the circuit The substrate has two lower surfaces and a plurality of through holes, and some of the through holes form ventilation holes on the upper and lower surfaces of the tooth; and the upper surface of the substrate provides a bottom mat material to make the bottom mat material flow. To the gap between the circuit substrates and blocking the aforementioned vias. [Detailed description of the invention] f. Page 7 488041 V. Description of the invention (4) "1 Please refer to the attached drawings' The present invention will list the following embodiments: As shown in Figures 3a to 3c, It is the filling process of the base material of the first embodiment of the present invention. As shown in FIG. 3a, a circuit substrate 31 is first provided, and the circuit substrate 31 is a printed circuit board or a ball grid array substrate. BGA substrate]. In this embodiment, the circuit substrate 31 is a mixture of FR4 [epoxy resin fiberglass cloth] or jB ^ ismaleimide Triazine resin. A ball grid array substrate made of glass fiber cloth. The circuit substrate 31 has an upper surface 312, a lower surface 313, and a plurality of via holes 311. The circuit substrate 31 is conventionally provided on the upper surface 312 and the lower surface 313. Each has a suitable circuit pattern. For example, it has a plurality of connection pads [c0nnecti〇n pad] [, not shown] on the upper surface 312, and is used to electrically connect the chip 32, and has a plurality of additional numbers on the lower surface 313. Connection pads (connecti〇n pad] [not shown in the figure], for electrically connecting the solder ball 37, and electrically connecting the connecting pads of the upper surface 312 and the lower surface 313 with a via hole 311 [via hole], part of the via holes 311 are The gas holes are formed through the upper surface 312 and the lower surface 313 without being filled with electricity ore for gas flow. ^ 3 2 is a semiconductor chip, such as a microprocessor chip, a memory chip, or a system single chip Its material can be silicon or gallium arsenide. On the surface of the wafer 32, the integrated circuit and a plurality of solder pads (not shown in the figure) are formed, and a bump 33 (bump) is formed on the surface and the surface. ], Such as gold, by this, H plus 2 series is in a flip-chip form [f 1 ip — chip conf iguraH011] is electrically connected to the upper surface 312 of the circuit substrate 31 with the complex bump 33 [connection
第8頁 五、發明說明（5) 、士火、烤〔CUring〕或回焊〔reflowing〕之結合方 =並由複數個凸塊33在晶片32與電路基板31之間形成一 一妹、關於晶片3 2與電路基板3 1之電性連接之另 曰方法為凸塊33係預先形成於電路基板31後，再結合 3曰1曰之焊料該f Ϊ33係提供作為電性連接晶片32與電路基板 谇枓，其材質可為金〔Gold〕、銀〔Silver〕、銦 二ndlum〕、錫鉛〔tin lead〕或其他合金，甚至是導電 十之聚合物〔P〇lymeric〕或環氧化合物〔ep〇xy〕。 盥一 Ϊ ΐ Ϊ/曰片32與電路基板31之組合構造以-上模具％ 7 5夾合之，由上模具36與下模具35形成一模穴 於？片==〕/、以容置晶片32，而在上模具36在對應 ； 方形成一注膠孔361，以供底墊材34導入， =，具35在對應於晶片32之下方形成—抽氣通道， 通這351係連接至一可抽真空裝置〔圖未繪出〕， 例中，係先經由抽氣通道351將模穴之空氣抽離 Π ίί:之後由注膠孔361在晶片32上方導入底墊材 之* 5 ^快速填滿模穴並流入晶片32與電路基板31間 ::二’取/Λ塞至〔或部份填充〕t路基板31之通氣導 ίί化ί 塾材34填充至電路基板31之通氣導通 底墊材34料—種環氧物〔e卿y〕或丙烯 酉^树月曰〔aCryllc resin〕或其可内含少量惰性填充劑 殖1 l!ller material〕，如二氧化石夕等填充材，在 =過程中，底墊材34之黏度、晶片32與電路基板31間之 二隙大小、電路基板3丨之通氣導通孔311尺寸及抽氣降壓 488041 五、發明說明（6) 之程度應列入考慮，較佳地通氣導通孔3丨丨尺寸係可供氣 體流動而不利於底墊材3 4之通過，而形成近似過濾網之現 象’因此’藉由上述之操作，底墊材3 4可快速地填滿在晶 片32與電路基板31間之空隙並密封該複數個凸塊33。 之後’待底墊材34固化後，如第3b圖所示，移開上模 具36 ’即可取出此一具有底墊材34之晶片32與電路基板31 之、、且a構^ ’再習知地接植焊球〔s ο 1 d e r b a 1 1〕與切割 〔d i c i ng〕後’得到一如第3 c圖所示之以覆晶結合之球格 陣列〔BGA〕封裝結構〔業界簡稱為覆晶封裝結構 flip-chip package〕，在本實施例中之覆晶封裝結構包 含有一電路基板31、一晶片32及一底墊34，其中該電路基 板31係具有一上表面312、一下表面313及複數個導通孔 311，而部份之導通孔311係形成貫穿上表面312與下表面 3 1 3之通氣孔，而該晶片3 2呈覆晶型態以複數個凸塊3 3電 性連接至該電路基板31之上表面312，並使在該晶片32與 電路基板31之間形成有一空隙，該底墊材34係填充於該空 隙並阻塞上述通氣之導通孔3 11，較佳地該底墊材3 4係填 充於上述通氣之導通孔311以及密封該晶片32，並在該電 路基板31之下表面313形成有複數個焊球37，使該覆晶封 裝結構具有球格陣列〔B a 1 1 G r i d A r r a y〕型態，或者是 在該電路基板31之下表面313僅有複數個連接墊而不具有 焊球3 7，而使該覆晶封裝結構成為一平面陣列封裝結構 〔Land Grid Array package 〕。 如第4 a至4 c圖所示，其係為本發明之第二具體實施例5. Description of the invention (5), the combination of fire, baking (CUring) or reflowing = and a plurality of bumps 33 form a sister between the wafer 32 and the circuit substrate 31, about Another method for the electrical connection of the chip 32 and the circuit substrate 31 is that the bump 33 is formed in advance on the circuit substrate 31, and then the solder of the 3 and 1 is combined. The fΪ33 is provided as an electrical connection between the chip 32 and the circuit. Substrate 谇 枓, its material can be gold [Gold], silver [Silver], indium ndlum], tin lead [tin lead] or other alloys, or even conductive polymer [Polymeric] or epoxy compounds [ ep〇xy].一一 ΐ ΐ 曰 / The combination structure of the film 32 and the circuit substrate 31 is sandwiched with -upper mold% 75, and the upper mold 36 and the lower mold 35 form a cavity. Piece ==] /, to accommodate the wafer 32, and the upper mold 36 is corresponding; a glue injection hole 361 is formed on the side for the introduction of the bottom pad 34, =, a tool 35 is formed below the corresponding wafer 32—drawing The air channel 351 is connected to a evacuable device (not shown in the figure). In the example, the air in the cavity is evacuated through the air extraction channel 351. Afterwards, the injection hole 361 is used in the wafer 32. * 5 ^ introduced into the bottom cushion material at the top quickly fills the cavity and flows between the wafer 32 and the circuit substrate 31 :: two 'take / Λ plug to [or partially filled] t-way substrate 31 ventilation guide 34 Air-conducting bottom pad material filled to the circuit substrate 31 34 material—an epoxy compound [eqingy] or acrylic resin [aCryllc resin] or a small amount of inert filler may be contained therein 1 l! Ller material ], Such as stone dioxide and other filling materials, in the process, the viscosity of the bottom pad 34, the size of the two gaps between the wafer 32 and the circuit substrate 31, the size of the ventilation hole 311 of the circuit substrate 3, and the pressure reduction 488041 V. The degree of invention description (6) should be taken into consideration. It is preferable that the size of the vent hole 3 丨 is for gas flow. It is beneficial for the passage of the bottom mat 34 to form a phenomenon similar to a filter screen. Therefore, by the above operation, the bottom mat 34 can quickly fill the gap between the wafer 32 and the circuit substrate 31 and seal the plurality Convex block 33. After 'after the underlay material 34 is cured, as shown in FIG. 3b, remove the upper mold 36' to take out this wafer 32 with the underlay material 34 and the circuit substrate 31, and a structure ^ ' After the implanted solder ball [s ο 1 derba 1 1] and cutting (dici ng) are obtained, a ball grid array (BGA) package structure combined with flip-chips as shown in Figure 3c is obtained. Flip-chip package], the flip-chip package structure in this embodiment includes a circuit substrate 31, a wafer 32, and a bottom pad 34, wherein the circuit substrate 31 has an upper surface 312, a lower surface 313, and A plurality of via holes 311, and a part of the via holes 311 are formed as air holes penetrating the upper surface 312 and the lower surface 3 1 3, and the wafer 32 is in a flip-chip type and is electrically connected to a plurality of bumps 3 3 The circuit substrate 31 has an upper surface 312 and a gap is formed between the wafer 32 and the circuit substrate 31. The bottom pad material 34 is filled in the gap and blocks the above-mentioned venting through-holes 31, preferably the bottom. The cushion material 3 4 is filled in the aforesaid ventilation through hole 311 and the wafer 32 is sealed, and A plurality of solder balls 37 are formed on the lower surface 313 of the circuit substrate 31, so that the flip-chip package structure has a ball grid array [B a 1 1 G rid Array] type, or is on the lower surface 313 of the circuit substrate 31 There are only a plurality of connection pads without solder balls 37, so that the flip-chip package structure becomes a planar array package structure [Land Grid Array package]. As shown in Figures 4a to 4c, this is a second specific embodiment of the present invention
第10頁 488041Page 10 488041
之底墊材之填充過程，如第4 、， 板41，該電路基板41係為一種二=，百先提供一電路基 電路基板31係具有一上表面4„材之球格陣列基板’該 通孔4U〔via hole〕，其中立丄—下表面413及複數個導 填滿而形成貫穿上表面41 2蛊；：H通孔411係未被電鍍 體流動。 ”下表面413之通氣孔，以供氣 晶片4 2係為一微處理器 片’在晶片42之下表面係包 〔圖未繪出〕，在焊墊上分 片4 2係以覆晶型態電性連接 由該複數個凸塊43在晶片42 〔gap〕 〇 曰曰片、§己憶體晶片或系統單晶 含有積體電路及複數個焊墊 別形成有一凸塊43，藉此，晶 電路基板41之上表面412，並 與電路基板4 1之間形成^ 空隙 將上述晶片42與電路基板41之組合構造以一上模具“ 與一下模具45夾合之，由上模具46與下模具45形成一^ 穴，以容置晶片42，其中上模具46係緊接晶片42之上表 面，並在上模具4 6對應於晶片3 2之邊緣形成複數個注膠孔 461，以供底墊材44導入，另外，下模具45在對應於電路 基板41之下方形成一抽氣通道451，且具有複數個支撐柱 452，以支撐該陶瓷電路基板41，該抽氣通道35ι係連接至 一抽氣裝置〔圖未繪出〕，在本實施例中，係由注膠孔 461在晶片42上方導入底塾材44，同時經由抽氣通道451將 模穴内之空氣抽吸而形成一流動通道，底塾材44受吸力、 地心引力及毛細現象能夠快速填滿模穴並流入晶片4 2與電 路基板4 1間之空隙，最後阻塞至電路基板41之通氣導通孔The filling process of the bottom mat material, such as the fourth, the board 41, the circuit substrate 41 is a kind of two =, Baixian provides a circuit-based circuit substrate 31 is a ball grid array substrate with an upper surface 4 Through hole 4U [via hole], where the ridge-lower surface 413 and a plurality of guides are filled to form the upper surface 41 2 蛊;: H through-hole 411 does not flow through the electroplated body. "The air hole of the lower surface 413, The gas supply chip 4 2 is used as a microprocessor chip. The surface of the chip 42 is packaged (not shown in the figure), and the chip 4 2 is electrically connected by a flip-chip type on the bonding pad. The block 43 is formed with a bump 43 on the wafer 42 [gap], the chip, or the single crystal containing the integrated circuit and a plurality of pads, whereby the upper surface 412 of the crystal circuit substrate 41, A gap is formed between the circuit board 41 and the circuit board 41, and the combined structure of the above-mentioned wafer 42 and the circuit board 41 is formed with an upper mold "and sandwiched with the lower mold 45, and a cavity is formed by the upper mold 46 and the lower mold 45 to accommodate The wafer 42 is set, wherein the upper mold 46 is close to the upper surface of the wafer 42 and the upper mold 46 corresponds to A plurality of glue injection holes 461 are formed on the edge of the sheet 32 for the bottom cushion material 44 to be introduced. In addition, the lower mold 45 forms a suction channel 451 under the circuit board 41 and has a plurality of support posts 452. The ceramic circuit substrate 41 is supported, and the exhaust channel 35m is connected to an exhaust device (not shown in the figure). In this embodiment, the base material 44 is introduced through the glue injection hole 461 above the wafer 42 while passing through The suction channel 451 sucks the air in the mold cavity to form a flow channel. The bottom rafter 44 can quickly fill the mold cavity by suction, gravity and capillary phenomenon, and flows into the gap between the wafer 42 and the circuit substrate 41. Finally blocked to the vent hole of the circuit substrate 41
第11頁 488041 五、發明說明（8) 411，較佳為底墊材44填充至電路基板41之通氣導通孔 4 11，因此，在填充過程中，底墊材44可快速地填滿在晶 片42與電路基板41間之空隙並密封該複數個凸塊43。 之後，待底墊材44固化後，如第4b圖所示，移開上模 具46，即可取出此一具有底墊材44之晶片42與電路基板41 之組合構造’再習知地接植焊球〔s0 1 der ba 1 1〕與切割 〔dicing〕後，得到一如第4c圖所示之以覆晶結合之球格 陣列〔BGA〕封裝結構〔簡稱為覆晶封裝結構f Up —chip package〕，在本實施例中之覆晶封裝結構包含有一電路 基板41、一晶片42及一底墊44，其中該電路基板41係具有 一上表面412、一下表面413及複數個導通孔411，而部份 之導通孔411係形成貫穿上表面412與下表面413之通氣 孔，而該晶片42呈覆晶型態以複數個凸塊43電性連接至該 電路基板41之上表面412，並使在該晶片42與電路基板4i 之間形成有一空隙，該底墊材4 4係填充於該空隙並阻塞上 述通氣之導通孔411，較佳地該底墊材44係填充於上述通 氟之導通孔411而裸露出晶片42之上表面，並在該電路芙 板4 1之下表面41 3形成有複數個焊球4 7，使該覆晶封裝結 構具有球格陣列〔Ba 1 1 Gr i d Array〕型態。 故本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。- ^Page 11 488041 V. Description of the invention (8) 411, it is preferable that the underlaying material 44 is filled into the vent holes 41 of the circuit substrate 41. Therefore, the underlaying material 44 can be quickly filled in the wafer during the filling process. A gap between 42 and the circuit board 41 seals the plurality of bumps 43. Then, after the underlaying material 44 is cured, as shown in FIG. 4b, the upper mold 46 is removed, and this combined structure of the wafer 42 with the underlaying material 44 and the circuit substrate 41 can be taken out again and then implanted. After the solder ball [s0 1 der ba 1 1] and cutting (dicing), a ball grid array [BGA] package structure [referred to as the flip-chip package structure f Up — chip as shown in FIG. 4c is obtained. package], the flip-chip package structure in this embodiment includes a circuit substrate 41, a wafer 42, and a bottom pad 44, wherein the circuit substrate 41 has an upper surface 412, a lower surface 413, and a plurality of vias 411. A part of the through-hole 411 forms a vent hole penetrating the upper surface 412 and the lower surface 413, and the chip 42 is in a flip-chip type and is electrically connected to the upper surface 412 of the circuit substrate 41 with a plurality of bumps 43, and A gap is formed between the wafer 42 and the circuit substrate 4i, and the bottom mat material 44 is filled in the gap and blocks the above-mentioned venting through hole 411. Preferably, the bottom mat material 44 is filled in the above-mentioned fluorine-containing gas. The through hole 411 exposes the upper surface of the wafer 42 and exposes the circuit. 41 below the surface 413 is formed with a plurality of solder balls 47, so that the chip-ball grid array structure having a [Ba 1 1 Gr i d Array] patterns. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall be protected by the present invention. range. -^
圖式簡單說明 【圖式說明】 第1圖利第6,066,5 0 9 ?虎「凸塊化晶片之底墊填 h 兄万去」之截面示意圖； 、 第2圓ί·:::^6’081’997號「使用封膠射出法之積 面示意圖； 方法，以上模基板之結合空隙填充 之社人姓模具下杈具夾合該覆晶與電路基板 第3b固1 冓造後並抽真空之截面示意圖； “b圖1本發明之在覆晶與電路基板之結合空隙 後移除上模具之截二；意广主底塾及洪烤固化 第3c圖：依本發明之在覆晶與 法，接續第3b圖之步驟路J 填充方 球後切割得到直中之 在移除下杈具及種植焊 圖； 到其中之-覆晶封裝結構之截面示意 第4a圖 依本發明另一在覆晶與電 方法，以上模且及下禮Γ 結合空隙填充 第4b圖 之結合構造後：抽真晶與電路基板 依本發明另一在覆晶與二=z丄 方法，接續第4a圖之步驟=之結合空隙填充 第4c圖 化後移除上模具之截面示意圖〆；i底塾及供烤固 發合空隙填充 焊球後切割得到其中之二:多除下模具及種植 覆日日封裝結構之截面示 488041Brief description of the drawings [Illustration of the drawings] Figure 1 Figure 6,066,5 0 9? Sectional diagram of the tiger "bumped pad under the pad h brother Wanqu"; 2nd circle ί ::: ^ 6 No. '081'997 "A schematic diagram of the build-up surface using the sealant injection method; method, the upper mold substrate combined with the gap filling of the surname of the mold, the lower mold clamps the flip chip and the circuit substrate. Schematic cross-section of vacuum; "b Fig. 1 The second section of the present invention removes the upper mold after the bonding gap between the flip chip and the circuit substrate; the main bottom of the yinguang and the curing of the flood. Figure 3c: the flip chip according to the present invention And method, following step 3b in Figure 3b, filling the square ball and cutting to obtain straight removal of the lower tool and the planting soldering pattern; to it-a schematic cross-section of the flip-chip packaging structure. Figure 4a according to another of the present invention After the flip-chip and electrical method, the above mold and the following structure are combined with the gap filling structure of FIG. 4b: drawing the true crystal and the circuit substrate according to the present invention, the flip-chip and two = z 丄 method, continuing from FIG. 4a Step = Schematic cross-section diagram of removing the upper mold after combining the gap filling in Fig. 4c; i bottom 塾 and CDCC roasted solid obtained by cutting after filling the void of the two balls wherein: the multi-sectional mold, and lowered cultivation day overlying package structure shown 488041
B式簡單說明 意圖。 【圖 號說明】 11 電路基板 12 晶片 13 凸塊 14 底墊材 15 注膠嘴 21 電路基板 211 開口 22 晶片 23 凸塊 24 底墊材 25 下模具 251 注膠孔 26 上模具 261 逃料通槽 31 電路基板 311 導通孔 312 上表面 313 下表面 32 晶片 33 凸塊 34 底墊材 35 下模具 351 抽氣通道 36 上模具 361 注膠孔 37 焊球 41 電路基板 411 導通孔 412 上表面 413 下表面 42 晶片 43 凸塊 44 底墊材 45 下模具 451 抽氣通道 452 支樓柱 46 上模具 461 注膠孔 47 焊球 ；-·Type B simply explains the intention. [Illustration of the drawing number] 11 Circuit board 12 Wafer 13 Bump 14 Bottom pad 15 Adhesive nozzle 21 Circuit board 211 Opening 22 Wafer 23 Bump 24 Bottom pad 25 Lower mold 251 Injection hole 26 Upper mold 261 Escape slot 31 Circuit board 311 Via hole 312 Upper surface 313 Lower surface 32 Wafer 33 Bump 34 Bottom material 35 Lower mold 351 Suction channel 36 Upper mold 361 Fill hole 37 Solder ball 41 Circuit board 411 Via hole 412 Upper surface 413 Lower surface 42 Wafer 43 Bump 44 Bottom underlay 45 Lower mold 451 Exhaust passage 452 Support pillar 46 Upper mold 461 Injection hole 47 Solder ball;-·
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090102581ATW488041B (en) | 2001-02-05 | 2001-02-05 | An underfilling method of bonding gap between flip-chip and circuit board |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090102581ATW488041B (en) | 2001-02-05 | 2001-02-05 | An underfilling method of bonding gap between flip-chip and circuit board |
| Publication Number | Publication Date |
|---|---|
| TW488041Btrue TW488041B (en) | 2002-05-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW090102581ATW488041B (en) | 2001-02-05 | 2001-02-05 | An underfilling method of bonding gap between flip-chip and circuit board |
| Country | Link |
|---|---|
| TW (1) | TW488041B (en) |
| Publication | Publication Date | Title |
|---|---|---|
| US6324069B1 (en) | Chip package with molded underfill | |
| US6495083B2 (en) | Method of underfilling an integrated circuit chip | |
| US8278142B2 (en) | Combined metallic bonding and molding for electronic assemblies including void-reduced underfill | |
| US6048656A (en) | Void-free underfill of surface mounted chips | |
| US6038136A (en) | Chip package with molded underfill | |
| US6207475B1 (en) | Method for dispensing underfill and devices formed | |
| US6599774B2 (en) | Technique for underfilling stacked chips on a cavity MLC module | |
| US7459339B2 (en) | Flip-chip semiconductor device manufacturing method | |
| US20060160274A1 (en) | Methods relating to forming interconnects | |
| US20020173074A1 (en) | Method for underfilling bonding gap between flip-chip and circuit substrate | |
| US7700414B1 (en) | Method of making flip-chip package with underfill | |
| JP2011086705A (en) | Semiconductor device, and method for manufacturing the same | |
| US20100255641A1 (en) | Semiconductor Manufacturing Method | |
| JP2004072009A (en) | Semiconductor device and manufacturing method thereof | |
| US6693239B2 (en) | Overmolded circuit board with underfilled surface-mount component and method therefor | |
| JP3384359B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2003347352A (en) | Method for bonding ic chip by non-conductive adhesive to substrate and assembly formed by the method | |
| JP4569605B2 (en) | Filling method of underfill of semiconductor device | |
| JP2008113045A (en) | Manufacturing method of semiconductor device | |
| JP2010135501A (en) | Method of manufacturing semiconductor device | |
| TW488041B (en) | An underfilling method of bonding gap between flip-chip and circuit board | |
| KR100674501B1 (en) | Semiconductor chip mounting method using flip chip bonding technology | |
| JP3763962B2 (en) | Mounting method of chip parts on printed circuit board | |
| JPH07226420A (en) | Method for manufacturing semiconductor device | |
| JPH1098077A (en) | Method for manufacturing semiconductor device |
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |