473997 A7 _____B7 五、發明說明（/ ) 本發明係關於一種DRAM晶胞配置，即，動態隨機存取式 記憶胞配置。 (請先閱讀背面之注意事項再填寫本頁) 目前幾乎只使用所謂單一電晶體記憶胞作爲DRAM晶胞 (c e 1 1 )配置之記憶胞，其含有一個電晶體和一個電容器。 記憶胞之資訊是以電荷之形式儲存在電容器上。電容器是 與電晶體相連接，以便在經由字元線來控制電晶體時此電 容器之電荷可經由位元線而讀出。 通常是力求產生一種DRAM晶胞配置，其具有很高之封裝 密度。 此種DRAM晶胞配置例如已描述在M. Aoki et al ·，“ Ful ly Self-Aligned 6F2 Cell Technology for Low Cast 1 Gb DRAM ” ,Symposium on VLSI Technology Digest of Technical 經濟部智慧財產局員工消費合作社印製473997 A7 _____B7 V. Description of the Invention (/) The present invention relates to a DRAM cell configuration, that is, a dynamic random access memory cell configuration. (Please read the notes on the back before filling out this page) At present, almost only the so-called single transistor memory cell is used as the memory cell of the DRAM cell (c e 1 1) configuration, which contains a transistor and a capacitor. The memory cell information is stored on the capacitor as a charge. The capacitor is connected to the transistor so that when the transistor is controlled via the word line, the electric charge of the capacitor can be read out via the bit line. It is generally sought to produce a DRAM cell configuration that has a high packing density. Such a DRAM cell configuration has been described, for example, in M. Aoki et al., "Fully Self-Aligned 6F2 Cell Technology for Low Cast 1 Gb DRAM", Symposium on VLSI Technology Digest of Technical system
Papers(1996)，第22頁中。藉由熱氧化作用而在基板中產 生條形之隔離結構，其可界定電晶體之主動區。基板之表 面是以閘極介電質覆蓋。然後產生字元線，其垂直於隔離 結構而延伸且以氮化矽覆蓋。在字元線和隔離結構之間產 生電晶體之源極/汲極區。沈積第一隔離層，其中產生一 些接觸孔，這些接觸孔分別可到達各源極/汲極區中之一 。然後沈積一種同次（1 n s i t u )摻雜之多晶矽，其厚度須使 這些接觸孔未塡滿。沈積第二隔離層，其塡入這些接觸孔 中。沿著一個隔離結構而相隣之每一第三接觸孔須開啓 (〇 p e η )且以另一同次摻雜之多晶矽塡入，以便產生一些接 觸區。第二隔離層，多晶矽之配置於字元線上方之此一部 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 473997 經濟部智慧財產局員工消費合作社印製 A7 — —__B7___ 五、發明說明（2 ) 份以及第一隔離層須去除。接觸孔中之其餘之多晶矽（其中 未產生上述之接觸區）形成此記憶胞之電容器之第一電極 。產生電容器介電質及配置於其上之電容器第二電極而由 第三隔離層所覆蓋。在第三隔離層中產生一些凹口，這些 凹口使接觸區裸露出來。然後產生位元線（其隣接於接觸區 )。每一第三字元線（其配置在二個分別與一個電容器相連 接之源極/汲極區之間）須連接至一種電位，使這些源極/ 汲極區之間不可有電流流動。這些字元線用作隔離區。 在德國專利文件DE440 8 7 64C2中描述一種DRAM晶胞配置 ，其中在基板中設置第一溝渠（其互相平行而延伸）及垂直 於第一溝渠而延伸之第二溝渠。在第二溝渠之下部中配置 一條字元線，此條字元線藉由閘極介電質而與基板相隔離 。字元線外部之第一溝渠中塡入一種絕緣材料。在第一溝 渠和第二溝渠之間在基板中配置電晶體之源極/汲極區， 其隣接於基板之表面。這些源極/汲極區具有一種旋轉式 U之形式且直至第二溝渠之下部區域爲止都是隣接於第二 溝渠之邊緣。這些源極/汲極區（其沿著第一溝渠而相隣） 之每第三個是與一條平行於第一溝渠而延伸之位元線相連 接。其餘之源極/汲極區是以電容器介電質覆蓋，介電質 上方配置一種薄導電層（其到達字元線溝渠之上部區域中 且用作電容器之板面）。電容器介電質同樣配置在字元線溝 渠之上部區域中且使這些源極/汲極區（其不與位元線相 連接且用作電容器電極）可與電容器板面相隔離。這些字元 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） hlL --------訂—^------線 (請先閱讀背面之注意事項再填寫本頁) 473997 經濟部智慧財產局員工消費合作社印製 A7 B7___ 五、發明說明（S) 線（其配置在二個作爲電容器電極用之源極/汲極區之間） 連接至一個固定之電位，使得在這些源極/汲極區之間不 會有電流流動。這些字元線因此用作相隣記憶胞之隔離區 〇 本發明之目的是提供一種dram晶胞配置，其在同樣大之 封裝密度時較先前技藝有更優良之電性。此外，本發明亦 涉及此種DRAM晶胞配置之製造方法。 上述目的是以一種DRAM晶胞配置來達成，其中在基板中 配置第一溝渠（其互相平行而延伸）及第二溝渠（其垂直於 第一S '渠且互相平行而延伸）。第二溝渠劃分成字元線溝渠 (其設有閘極介電質且其中配置一條字元線）及隔離溝渠（ 其中以絕緣材料塡入）。在字元線上方於字元線溝渠中配置 一種隔離用之保護結構，此種保護結構一起與字元線塡入 字元；線溝渠中。字元線溝渠中之一是與另一個字元線溝渠 相隣且與一個隔離溝渠相隣。隔離溝渠中之一是與字元線 溝渠中之二個相隣。第一溝渠在字元線溝渠外部之部份是 以絕緣材料塡入。在基板中配置電晶體之第一源極/汲極 區’其隣接於基板之表面且具有一種均勻之垂直厚度（即 ’垂直於基板表面之厚度），第一源極/汲極區在基板中 之深度較字元線淺且與位元線相連接以及分別隣接於二個 字元線溝渠和二個第一溝渠。在基板中配置電晶體之二源 @ /汲極區’其隣接於基板之表面且具有一種均勻之垂直 厚度’其在基板中之深度較字元線淺且與電容器相連接以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---L------------------訂---^------線^^· (請先閱讀背面之注意事項再填寫本頁) 473997 A7 ----包 —___ 五、發明說明（4 ) 及分別隣接於字元線溝渠中之一，隔離溝渠中之一和二個 第一溝渠。 位兀線垂直於字元線而延伸。 此外，上述目的是藉由一種DRAM晶胞配置之產生方法來 達成，其中在基板中產生第一溝渠（其互相平行而延伸）及 第一溝渠（其垂直於第一溝渠且互相平行而延伸）。一些第 二溝渠（其稱爲字元線溝渠）設有閘極介電質而其餘之第二 溝渠（其稱爲隔離溝渠）中以絕緣材料塡入，其中字元線溝 渠中之一是與另一個字元線溝渠及隔離溝渠中之一相隣， 隔離溝渠中之一是與二個字元線溝渠相隣。在字元線溝渠 中分別產生一條字元線和配置於此字元線上方之隔離用之 保護結構，它們一起塡入相對應之字元線溝渠中。第一溝 渠在字兀線溝渠外部之部份是以絕緣材料塡入。在基板中 須產生電晶體之第一源極/汲極區，使其隣接於其板之表 面’具有均勻之垂直厚度，其在基板中之深度較字元線溝 渠淺且分別隣接於二個字元線溝渠及二個第一溝渠。產生 位兀線且使其與第一源極/汲極區相連接。6在基板中須產 生電晶體之第二源極/汲極區，使其隣接於基板之表面， 具有均勻之垂直厚度，其在基板中之深度較字元線溝渠淺 且分別隣接於字元線溝渠中之一，隔離溝渠中之一以及二 個第一溝渠。產生電容器且使其與第二源極/汲極區相連 接。 此種DRAM晶胞胞置之記憶胞包含一個電晶體及一個與此 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂---^------線在 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 473997 A7 ___________ B7 五、發明說明（f ) 電晶體相連接之電容器。隔離溝渠使這些沿著第一溝渠而 相隣之記憶胞互相隔離。第一溝渠使這些沿著字元線溝渠 而相瞵之記憶胞相隔離。 源極/汲極區之一之垂直厚度可局部性地稍微有一些變 動。此種變動須溯及此源極/汲極產生時未準確地界定之 植入深度或此源極/汲極之摻雜物質在擴散時統計上之偏 差。 電晶體之通道區是U形的。雖然此種DRAM晶胞配置有較 高之封裝密度（即，每個記憶胞之空間需求較小），但由於 字元線溝渠之深度而可使電晶體之通道長度變長，因此可 防止短通道效變。 由於不須使用這些保持在一固定電位之字元線來使相隣 之記憶胞互相隔開，因此可防止此種由這些字元線和相隣 導電性結構（例如，位元線或源極/汲極區）所形成之電容 〇 這樣可使此種DRAM晶胞配置之電性獲得改進，例如可縮 短電晶體之切換時間。利用此種字元線，則這些字元線亦 可分攤各別之接點，這些字元線經由這些接點而保持在一 固定之電位，使此種DRAM晶胞配置之周邊可具有一種特別 低之空間需求。 可以較高之封裝密度產生此種DRAM晶胞配置，這是因爲 電晶體之源極/汲極區可相對於字元線溝渠和第一溝渠而 以自我對準之方式產生且源極/汲極區和位元線（或電容 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^ --------^^------ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 473997 A7 ___ B7 五、發明說明（<) 器）之間的接觸區亦可以較高之對準容許度（t ο 1 e r a n c e )而產生。 在產生電晶體之後可在基板之表面上沈積一種中間氧化 物，其中可開啓一些至源極/汲極區之接觸孔。這些接觸 孔之對準容許度較大，這是因爲各保護結構覆蓋各字元線 ，且中間氧化物可選擇性地對這些保護結構而被蝕刻。字 元線和接觸區之間的短路（其產生於接觸孔中）因此即可 避免。 爲了簡化製程，則直接在接觸孔中產生電容器是有利的 ，這樣即可省略相對應之接觸區。第二源極/汲極區同時 可用作電容器之電極。 本發明之範圍包括：須產生一些位元線，使其隣接於第 一源極/汲極區，因此可省略相對應之接觸區。在此種情 況下須在中間氧化物中對一種用於每一條位元線之溝渠進 行鈾刻且溝渠中塡入一種導電性材料。 若第一溝渠之寬度，第一溝渠之間的距離，第二溝渠之 寬度以及第二溝渠之間的距離具有相同之大小且較佳是等 於以所使用之技術所可製成之最小之結構之大小F時，則 可達到一種特別高之封裝密度。 本發明之範圍包括：在隔離溝渠和與其相隣之字元線溝 渠之間設置一種較大之間距。電容器因此能以較大之電容 來產生，例如，其水平橫切面在此種情況下可變大。亦可 在基板中產生一種凹口，其切割第二源極/汲極區且此凹 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） . .--------------tr----------$· (請先閱讀背面之注意事項再填寫本頁) A7Papers (1996), p. 22. A strip-shaped isolation structure is generated in the substrate by thermal oxidation, which can define the active area of the transistor. The surface of the substrate is covered with a gate dielectric. Word lines are then generated that extend perpendicular to the isolation structure and are covered with silicon nitride. A source / drain region of the transistor is generated between the word line and the isolation structure. A first isolation layer is deposited in which a number of contact holes are created, each of which can reach one of the source / drain regions. Then a polycrystalline silicon doped with the same (1 n s i t u) is deposited to a thickness such that these contact holes are not full. A second isolation layer is deposited, which penetrates into these contact holes. Each adjacent third contact hole along an isolation structure must be opened (0 p e η) and inserted with another polycrystalline silicon doped at the same time in order to create some contact areas. The second isolation layer, the polycrystalline silicon is placed above the character line. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 473997 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 — — __B7___ 5. The description of the invention (2) and the first isolation layer shall be removed. The remaining polycrystalline silicon in the contact hole (where the above-mentioned contact area is not generated) forms the first electrode of the capacitor of the memory cell. A capacitor dielectric is generated and a capacitor second electrode disposed thereon is covered by a third isolation layer. A few notches are created in the third isolation layer, these notches exposing the contact area. A bit line (which is adjacent to the contact area) is then generated. Each third word line (configured between two source / drain regions connected to a capacitor, respectively) must be connected to a potential so that no current can flow between these source / drain regions. These word lines are used as isolation areas. A German DRAM cell configuration is described in German patent document DE440 8 7 64C2, in which a first trench (which extends parallel to each other) and a second trench extending perpendicular to the first trench are provided in a substrate. A word line is arranged in the lower part of the second trench, and the word line is isolated from the substrate by the gate dielectric. An insulating material is inserted into the first trench outside the word line. A source / drain region of the transistor is disposed in the substrate between the first trench and the second trench, and is adjacent to the surface of the substrate. These source / drain regions have a form of a rotating U and are adjacent to the edge of the second trench up to the lower region of the second trench. Each third of these source / drain regions (which are adjacent along the first trench) is connected to a bit line extending parallel to the first trench. The remaining source / drain regions are covered by the capacitor dielectric, and a thin conductive layer (which reaches the upper area of the word line trench and serves as the board surface of the capacitor) is disposed above the dielectric. The capacitor dielectric is also disposed in the area above the word line trenches and allows these source / drain regions (which are not connected to the bit line and function as capacitor electrodes) to be isolated from the capacitor board surface. These characters -4- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) hlL -------- Order-^ ------ line (please read the first Note: Please fill in this page again.) 473997 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7___ V. Description of Invention (S) line (It is configured between two source / drain regions used as capacitor electrodes) Connect to A fixed potential so that no current flows between these source / drain regions. These word lines are therefore used as an isolation region for adjacent memory cells. The object of the present invention is to provide a dram cell configuration which has better electrical properties than previous techniques at the same package density. In addition, the present invention also relates to a method for manufacturing such a DRAM cell configuration. The above object is achieved by a DRAM cell configuration, in which a first trench (which extends parallel to each other) and a second trench (which is perpendicular to the first S ′ channel and extends parallel to each other) are arranged in the substrate. The second trench is divided into a character line trench (which is provided with a gate dielectric and a character line therein) and an isolation trench (in which an insulating material is inserted). An isolation protection structure is arranged in the character line trench above the character line, and this protection structure is inserted into the character together with the character line in the character line trench. One of the character line trenches is adjacent to another character line trench and adjacent to an isolation trench. One of the isolation trenches is adjacent to two of the character line trenches. The portion of the first trench outside the character line trench is penetrated with an insulating material. The first source / drain region of the transistor is disposed in the substrate, which is adjacent to the surface of the substrate and has a uniform vertical thickness (that is, the thickness perpendicular to the surface of the substrate). The first source / drain region is on the substrate. The depth in the middle is shallower than the character line and connected to the bit line and is adjacent to the two character line trenches and the two first trenches, respectively. The two sources of the transistor are arranged in the substrate. 'It is adjacent to the surface of the substrate and has a uniform vertical thickness.' Its depth in the substrate is shallower than the character line and connected to the capacitor. Applicable to this paper scale China National Standard (CNS) A4 Specification (210 X 297 mm) --- L ------------------ Order --- ^ ------ Line ^ ^ · (Please read the notes on the back before filling this page) 473997 A7 ---- Package —___ V. Description of the invention (4) and one of the trenches adjacent to the character line, one and two of the isolation trenches First ditch. The bit line extends perpendicular to the character line. In addition, the above object is achieved by a method for generating a DRAM cell configuration, in which a first trench (which extends parallel to each other) and a first trench (which extends perpendicular to the first trench and extends parallel to each other) are generated in a substrate. . Some second trenches (referred to as character line trenches) are provided with a gate dielectric, while the remaining second trenches (referred to as isolation trenches) are infiltrated with insulating materials. One of the character line trenches is connected with One of the other character line trenches and the isolation trench is adjacent, and one of the isolation trenches is adjacent to the two character line trenches. A character line and an isolation protection structure arranged above the character line are respectively generated in the character line trench, and they are inserted into the corresponding character line trench together. The part of the first trench outside the word line trench is penetrated with an insulating material. The first source / drain region of the transistor must be generated in the substrate so that its surface adjacent to the plate has a uniform vertical thickness, and its depth in the substrate is shallower than the character line trench and adjacent to two characters, respectively. Yuan line trench and two first trenches. A bit line is generated and connected to the first source / drain region. 6 The second source / drain region of the transistor must be generated in the substrate so that it is adjacent to the surface of the substrate and has a uniform vertical thickness. The depth in the substrate is shallower than the character line trench and adjacent to the character line One of the trenches, one of the isolation trenches, and two first trenches. A capacitor is generated and connected to the second source / drain region. The memory cell of this DRAM cell contains a transistor and a Chinese standard (CNS) A4 specification (210 X 297 mm) that is compatible with this paper size (please read the precautions on the back before filling this page) -------- Order --- ^ ------ Online printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 473997 A7 ___________ B7 V. Description of the invention ( f) Capacitors with transistors connected. The isolation trench isolates these adjacent memory cells from each other along the first trench. The first ditch isolates these memory cells that lie next to each other along the character line ditch. The vertical thickness of one of the source / drain regions may vary slightly locally. Such changes must be traced to the implantation depth that was not accurately defined at the time the source / drain was generated or the statistical deviation of the dopant substance at the source / drain during diffusion. The channel region of the transistor is U-shaped. Although this type of DRAM cell is configured with a higher packing density (that is, each memory cell has a smaller space requirement), the channel length of the transistor can be made longer due to the depth of the word line trenches, thus preventing short Channel changes. Since it is not necessary to use the word lines maintained at a fixed potential to separate adjacent memory cells from each other, such word lines and adjacent conductive structures (for example, bit lines or source electrodes) can be prevented. / Drain region). This can improve the electrical properties of this DRAM cell configuration, such as shortening the switching time of the transistor. By using such word lines, these word lines can also share their respective contacts. These word lines are maintained at a fixed potential via these contacts, so that the periphery of this DRAM cell configuration can have a special Low space requirements. This DRAM cell configuration can be produced with a higher packaging density because the source / drain regions of the transistor can be generated in a self-aligned manner with respect to the word line trenches and the first trench and the source / drain regions Polar regions and bit lines (or capacitors) The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ -------- ^^ ------ (Please read the back first Please fill in this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 473997 A7 ___ B7 V. The contact area between the invention description (&) device can also have a higher alignment tolerance (t ο 1 erance). After the transistor is generated, an intermediate oxide can be deposited on the surface of the substrate, and some contact holes to the source / drain regions can be opened. The alignment tolerance of these contact holes is large because each protection structure covers each word line, and the intermediate oxide can selectively etch these protection structures. A short circuit between the word line and the contact area (which is generated in the contact hole) is therefore avoided. In order to simplify the manufacturing process, it is advantageous to create a capacitor directly in the contact hole, so that the corresponding contact area can be omitted. The second source / drain region can also be used as an electrode of a capacitor. The scope of the present invention includes: some bit lines must be generated so as to be adjacent to the first source / drain region, so corresponding contact regions can be omitted. In this case, a trench for each bit line must be etched in the intermediate oxide and a conductive material must be implanted in the trench. If the width of the first ditch, the distance between the first ditch, the width of the second ditch, and the distance between the second ditch are the same size and preferably equal to the smallest structure that can be made using the technology used With a size F, a particularly high packaging density can be achieved. The scope of the present invention includes: providing a larger distance between the isolation trench and the adjacent character line trench. Capacitors can therefore be produced with a larger capacitance, for example, their horizontal cross section can become larger in this case. It is also possible to create a notch in the substrate, which cuts the second source / drain region and the size of this concave paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ..------ -------- tr ---------- $ · (Please read the notes on the back before filling this page) A7
473997 五、發明說明（7 ) 口中可配置一個電容器。 若相隣之各字元線之間的距離特別大，則由於類似上述 之原因此種情況是有利的。位元線可配置在另〜溝渠（其 切割第一源極/汲極區）中。 隔離溝渠和字元線構渠中可以下述方式塡入材料：首先 以絕緣材料塡入第二溝渠中。然後產生一種條形之遮罩， 其條形覆蓋第二溝渠中之每第三個溝渠（即，隔離溝渠） 。藉助於此種遮罩而在未覆蓋之第二溝渠（即，字元線溝 渠）中去除此種裸露之絕緣材料。然後在第二溝渠（其中 該絕緣材料已被去除）中產生閘極介電質及字元線。 本發明之範圍包括：首先產生第一溝渠且其中以絕緣材 料塡入。然後施加一種輔助層且以條形方式將此輔助層結 構化。在此種已結構化之輔助層之各條形（其作爲遮罩用 )之間產生第二溝渠。除了條形之遮罩以外，在由字元線 溝渠中去除此絕緣材料時此輔助層亦可作爲遮罩用。此種 輔助層可防止··字元線溝渠外部之絕緣材料仍保持在第一 溝渠中。由於首先產生第一溝渠，則第一溝渠可較第二溝 渠還深，這樣可防止這些沿著字元線而相隣之源極/汲極 "—-------------訂—-----線· (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 字除 保 和去 各 渠須 和 溝不 線 一 料 元 第材 字 彳緣 生 份絕 產 部之 在 一 上 。 之部 渠 渠底 溝 溝之 二 一) 第 第中 生 在份 產 種部 先 。 此此 首 流下於 可 電況交 是 漏情相 式 的種渠 方 間此溝 一 之在線 另 區元。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 473997 A7 B7 五、發明說明（》） 護結構之後，藉助於其它之條形遮罩（其條形垂直於第二 溝渠而延伸）而選擇性地對該保護結構來對矽進行蝕刻， 以便產生第一溝渠，但由於各保護結構之故’這些第一溝 渠是和一般情況不同的。 基板由半導體材料（例如，矽）所構成。 字元線可由摻雜之多晶矽或其它導電性材料（例如，金屬 或金屬矽化物）所構成。 若上述之中間氧化物是由s i 〇2所構成，則各保護結構是 由氮化矽所構成時對選擇性可蝕刻性而言是有利的。 本發明之實施例以下將依據各圖式來詳述。圖式簡單說 明如下： 第1圖 在產生第一溝渠之後，此基板之府視圖。 第2圖 在產生一種輔助層，第二溝渠和一個遮罩之後， 此基板之橫切面。 第3 a圖 在產生閘極介電質，字元線，各保護結構，電 晶體之源極/汲極區，中間氧化物，接觸區，電容器和位 元線之後第2圖之橫切面。 第3b圖 在第3a圖之各步驟之後第1圖之府視圖，其中 顯示一些接觸區，字元線，第一溝渠和第二溝渠。 這些圖式未依比例繪製。 原始材料是一種含有P -摻雜之矽之基板1 。藉助於由光 阻（未顯示）所構成之第一遮罩而在基板1中產生大約4 0 0 n in 深之第一溝渠G1。第一溝渠G1大約1 50nm寬且相互間之距 -1 0 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .一 --------訂—-----線^^ (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 473997 A7 _ B7 五、發明說明（ί ) 離大約是約1 5 0 n m。第一溝渠G 1中以絕緣材料塡入，其過 程是沈積一種厚度大約90nm之Si〇2且藉由化學_機械式拋 光法而整平直至基板1裸露爲止（參閱第1圖）。 爲了產生一種輔助層Η，須沈積厚度大約5 〇 n m之氮化矽（ 弟2圖）。 藉助於由光阻（未顯示）所構成之第二條形遮罩（其條形 垂直於第一溝渠G 1而延伸）來對氮化矽，s i 〇2和矽進行蝕 刻，以便在第二遮罩之條形之間產生大約4 0 〇 n m深之第二溝 渠G2。第二溝渠G2大約150ιιπι寬且相互間之距離大約150nm 〇 第二溝渠G2中是以絕緣材料塡入，其過程是沈積一種厚 度大約是90nm之S i〇2且以化學機械法拋光直至輔助層η裸 露爲止。 藉助於條形之第三光阻遮罩Ρ(其條形平行於第二溝渠G2 而延伸，大約300nm寬且覆蓋第二溝渠G2之每第三個溝渠） 選擇性地對氮化矽來對S i 02進行蝕刻。在第二溝渠G2 (其是 由第三光阻遮罩P所覆蓋）中保持著絕緣材料。第二溝渠G 2 以下稱爲隔離溝渠。由其餘之第二溝渠G2 (以下稱爲字元線 溝渠）中去除該絕緣材料直至字元線溝渠之底部裸露爲止（ 第2圖）。 去除第三光阻遮罩P。 藉由熱氧化作用而產生厚度大約6nm之閘極介電質GD， 其覆蓋字元線溝渠之邊緣和底部（第3 a圖）。 -1 1 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------.--------------訂----------線 (請先閱讀背面之注意事項再填寫本頁) 473997 A7 B7 五、發明說明) (請先閱讀背面之注意事項再填寫本頁) 爲了在子兀線溝渠中產生字兀線w ，須沈積厚度大約是 3〇nm之多晶砂且其上沈積厚度大約60nm之Wi以及藉由化學 -機械式拋光法而整平直至輔助層Η裸露爲止。然後對WS i 和多晶矽進行回蝕刻，直至字元線W之上部平面位於基板1 之表面F下方大約50nm爲止（第3a圖）。 輔助層Η例如以熱的H3P〇4來去除。 然後沈積厚度大約7 0 n m之氮化矽且藉由化學-機械式拋 光法來整平直至基板1之表面F裸露爲止。這樣可由字元線 W產生一些隔離用之保護結構S，其一起與字元線W塡入字 元線溝渠中（第3 a圖）。 經濟部智慧財產局員工消費合作社印製 藉由以η -摻雜之離子來進行之植入而在第一溝渠G 1和第 二溝渠G 2之間產生電晶體之第一源極/汲極區S / D 1及第二 源極/汲極區S / D 2。源極/汲極區S / D 1，S / D 2大約8 0 n m 深且具有一種均勻之垂直（即，垂直於基板1之表面F)延伸 之厚度。源極/汲極區S/D1，S/D2在基板1中之深度較字 元線溝渠淺，因此亦較字元線W淺，因此在控制電晶體時會 產生一種通道，此種通道以U形方式而延伸。電流因此可在 字元線溝渠之邊緣和底部處流動。二個電晶體分別由二個 相隣之第一溝渠G 1及二個相隣之隔離溝渠所圍繞。各第一 源極/汲極區S / D 1分別配置在二個字元線溝渠之間且分別 作爲各電晶體中之二個之共同之源極/汲極區。 爲了產生中間氧化物Z，須沈積厚度大約lOOOnm之Si02( 第3a圖）。 -1 2 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 473997 ㈣鄉^充 ' --Igfs—s—BSKssamaa i五、發明說明（11) 藉助於一種由光阻（未顯示）所構成之第四遮罩而產生一些 接觸孔，其可使電晶體之源極/汲極區S/D1，S/D2中之一裸 露出來（第3a和3b圖）。於是選擇性地對各保護結構S來對此 中間氧化物Z進行蝕刻。 在這些接觸孔（其使第一源極/汲極S/D1裸露出來）中產生 一些至位元線B之接觸區KB(第3a和3b圖）。在這些接觸孔（其 使第二源極/汲極區S/D2裸露出來）中產生一些至電容器K0 之接觸區KS(第3a和3b圖）。 然後以習知之方式產生電容器K0 (顯示在第3a圖中）及位元 線B (其垂直於字元線W而延伸）。 本實施例可有很多變型，其同樣在本發明之範圍中。因此 這些層，溝渠，結構，接觸區和各區域之大小可依據各別之 需求而調整。同樣情況亦適用於各別材料之選取。 元件符號表 1 基板 B 位元線 F 表面 G1，G2 溝渠 GD 閘極介電質 Η 輔助層 KB，KS 接觸區 KO 電容器 Ρ 遮罩 S 保護結構 S/Dl, S/D2 源極/汲極區 Ζ 中間氧化物 -13 -473997 V. Description of the invention (7) A capacitor may be arranged in the mouth. If the distance between adjacent character lines is particularly large, this is advantageous for reasons similar to those described above. The bit line can be arranged in another trench, which cuts the first source / drain region. Isolation trenches and word line construction trenches can be filled with material in the following way: first into the second trench with insulating material. A stripe mask is then generated that covers each third of the second trenches (ie, isolation trenches). With the help of such a mask, the bare insulating material is removed in an uncovered second trench (ie, a character line trench). Gate dielectric and word lines are then generated in the second trench, where the insulating material has been removed. The scope of the present invention includes: firstly generating a first trench and injecting it with an insulating material therein. An auxiliary layer is then applied and structured in a stripe fashion. A second ditch is created between the bars of this structured auxiliary layer (which serves as a mask). In addition to the strip-shaped mask, the auxiliary layer can also be used as a mask when the insulating material is removed from the character line trench. This auxiliary layer prevents the insulation material outside the character line trench from remaining in the first trench. Since the first trench is generated first, the first trench can be deeper than the second trench, which can prevent these adjacent source / drain electrodes along the word line " -------------- --- Order —----- Line · (Please read the note on the back? Matters before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The raw material section of the Yuanyuan Zizi Yuanyuan Moisturizing Department is on the top. Department of the channel canal bottom canal ditch 2 1) The first middle school student first in the seed production department. In this way, there is a gap between the electric current and the leaky situation, which is another online element. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 473997 A7 B7 V. Description of the invention (") After protecting the structure, use other strips to cover it The cover (the stripe of which extends perpendicular to the second trench) selectively etches the protection structure to etch silicon to produce the first trenches. However, due to the protection structures, these first trenches are different from the general case. of. The substrate is made of a semiconductor material (for example, silicon). Word lines can be composed of doped polycrystalline silicon or other conductive materials (for example, metals or metal silicides). If the above-mentioned intermediate oxide is composed of sio2, it is advantageous for selective etchability when each protective structure is composed of silicon nitride. Embodiments of the present invention will be described in detail below with reference to the drawings. The diagram is briefly explained as follows: Figure 1 View of the base of this substrate after the first trench is created. Figure 2 A cross-section of the substrate after an auxiliary layer, a second trench and a mask are created. Fig. 3a is the cross-section of Fig. 2 after the gate dielectrics, word lines, protective structures, source / drain regions of transistors, intermediate oxides, contact areas, capacitors and bit lines are generated. Figure 3b The view of Figure 1 after the steps in Figure 3a, showing some contact areas, character lines, first trench and second trench. These figures are not drawn to scale. The starting material is a substrate containing P-doped silicon1. A first trench G1 having a depth of about 4 00 n in is generated in the substrate 1 by means of a first mask made of a photoresist (not shown). The first trench G1 is about 1 50nm wide and the distance between each other-1 0-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). --- line ^^ (Please read the note on the back? Matters before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 473997 A7 _ B7 V. Description of the invention (ί) The distance is about 1 50 nm . The first trench G1 is penetrated with an insulating material. The process is to deposit a Si02 with a thickness of about 90 nm and level it by chemical-mechanical polishing until the substrate 1 is exposed (see Fig. 1). In order to generate an auxiliary layer of silicon, silicon nitride with a thickness of about 50 nm must be deposited (Figure 2). The silicon nitride, si 〇2, and silicon are etched by means of a second stripe mask (the stripe extending perpendicular to the first trench G1) composed of a photoresist (not shown) so that A second trench G2 having a depth of about 400 nm is generated between the bars of the mask. The second trench G2 is about 150 μm wide and the distance between each other is about 150 nm. The second trench G2 is penetrated with an insulating material. The process is to deposit a Si02 with a thickness of about 90 nm and polish it by chemical mechanical method until the auxiliary layer η until exposed. By means of a stripe-shaped third photoresist mask P (the stripe extends parallel to the second trench G2, approximately 300 nm wide and covers every third trench of the second trench G2), the silicon nitride is selectively aligned. Si 02 is etched. An insulating material is held in the second trench G2, which is covered by the third photoresist mask P. The second trench G 2 is hereinafter referred to as an isolation trench. The insulating material is removed from the remaining second trenches G2 (hereinafter referred to as a character line trench) until the bottom of the character line trench is exposed (Figure 2). Remove the third photoresist mask P. A gate dielectric GD with a thickness of about 6 nm is generated by thermal oxidation, which covers the edges and bottoms of the word line trenches (Figure 3a). -1 1-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------.-------------- Order ---- ------ line (please read the precautions on the back before filling this page) 473997 A7 B7 V. Description of the invention) (please read the precautions on the back before filling this page) In order to generate words in the trench of Ziwu line The line w must be polycrystalline sand with a thickness of about 30 nm and Wi with a thickness of about 60 nm, and be leveled by chemical-mechanical polishing until the auxiliary layer Η is exposed. Then, WS i and polycrystalline silicon are etched back until the upper plane of the word line W is located about 50 nm below the surface F of the substrate 1 (FIG. 3 a). The auxiliary layer Η is removed, for example, with hot H3P04. Then, silicon nitride having a thickness of about 70 nm is deposited and leveled by chemical-mechanical polishing until the surface F of the substrate 1 is exposed. In this way, some isolation protection structures S can be generated from the character line W, which together with the character line W enter the character line trench (Fig. 3a). The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a first source / drain that generates a transistor between the first trench G 1 and the second trench G 2 by implantation with n-doped ions Region S / D1 and second source / drain region S / D2. The source / drain regions S / D1, S / D2 are approximately 80 nm deep and have a uniform thickness extending perpendicularly (ie, perpendicular to the surface F of the substrate 1). The depth of the source / drain regions S / D1 and S / D2 in the substrate 1 is shallower than the character line trench, and therefore shallower than the character line W. Therefore, a channel is generated when the transistor is controlled. U-shaped extension. Current can therefore flow at the edges and bottom of the wordline trench. The two transistors are respectively surrounded by two adjacent first trenches G1 and two adjacent isolation trenches. Each of the first source / drain regions S / D1 is disposed between two word line trenches and serves as a common source / drain region of two of the transistors. In order to produce the intermediate oxide Z, SiO 2 with a thickness of about 100 nm must be deposited (Fig. 3a). -1 2-This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 473997 ㈣ 乡 ^ 充 '--Igfs—s—BSKssamaa i V. Description of the invention (11) The fourth mask (not shown) constitutes some contact holes, which can expose one of the source / drain regions S / D1, S / D2 of the transistor (Figures 3a and 3b). This intermediate oxide Z is then selectively etched for each protective structure S. In these contact holes, which expose the first source / drain S / D1, some contact areas KB to the bit line B are generated (FIGS. 3a and 3b). In these contact holes, which expose the second source / drain region S / D2, some contact regions KS to the capacitor K0 are generated (FIGS. 3a and 3b). A capacitor K0 (shown in Figure 3a) and a bit line B (which extends perpendicular to the word line W) are then generated in a conventional manner. There are many variations to this embodiment, which are also within the scope of the present invention. Therefore, the size of these layers, trenches, structures, contact areas and areas can be adjusted according to individual needs. The same applies to the selection of individual materials. Component symbol table 1 Substrate B bit line F surface G1, G2 trench GD gate dielectric Η auxiliary layer KB, KS contact area KO capacitor P shield S protection structure S / Dl, S / D2 source / drain area Zn intermediate oxide-13-