455900 經濟部智慧財產局員工消費合作钍印製 A7 B7 五、發明說明（1 ) 本發明係關於場發射裝置（FEDs)應用於使用電子束之 裝置之領域，包括扁平面板顯示裝置' 感測器、高頻振盪 器、超高速裝置、電子顯微鏡及電子束曝光裝置，及其製 法。更特別本發明係關於附有射極之FEDs其經由集成場 效電晶體（FET)可穩定發射電流；FEDs具有高電流密度、 均勻度及滿意的電流效率；及其製法。 發明背景 習知場發射裝置（FED)作為眾所周知的基本配置具有 錐型史賓特（Spindt)結構，揭示於C.A.史賓特等人，應用 物理學期刊’第47期5238頁1976年。但具有此種史賓特結 構之FED有穩定發射流的問題。特別不穩定的發射流結果 導致用於扁平顯示裝置時的重大問題，由於不穩定電流直 接影響顯示圊像品質，扁平顯示裝置提示於日本專利公告 案第H6-14263號。 曰本專利公告案第H7-118259號揭示具有穩定發射的 FED ’使用電阻的負回授效應，係經由串聯連結高電阻電 阻器至射極發射電子。但使用10至1〇〇百萬歐姆之高電阻 電阻器$聯連結於射極降低FED響應且消耗大量電源。除 了插置該高電阻電阻器外’為了解決此種問題例如大於 1000個射極集成而形成一個fed的射極陣列俾藉由多個射 極輸出平均來對抗射極不穩定問題。但射極數目增加造成 複雜度增高且提高FED製造成本。 為了解決此等問題，日本專利公開案第H9-259744號 揭示一種控制電流於射極流動之辦法，係經由黏合一主動 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 -------* 1 Γ 1 If V I --II----· - -------I <請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟郭智慧財產局3工消費合作社^.¾ 五、發明說明（ 元件例如一電晶體至FED的射極。如此使電流於低電源消 耗下穩疋化。此外可免除形成大量射極的需要。但先前技 術使用箪晶矽作為基材，結果導致無法製造大尺寸扁平顯 示元件且成本增高。 晚近曰本專利公開案第H9_129123號；H Gam〇等人 ，應用物理學函件第73期1301頁1998年及Y.H, Song等人 SID 98文摘1 89頁1998年揭示使用玻璃基材替代單晶矽來 允許加大尺寸以及降低成本應用於扁平面板顯示裝置之用 途。此種結構中，射極、場效電晶體（FET)及其篆與電晶 體（TET)係形成於使用非晶矽及多晶矽的玻璃基 第10 (a)及1 0 (b)圖顯示習者包含射極卩車列7及丁 ||卫.2 3之 配置。第10(a)圖為透視圖說明整體FED對應一個像素。第 10(b)圖為射極陣列7之一個射極及！^丁之放大剖面圖。 如第丨0(a)圖所示，大於1000個射極丨〇形成於FED之射 極陣列7用於有一個TFT 23控制的各個像素。由射極陣列 7發射的電流係由一個TFT 23透過一個陰極電極連結至射 極陣列7之角隅控制。 _455900 Consumption cooperation with employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Description of the invention (1) The present invention relates to the field emission devices (FEDs) applied to the field of devices using electron beams, including flat panel display devices' sensors , High-frequency oscillator, ultra-high-speed device, electron microscope and electron beam exposure device, and its manufacturing method. More specifically, the present invention relates to FEDs with an emitter that can stably emit current through an integrated field effect transistor (FET); FEDs have high current density, uniformity, and satisfactory current efficiency; and a method for manufacturing the same. BACKGROUND OF THE INVENTION The conventional field emission device (FED), as a well-known basic configuration, has a cone-shaped Spindt structure, which is disclosed in C.A. Spint et al., Journal of Applied Physics, 47, 5238, 1976. However, the FED with this kind of Spindt structure has a problem of stable emission stream. As a result of the particularly unstable emission current, it causes a major problem when used in a flat display device. Since the unstable current directly affects the display artifact quality, the flat display device is disclosed in Japanese Patent Publication No. H6-14263. Japanese Patent Publication No. H7-118259 discloses that the FED with stable emission uses the negative feedback effect of a resistor, and emits electrons through a series connection of a high-resistance resistor to an emitter. However, the use of high-resistance resistors of 10 to 100 million ohms connected to the emitter reduces the FED response and consumes a lot of power. In addition to inserting the high-resistance resistor, in order to solve such a problem, for example, more than 1000 emitters are integrated, a fed emitter array is formed, and the problem of emitter instability is countered by averaging multiple emitter outputs. However, the increase in the number of emitters leads to increased complexity and increased FED manufacturing costs. In order to solve these problems, Japanese Patent Laid-Open No. H9-259744 discloses a method for controlling the current flow in the emitter by bonding an active paper size to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 ------- * 1 Γ 1 If VI --II ---- ·-------- I < Please read the notes on the back before filling this page) A7 B7 Economy Guo Zhizhi Property Bureau 3 Industrial Consumer Cooperative ^ .¾ 5. Description of the invention (Components such as a transistor to the emitter of the FED. This stabilizes the current with low power consumption. In addition, the need to form a large number of emitters can be eliminated. The use of gadolinium silicon as a substrate has resulted in the inability to manufacture large-sized flat display elements and increased costs. Recently, this patent publication No. H9_129123; H Gamó et al., Letters of Applied Physics 73, 1301, 1998 and YH , Song et al., SID 98 Abstract 1 page 89, 1998 Reveals the use of glass substrates instead of single crystal silicon to allow for increased size and reduced cost for flat panel display devices. In this structure, the emitter and field effect transistors (FET) and its tritium and transistor (TET) It is formed on a glass-based substrate using amorphous silicon and polycrystalline silicon. Figures 10 (a) and 10 (b) show the trainer's configuration including the emitter and train 7 and Ding || Wei. 2 3. Section 10 (a) The figure is a perspective view showing that the overall FED corresponds to one pixel. Figure 10 (b) is an enlarged cross-sectional view of one emitter and! ^ Of the emitter array 7. As shown in Figure 0 (a), there are more than 1000 emitters. The emitter array 7 formed in the FED is used for each pixel controlled by a TFT 23. The current emitted by the emitter array 7 is controlled by a TFT 23 connected to the corner of the emitter array 7 through a cathode electrode. _
如第10(b)圊所示，FED皂含^述τ1Τ 23以及經由汲 極電掻丨9連結的射極單元。23包含一鉻源極電極9於 玻璃基材上，非晶矽接觸層及通道丨非晶矽層2〇，二氧 上矽閘極絕緣層3及鉻閘極電極4。射極單元包含前述TFT B，鉻汲極金屬19 .非晶矽射極10，二氧化矽絕緣層以及 銳提取電極11， 第Η圖顯示習知FED之製法：，如第1Ua)圖所示，各種 ---------------^--------^---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 455900 A7 _ B7 五、發明說明（3 ) 材料係循序層疊。然後將變成TFT 7之部分覆蓋從抗光蝕 劑21 * TFT以外區域藉姓刻去除而暴露出下方汲極電極19( 第11 (b)圖）。其次再度形成將形成射極的非晶矽層2〇(第 11 (c)圊）。然後形成射極形狀（第11 (d)圖），絕緣層24及提 取電極11形成於其頂上，形成一個射極孔洞來暴露出射極 梢端（第11(e)囷）。 說明中發射冷電子部分例如錐形部分後文稱作射極， 以及藉由連結射極與電晶體製成的整體裝置稱作fed。 習知FED有下列缺點。 當厚200毫微米或以下之薄非晶或多晶梦層形成於玻 璃基材上時，無法獲得具有高電子活動性及良好結晶性的 矽層。若FET之TFT或通道層形成於此種矽層上，則無法 獲得具有一致良好特性之TFT或FET。 此外，準分子雷射用於退火玻璃基材上的非晶矽使其 結晶化。如此使製程變複雜。雷射退火對於大量生產上不 利，增高製造成本。 更進一步，先前技術要求形成薄非晶矽層，絕緣層及 金屬層用於製造TFT或FET。射極上之各層經蝕刻，再度 形成射極用的較厚的非晶矽層，如此造成製程複雜化。於 再度形成非晶矽層來形成射極前，其形成面暴露於空氣。 如此污染生長中的表面，也可能劣化非晶矽層之結晶性。 又如第10(a)圖所示，無數射極睁列係由一個連結於 陣列區末端之FET控制。如此造成FET汲極與各射極晶片 間距離不同，造成FET與電極間電阻差異。結果各個射極 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐〉 I--'---i 裝-----— II 訂-----！·#. (諳先閱讀背面之注$項再填寫本頁) 經濟部智慧財產局員工消費合作社印*·ί A7 --------B7__ 五、發明說明（4 ) 之發射特性不等。 、 此外’ FET之閘極及源極相對於射極陣列以非對$方 式放置。如此造成射極陣列與陽極基材間之空間電位分布 非對襯’當FED用於扁平面板顯示裝置時，陽極基材為碟 側。如此電子的行進方向變成各向異性__ 又復由於FET之閘極金屬僅以絕緣層覆蓋，任何微小 程度的外部雜訊皆可能影響閘極金屬因而錯誤觸發FET， 大為變更射極的發射電流。 如前述’先前技術FED仍有各種缺點，使用此種fed 於扁平面板顯示裝置無法獲得高圖像品質，高圖傈品質有 賴於均勻一致以及高亮度。同時也增加電力消耗及成本。 發明概述 本發明之FED包含 一非晶基材； 雜質擴散阻擋層； 場效電晶體（FET)形成於由非晶矽或多晶石夕製成的— 半導體層表面上，該半導體層係形成於雜質擴散阻擋層上 方； 一或多個射極帶有尖化梢端係經由蝕刻FET之一沒極 區上的半導體層製成；以及 提取電極用於藉由外加高電場至射極而引導出電子。 半導體層係經由使用化學氣相沈積方法（CVD方法）利 用半導體材料氣體接觸加熱至高溫的高熔點金屬引發的催 ί匕效果形成' I ——I— II - II · I I I I I I ί ·11111111 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 455900 五、發明說明（ -射極或一包含多於一個射極之陣列形成於圓形或多 角形FET汲極區。射極陣列係由環形或多_祕電極及 源極電極環繞。然後_FET|t蓋於絕緣層及金屬層。 前述配置獲得下列效果。 5〇〇毫微求或以上的厚多晶妙層可以〇 2毫微米/秒或 更快速速率（相當高速）直接形成。如此可免除於形成多晶 砂層後使用雷射退的火多晶化過程。此外厚潛可改進表面 附近的結晶度，達成高活動性，因而可製造帶有均勻良好 特性的FET。 Μ由以單一步驟生長半導體層形成FET及射極也可減 化製程。消除第二步驟獲得厚半導體層，可防止生長中的 表面暴露於空氣，避免表面污染的可能。 以環形或多角形FET汲極區形成射極陣列可使fet汲 極與各射極間距相等，因此可平埃备1射極的電阻，如此使 各射極晶片的發射特性一致。此^ 射極陣列與陽極基材 間之空間電位分布與基材内部變對 因此可使電子發射As shown in Section 10 (b) (b), the FED soap contains the τ1Τ 23 and the emitter unit connected via the drain electrode 99. 23 includes a chromium source electrode 9 on a glass substrate, an amorphous silicon contact layer and a channel, an amorphous silicon layer 20, a silicon oxide insulating layer 3 and a chromium gate electrode 4 on the oxygen. The emitter unit includes the aforementioned TFT B, chromium drain metal 19, amorphous silicon emitter 10, silicon dioxide insulating layer, and sharp extraction electrode 11. The first figure shows a conventional FED manufacturing method: as shown in Figure 1Ua) , Various ----------------------- ^ --------- ^ (Please read the notes on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 455900 A7 _ B7 V. Description of the Invention (3) The materials are sequentially stacked. Then the part of the cover that becomes the TFT 7 is removed from the area outside the photoresist 21 * TFT by the last name to expose the lower drain electrode 19 (Fig. 11 (b)). Next, an amorphous silicon layer 20 (No. 11 (c)) that will form an emitter is formed again. Then, an emitter shape is formed (FIG. 11 (d)), and the insulating layer 24 and the extraction electrode 11 are formed on top of the emitter layer to form an emitter hole to expose the emitter tip (No. 11 (e) 囷). In the description, a part that emits cold electrons, such as a conical part, is hereinafter referred to as an emitter, and the entire device made by connecting the emitter and the transistor is called fed. The conventional FED has the following disadvantages. When a thin amorphous or polycrystalline dream layer having a thickness of 200 nm or less is formed on a glass substrate, a silicon layer having high electronic mobility and good crystallinity cannot be obtained. If a TFT or a channel layer of a FET is formed on such a silicon layer, a TFT or FET having consistently good characteristics cannot be obtained. In addition, excimer lasers are used to anneal amorphous silicon on glass substrates to crystallize it. This complicates the process. Laser annealing is not good for mass production and increases manufacturing costs. Furthermore, the prior art required the formation of a thin amorphous silicon layer, an insulating layer and a metal layer for manufacturing a TFT or FET. The layers on the emitter are etched to form a thicker amorphous silicon layer for the emitter again, which complicates the process. Before the amorphous silicon layer is formed again to form an emitter, its formation surface is exposed to air. Such contamination of the growing surface may also degrade the crystallinity of the amorphous silicon layer. As shown in Fig. 10 (a), countless emitter rows are controlled by a FET connected to the end of the array region. This results in a difference in the distance between the FET drain and each emitter chip, resulting in a difference in resistance between the FET and the electrodes. Results The paper size of each emitter was in accordance with China National Standard (CNS) A4 (210 * 297 mm) I --'--- i Packing ------- II Order -----! · #. ( (谙 Please read the note on the back before filling in this page) Seal of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * · ί A7 -------- B7__ 5. The emission characteristics of the invention description (4) vary. 'The gate and source of the FET are placed in a non-aligned manner relative to the emitter array. This causes the spatial potential distribution between the emitter array and the anode substrate to be non-aligned.' When FED is used in flat panel display devices, the anode base The material is on the dish side. In this way, the direction of the electrons becomes anisotropic. __ Also because the gate metal of the FET is only covered with an insulating layer, any slight external noise may affect the gate metal and trigger the FET by mistake. Change the emission current of the emitter. As mentioned above, the prior art FED still has various shortcomings. Using this kind of fed on flat panel display devices cannot obtain high image quality. High image quality depends on uniformity and high brightness. At the same time, power is also increased. Consumption and cost Summary of the invention The FED package of the present invention An amorphous substrate; an impurity diffusion barrier layer; a field effect transistor (FET) formed on the surface of a semiconductor layer made of amorphous silicon or polycrystalline silicon, the semiconductor layer being formed over the impurity diffusion barrier layer; One or more emitters with sharpened tips are made by etching a semiconductor layer on one of the electrode regions of the FET; and an extraction electrode is used to guide electrons by applying a high electric field to the emitter. The chemical vapor deposition method (CVD method) is used to utilize the semiconductor material gas to contact the high-melting-point metal that is heated to a high temperature to promote the dagger effect to form 'I ——I— II-II · IIIIII ί · 11111111 (Please read the note on the back first Please fill in this page for further information) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 455900 V. Description of the invention (-emitter or an array containing more than one emitter is formed in the circular or polygonal FET drain region. Emitter array It is surrounded by a ring-shaped or multiple _ secret electrode and source electrode. Then _FET | t is covered on the insulating layer and the metal layer. The foregoing configuration achieves the following effects. Thick polycrystalline layers of 500 nm or more can be used 〇2nm / sec or faster (very high speed) direct formation. This can avoid the fire polycrystallization process using laser retreat after the formation of polycrystalline sand layer. In addition, the thick latent can improve the crystallinity near the surface to achieve high Mobility makes it possible to manufacture FETs with uniform and good characteristics. The formation of FETs and emitters by growing semiconductor layers in a single step can also reduce the manufacturing process. Eliminating the second step to obtain a thick semiconductor layer prevents the growing surface from being exposed to Air to avoid the possibility of surface contamination. Forming an emitter array with a ring or polygonal FET drain region can make the fet drain equal to the distance between each emitter, so the resistance of one emitter can be prepared, so that each emitter chip The emission characteristics are consistent. The space potential distribution between the emitter array and the anode substrate is aligned with the interior of the substrate, so that electrons can be emitted.
1 I 於各方向均勻一致。FET比（閘極笔#_/閘極長度）也變大， 因而即使FET的活動力低也可製造具有高電流程度的fEt 對FET放置金屬層來屏蔽雜訊。如此避免FET受到FET 受到微弱外部雜訊影像出現脫離常軌的操作而造成射極發 射電流的高度起伏波動。 前述FET特徵應用於扁平面板顯示裝置將可提供高圖 像品質，包括均勻度及高亮度、低電源消耗及低成本。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） '裝 ------訂 --------" {請先閱讀背面之注意事項再填寫本頁) A7 五、發明說明（6 圖式之簡單說明 第1圖为J 4+ 固. '康本發明之第一具體實施例之FED之剖面 圖， 〒為根據本發明之第—具體實施例之錐型fe 剖面圖：、丨、， 第3 4為剖面圖無』1 一：面圖舉例說明根據本發明之第一具體實施 例之FED之^>。 第_為根據本發明之第二具體實施例之FED之剖面 圖； 第3圖為根據本發明之第三具體實施例之FED之剖面 圖； I------------裝。--- (請先閱讚背面之注意事項再填寫本頁) 圖： 6圖為根據本發明之第四具體實施例之FED之剖面 訂 經濟部智慧时產苟Λ工消費合作钍印 第7(a)圖為根據本發明之第五具體實施例之FED之平 面圖； 第7(b)圖為根據本發明之第五具體實施例之fed之剖 面圖： 第8圖為根據本發明之第五具體實施例附有收歛電極 之FED之剖面圊； 第9圖為根據本發明之第六具體實施例之fed之剖面 圖； 第！0(a)圖為習知FED之透視圖： 第為有關習知FEX)之元件部分之放大剖面圖： ( 第11 - j剖面圖舉例說明習知fed之製法： ；ϋ： ^ 9 經濟部智慧財產局員工消費合作社印制Λ 455900 A7 ___B7___ 五、發明說明（7 ) 第一具體實施例 本發明之第一具體實施例將參照第1、2及3圖說明如 後。 如第1圖所示，本發明之FED包含基材1，半導體層2 ，FET閘極絕緣層3，FET閘極金屬4，源極區5，FET汲極 區6及射極陣列7。 第一具體實施例中’射極陣列7係經由於形成FET後 蝕刻FET汲極區上的半導體層2形成。換言之，第一具體 實施例可藉單次生長半導體層2而形成FET及射極。防止 表面暴露於空氣可簡化製程及避免結晶性的低劣，空氣對 二階段生長半導體層2成問題。 第2圖顯示於錐形射極1〇及提取電極丨丨添加至第丨圖所 示射極單元後之FED之剖面圖。除第1圖外，第又圖顯示雜 質擴散阻擋層8，FET源極電極9，射極陣列1^之—個錐形 射極10 ’提取電極11，提取電極續不方之絕緣 <以:友FET 被動層13。 _雙,> '^0^ 由於錐形射極係位在圓柱形孔洞士心，電場係於其梢 端均勻集中，均句且以相對低電量發射於電子。如此使用 錐形射極及提取電極於第1圖所示FET配置將可達成滿意 的冷電子發射特性》 基材1為半導體例如矽製成的單晶或多晶基材=特別 使用非晶玻璃基材可放大尺寸，因而當應用於顯示元件時 可降低成本且增大尺寸。 通常於層形成的初步階段使用比200毫微米更薄的薄 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 10 -----I------- -裝！ — |_丨訂---------#f {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合"钍^匀 A7 ______B?______ 五、發明說明（8 ) 層無法達成滿.¾的結晶度’原因在於當多晶半導體層2形 成於玻璃基材1上時各晶體間的晶格常數不同故。於層厚 度超過500毫微米之後結晶度漸近改良=如此於厚度大於 500毫微米之層之晶體面上形成fet有助於形成電子活動 性超過10平方厘米/伏.秒的半導體層2。一種形成半導體 層2的方法為CVD方法，其利用半導體材料氣體接觸被加 熱至高溫的高溶點金屬引發的揮發效應。若微晶粒矽或多 晶矽使用此種CVD方法生長，則獲得電子活動性高於1〇 平方厘米/伏·秒的半導體層2 ,此種半導體層適合控制射 極的發射電流。 雜質擴散阻擋層8放置用以防止當基材與頂上半導體 層具有不同組成時，基材的元素熱擴散至半導體層成為雜 質造成的任何有害影響。特別用於一般製程之緊密填裳氧 化矽及氮化矽層可有效壓抑雜質的擴散同時也容易製造。 至於半導體2,可使用IV族半導體如矽及⑴-乂族半導 體如鎵及砷。特別有寬帶隙的半導體如鑽石、氮化硼及氣 化鎵本身具有高電子親和力。此等類型於真空於低電壓發 射電子’因而適合作為射極。也對石夕用於積體電路做徹底 研究’碎也具有穩定氧化物層。如此使用石夕對於控制使用 積體電路射極有利。由於前述半導體也可用作射極，因此 谷易製造射極與FET的組合。 為了製造一種η通道FET ‘可快速響應且可流動大量 電流’可使用ρ型東導體作為半導體層2的材料：ρ型半導 體可藉攙雜硼或鋁至[V族半導體，或藉攙雜鎂及鋅至U卜 . 1 Μ. ----^---------線 (請先間讀背面之注意事項再填寫本頁) 455900 A7 五、發明說明（9 經 濟 部 智 慧 財 產 局1 I is uniform in all directions. The FET ratio (gate pole pen # _ / gate length) also becomes larger, so fEt with a high current level can be manufactured even if the FET has low mobility. A metal layer can be placed on the FET to shield it from noise. This prevents the FET from being subjected to weak external noise and the FET is subjected to off-orbit operation, which causes high fluctuations in the emitter emission current. The aforementioned FET features applied to flat panel display devices will provide high image quality, including uniformity and high brightness, low power consumption, and low cost. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 'Packing ------ Order -------- " {Please read the precautions on the back before filling this page ) A7 V. Explanation of the invention (6 Brief description of the diagram The first diagram is J 4+ solid. 'Kang sectional view of the FED of the first embodiment of the present invention, 〒 is the first-specific embodiment of the present invention Sectional view of the cone-shaped fe: ,,,,, 3, 4 is a cross-sectional view without "1": The surface view illustrates the FED of the FED according to the first embodiment of the present invention. ^ Is the second according to the present invention. A cross-sectional view of a FED in a specific embodiment; FIG. 3 is a cross-sectional view of a FED in accordance with a third specific embodiment of the present invention; I ------------ install. --- (Please read first Note on the back of this page, please fill out this page again) Figure: Figure 6 is a cross-section of the FED according to the fourth embodiment of the present invention. The fifth embodiment of the invention is a plan view of the FED; FIG. 7 (b) is a sectional view of the fed according to the fifth embodiment of the invention: FIG. 8 is a fifth embodiment of the invention Section 圊 of a FED with a converging electrode in the embodiment; Figure 9 is a sectional view of a fed according to a sixth specific embodiment of the present invention; Figure 0 (a) is a perspective view of a conventional FED: Enlarged sectional view of the component part of the FEX): (Section 11-j illustrates the conventional method of manufacturing fed: ϋ: ^ 9 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ 455900 A7 ___B7___ V. Description of the invention ( 7) First specific embodiment The first specific embodiment of the present invention will be described below with reference to Figures 1, 2 and 3. As shown in Figure 1, the FED of the present invention includes a substrate 1, a semiconductor layer 2, and a FET gate. The electrode insulating layer 3, the FET gate metal 4, the source region 5, the FET drain region 6 and the emitter array 7. In the first embodiment, the 'emitter array 7 is formed by etching the FET drain region after forming the FET. In other words, the first specific embodiment can form a FET and an emitter by growing the semiconductor layer 2 at a time. Preventing the surface from being exposed to air can simplify the process and avoid poor crystallinity. 2 becomes a problem. Figure 2 shows the tapered emitter 10 and Take the cross section of the FED after the electrode is added to the emitter unit shown in Figure 丨. In addition to Figure 1, the figure shows the impurity diffusion barrier layer 8, the FET source electrode 9, and the emitter array 1 ^- Tapered emitters 10 'extract electrodes 11, the extraction electrodes continue to be insulated < with: Friends of FET passive layer 13. _double, >' ^ 0 ^ Because the tapered emitter is located in the center of a cylindrical hole The electric field is uniformly concentrated at its tip, and it emits electrons with relatively low power. Using the tapered emitter and extraction electrode in the FET configuration shown in Figure 1 will achieve satisfactory cold electron emission characteristics. "The substrate 1 is a single crystal or polycrystalline substrate made of a semiconductor such as silicon. In particular, amorphous glass is used. The substrate can be enlarged in size, so that it can reduce cost and increase size when applied to a display element. Usually in the initial stage of layer formation, thinner than 200 nanometers is used. The paper size is applicable to China National Standard (CNS) A4 (210 * 297 mm) 10 ----- I -------- Install! — | _ 丨 定 --------- # f {Please read the notes on the back before filling out this page) Staff Consumption Agreement of the Intellectual Property Bureau of the Ministry of Economic Affairs " 钍 ^ Uniform A7 ______ B? ______ 5. Description of the Invention (8) The layer cannot achieve full crystallinity. The reason is that when the polycrystalline semiconductor layer 2 is formed on the glass substrate 1, the lattice constants between the crystals are different. Gradual improvement in crystallinity after layer thickness exceeds 500 nm = thus forming a fet on the crystal surface of a layer with a thickness of more than 500 nm helps to form a semiconductor layer 2 having an electron mobility of more than 10 cm2 / V.s. One method of forming the semiconductor layer 2 is a CVD method, which uses a volatilization effect caused by contacting a semiconductor material gas with a high melting point metal heated to a high temperature. If microcrystalline silicon or polycrystalline silicon is grown using this CVD method, a semiconductor layer 2 having an electron mobility higher than 10 cm2 / v · s is obtained, and this semiconductor layer is suitable for controlling the emission current of the emitter. The impurity diffusion barrier layer 8 is placed to prevent any harmful effects caused by thermal diffusion of elements of the substrate to the semiconductor layer when the substrate and the semiconductor layer on top have different compositions. Especially tightly packed silicon oxide and silicon nitride layers for general processes can effectively suppress the diffusion of impurities and are easy to manufacture. As for the semiconductor 2, a group IV semiconductor such as silicon and a hafnium-rhenium semiconductor such as gallium and arsenic can be used. Particularly wide-bandgap semiconductors such as diamond, boron nitride, and gallium gas have high electron affinity by themselves. These types emit electrons in a vacuum at a low voltage and are therefore suitable as emitters. A thorough study of Shi Xi's use in integrated circuits has also been made. The chip also has a stable oxide layer. Using Shi Xi in this way is extremely beneficial for controlling the use of integrated circuit emitters. Since the aforementioned semiconductor can also be used as an emitter, Gu Yi manufactures a combination of an emitter and a FET. In order to make an n-channel FET 'fast-responding and capable of flowing a large amount of current', a p-type east conductor can be used as a material for the semiconductor layer 2: a p-type semiconductor can be doped with boron or aluminum to a [V group semiconductor, or doped with magnesium and zinc To U. 1 Μ. ---- ^ --------- line (please read the notes on the back before filling this page) 455900 A7 V. Invention Description (9 Intellectual Property Bureau, Ministry of Economic Affairs
消費 合 作 社. 印 4'J V族半導雜。他方面’為了製造n通道，可使_型半 導體。N型半導雖之製法可經由攙雜峨或砷至…族半導體 ，以及經由攙雜矽或硫至m_v族半導體。為了集成電子 電路來控制射極的作業，以c_M〇s電路為佳。此例中需要 η通道及p通道FETs二者。 半導體層2可為非晶、多晶或單晶結構。當使用單晶 於半導體層2時，基材1的材料受限制。用於大型玻璃基材 ，可能需要使用非晶或多晶半導體層2。此種情況下，氫 處理可有效藉由半導體内部的懸掛鍵而改善結晶度！ FET開極絕緣層3可由二氧化矽 '氮化矽或其複合物 製成’其具有高電絕緣能力及極緻密結構。為了減少絕緣 層3的失真，單層此種材料層組合而形成各層。若使用cvd 方法製造絕緣層3’則由半導體層至氮化矽層的各層可接 績形成而未對半導體層造成任何傷害。如此可製造具有良 好特性的FET。前述絕緣層3也可用作加工處理射極的蝕 刻罩蓋，或攙雜離子於ΪΈΤ汲極區的罩蓋。 用於加工處理射極形狀，前述絕緣層3可用作罩蓋。 絕緣層3也可用作攙雜離子於FET汲極區之罩蓋。 用於金屬佈線包括FET閘極金屬4、FET源極電極9及 提取電極11 ;可使用具有低電阻的廉價鋁，鋁也可用於形 成高品質陽極氧化物層。另外，可使用廉價銅且有甚至更 低電阻：鈦，其可改良對玻璃基材的黏著性：或钽其也可 形成良好品質之陽極氧化物層β其他元素例如鍺也可添加 至例如紹來壓抑形成小丘，且產生含有95%重量比或以上 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） 12 ______‘___I___^1··裝___ (請先閱讀背面之沒意事項再填寫本頁) Μ6- 線丨 A7 B7 經濟部智慧財產局員工"'費合作?±印 五、發明說明（10 ) 之主要成分的合金。 當於玻璃基材上形成金屬層時，可首先形成100毫微 米或以下的濤鈦層接著形成鋁層來改良黏著性及導電度。 如此此等金屬元素可用作單層或合併形成多層來獲得各種 金屬的最佳特性。 第3(a)至3(f)圖顯示於第一具體實施例中FED製法之 例之剖面圖。 如第3(a)圖所示，雜質擴散阻擋層8、半導體層2及feT 閘極絕緣層3係連續使用電漿輔助cvd方法接著使用FET 閘極金屬4沈積而藉真空沈積連續形成3其次如第3(b)圖 所示，閘極金屬4及閘極絕緣層3係藉蝕刻例如反應性離子 蝕刻圖樣化而形成FET之射極位置3 然後如第3(c)圖所示，使用閘極絕緣層3作為蝕刻例 如反應性離子敍刻罩蓋而形成錐形射極。 其次如第3(d)圖所示，使用攙雜技術例如離子植入形 成FET源極區5及FET汲極區6 〇射極係同時攙雜。 如第3(e)圖所示，提取電極u下方的絕緣層12典型係 使用電漿輔助CVD方法形成，隨後於源極區5蝕刻接觸孔 /同.以及典型使用減鍵形成F Ε τ源極電極9。 如第3(f)圖所示，典型使用電漿輔助CVD方法連續形 成FET被動絕緣層13及提取電極丨卜 最後如第3(g)圖所示，提取電極u及提取電極u下方 的絕緣層12經敍刻雨暴露出雜形射極： 絕緣層1 3係以比絕緣層丨2更慢的蝕刻速率蝕刻…例如 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁> 經濟部智慈財產局員工消費合作社印製 455900 A7 ____B7____ 五、發明說明（11 ) 二氧化矽可用於絕緣層12 ’氮化矽可用於絕緣層13，或絕 緣層Π可製作成比絕緣層12更厚《原因在於若絕緣層12及 絕緣層13係由相同材料且相等厚度製成，則fet本身可藉 由溶解於蝕刻劑攜毁’而提取電極11及絕緣層12經蝕刻而 暴露出射極。 第3(a)圖所示半導體層2或閘極絕緣層3係較佳使用一 或多種一矽烷，二矽烷，氫，氮，氨，甲烷，乙烷，丙烧 ’丁炫，三甲基鎵，三乙基鎵，三甲基鋁，胂烷，膦，及 乙硼院作為CVD之材料氣體’利用高溶點金屬例如鈦、 组及翻之催化效果形成（所謂的熱線方法）^如此比較使用 射頻的尋常電漿輔助CVD ’可於相當快速率約〇.2至0.5毫 微米/秒甚至於相對低溫低於500°C或以下，形成厚500毫 微米或以上之多晶石夕層且附有電子活動力1〇平方厘米•伏 秒。結果無需例如使用準分子雷射退火至多晶矽的後退 火製程β 此外，如第3(c)圖所示，使用部分閘極絕緣層3作為 蝕刻罩蓋用於蝕刻錐形射極可減化製程β 如第3(d)圖所示’ FET源極區5、FET汲極區6、錐形 射極10、FET汲極及射極之電阻可使用離子植入調整，也 可減化製程。若離子係被植入於FET汲極與射極間，留〒 部分FET閘極絕緣層3 ’則此剩餘部分將不被攙雜或較少 被攙雜’因而可微調FET汲極與射極間整體通道的電阻。 離子攙雜量也需根據FET閘極絕緣層3厚度調整，如 此也可調整電阻。由於各射極與汲極間電阻可調整，故由 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 14 --------.--l· 裝--------訂---------梦r (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作，社印製 A7 ___B7 五、發明說明（Π ) 各射極發射的電子可被均勻一致。此外，若高電阻提供於 射極與汲極間’則隨著時間由射極發射電子變化可就電阻 的負面回授穩定化。 如第3(g)圖所示方法’半導體層2之結晶性可藉加熱 處理改良’如此可改良FET及於平面均勻度等特性3特別 於非晶矽及多晶矽之例，若形成含大量氫的氮化矽被動層 ’則加熱處理可於單純氮或惰性氣體執行。但通常FET特 性可藉加熱處理於含氫或水蒸氣氣氛下加熱處理而有效改 善。 第二具體實施例 參照第4圖說明本發明之第二具體實施例。射極1 〇表 面覆蓋碳保源層14例如鑽石或仿鑽石碳，其為化學鈍性且 不會劣化電子發射特性，因而使射極表面變成化學鈍性。 結果即使於相對低真空仍可維持滿意的電子發射特性’而 未於真空系統受其餘氣體衝擊或吸附損傷。保護層14係於 第3(f)圖所示步驟後於電極墊以外區域，典型使用微波激 勵電漿輔助CVD形成》 第三具體例實施例 其次參照第5圖說明本發明之第三具體例實施例： 如第，圖所示，本具體實施例之FET包括一高電阻區15 介於FET之閘極與源極間以及介於四丁之閘極與汲極間。 巧電咀區1:»可藉由減少閘極與源極間以及閘極與汲極間的 攙雜量形成：第二具體實施例之結搆可防止因汲極電極周 圍的高電場產生的衝擊離子效應造成發射電流的漂流，如 15 裝--------訂------，1!線 (請先間讀背面之沒意事項再填寫本頁) 455900 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（l3 此減少OFF電流以及衝擊離子效應。 第四具體實施例 其次參照第6圖說明本發明之第四具體實施例。 當玻璃基材1或雜質擴散阻擋層8為非晶形時，或具有 與半導體層2不同的晶格常數時，玻璃基材1上或雜質擴散 阻擋層8上形成半導體層結晶化困難。即使半導體層被結 晶化也增加失真或瑕嵌密度β為了減少此種失真或瑕庇g:4>失 度，第五具體實施例之FET將厚100毫微米或以下之非 層16插置於基材與半導體層間或插置於雜質擴散阻擋層與^: 半導體層間。 例如若多晶矽形成於玻璃基材上，則厚1 〇〇毫微米或 以下之矽及鍺或非晶矽層的應變超晶格可使用電漿輔助 CVD方法插置’因而防止於交界面產生之缺陷晶體生長 的漫延。由於晶格常數或熱膨脹係數差異引起的失真也可 減少而輔助半導體層的結晶化。非晶矽層也可使用相同方 法於比多晶矽更低溫於形成多晶矽層之前形成^此型非晶 矽層對於稍後製程於整體基材内部之多晶矽層一致的結晶 化特別有效。 第五具體實施例 後文參照第7及8圖說明本發明之第五具想實施例。 此具體實施例之FED之製法同第3圖舉例說明之製法 。差異在於如第7圖所示，採用環形閘極結構作為fet， 以及射極係形成於FET中心的環形；;及極區- 射極10係設置於環形汲極區6呈同心或迴轉對襯，故 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 16 ------!Γ! !裝，--I---—訂·--------梦 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財壹局員工消費合"社£0" A7 B7 五、發明說明（Η ) FET閘極與各個射極間之間距維持相等。各射極之電阻相 等因此可使來自各射極的發射電流相等，同時防止來自 FET的漏電流。 此外，由提取電極1 1 '閘極金屬4及源極電極3形成的 電場對由射極發射的電子具有相等效果，如此電子係於各 方向一致發射。此外，環形閘極結構可獲得FET之閘極寬 度/閘極長度（W/L)之比值變大，允許即使半導體層2之電 子活動性低仍可製造具有高電流可接受的FETs。 若形成如第10(a)圖所示’具有與先前技術相等電流 程度的FET ’則閘極面積（w X L)可變成比先前技術更大， 如此可減少由於FETs製造尺寸上的偏差造成基材内部w/L 偏差= 但於η通道之例，閘極電壓通常係藉正電場控制。如 此吸引由射極發射電子，使電子略微展布於基材。於負電 場的收歛電極17形成於環形FET上（如第8圊所示）俾調整發 射電子的展開角度。第3(f)圖所示提取電極11也可圖樣化 而作為收歛電極1 7。 第六具體實施例 參照第9圖說明本發明之第六具體實施例。 第六具體實施例中，整個FET覆蓋金屬層18而形成FET 雜訊屏蔽層。如此免除由於對閘極金屬的感應雜訊產生的 十的外部雜訊造成形成於F +ET汲極之射極發射電流出現大 起丨犬波動第3(f)圖所示提取電極11可被圖樣化而作為此 楂金屬層1 8 '金屬層1 8也可維持地電位俾達成足夠雜訊屏 II —i n n I I If ·1 一OJ Itr ff I n t— t I (請先閱讀背面之注意事項再填寫本頁) U用嘌準（cx:w規格Consumer Cooperatives. India 4'J V family semiconducting miscellaneous. In other aspects, in order to make n-channels, _-type semiconductors can be used. Although N-type semiconductors can be manufactured through doped arsenic or arsenic to group semiconductors, and through doped silicon or sulfur to m_v group semiconductors. In order to integrate the electronic circuit to control the operation of the emitter, a c_Mos circuit is preferred. Both n-channel and p-channel FETs are required in this example. The semiconductor layer 2 may have an amorphous, polycrystalline, or single crystal structure. When a single crystal is used for the semiconductor layer 2, the material of the substrate 1 is limited. For large glass substrates, amorphous or polycrystalline semiconductor layers 2 may be required. In this case, hydrogen treatment can effectively improve the crystallinity by dangling bonds inside the semiconductor! The FET open-electrode insulating layer 3 may be made of silicon dioxide 'silicon nitride or a composite thereof', which has a high electrical insulation ability and an extremely dense structure. In order to reduce the distortion of the insulating layer 3, a single layer of such a material layer is combined to form each layer. If the cvd method is used to manufacture the insulating layer 3 ', each layer from the semiconductor layer to the silicon nitride layer can be formed successively without causing any damage to the semiconductor layer. In this way, a FET having good characteristics can be manufactured. The foregoing insulating layer 3 can also be used as an etching cover for processing the emitter electrode, or a cover for doping ions in the drain region. For processing the shape of the emitter, the aforementioned insulating layer 3 can be used as a cover. The insulating layer 3 can also be used as a cover for doping ions in the drain region of the FET. Used for metal wiring includes FET gate metal 4, FET source electrode 9 and extraction electrode 11; inexpensive aluminum with low resistance can be used, and aluminum can also be used to form a high-quality anodic oxide layer. In addition, inexpensive copper can be used with even lower resistance: titanium, which can improve adhesion to glass substrates: or tantalum which can also form a good quality anodic oxide layer β other elements such as germanium can also be added to, for example, Shao To suppress the formation of hillocks, and produce 95% by weight or more of this paper size applicable to Chinese national standard < CNS) A4 specification (210 X 297 mm) 12 ______'___ I ___ ^ 1 ·· installation ___ (Please read first Please fill out this page on the unintentional matter on the back) Ｍ6- 线 丨 A7 B7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs " Fee cooperation? ± Imprint 5. Invention alloy (10) as the main component of the alloy. When forming a metal layer on a glass substrate, a titanium layer of 100 nm or less can be formed first and then an aluminum layer can be formed to improve adhesion and conductivity. As such, these metal elements can be used as a single layer or combined to form multiple layers to obtain the best characteristics of various metals. Figures 3 (a) to 3 (f) are sectional views showing an example of the FED manufacturing method in the first embodiment. As shown in FIG. 3 (a), the impurity diffusion barrier layer 8, the semiconductor layer 2, and the feT gate insulation layer 3 are continuously formed using a plasma-assisted cvd method, followed by deposition using FET gate metal 4, and subsequently formed by vacuum deposition. As shown in FIG. 3 (b), the gate metal 4 and the gate insulating layer 3 are patterned by etching, such as reactive ion etching, to form the emitter position 3 of the FET. Then, as shown in FIG. 3 (c), use The gate insulating layer 3 forms a tapered emitter as an etching such as a reactive ion etch cover. Secondly, as shown in Fig. 3 (d), doping techniques such as ion implantation are used to form the FET source region 5 and the FET drain region 60. The emitter is simultaneously doped. As shown in FIG. 3 (e), the insulating layer 12 under the extraction electrode u is typically formed using a plasma-assisted CVD method, and then a contact hole is etched in the source region 5 and the F E τ source is typically formed using a reduced bond.极 electrode 9. As shown in FIG. 3 (f), a plasma-assisted CVD method is typically used to continuously form the FET passive insulating layer 13 and the extraction electrode. Finally, as shown in FIG. 3 (g), the extraction electrode u and the insulation under the extraction electrode u are continuously formed. Layer 12 exposes a heterogeneous emitter through the scoring rain: The insulating layer 1 3 is etched at a slower etching rate than the insulating layer 丨 2 ... For example ------------- installation ---- ---- Order --------- Line (Please read the notes on the back before filling out this page >> Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 455900 A7 ____B7____ 5. Description of the invention (11) Silicon dioxide can be used for the insulation layer 12 'Silicon nitride can be used for the insulation layer 13 or the insulation layer Π can be made thicker than the insulation layer 12 "The reason is that if the insulation layer 12 and the insulation layer 13 are made of the same material and the same thickness If the electrode itself and the insulating layer 12 are etched by dissolving in the etchant, the electrode 11 and the insulating layer 12 are etched to expose the emitter. The semiconductor layer 2 or the gate insulating layer 3 shown in FIG. 3 (a) is preferred. Use one or more monosilanes, disilanes, hydrogen, nitrogen, ammonia, methane, ethane, propane, butylene, trimethylgallium, triethylgallium, trimethylaluminum Phenane, phosphine, and diboron are used as CVD material gases 'formed using the catalytic effect of high melting point metals such as titanium, titanium and titanium (the so-called hotline method) ^ Such a comparison of ordinary plasma-assisted CVD using radio frequency' can be used in Quite a fast rate of about 0.2 to 0.5 nm / sec or even a relatively low temperature of less than 500 ° C or below, forming a polycrystalline layer with a thickness of 500 nm or more with an electronic activity of 10 cm 2 • V The result does not require, for example, the post-annealing process β using excimer laser annealing to polycrystalline silicon. In addition, as shown in FIG. 3 (c), the use of part of the gate insulating layer 3 as an etching cover for etching the tapered emitter can be reduced. The fabrication process β is shown in FIG. 3 (d). The resistance of the FET source region 5, FET drain region 6, cone emitter 10, FET drain and emitter can be adjusted by ion implantation, or reduced. Process. If the ion system is implanted between the FET drain and emitter, leaving a part of the FET gate insulation layer 3 ', the remaining part will not be doped or less doped, so the FET drain and emitter can be fine-tuned. The overall channel resistance. The amount of ion dopant also depends on the thickness of the FET gate insulation layer. The adjustment can also adjust the resistance in this way. Because the resistance between each emitter and the drain can be adjusted, the Chinese national standard (CNS) A4 specification (210x297 mm) is applied from this paper size 14 --------.- -l · Outfit -------- Order --------- Dream (Please read the notes on the back before filling out this page) The Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Co-operation, A7 ___B7 V. Description of the Invention (Π) The electrons emitted by each emitter can be uniform. In addition, if a high resistance is provided between the emitter and the drain ', then the electrons emitted from the emitter change over time, and the negative feedback of the resistance can be given. Stabilization. As shown in Figure 3 (g), the method "the crystallinity of the semiconductor layer 2 can be improved by heat treatment" can improve the characteristics of the FET and the uniformity in the plane. 3 It is particularly the case of amorphous silicon and polycrystalline silicon. If a large amount of hydrogen is formed, The silicon nitride passive layer 'can be heat-treated in pure nitrogen or inert gas. However, the characteristics of FETs can usually be effectively improved by heat treatment under hydrogen or water vapor atmosphere. Second Specific Embodiment A second specific embodiment of the present invention will be described with reference to Fig. 4. The surface of the emitter electrode 10 is covered with a carbon source layer 14 such as diamond or diamond-like carbon, which is chemically inert and does not deteriorate electron emission characteristics, thereby making the surface of the emitter chemically inactive. As a result, satisfactory electron emission characteristics can be maintained even at a relatively low vacuum without being damaged by the impact or adsorption of the remaining gas in the vacuum system. The protective layer 14 is formed in a region other than the electrode pad after the step shown in FIG. 3 (f), and is typically formed using a microwave excited plasma to assist CVD. A third specific embodiment is described next with reference to FIG. 5. Embodiment: As shown in the figure, the FET of this embodiment includes a high-resistance region 15 between a gate and a source of the FET and between a gate and a drain of a quadrupole. Qiaodianzui area 1: »can be formed by reducing the amount of impurities between the gate and the source and between the gate and the drain: the structure of the second embodiment can prevent impact ions generated by the high electric field around the drain electrode Effect causes drift of emission current, such as 15 packs -------- order --------, 1! Line (please read the unintentional matter on the back before filling in this page) 455900 A7 B7 Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau. 5. Description of the invention (l3 This reduces the OFF current and the impact ion effect. Fourth specific embodiment Secondly, the fourth specific embodiment of the present invention will be described with reference to FIG. 6. When the glass substrate 1 or impurities diffuse When the barrier layer 8 is amorphous or has a lattice constant different from that of the semiconductor layer 2, it is difficult to crystallize the semiconductor layer formed on the glass substrate 1 or the impurity diffusion barrier layer 8. Even if the semiconductor layer is crystallized, distortion or Defect embedding density β In order to reduce such distortion or defect g: 4 > misalignment, the FET of the fifth embodiment inserts a non-layer 16 having a thickness of 100 nm or less between a substrate and a semiconductor layer or an impurity Between the diffusion barrier layer and the semiconductor layer. If polycrystalline silicon is formed on a glass substrate, the strained superlattice of silicon and germanium or amorphous silicon layers with a thickness of 1000 nm or less can be inserted using a plasma-assisted CVD method, thereby preventing defects at the interface. Crystal growth. The distortion caused by the difference in lattice constant or thermal expansion coefficient can also be reduced to assist the crystallization of the semiconductor layer. The amorphous silicon layer can also be formed at a lower temperature than polycrystalline silicon before the polycrystalline silicon layer is formed ^ This type The amorphous silicon layer is particularly effective for uniform crystallization of a polycrystalline silicon layer that is later manufactured inside the monolithic substrate. Fifth Specific Embodiment Hereinafter, a fifth conceivable embodiment of the present invention will be described with reference to FIGS. 7 and 8. This specific implementation The manufacturing method of the example FED is the same as that illustrated in Figure 3. The difference is that as shown in Figure 7, a ring gate structure is used as the fet, and the emitter is formed in a ring shape in the center of the FET; and the pole region-the emitter 10 It is set in the ring-shaped drain region 6 to be concentric or rotating, so the paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) 16 ------! Γ!! I ---- Order · -------- Dream (Please read the precautions on the back before filling out this page.) The Consumers ’Consumption Cooperative of the Ministry of Economic Affairs and the Intelligent Welfare Bureau A7 B7 V. Description of the Invention ()) The distance between the FET gate and each emitter is kept equal. The resistance of each emitter is equal, so that the emission current from each emitter can be equalized, and the leakage current from the FET can be prevented at the same time. In addition, the electric field formed by the extraction electrode 1 1 ′ gate metal 4 and the source electrode 3 pairs the emitter. The emitted electrons have an equal effect, so that the electrons are emitted uniformly in all directions. In addition, the ring gate structure can obtain a larger gate width / gate length (W / L) ratio of the FET, allowing even the electrons of the semiconductor layer 2 Low activity can still make FETs with high current acceptable. If a FET having the same current level as that of the prior art is formed as shown in FIG. 10 (a), the gate area (w XL) can be larger than that of the prior art, which can reduce the basis caused by deviations in manufacturing dimensions of the FETs. Internal w / L deviation = But in the case of η channel, the gate voltage is usually controlled by a positive electric field. This attracts electrons emitted by the emitter, causing the electrons to spread slightly on the substrate. The converging electrode 17 in the negative electric field is formed on the ring FET (as shown in Fig. 8), and the spread angle of the emitted electrons is adjusted. The extraction electrode 11 shown in Fig. 3 (f) may be patterned and used as a convergent electrode 17. Sixth Specific Embodiment A sixth specific embodiment of the present invention will be described with reference to Fig. 9. In the sixth specific embodiment, the entire FET is covered with the metal layer 18 to form a FET noise shielding layer. This eliminates the large external emission noise caused by the induction noise on the gate metal, which causes the emitter emission current formed in the F + ET drain to increase greatly. The extraction electrode 11 shown in Figure 3 (f) can be changed. The pattern can be used as the metal layer of the hawk 1 'The metal layer 18 can also maintain the ground potential and achieve a sufficient noise screen II —inn II If · 1-OJ Itr ff I nt — t I (Please read the precautions on the back first (Fill in this page again) Purine standard for U (cx: w specifications
JiO - 297 17 455900 A7 B7 五、發明說明（15 ) 蔽效果。 產業應用 如前述，本發明之FED使用於單一步驟形成半導體層 於大片玻璃基材上之簡單方法，無需後退火製程可製造具 有均勻一致且滿意的特徵之帶有FETs之射極陣列。 此外，使用具有環形閘極之金屬層屏蔽型FET可賦與 對外部雜訊的強力抗性，因而可一致控制相當大電流發射 特性，且獲得各方向帶有均勻電子發射的射極特性。當本 發明之FED應用至扁平面板顯示裝置時，可實現對高圖像 品質具有關鍵重要性的因素包括均勻度及高亮度，且可實 現低電力消耗及低成本。 ---I-------L. I --------訂 ------練'·' (請先Μ讀背面之注*1^項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 18 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） A7 _B7_ 五、發明說明（I6 ) 元件標號對照 經濟部智慧財產局—工消費合作社印絜 1…基材 13…FET被動層 2…半導體層 14···保護層 3…FET閘極絕緣層 15.··高電阻層 4…FET閘極金屬 16…應變超晶格或非晶層 5..· FET源極區 17…收歛電極 6…F E T〉及極區 18···屏蔽金屬層 7…射極陣列 19…汲極電極 8···雜質擴散阻擋層 20·..非晶矽 9··· FET源極電極 21 · · ·抗光ϋ劑 10…於射極陣列之一錐形 22…二氧化矽罩蓋 射極 23---FET 11…提取電極 24···二氧化矽絕緣層 12···於提取電極下方之絕 緣層 I n n n ^1. I— .^1 · n n If I 1^1 ^1 ^1 ^1 ^1 ^1 I (請先閱讀背面之注意事項再填寫本頁)JiO-297 17 455900 A7 B7 V. Description of the invention (15) The shielding effect. Industrial Application As mentioned above, the FED of the present invention uses a simple method of forming a semiconductor layer on a large glass substrate in a single step. Without post-annealing, an emitter array with FETs with uniform and satisfactory characteristics can be manufactured. In addition, the use of a metal-layer shielded FET with a ring gate can impart strong resistance to external noise, so that it can uniformly control a relatively large current emission characteristic, and obtain an emitter characteristic with uniform electron emission in all directions. When the FED of the present invention is applied to a flat panel display device, factors that can achieve key importance to high image quality include uniformity and high brightness, and can achieve low power consumption and low cost. --- I ------- L. I -------- Order ------ Practice '·' (Please read the note on the back * 1 ^ before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs of the Consumer Cooperatives 18 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) A7 _B7_ V. Description of the invention (I6) The component numbers are compared with the Intellectual Property Bureau of the Ministry of Economic Affairs-Industry Consumer cooperative seal 1 ... substrate 13 ... FET passive layer 2 ... semiconductor layer 14 ... protective layer 3 ... FET gate insulating layer 15 .... high resistance layer 4 ... FET gate metal 16 ... strained superlattice or Amorphous layer 5 ..... FET source region 17 ... convergent electrode 6 ... FET> and electrode region 18 ... shield metal layer 7 ... emitter array 19 ... drain electrode 8 ... impurity diffusion barrier layer 20 ... Amorphous silicon 9 ··· FET source electrode 21 · · · Anti-light tincture 10 ... one cone 22 of the emitter array ... silicon dioxide cover emitter 23-FET 11 ... extraction electrode 24 · ·· Silicon dioxide insulation layer 12 ··· Insulation layer under the extraction electrode I nnn ^ 1. I—. ^ 1 · nn If I 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 I (Please read first (Notes on the back then fill out this page)