408426 4259twf.doc/〇〇6 A 7 _^___B7___ 五、發明説明（/ ) 本發明是有關於一種動態隨機存取記憶體（Dynamic408426 4259twf.doc / 〇〇6 A 7 _ ^ ___ B7___ 5. Description of the invention (/) The present invention relates to a dynamic random access memory (Dynamic
Random Access Memory; DRAM)電容器（Capacitor)之 介電膜層（Dielectric Layer)的製造方法’且特別是有 關於一種增加電容器儲存電荷能力的方法。 單一電晶體DRAM胞，是由一個金氧半電晶體與一個 電容器所構成，而電容器是DRAM胞藉以儲存訊號的心臟 部位，如果電容器所儲存的電荷愈多，則讀取放大器在讀 取資料時受雜訊的影響將可大大的降低，更可減少"再補 充（Refresh) 〃的頻率。增加電容器儲存電荷能力的方 法有：（1)增加電容器的面積，使整個儲存於電容器內的 電荷數量增加，但這將使得DRAM的積集度（Integration) 下降；（2)選擇適當的介電層材料以增加介電層的介電常 數，使電容器單位面積所能儲存的電荷數增加；（3)減少 介電層的厚度，但是由於介電層材質特性及製造技術的限 制，將使介電層的厚度受限於某一最低値。 習知DRAM電容器介電層的製造方法，是以0N0 (Oxide-Nitride -·Όχ ide，氧化層-氮化層-氧化層）的型 式來形成，其中與電容器的複晶矽儲存電極（Storage Electrode)接觸的氧化層是爲原生氧化層（Native Oxide)，之後再於原生氧化層上沈積氮化矽層和氧化層， 隨後再沈積一上電極（Upper Elecuodf) ’來達到形成 DRAM電容器的目的。 由於複晶矽儲存電極表面會有原生氧化層存在，而原 生氧化層在室溫下即會生成，無法做告效地去除 3 本紙张尺度‘5中國围家標埤(Fns] Λ4祕（2丨0X297公h ~^ (請先閱讀背面之注意事Γ'4·寫本頁) -裝. 訂 線 408426 4259twf.doc/006 A 7 ___B7 五、發明説明（工） 化層的介電常數比氮化矽層小，所以原生氧化層的存在， 會使得ΟΝΟ介電膜層的有效介電常數無法做有效地減小。 因此，本發明提供一種動態隨機存取記憶體電容器之 介電膜層的製造方法，適用於表面有原生氧化層的儲存電 極，其製造方法包括：將製程壓力控制在小於ΙίΤ5托爾下，' 進行一快速升溫製程，以剝除原生氧化層，接著進行氮化 反應，以於儲存電極表面形成第一介電層，再於第一介電 層上形成氮化矽層。 依照本發明的一較佳實施例，其中快速升溫製程的起 始溫度約爲攝氏450至550度，升溫速度爲每分鐘溫度上 升約攝氏80至120度，終止溫度約爲攝氏700至850度。 其中氮化反應的條件包括：製程氣體爲氨氣，製程溫度約 爲攝氏700至850度，所需的製程時間約爲10至60分鐘。 而第一介電層的材質包括氮化砂和氮氧化砂二者擇一。此 外，更包括於氮化矽層上形成一氧化層，其形成方法包 括：於一氧化二氮、氧氣、或一氧化二氮/氧氣的環境下 進行快速熱製程。闼此本發明所形成之介電膜層的結構有 NO (氮化砂層-氧化層）和Ν (氮化砂層）兩種。 +由於本發明利用快速升溫製程來去除原生氧化層’其 所需的時間甚短，使晶片不致久置於高溫中’故可以有較 低的熱預算。再者，並於已剝除原生氧f層的複晶矽儲存 電極表面進行氮化反應，以避免原生氧化層的再次形成° 因此本發明之電容器介電膜層的製造方法’能夠在不影響 介電膜層性質的情況下，將原生氧化層完全去除’以增加 4 ’本紙張尺度鸿疋中國15家^ ( CNS ) Λ4規格0X297公釐） 經漓部十次梂準局只T;消介合竹社印犁 408426 4259twf.doc/006 A 7 _____B7_ 五、發明説明（> ) — 介電膜層的有效介電常數，使電容器單位面積所能儲存的 電荷數增加。 本發明提供一種剝除複晶矽表面之原生氧化層的方 法，其方法包括：將製程壓力控制在小於10_5托爾下，進 行一快速扞溫製程，其中該快速升溫製程的起始溫度約爲 攝氏450至550度，升溫速度約爲每分鐘溫度上升約攝氏 80至120度，終止溫度約爲攝氏700至850度。 由於本發明利用快速升溫製程來去除原生氧化層，其 所需的時間甚短，使晶片不致久置於高溫中，故可以有較 低的熱預算。因此本發明之電容器介電膜層的製造方法， 能夠在不影響介電膜層性質的情況下，將原生氧化層完全 去除，以增加介電膜層的有效介電常數，使電容器單位面 積所能儲存的電荷數增加。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1F圖係繪示根據本發明一較佳實施例之 一種動態隨機存取記憶體之電容器介電膜層的製造流程 剖®圖。 其中，各圖標號與構件名稱之關係如下： .100 :基底 102 :源極/汲極區 104 _金氧半電晶體 5 本紙張尺度递疋中國囤家摞埤("cns ) \ 210X297^^1 —~~~ <讀先閱讀背面之注意事填寫本頁} 裝 -. Je 4259twf.doc/006 408426 勉淋—部十央標準：？貝T;消抡合作社印絮 A7 B7 . ______ 五、發明説明（^ ) 106 :絕緣層 108 :儲存電極 ηο :原生氧化層 112 :氮化矽層或氮氧化矽層 114 ^氮化矽層 116 :氧化層 118 :導電層（上電極） 實施例 第1Α圖至第1F圖所示，爲根據本發明一較佳實施例 之一種動態隨機存取記憶體電容器之介電膜層的製造流 程剖面圖。 首先請參照第1Α圖，提供基底100，電容器的儲存電 極108穿越絕緣層106與M0S電晶體104的源極/汲極區 102之一相接觸，其中此儲存電極108的材質比如爲複晶 矽，此儲存電極108可以是半球形矽晶粒（HSG)結構， 爲方便圖示，在此以簡單的柱形爲例。由於複晶矽儲存電 極108在沈積完後...，在含氧的環境中，其表面會與周圍的 氧起氧化反應，此反應在室溫下即會進行，因而形成一薄 薄的二氧化矽，稱爲原生氧化層110。 .接著請參照第1Β圖，由於氧化物的介電常數比氮化 物低，爲了使電容器之介電膜層有較高的介電常數，因此 本發明在形成氮化矽層之前，先將複晶&儲存電極108表 面的原生氧化層110完全剝除，其方法爲在壓力約小於1〇^ 托爾之高真空度，且在起始溫度約爲攝氏450度至攝氏550 6 本紙張从“巾關雜彳(— C’NS ) /\4胁（210X297公敛） _ 一 (請先閲讀背面之注意事哼-ft,填寫本頁) -裝· -線. 408426 4259twf.doc/006 經濟部屮次梂準扃负工消此合作社印絮 五、發明説明（5 ) 度的反應室中，進彳了快速升溫（Fas t Ramp )製程，以利 於下式反應的進行： S|〇2(s) + Si — SiO(it) 其中快速升溫製程的升溫速度約爲攝氏80至120度/分 鐘’而終It溫度約爲攝氏700至850度。由於反應的產物 SiO⑴是爲氣體，因此可以藉由真空幫浦抽離反應室。根據 勒沙特列原理，當產物不斷地被抽離，則上式的反應式會 不斷地向右進行，而且隨著溫度的上升，反應速率亦會增 快，於是可以將複晶矽儲存電極108表面的原生氧化層110 完全剝除，而且所需的時間甚短，約1分鐘至5分鐘左右° 由於本發明利用快速升溫製程來進行原生氧化層的 剝除，且所需的時間甚短，使整個基底100結構在高溫的 環境下不會置放過久，因此可以有較低的熱預算（Thermal Budget ) ° 接著請參照第1C圖，於已去除原生氧化層110的複 晶矽儲存電極108表面進行氮化反應（Nitridation)， 以抑制原生氧化層的再次成長，於是於複晶矽儲存電極 108表面形成一薄層的氮化矽（SiN«)層或氮氧化矽 (SiO,Nz)層112。氮化反應進行的條件包括溫度約爲攝氏 700至850度左右，製程氣體爲氨氣（仙〇，反應進行的 時間約爲10分鐘至60分鐘左右。 .當進行完原生氧化層110的剝除後'，係在同一個反應 室中進行氮化反應，如需更換不同反應室進行氮化反應 時，則在傳輸晶片的過程中須維持在無氧的狀態。 7 本紙乐尺度诚^中圇囤家榡埤(C'NS") A4^ ( 210X297^^ ) ^ (对先閲讀背面之項界填寫本I ) .裝. 訂 線 408426 4259twf.doc/006 _______ _ ____B7_ 五、發明説明（6) 接著請參照第ID圖，之後於氮化矽層或氮氧化矽層 112上方形成一層氮化矽層114。其形成方法比如以SiH2Ch 和氨氣爲製程氣體，在爐管中進行反應；以SiCh和氨氣 爲製程氣體，在爐管中進行反應；或以SiH2C12和氨氣爲 製程氣體％進行快速熱製程。 接著請參照第1E圖，進行快速熱製程，用以於氮化 矽層114表面形成一層氧化層116，其製程氣體比如是一 氧化二氮（N2〇)、氧氣二者擇一，或者是一氧化二氮和氧 氣兩者的混合等。.此層氧化層116可以降低氮化矽層114 的缺陷，由於使用快速熱製程成長氧化層116,因此可以 有較低的熱預算，且由於所需的時間短，所形成之氧化層 116不會太厚，並可避免製程氣體擴散至氮化矽層114和 複晶矽儲存電極108的界面處，故亦可避免於氮化矽層114 和複晶矽儲存電極108之間形成氧化物。 另外，以SiCh和氨氣爲製程氣體，在爐管中進行反 應所形成之氮化矽層114有較平滑的表面，且有較少的 Si-H鍵，所以可以不須再於其上方形成一層氧化層116來 降低氮化砂層1Η的缺陷，因此可以減少一道氧化層116 的嵌成步驟。 .本發明所形成之電容器的介電膜層爲NO (氮化矽層-氧化層）或N (氮化矽層）的結構’由p已有效地去除原 生氧化層，故可以提高介電膜層的有效介電常數’因此增 加電容器儲存電荷的能力。且在去除原生氧化層的過程’ 有較小的熱預算’故可以避免所形成的元件受到傷害。Random Access Memory (DRAM) capacitor (Capacitor) manufacturing method of the dielectric layer (Dielectric Layer) method, and in particular relates to a method to increase the capacitor's ability to store charge. A single transistor DRAM cell is composed of a metal-oxide semiconductor and a capacitor, and the capacitor is the heart part of the DRAM cell to store the signal. If the capacitor stores more charge, the read amplifier will read the data The influence of noise will be greatly reduced, and the frequency of " Refresh " will be reduced. The methods to increase the capacity of the capacitor to store charge are: (1) increase the area of the capacitor, so that the total amount of charge stored in the capacitor increases, but this will reduce the integration of the DRAM (Integration); (2) choose the appropriate dielectric Layer material to increase the dielectric constant of the dielectric layer, so that the number of charges that can be stored per unit area of the capacitor increases; (3) reduce the thickness of the dielectric layer, but due to the material characteristics of the dielectric layer and manufacturing technology limitations, the dielectric The thickness of the electrical layer is limited to a certain minimum thickness. The conventional manufacturing method for the dielectric layer of a DRAM capacitor is formed by a type of 0N0 (Oxide-Nitride- · χχ ide, oxide layer-nitride layer-oxide layer). The contact oxide layer is a native oxide layer, and then a silicon nitride layer and an oxide layer are deposited on the native oxide layer, and then an upper electrode (Upper Elecuodf) is deposited to achieve the purpose of forming a DRAM capacitor. Since the primary silicon oxide layer exists on the surface of the polycrystalline silicon storage electrode, and the primary oxide layer will be generated at room temperature, it cannot be effectively removed. 3 paper size '5 Chinese enclosure standard 埤 (Fns) Λ4 secret (2丨 0X297 male h ~ ^ (Please read the note on the back Γ'4 · Write this page first)-Binding. 408426 4259twf.doc / 006 A 7 ___B7 V. The dielectric constant ratio of the invention (industrial) layer The silicon nitride layer is small, so the existence of the native oxide layer will make the effective dielectric constant of the ONO dielectric film layer cannot be effectively reduced. Therefore, the present invention provides a dielectric film layer of a dynamic random access memory capacitor. The manufacturing method is suitable for a storage electrode with a native oxide layer on the surface. The manufacturing method includes: controlling the process pressure to less than ΙΤΤ5 Torr, and performing a rapid heating process to strip the native oxide layer, followed by a nitriding reaction. In order to form a first dielectric layer on the surface of the storage electrode, and then form a silicon nitride layer on the first dielectric layer. According to a preferred embodiment of the present invention, the starting temperature of the rapid heating process is about 450 to celsius. 550 degrees, heating up The temperature is about 80 to 120 degrees Celsius per minute, and the termination temperature is about 700 to 850 degrees Celsius. The nitriding reaction conditions include: the process gas is ammonia, and the process temperature is about 700 to 850 degrees Celsius. The processing time is about 10 to 60 minutes. The material of the first dielectric layer includes one of nitride sand and oxynitride sand. In addition, it further includes forming an oxide layer on the silicon nitride layer, and a forming method thereof includes: The rapid thermal process is performed under the environment of nitrous oxide, oxygen, or nitrous oxide / oxygen. The structure of the dielectric film layer formed by the present invention includes NO (nitrided sand layer-oxide layer) and N (nitrogen) (Sand layer) two kinds. + Because the present invention uses a rapid heating process to remove the native oxide layer 'it takes very short time, so that the wafer will not be placed in high temperature for a long time', so it can have a lower thermal budget. Furthermore, and The nitriding reaction is performed on the surface of the polycrystalline silicon storage electrode from which the native oxygen f layer has been stripped to avoid the re-formation of the native oxide layer. Therefore, the manufacturing method of the capacitor dielectric film layer of the present invention can not affect the dielectric film layer. Case of nature Completely remove the native oxide layer to increase the size of the paper. 15 Chinese companies ^ (CNS) Λ4 size 0X297 mm) Ten times by the Ministry of Standards, only T; Consumer Media Co., Ltd. Bamboo Plough 408426 4259twf. doc / 006 A 7 _____B7_ 5. Explanation of the invention (>) — The effective dielectric constant of the dielectric film layer increases the number of charges that can be stored per unit area of the capacitor. The invention provides a method for stripping the primary oxidation of the surface of the polycrystalline silicon The method includes: controlling the process pressure to less than 10_5 Torr, and performing a rapid temperature-preserving process, wherein the starting temperature of the rapid heating process is about 450 to 550 degrees Celsius, and the heating rate is about a temperature per minute The rise is about 80 to 120 degrees Celsius, and the end temperature is about 700 to 850 degrees Celsius. Since the present invention uses a rapid heating process to remove the native oxide layer, the time required is very short, so that the wafer is not exposed to high temperatures for a long time, so it can have a lower thermal budget. Therefore, the manufacturing method of the capacitor dielectric film layer of the present invention can completely remove the native oxide layer without affecting the properties of the dielectric film layer, so as to increase the effective dielectric constant of the dielectric film layer and make the unit area of the capacitor smaller. The number of charges that can be stored increases. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A to FIG. 1F is a cross-sectional view illustrating a manufacturing process of a capacitor dielectric film layer of a dynamic random access memory according to a preferred embodiment of the present invention. Among them, the relationship between each icon number and the component name is as follows: .100: substrate 102: source / drain region 104 _metal oxide semi-transistor 5 This paper is reprinted in China (" cns) \ 210X297 ^ ^ 1 — ~~~ < Read the notes on the back and fill in this page} Pretend-. Je 4259twf.doc / 006 408426 Mianlin—Ministry Central Standard :? T: A7 B7 of Consumer Cooperatives. ______ V. Description of the Invention (^) 106: Insulating layer 108: Storage electrode ηο: Native oxide layer 112: Silicon nitride layer or silicon oxynitride layer 114 ^ Silicon nitride layer 116 : Oxide layer 118: conductive layer (upper electrode) FIG. 1A to FIG. 1F of the embodiment are cross-sections of a manufacturing process of a dielectric film layer of a dynamic random access memory capacitor according to a preferred embodiment of the present invention Illustration. First, referring to FIG. 1A, a substrate 100 is provided. The storage electrode 108 of the capacitor passes through the insulating layer 106 and contacts one of the source / drain regions 102 of the MOS transistor 104. The material of the storage electrode 108 is, for example, polycrystalline silicon. The storage electrode 108 may have a hemispherical silicon grain (HSG) structure. For convenience of illustration, a simple pillar shape is used as an example here. After the deposition of the polycrystalline silicon storage electrode 108 ... in an oxygen-containing environment, its surface will oxidize with the surrounding oxygen, and this reaction will proceed at room temperature, thus forming a thin Silicon oxide is called a native oxide layer 110. Next, please refer to FIG. 1B. Since the dielectric constant of the oxide is lower than that of the nitride, in order to make the dielectric film layer of the capacitor have a higher dielectric constant, the present invention The primary oxide layer 110 on the surface of the crystal & storage electrode 108 is completely peeled off by using a high vacuum at a pressure of about less than 10 ^ Tor and a starting temperature of about 450 ° C to 550 ° C. "Jiang Guan Zai (— C'NS) / \ 4 threat (210X297)" _ one (please read the note on the back first -ft, fill out this page) -install · -line. 408426 4259twf.doc / 006 The Ministry of Economic Affairs and the Ministry of Economic Affairs of the People's Republic of China have voluntarily eliminated the print of this cooperative. 5. In the reaction chamber with a description of (5) degrees, a rapid heating (Fast t Ramp) process has been performed to facilitate the reaction of the following formula: S | 〇 2 (s) + Si — SiO (it) where the heating rate of the rapid heating process is about 80 to 120 ° C / min 'and the final It temperature is about 700 to 850 ° C. Since the reaction product SiO⑴ is a gas, so The reaction chamber can be evacuated by vacuum pumping. According to Le Chatelier's principle, when the product is continuously evacuated, The reaction formula above will continue to the right, and the reaction rate will increase as the temperature rises, so the primary oxide layer 110 on the surface of the polycrystalline silicon storage electrode 108 can be completely stripped, and the time required Very short, about 1 minute to 5 minutes. As the invention uses a rapid heating process to strip the native oxide layer, and the time required is very short, the entire substrate 100 structure will not be placed in a high temperature environment. For a long time, it is possible to have a lower thermal budget. Then, referring to FIG. 1C, perform a nitridation on the surface of the polycrystalline silicon storage electrode 108 from which the native oxide layer 110 has been removed to suppress the native oxide layer. Growth of silicon, a thin layer of silicon nitride (SiN «) layer or silicon oxynitride (SiO, Nz) layer 112 is formed on the surface of the polycrystalline silicon storage electrode 108. The conditions for the nitridation reaction include a temperature of about 700 ° C To about 850 degrees, the process gas is ammonia (sen0, the reaction time is about 10 minutes to about 60 minutes. After the stripping of the primary oxide layer 110 ', nitrogen is carried out in the same reaction chamber Chemical reaction, if different reaction chambers need to be replaced for nitriding reaction, it must be maintained in an oxygen-free state during the process of transferring wafers. 7 This paper is a good standard ^ 囵 中 囵 家家 (C'NS ") A4 ^ ( 210X297 ^^) ^ (Fill in the I field on the back of the book first, fill in this I). Binding. 408426 4259twf.doc / 006 _______ _ ____B7_ V. Description of the invention (6) Then please refer to the figure ID, and then the silicon nitride A layer of silicon nitride 114 is formed on the layer or the silicon oxynitride layer 112. Its formation method, for example, uses SiH2Ch and ammonia as the process gas to perform the reaction in the furnace tube; uses SiCh and ammonia as the process gas to perform the reaction in the furnace tube; or uses SiH2C12 and ammonia as the process gas% for the rapid thermal process. . Next, referring to FIG. 1E, a rapid thermal process is performed to form an oxide layer 116 on the surface of the silicon nitride layer 114. The process gas is, for example, nitrous oxide (N20), oxygen, or one Mixing of both nitrous oxide and oxygen. This layer of oxide layer 116 can reduce the defects of the silicon nitride layer 114. Since the oxide layer 116 is grown using a rapid thermal process, a lower thermal budget can be achieved, and because the required time is short, the oxide layer 116 is not formed. It will be too thick, and the process gas can be prevented from diffusing to the interface between the silicon nitride layer 114 and the polycrystalline silicon storage electrode 108. Therefore, an oxide can also be prevented from being formed between the silicon nitride layer 114 and the polycrystalline silicon storage electrode 108. In addition, the silicon nitride layer 114 formed by using SiCh and ammonia as a process gas and reacting in the furnace tube has a smoother surface and fewer Si-H bonds, so it is not necessary to form over it. An oxide layer 116 is used to reduce the defects of the nitrided sand layer 1Η. Therefore, an embedding step of the oxide layer 116 can be reduced. The dielectric film layer of the capacitor formed by the present invention has a structure of NO (silicon nitride layer-oxide layer) or N (silicon nitride layer). The p-oxide layer has been effectively removed by p, so the dielectric film can be improved. The effective dielectric constant of the layer 'therefore increases the capacitor's ability to store charge. And in the process of removing the native oxide layer, ‘there is a smaller thermal budget’ so that the formed elements can be prevented from being harmed.
S I-im xSJ?((，阽}/\4規招{210乂297公芨) 408426S I-im xSJ? ((, 阽) / \ 4 规 招 {210 乂 297 公 芨) 408426
Pj A 部 Ί· 樣 卑 ! fl ii 印 4259twf.doc/006 A/ _ B7___ 五、發明説明（9) 接著請參照第1F圖.，於介電膜層上方覆蓋一層導電 層118，做爲電容器的上電極之用。其中導電層的材質包 括摻雜的複晶矽、氮化鈦（TiN) /摻雜的複晶矽、氮化鎢 (WN) /摻雜的複晶矽、氮化鉬（TaN) /摻雜的複晶矽等。 如果使用氮化鈦/摻雜的複晶矽、氮化鎢/摻雜的複晶矽、 氮化鉬/摻雜的複晶矽做爲上電極，配合本發明的介電膜 層，於電容器操作的過程中，可以有效抑制空乏 (Depletion)現象的發生，且其電容-電壓曲線與以五氧 化二鉅（Ta2〇s)爲介電膜層的MIS (金屬層-絕緣層-複晶 '矽層）結構相同，而且所組成的電容器之電容器量會大於 2 fF/ce 11。 本發明的特徵如下： (1) 本發明剝除複晶矽儲存電極表面之原生氧化層的 方法包括在真空度約高於10·5托爾，且在起始溫度約爲攝 氏450至550度的環境下，進行快速升溫製程。其中升溫 的速度約爲攝氏80至120度/分鐘，終止溫度約爲攝氏700 至850度。 (2) 由於本發明利用快速升溫製程來去除原生氧化 層'，其所需的時間甚短，使晶片不致久置於高溫中，故可 以有較低的熱預算。 (3) 本發明於已剝除原生氧化層的複晶矽儲存電極表 面進行氮化反應，以避免原生氧化層的^次形成。 (4) 使用氮化鈦/摻雜的複晶矽、氮化鎢/摻雜的複晶 矽、氮化钽/摻雜的複晶矽做爲上電極，配合本發明的介Pj A Ί Ί 卑 卑! Fl ii printed 4259twf.doc / 006 A / _ B7___ V. Description of the invention (9) Then refer to Figure 1F. Cover the dielectric film layer with a conductive layer 118 as a capacitor The use of the upper electrode. The material of the conductive layer includes doped polycrystalline silicon, titanium nitride (TiN) / doped polycrystalline silicon, tungsten nitride (WN) / doped polycrystalline silicon, molybdenum nitride (TaN) / doped Polycrystalline silicon and so on. If titanium nitride / doped complex silicon, tungsten nitride / doped complex silicon, or molybdenum nitride / doped complex silicon are used as the upper electrode, the dielectric film layer of the present invention is used in a capacitor. During the operation, it can effectively suppress the occurrence of depletion, and its capacitance-voltage curve and MIS (metal layer-insulation layer-multicrystal) with a dielectric layer of pentoxide (Ta20s) as its dielectric layer Silicon layer) structure is the same, and the capacitor capacity of the capacitor will be greater than 2 fF / ce 11. The features of the present invention are as follows: (1) The method for stripping the native oxide layer on the surface of the polycrystalline silicon storage electrode according to the present invention includes a vacuum degree higher than about 10 · 5 Torr, and a starting temperature of about 450 to 550 degrees Celsius. Under the environment, the rapid heating process is performed. The rate of temperature increase is about 80 to 120 ° C / min, and the end temperature is about 700 to 850 ° C. (2) Since the present invention uses a rapid temperature rise process to remove the native oxide layer, the time required is very short, so that the wafer is not exposed to high temperature for a long time, so it can have a lower thermal budget. (3) The present invention performs a nitriding reaction on the surface of the polycrystalline silicon storage electrode from which the native oxide layer has been stripped to avoid the formation of the native oxide layer. (4) Titanium nitride / doped complex silicon, tungsten nitride / doped complex silicon, and tantalum nitride / doped complex silicon are used as the upper electrodes.
訂 線 本紙相彳，關丨料（CNS)A4^ ( 210X297^-f.~) 40842β 4259twf.doc/006 Α7 Β7 五、發明説明（》） . 電膜層，於電容器操作的過程中，可以有效抑制空乏現象 的產生。 (5) 使用氮化鈦/摻雜的複晶矽、氮化鎢/摻雜的複晶 矽、氮化鉬/摻雜的複晶矽做爲上電極，配合本發明的介 電膜層，所獲得的電容-電壓曲線與以Ta2〇5爲介電膜層的 ΜIS結構相同。 (6) 使用氮化鈦/摻雜的複晶矽、氮化鎢/摻雜的複晶 矽、氮化鉅/摻雜的複晶矽做爲上電極，配合本發明的介 電膜層所組成的電容器，其電容器量會大於2 fF/cell。 .雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (誚先閱讀背面之注意事ϊιι-χ^'寫本頁) 裝 _線_ 部 而 J3 j 消 f: 竹 印 10 本紙汰尺度滴)彳1中K段家( rNS ) Λ4規梠（210X297公釐）Binding paper and paper, related materials (CNS) A4 ^ (210X297 ^ -f. ~) 40842β 4259twf.doc / 006 Α7 Β7 V. Description of the invention ("). The electric film layer can be used in the capacitor operation process. Effectively suppress the occurrence of emptyness. (5) using titanium nitride / doped polycrystalline silicon, tungsten nitride / doped polycrystalline silicon, molybdenum nitride / doped polycrystalline silicon as the upper electrode, with the dielectric film layer of the present invention, The obtained capacitance-voltage curve is the same as the MIS structure with Ta205 as the dielectric film layer. (6) Titanium nitride / doped polycrystalline silicon, tungsten nitride / doped polycrystalline silicon, and nitride / doped polycrystalline silicon are used as the upper electrode, and are matched with the dielectric film layer of the present invention. The amount of capacitor will be greater than 2 fF / cell. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the note on the back first ϊι-χ ^ 'to write this page) Install _ Line _ Buer J3 j No. f: Bamboo Seal 10 Paper Paper Standard Drop) K1 K Section Home (rNS) Λ4 Regulations (210X297 Mm)