TW333683B - The improving processes for DRAM capacitor - Google Patents

Abstract

An improving process for DRAM capacitor, it includes following steps: (a) Provide a semiconductor substrate, which has already formed transistor that includes gate, source/drain and a planarization layer to cover on transistor. (b) Form contact opening in planarization layer, to expose the drain region of transistor. (c) Form 1st conductive layer to fill contact opening and extend to cover on planarization surface. (d) Serially form dielectric and 2nd conductive layer on 1st conductive surface. (e) Selectively etch 2nd conductive layer, dielectric and 1st conductive layer till the planarization surface, and simultaneously define the pattern of storage node and cell plate, to form capacitor structure. (f) Form insulating layer on capacitor structure and planarization surface, and form connect opening inside to expose cell plate of capacitor structure. (g) Form 3rd conductive layer to fill connect opening and cover on insulating surface, and define the pattern to form interconnect, to finish the DRAM capacitor structure.