TW289860B - Process for bottom plate of DRAM stacked capacitor - Google Patents

Abstract

A process for bottom plate of DRAM stacked capacitor, in which the stacked capacitor is formed on one silicon substrate and in sequence has one SiO2 layer, one bottom silicon plate consisting of polysilicon, one dielectric layer and one top plate, comprises the steps of: (1) depositing one first polysilicon on the SiO2 layer; (2) doping the first polysilicon; (3) activating the doped first polysilicon; (4) depositing one second polysilicon on the activated and doped first polysilicon; (5) doping the second polysilicon; (6) activating the doped second polysilicon; (7) with phosphoric acid etching the activated and doped second polysilicon, therefore forming one bottom plate consisting of polysilicon with rugged surface.