TW255058B - Process of DRAM capacitor - Google Patents

Abstract

A process of DRAM capacitor includes the following steps: (1) forming filed oxide layer needed to isolate active region; (2) forming transistor; (3) continuously depositing the first insulator and the second insulator; (4) by reactive ion etching technique defining the pattern of the first insulator and the second insulator to form cell contact; (5) continuously depositing the first polysilicon layer and the third insulator; (6) by reactive ion etching technique anisotropically etching the third insulator and partial the first polysilicon layer till some depth; (7) forming the forth insulator, i.e. SiO2; (8) by reactive ion etching technique anisotropically etching back the forth insulator and stopping until the first polysilicon layer is etched to the surface of some depth to form spacer; (9) with the spacer as etchmask, by reactive ion etching technique anisotropically etching the remaining part of the first polysilicon layer and stopping at the second insulator; (10) by hot phosphate etching liquid removing the third insulator, by the hydrofluoric acid liquid removing the spacer; (11) forming capacitor dielectric layer on the storage node surface of capacitor; (12) depositing one second polysilicon layer and defining its pattern by reactive ion etching technique as the top plate of capacitor.