本技術係關於資料處理領域。This technology relates to the field of data processing.
資料處理系統可具有位址轉譯電路系統，以將記憶體存取請求的一虛擬位址轉譯成對應於待在一記憶體系統中存取之一位置的一實體位址。Data processing systems may have address translation circuitry to translate a virtual address of a memory access request into a physical address corresponding to a location to be accessed in a memory system.
至少一些實例提供一種設備，其包含： 位址轉譯電路系統，其用以將一記憶體存取請求的一目標虛擬位址轉譯成一目標實體位址；及 屬性判定電路系統，其用以使用經轉譯的該目標實體位址來判定與該目標實體位址相關聯的屬性資訊； 其中該屬性判定電路系統經組態以： 使用該目標實體位址識別一實體定址表結構的一對應項，及 從一組屬性儲存位置中的一給定屬性儲存位置判定該屬性資訊，該給定屬性儲存位置由該實體定址表結構的該對應項指示的一索引來識別。At least some embodiments provide a device comprising:Address translation circuitry for translating a target virtual address of a memory access request into a target physical address; andAttribute determination circuitry for using the translated target physical address to determine attribute information associated with the target physical address;Wherein, the attribute determination circuitry is configured to:Use the target physical address to identify a corresponding entry in a physical address table structure; andDetermine the attribute information from a given attribute storage location in a set of attribute storage locations, the given attribute storage location being identified by an index indicated by the corresponding entry in the physical address table structure.
至少一些實例提供一種方法，其包含： 將一記憶體存取請求的一目標虛擬位址轉譯成一目標實體位址；及 使用該經轉譯目標實體位址來判定與該目標實體位址相關聯的屬性資訊； 其中判定該屬性資訊包含： 使用該目標實體位址識別一實體定址表結構的一對應項；及 從一組屬性儲存位置中的一給定屬性儲存位置判定該屬性資訊，該給定屬性儲存位置由該實體定址表結構的該對應項指示的一索引來識別。At least some embodiments provide a method comprising:translating a target virtual address of a memory access request into a target physical address;using the translated target physical address to determine attribute information associated with the target physical address;wherein determining the attribute information comprises:using the target physical address to identify a corresponding entry in a physical address table structure; anddetermining the attribute information from a given attribute storage location in a set of attribute storage locations, the given attribute storage location being identified by an index indicated by the corresponding entry in the physical address table structure.
至少一些實例提供一種電腦可讀取媒體，其用以儲存用於製造上文所描述之設備的電腦可讀取碼。At least some examples provide a computer-readable medium for storing computer-readable code for making the apparatus described above.
至少一些實例提供一種包含指令的電腦程式，當該等指令由一主機資料處理設備執行時，控制該主機資料處理設備提供用於執行目標程式碼的一指令執行環境，該電腦程式包含： 位址轉譯程式邏輯，其用以將一記憶體存取請求的一目標虛擬位址轉譯成一目標經模擬實體位址；及 屬性判定程式邏輯，其用以使用該經轉譯目標經模擬實體位址來判定與該目標經模擬實體位址相關聯的屬性資訊； 其中該屬性判定程式邏輯經組態以： 使用該目標經模擬實體位址識別一實體定址表結構的一對應項，及 從一組屬性儲存位置中的一給定屬性儲存位置判定該屬性資訊，該給定屬性儲存位置由該實體定址表結構的該對應項指示的一索引來識別。At least some embodiments provide a computer program comprising instructions that, when executed by a host data processing device, controls the host data processing device to provide an instruction execution environment for executing target program code. The computer program comprises:Address translation program logic for translating a target virtual address of a memory access request into a target emulated physical address; andAttribute determination program logic for using the translated target emulated physical address to determine attribute information associated with the target emulated physical address;Wherein, the attribute determination program logic is configured to:Using the target simulated physical address, a corresponding entry of a physical address table structure is identified, and the attribute information is determined from a given attribute storage location in a set of attribute storage locations, the given attribute storage location being identified by an index indicated by the corresponding entry of the physical address table structure.
一種儲存媒體可儲存上文提及的該電腦程式。該儲存媒體可係一非暫時性儲存媒體。A storage medium can store the computer program mentioned above. The storage medium can be a non-transitory storage medium.
資料處理系統可支援虛擬記憶體的使用，其中提供位址轉譯電路系統以將由記憶體存取請求指定的虛擬位址轉譯成與記憶體系統中之待存取的位置相關聯的目標實體位址。位址轉譯電路系統可例如包含與處理器相關聯的記憶體管理單元中的一者；及與至少一個裝置相關聯的系統記憶體管理單元，該至少一個裝置包含至少一個硬體加速器及/或至少一個輸入/輸出裝置。A data processing system may support the use of virtual memory, wherein address translation circuitry is provided to translate a virtual address specified by a memory access request into a target physical address associated with a location to be accessed in the memory system. The address translation circuitry may, for example, include one of a memory management unit associated with a processor; and a system memory management unit associated with at least one device including at least one hardware accelerator and/or at least one input/output device.
虛擬位址與實體位址之間的映射可在一或多個虛擬定址頁表（轉譯表）結構中定義。頁表結構內的頁表項亦可定義可控制是否允許在處理電路系統上執行的給定軟體程序存取特定虛擬位址的一些存取權限資訊。在一些處理系統中，對特定軟體程序是否可存取特定位址的控制可僅基於用以提供虛擬至實體位址轉譯映射的頁表結構提供。The mapping between virtual addresses and physical addresses can be defined in one or more virtual addressing page table (translation table) structures. Page table entries within these structures can also define certain access permission information that controls whether a given software program running on the processing system is allowed to access a particular virtual address. In some processing systems, control over whether a particular software program can access a particular address can be based solely on the page table structures used to provide the virtual-to-physical address mapping.
然而，對於一些敏感的處理工作負載，可能所欲的係提供比僅用虛擬定址轉譯表所能提供的額外安全性。由於用以定義位址映射及屬性的轉譯表結構一般由作業系統或超管理器控制，因此存在如下風險：若攻擊者設法損害作業系統或超管理器，則由轉譯表結構定義的存取權限屬性可能不足以為此類敏感工作負載提供足夠的安全保證。若作業系統或超管理器受損害，則此可導致可使敏感資訊變為可由攻擊者存取的安全性漏洞。However, for some sensitive processing workloads, it may be desirable to provide additional security beyond what a virtual address translation table alone can offer. Because the translation table structure that defines address mappings and attributes is typically controlled by the operating system or hypervisor, there is a risk that if an attacker manages to compromise the operating system or hypervisor, the access permission attributes defined by the translation table structure may not be sufficient to provide adequate security for such sensitive workloads. If the operating system or hypervisor is compromised, this can lead to security vulnerabilities that could make sensitive information accessible to the attacker.
因此，在一些系統中，可能所欲的係定義另一組屬性資訊以控制是否允許記憶體存取請求存取目標實體位址，而不受作業系統或超管理器的控制。因此，提供屬性判定電路系統以使用實體定址表結構來判定與目標實體位址相關聯的屬性資訊。藉由在實體定址表（基於實體位址查找的表，且因此獨立於用以提供從虛擬位址到實體位址之映射的轉譯表結構）中定義屬性資訊，可提供超出由作業系統或超管理器控制的安全層之外的附加安全層，以降低攻擊者可能導致對敏感處理工作負載使用的某些實體位址進行不當存取的風險。Therefore, in some systems, it may be desirable to define another set of attribute information to control whether a memory access request is allowed to access a target physical address, without being controlled by the operating system or hypervisor. Therefore, attribute determination circuitry is provided to use a physical address table structure to determine attribute information associated with a target physical address. By defining attribute information in a physical address table (a table that is based on physical address lookups and is therefore independent of a translation table structure used to provide mappings from virtual addresses to physical addresses), an additional layer of security beyond that controlled by the operating system or hypervisor can be provided to reduce the risk that an attacker may cause improper access to certain physical addresses used by sensitive processing workloads.
應理解，可存在與目標實體位址相關聯之屬性資訊的許多不同實例，該等實例在記憶體存取請求的處理期間可能係相關的。雖然下面將更詳細地論述各種選項，但屬性資訊可包括識別可存取特定目標實體位址的實體位址空間、可從其存取目標實體位址的處理域、可從其存取實體位址的請求者裝置、目標實體位址係在由記憶體標籤保護的區域內或在儲存記憶體標籤的區域內的指示、及讀取/寫入權限的資訊。應理解，該列表係非窮舉的，且通常屬性資訊可定義與實體位址相關聯的資訊，該資訊可與判定是否允許存取請求存取該實體位址相關。It should be understood that there may be many different instances of attribute information associated with a target physical address that may be relevant during the processing of a memory access request. While various options are discussed in greater detail below, the attribute information may include information identifying the physical address space from which a particular target physical address may be accessed, the processing domain from which the target physical address may be accessed, the requestor device from which the physical address may be accessed, an indication that the target physical address is within an area protected by a memory tag or within an area where a memory tag is stored, and read/write permission information. It should be understood that this list is non-exhaustive and that generally attribute information may define information associated with a physical address that may be relevant in determining whether an access request is allowed to access the physical address.
在一些使用實體定址表結構來識別屬性資訊的系統中，屬性判定電路系統可直接從對應於目標實體位址之實體定址表結構的項讀取屬性資訊。例如，實體定址表結構的各項可對應於共用相同屬性資訊的實體位址顆粒，且對應項係對應於包含目標實體位址之實體位址顆粒的項。接著，屬性資訊可直接使用，或可經快取，直到在記憶體存取期間其需要被使用為止。In some systems that use a physical address table structure to identify attribute information, the attribute determination circuitry can read the attribute information directly from the entry in the physical address table structure that corresponds to the target physical address. For example, each entry in the physical address table structure can correspond to physical address granules that share the same attribute information, and the corresponding entry is the entry corresponding to the physical address granule that contains the target physical address. The attribute information can then be used directly or cached until it is needed during a memory access.
然而，本發明人已經認識到，給定可由屬性資訊表示的潛在大量相異資訊，若實體定址表結構要直接指定各項中的屬性資訊，則實體定址表結構的大小可能會變得非所欲地大，且表的儲存及使用可與大的開銷相關聯。另外，本發明人認識到，在可更新屬性資訊的情形下，針對各項分開更新屬性資訊可能產生大的開銷。However, the inventors have recognized that, given the potentially large amount of different information that can be represented by attribute information, if the entity address table structure were to directly specify the attribute information in each entry, the size of the entity address table structure could become undesirably large, and the storage and use of the table could be associated with significant overhead. Furthermore, the inventors have recognized that, in the case of updateable attribute information, updating the attribute information separately for each entry could incur significant overhead.
本發明人亦認識到，儘管屬性資訊的編碼可能存在大量選項，但實際上，一些編碼比其他編碼使用得更頻繁。實際上，在給定時間，可能所欲的係僅屬性資訊之不同潛在編碼的子集與實體位址的顆粒相關聯。The inventors have also recognized that, although there may be a large number of options for encoding attribute information, in practice, some encodings are used more frequently than others. In practice, at a given time, it may be desirable to associate only a subset of the different potential encodings of attribute information with a particle of a physical address.
因此，本發明人已經認識到，最有可能使用之屬性資訊的一組編碼可儲存在一組屬性儲存位置中，而非直接指定實體定址表結構的各項中的屬性資訊，且實體定址表結構的項可指定識別屬性儲存位置中之一者的索引以識別屬性資訊的特定編碼。因此，與直接指定屬性資訊本身相比，實體定址表結構的項可產生指示識別一對應組的屬性資訊之索引的小得多的儲存成本。因此，與儲存屬性資訊本身相關聯的較大儲存成本會減少次數，因為此等項之各者可使用較小的索引來引用在屬性儲存位置中儲存一次的屬性資訊，而非產生在實體定址表結構的幾個項中儲存相同屬性資訊的成本。此外，當所欲的係更新屬性資訊時，則可更新少量的屬性儲存位置，且實體定址表結構的各項中儲存的索引可保持相同，此意謂著可能需要進行少得多的更新操作。Therefore, the inventors have recognized that, rather than directly specifying the attribute information in each entry of an entity address table structure, a set of encodings of attribute information that is most likely to be used can be stored in a set of attribute storage locations. Furthermore, an entry of the entity address table structure can specify an index identifying one of the attribute storage locations to identify a particular encoding of the attribute information. Thus, compared to directly specifying the attribute information itself, an entry of the entity address table structure can incur a much lower storage cost for indicating an index identifying a corresponding set of attribute information. Therefore, the larger storage costs associated with storing the attribute information itself are reduced a number of times because each of these entries can use a smaller index to reference the attribute information stored once in the attribute storage location, rather than incurring the cost of storing the same attribute information in several entries in the physical address table structure. In addition, when it is desired to update the attribute information, a small number of attribute storage locations can be updated, and the index stored in each entry of the physical address table structure can remain the same, which means that far fewer update operations may be required.
在一組屬性儲存位置中提供屬性資訊而非直接在實體定址表結構中提供屬性資訊似乎係不尋常的，因為此導致判定屬性資訊所需的存取次數的增加。不是直接存取實體定址表結構中的屬性資訊，而是基於對實體定址表結構的存取來進行對屬性儲存位置的進一步存取（至少在第一次從該組屬性儲存位置判定屬性資訊時）。然而，本發明人已經認識到，令人驚訝的是，由於可由屬性資訊表示之屬性之數目的增加及若更新屬性資訊則可能引起之開銷的減少，此增加的存取次數係值得發生的。尤其令人驚訝的是，間接在實體定址表結構中係值得的，因為一般依賴於虛擬定址頁表來提供大量的權限，且可能預期實體定址表結構提供更有限數目的屬性，使得對於表的儲存要求在任何情形下均係最小的，此意謂著間接係不值得的。然而，本發明人已經識別了可與實體位址相關聯之屬性資訊的數個新實例，且已經認識到可與實體位址相關聯的此等進一步屬性可證明即使在實體定址表結構的情形下亦會產生間接的額外開銷係合理的。Providing attribute information in a set of attribute storage locations rather than directly in the physical address table structure may seem unusual because it results in an increase in the number of accesses required to determine the attribute information. Rather than directly accessing the attribute information in the physical address table structure, further accesses to the attribute storage locations are performed based on accesses to the physical address table structure (at least when first determining the attribute information from the set of attribute storage locations). However, the inventors have recognized that, surprisingly, this increase in accesses is worthwhile due to the increase in the number of attributes that can be represented by the attribute information and the reduction in overhead that may be incurred if the attribute information is updated. It is particularly surprising that indirection is worthwhile in a physical address table structure, because virtual address page tables are typically relied upon to provide a large number of permissions, and a physical address table structure might be expected to provide a more limited number of attributes so that the storage requirements for the table are minimal in any case, meaning that indirection is not worthwhile. However, the inventors have identified several new examples of attribute information that can be associated with a physical address, and have realized that these further attributes that can be associated with a physical address can justify the additional overhead of indirection even in the case of a physical address table structure.
可在記憶體中提供實體定址表結構，儘管從實體定址表結構的部分推導的資訊可經本地快取在屬性判定電路系統處。The physical address table structure may be provided in memory, although information derived from portions of the physical address table structure may be cached locally at the attribute determination circuitry.
儘管一些實例可實施實體定址表結構的線性結構（使用透過相對於基底位址的單一查找索引的連續位址空間區塊來表示），但此可能限制可為位址空間的各別顆粒定義相異項的粒度，因為可能難以為覆蓋大位址空間的單層顆粒保護表分配足夠大的連續位址空間區塊。While some implementations may implement a linear structure of the physical address table structure (represented using contiguous blocks of address space indexed by a single lookup relative to a base address), this may limit the granularity with which distinct entries can be defined for individual granules of address space, as it may be difficult to allocate a sufficiently large contiguous block of address space for a single-level granular protection table covering a large address space.
因此，在一些實例中，實體定址表結構包含多層表結構，該多層表結構包含複數個層級的實體定址表結構，對應於目標實體位址的項被儲存在記憶體系統位置處，該記憶體系統位置與從目標實體位址的一部分推導的實體位址以及從更高層級實體定址表結構中之對應於目標實體位址的更高層級項獲得的表指標相關聯。此使得能夠對較小顆粒之實體位址的相異屬性進行細粒度控制，而不會像單一線性結構的情形那樣施加限制，即整個表必須位於大小對應於待使用表保護之整個實體位址空間之大小的連續記憶體區塊。Thus, in some embodiments, the physical address table structure includes a multi-level table structure comprising a plurality of levels of physical address table structures, wherein an entry corresponding to a target physical address is stored at a memory system location associated with a physical address derived from a portion of the target physical address and a table pointer obtained from a higher-level entry in a higher-level physical address table structure corresponding to the target physical address. This enables fine-grained control over the different properties of smaller-grain physical addresses without imposing the restriction, as in the case of a single linear structure, that the entire table must be located in a contiguous memory block of a size corresponding to the size of the entire physical address space to be protected by the table.
實體定址表結構的項可對應於實體位址的顆粒，其中給定顆粒係某個定義大小的連續位址區塊。顆粒的特定大小可取決於特定實施方案而變化。然而，在一個實例中，實體定址表結構具有能夠向使用實體定址表結構管理之實體位址空間內之實體位址的各4 KB顆粒指派獨立索引的編碼。使用4 KB顆粒係特別有用的，因為4 KB係用於定義轉譯表結構中的轉譯表屬性的典型頁大小，因此此方法允許實體定址表結構以對應於作業系統或超管理器將控制對記憶體之存取之粒度的粒度來定義屬性資訊。儘管實體定址表結構可能具有支援4 KB顆粒大小的編碼，但其亦可支援在單一項中指示多個顆粒之索引的選項（例如，藉由在多層表結構的更高層級編碼索引，指示索引對於大小大於最小顆粒大小的對應記憶體區塊係相同的，使得沒有必要存取表結構的進一步層級，若原本對於該區塊內的更小顆粒分開定義的屬性係所欲的，則將存取該表結構的進一步層級）。因此，雖然實體定址表結構的編碼可支援4 KB顆粒，但表的所有編碼沒有必要實際定義4 KB顆粒，且一些編碼可定義用於設定索引的更粗粒度。Entries of the physical address table structure may correspond to granules of physical addresses, where a given granule is a contiguous block of addresses of some defined size. The specific size of the granule may vary depending on the specific implementation. However, in one embodiment, the physical address table structure has an encoding that can assign a separate index to each 4 KB granule of physical addresses within the physical address space managed using the physical address table structure. Using 4 KB granules is particularly useful because 4 KB is the typical page size used to define translation table attributes in the translation table structure, so this approach allows the physical address table structure to define attribute information at a granularity that corresponds to the granularity at which the operating system or hypervisor will control access to memory. Although a physical address table structure may have an encoding that supports a 4 KB granule size, it may also support the option of indicating an index to multiple granules in a single entry (e.g., by encoding an index at a higher level of a multi-level table structure to indicate that the index is the same for corresponding memory blocks of sizes larger than the minimum granule size, so that there is no need to access further levels of the table structure that would be used if attributes that were originally defined separately for smaller granules within the block were desired). Thus, although an encoding of a physical address table structure may support 4 KB granules, it is not necessary for all encodings of the table to actually define 4 KB granules, and some encodings may define a coarser granularity for setting indexes.
提供該組屬性儲存位置的電路系統不受特別限制。例如，可由屬性判定電路系統存取的一組暫存器可提供一組屬性儲存位置。然而，如下文將論述的，在一些實例中，設備可係具有對共用記憶體之存取且因此具有對相同實體位址空間之共用存取之複數個裝置之較大系統的一部分。在此等實例中，可能所欲的係將相同的屬性與給定目標實體位址相關聯，而不管從哪個裝置存取該位址。因此，可能所欲的係在具有對記憶體之存取的複數個裝置之間共用該組屬性儲存位置。可實現此一點的一種方式係藉由在記憶體區域中提供該組屬性儲存位置，在包含複數個裝置的實例中，該記憶體區域係各裝置可存取的區域。The circuitry that provides the set of attribute storage locations is not particularly limited. For example, a set of registers accessible by the attribute determination circuitry may provide a set of attribute storage locations. However, as discussed below, in some instances, the apparatus may be part of a larger system of multiple devices that have access to a shared memory and, therefore, have shared access to the same physical address space. In such instances, it may be desirable to associate the same attribute with a given target physical address, regardless of which device accesses the address. Therefore, it may be desirable to share the set of attribute storage locations among multiple devices that have access to memory. One way this can be accomplished is by providing the set of property storage locations in a memory area that is accessible to each device in an instance involving multiple devices.
為了提高可存取屬性資訊的速度，在屬性資訊儲存在比快取存取記憶體更慢之位置的實例中，包含屬性判定電路系統的裝置在本地快取屬性資訊可能係有利的，諸如當屬性儲存位置處於記憶體中時。因此，屬性判定電路系統可經組態以快取從由實體定址表結構之對應項的索引識別的給定屬性儲存位置判定的屬性資訊。屬性判定電路系統可在擷取屬性資訊以控制記憶體存取請求的同時進行此操作，或可在預期將來將需要屬性資訊的情況下提前快取屬性資訊。To increase the speed at which attribute information can be accessed, in instances where the attribute information is stored in a location that is slower than cache access memory, it may be advantageous for a device including attribute determination circuitry to cache the attribute information locally, such as when the attribute storage location is in memory. Accordingly, the attribute determination circuitry may be configured to cache attribute information determined from a given attribute storage location identified by an index into a corresponding entry in a physical address table structure. The attribute determination circuitry may do this while retrieving the attribute information to control memory access requests, or it may cache the attribute information in anticipation of a future need for the attribute information.
如上所述，屬性資訊可指示當判定是否應允許特定記憶體存取請求存取目標實體位址時相關的屬性。因此，在一些實例中，可在屬性判定電路系統控制對記憶體存取請求之處理的同時進行屬性判定電路系統對屬性資訊的存取。屬性判定電路系統可控制記憶體存取請求的處理，且可選地亦可快取屬性資訊，使得不需要回應於未來的記憶體存取請求而從屬性儲存位置擷取屬性資訊。As described above, attribute information can indicate attributes that are relevant when determining whether a particular memory access request should be granted access to a target physical address. Therefore, in some examples, the attribute determination circuitry can access the attribute information concurrently with the attribute determination circuitry controlling the processing of the memory access request. The attribute determination circuitry can control the processing of the memory access request and, optionally, cache the attribute information so that the attribute information need not be retrieved from the attribute storage location in response to future memory access requests.
屬性資訊可用以在互連的請求者側而非在更靠近記憶體儲存器的完成者側過濾記憶體存取請求，以實現對從給定實體位址空間可存取哪些實體位址的較在完成者側實際的控制更細粒度的控制。此係因為完成者側一般可具有相對有限的存取整個記憶體系統的能力。例如，用於給定記憶體單元的記憶體控制器可僅具有對該記憶體單元內之位置的存取，且可不具有對位址空間之其他區域的存取。提供更細粒度的控制可依賴於可儲存在記憶體系統中的更複雜的粒度保護資訊表，且從請求者側存取此一表可能更實際，其中存在向記憶體系統的更寬子集發布記憶體存取請求的更大靈活性。Attribute information can be used to filter memory access requests on the requester side of the interconnect rather than on the completer side, which is closer to the memory storage, to achieve finer-grained control over which physical addresses can be accessed from a given physical address space than is actually possible on the completer side. This is because the completer side may generally have relatively limited access to the entire memory system. For example, the memory controller for a given memory unit may only have access to locations within that memory unit and may not have access to other areas of the address space. Providing finer-grained control may rely on a more complex table of granular protection information that can be stored in the memory system, and accessing such a table from the requester side may be more practical, where there is greater flexibility in issuing memory access requests to a wider subset of the memory system.
在需要某些程序與其他程序隔離地安全地執行的一些系統中，系統可支援數個相異實體位址空間。例如，給定實體位址空間中的位址可能無法由具有不同實體位址空間中之目標實體位址的記憶體存取請求存取。可禁止為與處理操作的某些域相關聯的記憶體存取請求選擇某些實體位址空間，從而防止那些域存取記憶體的某些區域。藉由隔離至相異實體位址空間中的存取，此可提供不依賴由作業系統或超管理器所設定之頁表權限資訊的更強的安全保證。在記憶體存取請求的虛擬位址可映射至二或更多個相異實體位址空間中之一者中之實體位址的系統中，屬性資訊可用以限制在特定實體位址空間內的哪些實體位址係可存取的。此可用於確保以晶片上或晶片外之硬體實施的某些實體記憶體位置係存取受限在特定實體位址空間或實體位址空間內之特定子集（若所欲）內。In some systems that require certain programs to run securely and isolated from other programs, the system may support multiple distinct physical address spaces. For example, addresses in a given physical address space may be inaccessible to memory access requests with a target physical address in a different physical address space. Certain physical address spaces may be prohibited from being selected for memory access requests associated with certain domains of processing operations, thereby preventing those domains from accessing certain areas of memory. By isolating access to distinct physical address spaces, this provides stronger security that is independent of page table permission information set by the operating system or hypervisor. In systems where the virtual address of a memory access request can be mapped to a physical address in one of two or more different physical address spaces, attribute information can be used to restrict which physical addresses within a particular physical address space are accessible. This can be used to ensure that certain physical memory locations implemented with on-chip or off-chip hardware are restricted to a particular physical address space or a specific subset of the physical address space (as desired).
因此，設備可包含實體位址空間(physical address space, PAS)選擇電路系統以從二或更多個PAS中選擇用於記憶體存取請求的經選擇PAS。在此一設備中，屬性判定電路系統可經組態以基於與目標實體位址相關聯的屬性資訊來判定複數個實體位址空間中之何者係經允許實體位址空間，其中與經允許實體位址空間以外的實體位址空間相關聯的記憶體存取請求被禁止存取目標實體位址。Therefore, a device may include physical address space (PAS) selection circuitry to select a selected PAS from two or more PASs for a memory access request. In such a device, the attribute determination circuitry may be configured to determine which of the plurality of physical address spaces is an allowed physical address space based on attribute information associated with a target physical address, wherein memory access requests associated with physical address spaces other than the allowed physical address space are prohibited from accessing the target physical address.
該設備可具有實體別名點(point of physical aliasing, PoPA)記憶體系統組件，該實體別名點記憶體系統組件經組態以將來自對應於相同記憶體系統位置之不同PAS的複數個別名實體位址去別名，以將複數個別名實體位址中的任一者映射至待提供至至少一個下游記憶體系統組件的經去別名實體位址；及經提供在該PoPA記憶體系統組件上游的至少一個前PoPA記憶體系統組件，其中該至少一個前PoPA記憶體系統組件經組態以將來自不同PAS的別名實體位址視為彷彿別名實體位址對應於不同的記憶體系統位置。The apparatus may have a point of physical aliasing (PoPA) memory system component configured to de-alias a plurality of individual aliased physical addresses from different PASs corresponding to the same memory system location to map any one of the plurality of individual aliased physical addresses to a de-aliased physical address to be provided to at least one downstream memory system component; and at least one pre-PoPA memory system component provided upstream of the PoPA memory system component, wherein the at least one pre-PoPA memory system component is configured to treat the aliased physical addresses from different PASs as if the aliased physical addresses correspond to different memory system locations.
因此，對於該記憶體系統的至少一些組件，其虛擬位址被轉譯成在不同實體位址空間中之實體位址的記憶體存取請求經視為彷彿其等正在存取在記憶體中完全分開的位址，即使在各別實體位址空間中的實體位址實際上對應於記憶體中的相同位置。Thus, for at least some components of the memory system, memory access requests whose virtual addresses are translated into physical addresses in different physical address spaces are treated as if they are accessing completely separate addresses in memory, even though the physical addresses in the respective physical address spaces actually correspond to the same location in memory.
例如，至少一個前PoPA記憶體系統組件可包括可將用於別名實體位址的資料、程式碼、或位址轉譯資訊快取在單獨項中的快取記憶體或轉譯後備緩衝區，使得若相同的記憶體系統資源經請求從不同的實體位址空間存取，則存取將導致分配單獨的快取記憶體或TLB項。再者，前PoPA記憶體系統組件可包括一致性控制電路系統，諸如一致性互連、監聽過濾器、或用於在各別主裝置處的經快取資訊之間維持一致性的其他機制。一致性控制電路系統可將單獨的一致性狀態指派給不同實體位址空間中的各別別名實體位址。因此，出於維持一致性的目的，即使別名實體位址實際上對應於相同的底層記憶體系統資源，將其等視為分開的位址。雖然表面上，分開追蹤別名實體位址的一致性看起來可能會導致一致性損失的問題，實際上此由於若在不同域中操作的程序確實意圖共用對特定記憶體系統資源的存取，則其等可使用不同域可存取的實體位址空間以提供對該資源的存取而不成問題。前PoPA記憶體系統組件的另一實例可係記憶體保護引擎，其經提供以用於保護儲存至晶片外記憶體的資料防備機密損失及/或篡改。例如，此一記憶體保護引擎可取決於資源從哪個實體位址空間存取而使用不同的加密金鑰分開加密與特定記憶體系統資源關聯的資料，有效地將別名實體位址視為彷彿其等對應於不同的記憶體系統資源（例如，可使用使加密相依於位址的加密方案，且可針對此目的，將實體位址空間識別符視為係位址的部分）。For example, at least one pre-PoPA memory system component may include a cache or translation lookaside buffer that can cache data, code, or address translation information for aliased physical addresses in separate entries, such that if the same memory system resource is requested to be accessed from different physical address spaces, the access will result in the allocation of separate cache or TLB entries. Furthermore, the pre-PoPA memory system component may include coherence control circuitry, such as a coherence interconnect, a snoop filter, or other mechanism for maintaining coherence between cached information at separate masters. The coherence control circuitry can assign separate coherence states to separate aliased physical addresses in different physical address spaces. Therefore, for consistency purposes, alias physical addresses are treated as separate addresses even if they actually correspond to the same underlying memory system resource. While on the surface, separately tracking the consistency of alias physical addresses may appear to lead to consistency loss issues, this is because if programs operating in different domains do intend to share access to a particular memory system resource, they can use the physical address space accessible to the different domains to provide access to that resource without a problem. Another example of a pre-PoPA memory system component may be a memory protection engine, which is provided for protecting data stored in off-chip memory from confidentiality loss and/or tampering. For example, such a memory protection engine may separately encrypt data associated with a particular memory system resource using different encryption keys depending on which physical address space the resource is accessed from, effectively treating the aliased physical addresses as if they corresponded to different memory system resources (e.g., an encryption scheme may be used that makes encryption address-dependent, and the physical address space identifier may be treated as part of the address for this purpose).
無論前PoPA記憶體系統組件的形式為何，此一PoPA記憶體系統組件將別名實體位址視為彷彿其等對應於不同的記憶體系統資源可係有用的，由於此在發布至不同的實體位址空間的存取之間提供硬體強制隔離，使得與一個域關聯的資訊無法藉由諸如快取記憶體時序側通道或涉及由一致性控制電路系統所觸發的一致性的改變的側通道的特徵而洩露至另一域。Regardless of the form of the pre-PoPA memory system component, it may be useful for such a PoPA memory system component to treat aliased physical addresses as if they correspond to different memory system resources, since this provides hardware-enforced isolation between accesses issued to different physical address spaces such that information associated with one domain cannot be leaked to another domain via characteristics such as cache timing side channels or side channels involving coherence changes triggered by coherence control circuitry.
在一些實施方案中，不同實體位址空間中的別名實體位址針對各別不同的實體位址空間使用不同的數值實體位址值表示可係可行的。此方法可能需要映射表以在PoPA處判定不同的實體位址值的哪些對應於相同的記憶體系統資源。然而，可將維持映射表的此負擔視為係不需要的，且因此在一些實施方案中，若別名實體位址包含在不同實體位址空間之各者中使用相同數值實體位址值表示的實體位址，可能更簡單。若採用此方法，則在實體別名點處，其可足夠簡單以將識別哪個實體位址空間係使用記憶體存取存取的實體位址空間識別符拋棄，且接著在下游將剩餘的實體位址位元提供為經去別名實體位址。In some embodiments, it may be feasible for aliased physical addresses in different physical address spaces to be represented using different numerical physical address values for respectively different physical address spaces. This approach may require a mapping table to determine at the PoPA which of the different physical address values correspond to the same memory system resource. However, this burden of maintaining a mapping table may be considered unnecessary, and therefore in some embodiments, it may be simpler if the aliased physical address includes physical addresses represented using the same numerical physical address value in each of the different physical address spaces. If this approach is adopted, then at the physical aliasing point, it may be simple enough to discard the physical address space identifier that identifies which physical address space is accessed using a memory access, and then provide the remaining physical address bits downstream as a de-aliased physical address.
因此，除了前PoPA記憶體系統組件外，該記憶體系統亦可包括一PoPA記憶體系統組件，該PoPA記憶體系統組件經組態以將該複數個別名實體位址去別名以獲得待提供至至少一個下游記憶體系統組件的一經去別名實體位址。如上文所述，PoPA記憶體系統組件可係存取映射表以找出對應於特定位址空間中的別名位址的經去別名位址的裝置。然而，PoPA組件亦可簡單地係在記憶體系統內的位置，其中將與給定記憶體存取關聯的實體位址標籤拋棄，使得下游提供的實體位址唯一識別對應的記憶體系統資源，無論此係從哪個實體位址空間提供。替代地，在一些情形中，PoPA記憶體系統組件仍可將實體位址空間標籤提供給至少一個下游記憶體系統組件（例如，如下文進一步討論的，出於啟用完成者側過濾的目的），但PoPA可標示記憶體系統內之超出其下游記憶體系統組件就不再將別名實體位址視為不同記憶體系統資源的點，但將別名實體位址之各者視為映射相同的記憶體系統資源。例如，若PoPA下游的記憶體控制器或硬體記憶體儲存裝置接收實體位址標籤及給定記憶體存取請求的實體位址，則若該實體位址對應於與先前所見交易相同的實體位址，則可施加針對存取相同實體位址（諸如將存取合併至相同位址）的各別交易執行的任何風險檢查或效能改善，即使該等各別交易指定不同的實體位址空間標籤。相比之下，對於PoPA上游的記憶體系統組件，若此等交易指定不同實體位址空間中的相同實體位址，可不叫用針對存取相同實體位址的交易所採取的此類風險檢查或效能改善步驟。Therefore, in addition to the pre-PoPA memory system component, the memory system may also include a PoPA memory system component configured to de-alias the plurality of aliased physical addresses to obtain a de-aliased physical address to be provided to at least one downstream memory system component. As described above, the PoPA memory system component may be a device that accesses a mapping table to locate a de-aliased address corresponding to an aliased address in a particular address space. However, the PoPA component may simply be a location within the memory system where the physical address tag associated with a given memory access is discarded, such that the physical address provided downstream uniquely identifies the corresponding memory system resource, regardless of the physical address space from which it is provided. Alternatively, in some cases, a PoPA memory system component may still provide the physical address space label to at least one downstream memory system component (e.g., for the purpose of enabling completer-side filtering, as discussed further below), but the PoPA may mark a point within the memory system beyond which its downstream memory system components no longer treat the aliased physical addresses as distinct memory system resources, but rather treat each of the aliased physical addresses as mapping the same memory system resource. For example, if a memory controller or hardware memory storage device downstream of PoPA receives a physical address tag and the physical address of a given memory access request, then if the physical address corresponds to the same physical address as a previously seen transaction, any risk checks or performance improvements that are applied to separate transactions accessing the same physical address (e.g., coalescing accesses to the same address) may be applied, even if the separate transactions specify different physical address space tags. In contrast, for a memory system component upstream of PoPA, if the transactions specify the same physical address in different physical address spaces, such risk checks or performance improvements that are applied to transactions accessing the same physical address may not be applied.
支援複數個實體位址空間的一些系統可支援數個域中的操作。在一些實例中，該等域可包括至少一較低安全域及一較高安全域（分別對應於較低安全實體位址空間及較高安全實體位址空間），且該較高安全實體位址空間可被禁止經選擇用於與該較低安全域相關聯的記憶體存取請求。藉由禁止較低安全域選擇較高安全實體位址空間用於記憶體存取請求，則可防止較低安全域存取儲存在由屬性資訊指示為僅可從安全實體位址空間存取之位置中的資料。因此，安全域可具有對與較低安全域完全隔離的記憶體區域的存取，此對於提高安全性可係有用的。可允許較高安全域在較高安全或較低安全實體位址空間中發布記憶體存取請求，從而與較低安全域相比具有對更大範圍之實體位址的存取。Some systems that support multiple physical address spaces may support operations in several domains. In some examples, the domains may include at least one lower security domain and one higher security domain (corresponding to the lower security physical address space and the higher security physical address space, respectively), and the higher security physical address space may be prohibited from being selected for memory access requests associated with the lower security domain. By prohibiting the lower security domain from selecting the higher security physical address space for memory access requests, the lower security domain may be prevented from accessing data stored in locations indicated by attribute information as accessible only from the secure physical address space. Thus, a secure domain may have access to memory areas that are completely isolated from the lower security domain, which may be useful for improving security. A higher security domain may be allowed to issue memory access requests in a higher security or lower security physical address space, thereby having access to a larger range of physical addresses than a lower security domain.
在一些實例中，亦可支援其他處理域。例如，可支援與額外較高安全PAS相關聯的額外較高安全域。該額外較高安全PAS可被禁止經選擇用於與該較低安全域相關聯的記憶體存取請求。該額外較高安全PAS亦可被禁止經選擇用於與該較高安全域相關聯的記憶體存取請求，且該較高安全PAS可被禁止經選擇用於與該額外較高安全域相關聯的記憶體存取請求。藉由提供兩個較高安全域，其各具有無法從另一較高安全域存取的對應較高安全PAS（而與該較低安全域相關聯的記憶體存取請求無法存取該等較高安全PAS之任何者），此允許由兩個相互不受信任的軟體開發者所提供之軟體共存於相同硬體上，而無需彼此信任，即使當提供者兩者需要保證與較低安全軟體組件隔離。例如，該較高安全域及該額外較高安全域可對應於下文提及之安全域及領域域（或反之亦然）。In some embodiments, other processing domains may also be supported. For example, an additional higher security domain associated with an additional higher security PAS may be supported. The additional higher security PAS may be disabled for selected memory access requests associated with the lower security domain. The additional higher security PAS may also be disabled for selected memory access requests associated with the higher security domain, and the higher security PAS may be disabled for selected memory access requests associated with the additional higher security domain. By providing two higher security domains, each with a corresponding higher security PAS that cannot be accessed from the other higher security domain (and memory access requests associated with the lower security domain cannot access any of the higher security PAS), this allows software provided by two mutually untrusted software developers to coexist on the same hardware without trusting each other, even when both providers need to ensure isolation from the lower security software components. For example, the higher security domain and the additional higher security domain can correspond to the security domain and domain domain mentioned below (or vice versa).
在一些實例中，可存在最安全域，其被允許存取任何實體位址空間，且具有對任何其他域不能存取之實體位址空間的存取。例如，該等域可包括用於管理該複數個域之其他域之間的切換的一根域。該根域與一根PAS相關聯，該根PAS被禁止經選擇用於與除了該根域以外的一域相關聯的記憶體存取請求。In some examples, there may be a most secure domain that is allowed to access any physical address space and has access to physical address space that is inaccessible to any other domain. For example, the domains may include a root domain for managing handoffs between other domains in the plurality of domains. The root domain is associated with a root PAS that is disabled from being used for memory access requests associated with a domain other than the root domain.
亦可能存在一些支援複數個操作域但不一定支援複數個實體位址空間的系統。在此類實例中，不同的操作域可具有對不同組資源的存取且可具有階層式結構，其中某些域比其他域更受信任。There may also be some systems that support multiple operating domains but not necessarily multiple physical address spaces. In such examples, different operating domains may have access to different sets of resources and may have a hierarchical structure where some domains are more trusted than others.
在支援複數個域的系統中，將對某些實體位址的存取限制為從某些域發布的記憶體存取可能係所欲的。除了基於發布記憶體存取請求的實體位址空間來限制存取之外，或替代基於發布記憶體存取請求的實體位址空間來限制存取，亦可提供此一點。因此，在一些實例中，屬性判定電路系統經組態以基於與目標實體位址相關聯的屬性資訊來判定複數個域中之何者係經允許域，其中與經允許域以外的域相關聯的記憶體存取請求被禁止存取目標實體位址。基於發布記憶體存取請求的域來限制存取可在期望禁止從特定操作域存取特定實體位址的系統中提供額外安全保證。使用該組屬性儲存位置來表示域屬性資訊可能係特別有用的，因為考慮到項大小的相關聯增加，直接在實體定址表結構的項中表示此資訊可能係不合理的。In a system that supports multiple domains, it may be desirable to restrict access to certain physical addresses to memory accesses issued from certain domains. This may be provided in addition to or in lieu of restricting access based on the physical address space from which the memory access request is issued. Thus, in some examples, attribute determination circuitry is configured to determine which of a plurality of domains is an allowed domain based on attribute information associated with a target physical address, wherein memory access requests associated with domains other than the allowed domains are prohibited from accessing the target physical address. Restricting access based on the domain from which the memory access request is issued may provide additional security in systems where it is desired to prohibit access to specific physical addresses from specific operating domains. Using the set of attribute storage locations to represent domain attribute information may be particularly useful because representing this information directly in the entries of the entity address table structure may not be reasonable due to the associated increase in entry size.
在支援複數個域及複數個實體位址空間二者的一些實例中，屬性判定電路系統可經組態以基於與目標實體位址相關聯的屬性資訊來判定複數個域及複數個實體位址空間之組合中之何者係域及實體位址空間之經允許組合，其中與經允許組合以外的組合相關聯的記憶體存取請求被禁止存取目標實體位址。考慮記憶體存取請求的域及實體位址空間二者可提高安全性並增加記憶體存取控制的靈活性。In some embodiments supporting both a plurality of domains and a plurality of physical address spaces, the attribute determination circuitry can be configured to determine which of the combinations of the plurality of domains and the plurality of physical address spaces is a permitted combination of domains and physical address spaces based on attribute information associated with a target physical address, wherein memory access requests associated with combinations other than the permitted combination are prohibited from accessing the target physical address. Considering both the domain and the physical address space of a memory access request can improve security and increase the flexibility of memory access control.
例如，在一些實例中，通常允許較高安全域向較低安全實體位址空間中的給定目標位址發布記憶體存取請求，且因此若屬性資訊指示目標實體位址可從較低安全實體位址空間存取，則沒有什麼可禁止較高安全域存取給定目標位址。然而，可能存在防止較高安全域存取可在較低安全實體位址空間中存取的目標實體位址係所欲的情況。例如，此可提高抗混淆副攻擊（其係利用較高安全軟體之更大特權之攻擊的形式）的穩健性。例如，攻擊者可欺騙在較高安全域中執行的軟體執行記憶體存取，其損害與該較低安全域相關聯的資源。藉由提供指示實體位址空間及經允許域之經允許組合的屬性資訊，則可將較低安全PAS的某些區域與在較高安全域中操作的較高安全軟體隔離，因為對於此等區域，較低安全PAS及較高安全域的組合可能不係經允許組合，且因此與較高安全域相關聯的記憶體存取請求可能不能存取此等區域中的實體位址，即使當其等指定了與較低安全域相關聯的較低安全PAS。此有助於建立一額外保護層，其可在「縱深防禦(defence in depth)」方法中有助於防禦由較低安全軟體所使用抗混淆副攻擊的資源。考慮經允許PAS及域的組合可極大地增加屬性資訊之可能編碼的數目，且因此，此技術在屬性資訊可直接在實體定址表結構中指定的實例中可能顯得不尋常。然而，當考慮是否允許存取請求存取特定實體位址時，藉由在單獨的屬性儲存位置中指定屬性資訊來使用間接，可使得能夠使用PAS及域的任意組合。For example, in some instances, a higher security domain is generally permitted to issue memory access requests to a given target address in a lower security entity address space, and therefore, if attribute information indicates that the target entity address is accessible from the lower security entity address space, then there is nothing to prohibit the higher security domain from accessing the given target address. However, there may be situations where it is desirable to prevent a higher security domain from accessing a target entity address that is accessible in the lower security entity address space. For example, this can increase robustness against obfuscation attacks (which are a form of attack that exploits the greater privileges of higher security software). For example, an attacker can trick software executing in a higher security domain into performing memory accesses that compromise resources associated with the lower security domain. By providing attribute information indicating permitted combinations of physical address space and permitted domains, certain areas of the lower-security PAS can be isolated from higher-security software operating in a higher-security domain because the combination of the lower-security PAS and the higher-security domain may not be a permitted combination for these areas, and therefore memory access requests associated with the higher-security domain may not be able to access physical addresses in these areas, even when they specify the lower-security PAS associated with the lower-security domain. This helps to establish an additional layer of protection that can help defend against obfuscation attacks used by lower-security software in a "defense in depth" approach. Considering the allowed combinations of PAS and domains can greatly increase the number of possible encodings of attribute information, and therefore, this technique may be undesirable in instances where attribute information can be specified directly in the entity address table structure. However, using indirection by specifying attribute information in a separate attribute storage location when considering whether to grant access to a particular entity address to an access request enables the use of any combination of PAS and domains.
在一些實例中，除了指定指示給定屬性儲存位置的索引之外，實體定址表結構的項亦可指定某些屬性資訊。然而，在一些實例中，可藉由僅指定實體定址表結構之各項中的索引及屬性儲存位置中的所有屬性來最小化項的大小。因此，在一些實例中，屬性判定電路系統經配置以從實體定址表結構之對應項的整體判定索引。In some examples, in addition to specifying an index indicating a given attribute storage location, an entry in the entity address table structure may also specify certain attribute information. However, in some examples, the size of the entry can be minimized by specifying only the index in each entry of the entity address table structure and all attributes in the attribute storage location. Therefore, in some examples, the attribute determination circuitry is configured to determine the index from the entirety of the corresponding entry in the entity address table structure.
在一些實例中，屬性判定電路系統經組態以將實體定址表結構之項的至少一個編碼視為不能用以指示屬性儲存位置的保留編碼，且回應於判定包含對應項之實體定址表結構的一部分包含具有保留編碼的項，屬性判定電路系統經組態以觸發錯誤處理回應。保留編碼可係例如不對應於該組屬性儲存位置中之有效項的索引。保留編碼的識別可係固線式的，或可係可程式化的，使得保留編碼的數目可係可變的。存在具有保留編碼的項（不應為正確組態的記憶體區域選擇該項）可能暗示發生了錯誤（諸如藉由改變識別屬性儲存位置之索引的狀態來破壞系統操作的惡意嘗試，或諸如由於粒子撞擊或其他隨機發生的實體事件導致之位元從0翻換到1或反之亦然的意外錯誤）。因此，回應於偵測到具有保留編碼的項而觸發錯誤處理回應可幫助減少出錯的可能性。In some examples, the attribute determination circuitry is configured to treat at least one encoding of an entry in a physical address table structure as a reserved encoding that cannot be used to indicate a property storage location, and in response to determining that a portion of the physical address table structure containing the corresponding entry includes an entry with a reserved encoding, the attribute determination circuitry is configured to trigger an error handling response. The reserved encoding may be, for example, an index that does not correspond to a valid entry in the set of property storage locations. The identification of the reserved encodings may be fixed or programmable such that the number of reserved encodings is variable. The presence of an entry with a reserved encoding (which should not be selected for a correctly configured memory area) may indicate that an error has occurred (such as a malicious attempt to disrupt system operation by changing the state of an index identifying a property storage location, or an unexpected error such as a bit flipping from 0 to 1 or vice versa due to a particle impact or other randomly occurring physical event). Therefore, triggering an error handling response in response to detecting an entry with a reserved encoding can help reduce the likelihood of errors.
在一些實例中，當存取表結構以尋找給定目標實體位址的資訊時針對保留編碼進行檢查之實體定址表結構的部分可僅包含與給定目標實體位址相關的對應項。然而，實際上，若大量的編碼用作非保留編碼（例如，若索引具有N個位元且該組屬性儲存位置包含幾乎2^N個屬性儲存位置），則對於給定項將僅存在很少的保留編碼。若隨機修改項，則意外選擇非保留編碼的機會可能因此相對較高，且在該部分僅包含對應項的情形下使用上述方法識別錯誤的機會可能相對較低。In some examples, the portion of the entity address table structure that is checked for reserved encodings when accessing the table structure to find information for a given target entity address may contain only corresponding entries associated with the given target entity address. However, in practice, if a large number of encodings are used as non-reserved encodings (for example, if the index has N bits and the set of attribute storage locations includes approximately 2^N attribute storage locations), then there will be only a few reserved encodings for a given entry. Therefore, if an entry is randomly modified, the chance of accidentally selecting a non-reserved encoding may be relatively high, and the chance of identifying an error using the above method when the portion contains only corresponding entries may be relatively low.
因此，在一些實例中，當尋找與給定目標實體位址相關的資訊時針對保留編碼進行檢查之實體定址表結構的部分可包含比與該給定目標實體位址相關的對應項更多的項，且若實體定址表結構之部分中的任何項具有保留編碼，則屬性判定電路系統可經組態以觸發錯誤處理回應，即使該項並非與目前記憶體存取請求相關聯之目標實體位址的對應項。在一些實例中，該部分可包含含有實體定址表結構之項的記憶體區塊，該實體定址表結構包含對應項。然而，為了進一步增加識別錯誤的機會（此在保留編碼的數目極其有限的情形下可能係特別有用的），在一些實例中，該部分可包含含有實體定址表結構之項的若干記憶體區塊，該實體定址表結構包含對應項。Thus, in some examples, the portion of the physical address table structure that is checked for reserved encodings when looking up information associated with a given target physical address may contain more entries than corresponding entries associated with the given target physical address, and the attribute determination circuitry may be configured to trigger an error handling response if any entry in the portion of the physical address table structure has a reserved encoding, even if the entry is not a corresponding entry for the target physical address associated with the current memory access request. In some examples, the portion may include a memory block containing an entry of the physical address table structure that contains the corresponding entry. However, to further increase the chances of identifying errors (which may be particularly useful where the number of reserved encodings is extremely limited), in some examples the portion may include several memory blocks containing entries of a physical address table structure containing corresponding entries.
例如，在一些實例中，實體定址表結構的項可包含編碼至多2^4=16個不同索引的4個位元。若有15個有效的屬性儲存位置，則索引的1個編碼可能係不能用以指示屬性儲存位置的保留編碼。實體定址表結構可包含在單一記憶體存取中載入的64個位元的區段，且因此在實體定址表結構的各區段中可存在16個項，當載入給定的4位元項時此等項被一起載入。在一些實例中，該部分可包含實體定址表結構的64位元區段，使得若在存取對應項時載入之16個項中之任一者具有保留編碼，則觸發錯誤處理回應。此可增加識別錯誤的可能性，而不會增加記憶體存取開銷。在識別任何錯誤係更加所欲的其他情形下，可將表的其他區段與包含對應項的區段一起載入，使得當存取對應項時，可針對（多個）保留編碼檢查實體定址表結構的128位元、256位元、或512位元（例如）部分。For example, in some instances, an entry of the physical address table structure may include 4 bits that encode up to 2^4=16 different indices. If there are 15 valid attribute storage locations, then 1 encoding of the index may be a reserved encoding that cannot be used to indicate an attribute storage location. The physical address table structure may include a 64-bit segment that is loaded in a single memory access, and therefore there may be 16 entries in each segment of the physical address table structure, which are loaded together when a given 4-bit entry is loaded. In some instances, the portion may include a 64-bit segment of the physical address table structure, such that if any of the 16 entries loaded when the corresponding entry is accessed has a reserved encoding, an error handling response is triggered. This may increase the likelihood of identifying errors without increasing memory access overhead. In other cases where it is more desirable to identify any errors, other sections of the table may be loaded along with the section containing the corresponding entry so that when the corresponding entry is accessed, a 128-bit, 256-bit, or 512-bit (for example) portion of the physical address table structure may be checked for the reserved encoding(s).
在一些實例中，屬性儲存位置的大小超過實體定址表結構的項的大小，從而允許對於實體定址表結構之每個項之給定數目的位元，各項與比藉由直接指示實體定址表結構之各項中的屬性可實現之更大數目的屬性相關聯。然而，在一些實例中，屬性儲存位置可不大於實體定址表結構的對應項。在此等實例中，屬性儲存位置的提供可能不會減少實體定址表結構的儲存要求，但可能仍然係有用的。例如，屬性儲存位置的提供可使得能夠以減少的操作次數來更新屬性資訊。若實體位址的若干顆粒共用同一組屬性且若所欲的係更新該組屬性，則在屬性資訊直接在實體定址表結構中指定的實例中，各項將需要單獨更新。然而，在共用屬性的項全部提供對儲存屬性資訊之相同屬性儲存位置之索引的實例中，則可在屬性儲存位置的單一更新中更新該屬性資訊。In some instances, the size of the attribute storage location exceeds the size of the entries of the entity address table structure, thereby allowing, for a given number of bits per entry of the entity address table structure, each entry to be associated with a greater number of attributes than could be achieved by directly indicating the attributes in the entries of the entity address table structure. However, in some instances, the attribute storage location may be no larger than the corresponding entry of the entity address table structure. In such instances, the provision of an attribute storage location may not reduce the storage requirements of the entity address table structure, but may still be useful. For example, the provision of an attribute storage location may enable attribute information to be updated with a reduced number of operations. If several particles of an entity address share the same set of attributes and if it is desired to update that set of attributes, then in instances where the attribute information is specified directly in the entity address table structure, each entry will need to be updated individually. However, in instances where the items sharing a common attribute all provide a reference to the same attribute storage location storing attribute information, then the attribute information may be updated in a single update of the attribute storage location.
如上所述，在一些實例中，若干裝置可共用對包含對應於實體位址之儲存位置的記憶體系統的存取，該等實體位址在實體定址表結構中具有對應項。在一些實例中，可能所欲的係將相同屬性與各實體位址相關聯，而不管記憶體存取源自哪個裝置。例如，此可使得能夠針對具有對記憶體之存取的各裝置強制一致地執行安全性。存取記憶體的各裝置可具有其自身的屬性判定電路系統實例，或若干裝置可共用對屬性判定電路系統的存取。在任一情形下，為了在系統上一致地將相同屬性與實體位址相關聯，在一些實例中，該組屬性儲存位置可被強制為在屬性判定電路系統的複數個實例上係一致的。As described above, in some instances, several devices may share access to a memory system that includes storage locations corresponding to physical addresses that have corresponding entries in a physical address table structure. In some instances, it may be desirable to associate the same attributes with each physical address, regardless of which device the memory access originates from. This may enable, for example, security to be enforced consistently across devices that have access to memory. Each device that accesses memory may have its own instance of attribute determination circuitry, or several devices may share access to the attribute determination circuitry. In either case, in order to systematically associate the same attributes with physical addresses consistently, in some instances, the set of attribute storage locations may be enforced to be consistent across multiple instances of the attribute determination circuitry.
例如，屬性判定電路系統的複數個實例可使用該相同組的屬性儲存位置或被強制為彼此一致的不同組的屬性儲存位置來判定與由來自不同來源的記憶體存取請求指定的目標實體位址相關聯的屬性資訊。For example, multiple instances of the attribute determination circuitry may use the same set of attribute storage locations or different sets of attribute storage locations that are enforced to be consistent with each other to determine attribute information associated with a target physical address specified by memory access requests from different sources.
此可以多種方式實現。例如，該組屬性儲存位置可儲存在屬性判定電路系統的各實例本地的暫存器中，且可提供機制來強制暫存器之間的一致性。替代地，該組屬性儲存位置可儲存在記憶體中，該記憶體在包含屬性判定電路系統之複數個實例的裝置之間共用。在此等實例中，藉由從記憶體存取該組屬性儲存位置，屬性判定電路系統的複數個實例存取相同的屬性資訊。This can be implemented in a variety of ways. For example, the set of property storage locations can be stored in registers local to each instance of the property determination circuitry, and a mechanism can be provided to enforce consistency between registers. Alternatively, the set of property storage locations can be stored in a memory shared among devices that include multiple instances of the property determination circuitry. In such instances, by accessing the set of property storage locations from the memory, multiple instances of the property determination circuitry access the same property information.
在屬性資訊儲存在記憶體中的一些實例中，該組屬性儲存位置可針對屬性判定電路系統的不同實例經本地快取，且在此類系統中，可強制經快取副本彼此一致。例如，回應於該組屬性儲存位置的任何修改，可使屬性儲存位置的經快取副本無效，如下所論述。In some instances where attribute information is stored in memory, the set of attribute storage locations can be cached locally for different instances of the attribute determination circuitry, and in such systems, the cached copies can be forced to be consistent with each other. For example, any modification to the set of attribute storage locations can invalidate the cached copy of the attribute storage location, as discussed below.
在一些實例中，可以相同的方式考慮對給定實體位址空間內之特定實體位址的所有存取，而不管哪個特定硬體裝置起始請求。雖然此方法可提供高安全性，但其可能相對不靈活，因為在現代資料處理系統中，可能存在許多實體處理器、硬體加速器、及具有記憶體存取能力的其他請求者裝置，此等裝置在一些使用模型中可能具有不同的安全性要求。In some examples, all accesses to a particular physical address within a given physical address space can be considered in the same manner, regardless of which specific hardware device initiates the request. While this approach can provide high security, it can be relatively inflexible because in modern data processing systems, there may be many physical processors, hardware accelerators, and other requestor devices with memory access capabilities, each of which may have different security requirements in some usage models.
相反，在一些實例中，從請求者硬體裝置接收的記憶體存取請求指定與該請求硬體裝置相關聯的請求者群組識別符(requester group identifier, RGID)。屬性判定電路系統經組態以基於與目標實體位址相關聯的屬性資訊來判定複數個RGID中之何者係經允許RGID，其中與經允許RGID以外的RGID相關聯的記憶體存取請求被禁止存取目標實體位址。利用此方法，對相同實體位址空間中之相同實體位址的記憶體存取請求可取決於哪個硬體裝置發布請求而被不同地處理，而不需要依賴於在轉譯表結構中定義的特定權限。因此，即使定義轉譯表結構的作業系統或超管理器不可信，亦可限制對實體位址空間之某些區域的存取，同時使得一個硬體裝置能夠獲得另一硬體裝置無法看到的實體記憶體的視圖，即使原則上允許兩個硬體裝置存取相同的實體位址空間。In contrast, in some examples, a memory access request received from a requestor hardware device specifies a requester group identifier (RGID) associated with the requesting hardware device. The attribute determination circuitry is configured to determine which of a plurality of RGIDs is an allowed RGID based on attribute information associated with a target physical address, wherein memory access requests associated with RGIDs other than the allowed RGIDs are prohibited from accessing the target physical address. Using this approach, memory access requests to the same physical address in the same physical address space can be handled differently depending on which hardware device issues the request, without relying on specific permissions defined in a translation table structure. Thus, even if the operating system or hypervisor that defines the translation table structures is untrusted, it is possible to restrict access to certain areas of the physical address space, while enabling one hardware device to gain a view of physical memory that another hardware device cannot see, even though both hardware devices are in principle allowed to access the same physical address space.
在一些實例中，可能存在受記憶體標記保護之實體位址空間的區域，其中記憶體位置與記憶體標籤相關聯且與位址標籤相關聯地發布記憶體請求。對於經標記憶體區域，可能需要比較記憶體標籤及位址標籤來判定是否允許記憶體存取。因此，當處理記憶體存取請求時，知道經存取記憶體區域是否係經標記憶體區域可係有用的，如此便知道是否進行標籤檢查。知道經存取記憶體區域是否儲存記憶體標籤亦可係有用的，因為儲存記憶體標籤的區域可受到與其他區域不同之單獨的權限檢查，以防止記憶體標籤的不正確修改。例如，僅允許標籤修改存取請求或儲存指令類型的子集修改指定用於儲存記憶體標籤的記憶體區域。In some instances, there may be regions of physical address space that are protected by memory tags, where memory locations are associated with memory tags and memory requests are issued in association with the address tags. For regions of tagged memory, it may be necessary to compare the memory tag and the address tag to determine whether memory access is allowed. Therefore, when processing a memory access request, it may be useful to know whether the accessed memory region is a tagged memory region so that it knows whether to perform a tag check. It may also be useful to know whether the accessed memory region stores memory tags, because regions that store memory tags can be subject to separate permission checks from other regions to prevent incorrect modification of memory tags. For example, only a subset of tag-modifying access requests or store instruction types are allowed to modify the memory region designated for storing memory tags.
可在實體位址空間中定義受記憶體標記保護的區域及儲存記憶體標籤的區域。因此，實體定址表結構提供用於定義記憶體標記屬性的特別方便的機制。因此，在一些實例中，屬性判定電路系統經組態以基於與目標實體位址相關聯的屬性資訊來判定記憶體標記屬性，該記憶體標記屬性包含以下中之至少一者：對目標實體位址是否位於受記憶體標記保護的記憶體區域中的指示；及對目標實體位址是否位於儲存記憶體標籤的記憶體區域中的指示。Regions protected by memory tags and regions storing memory tags can be defined in the physical address space. Thus, the physical address table structure provides a particularly convenient mechanism for defining memory tag attributes. Thus, in some examples, the attribute determination circuitry is configured to determine a memory tag attribute based on attribute information associated with a target physical address, the memory tag attribute including at least one of: an indication of whether the target physical address is located in a memory region protected by memory tags; and an indication of whether the target physical address is located in a memory region storing memory tags.
在屬性儲存位置中指定屬性資訊的方式沒有特別限制。在一些實例中，對於各屬性類別，可提供具有比該屬性類別之相異值的總數更少的位元的位元欄。例如，若有四個可能的實體位址空間，則可使用2位元欄來編碼該屬性資訊。然而，在一些實例中，為了在指定屬性資訊時提供更大的靈活性（例如，允許獨立於其他屬性來修改某些屬性），屬性資訊可指示至少一個位元映像，其中該至少一個位元映像的各位元指示是否給定類別的記憶體存取請求為不被禁止存取目標實體位址之經允許類別的記憶體存取請求。例如，可為各實體位址空間單獨提供一位元來指示是否允許在該實體位址空間中發布的記憶體存取請求來存取目標實體位址。此可允許為給定目標位址定義之屬性的任意組合。位元映像一般係一種比其他編碼更不緊湊的編碼，用於表示給定量的資訊，且對於直接在實體定址表結構的項中指定屬性資訊而言，位元映像似乎係不尋常的選擇。然而，由於在本技術中，屬性資訊經定義在一組單獨的屬性儲存位置中，因此可使用位元映像來表示屬性資訊，而不會導致實體定址表結構之項之大小的不合理增加。因此，在一些實例中，使用該組屬性儲存位置使得能夠使用更靈活的位元映像編碼來表示屬性資訊，從而使得能夠設定的相異屬性組合的數目具有更大的靈活性。There are no particular limitations on the manner in which attribute information may be specified in an attribute storage location. In some examples, for each attribute category, a bit field having fewer bits than the total number of distinct values for the attribute category may be provided. For example, if there are four possible physical address spaces, a 2-bit field may be used to encode the attribute information. However, in some examples, in order to provide greater flexibility in specifying attribute information (e.g., to allow certain attributes to be modified independently of other attributes), the attribute information may indicate at least one bit image, wherein each bit of the at least one bit image indicates whether a memory access request of a given category is a memory access request of an allowed category that is not prohibited from accessing the target physical address. For example, a single bit may be provided for each physical address space to indicate whether a memory access request issued in that physical address space is allowed to access the target physical address. This allows any combination of attributes defined for a given target address. Bitmaps are generally a less compact encoding than other encodings for representing a given amount of information, and may seem an unusual choice for specifying attribute information directly in entries of a physical address table structure. However, because the attribute information is defined in a separate set of attribute storage locations in the present technology, bitmaps may be used to represent the attribute information without unduly increasing the size of the entries of the physical address table structure. Thus, in some instances, using this set of attribute storage locations enables the use of a more flexible bitmap encoding to represent attribute information, thereby allowing greater flexibility in the number of different attribute combinations that can be set.
如上所述，在一些實例中，為了強制屬性資訊的一致性，屬性判定電路系統可經組態以回應於判定屬性資訊的屬性儲存位置已經更新的指示而使任何經快取屬性資訊無效。例如，裝置的處理電路系統支援的ISA可支援「使屬性無效」指令，該指令在執行時導致來自該組屬性儲存位置之屬性資訊的經本地快取版本無效。雖然在一些實例中，無效屬性指令可係全域指令，該指令在執行時導致所有經快取屬性資訊無效，但在一些其他實例中，無效屬性指令可指定特定屬性儲存位置（或屬性儲存位置的子集，例如，由一範圍的屬性儲存項識別符來識別）的識別符，且回應於無效屬性指令，可僅使從由指定屬性儲存位置（或屬性儲存位置的子集）判定的屬性資訊推導的經快取資訊無效。當軟體修改屬性儲存位置中的屬性時，且尤其係在屬性儲存位置經提供在記憶體中的情形下（其中在沒有無效屬性指令的情形下可能難以判定給定儲存是否導致屬性資訊的修改），可執行無效屬性指令。藉由支援無效屬性指令或用於在更新屬性儲存位置時使屬性資訊的經快取副本無效的任何其他機制，系統可強制與目標實體位址相關聯的屬性資訊之間的一致性。As described above, in some examples, to enforce consistency of attribute information, the attribute determination circuitry may be configured to invalidate any cached attribute information in response to an indication that the attribute storage locations that determine the attribute information have been updated. For example, the ISA supported by the processing circuitry of the device may support an "invalidate attribute" instruction that, when executed, causes the locally cached version of the attribute information from the set of attribute storage locations to be invalidated. While in some examples, the invalidate-attributes instruction may be a global instruction that, when executed, causes all cached attribute information to be invalidated, in some other examples, the invalidate-attributes instruction may specify an identifier for a particular attribute storage location (or a subset of attribute storage locations, e.g., identified by a range of attribute storage entry identifiers), and in response to the invalidate-attributes instruction, only cached information derived from attribute information determined by the specified attribute storage location (or subset of attribute storage locations) may be invalidated. When software modifies properties in a property storage location, and particularly where the property storage location is provided in memory (where it may be difficult to determine whether a given store results in a modification of the property information without an invalidate property instruction), an invalidate property instruction may be executed. By supporting an invalidate property instruction or any other mechanism for invalidating cached copies of property information when updating a property storage location, the system can enforce consistency between property information associated with a target physical address.
亦如上文所論述，存在一些在記憶體中提供該組屬性儲存位置的實例。因此，為了使得屬性判定電路系統可定位屬性儲存位置，屬性判定電路系統可具有對指標儲存位置的存取，該指標儲存位置儲存指示包含該組屬性儲存位置之記憶體系統中之一或多個位置的指標資訊。由實體定址表結構的對應項指定的索引可添加到指標資訊或與指標資訊連接，以識別儲存對應於目標實體位址之屬性資訊的經選擇屬性儲存位置。As also discussed above, there are some examples of providing the set of attribute storage locations in memory. Therefore, to enable the attribute determination circuitry to locate the attribute storage location, the attribute determination circuitry may have access to a pointer storage location that stores pointer information indicating one or more locations in the memory system that contain the set of attribute storage locations. An index specified by a corresponding entry in the entity address table structure may be added to or concatenated with the pointer information to identify a selected attribute storage location that stores attribute information corresponding to the target entity address.
在一些實例中，屬性資訊可包含至少一個讀取/寫入權限屬性，該至少一個讀取/寫入權限屬性指示是否禁止對實體位址之目標顆粒的讀取存取，及（獨立於是否禁止讀取存取）是否禁止對實體位址之目標顆粒的寫入存取。此可幫助支援使用超出在轉譯表結構中設定屬性之軟體（其通常用以控制唯讀或唯寫記憶體屬性）之控制的屬性來定義唯讀或唯寫區域，且因此可在設定轉譯表的軟體可能不可信的系統中提供額外安全層。使用屬性儲存位置來提供讀取/寫入權限意謂著其等不需要直接在實體定址表結構的項中指示，且因此可以減少的開銷來提供。In some examples, the attribute information may include at least one read/write permission attribute that indicates whether read access to the target particle at the physical address is prohibited, and (independent of whether read access is prohibited) whether write access to the target particle at the physical address is prohibited. This can help support the use of attributes that are beyond the control of software that sets attributes in the translation table structure (which is typically used to control read-only or write-only memory attributes) to define read-only or write-only areas, and thus can provide an additional layer of security in systems where the software that sets the translation table may not be trusted. Using attribute storage locations to provide read/write permissions means that they do not need to be indicated directly in the entries of the physical address table structure, and can therefore be provided with reduced overhead.
在屬性資訊指示讀取/寫入屬性及經允許RGID二者的一些實例中，屬性資訊可包含複數個讀取/寫入權限屬性，以針對請求者群組識別符的複數個各別值獨立定義是否對於與請求者群組識別符的各別值相關聯之一或多個請求者硬體裝置的各別群組，禁止讀取存取或寫入存取。此對於以下可係有用的：允許與不同RGID相關聯的不同硬體裝置，以正交於作業系統或超管理器控制之轉譯表權限的方式被給予關於其等是否可讀取或寫入給定記憶體區域的不同權限。例如，當記憶體區域用作由多個請求者裝置或程序以管線方式處理之內容的緩衝區時，給予與一個RGID值相關聯的一或多個請求者硬體裝置對給定記憶體區域的唯讀存取及給予與不同RGID值相關聯的一或多個請求者硬體裝置對給定記憶體區域的唯寫存取可係有用的。此可幫助定義硬體裝置之間的生產者-消費者關係，以便充當管線中給定步驟之生產者的裝置可被給予唯寫存取，且充當管線中給定步驟產生之資料之消費者的裝置被給予唯讀存取。藉由在存取給定記憶體區域時限制給定RGID允許的存取類型，此可提高安全性。In some instances where the attribute information indicates both read/write attributes and permitted RGIDs, the attribute information may include a plurality of read/write permission attributes to independently define, for a plurality of respective values of the requestor group identifier, whether read access or write access is prohibited for respective groups of one or more requestor hardware devices associated with the respective values of the requestor group identifier. This may be useful for allowing different hardware devices associated with different RGIDs to be given different permissions regarding whether they can read or write to a given memory region in a manner orthogonal to translation table permissions controlled by the operating system or hypervisor. For example, when a memory region is used as a buffer for content that is processed in a pipelined manner by multiple requestor devices or processes, it can be useful to give one or more requestor hardware devices associated with one RGID value only read-only access to the given memory region, and to give one or more requestor hardware devices associated with a different RGID value only write-only access to the given memory region. This can help define producer-consumer relationships between hardware devices so that devices that act as producers for a given step in the pipeline can be given write-only access, and devices that act as consumers of data produced by a given step in the pipeline are given read-only access. This can improve security by limiting the type of access allowed for a given RGID when accessing a given memory region.
上文論述的技術可在具有用於實施如上文所論述之功能之硬體電路系統邏輯的硬體設備中實施。因此，位址轉譯電路系統及屬性判定電路系統可包含硬體電路邏輯。然而，在其他實例中，用於控制主機資料處理設備以提供用於執行目標碼之指令執行環境的電腦程式可具備位址轉譯程式邏輯及屬性判定程式邏輯，其在軟體中進行與上文所論述之位址轉譯電路系統及位址轉譯電路系統等效的功能。例如，此對於使得為特定指令集架構編寫的目標碼能夠在可能不支援該指令集架構的主機電腦上執行可係有用的。主機電腦未提供之指令集架構所預期的功能可由模擬軟體來仿真，該模擬軟體為目標碼提供等效的指令執行環境，如若目標碼已經在實際支援指令集架構的硬體裝置上執行所預期的那樣。提供此一模擬對於一系列目的可係有用的，例如用於使得為一種指令集架構編寫的舊有碼能夠在支援不同指令集架構的不同平台上執行，或當支援新版本指令集架構的硬體裝置尚不可用時，用於輔助待為新版本指令集架構執行之新軟體的軟體開發（此可使得用於新版本架構的軟體能夠與支援新版本架構之硬體裝置的開發並行地開始開發）。The techniques discussed above may be implemented in hardware having hardware circuitry logic for implementing the functions discussed above. Thus, the address translation circuitry and the attribute determination circuitry may comprise hardware circuit logic. However, in other examples, a computer program for controlling a host data processing device to provide an instruction execution environment for executing target code may have address translation program logic and attribute determination program logic that perform equivalent functions in software to the address translation circuitry and address translation circuitry discussed above. This may be useful, for example, to enable target code written for a particular instruction set architecture to execute on a host computer that may not support that instruction set architecture. Functionality expected of an ISA not provided by the host computer can be simulated by emulation software, which provides the target code with an instruction execution environment equivalent to what the target code would have performed had it been executed on a hardware device that actually supports the ISA. Providing such emulation can be useful for a variety of purposes, such as enabling legacy code written for one ISA to run on a different platform supporting a different ISA, or to aid the development of new software to be run on a new ISA version when hardware devices supporting the new ISA are not yet available (this allows software development for the new ISA version to begin in parallel with the development of hardware devices supporting the new ISA).
現將參照圖式描述特定實例。Specific examples will now be described with reference to the drawings.
圖1示意地繪示具有用於回應於指令而進行資料處理之處理電路系統10之設備的實例。處理電路系統10可能能夠發布指定識別待存取之可定址位置之目標虛擬位址(virtual address, VA)的記憶體存取請求。位址轉譯電路系統16（例如，記憶體管理單元(memory management unit, MMU)）基於定義在儲存在記憶體系統中的頁表結構中的頁表資料而通過多級位址轉譯之一者將虛擬位址轉譯成實體位址(physical address, PA)。轉譯後備緩衝區(translation lookaside buffer, TLB) 18充當用於快取一些頁表資訊的查找快取記憶體，以用於在每次需要位址轉譯時，比若必需從記憶體提取頁表資訊更快的存取。FIG1 schematically illustrates an example of an apparatus having a processing circuitry 10 for performing data processing in response to an instruction. The processing circuitry 10 may be capable of issuing a memory access request that specifies a target virtual address (VA) identifying an addressable location to be accessed. Address translation circuitry 16 (e.g., a memory management unit (MMU)) translates the virtual address into a physical address (PA) through one of multiple levels of address translation based on page table data defined in a page table structure stored in the memory system. The translation lookaside buffer (TLB) 18 acts as a lookup cache for caching some page table information for faster access than if the page table information had to be fetched from memory each time an address translation is required.
除了提供位址轉譯之外，虛擬定址頁表結構中指定的頁表資料亦可指定用於控制是否允許對特定目標虛擬位址之記憶體存取的一些權限。用以定義此等權限的頁表結構一般由作業系統或超管理器控制，且存在如下風險：若攻擊者設法損害作業系統或超管理器，則由轉譯表結構定義的存取權限屬性可能不足以為某些敏感工作負載提供足夠的安全保證。In addition to providing address translation, the page table data specified in the virtual address page table structure can also specify permissions that control whether memory access to a specific target virtual address is allowed. The page table structure used to define these permissions is typically controlled by the operating system or hypervisor, and there is a risk that if an attacker manages to compromise the operating system or hypervisor, the access permission attributes defined by the translation table structure may not provide sufficient security for certain sensitive workloads.
因此，該設備亦包含屬性判定電路系統17，該屬性判定電路系統經組態以存取儲存在記憶體系統6、7中的實體定址表結構，以判定與記憶體存取請求的目標實體位址相關聯的屬性資訊。藉由在實體定址表（基於實體位址查找的表，且因此獨立於用以提供從虛擬位址到實體位址之映射的轉譯表結構）中定義屬性資訊，可提供超出由作業系統或超管理器控制的安全層之外的附加安全層，以降低攻擊可能導致對敏感處理工作負載使用的某些實體位址進行不當存取的風險。Therefore, the apparatus also includes an attribute determination circuit system 17 that is configured to access a physical address table structure stored in the memory system 6, 7 to determine attribute information associated with the target physical address of the memory access request. By defining attribute information in the physical address table (a table that is based on physical address lookups and is therefore independent of the translation table structure used to provide mappings from virtual addresses to physical addresses), an additional layer of security beyond that controlled by the operating system or hypervisor can be provided to reduce the risk that an attack may result in improper access to certain physical addresses used by sensitive processing workloads.
屬性資訊可用於控制對記憶體的存取。然而，屬性判定電路系統不需要僅在處理記憶體存取請求時存取屬性資訊，且在一些實例中，可在預期屬性資訊將與處理未來存取請求相關的情況下預載及快取某些屬性資訊。Attribute information can be used to control access to memory. However, attribute determination circuitry need not access attribute information only when processing a memory access request, and in some instances, may preload and cache certain attribute information in anticipation that the attribute information will be relevant to processing future access requests.
實體定址表結構包含對應於實體位址之顆粒的項。為了識別與目標實體位址相關聯的屬性資訊，屬性判定電路系統查找實體定址表結構，以識別對應於含有目標實體位址之實體位址之顆粒的項。The physical address table structure includes an entry corresponding to a particle of the physical address. To identify attribute information associated with the target physical address, the attribute determination circuitry searches the physical address table structure to identify an entry corresponding to the particle of the physical address containing the target physical address.
屬性判定電路系統使用由實體定址表結構的對應項指定的索引來識別一組屬性儲存位置19中的一者。屬性儲存位置19可經提供在暫存器或記憶體6中，且可從記憶體快取在快取記憶體7中。對應於目標實體位址的屬性資訊係由經選擇屬性儲存位置指定。因此，實體定址表結構不直接指定（全部）屬性資訊，而指定可用以從單獨的屬性儲存位置擷取屬性資訊之至少一部分的索引。The attribute determination circuitry uses the index specified by the corresponding entry of the physical address table structure to identify one of a set of attribute storage locations 19. The attribute storage locations 19 may be provided in register or memory 6 and may be cached from memory in cache 7. The attribute information corresponding to the target physical address is specified by the selected attribute storage location. Therefore, the physical address table structure does not directly specify (all) the attribute information, but rather specifies an index that can be used to retrieve at least a portion of the attribute information from a single attribute storage location.
與在實體定址表結構中直接指定屬性資訊的情況相比，索引的使用使得更多數目的獨立權限能夠與給定實體位址相關聯，因為儲存成本可能產生於屬性儲存位置而非實體定址表結構本身中。可用的索引編碼的數目一般小於可能的屬性組合的數目（以允許索引小於屬性資訊）。例如，N位元索引可指定多達2N個屬性儲存位置。然而，若存在多於2N個屬性資訊的編碼（此很可能係此種情形），則此意謂著屬性儲存位置的數目可能小於屬性之可能組合的數目，使得不可能表示該組屬性儲存位置中的每個屬性組合。然而，發明人已經認識到，一次僅可使用屬性資訊之可能編碼的子集，因此不是將屬性的各唯一組合指派其自身的屬性儲存位置，而是可在屬性儲存位置中提供常用的屬性資訊編碼子集。使用比屬性資訊更少的位元來編碼索引意謂著實體定址表結構的項可比其等直接指定屬性資訊（或指定索引，該索引全組屬性儲存位置中之一者，該位置可識別各可能編碼）更小，當大量實體位址顆粒與項相關聯且因此提供許多項時，此對於具有大實體位址空間之現代系統中的功率及面積開銷可係極其重要的。The use of an index allows a greater number of independent permissions to be associated with a given physical address than would be possible if the attribute information were specified directly in the physical address table structure, because the storage cost can be incurred in the attribute storage locations rather than in the physical address table structure itself. The number of available index encodings is generally smaller than the number of possible attribute combinations (to allow the index to be smaller than the attribute information). For example, an N-bit index can specify up to2N attribute storage locations. However, if there are more than2N attribute information encodings (which is likely the case), this means that the number of attribute storage locations may be smaller than the number of possible attribute combinations, making it impossible to represent every attribute combination in the set of attribute storage locations. However, the inventors have recognized that only a subset of the possible encodings of the attribute information may be used at a time, so rather than assigning each unique combination of attributes its own attribute storage location, a commonly used subset of attribute information encodings may be provided in the attribute storage locations. Using fewer bits to encode the index than the attribute information means that entries in the physical address table structure can be smaller than if they directly specified the attribute information (or specified an index into one of a set of attribute storage locations that identifies each possible encoding). This can be a significant power and area overhead in modern systems with large physical address spaces when a large number of physical address particles are associated with the entry and therefore many entries are provided.
在該組屬性儲存位置中表示屬性資訊而非實體定址表結構本身之項的額外益處係可使屬性資訊的更新變得更簡單。例如，若若干項共用相同的屬性資訊，則若直接在項中指定屬性資訊，則需要更新該等若干項之各者。相較之下，當項替代地指定指向該屬性儲存位置的相同索引時，僅需要對屬性儲存位置進行一次更新。An additional benefit of representing attribute information in the set of attribute storage locations rather than in the entries of the physical address table structure itself is that updating the attribute information becomes simpler. For example, if several entries share the same attribute information, specifying the attribute information directly in the entry requires updating each of those entries. In contrast, if the entry instead specifies the same index pointing to the attribute storage location, only a single update of the attribute storage location is required.
圖2更詳細地繪示實體定址表結構及該組屬性儲存位置的實例。圖2的實體定址表結構經繪示為單一線性結構，儘管如稍後進一步詳細論述的，亦可被提供為多層表結構。從記憶體存取請求指定的目標虛擬位址轉譯而來的目標實體位址用以查找實體定址表結構。識別對應於包含目標實體位址之實體位址顆粒的項，其中對應項指定索引。FIG2 illustrates an example of a physical address table structure and the location where the set of attributes are stored in greater detail. The physical address table structure of FIG2 is illustrated as a single linear structure, although, as discussed in further detail later, it may also be provided as a multi-level table structure. The target physical address, which is translated from the target virtual address specified in the memory access request, is used to look up the physical address table structure. The entry corresponding to the physical address granule containing the target physical address is identified, where the corresponding entry specifies an index.
由實體定址表結構的對應項指定的索引用以在一組屬性儲存位置中選擇給定屬性儲存位置。屬性判定電路系統經組態以從給定屬性儲存位置判定對應於目標實體位址的屬性資訊。The index specified by the corresponding entry of the physical address table structure is used to select a given attribute storage location from a set of attribute storage locations. The attribute determination circuit system is configured to determine attribute information corresponding to the target physical address from the given attribute storage location.
實體定址表結構及該組屬性儲存位置二者均可提供在記憶體中。替代地，該組屬性儲存位置可儲存在暫存器中。當儲存在記憶體中時，該組屬性儲存位置可本地快取到屬性判定電路系統，以便更快存取。Both the physical address table structure and the set of attribute storage locations may be provided in memory. Alternatively, the set of attribute storage locations may be stored in registers. When stored in memory, the set of attribute storage locations may be locally cached to the attribute determination circuitry for faster access.
儘管圖2顯示僅指定索引之實體定址表結構的各項，但在其他實例中，除了在對應屬性儲存位置中指定的屬性之外，項仍可指定其他屬性。然而，相較於虛擬定址頁表結構的項，實體定址結構的項不需要包括對應於項的位址轉譯。此意謂著在一些實例中，項可僅包含索引，若將間接應用於頁表結構，則此係不可能的。Although Figure 2 shows the entries of the physical address table structure specifying only indexes, in other instances, entries can specify additional attributes in addition to the attributes specified in the corresponding attribute storage location. However, unlike entries in the virtual address page table structure, entries in the physical address structure do not need to include the address translation corresponding to the entry. This means that in some instances, an entry can contain only an index, which is not possible if the indirect application is used for the page table structure.
圖3示意地繪示具有至少一個請求者裝置4及至少一個完成者裝置6之資料處理系統2的實例。互連8提供請求者裝置4與完成者裝置6之間的通訊。請求者裝置能夠發布請求對特定可定址記憶體系統位置的記憶體存取的記憶體存取請求。完成者裝置6係具有服務指向其之記憶體存取請求之責任的裝置。雖然未顯示於圖3中，一些裝置可能能夠充當請求者裝置及充當完成者裝置二者。請求者裝置4可例如包括處理元件（諸如中央處理單元(central processing unit, CPU)或圖形處理單元(graphics processing unit, GPU)）或其他主裝置（諸如匯流排主裝置、網路介面控制器、顯示器控制器）等。完成者裝置可包括負責控制對對應記憶體儲存單元之存取的記憶體控制器、用於控制對周邊裝置之存取的周邊控制器等。圖3更詳細地顯示請求者裝置4之一者的實例組態，但應理解其他請求者裝置4可具有類似組態。替代地，其他請求者裝置可具有與圖3左側所示的請求者裝置4不同的組態（例如，如下文更詳細論述的圖4所示，在一些情形中，另一請求者裝置4可係系統記憶體管理單元(system memory management unit, SMMU)，其具有位址轉譯電路系統16及PAS過濾器20，但不具有圖3所示的處理電路系統10）。FIG3 schematically illustrates an example of a data processing system 2 having at least one requester device 4 and at least one completer device 6. Interconnect 8 provides communication between requester device 4 and completer device 6. A requester device can issue memory access requests requesting memory access to a specific addressable memory system location. Completer device 6 is the device with the responsibility of servicing memory access requests directed to it. Although not shown in FIG3 , some devices may be capable of acting as both a requester device and a completer device. Requester device 4 may include, for example, a processing element (such as a central processing unit (CPU) or a graphics processing unit (GPU)) or other host devices (such as a bus host, a network interface controller, or a display controller). A completer device may include a memory controller responsible for controlling access to corresponding memory storage units, a peripheral controller for controlling access to peripheral devices, and the like. FIG3 illustrates an example configuration of one of requester devices 4 in greater detail, but it should be understood that other requester devices 4 may have similar configurations. Alternatively, other requestor devices may have a different configuration than the requestor device 4 shown on the left side of FIG. 3 (for example, as shown in FIG. 4 discussed in more detail below, in some cases, another requestor device 4 may be a system memory management unit (SMMU), which has address translation circuitry 16 and PAS filter 20 but does not have the processing circuitry 10 shown in FIG. 3 ).
圖3所示的請求者裝置4具有用於回應於指令而參考儲存在暫存器12中的資料進行資料處理的處理電路系統10。暫存器12可包括用於儲存運算元及經處理指令之結果的通用暫存器，以及用於儲存用於組態處理如何由處理電路系統執行的控制資料的控制暫存器。例如，控制資料可包括用以選擇哪個操作域係目前域的目前域指示14，及指示哪個例外等級係處理電路系統10正在操作的目前例外等級的目前例外等級指示15。The requester device 4 shown in FIG3 has a processing circuit system 10 for processing data in response to instructions with reference to data stored in registers 12. Registers 12 may include general registers for storing operands and results of processed instructions, and control registers for storing control data for configuring how processing is performed by the processing circuit system. For example, the control data may include a current domain indicator 14 for selecting which operating domain is the current domain, and a current exception level indicator 15 for indicating which exception level is the current exception level being operated by the processing circuit system 10.
處理電路系統10可能能夠發布指定識別待存取之可定址位置的虛擬位址(VA)的記憶體存取請求及識別目前域的域識別符（域ID或「安全狀態」）。位址轉譯電路系統16（例如，記憶體管理單元(MMU)）基於定義在儲存在記憶體系統中的頁表結構中的頁表資料而通過多級位址轉譯之一者將虛擬位址轉譯成實體位址(PA)。轉譯後備緩衝區(TLB) 18充當用於快取一些頁表資訊的查找快取記憶體，以用於在每次需要位址轉譯時，比若必需從記憶體提取頁表資訊更快的存取。在此實例中，除了產生實體位址外，位址轉譯電路系統16亦選擇若干個實體位址空間之與該實體位址關聯之一者，並輸出識別經選擇實體位址空間的實體位址空間(PAS)識別符。PAS的選擇將於下文更詳細地論述。Processing circuitry 10 may be capable of issuing a memory access request specifying a virtual address (VA) identifying an addressable location to be accessed and a domain identifier (domain ID or "security state") identifying the current domain. Address translation circuitry 16 (e.g., a memory management unit (MMU)) translates the virtual address into a physical address (PA) through one of multiple levels of address translation based on page table data defined in a page table structure stored in the memory system. Translation lookaside buffer (TLB) 18 acts as a lookup cache for caching some page table information, allowing for faster access than if the page table information had to be fetched from memory each time an address translation is needed. In this example, in addition to generating a physical address, the address translation circuitry 16 also selects one of several physical address spaces to be associated with the physical address and outputs a physical address space (PAS) identifier that identifies the selected physical address space. The selection of the PAS will be discussed in more detail below.
PAS過濾器20充當用於基於經轉譯實體位址及PAS識別符檢查是否允許該實體位址在由PAS識別符識別的經指定實體位址空間內存取的檢查電路系統。此查找係基於使用儲存在記憶體系統內的顆粒保護表結構（其係實體定址表結構）來存取的顆粒保護資訊（其係上文所論述之屬性資訊的實例）。如上文所論述，對應於目標PA之顆粒保護表的項指定索引，且從屬性儲存位置（未示出，儘管此可係暫存器12內或記憶體內的位置，例如在完成者裝置6處）擷取顆粒保護資訊。一旦使用實體定址顆粒保護表從屬性儲存位置擷取顆粒保護資訊，顆粒保護資訊就可經快取在顆粒保護資訊快取記憶體22內，類似於TLB 18中頁表資料的快取。雖然在圖3的實例中將顆粒保護資訊快取記憶體22顯示成係與TLB 18分開的結構，在其他實例中，可將此等類型的查找快取記憶體組合成單一查找快取記憶體結構，使得經組合結構之項的單一查找提供頁表資訊及顆粒保護資訊二者。顆粒保護資訊定義限制給定實體位址可自其存取之實體位址空間的資訊，且基於此查找，PAS過濾器20判定是否允許記憶體存取請求繼續進行以發布至一或多個快取記憶體24及/或互連8。若不允許記憶體存取請求的經指定PAS存取經指定實體位址，則PAS過濾器20阻止交易且可傳訊故障。The PAS filter 20 acts as a checking circuit system for checking, based on the translated physical address and the PAS identifier, whether the physical address is allowed to be accessed within the specified physical address space identified by the PAS identifier. This lookup is based on accessing particle protection information (which is an example of the attribute information discussed above) stored in a particle protection table structure (which is a physical address table structure) within the memory system. As discussed above, the entry of the particle protection table corresponding to the target PA specifies an index and retrieves the particle protection information from the attribute storage location (not shown, although this can be a location within the register 12 or within memory, such as at the completer device 6). Once the granule protection information is retrieved from the attribute storage location using the physically addressed granule protection table, the granule protection information may be cached in the granule protection information cache 22, similar to the caching of page table data in the TLB 18. Although the granule protection information cache 22 is shown as a separate structure from the TLB 18 in the example of FIG3 , in other examples, these types of lookup caches may be combined into a single lookup cache structure such that a single lookup of an entry of the combined structure provides both page table information and granule protection information. The granular protection information defines information that restricts the physical address space from which a given physical address can access, and based on this lookup, the PAS filter 20 determines whether to allow the memory access request to proceed for issuance to one or more caches 24 and/or the interconnect 8. If the specified PAS of the memory access request is not allowed to access the specified physical address, the PAS filter 20 blocks the transaction and may signal a fault.
雖然圖3顯示具有多個請求者裝置4之系統的實例，針對圖3左側的一個請求者裝置顯示的特徵亦可包括在僅有一個請求者裝置（諸如單核心處理器）的系統中。Although FIG3 shows an example of a system having multiple requester devices 4, the features shown for one requester device on the left side of FIG3 may also be included in a system having only one requester device (e.g., a single-core processor).
雖然圖3顯示用於給定請求之PAS的選擇係由位址轉譯電路系統16執行的實例，在其他實例中，用於判定選擇哪個PAS的資訊可連同PA由位址轉譯電路系統16輸出至PAS過濾器20，且PAS過濾器20可選擇PAS且檢查是否允許PA在經選擇PAS內存取。因此，PAS選擇電路系統可由位址轉譯電路系統16或PAS過濾器20或二者一起工作來提供。Although FIG3 shows an example in which the selection of a PAS for a given request is performed by the address translation circuitry 16, in other examples, information used to determine which PAS to select may be output by the address translation circuitry 16 along with the PA to the PAS filter 20, and the PAS filter 20 may select the PAS and check whether the PA is allowed access within the selected PAS. Thus, the PAS selection circuitry may be provided by the address translation circuitry 16 or the PAS filter 20, or both working together.
PAS過濾器20的提供幫助支援可在若干個操作域中操作的系統，該等操作域各與其自身的經隔離實體位址空間關聯，其中對於至少部分的記憶體系統（例如，對於一些快取記憶體或一致性強制機制，諸如監聽過濾器），將分開的實體位址空間視為彷彿其等參考至識別分開的記憶體系統位置的完全分開的位址組，即使在彼等位址空間內的位址實際上參考至記憶體系統中的相同實體位置。此對安全目的可係有用的。The provision of the PAS filter 20 helps support systems that can operate in several operational domains, each associated with its own isolated physical address space, where the separate physical address spaces are treated by at least part of the memory system (e.g., by some cache or consistency enforcement mechanisms such as snoop filters) as if they were completely separate sets of addresses that reference locations identifying separate memory systems, even though the addresses within those address spaces actually reference the same physical location in the memory system. This can be useful for security purposes.
圖3的上述實例顯示請求者裝置4內的位址轉譯電路系統16及PAS過濾器20（檢查電路系統）以及由位址轉譯電路系統16及PAS過濾器20中的一者或二者表示的PAS選擇電路系統，該請求者裝置可例如係處理器，諸如CPU、GPU、或其他能夠執行來自指令集架構之程式指令的其他處理單元。The above example of FIG. 3 shows an address translation circuit system 16 and a PAS filter 20 (checking circuit system) within a requester device 4, which may be, for example, a processor such as a CPU, a GPU, or other processing unit capable of executing program instructions from an instruction set architecture, and a PAS selection circuit system represented by one or both of the address translation circuit system 16 and the PAS filter 20.
然而，如圖4所示，由此一請求者裝置4（例如圖4之實例中的CPU）存取的記憶體系統可經共用以亦可由一或多個其他裝置252存取，該一或多個其他裝置可經由系統記憶體管理單元（SMMU，亦稱為輸入/輸出記憶體管理單元或IOMMU）250存取記憶體。SMMU 250可係圖3所示之其他請求者裝置4的實例。However, as shown in FIG4 , the memory system accessed by one requester device 4 (e.g., the CPU in the example of FIG4 ) may be shared and also accessed by one or more other devices 252, which may access the memory via a system memory management unit (SMMU, also known as an input/output memory management unit or IOMMU) 250. SMMU 250 may be an example of the other requester device 4 shown in FIG3 .
裝置252可例如包括在CPU 4與外界之間提供介面的周邊裝置或I/O裝置（例如，裝置可包括顯示控制器、網路控制器、使用者介面控制器、用於存取外部裝置外儲存的記憶體控制制器等）。而且，裝置252可包括硬體加速器，該等硬體加速器被提供來使用專用硬體來加速定製處理任務，該專用硬體可比CPU 4提供的通用處理器硬體更有效地進行此任務。例如，可提供硬體加速器來加速諸如密碼操作的功能及諸如神經網路處理的機器學習任務。使用硬體加速器亦可有助於卸載在CPU 4處正在進行之處理之後台進行的某些記憶體密集型任務。Devices 252 may include, for example, peripheral devices or I/O devices that provide an interface between CPU 4 and the outside world (e.g., devices may include a display controller, a network controller, a user interface controller, a memory controller for accessing external storage, etc.). Furthermore, devices 252 may include hardware accelerators, which are provided to accelerate custom processing tasks using specialized hardware that can perform such tasks more efficiently than the general-purpose processor hardware provided by CPU 4. For example, hardware accelerators may be provided to accelerate functions such as cryptographic operations and machine learning tasks such as neural network processing. The use of hardware accelerators may also help offload certain memory-intensive tasks that are performed in the background of processing being performed by CPU 4.
由於裝置252可能不具能夠基於由CPU 4使用之頁表定義的豐富記憶體映射將虛擬位址轉譯成實體位址之其等自身的位址轉譯電路系統，因此可提供SMMU 250作為系統組件以從裝置252接收指定虛擬位址的請求，且代表裝置進行所需的位址轉譯。Because the device 252 may not have its own address translation circuitry capable of translating virtual addresses into physical addresses based on the rich memory mapping defined by the page tables used by the CPU 4, an SMMU 250 may be provided as a system component to receive requests from the device 252 specifying a virtual address and perform the required address translation on behalf of the device.
因此，在一些系統中，SMMU 250可具備類似於圖3所示的位址轉譯電路系統16及PAS過濾器20，其中PAS過濾器20充當用於檢查由顆粒保護資訊定義之權限的檢查電路系統，且SMMU 250的位址轉譯電路系統16及PAS過濾器20中的一者或二者提供稍早描述的PAS選擇電路系統。因此，SMMU 250亦可支援對多個實體位址空間的存取及基於顆粒保護資訊的第三階段檢查，如圖9所示。位址轉譯電路系統16及PAS過濾器20因此可以與如上文所論述之相同的方式操作。SMMU 250可具有類似圖3所示之請求者4中之對應快取結構的TLB 18及/或GPI快取記憶體22。Thus, in some systems, the SMMU 250 may have an address translation circuitry 16 and a PAS filter 20 similar to those shown in FIG3 , wherein the PAS filter 20 serves as the checking circuitry for checking permissions defined by the granule protection information, and one or both of the address translation circuitry 16 and the PAS filter 20 of the SMMU 250 provide the PAS selection circuitry described earlier. Thus, the SMMU 250 may also support access to multiple physical address spaces and third-stage checking based on granule protection information, as shown in FIG9 . The address translation circuitry 16 and the PAS filter 20 may thus operate in the same manner as discussed above. SMMU 250 may have a TLB 18 and/or GPI cache 22 with corresponding cache structures similar to those in requester 4 shown in FIG. 3 .
在待論述的一些實例中，其中可基於發布記憶體存取請求的域來過濾存取請求，SMMU 250的PAS過濾器20需要關於哪個域（安全狀態）與從裝置252接收到的記憶體存取請求相關聯的資訊。SMMU 250將無法存取CPU的系統暫存器12，該等系統暫存器定義暫存器狀態14，該暫存器狀態定義目前操作域，且在任何情形下，由給定裝置252發送的請求可與在CPU 4處活動的目前域以外之域中的處理相關。因此，在圖4所示的方法中，由裝置252發送到SMMU 250的記憶體存取請求可指定識別與記憶體存取請求相關聯之域的域識別符。例如，各裝置252可維護資料結構，該資料結構針對指派給該裝置的各工作負載識別對應域識別符（其可例如在將工作指派給該裝置時基於與導致將工作指派給該裝置的軟體相關聯的目前域14來設定）。當向SMMU 250發布記憶體存取請求時，裝置252可使用此資料結構來選擇在提供給SMMU 250的域識別符中指定哪個域。來自裝置的記憶體存取請求與特定域識別符值相關聯的特定機制可取決於裝置的特定目的及軟體開發者選擇的用於向裝置252指派工作負載的機制，因此可能不係系統硬體的所需特徵。然而，通常，用於提供允許域識別符連同記憶體存取請求由裝置252提供給SMMU 250之信號路徑的硬體支援意謂著SMMU 250內的PAS過濾器20可使用與記憶體存取請求相關聯的域而不僅僅係經選擇PAS來實施保護檢查。In some examples to be discussed, in which memory access requests may be filtered based on the domain from which they are issued, the PAS filter 20 of the SMMU 250 requires information about which domain (security state) is associated with a memory access request received from a device 252. The SMMU 250 will not be able to access the CPU's system registers 12, which define the register state 14 that defines the current operating domain, and in any case, a request sent by a given device 252 may be associated with a process in a domain other than the current domain active at the CPU 4. Thus, in the method illustrated in FIG4 , a memory access request sent by a device 252 to the SMMU 250 may specify a domain identifier that identifies the domain associated with the memory access request. For example, each device 252 may maintain a data structure that identifies a corresponding domain identifier for each workload assigned to the device (which may be set, for example, when the workload is assigned to the device based on the current domain 14 associated with the software that caused the workload to be assigned to the device). When issuing a memory access request to the SMMU 250, the device 252 may use this data structure to select which domain to specify in the domain identifier provided to the SMMU 250. The specific mechanism by which a memory access request from a device is associated with a particular domain identifier value may depend on the specific purpose of the device and the mechanism chosen by the software developer for assigning workloads to the device 252, and therefore may not be a desired feature of the system hardware. However, generally, hardware support for providing a signal path that allows a domain identifier to be provided by the device 252 to the SMMU 250 along with a memory access request means that the PAS filter 20 within the SMMU 250 can use the domain associated with the memory access request, rather than just the selected PAS, to perform protection checks.
如圖4的實例所示，互連8可包括系統快取記憶體300，該系統快取可係前PoPA記憶體系統組件的實例，該前PoPA記憶體系統組件將來自不同PAS的別名實體位址視為其等對應於不同的記憶體系統資源一般。As shown in the example of FIG. 4 , interconnect 8 may include a system cache 300, which may be an instance of a pre-PoPA memory system component that treats aliased physical addresses from different PASs as if they correspond to different memory system resources.
圖5顯示處理電路系統10可在其中操作的不同操作狀態及域的實例，及可在不同例外等級及域中執行之軟體之類型的實例（當然，應理解安裝在系統上的特定軟體係由管理該系統的管理方選擇且因此係非硬體架構的基本特徵）。Figure 5 shows examples of different operating states and domains in which the processing circuit system 10 can operate, and examples of the types of software that can execute in different exception levels and domains (of course, it should be understood that the specific software installed on the system is selected by the administrator who manages the system and is therefore not an essential feature of the hardware architecture).
處理電路系統10可在數個不同的例外等級80操作，在此實例中，標記為EL0、EL1、EL2、及EL3的四個例外等級，其中在此實例中，EL3係指具有最大特權等級的例外等級，而EL0係指具有最小特權的例外等級。應理解其他架構可選擇相反的編號，使得可將具有最高數目的例外等級視為具有最低特權。在此實例中，最小特權例外等級EL0係用於應用程式層級碼、次一最高特權例外等級EL1係用於作業系統層級碼、次一最高特權例外等級EL2係用於管理若干個虛擬化作業系統之間的切換的超管理器層級碼、而最高特權例外等級EL3係用於管理各別域之間的切換及實體位址至實體位址空間之分配的監測碼，如稍後描述的。The processing circuit system 10 can operate at several different exception levels 80, in this example, four exception levels labeled EL0, EL1, EL2, and EL3, where in this example, EL3 is the exception level with the highest privilege and EL0 is the exception level with the lowest privilege. It should be understood that other architectures may choose the opposite numbering, such that the exception level with the highest number is considered the least privileged. In this example, the least privileged exception level EL0 is used for application-level code, the next most privileged exception level EL1 is used for operating system-level code, the next most privileged exception level EL2 is used for hypervisor-level code that manages switching between several virtualized operating systems, and the most privileged exception level EL3 is used for monitor code that manages switching between domains and allocation of physical addresses to physical address space, as described later.
當例外在處理在特定例外等級中之軟體的同時發生時，對於一些類型的例外，將該例外取至更高（更多特權）的例外等級，其中該例外取至其的特定例外等級係基於所發生之特定例外的屬性選擇。然而，在一些情況下，其他類型的例外在與採取例外時正在處理之碼關聯的例外等級相同的例外等級採取可係可能的。當採取例外時，可儲存描述處理器在採取例外時之狀態的特性的資訊，包括例如在採取例外時的目前例外等級，且因此一旦例外處置器已經處理以應付該例外時，處理可接著返回至先前處理且經儲存資訊可用以識別處理應返回的例外等級。When an exception occurs while processing software within a particular exception level, for some types of exceptions, the exception is taken to a higher (more privileged) exception level, where the particular exception level to which the exception is taken is selected based on the properties of the particular exception that occurred. However, in some cases, it may be possible for other types of exceptions to be taken at the same exception level as the exception level associated with the code being processed when the exception is taken. When an exception is taken, information describing the characteristics of the state of the processor at the time the exception is taken may be stored, including, for example, the current exception level at the time the exception was taken, so that once the exception handler has processed to address the exception, processing can then return to the previous processing and the stored information can be used to identify the exception level to which processing should return.
除了不同的例外等級外，處理電路系統亦支援包括數個操作域（亦稱為「安全性狀態」），該等域包括根域82、安全(S)域84、較不安全域86、及領域域88的。為便於參考，較不安全域將於下文描述為「非安全」(non-secure, NS)域，但應理解此未意圖暗示任何特定的安全（或缺乏安全）等級。替代地，「非安全(non-secure)」僅指示非安全域意圖用於比在安全域中操作之碼更不安全的碼。當處理電路系統10在最高例外等級EL3時，選擇根域82。當處理電路系統在其他例外等級EL0至EL2之一者中時，目前域係基於指示其他域84、86、88的何者係使用中的目前域指示符14選擇。對於其他域84、86、88之各者，處理電路系統可在例外等級EL0、EL1、或EL2的任一者中。In addition to different exception levels, the processing circuitry also supports several operating domains (also referred to as "security states"), including a root domain 82, a secure (S) domain 84, a less secure domain 86, and a domain domain 88. For ease of reference, the less secure domain will be described below as a "non-secure" (NS) domain, but it should be understood that this is not intended to imply any particular level of security (or lack thereof). Instead, "non-secure" simply indicates that the non-secure domain is intended for code that is less secure than code operating in the secure domain. When the processing circuitry 10 is at the highest exception level, EL3, the root domain 82 is selected. When the processing circuitry is in one of the other exception levels, EL0 through EL2, the current domain is selected based on a current domain indicator 14 indicating which of the other domains 84, 86, 88 is in use. For each of the other domains 84, 86, 88, the processing circuitry may be in any of the exception levels EL0, EL1, or EL2.
在啟動時間，數個啟動碼區段（例如，BL1、BL2、OEM啟動）可例如在更高特權例外等級EL3或EL2內執行。例如，啟動碼BL1、BL2可與根域關聯且OEM啟動碼可在安全域中操作。然而，一旦系統經啟動，在運行時間，可將處理電路系統10視為每次在域82、84、86、及88之一者中操作。域82至88之各者與其自身之經關聯實體位址空間(PAS)關聯，其使資料能在至少部分的記憶體系統內與不同域隔離。此將於下文更詳細地描述。At boot time, several boot code segments (e.g., BL1, BL2, OEM boot) may execute, for example, within a more privileged exception level, EL3 or EL2. For example, boot code BL1 and BL2 may be associated with the root domain, and OEM boot code may operate in the secure domain. However, once the system is booted, at runtime, processing circuitry 10 may be considered to be operating in one of domains 82, 84, 86, and 88 at a time. Each of domains 82 through 88 is associated with its own associated physical address space (PAS), which enables data isolation between different domains within at least a portion of the memory system. This will be described in more detail below.
非安全域86可用於常規應用程式層級處理，及用於管理此類應用程式的作業系統及超管理器活動。因此，在非安全域86內，可存在在EL0操作的應用程式碼30、在EL1操作的作業系統(OS)碼32、及在EL2操作的超管理器碼34。The non-secure domain 86 may be used for conventional application-level processing, and for managing operating system and hypervisor activities for such applications. Thus, within the non-secure domain 86, there may be application code 30 operating at EL0, operating system (OS) code 32 operating at EL1, and hypervisor code 34 operating at EL2.
安全域84使某些系統單晶片安全性、媒體、或系統服務能隔離至與用於非安全處理的實體位址空間分開的實體位址空間中。安全及非安全域就非安全域碼無法存取與安全域84關聯的資源而安全域可存取安全及非安全資源二者的意義上而言並不相等（至少對於未定義下面進一步描述的預定較低安全記憶體性質的記憶體區域）。支援安全域84及非安全域86之此類分割之系統的實例係基於由Arm®Limited提供的TrustZone®架構的系統。安全域可在EL0運行受信任應用程式36、在EL1運行受信任作業系統38、以及可選地在EL2運行安全分割管理器40，若支援安全分割，該安全分割管理器可使用2階頁表以與超管理器34可以其管理在非安全域86中執行之虛擬機器或客作業系統32之間的隔離的方式類似的方式支援在安全域84中執行的不同受信任作業系統38之間的隔離。The secure domain 84 enables certain SoC security, media, or system services to be isolated in a physical address space separate from the physical address space used for non-secure processing. The secure and non-secure domains are not equivalent in the sense that non-secure domain code cannot access resources associated with the secure domain 84, while the secure domain can access both secure and non-secure resources (at least with respect to memory regions that do not define the properties of the predetermined less secure memory described further below). An example of a system that supports such a partitioning of the secure domain 84 and the non-secure domain 86 is a system based on theTrustZone® architecture provided byArm® Limited. The secure domain can run trusted applications 36 at EL0, a trusted operating system 38 at EL1, and optionally a secure partitioning manager 40 at EL2. If secure partitioning is supported, the secure partitioning manager can use a two-level page table to support isolation between different trusted operating systems 38 running in the secure domain 84 in a manner similar to the way the hypervisor 34 can manage isolation between virtual machines or guest operating systems 32 running in the non-secure domain 86.
延伸系統以支援安全域84由於其使單一硬體處理器能支援經隔離安全處理，避免在單獨硬體處理器上執行該處理的需求而在近年變得普遍。然而，隨著安全域的使用日益普遍，具有此一安全域的許多實際系統現在在安全域內支援由範圍廣泛的不同軟體提供商提供的相對複雜的混合服務環境。例如，在安全域84中操作的碼可包括由（尤其）下列提供的不同軟體區段：製造積體電路的矽供應商、將由矽供應商提供的積體電路組裝成電子裝置（諸如行動電話）的原始設備製造商(original equipment manufacturer, OEM)、提供用於裝置之作業系統32的作業系統廠商(operating system vendor, OSV)；及/或管理通過雲端支援用於若干個不同用戶端之服務的雲端伺服器的雲端平台供應商。Extending systems to support security domains 84 has become common in recent years because it enables a single hardware processor to support isolated secure processing, avoiding the need to run that processing on a separate hardware processor. However, as the use of security domains has become more common, many actual systems with such security domains now support a relatively complex mixed service environment within the security domain provided by a wide range of different software vendors. For example, the code operating in the secure domain 84 may include different software segments provided by, among other things: a silicon supplier that manufactures integrated circuits; an original equipment manufacturer (OEM) that assembles the integrated circuits provided by the silicon supplier into an electronic device (such as a mobile phone); an operating system vendor (OSV) that provides an operating system 32 for the device; and/or a cloud platform provider that manages a cloud server that supports services for a number of different clients via the cloud.
然而，提供使用者層級碼（通常可預期其執行為在非安全域86內的應用程式30）的供應方對於具有可被信任不將資訊洩露給在相同實體平台上的其他方操作碼的安全計算環境的期望逐漸增加。此類安全計算環境在運行時間可動態地分配、及認證、及可證明，使得使用者在信任該裝置處理可能敏感的碼或資料之前能夠驗證是否在實體平台上提供足夠的安全保證可係所欲的。此類軟體的使用者可能不希望信任提供通常可能在非安全域86中操作之富作業系統32或超管理器34的供應方（或即使彼等供應商本身可被信任，使用者可能希望保護自身免於作業系統32或超管理器34為攻擊者所損害）。再者，雖然安全域84可用於需要安全處理的此類使用者提供應用程式，實際上，此對於提供需要安全計算環境之碼的使用者及對於在安全域84內操作之現有碼的供應商雙方導致問題。對於在安全域84內操作之現有碼的供應商，將任意使用者提供碼添加在安全域內會增加潛在攻擊其等碼的攻擊表面，其可係非所欲的，且因此可能強烈地勸阻允許使用者將碼添加至安全域84中。另一方面，提供需要安全計算環境之碼的使用者可能不願意信任在安全域84中操作的不同碼區段的所有供應商具有對其資料或碼的存取，若需要認證或證明在特定域中操作的碼以作為使用者提供碼執行其處理的先決條件，可能難以審核及認證由不同軟體供應商提供之在安全域84中操作的所有不同碼區段，其可能限制第三方提供更安全服務的機會。However, there is an increasing desire among vendors of user-level code (which is typically expected to execute as an application 30 within a non-secure domain 86) to have a secure computing environment that can be trusted not to leak information to other parties operating code on the same physical platform. Such a secure computing environment can be dynamically allocated, authenticated, and certifiable at runtime, so that users can verify that sufficient security guarantees are desirable on the physical platform before trusting the device to process potentially sensitive code or data. Users of such software may not want to trust vendors that provide rich operating systems 32 or hypervisors 34 that might typically operate in a non-secure domain 86 (or even if the vendors themselves can be trusted, users may want to protect themselves from having their operating systems 32 or hypervisors 34 compromised by attackers). Furthermore, while security domain 84 may be used for such user-provided applications that require secure processing, in practice this creates problems for both users who provide code that requires a secure computing environment and for vendors of existing code that operates within security domain 84. For vendors of existing code that operates within security domain 84, adding arbitrary user-provided code within the security domain increases the potential attack surface for their code, which may be undesirable, and therefore there may be strong disincentives to allow users to add code to security domain 84. On the other hand, users who provide code that requires a secure computing environment may not be willing to trust all suppliers of different code segments operating in security domain 84 with access to their data or code. If authentication or proof of code operating in a specific domain is required as a prerequisite for user-provided code to perform its processing, it may be difficult to review and authenticate all different code segments operating in security domain 84 provided by different software suppliers, which may limit the opportunities for third parties to provide more secure services.
因此，如圖5所示，提供稱為領域域的額外較高安全域88，其可由此類使用者引入碼使用以提供正交於與在安全域24中操作之組件關聯的任何安全計算環境的安全計算環境。在領域域中，所執行的軟體可包括若干個領域，其中各領域可藉由在例外等級EL2操作的領域管理模組(realm management module, RMM) 46與其他領域隔離。RMM 46可控制執行領域域88的各別領域42、44之間的隔離，例如，藉由類似於超管理器34以其管理在非安全域86中操作的不同組件之間的隔離的方式將存取權限及位址映射定義在頁表結構中。在此實例中，領域包括在EL0執行的應用程式層級領域42，及橫跨例外等級EL0及EL1執行的經封裝應用程式/作業系統領域44。應理解支援EL0及EL0/EL1類型的領域係非必要的，且相同類型的多個領域可由RMM 46建立。5 , an additional higher security domain 88, referred to as the realm domain, is provided that can be used by such user-introduced code to provide a secure computing environment that is orthogonal to any secure computing environment associated with components operating in the secure domain 24. Within the realm domain, the software executed may include a number of realms, each of which may be isolated from the other realms by a realm management module (RMM) 46 operating at exception level EL2. The RMM 46 may control the isolation between the respective realms 42, 44 executing the realm domain 88, for example, by defining access permissions and address mappings in page table structures in a manner similar to how the hypervisor 34 manages isolation between different components operating in the non-secure domain 86. In this example, the domains include an application-level domain 42 that executes at EL0, and a packaged application/operating system domain 44 that executes across exception levels EL0 and EL1. It should be understood that supporting both EL0 and EL0/EL1 type domains is not required, and multiple domains of the same type may be created by RMM 46.
領域域88具有類似於安全域84之分配給其之其自身的實體位址空間，但就領域域88及安全域84可各存取與非安全域86關聯的非安全PAS的同時，領域域88及安全域84無法存取彼此的實體位址空間的意義上而言，領域域正交於安全域84。此意謂著在領域域88及安全域84中執行的碼彼此不具有相依性。領域域中的碼僅需要信任硬體、RMM 46、及在根域82中操作之管理域之間的切換的碼，其意謂著證明及認證變得更可行。證明使給定軟體區段能請求安裝在裝置上的碼匹配某些預期性質的驗證。此可藉由檢查安裝在裝置上之程式碼的雜湊是否匹配由受信任方使用密碼協定簽署的預期值而實施。例如，RMM 46及監測碼29可藉由檢查此軟體的雜湊是否匹配由受信任方（諸如製造包含處理系統2之積體電路的矽供應商，或設計支援基於域之記憶體存取控制之處理器架構的架構供應商）簽署的預期值而證明。此可允許使用者提供碼42、44在執行任何安全或敏感功能之前驗證基於域之架構的完整性是否可信任。Domain domain 88 has its own physical address space allocated to it, similar to secure domain 84. However, domain domain 88 is orthogonal to secure domain 84 in that, while domain domain 88 and secure domain 84 can each access the non-secure PAS associated with non-secure domain 86, domain domain 88 and secure domain 84 cannot access each other's physical address space. This means that the code executing in domain domain 88 and secure domain 84 has no dependencies on each other. Code in the domain domain only needs to trust the hardware, RMM 46, and the code switching between management domains operating in root domain 82, which means that certification and authentication become more feasible. Certification enables a given piece of software to request verification that the code installed on a device matches certain expected properties. This can be implemented by checking whether the hash of the code installed on the device matches the expected value signed by a trusted party using a cryptographic protocol. For example, RMM 46 and monitoring code 29 can be proven by checking whether the hash of the software matches the expected value signed by a trusted party (such as the silicon vendor that manufactured the integrated circuit that includes the processing system 2, or the architecture vendor that designed the processor architecture that supports domain-based memory access control). This allows user-provided code 42, 44 to verify that the integrity of the domain-based architecture can be trusted before executing any secure or sensitive functions.
因此，可看出與領域42、44關聯的碼（其將已於先前在非安全域86中執行，如藉由顯示在此等程序將已於先前於該處執行之非安全域中之間隙的虛線所示）現在可移動至其等由於其等的資料及碼不可由在非安全域86中操作的其他碼存取而可具有更強安全保證的領域域中。然而，導因於領域域88與安全域84正交且因此無法看見彼此的實體位址空間，此意謂著領域域中之碼的供應商不需要信任安全域中之碼的供應商，反之亦然。領域域中的碼可簡單地信任提供用於根域82之監測碼29及RMM 46的受信任韌體，該受信任韌體可由當碼在矽供應商或由處理器所支援之指令集架構的供應商的裝置上執行時可已經固有地必需受信任的該等供應商提供，使得使用者能夠具有安全計算環境而不需要與其他作業系統廠商、OEM、或雲端主機的進一步信任關係。Thus, it can be seen that code associated with domains 42, 44 (which would have previously executed in non-secure domain 86, as indicated by the dashed lines showing gaps in the non-secure domain where such programs would have previously executed) can now be moved into domains where they can have stronger security guarantees because their data and code are not accessible to other code operating in non-secure domain 86. However, because domain 88 and secure domain 84 are orthogonal and therefore cannot see into each other's physical address space, this means that suppliers of code in the domains do not need to trust suppliers of code in the secure domain, and vice versa. Code in the domain domain can simply trust the trusted firmware that provides the monitoring code 29 and RMM 46 for the root domain 82. This trusted firmware can be provided by the silicon vendor or the vendor of the instruction set architecture supported by the processor, which may already be inherently trusted when the code is executed on such vendors' devices, allowing users to have a secure computing environment without the need for further trust relationships with other operating system vendors, OEMs, or cloud hosts.
此可對一系列應用程式及使用情形有用，包括例如行動電子錢包及支付應用程式、遊戲反作弊及盜版機制、作業系統平台安全增強、安全虛擬機器託管、機密計算、網路、或用於物聯網裝置的閘道器處理。將理解使用者可發現領域支援係有用的許多其他應用。This can be useful for a range of applications and use cases, including, for example, mobile e-wallets and payment applications, game anti-cheat and piracy mechanisms, operating system platform security enhancements, secure virtual machine hosting, confidential computing, networking, or gateway processing for IoT devices. It will be appreciated that users may find domain support useful for many other applications.
為支援對領域提供的安全保證，處理系統可支援證明報告功能，其中在啟動時間或在運行時間，對韌體影像及組態進行測量，例如監測碼影像及組態或RMM碼影像及組態，且在運行時間，測量領域內容及組態，使得領域所有者可將有關證明報告回溯追蹤至已知實施方案及認證以作出是否在該系統上操作的信任決定。To support security assurance provided to a domain, the processing system may support an attestation reporting capability whereby firmware images and configurations are measured at boot time or at runtime, such as monitoring code images and configurations or RMM code images and configurations, and domain content and configurations are measured at runtime, such that the domain owner may trace the attestation reports back to known implementations and certifications to make a trust decision on whether to operate on the system.
如圖5所示，提供管理域切換的單獨根域82，且該根域具有其自身的經隔離根實體位址空間。根域的建立及其資源與安全域的隔離，甚至對於僅具有非安全域86及安全域84但不具有領域域88的系統，允許更強固的實施方案，但亦可用於確實支援領域域88的實施方案。根域82可使用由矽供應商或架構設計者提供（或認證）的監測軟體29實施，且可用以提供安全啟動功能性、受信任啟動測量、系統單晶片組態、偵錯控制、及管理由其他方（諸如OEM）提供之韌體組件的韌體更新。根域碼可由矽供應商或架構設計者開發、認證、及部署而無須相依於最終裝置。相比之下，安全域84可由OEM管理以用於實施某些平台及安全服務。非安全域86的管理可由作業系統32控制以提供作業系統服務，而領域域88在與安全域84中的現有安全軟體環境互相隔離的同時，允許可專用於使用者或第三方應用程式的新形式的受信任執行環境的開發。As shown in Figure 5, a separate root domain 82 is provided to manage domain switching, and this root domain has its own isolated root physical address space. The establishment of the root domain and the isolation of its resources from the secure domain allow for more robust implementations even for systems with only non-secure domains 86 and secure domains 84, but no domain domain 88, but can also be used for implementations that do support domain domain 88. Root domain 82 can be implemented using monitoring software 29 provided (or certified) by a silicon vendor or architecture designer and can be used to provide secure boot functionality, trusted boot measurement, system-on-chip configuration, debugging control, and management of firmware updates for firmware components provided by other parties (such as OEMs). Root domain code can be developed, certified, and deployed by silicon vendors or architecture designers without dependencies on the end device. In contrast, secure domain 84 can be managed by the OEM to implement certain platform and security services. Management of non-secure domain 86 can be controlled by the operating system 32 to provide operating system services, while domain 88, while isolated from the existing secure software environment in secure domain 84, allows the development of new forms of trusted execution environments that can be dedicated to user or third-party applications.
圖6示意地繪示用於支援此等技術之處理系統2的另一實例。與圖3相同的元件使用相同的元件符號說明。圖6更詳細地顯示位址轉譯電路系統16，其包含1階記憶體管理單元50及2階記憶體管理單元52。1階MMU 50可負責將虛擬位址轉譯成實體位址（當轉譯由EL2或EL3碼觸發時）或中間位址（當轉譯在需要藉由2階MMU 52的另外的2階轉譯的操作狀態中由EL0或EL1碼觸發時）。2階MMU可將中間位址轉譯成實體位址。1階MMU可基於由作業系統控制之用於從EL0或EL1起始之轉譯的頁表、由超管理器控制之用於來自EL2之轉譯的頁表、或由監測碼29控制之用於來自EL3之轉譯的頁表。另一方面，2階MMU 52可基於取決於正在使用哪個域而由超管理器34、RMM 46、或安全分割管理器14定義的頁表結構。以此方式將轉譯分成二個階段允許作業系統在其等係唯一在系統上運行之作業系統的假設下管理其等自身及應用程式的位址轉譯，而RMM 46、超管理器34、或SPM 40可管理在相同域中運行的不同作業系統之間的隔離。FIG6 schematically illustrates another example of a processing system 2 for supporting these techniques. Components identical to those in FIG3 are depicted using the same component numbers. FIG6 shows in greater detail the address translation circuitry 16, which includes a level-1 memory management unit 50 and a level-2 memory management unit 52. Level-1 MMU 50 may be responsible for translating virtual addresses into physical addresses (when the translation is triggered by EL2 or EL3 code) or intermediate addresses (when the translation is triggered by EL0 or EL1 code in an operating state requiring additional level-2 translation by level-2 MMU 52). The level-2 MMU may translate intermediate addresses into physical addresses. The level 1 MMU may be based on page tables controlled by the operating system for translations originating from EL0 or EL1, by the hypervisor for translations from EL2, or by monitor code 29 for translations from EL3. Level 2 MMU 52, on the other hand, may be based on a page table structure defined by the hypervisor 34, RMM 46, or secure partition manager 14, depending on which domain is being used. Separating translation into two stages in this way allows the operating system to manage address translation for itself and its applications under the assumption that it is the only operating system running on the system, while RMM 46, hypervisor 34, or SPM 40 can manage isolation between different operating systems running in the same domain.
如圖6所示，使用位址轉譯電路系統16的位址轉譯程序可返回安全屬性54，該等安全屬性與目前例外等級15及目前域14（或安全狀態）結合以回應於給定記憶體存取請求而允許存取特定實體位址空間之區段（藉由PAS識別符或「PAS TAG」識別）。可在顆粒保護表56中查找實體位址及PAS識別符，該顆粒保護表提供索引以識別提供稍早描述之顆粒保護資訊的屬性儲存位置。在此實例中，將PAS過濾器20顯示為顆粒記憶體保護單元(granular memory protection unit, GMPU)，該顆粒記憶體保護單元驗證是否允許經選擇PAS存取所請求的實體位址，且若如此，允許交易傳遞至係記憶體系統之系統網狀架構的部分的任何快取記憶體24或互連8。As shown in Figure 6, the address translation process using the address translation circuitry 16 can return security attributes 54 that, in combination with the current exception level 15 and the current domain 14 (or security state), allow access to a particular segment of the physical address space (identified by a PAS identifier or "PAS TAG") in response to a given memory access request. The physical address and PAS identifier can be looked up in a granule protection table 56, which provides an index to identify the location where the attributes providing the granule protection information described earlier are stored. In this example, the PAS filter 20 is shown as a granular memory protection unit (GMPU) that verifies whether the selected PAS is allowed to access the requested physical address and, if so, allows the transaction to pass to any cache 24 or interconnect 8 that is part of the system fabric of the memory system.
GMPU 20允許將記憶體指派給分開的位址空間而提供強的基於硬體的隔離保證且在實體記憶體至此等位址空間中的指派方法中提供空間及時間彈性，以及允許有效率的共用方案。如稍早描述的，將系統中的執行單元邏輯地分割成虛擬執行狀態（域或「世界(World)」），其中存在一個位於最高例外等級(EL3)之稱為「根世界(Root World)」之管理對此等世界之實體記憶體指派的執行狀態（根世界）。The GMPU 20 allows memory to be assigned to separate address spaces, providing strong hardware-based isolation guarantees and spatial and temporal flexibility in the allocation of physical memory to these address spaces, as well as allowing for efficient sharing schemes. As described earlier, the execution units in the system are logically divided into virtual execution states (domains or "worlds"), of which there is an execution state (root world) at the highest exception level (EL3) called the "root world" that manages the allocation of physical memory to these worlds.
將單一系統實體位址空間虛擬化成多個「邏輯」或「架構」實體位址空間(PAS)，其中各此類PAS係具有獨立一致性屬性的正交位址空間。系統實體位址藉由使用PAS標籤延伸而映射至單一「邏輯」實體位址空間。Virtualizes a single system physical address space into multiple "logical" or "fabricated" physical address spaces (PAS), where each PAS is an orthogonal address space with independent consistency properties. System physical addresses are mapped to the single "logical" physical address space using PAS tag extensions.
允許給定世界存取邏輯實體位址空間的子集。此係藉由可附接至記憶體管理單元16之輸出的硬體過濾器20強制執行。A given world is allowed to access a subset of the logical physical address space. This is enforced by a hardware filter 20 that can be attached to the output of the memory management unit 16.
世界使用用於位址轉譯之虛擬定址頁表之轉譯表描述符中的欄位定義存取的安全屬性（PAS標籤）。硬體過濾器20具有對指定系統實體位址空間中之各頁之索引的表（顆粒保護表56，或GPT）的存取，該表可用以存取儲存指示與其相關聯之PAS TAG及（可選地）其他顆粒保護屬性之顆粒保護資訊(granule protection information, GPI)的屬性儲存位置。The world uses fields in the translation table descriptor of the virtual address page table used for address translation to define the security attributes of access (PAS tag). The hardware filter 20 has access to a table (granule protection table 56, or GPT) that specifies the index of each page in the system's physical address space. This table can be used to access the attribute storage location that stores granule protection information (GPI) indicating the PAS tag associated with it and (optionally) other granule protection attributes.
硬體過濾器20對照顆粒的GPI檢查世界ID及安全屬性並決定是否可授權存取，因此形成顆粒記憶體保護單元(GMPU)。The hardware filter 20 checks the world ID and security attributes against the particle's GPI and determines whether access is authorized, thus forming a particle memory protection unit (GMPU).
例如，GPT 56可駐存在晶片上SRAM中或晶片外DRAM中。若儲存在晶片外，GPT 56可藉由可使用加密、完整性、及新鮮性機制以維持GPT 56之安全性的晶片上記憶體保護引擎受完整性保護。For example, GPT 56 may reside in on-chip SRAM or off-chip DRAM. If stored off-chip, GPT 56 may be integrity protected by an on-chip memory protection engine that may use encryption, integrity, and freshness mechanisms to maintain the security of GPT 56.
將GMPU 20定位在系統的請求者側上（例如，在MMU輸出上）而非在完成者側上允許以頁粒度分配存取權限，同時允許互連8繼續橫跨多個DRAM埠雜湊/剝除頁。Locating the GMPU 20 on the requester side of the system (e.g., on the MMU output) rather than on the completer side allows access permissions to be allocated at a page granularity while allowing the interconnect 8 to continue shuffling/stripping pages across multiple DRAM ports.
交易在其等在系統網狀架構24、8各處傳播時保持以PAS TAG標記直到到達定義為實體別名點60的位置為止。與從屬側過濾相比，此允許將過濾器定位在主站側上而無需減少安全保證。當交易在系統各處傳播時，可將PAS TAG使用為用於位址隔離的深度安全機制：例如，快取記憶體可將PAS TAG添加至快取記憶體中的位址標籤，防止使用錯誤的PAS TAG對相同PA的存取在快取記憶體中命中，且因此改善側通道抗性。PAS TAG亦可使用為用於保護引擎的上下文選擇器，該保護引擎附接至在將資料寫至外部DRAM之前加密其的記憶體控制器。Transactions remain tagged with the PAS TAG as they propagate throughout the system mesh fabric 24, 8 until they reach a location defined as a physical alias point 60. This allows filters to be located on the master side without compromising security compared to slave-side filtering. PAS TAGs can be used as a deep security mechanism for address isolation as transactions propagate throughout the system: for example, a cache can add the PAS TAG to the address tags in the cache, preventing accesses to the same PA with the wrong PAS TAG from hitting in the cache and thus improving side-channel resistance. PAS TAGs can also be used as a context selector for a protection engine attached to a memory controller that encrypts data before writing it to external DRAM.
實體別名點(PoPA)係系統中之將PAS TAG剝除且將位址從邏輯實體位址改變回系統實體位址的位置。PoPA可位於在系統之（使用通過PAS TAG解析的加密上下文）進行對實體DRAM之存取的完成者側的快取記憶體之下。替代地，其可位於快取記憶體之上而以降低安全性的成本簡化系統實施方案。The physical point of alias (PoPA) is the location in the system where the PAS tag is stripped and the address is changed from a logical physical address back to a system physical address. The PoPA can be located below the cache on the completer side of the system that accesses the physical DRAM (using the encryption context resolved via the PAS tag). Alternatively, it can be located above the cache to simplify the system implementation at the cost of reduced security.
在任何時間點，世界可請求將頁從一個PAS轉變至另一者。進行對在EL3之檢測GPI之目前狀態的監測碼29的請求。EL3可僅允許一組特定的轉換（例如，從非安全PAS到安全PAS，但不允許從領域PAS到安全PAS，另一支援轉換可能係介於具有預定較低安全記憶體性質的非安全PAS與具有第二較低安全記憶體性質的非安全PAS之間）。為提供乾淨轉變，由系統支援新指令-「對實體別名點的資料清理及無效化」，EL3可在將頁轉變至新的PAS之前提交其–此保證與先前PAS關聯的任何殘餘狀態從PoPA 60上游（比該PoPA更接近請求者側）的任何快取記憶體清除。At any point in time, the world may request to transfer a page from one PAS to another. The request is made to monitor code 29 at EL3, which detects the current state of the GPI. EL3 may only allow a specific set of transitions (e.g., from non-secure PAS to secure PAS, but not from domain PAS to secure PAS. Another supported transition might be between a non-secure PAS with predetermined less secure memory properties and a non-secure PAS with a second less secure memory property). To provide clean transitions, a new instruction is supported by the system - "Clean and invalidate data on physical alias points" which EL3 can submit before transferring a page to a new PAS - this ensures that any residual state associated with the previous PAS is cleared from any caches upstream of the PoPA 60 (closer to the requester than the PoPA).
可藉由將GMPU 20附接至主站側而實現的另一性質係世界之間的記憶體的有效率共用。將對實體顆粒的共用存取授權N個世界的子集而防止其他世界存取其可係所欲的。此可藉由添加「限制性共用(restrictive shared)」語意至顆粒保護資訊，同時強制其使用特定的PAS TAG而實現。作為一實例，GPI在以安全PAS 84的PAS TAG標記的同時可指示實體顆粒可僅由「領域世界(Realm World)」88及「安全世界(Secure World)」84存取。Another feature enabled by attaching the GMPU 20 to the master side is efficient sharing of memory between worlds. It's possible to grant shared access to a physical particle to a subset of N worlds while preventing access from other worlds. This can be achieved by adding "restrictive sharing" semantics to the particle protection information and enforcing the use of a specific PAS tag. As an example, a GPI, while tagged with the PAS tag of secure PAS 84, can indicate that a physical particle is accessible only to "Realm World" 88 and "Secure World" 84.
上述性質的實例使特定實體顆粒的可見性性質快速改變。考慮各世界經指派有僅可由該世界存取之私密PAS的情形。對於特定顆粒，世界可藉由將其等的GPI從「獨佔(exclusive)」改變成「與非安全世界的限制性共用(restrictive shared with Non-Secure world)」而在任何時間點請求使其等可為非安全世界可見，而無需改變PAS關聯性。如此，可增加該顆粒的可見性而不需要昂貴的快取維護或資料複製操作。An example of this property allows the visibility of a particular entity particle to be rapidly changed. Consider a scenario where each world is assigned a private PAS that is accessible only to that world. For a particular particle, a world can request that it be made visible to the non-secure world at any time by changing its GPI from "exclusive" to "restrictively shared with the non-secure world" without changing the PAS association. This allows the visibility of that particle to be increased without requiring expensive cache maintenance or data replication.
圖7繪示在將各別實體位址空間別名至以硬體提供之實體記憶體上的概念。如稍早所述，域82、84、86、88之各者具有其自身的各別實體位址空間61。Figure 7 illustrates the concept of aliasing individual physical address spaces to physical memory provided by hardware. As mentioned earlier, each of the domains 82, 84, 86, 88 has its own individual physical address space 61.
在實體位址由位址轉譯電路系統16產生時，該實體位址具有在由系統所支援的某個數值範圍62內的值，不論選擇哪個實體位址空間，其皆相同。然而，除了產生實體位址外，位址轉譯電路系統16亦可基於目前域14及/或用以推導實體位址之頁表項中的資訊選擇特定實體位址空間(PAS)。替代地，位址轉譯電路系統（例如，MMU）可輸出實體位址及從用於PAS之選擇的頁表項(page table entry, PTE)推導的資訊，且接著此資訊可由PAS過濾器或GMPU 20使用以選擇PAS，而非位址轉譯電路系統16執行PAS的選擇。When a physical address is generated by the address translation circuitry 16, the physical address has a value within a certain range of values 62 supported by the system, which is the same regardless of which physical address space is selected. However, in addition to generating a physical address, the address translation circuitry 16 may also select a particular physical address space (PAS) based on information in the current domain 14 and/or the page table entry used to derive the physical address. Alternatively, the address translation circuitry (e.g., an MMU) may output the physical address and information derived from the page table entry (PTE) used for PAS selection, and this information may then be used by the PAS filter or GMPU 20 to select the PAS, rather than the address translation circuitry 16 performing the PAS selection.
用於給定記憶體存取請求之PAS的選擇可取決於處理電路系統10在發布記憶體存取請求時正於其中操作的目前域而根據定義於下表中的規則受限制：
對於存在可用於選擇的多個實體位址空間的彼等域，使用來自用以提供實體位址之經存取頁表項的資訊以在可用PAS選項之間選擇。對於表中標示為*之關於存取非安全PAS的項，安全域及領域域是否能夠存取非安全PAS亦取決於稍早定義的預定較低安全記憶體性質是否已經在用於正被存取之PA的顆粒保護資訊(GPI)中經指定（至少在一些操作模式中——可能出於向後相容性原因，提供其中停用此性質的模式）。For those domains where there are multiple physical address spaces available for selection, information from the accessed page table entry providing the physical address is used to select between the available PAS options. For the entries marked with an * in the table regarding access to non-secure PAS, whether secure and domain-level domains can access non-secure PAS also depends on whether the predetermined less secure memory property defined earlier has been specified in the Granular Protection Information (GPI) for the PA being accessed (at least in some operating modes - modes may be provided in which this property is disabled for backward compatibility reasons).
因此，在PAS過濾器20將記憶體存取請求（假設其通過任何過濾檢查）輸出至系統網狀架構24、8時，記憶體存取請求與實體位址(PA)及經選擇實體位址空間(PAS)關聯。Therefore, when the PAS filter 20 outputs a memory access request (assuming it passes any filtering checks) to the system fabric 24, 8, the memory access request is associated with a physical address (PA) and a selected physical address space (PAS).
從在實體別名點(PoPA) 60之前操作的記憶體系統組件（諸如快取記憶體、互連、監聽過濾器等）的觀點，將各別實體位址空間61視為係對應於記憶體內的不同系統位置的完全分開的位址範圍。此意謂著，從前PoPA記憶體系統組件的觀點，由於有效地將PAS識別符視為在實體位址本身旁邊的額外位址位元，使得取決於哪個PAS經選擇，可將相同的實體位址PAx映射至相異實體位址空間61中的若干個別名實體位址63，由記憶體存取請求識別的位址範圍實際上係可在位址轉譯中輸出之範圍62的大小的四倍。此等別名實體位址63實際上全部對應於以實體硬體實施的相同記憶體系統位置，但前PoPA記憶體系統組件將別名位址63視為分開的位址。因此，若存在針對此類位址分配項的任何前PoPA快取記憶體或監聽過濾器，別名位址63將隨著各別的快取命中/未命中決定及各別的一致性管理而映射至不同項中。此降低攻擊者將快取記憶體或一致性側通道使用為探測其他域之操作的機制的可能性或有效性。From the perspective of memory system components operating before a physical point of alias (PoPA) 60 (e.g., caches, interconnects, snoop filters, etc.), the respective physical address spaces 61 are viewed as completely separate address ranges corresponding to different system locations within memory. This means that from the perspective of the pre-PoPA memory system components, the range of addresses identified by a memory access request is effectively four times the size of the range 62 that can be output in the address translation, since the PAS identifier is effectively viewed as an additional address bit next to the physical address itself, such that the same physical address PAx can be mapped to several aliased physical addresses 63 in different physical address spaces 61, depending on which PAS is selected. These alias physical addresses 63 actually all correspond to the same memory system location implemented in physical hardware, but the pre-PoPA memory system components treat the alias addresses 63 as separate addresses. Therefore, if there are any pre-PoPA caches or snoop filters that allocate entries for these addresses, the alias addresses 63 will be mapped to different entries based on separate cache hit/miss decisions and separate coherence management. This reduces the likelihood or effectiveness of an attacker using the cache or coherence side-channel as a mechanism to spy on operations in other domains.
該系統可包括多於一個PoPA 60（例如，指定不同實體位址的記憶體存取請求可經由記憶體系統中的不同路徑來路由，且可由不同PoPA 60來處理）。在各PoPA 60處，將別名實體位址摺疊成系統實體位址空間64中的單一經去別名位址65。將經去別名位址65提供至下游的任何後PoPA組件，使得實際上識別記憶體系統位置的系統實體位址空間64再次與可在請求者側上執行的位址轉譯中輸出的實體位址的範圍的大小相同。例如，在PoPA 60處可將PAS識別符從位址剝除，且對於下游組件，位址可簡單地使用實體位址值識別而無需指定PAS。替代地，對於期望某種完成者側記憶體存取請求過濾的一些情形，PAS識別符可仍在PoPA 60的下游提供，但可不被解譯為位址的部分，使得出現在不同實體位址空間60中的相同實體位址將在PoPA的下游解譯為參考至相同的記憶體系統位置，但所供應的PAS識別符仍可用於執行任何完成者側安全檢查。The system may include more than one PoPA 60 (e.g., memory access requests specifying different physical addresses may be routed via different paths in the memory system and may be processed by different PoPAs 60). At each PoPA 60, the aliased physical addresses are collapsed into a single de-aliased address 65 in the system physical address space 64. The de-aliased address 65 is provided to any downstream post-PoPA components so that the system physical address space 64 that actually identifies the memory system location is again the same size as the range of physical addresses that can be output in the address translation performed on the requester side. For example, the PAS identifier may be stripped from the address at the PoPA 60, and for downstream components, the address may simply be identified using the physical address value without specifying a PAS. Alternatively, for some scenarios where some completer-side memory access request filtering is desired, the PAS identifier may still be provided downstream of the PoPA 60, but may not be interpreted as part of the address, such that the same physical address appearing in different physical address spaces 60 will be interpreted downstream of the PoPA as referring to the same memory system location, but the provided PAS identifier may still be used to perform any completer-side security checks.
圖8繪示可如何使用顆粒保護表56將系統實體位址空間64劃分成經分配以用於在特定架構實體位址空間61內存取的塊。對應於實體位址之各顆粒的屬性資訊定義允許從各架構實體位址空間61存取系統實體位址空間65的哪些部分。例如，GPT 56可包含數個項，各項對應於特定大小的實體位址顆粒（例如4K頁）。對應於特定目標實體位址的GPT項可指定用於識別對應於該實體位址之屬性儲存位置的索引，該屬性儲存位置指定顆粒保護資訊(GPI)。GPI可為該顆粒指派特定PAS，或可指示可使用多於一個PAS來存取該顆粒。GPI亦可施加關於哪個域與記憶體存取請求相關聯的進一步要求。若實體記憶體位址空間的特定顆粒或一組顆粒在GPT中經定義為僅可從一個PAS存取，則其可僅在該PAS內經存取，而不能在其他域的PAS內經存取。然而，應注意雖然分配給安全PAS（例如）的顆粒無法從根PAS內存取，然而根域82能夠藉由在其頁表中指定用於確保將與映射至實體經定址記憶體之該區域的頁關聯的虛擬位址轉譯成在安全PAS中而非根PAS中的實體位址的PAS選擇資訊而存取實體位址的該顆粒。因此，橫跨域的資料共用（在由定義在稍早描述之表中的可存取性/不可存取性規則所允許的情況下）可在選擇用於給定記憶體存取請求的PAS時受控制。Figure 8 illustrates how a granule protection table 56 may be used to partition the system physical address space 64 into blocks allocated for access within a particular architectural physical address space 61. Attribute information corresponding to each granule of a physical address defines which portions of the system physical address space 65 are permitted to be accessed from each architectural physical address space 61. For example, the GPT 56 may include several entries, each corresponding to a physical address granule of a particular size (e.g., a 4K page). The GPT entry corresponding to a particular target physical address may specify an index identifying an attribute storage location corresponding to that physical address, the attribute storage location specifying granule protection information (GPI). The GPI may assign a specific PAS to the granule, or may indicate that more than one PAS may be used to access the granule. GPI may also impose further requirements regarding which domain is associated with a memory access request. If a particular granule or set of granules of the physical memory address space is defined in the GPT as accessible only from one PAS, then it can be accessed only within that PAS and not within the PASs of other domains. However, it should be noted that although a granule assigned to a secure PAS (for example) cannot be accessed from within the root PAS, the root domain 82 is able to access that granule of a physical address by specifying PAS selection information in its page table that ensures that the virtual address associated with the page mapped to that region of physical addressed memory is translated into a physical address in the secure PAS rather than the root PAS. Thus, data sharing across domains (where permitted by the accessibility/inaccessibility rules defined in the table described earlier) can be controlled when selecting the PAS for a given memory access request.
然而，在一些實施方案中，除了允許實體位址的顆粒在由GPI定義的單一經指派PAS內存取外，GPI可將位址空間的某些區域標示成與另一位址空間（例如，與通常將不允許其針對該域之存取請求選擇經指派PAS的較低特權或正交特權的域關聯的位址空間）共用。此可促進資料的暫時共用而不需要改變用於給定顆粒的經指派PAS。例如，在圖8中，領域PAS的區域70在由GPT指示之屬性儲存位置識別的GPI中經定義為對應於指派給領域域的該區域，因此通常其將不可從非安全域86存取，因為非安全域86無法為其存取請求選擇領域PAS。由於非安全域26無法存取領域PAS，則非安全碼通常不能看到區域70中的資料。然而，若領域暫時希望與非安全域共用在其經指派記憶體區域中之其資料的一些，則其可請求在根域82中操作的監測碼29更新GPI 56以指示區域70將與非安全域86共用，且如圖8左側所示，此可使區域70亦可從非安全PAS存取，而不需要改變哪個域係用於區域70的經指派域。若領域域已將其位址空間的區域指定為與非安全域共用，則雖然從非安全域發布之標定該區域的記憶體存取請求最初可指定該非安全PAS，但PAS過濾器20可重映射該請求的PAS識別符以替代地指定領域PAS，使得下游記憶體系統組件將該請求視為彷彿其始終從領域域發布。由於將不同域指派至特定記憶體區域的操作涉及較大程度的快取記憶體/TLB無效化及/或記憶體中的資料歸零或資料在記憶體區域之間的複製而可係更效能密集的，若預期共用僅係暫時的，該等操作可係不必要的，此共用可改善效能。However, in some embodiments, in addition to allowing physical address particles to be accessed within a single assigned PAS defined by the GPI, the GPI may mark certain areas of the address space as shared with another address space (e.g., an address space associated with a domain of lower or orthogonal privilege that would not normally be allowed to select the assigned PAS for access requests to that domain). This can facilitate temporary sharing of data without requiring a change to the assigned PAS for a given particle. For example, in FIG8 , area 70 of the domain PAS is defined in the GPI identified by the attribute storage location indicated by the GPT as corresponding to that area assigned to the domain, and therefore would normally be inaccessible from the non-secure domain 86 because the non-secure domain 86 would not be able to select the domain PAS for its access requests. Since the non-secure domain 26 cannot access the domain PAS, the non-secure code cannot normally see the data in area 70. However, if a domain temporarily wishes to share some of its data in its assigned memory area with the non-secure domain, it can request the monitoring code 29 operating in the root domain 82 to update the GPI 56 to indicate that area 70 is to be shared with the non-secure domain 86, and as shown on the left side of Figure 8, this can make area 70 accessible from the non-secure PAS as well, without changing which domain is the assigned domain for area 70. If a domain domain has designated a region of its address space as shared with a non-secure domain, then although a memory access request issued from the non-secure domain targeting that region may initially specify the non-secure PAS, the PAS filter 20 may remap the PAS identifier of the request to instead specify the domain PAS so that downstream memory system components treat the request as if it had always been issued from the domain domain. This sharing may improve performance because the operation of assigning different domains to a particular memory region may be more performance intensive due to the greater degree of cache/TLB invalidation and/or data zeroing in memory or copying of data between memory regions, which may not be necessary if the intended sharing is only temporary.
其他實施方案可能不支援此類共用選項，且因此GPT可能會限制各實體位址僅可經由一個PAS存取。Other implementations may not support such sharing options, and therefore GPT may restrict each physical address to be accessible via only one PAS.
圖9係顯示如何判定目前操作域的流程圖，其可由處理電路系統10或由位址轉譯電路系統16或PAS過濾器20進行。在步驟100，判定目前例外等級15是否係EL3，且若如此，則在步驟102，目前域經判定為係根域82。若目前例外等級係非EL3，則在步驟104，如藉由處理器之EL3控制暫存器內的至少二個域指示位元14指示的，將目前域判定為係非安全域86、安全域84、及領域域88之一者（由於根域藉由係EL3的目前例外等級指示，域指示位元14可能不必具有對應於根域的編碼，所以域指示位元的至少一個編碼可保留以用於其他目的）。EL3控制暫存器當在EL3操作時可寫入且無法從其他例外等級EL2至EL0寫入。FIG9 is a flow chart showing how the current operating domain is determined, which may be performed by processing circuitry 10, or by address translation circuitry 16, or PAS filter 20. At step 100, a determination is made as to whether the current exception level 15 is EL3, and if so, at step 102, the current domain is determined to be the root domain 82. If the current exception level is not EL3, then at step 104, the current domain is determined to be one of the non-secure domain 86, the secure domain 84, and the domain domain 88, as indicated by at least two domain indicator bits 14 in the processor's EL3 control register (since the root domain is indicated by the current exception level being EL3, the domain indicator bits 14 may not necessarily have a coding corresponding to the root domain, so at least one coding of the domain indicator bits may be reserved for other purposes). The EL3 control registers are writable when operating at EL3 and cannot be written from other exception levels, EL2 through EL0.
圖10顯示頁表項(PTE)格式的實例，其可用於由位址轉譯電路系統16使用以用於將虛擬位址映射至實體位址、將虛擬位址映射至中間位址、或將中間位址映射至實體位址之頁表結構中的頁表項（取決於轉譯是否正在完全需要2階轉譯的操作狀態中執行，且若需要2階轉譯，取決於轉譯係1階轉譯或2階轉譯）。一般而言，可將給定頁表結構定義為實施為頁表樹的多層表結構，其中第一層頁表基於儲存在處理器之轉譯表基底位址暫存器中的基底位址識別，且選擇頁表內的特定1階表項的索引係從正針對其執行轉譯查找之輸入位址的位元子集推導（輸入位址可係用於2階轉譯之中間位址的1階轉譯的虛擬位址）。1階頁表項可係提供至次一層頁表之指標112的「表描述符」110，另外的頁表項接著可基於輸入位址的另外的位元子集自其選擇。最後，在對連續層頁表的一或多個查找之後，可識別提供對應於輸入位址之輸出位址120的區塊或頁描述符PTE 114、116、118。輸出位址可係中間位址（用於在亦執行進一步2階轉譯的操作狀態中執行的1階轉譯）或實體位址（用於2階轉譯，或當不需要2階轉譯時，用於1階轉譯）。FIG10 shows an example of a page table entry (PTE) format that may be used by the address translation circuitry 16 for use in a page table structure for mapping a virtual address to a physical address, mapping a virtual address to an intermediate address, or mapping an intermediate address to a physical address (depending on whether the translation is being performed in an operating state that fully requires a 2-level translation, and if 2-level translation is required, depending on whether the translation is a 1-level translation or a 2-level translation). In general, a given page table structure can be defined as a multi-level table structure implemented as a tree of page tables, where a first-level page table is identified based on a base address stored in a processor's translation table base address register, and the index that selects a particular level 1 table entry within the page table is derived from a bit subset of the input address for which the translation lookup is being performed (the input address may be the virtual address of the level 1 translation of an intermediate address used for a level 2 translation). The level 1 page table entry may be a "table descriptor" 110 that provides a pointer 112 to the next-level page table, from which additional page table entries may then be selected based on additional bit subsets of the input address. Finally, after one or more lookups in the consecutive levels of page tables, a block or page descriptor PTE 114, 116, 118 is identified that provides an output address 120 corresponding to the input address. The output address can be an intermediate address (for level 1 translation in an operating state that also performs further level 2 translation) or a physical address (for level 2 translation, or for level 1 translation when level 2 translation is not required).
為支援上文描述的相異實體位址空間，除了次一層頁表指標112或輸出位址120及用於控制對對應記憶體區塊之存取的任何屬性122外，頁表項格式亦可指定某個額外狀態以用於在實體位址空間選擇時使用。To support the different physical address spaces described above, in addition to the next-level page table pointer 112 or output address 120 and any attributes 122 used to control access to the corresponding memory block, the page table entry format may also specify some additional state for use in physical address space selection.
對於表描述符110，由非安全域86以外的任何域使用的PTE包括指示次一層頁表將從非安全實體位址空間或從目前域的實體位址空間存取的非安全表指示符124。此幫助促進更有效率的頁表管理。通常由根域、領域域、或安全域24使用的頁表結構可僅需要定義用於虛擬位址空間的一部分的特殊頁表項，且當由非安全域26使用時相同的頁表項可用於其他部分，所以藉由提供非安全表指示符124，此可允許更高階的頁表結構提供專用領域/安全表描述符，同時在頁表樹的特定點處，根域、領域域、或安全域可切換以將來自非安全域的頁表項用於位址空間之不需要較高安全性的彼等部分。在頁表樹的其他部分中的其他頁表描述符仍可從與根域、領域域、或安全域關聯的有關實體位址空間提取。For table descriptors 110, PTEs used by any domain other than the non-secure domain 86 include a non-secure table indicator 124 indicating that the next-level page table will be accessed from the non-secure physical address space or from the physical address space of the current domain. This helps facilitate more efficient page table management. Typically, a page table structure used by the root domain, domain domain, or secure domain 24 may only need to define special page table entries for a portion of the virtual address space, and the same page table entries can be used for the other portion when used by the non-secure domain 26. So by providing the non-secure table indicator 124, this allows higher-level page table structures to provide dedicated domain/secure table descriptors, while at specific points in the page table tree, the root domain, domain domain, or secure domain can switch to using page table entries from the non-secure domain for those portions of the address space that do not require higher security. Other page table descriptors in other parts of the page table tree may still be fetched from the relevant physical address space associated with the root domain, domain domain, or security domain.
另一方面，取決區塊/頁描述符114、116、118與哪個域關聯，其等可包括實體位址空間選擇資訊126。由於非安全域僅能夠存取非安全PAS，使用在非安全域86中的非安全區塊/頁描述符118不包括任何PAS選擇資訊。然而，對於其他域，區塊/頁描述符114、116包括用以選擇將輸入位址轉譯至哪個PAS中的PAS選擇資訊126。對於根域22，EL3頁表項可具有包括至少2個位元以將與4個域82、84、86、88的任一者關聯的PAS指示為對應實體位址將轉譯至其中之經選擇PAS的PAS選擇資訊126。相比之下，對於領域域及安全域，對應的區塊/頁描述符116僅需要包括PAS選擇資訊126的一個位元，該位元用於該領域域時，在領域PAS與非安全PAS之間選擇，且用於安全域時，在安全PAS與非安全PAS之間選擇。為改善電路實施方案的效率並避免增加頁表項的大小，對於領域域及安全域，無論目前域係領域域或安全域，區塊/頁描述符116可將PAS選擇資訊126編碼在PTE內的相同位置，使得PAS選擇位元126可共用。On the other hand, depending on which domain a block/page descriptor 114, 116, or 118 is associated with, it may include physical address space selection information 126. Since the non-secure domain can only access the non-secure PAS, the non-secure block/page descriptor 118 used in the non-secure domain 86 does not include any PAS selection information. However, for other domains, the block/page descriptors 114 and 116 include PAS selection information 126 for selecting the PAS to which the input address is translated. For the root domain 22, the EL3 page table entry may have PAS selection information 126 that includes at least two bits to indicate the PAS associated with any of the four domains 82, 84, 86, or 88 as the selected PAS to which the corresponding physical address is to be translated. In contrast, for the domain domain and the security domain, the corresponding block/page descriptor 116 only needs to include one bit of PAS selection information 126, which selects between the domain PAS and the non-secure PAS when used in the domain domain, and selects between the secure PAS and the non-secure PAS when used in the security domain. To improve the efficiency of the circuit implementation and avoid increasing the size of the page table entry, for the domain domain and the security domain, the block/page descriptor 116 can encode the PAS selection information 126 in the same position within the PTE, regardless of whether the current domain is the domain domain or the security domain, so that the PAS selection bit 126 can be shared.
因此，圖11係顯示基於目前域及來自在產生給定記憶體存取請求之實體位址時所使用的區塊/頁PTE的資訊124、126選擇PAS的方法的流程圖。PAS選擇可由位址轉譯電路系統16執行，或若位址轉譯電路系統將PAS選擇資訊126轉發至PAS過濾器20，由位址轉譯電路系統16及PAS過濾器20的組合執行。11 is a flow chart illustrating a method for selecting a PAS based on the current domain and information 124, 126 from the block/page PTE used in generating the physical address of a given memory access request. PAS selection may be performed by the address translation circuitry 16, or by a combination of the address translation circuitry 16 and the PAS filter 20 if the address translation circuitry forwards the PAS selection information 126 to the PAS filter 20.
在圖11中的步驟130，處理電路系統10發布將給定虛擬位址(VA)指定為目標VA的記憶體存取請求。在步驟132，位址轉譯電路系統16在其TLB 18中查找任何頁表項（或從此類頁表項推導的經快取資訊）。若任何所需頁表資訊皆不可用，位址轉譯電路系統16對記憶體起始頁表走訪以提取所需的PTE（可能需要一系列記憶體存取以逐步通過頁表結構的各別層及/或位址轉譯的多個階段以用於獲得從VA至中間位址(IPA)且接著從IPA至PA的映射）。應注意到在頁表走訪操作中由位址轉譯電路系統16發布的任何記憶體存取請求本身可受位址轉譯及PAS過濾，所以在步驟130接收的請求可係經發布以向記憶體請求頁表項的記憶體存取請求。一旦相關頁表資訊已識別，將虛擬位址轉譯成實體位址（可能經由IPA以二個階段）。在步驟134，位址轉譯電路系統16或PAS過濾器20使用稍早所示方法判定哪個域係目前域。At step 130 in Figure 11, processing circuitry 10 issues a memory access request specifying a given virtual address (VA) as the target VA. At step 132, address translation circuitry 16 searches its TLB 18 for any page table entries (or cached information derived from such page table entries). If any required page table information is not available, address translation circuitry 16 accesses the memory home page table to retrieve the required PTE (a series of memory accesses may be required to step through various layers of the page table structure and/or multiple stages of address translation to obtain a mapping from the VA to the intermediate address (IPA) and then from the IPA to the PA). It should be noted that any memory access request issued by the address translation circuitry 16 during a page table walk operation may itself be subject to address translation and PAS filtering. Therefore, the request received in step 130 may be a memory access request issued to request a page table entry from memory. Once the relevant page table information has been identified, the virtual address is translated into a physical address (possibly via IPA in two stages). In step 134, the address translation circuitry 16 or PAS filter 20 determines which domain is the current domain using the method described earlier.
若目前域係非安全域，則在步驟136，針對此記憶體存取請求選擇的輸出PAS係非安全PAS。If the current domain is a non-secure domain, then in step 136, the output PAS selected for this memory access request is the non-secure PAS.
若目前域係安全域，則在步驟138，輸出PAS係基於包括在提供實體位址之區塊/頁描述符PTE中的PAS選擇資訊126選擇，其中將該輸出PAS選擇為安全PAS或非安全PAS之任一者。If the current domain is a secure domain, then in step 138, the output PAS is selected based on the PAS selection information 126 included in the block/page descriptor PTE providing the physical address, wherein the output PAS is selected as either a secure PAS or a non-secure PAS.
若目前域係領域域，則在步驟140，輸出PAS係基於包括在實體位址係自其推導之區塊/頁描述符PTE中的PAS選擇資訊126選擇，且在此情形中，將該輸出PAS選擇為領域PAS或非安全PAS之任一者。If the current domain is the domain domain, then in step 140, the output PAS is selected based on the PAS selection information 126 included in the block/page descriptor PTE from which the physical address is derived, and in this case, the output PAS is selected as either the domain PAS or the non-secure PAS.
若在步驟134，目前域經判定係根域，則在步驟142，輸出PAS係基於實體位址係自其推導之根區塊/頁描述符PTE 114中的PAS選擇資訊126選擇。在此情形中，將輸出PAS選擇成與根域、領域域、安全域、及非安全域關聯的實體位址空間的任一者。If the current domain is determined to be the root domain in step 134, then in step 142, the output PAS is selected based on the PAS selection information 126 in the root block/page descriptor PTE 114 from which the physical address is derived. In this case, the output PAS is selected to be any one of the physical address spaces associated with the root domain, the domain domain, the secure domain, and the non-secure domain.
圖12總結位址轉譯電路系統16及PAS過濾器20的操作。PAS過濾20可被認為係在由位址轉譯電路系統進行的1階（及可選地，2階）位址轉譯之後進行的額外3階檢查。亦當注意，EL3轉譯係基於頁表項，該等頁表項提供兩位元基於位址的選擇資訊（在圖12的實例中標記為NS、NSE），而單一位元選擇資訊「NS」用以選擇其他狀態中的PAS。圖12中指示的作為顆粒保護檢查之輸入的安全狀態係指識別處理元件4之目前域的域ID。FIG12 summarizes the operation of the address translation circuitry 16 and the PAS filter 20. The PAS filter 20 can be considered an additional 3rd-level check performed after the 1st-level (and optionally 2nd-level) address translation performed by the address translation circuitry. It should also be noted that EL3 translation is based on page table entries, which provide two bits of address-based selection information (labeled NS, NSE in the example of FIG12 ), while the single-bit selection information "NS" is used to select the PAS in other states. The security state indicated in FIG12 as input to the granular protection check refers to the domain ID that identifies the current domain of the processing element 4.
圖13係繪示PAS過濾器20（檢查電路系統）在圖9所示的3階進行保護檢查之方法的流程圖。在步驟200，PAS過濾器20獲得對應於位址轉譯電路系統16針對記憶體存取請求所獲得之目標實體位址(PA)的保護資訊GPT[PA]。例如，PAS過濾器20在顆粒保護資訊快取記憶體22中查找目標PA，且若存在針對目標PA的命中，則基於在顆粒保護資訊快取記憶體22的命中項中指定的經快取資訊來判定與目標PA相關聯的保護資訊。若目標PA在顆粒保護資訊快取記憶體22中未命中，則向記憶體系統發送至少一個記憶體存取請求，以請求從記憶體返回對應於目標PA的顆粒保護項。FIG13 is a flow chart illustrating a method by which the PAS filter 20 (checking circuitry) performs protection checking at the three-stage level shown in FIG9 . In step 200 , the PAS filter 20 obtains protection information GPT[PA] corresponding to the target physical address (PA) obtained by the address translation circuitry 16 in response to a memory access request. For example, the PAS filter 20 searches for the target PA in the granular protection information cache 22 . If a hit is found for the target PA, the PAS filter 20 determines the protection information associated with the target PA based on the cached information specified in the hit entry in the granular protection information cache 22 . If the target PA does not hit in the granular protection information cache 22, at least one memory access request is sent to the memory system to request the granular protection entry corresponding to the target PA to be returned from the memory.
例如，PAS過濾器20可具有儲存用以定義顆粒保護資訊之顆粒保護表的基底位址的暫存器，且可根據基底位址及目標PA產生經發布以請求相關顆粒保護項之（多個）記憶體存取請求的（多個）位址。更新儲存GPT基底位址之暫存器的權限可能僅限於在根域中執行的軟體（在例外等級EL3）。For example, the PAS filter 20 may have a register storing the base address of a granular protection table used to define granular protection information, and may generate the address(es) of memory access requests issued to request the relevant granular protection entries based on the base address and the target PA. The permission to update the register storing the GPT base address may be limited to software running in the root domain (at exception level EL3).
儘管一些實施方案可使用能夠在單一存取中存取所需粒度保護項的線性表結構，但其他方法可使用類似於位址轉譯電路系統16用於存取位址轉譯映射之多層頁表的階層式表結構，從而可能需要發布多於一個記憶體存取請求來逐步通過多層顆粒保護表，其中各層顆粒保護表基於目標PA的各別部分進行索引，且在一層顆粒保護表中的項中提供的指針提供可用以導出下一層顆粒保護表將經存取之位址的基底位址。一旦從記憶體返回了對應於原始記憶體存取的目標PA的相關顆粒保護項，則由該項指定的索引可用以識別一組屬性儲存位置中的一者。屬性儲存位置可例如被提供為記憶體系統中的位置（其可可選地經快取以用於更快的存取），或可提供在一組暫存器中。對應於目標PA的顆粒保護資訊可從對應於相關顆粒保護項指定之索引的屬性儲存位置中擷取。While some implementations may use a linear table structure capable of accessing the desired granularity protection entries in a single access, other approaches may use a hierarchical table structure similar to the multiple levels of page tables used by the address translation circuitry 16 to access the address translation mapping, whereby more than one memory access request may need to be issued to step through multiple levels of granular protection tables, where each level of granular protection table is indexed based on a respective portion of the target PA, and where a pointer provided in an entry in one level of granular protection table provides a base address that can be used to derive the address to be accessed by the next level of granular protection table. Once the relevant granular protection entry corresponding to the target PA of the original memory access is returned from memory, the index specified by the entry can be used to identify one of a set of attribute storage locations. The attribute storage location can be provided, for example, as a location in the memory system (which can optionally be cached for faster access) or in a set of registers. The granular protection information corresponding to the target PA can be retrieved from the attribute storage location corresponding to the index specified by the relevant granular protection entry.
因此，在步驟200，允許PAS過濾器20判定對應於目標PA的顆粒保護資訊之編碼的資訊由PAS過濾器20識別。此可基於快取記憶體22中經快取資訊或基於記憶體中儲存的資訊來識別。Thus, in step 200, information that allows the PAS filter 20 to determine the encoded particle protection information corresponding to the target PA is identified by the PAS filter 20. This identification may be based on cached information in the cache 22 or based on information stored in memory.
在步驟202，PAS過濾器20基於識別對應於目標PA之顆粒保護資訊的資訊來判定是否允許記憶體存取請求。若記憶體存取請求不被允許，則在步驟204拒絕記憶體存取請求，且對故障進行傳訊。若判定允許記憶體存取請求，則在步驟206允許記憶體存取請求繼續進行。In step 202, the PAS filter 20 determines whether to allow the memory access request based on the information identifying the granular protection information corresponding to the target PA. If the memory access request is not allowed, the memory access request is denied in step 204 and a fault is signaled. If the memory access request is allowed, the memory access request is allowed to proceed in step 206.
圖14繪示可用於轉譯表結構及實體定址表結構（例如，GPT）的多層表結構。Figure 14 illustrates a multi-level table structure that may be used for a translation table structure and a physical address table structure (e.g., GPT).
MMU 16或SMMU 26基於位址映射將虛擬位址轉譯成實體位址。虛擬位址與實體位址之間的映射儲存在轉譯表（有時稱為頁表）中。轉譯表儲存在記憶體中且由軟體（一般係OS或超管理器）管理。轉譯表並非靜態的，且可隨著軟體需求的變化而更新表。此改變了虛擬位址與實體位址之間的映射。轉譯表亦可指定存取控制屬性，諸如關於記憶體區域是否可分別由讀取存取、寫入存取、及指令提取存取（用於提取可執行指令）來存取的資訊。The MMU 16 or SMMU 26 translates virtual addresses into physical addresses based on an address map. The mapping between virtual and physical addresses is stored in a translation table (sometimes called a page table). The translation table is stored in memory and managed by software (typically an OS or hypervisor). The translation table is not static and can be updated as the software's needs change. This changes the mapping between virtual and physical addresses. The translation table can also specify access control attributes, such as whether a memory area can be accessed by read access, write access, and instruction fetch access (for fetching executable instructions), respectively.
對於當處理電路系統4處於執行狀態的某個子集時（具體地，當處理電路系統4處於圖5所示之例外模型中的EL0或EL1時）進行的記憶體存取，使用二階位址轉譯（對於其他執行狀態使用1階頁表進行位址轉譯的一個階段就足夠了）。因此，來自EL0及EL1的虛擬位址使用兩組表進行轉譯。此等表支援虛擬化，且允許超管理器虛擬化給定虛擬機器(virtual machine, VM)（對應於客作業系統及由該客作業系統控制之應用的虛擬機器）所看到的實體記憶體視圖。吾人將由OS控制的該組轉譯稱為1階。1階表將虛擬位址(VA)轉譯為中間實體位址(intermediate physical address, IPA)。在1階，OS認為IPA係實體位址。然而，超管理器控制稱為2階的第二組轉譯映射。此第二組轉譯映射將IPA轉譯為實體位址(PA)。儘管有其等的名稱，中間實體位址並非實體位址，因為其等不對應於記憶體中的位置，而該名稱源自OS認為IPA係PA的事實。For memory accesses made while the processing circuitry 4 is in a certain subset of execution states (specifically, when the processing circuitry 4 is at EL0 or EL1 in the exception model shown in FIG5 ), second-level address translation is used (for other execution states, a single stage of address translation using a level 1 page table is sufficient). Thus, virtual addresses from EL0 and EL1 are translated using two sets of tables. These tables support virtualization and allow the hypervisor to virtualize the view of physical memory seen by a given virtual machine (VM) (corresponding to the guest operating system and the VMs controlled by the guest operating system). We refer to the set of translations controlled by the OS as level 1. Level 1 tables translate virtual addresses (VAs) into intermediate physical addresses (IPAs). At level 1, the OS considers IPAs to be physical addresses. However, the hypervisor controls a second set of translation maps, called level 2. This second set of translation maps translates IPAs into physical addresses (PAs). Despite their name, intermediate physical addresses are not physical addresses because they do not correspond to locations in memory. The name comes from the fact that the OS considers IPAs to be PAs.
1階及2階轉譯表經實施為包含數個層級的轉譯表的階層式多層表結構，如圖14所示。在此實例中，1階表及2階表二者最多可具有4層頁表，亦即0層(L0)、1層(L1)、2層(L2)、及3層(L3)。The level 1 and level 2 translation tables are implemented as a hierarchical multi-level table structure including several levels of translation tables, as shown in Figure 14. In this example, both the level 1 and level 2 tables can have up to four levels of page tables, namely level 0 (L0), level 1 (L1), level 2 (L2), and level 3 (L3).
為了定位給定位址的實體位址映射，進行包含一或多個轉譯表查找的轉譯表走訪。轉譯表走訪係將虛擬位址轉譯成實體位址所需的一組查找（記憶體存取）。對於EL1&0轉譯機制(regime)，此組包括對1階轉譯及2階轉譯二者的查找。使用1階及2階查找成功轉譯表走訪返回的資訊係： • 所需的實體位址（基於到中間位址的1階映射及到實體位址的2階映射進行轉譯）。 • 目標記憶體區域的存取權限及/或記憶體屬性，其提供有關如何控制對該記憶體區域之存取的資訊。此等可包括在1階表結構中定義的1階存取權限及/或屬性以及在2階表結構中定義的2階存取權限及/或屬性。To locate the physical address mapping for a given address, a translation table walk consisting of one or more translation table lookups is performed. A translation table walk is the set of lookups (memory accesses) required to translate a virtual address into a physical address. For the EL1&0 translation regime, this set includes lookups for both level-1 and level-2 translations. The information returned by a successful translation table walk using level-1 and level-2 lookups is:• The desired physical address (translated based on the level-1 mapping to the intermediate address and the level-2 mapping to the physical address).• The access permissions and/or memory attributes of the target memory region, which provide information about how access to that memory region is controlled. These may include first-level access permissions and/or attributes defined in a first-level table structure and second-level access permissions and/or attributes defined in a second-level table structure.
為了遍歷1階及2階結構中的給定一者，走訪首先基於轉譯表基底位址暫存器中指定的位址讀取頂層(L0)轉譯表以進行初始查找（例如，1階的TTBR，2階的VTTBR_EL2）。各轉譯表查找均返回一描述符，該描述符指示以下中的一者： • 該項係1階或2階結構遍歷的最終項，其提供了正經查找的位址映射及記憶體區域權限/屬性。若該項位於最終層表L3中，則該項稱為頁描述符(D_Page)，而若提供走訪的最終項的項處於更高層中的一者，則該項稱為區塊描述符(D_Block)。遍歷的最終項含有輸出位址（亦即1階的IPA或2階的PA）以及用於存取的權限及屬性。若在轉譯表結構的更高層找到區塊描述符，則此意謂著該區塊描述符表示比由L3處的單一項表示的4kB記憶體頁大小更大的記憶體區域（由L1及L2處的區塊描述符表示的特定大小取決於用以索引到L1或L2表中之索引位元的數目，例如，L1及L2區塊描述符可分別表示1GB及2MB區域）。 • 需要額外的查找層級。在此情形中，該項稱為表描述符(D_Table)，因為其提供了一指標，指示用於在進一步層級的表中進行查找的轉譯表基底位址。表描述符亦可以可選地提供可應用於最終轉譯的其他階層式屬性。1層及2層之轉譯表項的編碼將區塊描述符與表格描述符區分開。 • 描述符無效。在此情形中，記憶體存取會產生轉譯錯誤。To traverse a given level 1 or level 2 structure, the walk begins by reading the top-level (L0) translation table for an initial lookup (e.g., TTBR for level 1, VTTBR_EL2 for level 2) based on the address specified in the translation table base address register. Each translation table lookup returns a descriptor that indicates one of the following:• The entry that is the final entry in the level 1 or level 2 structure traversal, which provides the address mapping and memory region permissions/attributes being looked up. If the entry is in the final level table, L3, it is called a page descriptor (D_Page); if the entry providing the final entry of the walk is in one of the higher levels, it is called a block descriptor (D_Block). The final entry in the traversal contains the output address (i.e., the IPA for level 1 or the PA for level 2) as well as the permissions and attributes used for access. If a block descriptor is found at a higher level in the translation table structure, this means that the block descriptor represents a memory region larger than the 4kB memory page size represented by a single entry at L3 (the specific size represented by block descriptors at L1 and L2 depends on the number of index bits used to index into the L1 or L2 table; for example, L1 and L2 block descriptors can represent 1GB and 2MB regions, respectively).• An additional lookup level is required. In this case, the entry is called a table descriptor (D_Table) because it provides a pointer to the translation table base address used for lookups in tables at further levels. Table descriptors can optionally provide other hierarchical attributes that are applied to the final translation. The encoding of level 1 and level 2 translation table entries distinguishes block descriptors from table descriptors.• The descriptor is invalid. In this case, memory accesses result in a translation error.
圖14繪示使用依據VA（針對1階）或IPA（針對2階）之位元推導的索引值對1階及2階轉譯表的索引。在1階轉譯表的給定層級內選擇的特定項係基於索引值來判定的，該索引值對應作為查找的輸入位址提供的VA或IPA的某一位元子集或從其推導。各層級均基於VA或IPA的不同位元子集進行索引，其中給定層級基於VA/IPA的位元比結構中的下一層級更重要的部分進行索引（例如，L2使用比L1更不重要的位元部分進行索引）。給定表中相關項的位址係藉由將多個索引位元加入至該給定表的基底位址來獲得，該基底位址如基於TTBR或上一層級之表描述符中指定的位址所判定（應用於對應於一個轉譯表項之大小之索引值的乘數）。Figure 14 illustrates indexing the level 1 and level 2 translation tables using index values derived from bits of the VA (for level 1) or IPA (for level 2). The specific entry selected within a given level of the level 1 translation table is determined based on an index value that corresponds to or is derived from a subset of bits of the VA or IPA provided as the input address for the lookup. Each level is indexed based on a different subset of bits of the VA or IPA, with a given level indexed based on a more significant portion of the bits of the VA/IPA than the next level in the structure (e.g., L2 is indexed using a less significant portion of bits than L1). The address of the relevant entry in a given table is obtained by adding a number of index bits to the base address of the given table, as determined based on the address specified in the TTBR or the table descriptor of the next higher level (applied as a multiplier to the index value corresponding to the size of a translation table entry).
實際上，當進行包括1階轉譯及2階轉譯二者的完整轉譯表走訪時，則從TTBR獲得的各1階表基底位址及在1階L0、L1、L2轉譯表中存取的表描述符將係中間位址，其本身需要使用2階轉譯表進行轉譯。因此，若轉譯表走訪沒有遇到任何區塊描述符，而是一直前進到找到頁描述符的L3，則完整頁表走訪程序可包括24次記憶體存取（1階的4次查找、及2階的5*4查找，其中4個1階表基底位址(L0-L3)及1階L3位址映射返回之最終IPA中的每一者的轉譯均導致對此5個位址中之每一者之2階L0-L3表的一組單獨的4次查找）。In practice, when a full translation table walk is performed, including both level-1 and level-2 translation, the level-1 table base addresses obtained from the TTBR and the table descriptors accessed in the level-1 L0, L1, and L2 translation tables will be intermediate addresses, which themselves need to be translated using the level-2 translation tables. Therefore, if the translation table walk does not encounter any block descriptors, but proceeds all the way to L3 where a page descriptor is found, the full page table walk may include 24 memory accesses (4 lookups at level 1, and 5*4 lookups at level 2, where the translation of each of the four level 1 table base addresses (L0-L3) and the final IPA returned by the level 1 L3 address mapping results in a separate set of 4 lookups to the level 2 L0-L3 tables for each of these 5 addresses).
因此，在沒有任何快取的情況下，進行整個頁表走訪程序可能會極其緩慢，因為可能需要對記憶體的大量存取才能針對位址轉譯之階段之各者逐步通過頁表之層級之各者。此係為何經常需要在MMU 16或SMMU 28的TLB 18、28中快取從轉譯表走訪推導的資訊。經快取資訊可包括以下中之任一者： - 從VA到IPA的最終1階位址映射， - 從IPA到PA的最終2階映射， - 從VA直接到PA的組合1階及2階映射（從先前對1階及2階結構的查找推導）， - 從1階及2階結構中獲得的存取權限及屬性；及 - 從1階及2階表之更高層頁表的項推導的轉譯表指標。即使給定目標位址的最終層位址映射目前不在位址轉譯快取中，此亦可允許繞過全頁表走訪的至少一些步驟。Therefore, without any caching, performing the entire page table walk process can be extremely slow, as it may require numerous accesses to memory to step through each level of the page table for each stage of address translation. This is why it is often necessary to cache information derived from translation table walks in the TLB 18, 28 of the MMU 16 or SMMU 28. The cached information may include any of the following:- The final level-1 address mapping from VA to IPA,- The final level-2 mapping from IPA to PA,- The combined level-1 and level-2 mappings from VA directly to PA (derived from previous lookups in the level-1 and level-2 structures),- Access permissions and attributes obtained from the level-1 and level-2 structures; and- Translation table pointers derived from entries in higher-level page tables than the level-1 and level-2 tables. This allows bypassing at least some steps of the full page table walk even if the final level-1 address mapping for a given target address is not currently in the address translation cache.
如圖14所示，實體定址表結構可具有與轉譯表類似的多層結構，儘管最大層數可與轉譯表結構的最大層數不同。基於從處理器4或SMMU 28的暫存器獲得的實體定址表結構基底位址來存取實體定址表結構，該暫存器能夠由在管理執行狀態EL3下操作的軟體寫入，且在較低特權執行狀態EL1及EL2下不能夠寫入，該較低特權執行狀態EL1及EL2經允許分別更新儲存1階及2階表之基底位址的暫存器（亦可允許在EL2操作的軟體設定1階基底位址）。因此，允許設定1階基底位址的最低特權狀態係EL1，允許設定2階基底位址的最低特權狀態係EL2，且允許設定實體定址表結構基底位址的最低特權狀態係EL3。As shown in Figure 14, the physical address table structure may have a multi-level structure similar to the translation table, although the maximum number of levels may be different from the maximum number of levels of the translation table structure. The physical address table structure is accessed based on its base address obtained from a register in the processor 4 or the SMMU 28. The register is writable by software operating in the supervisor execution state EL3 and is not writable in the lower privilege execution states EL1 and EL2. The lower privilege execution states EL1 and EL2 are allowed to update the registers storing the base addresses of the level 1 and level 2 tables, respectively (software operating at EL2 may also be allowed to set the level 1 base address). Therefore, the lowest privilege state allowed for setting a level 1 base address is EL1, the lowest privilege state allowed for setting a level 2 base address is EL2, and the lowest privilege state allowed for setting a physical address table structure base address is EL3.
與轉譯表不同，實體定址表結構使用實體位址來定址，其中遍歷係基於在由MMU 16或SMMU 28基於來自轉譯表的映射進行的轉譯中產生的PA。Unlike translation tables, physical address table structures are addressed using physical addresses, where traversal is based on the PA generated in the translation performed by the MMU 16 or SMMU 28 based on the mapping from the translation table.
實體定址表結構藉由識別指向儲存屬性資訊的屬性儲存位置的索引，將一組屬性資訊與實體位址的各區域相關聯。若在實體定址表結構的最終層表中定義索引，則屬性資訊可與特定大小（例如4KB）的實體位址顆粒相關聯。由於實體定址表結構的對應項不需要指定位址轉譯映射，因此給定4KB區域的項可比為該區域提供位址映射的轉譯表項小得多，且因此各別4KB區域的多個項可經打包到單一快取線中，使得實體定址表結構可比轉譯表更緊湊，且因此涉及更少表層的結構可係實用的。例如，圖14顯示具有兩層結構之實體定址表結構的實例，其中基於由對應於目標PA的L0實體定址表結構的項提供的表指標來存取L1實體定址表結構。用於實體定址表結構之各層級的索引係基於目標PA的各別位元子集來選擇，其中使用比用於索引L0表之位元的部分更不重要的目標PA之位元的有效部分來索引L1表。應理解，2層實體定址表結構僅係一個實例，且其他實例可取決於為其定義索引的粒度（區域大小）而具有不同數目的實體定址表結構層級。由實體定址表結構的給定項中指定的索引識別的各組屬性資訊可至少指定上述基於PAS的權限，但亦可描述其他屬性資訊，如下面進一步實例中所解釋的。The physical address table structure associates a set of attribute information with each region of the physical address by identifying an index pointing to the attribute storage location where the attribute information is stored. If an index is defined in the final level table of the physical address table structure, the attribute information can be associated with a physical address granule of a specific size (e.g., 4KB). Because the corresponding entry of the physical address table structure does not need to specify an address translation mapping, the entry for a given 4KB region can be much smaller than the translation table entry that provides the address mapping for that region, and therefore multiple entries for respective 4KB regions can be packed into a single cache line, making the physical address table structure more compact than the translation table, and therefore a structure involving fewer table levels can be practical. For example, FIG14 shows an example of a physical address table structure having a two-level structure, wherein an L1 physical address table structure is accessed based on a table pointer provided by an entry in the L0 physical address table structure corresponding to a target PA. The index used for each level of the physical address table structure is selected based on a respective subset of bits of the target PA, wherein a less significant portion of the bits of the target PA is used to index the L1 table. It should be understood that a two-level physical address table structure is only one example, and other examples may have a different number of physical address table structure levels depending on the granularity (region size) for which the index is defined. Each set of attribute information identified by an index specified in a given entry of the entity address table structure may specify at least the PAS-based permissions described above, but may also describe other attribute information, as explained in the further examples below.
在參考圖4至圖13所描述的系統中，屬性資訊已經描述為包括PAS的指示（目標實體位址可從該PAS取得），及在一些實例中，經允許域（對目標實體位址的記憶體存取請求經允許域處於其中，以便授權請求）。應理解，此等僅係實例，且其他屬性可由屬性資訊指示。In the systems described with reference to FIG4 through FIG13 , the attribute information has been described as including an indication of a PAS (from which the target entity address can be obtained) and, in some examples, an allowed domain (the allowed domain within which a memory access request for the target entity address is located in order to authorize the request). It should be understood that these are merely examples, and other attributes may be indicated by the attribute information.
例如，圖15示意地繪示經標籤守衛的記憶體存取之概念。用以提及記憶體系統內之記憶體位置的實體位址空間可邏輯地分割成若干區塊150，其各自包含特定數目的可定址位置。為了簡潔，在圖15之實例中，各區塊150包含四個記憶體位置，但亦可使用其他區塊大小。各區塊150與對應的守衛標籤152（亦稱為記憶體標籤）相關聯。可將與特定數目的區塊150相關聯之守衛標籤收集在一起並儲存在實體位址空間內之不同的架構上可存取的記憶體位置154內，或者在架構上非可存取（未經映射至相同的實體位址空間）之主記憶體中所提供的額外儲存位置內。使用分開的非架構上可存取的儲存在一些情形中可係較佳的，以避免耗盡用於快取守衛標籤值之資料快取記憶體中的空間，其可能衝擊正規碼的性能並可能使一致性管理更複雜。可在微架構中提供額外的標籤快取記憶體以用於快取來自非架構上可存取之儲存的標籤值，以用於比必須從主記憶體存取標籤時更快的存取。哪些標籤儲存位置154對應於各區塊150的特定映射可由負載/儲存單元控制，並可係固線式或可係可程式化的。For example, Figure 15 schematically illustrates the concept of tag-guarded memory access. The physical address space used to refer to memory locations within a memory system can be logically divided into a number of blocks 150, each of which contains a specific number of addressable locations. For simplicity, in the example of Figure 15, each block 150 contains four memory locations, but other block sizes can also be used. Each block 150 is associated with a corresponding guard tag 152 (also called a memory tag). The guard tags associated with a particular number of blocks 150 may be collected together and stored in different architecturally accessible memory locations 154 within the physical address space, or in additional storage locations provided in main memory that is architecturally non-accessible (not mapped to the same physical address space). Using separate, non-architecturally accessible storage may be preferable in some circumstances to avoid using up space in the data cache for caching guard tag values, which may impact regular code performance and may complicate coherency management. Additional tag cache memory may be provided in the micro-architecture for caching tag values from non-architecturally accessible storage for faster access than if the tags had to be accessed from main memory. Which tag storage locations 154 correspond to a particular mapping of each block 150 may be controlled by the load/store unit and may be hard-wired or programmable.
因此，當需要經標籤守衛的記憶體存取時，比較位址標籤160與守衛標籤152。位址標籤160係與識別待存取之經定址位置164的目標位址162相關聯，且守衛標籤152與包括經定址位置164之記憶體位置區塊150相關聯。例如，在圖15中，目標位址162指向記憶體中的特定位置B1，在圖15的位址空間中標記為164。因此，與包括位置B1之位置區塊B相關聯的守衛標籤B係針對與目標位址164相關聯的位址標籤160作比較。Thus, when a tag-guarded memory access is required, address tag 160 is compared to guard tag 152. Address tag 160 is associated with target address 162 identifying addressed location 164 to be accessed, and guard tag 152 is associated with memory location block 150 including addressed location 164. For example, in FIG15 , target address 162 points to a specific location B1 in memory, designated 164 in the address space of FIG15 . Thus, guard tag B associated with location block B including location B1 is compared against address tag 160 associated with target address 164.
如圖15頂部所示，位址標籤160可在目標位址本身的經選擇位元內經指示，使得其可經判定為隨目標位址的經選擇位元而變動。具體地，位址標籤可從目標位址的一部分內之位元判定，該部分未用於指示待選擇作為經定址位置164之特定記憶體位置。例如，在一些架構中，目標位址之位元的頂部部分可總是具有某個固定值，諸如符號延伸（全0或全1），其不用以選擇經定址位置，且因此可重新用以儲存位址標籤，且因此可藉由用任意標籤值覆寫此等未經使用的位元來用位址標籤160標記位址。特定位址標籤值可由例如程式設計人員或編譯器選擇。位址標籤及守衛標籤152可係相對小的位元數目（例如，4個位元），且因此在記憶體內及在目標位址內不需佔據太多空間。提供4個位元的標籤空間（即，標籤的16個可能值）常可足以偵測許多共同類型的記憶體存取錯誤。15 , the address tag 160 may be indicated within selected bits of the target address itself so that it may be determined to vary with the selected bits of the target address. Specifically, the address tag may be determined from bits within a portion of the target address that are not used to indicate a particular memory location to be selected as the addressed location 164. For example, in some architectures, the top portion of the bits of the target address may always have a fixed value, such as a sign-extended (all 0s or all 1s), which is not used to select the addressed location and may therefore be reused to store the address tag, and thus an address may be marked with the address tag 160 by overwriting these unused bits with an arbitrary tag value. The particular address tag value may be selected by, for example, a programmer or compiler. The address tag and guard tag 152 can be a relatively small number of bits (e.g., 4 bits) and therefore do not take up much space in memory and in the target address. Providing 4 bits of tag space (i.e., 16 possible values for the tag) is often sufficient to detect many common types of memory access errors.
因此，當執行經標籤守衛的記憶體存取時，負載/儲存單元比較位址標籤160及（與包括經定址位置164之區塊150相關聯的）守衛標籤152，且判定其等是否匹配。負載/儲存單元產生匹配指示，其指示位址標籤160與守衛標籤152是否匹配。例如，此匹配指示可係若在位址標籤160與守衛標籤152之間存在不匹配而產生的錯誤信號。替代地，匹配指示可係放置在狀態暫存器中之指示是否存在匹配的指示。此外，匹配指示可係添加至錯誤報告的項，以指示偵測到錯誤的位址及/或觸發錯誤之指令的指令位址。若位址標籤與守衛標籤之間不匹配，則可阻止記憶體存取請求。替代地，可允許記憶體存取請求繼續進行且報告錯誤以供稍後分析。Thus, when performing a tag-guarded memory access, the load/store unit compares the address tag 160 and the guard tag 152 (associated with the block 150 including the addressed location 164) and determines whether they match. The load/store unit generates a match indication indicating whether the address tag 160 and the guard tag 152 match. For example, this match indication may be an error signal generated if there is a mismatch between the address tag 160 and the guard tag 152. Alternatively, the match indication may be an indication placed in a status register indicating whether a match exists. Additionally, a match indication can be added to the error report entry to indicate the address where the error was detected and/or the instruction address of the instruction that triggered the error. If there is a mismatch between the address tag and the guard tag, the memory access request can be blocked. Alternatively, the memory access request can be allowed to proceed and the error reported for later analysis.
記憶體標記可用於識別導致位址計算不正確的錯誤。指定不正確計算之位址的記憶體存取請求將與對應於正確位址的位址標籤相關聯，因為位址標籤與位址指標而非經計算位址值相關聯。不正確的位址將指向具有不太可能匹配與請求相關聯的位址標籤之守衛標籤的位置，因為位址標籤並非意圖匹配與記憶體中的不正確位置相關聯的守衛標籤。Memory tags can be used to identify errors that result in incorrect address calculations. A memory access request that specifies an incorrectly calculated address will be associated with an address tag that corresponds to the correct address because address tags are associated with address pointers, not calculated address values. An incorrect address will point to a location with a guard tag that is unlikely to match the address tag associated with the request because address tags are not intended to match guard tags associated with incorrect locations in memory.
在使用目標位址的一部分以判定位址標籤的實例中，須注意此位址標籤不同於目標位址的標籤部分，該標籤部分可由快取記憶體使用以判定來自由目標位址識別之經定址位置的資訊是否儲存在快取記憶體內。許多快取方案可將經快取資料的位址之一標籤部分儲存在快取記憶體內之該資料旁邊，使得在快取記憶體內搜尋給定位址方面，可比較該位址之部分與儲存在經快取資料旁邊的標籤，以判定該經快取資料是否實際對應於該所需位址。然而，在此情況中，與快取記憶體中之標籤相比較的位址之標籤部分將係實際上識別所需要之資料的特定經定址位置的位址之部分的部分，即，依據定義，改變位址之快取標籤部分將導致指向記憶體系統內之不同經定址位置的位址。相比之下，在位址標籤用於經標籤守衛的記憶體存取的情況下，記憶體存取電路系統可獨立於位址標籤選擇需要資料的經定址位置。亦即，即使位址標籤具有不同的值，由目標位址引用的經定址位置仍可係相同的，因為定址位置的選擇僅取決於目標位址的其他部分。此授予編譯器自由度以將與特定位址相關聯的位址標籤設定為任何值，以匹配已分配給記憶體系統中的相關資料區塊之對應的守衛標籤值。In instances where a portion of a target address is used to determine an address tag, it is important to note that this address tag is distinct from the tag portion of the target address, which may be used by the cache to determine whether information from the addressed location identified by the target address is stored in the cache. Many caching schemes may store a tag portion of the address of cached data next to the data in the cache, so that when searching for a given address in the cache, the portion of the address may be compared to the tag stored next to the cached data to determine whether the cached data actually corresponds to the desired address. However, in this case, the tag portion of the address that is compared to the tag in the cache will be the portion of the address that actually identifies the specific addressed location of the desired data. That is, by definition, changing the cache tag portion of the address will result in the address pointing to a different addressed location within the memory system. In contrast, where address tags are used for tag-guarded memory accesses, the memory access circuitry can select the addressed location of the desired data independently of the address tag. That is, even if the address tag has a different value, the addressed location referenced by the target address can still be the same because the selection of the addressed location depends only on the other portion of the target address. This gives the compiler freedom to set the address tag associated with a particular address to any value that matches the corresponding guard tag value assigned to the associated data block in the memory system.
在一些實例中，記憶體標記可僅針對記憶體位置的子集啟用，諸如具有較高安全性要求的位置。情形可能如此，因為記憶體標記可能會在記憶體存取上產生一些延時，且產生儲存每個記憶體位置的守衛標籤所需的儲存空間可能係非所欲的。因此，所欲的係，提供對記憶體的哪些區域係需要標籤檢查的區域及哪些係停用記憶體標記的區域的指示，以便知道如何處理記憶體存取請求。本發明人已經認識到實體定址表結構提供了用於提供此資訊的特別方便的機制，因為其已經將一些屬性與各記憶體位置相關聯且在記憶體存取時經查找。因此，將使用實體定址表結構來指示目標實體位址是否位於啟用記憶體標記的區域中。此似乎係不尋常的，因為若實體定址表結構直接在其項中指定屬性資訊，則產生表示目標實體位址是否需要標籤檢查之指示的成本可能更難證明係合理的。然而，本發明人已經認識到，由於在一組屬性儲存位置中間接指定屬性資訊，因此這消除了在屬性資訊中表示目標位址是否位於需要進行標籤檢查之記憶體區域內的指示的障礙。In some instances, memory tagging may be enabled only for a subset of memory locations, such as locations with higher security requirements. This may be the case because memory tagging may introduce some delay in memory accesses, and the storage space required to store a guard tag for each memory location may be undesirable. Therefore, it is desirable to provide an indication of which areas of memory require tag checking and which areas have memory tagging disabled so that a memory access request is handled. The inventors have recognized that the physical address table structure provides a particularly convenient mechanism for providing this information because it already has attributes associated with each memory location that are looked up when the memory is accessed. Therefore, a physical address table structure is used to indicate whether the target physical address is located in a region of memory that has tagging enabled. This may seem unusual because if the physical address table structure specifies attribute information directly in its entries, the cost of generating an indication of whether the target physical address requires tag checking may be more difficult to justify. However, the inventors have recognized that by indirectly specifying the attribute information in a set of attribute storage locations, this eliminates the obstacle of indicating in the attribute information whether the target address is located in a region of memory that requires tag checking.
除了對目標實體位址是否位於受記憶體標記保護之區域的指示之外，屬性資訊亦可提供對目標實體位址是否位於儲存記憶體標籤（守衛標籤）之區域的指示，諸如圖15中的位置154。可限制對守衛標籤的存取以防止對守衛標籤的不正確修改。例如，一些系統可能僅允許某些類型的記憶體存取請求修改守衛標籤，且因此當處理記憶體存取請求時，目標實體位址是否位於儲存守衛標籤的區域中可能係相關的。實體定址表結構提供了一種特別方便的機制來追蹤此等權限，且藉由將屬性儲存在屬性儲存位置中來使用間接，使得能夠以較在表的各項中直接指定權限低得多的開銷來實現此一點。In addition to indicating whether the target entity address is located in an area protected by a memory tag, the attribute information may also provide an indication of whether the target entity address is located in an area where memory tags (guard tags) are stored, such as location 154 in FIG. 15 . Access to guard tags may be restricted to prevent improper modification of guard tags. For example, some systems may only allow certain types of memory access requests to modify guard tags, and therefore, when processing a memory access request, whether the target entity address is located in an area where guard tags are stored may be relevant. The entity address table structure provides a particularly convenient mechanism for tracking such permissions, and uses indirection by storing attributes in the attribute store, allowing this to be done with much less overhead than specifying the permissions directly in the table entries.
在包含複數個請求者裝置（例如，圖4中的處理器4或其他裝置252）的一些系統中，各請求者裝置可與用以將能夠起始對記憶體之存取的硬體裝置分組為二或更多個群組的請求者群組識別符(RGID)相關聯。請求者硬體裝置的RGID可係在不可組態儲存器中永久指派給請求者硬體裝置的固線式識別符，或可在設備2啟動時由啟動碼靜態程式化，且接著在運行時不改變。替代地，RGID可儲存在可在運行時更新的可組態儲存器中（例如，基於在允許設定顆粒保護表基底位址的最高特權執行狀態EL3處執行的指令）。此外，在一些情形中，給定請求者硬體裝置（諸如硬體加速器或GPU）可能具有識別與二或更多不同執行上下文相關聯之RGID的表，且基於哪個執行上下文導致發布該存取來選擇為給定記憶體存取指定的RGID。In some systems that include a plurality of requester devices (e.g., processor 4 or other device 252 in FIG. 4 ), each requester device may be associated with a requester group identifier (RGID) that is used to group hardware devices that can initiate access to memory into two or more groups. The RGID of a requester hardware device may be a hard-wired identifier that is permanently assigned to the requester hardware device in non-configurable memory, or it may be statically programmed by startup code when device 2 boots up and then does not change at runtime. Alternatively, the RGID may be stored in a configurable register that can be updated at runtime (e.g., based on an instruction executed at EL3, the highest privileged execution state that allows setting the base address of the granule protection table). Furthermore, in some cases, a given requester hardware device (such as a hardware accelerator or GPU) may have a table identifying RGIDs associated with two or more different execution contexts, and select the RGID to specify for a given memory access based on which execution context caused the access to be issued.
對應於目標實體位址的屬性資訊可包括在記憶體存取請求期間使用的一或多個屬性，以判定哪些請求者硬體裝置群組（如請求者群組識別符所識別的）經允許存取（或被禁止存取）給定目標實體位址。此意謂著可能定義權限，從而使兩個硬體裝置具有不同的權限來存取相同實體位址空間中的相同實體位址，從而相較於不提供基於RGID之控制的實例中之可能控制，提供對安全性的更大控制。由於RGID權限與特定的實體位址相關聯，因此實體定址表結構提供了特別方便的機制來表示此等屬性。在實體定址表結構的各個別項中表示RGID權限可能係不合理的，但提供該組屬性儲存位置允許指定更大量的屬性資訊，且因此藉由在屬性儲存位置中而非直接在實體定址表結構項中提供屬性資訊，使用實體定址表結構將RGID權限與實體位址的顆粒相關聯變得更加合理。The attribute information corresponding to a target physical address may include one or more attributes used during a memory access request to determine which groups of requester hardware devices (as identified by a requester group identifier) are permitted to access (or are prohibited from accessing) a given target physical address. This means that permissions may be defined such that two hardware devices have different permissions to access the same physical address in the same physical address space, thereby providing greater control over security than would be possible in instances where RGID-based control is not provided. Because RGID permissions are associated with specific physical addresses, the physical address table structure provides a particularly convenient mechanism for representing such attributes. It may not be reasonable to represent RGID permissions in individual entries of the physical address table structure, but providing the set of attribute storage locations allows a larger amount of attribute information to be specified, and therefore it becomes more reasonable to use the physical address table structure to associate RGID permissions with particles of physical address by providing the attribute information in the attribute storage locations rather than directly in the physical address table structure entries.
考慮到上面的論述，屬性資訊的一種實例編碼可具有如下分配的位元：Considering the above discussion, one example encoding of attribute information may have the following allocation of bits:
位元[0]有效–指示項是否有效。若此位元的值係0，則此可指示保留編碼。Bit [0] Valid – Indicates whether the entry is valid. If the value of this bit is 0, this may indicate reserved encoding.
位元[1-4] PAS遮罩–表示記憶體存取請求的經允許實體位址空間，其中： 0001 ==安全 0010 ==非安全 0100 ==領域 1000 ==根 使得PAS遮罩位元的組合可指示經允許PAS的不同組合。例如，1010可指示位置僅可從根及非安全PAS存取。Bits [1-4] PAS Mask – Indicates the allowed physical address space for memory access requests, where:0001 == Secure0010 == Non-Secure0100 == Domain1000 == RootCombinations of PAS Mask bits can indicate different combinations of allowed PASs. For example, 1010 can indicate that a location is only accessible from the root and non-secure PASs.
位元[5-8]允許輸入安全狀態遮罩–指示可從哪些域存取實體位址，其中： 0001 ==安全 0010 ==非安全 0100 ==領域 1000 ==根 安全狀態遮罩指示可存取實體位址的經允許域。以與PAS遮罩相同的方式，安全狀態遮罩可指示位元的各種組合，例如，1100指示目標實體位址對於從僅在根域及領域域中操作的處理電路系統發布的記憶體存取請求係可存取的。即使以正確的PAS發布（如PAS遮罩所示），若請求係由已禁止存取目標實體位址的域發布的，則該請求亦可能被拒絕。Bits [5-8] allow entry of the security state mask – indicating the domains from which the physical address can be accessed, where:0001 == Secure0010 == Non-Secure0100 == Domain1000 == RootThe security state mask indicates the permitted domains from which the physical address can be accessed. Similar to the PAS mask, the security state mask can indicate various combinations of bits. For example, 1100 indicates that the target physical address is accessible for memory access requests issued from processing circuitry operating only in the root and domain domains. Even if issued with the correct PAS (as indicated by the PAS mask), a request may be denied if it is issued from a domain that has prohibited access to the target physical address.
位元[9-16] RGID遮罩–指示允許哪些請求者群組存取目標實體位址，其中： 00000001 == RGID 0 00000010 == RGID 1 00000100 == RGID 2 00001000 == RGID 3 00010000 == RGID 4 00100000 == RGID 5 01000000 == RGID 6 10000000 == RGID 7 可以各種不同的方式將請求者群組ID分配給不同類別的請求者。例如，RGID 0可係與CPU相關聯的指示符，使得所有CPU發布的記憶體存取請求與RGID 0指示符相關聯。在其他實例中，特定處理元件可與不同的RGID相關聯。在任何情形下，RGID遮罩指示哪些RGID可由允許的記憶體存取請求指定。若RGID遮罩指示發布記憶體存取請求的請求者不被允許存取目標實體位址，則可引發錯誤且可拒絕該要求。Bits [9-16] RGID Mask – Indicates which requestor groups are allowed to access the target physical address, where:00000001 == RGID 000000010 == RGID 100000100 == RGID 200001000 == RGID 300010000 == RGID 400100000 == RGID 501000000 == RGID 610000000 == RGID 7Requestor group IDs can be assigned to different classes of requesters in various ways. For example, RGID 0 can be a designator associated with the CPU, so that all memory access requests issued by the CPU are associated with the RGID 0 designator. In other examples, a particular processing element may be associated with a different RGID. In any case, the RGID mask indicates which RGIDs may be specified by the permitted memory access request. If the RGID mask indicates that the requestor issuing the memory access request is not permitted to access the target physical address, an error may be raised and the request may be denied.
位元[17-18] R/W權限位元-各位元分別指示是否允許從目標實體位址讀取資料或向目標實體位址寫入資料。儘管此等可作為獨立位元提供，但在一些其他編碼中，R/W權限可與RGID權限組合，使得每個請求者群組提供兩個位元來指示特定於對應請求者群組的R/W權限。Bits [17-18] R/W Permission Bits - Each bit indicates whether data is allowed to be read from or written to the target physical address. Although these may be provided as separate bits, in some other encodings, the R/W permission may be combined with the RGID permission so that each requestor group provides two bits to indicate the R/W permission specific to that requestor group.
圖16係繪示根據本技術之方法的流程圖。在步驟1600，位址轉譯電路系統接收指定目標虛擬位址的記憶體存取請求。例如，使用圖14所繪示的S1及S2轉譯表將目標虛擬位址轉譯成目標實體位址。在此階段，可識別與目標虛擬位址（及/或中間實體位址）相關聯的權限以控制記憶體存取請求的處理。在一些實例中，目標實體位址可藉由轉譯表與實體位址空間相關聯。FIG16 is a flow chart illustrating a method according to the present technology. At step 1600, the address translation circuitry receives a memory access request specifying a target virtual address. For example, the target virtual address is translated into a target physical address using the S1 and S2 translation tables shown in FIG14 . At this stage, permissions associated with the target virtual address (and/or intermediate physical addresses) may be identified to control the processing of the memory access request. In some embodiments, the target physical address may be associated with a physical address space via a translation table.
在獲得目標實體位址之後，屬性判定電路系統可使用目標實體位址在屬性快取記憶體中進行查找，以檢查與目標實體位址相關聯的屬性資訊是否先前已經判定及快取。若此查找導致未命中（或若根本不支援屬性資訊的快取），則在步驟1602，使用位址轉譯電路系統判定的目標實體位址來識別實體定址表結構中的對應項，諸如圖14中指示的那樣。可使用目標實體位址的部分從表格的一或多層中識別對應項。對應項不需要對於目標實體位址係唯一的，且在一些實例中對應於包括目標實體位址的位址顆粒（例如，連續位址，諸如記憶體中的4KB頁）。實體定址表結構可由具有比負責設定轉譯表的軟體更高特權等級的軟體來設定（例如，在一些實例中，對儲存實體定址表結構之記憶體區域的存取可經限制為根PAS (EL3)，請注意，設定實體定址表結構的軟體可負責設定權限，使得對根PAS的存取的此限制對於對應於實體定址表結構的位址經強制執行，且可能不存在設備的硬體特徵來確保已設定相關權限以保證對存取的此限制經強制執行）。因此，實體定址表結構可用以將權限與不易被受損害之OS/超管理器繞過的實體位址相關聯，因此增加了整體系統安全性。After obtaining the target physical address, the attribute determination circuitry may use the target physical address to perform a lookup in the attribute cache to check whether the attribute information associated with the target physical address has been previously determined and cached. If this lookup results in a miss (or if caching of attribute information is not supported at all), then in step 1602, the target physical address determined by the address translation circuitry is used to identify a corresponding entry in a physical address table structure, such as that indicated in FIG14. Portions of the target physical address may be used to identify corresponding entries from one or more levels of the table. The corresponding entry need not be unique to the target physical address and in some instances corresponds to an address granule (e.g., a sequential address, such as a 4KB page in memory) that includes the target physical address. The physical address table structure may be set up by software having a higher privilege level than the software responsible for setting up the translation table (for example, in some examples, access to the memory area where the physical address table structure is stored may be restricted to the root PAS (EL3), noting that the software setting up the physical address table structure may be responsible for setting permissions such that this restriction on access to the root PAS is enforced for addresses corresponding to the physical address table structure, and there may not be hardware features of the device to ensure that the relevant permissions have been set to guarantee that this restriction on access is enforced). Thus, the physical address table structure can be used to associate permissions with physical addresses that are not easily circumvented by a compromised OS/hypervisor, thereby increasing overall system security.
在一些實例中，對應項可直接指定與目標實體位址相關聯的某些屬性。然而，對應項至少指定一索引。在步驟1604，由對應項指定的索引用以識別一組屬性儲存位置中的屬性儲存位置。例如，可將索引添加至基底位址，以識別記憶體中的位置，且記憶體中的位置可係屬性儲存位置。替代地，索引可識別充當屬性儲存位置的暫存器。In some instances, a mapping entry may directly specify certain attributes associated with the target physical address. However, a mapping entry specifies at least an index. In step 1604, the index specified by the mapping entry is used to identify a property storage location in a set of property storage locations. For example, an index may be added to the base address to identify a location in memory, and the location in memory may be the property storage location. Alternatively, the index may identify a register that serves as the property storage location.
在步驟1606，從給定屬性儲存位置判定屬性資訊。從屬性儲存位置而非直接從實體定址表結構的對應項判定屬性資訊意謂著實體定址表結構的項僅需要指定索引，而無需指定一組完整的屬性。因此，可使實體定址表結構的項更小。考慮到在具有大實體位址空間的現代系統中將提供大量項，此可能導致實體定址表結構的大小顯著減少。由於若干項可指定相同索引，且因此可存取相同屬性儲存位置以判定屬性資訊，因此亦可藉由在項之間共用屬性資訊來降低總體儲存要求。In step 1606, attribute information is determined from the given attribute storage location. Determining attribute information from the attribute storage location rather than directly from the corresponding entry in the entity address table structure means that the entry in the entity address table structure only needs to specify an index, rather than a complete set of attributes. Therefore, the entries in the entity address table structure can be made smaller. Considering the large number of entries that will be provided in modern systems with large entity address spaces, this can result in a significant reduction in the size of the entity address table structure. Since several entries can specify the same index and therefore can access the same attribute storage location to determine attribute information, overall storage requirements can also be reduced by sharing attribute information between entries.
使用屬性儲存位置來指定屬性資訊意謂著更大量的屬性資訊可與各實體位址相關聯，而不必增加實體定址表結構的大小（若需要屬性資訊之更大範圍的相異編碼，則可使項更大以指定更大的索引來識別一組更大的屬性儲存位置中的一者，但索引的大小不直接耦合到屬性資訊的大小）。此為將屬性與實體位址相關聯創造了機會，若非此，將更難證明其合理性，並因此允許以新的方式增加裝置安全性。Using attribute storage locations to specify attribute information means that a larger amount of attribute information can be associated with each physical address without increasing the size of the physical address table structure. (If a wider range of distinct encodings of attribute information is required, the entries can be made larger to specify a larger index to identify one of a larger set of attribute storage locations, but the size of the index is not directly coupled to the size of the attribute information.) This creates opportunities to associate attributes with physical addresses that would otherwise be more difficult to justify, and thus allows for new ways to increase device security.
類似於實體定址表本身，若屬性儲存位置係基於記憶體的結構，則對儲存實體定址表結構之記憶體區域的存取可能限於根PAS (EL3)，再次，基於對管理屬性儲存位置之軟體的依賴，設定GPT或與適當儲存屬性的實體位址相關聯的其他屬性。Similar to the physical address table itself, if the attribute storage location is a memory-based structure, access to the memory area where the physical address table structure is stored may be restricted to the root PAS (EL3), again based on the dependency on the software that manages the attribute storage location, setting up the GPT or other attributes associated with the physical address where the attributes are stored appropriately.
在步驟1608，與目標實體位址相關聯的屬性資訊可用以控制記憶體存取請求的處理。屬性資訊亦可經快取（例如，在稍早提到的屬性快取記憶體中），使得將來可更快地識別用以控制對相同目標實體位址或相同顆粒中的另一位址之記憶體存取的屬性。在一些實例中，可快取屬性資訊而不處理記憶體存取本身，例如若記憶體存取請求僅係對將來可能請求對目標虛擬位址之記憶體存取的指示，則充當預提取屬性資訊的提示。At step 1608, attribute information associated with the target physical address may be used to control the processing of the memory access request. The attribute information may also be cached (e.g., in the attribute cache memory mentioned earlier) to enable faster identification of attributes used to control memory access to the same target physical address or another address within the same granule in the future. In some examples, the attribute information may be cached without processing the memory access itself, e.g., to serve as a hint to pre-fetch attribute information if the memory access request is merely an indication that a future memory access to the target virtual address may be requested.
圖17係繪示一種獨立於屬性資訊處理記憶體存取請求之方法的流程圖。在步驟1700，如圖16所示所判定的屬性資訊用以判定經允許類別的記憶體存取請求。此可能包括存取請求之若干特徵的經允許組合，諸如存取請求是讀取或寫入、目標實體位址所在的實體位址空間、發布記憶體存取請求的操作域、發布記憶體存取請求的請求者裝置的類型等。屬性資訊可例如使用如上所述的位元映像來指定屬性資訊，從該屬性資訊可判定經允許類別的存取請求。FIG17 is a flow chart illustrating a method for processing memory access requests independently of attribute information. In step 1700, the attribute information determined as shown in FIG16 is used to determine an allowed class of the memory access request. This may include allowed combinations of characteristics of the access request, such as whether the access request is for a read or write, the physical address space in which the target physical address resides, the operation domain issuing the memory access request, and the type of device issuing the memory access request. The attribute information can be specified, for example, using a bitmap as described above, from which the allowed class of the access request can be determined.
在步驟1702，將記憶體存取請求的性質與屬性資訊進行比較，以判定記憶體存取請求是否係經允許記憶體存取請求。In step 1702, the nature of the memory access request is compared with the attribute information to determine whether the memory access request is an allowed memory access request.
若不是，則在步驟1706觸發錯誤處理回應。此可能涉及拒絕記憶體存取請求及/或對故障進行傳訊。亦可維護錯誤日誌以追蹤錯誤的發生。If not, an error handling response is triggered at step 1706. This may involve denying the memory access request and/or signaling the failure. An error log may also be maintained to track the occurrence of errors.
若屬性資訊指示記憶體存取請求係經允許記憶體存取請求，則在步驟1704，視可能需要進行的任何進一步檢查，諸如基於由轉譯表指定之權限的檢查而定，允許對請求的處理。If the attribute information indicates that the memory access request is an allowed memory access request, then at step 1704, processing of the request is permitted, subject to any further checks that may need to be performed, such as checks based on permissions specified by a translation table.
圖18係繪示用於實體定址表結構之錯誤偵測之方法的流程圖。為了降低儲存成本，可提供沒有錯誤校正位元之實體定址表結構的項。因此，在擷取實體定址表結構的項（例如，從記憶體）時，可能難以識別該項是否已經惡意或意外地修改（例如，藉由隨機位元翻換）。雖然項可在記憶體中加密，使得其等不可經惡意修改為具有特定編碼，但仍然可能存在項可經隨機修改以導致系統行為不正確的機會。FIG18 is a flow chart illustrating a method for error detection of a physical address table structure. To reduce storage costs, entries of the physical address table structure may be provided without error correction bits. Consequently, when an entry of the physical address table structure is retrieved (e.g., from memory), it may be difficult to identify whether the entry has been maliciously or accidentally modified (e.g., by random bit flipping). Although entries may be encrypted in memory so that they cannot be maliciously modified to have a specific encoding, there is still a chance that an entry could be randomly modified to cause the system to behave incorrectly.
可識別錯誤的一種方式係藉由保留實體定址表結構之項的數個編碼，使得其等不能用以指示屬性儲存位置。例如，若各項中有4個位元具有16個可能的編碼，則可能存在（僅作為實例）指示屬性儲存位置中之一者的14個編碼及不能指示屬性儲存位置的2個保留編碼。若對應項具有保留編碼，則可識別出發生了錯誤（因為不應使用該編碼）。One way to identify errors is by reserving some encodings for entries in the physical address table structure so that they cannot be used to indicate attribute storage locations. For example, if 4 bits in each entry have 16 possible encodings, there could be (as an example only) 14 encodings that indicate one of the attribute storage locations and 2 reserved encodings that cannot indicate the attribute storage location. If the corresponding entry has a reserved encoding, it can be identified that an error has occurred (because that encoding should not be used).
使用單一項識別隨機錯誤可具有相對較低的成功機率，因為導致項採用保留編碼之錯誤的機率可能相對較低（例如，上面給出的實例中的1/8）。然而，由於實體定址表結構的項可能極其小（例如，4個位元），因此由於典型處理系統的性質，每當載入一個項時，可能會同時載入若干項。例如，系統每次可能至少載入64個位元的記憶體，因此一次載入16個項。在此等情形下，經載入項中之任一者的錯誤可能更通常地指示實體定址表結構中的錯誤，並因此可能指示對應項可能係不可信發（即使對應項不具有保留編碼）。因此，當判定是否信任對應項時，可檢查整個經載入部分的保留編碼。Using a single entry to identify a random error can have a relatively low probability of success because the probability of an error resulting in an entry using a reserved encoding can be relatively low (e.g., 1/8 in the example given above). However, since the entries of the physical address table structure can be extremely small (e.g., 4 bits), the nature of typical processing systems means that whenever an entry is loaded, several entries may be loaded simultaneously. For example, the system may load at least 64 bits of memory at a time, thus loading 16 entries at a time. In such cases, an error in any one of the loaded entries may more generally indicate an error in the physical address table structure, and therefore may indicate that the corresponding entry may be untrustworthy (even if the corresponding entry does not have a reserved encoding). Therefore, when determining whether to trust the corresponding entry, the reserved encoding of the entire loaded portion may be checked.
為了進一步增加識別錯誤的機會，當保留編碼的數目較低（例如，1個編碼）時，此可能係特別相關的，當檢查一個保留編碼中的錯誤時，可載入更大部分的記憶體且檢查保留編碼。亦即，即使要從記憶體載入的最小量係64個位元，當存取對應項時，亦可載入更大的量，諸如128個位元或256個位元，即使可載入更少量的資料。接著可檢查儲存在整個經載入部分中之項的保留編碼，以判定是否信任該一個對應項。To further increase the chances of identifying errors, which may be particularly relevant when the number of reserved encodings is low (e.g., 1 encoding), a larger portion of memory can be loaded and the reserved encodings checked when checking for errors in one reserved encoding. That is, even if the minimum amount to be loaded from memory is 64 bits, a larger amount, such as 128 bits or 256 bits, can be loaded when accessing the corresponding item, even though a smaller amount of data can be loaded. The reserved encodings of the items stored in the entire loaded portion can then be checked to determine whether the corresponding item is trustworthy.
因此，在步驟1800，由錯誤偵測電路系統擷取包含對應項之實體定址表結構的一部分，其中該部分可僅包括對應項、包含對應項的快取線、或記憶體的較大部分。在步驟1802，錯誤偵測電路系統可判定該部分中的任何項是否具有保留編碼。Thus, at step 1800, a portion of the physical address table structure containing the corresponding entry is retrieved by the error detection circuitry, where the portion may include only the corresponding entry, a cache line containing the corresponding entry, or a larger portion of memory. At step 1802, the error detection circuitry may determine whether any entry in the portion has a reserved encoding.
若在步驟1802判定任何項具有保留編碼，即使對應項不具有保留編碼，則在步驟1806觸發錯誤處理回應。錯誤處理回應可取決於實施方案而變化，但可涉及產生已偵測到錯誤的指示，且在一些實例中可涉及防止對應項用以判定屬性資訊。若不存在具有保留編碼的項，則在步驟1804，不觸發錯誤處理回應。If, at step 1802, it is determined that any item has a reserved encoding, even if the corresponding item does not, an error handling response is triggered at step 1806. The error handling response may vary depending on the implementation, but may involve generating an indication that an error has been detected and, in some instances, may involve preventing the corresponding item from being used to determine attribute information. If no item has a reserved encoding, then at step 1804, no error handling response is triggered.
類似的技術亦可應用於儲存在屬性儲存位置中的屬性資訊，其中該屬性資訊可被提供有用於錯誤偵測的數個保留編碼。然而，考慮到儲存在屬性儲存位置中不太受關注，屬性儲存位置可替代地指定屬性資訊內的一些錯誤偵測/校正位元（例如，奇偶校驗位元、ECC），該等錯誤偵測/校正位元可用以偵測及可選地校正錯誤。Similar techniques can also be applied to attribute information stored in an attribute storage location, where the attribute information can be provided with a number of reserved codes for error detection. However, considering that storage in an attribute storage location is less important, the attribute storage location can instead specify some error detection/correction bits (e.g., parity bits, ECC) within the attribute information, which can be used to detect and optionally correct errors.
圖19係繪示在支援記憶體標記的系統中處理記憶體存取請求之方法的流程圖。在步驟1900，屬性資訊（如圖16所示判定）用以判定與目標實體位址相關聯的記憶體標記屬性。Figure 19 is a flow chart illustrating a method for processing a memory access request in a system supporting memory tagging. In step 1900, attribute information (determined as shown in Figure 16) is used to determine the memory tag attribute associated with the target physical address.
在步驟1902，記憶體標記屬性用以判定目標實體位址是否位於受記憶體標記保護的記憶體區域內。若是，則在步驟1904，可觸發標籤檢查，以便擷取記憶體標籤且將其與關聯於記憶體存取請求的位址標籤進行比較。In step 1902, the memory tag attribute is used to determine whether the target physical address is located in the memory area protected by the memory tag. If so, in step 1904, a tag check can be triggered to extract the memory tag and compare it with the address tag associated with the memory access request.
在步驟1906，記憶體標記屬性用以判定目標實體位址是否位於指定用以儲存記憶體標籤的記憶體區域內。若是，則在步驟1908控制記憶體存取以防止記憶體標籤的不正確修改。例如，若記憶體存取請求係指定用於修改記憶體標籤之預定類型的記憶體存取（例如，由專用類別之一或多種類型的標籤修改指令觸發的記憶體存取，與更一般類別的載入/儲存指令分開），則可僅允許記憶體存取請求。預定類型的記憶體存取請求可不直接指定位於用於儲存記憶體標籤之區域中的位址，而可指定與儲存記憶體標籤的位址相關聯的另一位址。At step 1906, the memory tag attribute is used to determine whether the target physical address is within a memory region designated for storing memory tags. If so, memory access is controlled at step 1908 to prevent improper modification of memory tags. For example, a memory access request may only be permitted if the memory access request specifies a predetermined type of memory access for modifying memory tags (e.g., a memory access triggered by one or more types of tag modification instructions of a specialized class, separate from more general load/store instructions). A predetermined type of memory access request may not directly specify an address in an area for storing memory tags, but may specify another address associated with the address for storing memory tags.
若目標實體位址不位於受記憶體標記保護或儲存記憶體標籤的區域中，則記憶體標記屬性可能與記憶體存取請求的處理不相關，且記憶體存取請求的處理可基於其他屬性資訊來處理。If the target physical address is not located in an area protected by a memory tag or storing a memory tag, the memory tag attribute may not be relevant to processing of the memory access request, and processing of the memory access request may be processed based on other attribute information.
本文描述之概念可體現於用於製造體現所描述之概念的設備的電腦可讀取碼中。例如，電腦可讀取碼可在半導體設計及製造程序之一或多個階段中使用，其包括電子設計自動化(electronic design automation, EDA)階段，以製造包含體現該等概念之設備的積體電路。上述電腦可讀取碼可另外或替代地促成實現本文描述之概念之設備的定義、模型化、模擬、驗證及/或測試。The concepts described herein may be embodied in computer-readable code for fabricating devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and fabrication process, including the electronic design automation (EDA) stage, to fabricate integrated circuits containing devices embodying the concepts. Such computer-readable code may additionally or alternatively facilitate the definition, modeling, simulation, verification, and/or testing of devices implementing the concepts described herein.
例如，用於製造實現本文描述之概念的設備之電腦可讀取碼可以定義代表該等概念之硬體描述語言(hardware description language, HDL)的碼實施。例如，碼可定義用於定義實現概念的設備之一或多個邏輯電路的暫存器轉移層(register-transfer-level, RTL)抽象概念。碼可定義代表一或多個邏輯電路的HDL，其以Verilog、SystemVerilog、Chisel或VHDL（超高速積體電路硬體描述語言）以及諸如FIRRTL的中間表示實現設備。電腦可讀取碼可使用系統級模型化語言提供實現概念之定義，諸如SystemC及SystemVerilog或可藉由電腦解譯以促成概念的模擬、功能及/或正式驗證及測試之概念的其他行為表示。For example, computer-readable code used to fabricate a device implementing the concepts described herein may define a code implementation of a hardware description language (HDL) representing the concepts. For example, the code may define a register-transfer-level (RTL) abstraction that defines one or more logic circuits of a device implementing the concepts. The code may define an HDL representation of one or more logic circuits that implement the device in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer-readable code may provide a definition of the implementation concept using a system-level modeling language such as SystemC and SystemVerilog or other behavioral representation of the concept that can be interpreted by a computer to facilitate simulation, functional and/or formal verification and testing of the concept.
另外或替代地，電腦可讀取碼可定義實現本文描述之概念的積體電路組件的低階描述，諸如一或多個接線對照表或積體電路布局定義，包括諸如GDSII之表示。積體電路組件之一或多個接線對照表或其他電腦可讀取表示可藉由施加一或多個邏輯合成程序至RTL表示以產生用於製造實現本發明之設備的定義來產生。替代地或額外地，一或多個邏輯合成程序可從電腦可讀取碼產生一位元流，該位元流被載入至一場可程式化閘陣列(field programmable gate array, FPGA)中以組態FPGA以實現所述概念。FPGA可部署用於積體電路中之製造之前的驗證及測試概念的目的，或FPGA可直接部署於產品中。Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component that implements the concepts described herein, such as one or more wiring lookup tables or integrated circuit layout definitions, including representations such as GDSII. One or more wiring lookup tables or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis programs to the RTL representation to generate a definition for fabricating a device that implements the invention. Alternatively or additionally, one or more logic synthesis programs may generate a bit stream from the computer-readable code that is loaded into a field programmable gate array (FPGA) to configure the FPGA to implement the concepts. FPGAs can be deployed for the purpose of validating and testing concepts before manufacturing in integrated circuits, or FPGAs can be deployed directly in products.
電腦可讀取碼可包含用於製造設備之碼表示之混合，例如包括RTL表示、接線對照表表示、或用於半導體設計及製造程序以製造實現本發明之設備的另一電腦可讀取定義之一或多者之混合。替代地或額外地，概念可定義於以下電腦可讀取定義與電腦可讀取碼的組合：電腦可讀取定義待使用於半導體設計及製造程序中以製造設備、電腦可讀取碼定義待由所定義設備一旦經製造後執行的指令。The computer-readable code may include a mixture of code representations used to manufacture a device, including, for example, an RTL representation, a lookup table representation, or another computer-readable definition used in a semiconductor design and manufacturing process to manufacture a device embodying the present invention. Alternatively or additionally, a concept may be defined as a combination of a computer-readable definition to be used in a semiconductor design and manufacturing process to manufacture a device, and computer-readable code defining instructions to be executed by the defined device once it is manufactured.
此類電腦可讀取碼可設置於任何已知暫時性電腦可讀取媒體（諸如，網路上之有線或無線傳輸碼）或非暫時性電腦可讀取媒體（諸如，半導體、磁碟或光碟）中。使用電腦可讀取碼製造的積體電路可包含組件，諸如中央處理單元、圖形處理單元、神經處理單元、數位信號處理器或單獨或共同實現概念的其他組件之一或多者。Such computer-readable code can be placed on any known transient computer-readable medium (e.g., wired or wireless transmission over a network) or non-transitory computer-readable medium (e.g., semiconductors, magnetic disks, or optical disks). An integrated circuit fabricated using the computer-readable code can include components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or one or more of the other components that individually or collectively implement the concepts.
圖20繪示可使用的模擬器實施方案。雖然稍早所述之實施例以用於操作支援所關注技術的特定處理硬體之設備及方法來實施本發明，但亦可能根據本文所述之實施例提供一指令執行環境，其係透過使用電腦程式實施。此類電腦程式常稱為模擬器，因為其等提供硬體架構之基於軟體的實施方案。模擬器電腦程式的種類包括仿真器、虛擬機、模型、及二進制轉譯器（包括動態二進制轉譯器）。一般而言，模擬器實施方案可在可選地運行主機作業系統420、支援模擬器程式410的主機處理器430上運行。在一些配置中，在硬體與所提供的指令執行環境及/或相同的主機處理器上提供的多個相異指令執行環境之間可有多層模擬。歷史上，已需要強大的處理器以提供以合理速度執行的模擬器實施方案，但此種方法在某些情況下可係合理的，諸如當因為相容性或再使用原因而欲運行另一處理器原生的碼時。例如，模擬器實施方案可提供具有不為主機處理器硬體所支援之額外功能性的指令執行環境，或提供一般與不同的硬體架構相關聯的指令執行環境。模擬的綜述係於「Some Efficient Architecture Simulation Techniques」中給出，Robert Bedichek, Winter 1990 USENIX Conference，頁數53至63。FIG20 illustrates an emulator implementation that may be used. Although the embodiments described earlier implement the present invention using apparatus and methods for operating specific processing hardware supporting the technology of interest, it is also possible to provide an instruction execution environment according to the embodiments described herein that is implemented using a computer program. Such computer programs are often referred to as emulators because they provide a software-based implementation of the hardware architecture. Types of emulator computer programs include simulators, virtual machines, models, and binary translators (including dynamic binary translators). Generally speaking, the emulator implementation may be run on a host processor 430 that optionally runs a host operating system 420 and supports the emulator program 410. In some configurations, there may be multiple layers of emulation between the hardware and the provided instruction execution environment and/or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide emulator implementations that execute at reasonable speeds, but this approach may be justified in certain circumstances, such as when it is desirable to run code that is native to another processor for compatibility or reuse reasons. For example, a emulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or provide an instruction execution environment that is generally associated with a different hardware architecture. A general description of simulation is given in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, pages 53-63.
在先前已參照特定硬體架構或特徵來描述實施例之情況下，在一模擬實施例中，可藉由合適的軟體架構或特徵提供等效功能。例如，可在模擬實施例中將特定電路系統實施為電腦程式邏輯。類似地，記憶體硬體（諸如暫存器或快取）可在模擬實施例中實施為軟體資料結構。於先前描述實施例中提及的硬體元件的一或多者存在於主機硬體（例如，主機處理器430）上的配置中，一些模擬實施例可在合適時利用主機硬體。Where embodiments have been previously described with reference to specific hardware architectures or features, equivalent functionality may be provided in a simulated embodiment by appropriate software architectures or features. For example, specific circuitry may be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware (such as registers or caches) may be implemented as software data structures in a simulated embodiment. In configurations where one or more of the hardware components mentioned in previously described embodiments reside on host hardware (e.g., host processor 430), some simulated embodiments may utilize host hardware where appropriate.
模擬器程式410可儲存在電腦可讀取儲存媒體（其可係非暫時性媒體）上，並提供程式介面（指令執行環境）至目標碼400（其可包括應用程式、作業系統、及超管理器），該程式介面與藉由模擬器程式410模型化之硬體架構的介面相同。因此，目標碼400的程式指令可使用模擬器程式410自指令執行環境內執行，使得實際上不具有上文所論述之設備2之硬體特徵的主機電腦430可仿真此等特徵。例如，由於目標碼可藉由在不支援該架構的主機裝置上執行的模擬器內運行而測試，此對於允許在實際支援新版本處理器架構的硬體裝置仍可用之前測試針對該架構開發的目標碼400可係有用的。The emulator program 410 can be stored on a computer-readable storage medium (which can be a non-transitory medium) and provides a programming interface (instruction execution environment) to the object code 400 (which can include applications, an operating system, and a hypervisor). This programming interface is the same as the interface of the hardware architecture modeled by the emulator program 410. Therefore, program instructions of the object code 400 can be executed within the instruction execution environment using the emulator program 410, allowing the host computer 430, which does not actually have the hardware features of the device 2 discussed above, to emulate these features. For example, this may be useful for allowing object code 400 developed for a new version of a processor architecture to be tested before actual hardware devices supporting that architecture are available, since the object code may be tested by running it within an emulator executing on a host device that does not support the architecture.
模擬器碼包括處理程式邏輯412，該處理程式邏輯仿真處理電路系統10的行為，例如，包括解碼目標碼400之指令及將指令映射至由主機硬體430支援之原生指令集中的對應指令序列以執行等效於經解碼指令之功能的指令解碼程式邏輯。處理程式邏輯412亦模擬如上文描述之碼在不同例外等級及域中的處理。暫存器仿真程式邏輯413維持在主機處理器之主機位址空間中的資料結構，該資料結構仿真根據與目標碼400關聯的目標指令集架構定義的架構暫存器狀態。因此，替代將此類架構狀態儲存在硬體暫存器12中，其替代地儲存在主機處理器430的記憶體中，其中暫存器仿真程式邏輯413將目標碼400之指令的暫存器參考映射至對應位址以用於從主機記憶體獲得經模擬架構狀態資料。此架構狀態可包括稍早所述的目前域指示14及目前例外等級指示15。The emulator code includes handler logic 412 that emulates the behavior of processing circuitry 10, including, for example, instruction decoder logic that decodes instructions of target code 400 and maps them to corresponding instruction sequences in the native instruction set supported by host hardware 430 to perform functions equivalent to the decoded instructions. Handler logic 412 also emulates the processing of the code at different exception levels and domains as described above. Register emulator logic 413 maintains data structures in the host address space of the host processor that emulate the architectural register states defined according to the target instruction set architecture associated with target code 400. Therefore, instead of storing such architectural state in hardware registers 12, it is instead stored in memory of the host processor 430, where register emulator logic 413 maps register references in instructions of the target code 400 to corresponding addresses for obtaining emulated architectural state data from host memory. This architectural state may include the current domain indication 14 and the current exception level indication 15 described earlier.
模擬碼包括仿真位址轉譯電路系統16之功能的位址轉譯程式邏輯414。儘管未示出，但模擬碼亦可包含仿真PAS過濾器20之功能的過濾程式邏輯。模擬碼亦包含屬性判定程式邏輯416，該屬性判定程式邏輯使用實體定址表結構及一組屬性儲存位置來判定與由位址轉譯程式邏輯414轉譯的目標實體位址相關聯的屬性資訊。位址轉譯程式邏輯414及過濾程式邏輯中的一者或二者亦充當PAS選擇程式邏輯，用於基於處理程式邏輯412的目前域及使用頁表定義的PAS選擇資訊來選擇與給定記憶體存取請求相關聯的經選擇PAS。因此，位址轉譯程式邏輯414將由目標碼400指定的虛擬位址轉譯成PAS之一者中的經模擬實體位址（從目標碼的觀點，其係指記憶體中的實體位置，但實際上此等經模擬實體位址藉由位址空間映射程式邏輯415映射至主機處理器的（虛擬）位址空間上。屬性資訊可包括如稍早論述的RGID資訊。對於經模擬實例，RGID指示經模擬請求者硬體裝置群組，且RGID由模擬器碼410指派以表示將存在於真實處理設備2中的經模擬硬體裝置，但此等經模擬硬體裝置實際上可能不存在於主機硬體430中。The simulation code includes address translation logic 414 that emulates the functionality of address translation circuitry 16. Although not shown, the simulation code may also include filter logic that emulates the functionality of PAS filter 20. The simulation code also includes attribute determination logic 416 that uses a physical address table structure and a set of attribute storage locations to determine attribute information associated with the target physical address translated by address translation logic 414. One or both of the address translator logic 414 and the filter logic also functions as PAS selector logic for selecting a selected PAS associated with a given memory access request based on the current domain of the handler logic 412 and PAS selection information defined using the page table. Thus, the address translator logic 414 translates the virtual addresses specified by the target code 400 into emulated physical addresses in one of the PASs (from the target code's perspective, these refer to physical locations in memory, but in reality these emulated physical addresses are mapped to the (virtual) address space of the host processor by the address space mapper logic 415. The attribute information may include RGID information as discussed earlier. For the emulated instance, the RGID indicates the emulated requester hardware device group, and the RGID is assigned by the emulator code 410 to represent emulated hardware devices that will exist in the real processing device 2, but these emulated hardware devices may not actually exist in the host hardware 430.
在本申請案中，用語「經組態以...(configured to...)」係用以意指一設備的一元件具有能夠實行該經定義作業的一組態。在此上下文中，「組態(configuration)」意指硬體或軟體之互連的配置或方式。例如，該設備可具有專用硬體，其提供經定義的操作，或者一處理器或其他處理裝置可經程式化以執行該功能。「經組態以(configured to)」並不意味著設備元件需要以任何方式改變以提供所定義的作業。In this application, the term "configured to..." is used to mean that a component of a device has a configuration that enables it to perform the defined operation. In this context, "configuration" refers to the arrangement or manner in which hardware or software is interconnected. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device component needs to be modified in any way to provide the defined operation.
在本申請案中，以片語「中之至少一者(at least one of)」前綴的特徵清單意謂著此等特徵的任何一或多者可個別地或組合地提供。例如，「下列中之至少一者：[A]、[B]、及[C]」涵蓋下列選項中之任一者：單獨A（不具有B或C）、單獨B（不具有A或C）、單獨C（不具有A或B）、A及B的組合（不具有C）、A及C的組合（不具有B）、B及C的組合（不具有A）、或A、B、及C的組合。In this application, a list of features preceded by the phrase "at least one of" means that any one or more of these features may be provided individually or in combination. For example, "at least one of the following: [A], [B], and [C]" encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), the combination of A and B (without C), the combination of A and C (without B), the combination of B and C (without A), or the combination of A, B, and C.
雖然本文已參照附圖詳細地描述本發明的說明性實施例，應瞭解本發明不限於該等精確實施例，且所屬技術領域中具有通常知識者可於其中實行各種變化與修改，而不脫離如隨附申請專利範圍所定義的本發明的範圍。Although illustrative embodiments of the present invention have been described in detail with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.
2:資料處理系統；處理系統；設備；真實處理設備 4:請求者裝置；CPU；請求者；處理器 6:記憶體系統；記憶體；完成者裝置 7:記憶體系統；快取記憶體 8:互連；系統網狀架構 10:處理電路系統 12:暫存器；硬體暫存器；系統暫存器 14:目前域指示；暫存器狀態；目前域；目前域指示符；安全分割管理器；域指示位元 15:目前例外等級；目前例外等級指示 16:位址轉譯電路系統；記憶體管理單元(MMU) 17:屬性判定電路系統 18:轉譯後備緩衝區(TLB) 19:屬性儲存位置 20:PAS過濾器；硬體過濾器；GMPU；PAS過濾 22:顆粒保護資訊快取記憶體；GPI快取記憶體；根域；快取記憶體 24:快取記憶體；安全域；系統網狀架構 26:非安全域；SMMU 28:SMMU；TLB 29:監測碼；監測軟體 30:應用程式碼；應用程式 32:作業系統(OS)碼；作業系統 34:超管理器碼；超管理器 36:受信任應用程式 38:受信任作業系統 40:安全分割管理器；SPM 42:領域；應用程式層級領域；使用者提供碼 44:領域；經封裝應用程式/作業系統領域；使用者提供碼 46:領域管理模組(RMM) 50:1階記憶體管理單元；1階MMU 52:2階記憶體管理單元；2階MMU 54:安全屬性 56:顆粒保護表(GPT) 60:實體別名點(PoPA)；實體位址空間 61:實體位址空間；架構實體位址空間 62:數值範圍；範圍 63:別名實體位址；別名位址 64:系統實體位址空間 65:經去別名位址；系統實體位址空間 70:區域 80:例外等級 82:根域；域 84:安全(S)域；域；安全域；安全PAS；安全世界 86:較低安全域；域；非安全域 88:領域域；域；較高安全域；領域世界 100:步驟 102:步驟 104:步驟 110:表描述符 112:指標 114:區塊或頁描述符PTE；區塊/頁描述符；根區塊/頁描述符PTE 116:區塊或頁描述符PTE；區塊/頁描述符 118:區塊或頁描述符PTE；區塊/頁描述符；非安全區塊/頁描述符 120:輸出位址 122:屬性 124:非安全表指示符；資訊 126:實體位址空間選擇資訊；PAS選擇資訊；PAS選擇位元；資訊 130, 132, 134, 136, 138, 140, 142:步驟 150:區塊 152:守衛標籤 154:記憶體位置；標籤儲存位置；位置 160:位址標籤 162:目標位址 164:經定址位置 200, 202, 204, 206:步驟 250:系統記憶體管理單元(SMMU) 252:裝置 300:系統快取記憶體 400:目標碼 410:模擬器程式；模擬器碼 412:處理程式邏輯 413:暫存器仿真程式邏輯 414:位址轉譯程式邏輯 415:位址空間映射程式邏輯 416:屬性判定程式邏輯 420:主機作業系統 430:主機處理器；主機電腦；主機硬體 1600, 1602, 1604, 1606, 1608:步驟 1700, 1702, 1704, 1706:步驟 1800, 1802, 1804, 1806:步驟 1900, 1902, 1904, 1906, 1908, 1910:步驟 BL1, BL2:啟動碼 EL0, EL1, EL2, EL3:例外等級2: Data processing system; processing system; device; real processing device4: Requester device; CPU; requester; processor6: Memory system; memory; completer device7: Memory system; cache memory8: Interconnect; system network architecture10: Processing circuitry12: Registers; hardware registers; system registers14: Current domain indicator; register state; current domain; current domain indicator; secure partition manager; domain indicator bit15: Current exception level; current exception level indicator16: Address translation circuitry; Memory Management Unit (MMU)17: Attribute determination circuitry18: Translation lookaside buffer (TLB)19: Attribute storage location20: PAS filter; hardware filter; GMPU; PAS filter22: Granular protection information cache; GPI cache; root domain; cache24: cache; secure domain; system mesh architecture26: non-secure domain; SMMU28: SMMU; TLB29: monitoring code; monitoring software30: application code; application32: operating system (OS) code; operating system34: hypervisor code; hypervisor36: trusted application38: trusted operating system40: secure partition manager; SPM42: domain; application-level domain; user-provided code44: Domain; packaged application/operating system domain; user-provided code46: Domain Management Module (RMM)50: Level 1 Memory Management Unit; Level 1 MMU52: Level 2 Memory Management Unit; Level 2 MMU54: Security attributes56: Granular Protection Table (GPT)60: Point of Alias (PoPA); physical address space61: physical address space; architecture physical address space62: Value range; range63: Alias physical address; alias address64: System physical address space65: Dealiased address; system physical address space70: Zone80: Exception level82: Root domain; domain84: Secure (S) domain; domain; secure domain; secure PAS; secure world86: less secure domain; domain; non-secure domain88: domain domain; domain; more secure domain; domain world100: step102: step104: step110: table descriptor112: pointer114: block or page descriptor PTE; block/page descriptor; root block/page descriptor PTE116: block or page descriptor PTE; block/page descriptor118: block or page descriptor PTE; block/page descriptor; non-secure block/page descriptor120: output address122: attribute124: non-secure table pointer; information126: Physical address space selection information; PAS selection information; PAS selection bits; information130, 132, 134, 136, 138, 140, 142: Steps150: Block152: Guard tag154: Memory location; Tag storage location; Location160: Address tag162: Target address164: Addressed location200, 202, 204, 206: Steps250: System Memory Management Unit (SMMU)252: Device300: System cache400: Object code410: Emulator program; Emulator code412: Processor Logic413: Register Emulation Logic414: Address Translation Logic415: Address Space Mapper Logic416: Attribute Determination Logic420: Host Operating System430: Host Processor; Host Computer; Host Hardware1600, 1602, 1604, 1606, 1608: Steps1700, 1702, 1704, 1706: Steps1800, 1802, 1804, 1806: Steps1900, 1902, 1904, 1906, 1908, 1910: StepsBL1, BL2: Activation CodeEL0, EL1, EL2, EL3: Exception Levels
本技術的進一步態樣、特徵、及優點將由於結合附圖閱讀的以下實例描述而顯而易見，在該等附圖中： ［圖1］繪示資料處理設備的實例； ［圖2］繪示使用一組屬性儲存位置來判定與目標實體位址相關聯的屬性資訊； ［圖3］繪示資料處理設備的更詳細實例； ［圖4］繪示包含系統記憶體管理單元的實例資料處理設備； ［圖5］繪示設備的處理電路系統可於其中操作的數個域； ［圖6］繪示支援顆粒保護查找之處理系統的實例； ［圖7］示意地繪示將數個實體位址空間別名至識別記憶體系統中之位置的系統實體位址空間上； ［圖8］繪示分割有效硬體實體位址空間使得不同架構實體位址空間具有對系統實體位址空間之各別部分之存取的實例； ［圖9］係繪示判定處理電路系統之目前操作域之方法的流程圖； ［圖10］顯示用於將虛擬位址轉譯成實體位址之頁表項之頁表項格式的實例； ［圖11］係顯示選擇待由給定記憶體存取請求存取之實體位址空間之方法的流程圖； ［圖12］繪示位址轉譯及顆粒保護資訊過濾的數個階段； ［圖13］繪示基於顆粒保護資訊執行顆粒保護檢查的方法； ［圖14］繪示位址轉譯表及實體定址表結構的數個階段； ［圖15］顯示標籤檢查的實例，該標籤檢查包含檢查位址標籤是否匹配守衛標籤； ［圖16］係繪示判定屬性資訊之方法的流程圖； ［圖17］係繪示處理記憶體存取請求之方法的流程圖； ［圖18］係繪示偵測實體定址表結構中之錯誤之方法的流程圖； ［圖19］係繪示在支援記憶體標記的系統中處理記憶體存取請求之方法的流程圖； ［圖20］繪示模擬器實例。Further aspects, features, and advantages of the present technology will become apparent from the following example descriptions when read in conjunction with the accompanying drawings, in which: [Figure 1] illustrates an example of a data processing device;[Figure 2] illustrates the use of a set of attribute storage locations to determine attribute information associated with a target physical address;[Figure 3] illustrates a more detailed example of a data processing device;[Figure 4] illustrates an example data processing device including a system memory management unit;[Figure 5] illustrates several domains in which the processing circuitry of the device can operate;[Figure 6] illustrates an example of a processing system that supports granular protection lookup;[Figure 7] schematically illustrates aliasing multiple physical address spaces to a system physical address space that identifies locations in a memory system;[Figure 8] illustrates an example of partitioning the effective hardware physical address space so that different architecture physical address spaces have access to separate portions of the system physical address space;[Figure 9] is a flow chart illustrating a method for determining the current operating domain of a processing circuit system;[Figure 10] illustrates an example of a page table entry format for a page table entry used to translate a virtual address into a physical address;[Figure 11] is a flow chart illustrating a method for selecting a physical address space to be accessed by a given memory access request;[Figure 12] illustrates several stages of address translation and granular protection information filtering;[Figure 13] illustrates a method for performing a granular protection check based on granular protection information;[Figure 14] illustrates several stages of the address translation table and physical address table structures;[Figure 15] shows an example of a tag check, which includes checking whether an address tag matches a guard tag;[Figure 16] illustrates a flow chart of a method for determining attribute information;[Figure 17] illustrates a flow chart of a method for processing a memory access request;[Figure 18] illustrates a flow chart of a method for detecting errors in a physical address table structure;[Figure 19] illustrates a flow chart of a method for processing a memory access request in a system that supports memory tagging;[Figure 20] illustrates an example of a simulator.
6:記憶體系統；記憶體；完成者裝置6: Memory system; memory; completer device
7:記憶體系統；快取記憶體7: Memory system; cache memory
10:處理電路系統10: Processing circuit system
16:位址轉譯電路系統；記憶體管理單元(MMU)16: Address translation circuit system; memory management unit (MMU)
17:屬性判定電路系統17: Attribute determination circuit system
18:轉譯後備緩衝區(TLB)18: Translation Lookaside Buffer (TLB)
19:屬性儲存位置19: Attribute storage location
| Application Number | Priority Date | Filing Date | Title |
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| GB2401236.1 | 2024-01-31 |
| Publication Number | Publication Date |
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| TW202533061Atrue TW202533061A (en) | 2025-08-16 |
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