本揭露是有關於一種半導體晶片的製造方法，且特別是有關於一種可在半導體晶片轉移後直接進行檢測的半導體晶片的製造方法。The present disclosure relates to a method for manufacturing a semiconductor chip, and more particularly to a method for manufacturing a semiconductor chip that can be directly tested after the semiconductor chip is transferred.
電子裝置或拼接電子裝置已廣泛地應用於通訊、顯示、車用或航空等不同領域中。隨電子裝置蓬勃發展，電子裝置朝向輕薄化開發，因此對於電子裝置的可靠度或品質要求越高。Electronic devices, or spliced electronic devices, are widely used in various fields such as communications, displays, automotive, and aviation. With the rapid development of electronic devices, electronic devices are becoming thinner and lighter, which leads to higher requirements for reliability and quality.
本揭露提供一種半導體晶片的製造方法，其可在半導體晶片轉移後直接進行檢測，以提高半導體晶片的轉移良率。The present disclosure provides a method for manufacturing a semiconductor chip, which can directly perform inspection after the semiconductor chip is transferred to improve the transfer yield of the semiconductor chip.
本揭露的半導體晶片的製造方法包括以下步驟：提供第一載板；將半導體晶粒轉移至第一載板上，其中半導體晶粒具有彼此相對的表面與另一表面；形成填充層於半導體晶粒的側表面上；形成反射層於半導體晶粒以及側表面上，其中，反射層包括第一部分與第二部分，第一部分設置於半導體晶粒的表面上，第二部分設置於填充層上；以及形成透明導電層於半導體晶粒的另一表面上。The disclosed method for manufacturing a semiconductor chip includes the following steps: providing a first carrier; transferring a semiconductor die onto the first carrier, wherein the semiconductor die has a surface and another surface facing each other; forming a filler layer on the side surface of the semiconductor die; forming a reflective layer on the semiconductor die and the side surface, wherein the reflective layer includes a first portion and a second portion, the first portion being disposed on the surface of the semiconductor die and the second portion being disposed on the filler layer; and forming a transparent conductive layer on the other surface of the semiconductor die.
為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.
通過參考以下的詳細描述並同時結合附圖可以理解本揭露，須注意的是，為了使讀者能容易瞭解及為了圖式的簡潔，本揭露中的多張圖式只繪出電子裝置的一部分，且圖式中的特定元件並非依照實際比例繪圖。此外，圖中各元件的數量及尺寸僅作為示意，並非用來限制本揭露的範圍。The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of simplicity, many of the drawings in this disclosure depict only a portion of an electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and size of components in the drawings are for illustration only and are not intended to limit the scope of this disclosure.
在下文說明書與申請專利範圍中，「含有」與「包括」等詞為開放式詞語，因此其應被解釋為「含有但不限定為…」之意。In the following description and patent application, words such as "including" and "comprising" are open-ended words and should be interpreted as meaning "including but not limited to..."
應了解到，當元件或膜層被稱為在另一個元件或膜層「上」或「連接到」另一個元件或膜層時，它可以直接在此另一元件或膜層上或直接連接到此另一元件或層，或者兩者之間存在有插入的元件或膜層(非直接情況)。相反地，當元件被稱為「直接」在另一個元件或膜層「上」或「直接連接到」另一個元件或膜層時，兩者之間不存在有插入的元件或膜層。It should be understood that when an element or film layer is referred to as being “on” or “connected to” another element or film layer, it can be directly on or directly connected to the other element or layer, or an intervening element or film layer may be present therebetween (indirectly). Conversely, when an element is referred to as being “directly on” or “directly connected to” another element or film layer, there are no intervening elements or films present therebetween.
雖然術語「第一」、「第二」、「第三」…可用以描述多種組成元件，但組成元件並不以此術語為限。此術語僅用於區別說明書內單一組成元件與其他組成元件。申請專利範圍中可不使用相同術語，而依照申請專利範圍中元件宣告的順序以第一、第二、第三…取代。因此，在下文說明書中，第一組成元件在申請專利範圍中可能為第二組成元件。While the terms "first," "second," "third," etc. can be used to describe various components, they are not limited to these components. These terms are used solely to distinguish a single component from other components within the specification. The patent application may not use the same terms, but may be replaced with "first," "second," "third," etc., in the order in which the components are declared in the patent application. Thus, in the following description, the first component may be the second component within the patent application.
於文中，「約」、「大約」、「實質上」、「大致上」之用語通常表示在一給定值或範圍的10%內、或5%內、或3%之內、或2%之內、或1%之內、或0.5%之內。在此給定的數量為大約的數量，亦即在沒有特定說明「約」、「大約」、「實質上」、「大致上」的情況下，仍可隱含「約」、「大約」、「實質上」、「大致上」之含義。As used herein, the terms "about," "approximately," "substantially," and "generally" generally mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The quantities given herein are approximate quantities, meaning that even without the specific wording "about," "approximately," "substantially," or "generally," the meaning of "about," "approximately," "substantially," or "generally" may be implied.
在本揭露一些實施例中，關於接合、連接之用語例如「連接」、「互連」等，除非特別定義，否則可指兩個結構係直接接觸，或者亦可指兩個結構並非直接接觸，其中有其他結構設於此兩個結構之間。且此關於接合、連接之用語亦可包括兩個結構都可移動，或者兩個結構都固定之情況。此外，用語「耦接」包括任何直接及間接的電性連接手段。In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, unless otherwise specified, may refer to two structures being in direct contact, or to two structures not being in direct contact, with another structure positioned between them. Furthermore, these terms may include situations where both structures are movable or both structures are fixed. Furthermore, the term "coupled" encompasses any direct and indirect electrical connection means.
在本揭露一些實施例中，可使用光學顯微鏡(optical microscopy，OM)、掃描式電子顯微鏡(scanning electron microscope，SEM)、薄膜厚度輪廓測量儀(α-step)、橢圓測厚儀、或其他合適的方式量測各元件的面積、寬度、厚度或高度、或元件之間的距離或間距。詳細而言，根據一些實施例，可使用掃描式電子顯微鏡取得包括欲量測的元件的剖面結構影像，並量測各元件的面積、寬度、厚度或高度、或元件之間的距離或間距。In some embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step film thickness profiler, an elliptical thickness gauge, or other suitable methods can be used to measure the area, width, thickness, or height of each device, or the distance or spacing between devices. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structural image including the device to be measured, and the area, width, thickness, or height of each device, or the distance or spacing between devices, can be measured.
在本揭露中，半導體晶片可應用於電子裝置中。電子裝置可包括顯示裝置、發光裝置、背光裝置、虛擬實境裝置、擴增實境（augmented reality，AR）裝置、天線裝置、感測裝置、拼接裝置或其任意組合，但不以此為限。顯示裝置可依據需求而為非自發光型顯示器或自發光型顯示器，並可依據需求而為彩色顯示器或單色顯示器。天線裝置可為液晶型態的天線裝置或非液晶型態的天線裝置，感測裝置可為感測電容、光線、熱能或超聲波的感測裝置，拼接裝置可為顯示器拼接裝置或天線拼接裝置，但不以此為限。電子裝置中的電子元件可包括被動元件與主動元件，例如電容、電阻、電感、二極體、電晶體等。二極體可包括發光二極體(light emitting diode, LED)或光電二極體(photodiode)。發光二極體可例如包括有機發光二極體(organic light emitting diode，OLED)、次毫米發光二極體(mini LED)、微發光二極體(micro LED)或量子點發光二極體(quantum dot LED)，但不以此為限。電晶體可例如包括頂柵型(top gate)薄膜電晶體、底柵型(bottom gate)薄膜電晶體或雙柵(dual gate)薄膜電晶體，但不以此為限。電子裝置也可依據需求而包括螢光(fluorescence)材料、磷光(phosphor)材料、量子點(quantum dot, QD)材料或其他合適的材料，但不以此為限。電子裝置可具有驅動系統、控制系統、光源系統、…等周邊系統以支援顯示裝置、天線裝置、穿戴式裝置（例如包括擴增實境或虛擬實境裝置）、車載裝置（例如包括汽車擋風玻璃）或拼接裝置。需注意的是，電子裝置可為前述之任意排列組合，但不以此為限。下文將以電子裝置中的半導體晶片來說明本揭露內容，但本揭露不以此為限。In the present disclosure, semiconductor chips can be applied to electronic devices. The electronic devices may include, but are not limited to, display devices, light-emitting devices, backlight devices, virtual reality devices, augmented reality (AR) devices, antenna devices, sensing devices, splicing devices, or any combination thereof. The display device may be a non-luminous display or a self-luminous display as required, and may be a color display or a monochrome display as required. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound. The splicing device may be a display splicing device or an antenna splicing device, but is not limited thereto. Electronic components in electronic devices may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light emitting diodes (LEDs) or photodiodes. Light emitting diodes may include, but are not limited to, organic light emitting diodes (OLEDs), sub-millimeter light emitting diodes (mini LEDs), micro LEDs, or quantum dot LEDs. Transistors may include, but are not limited to, top gate thin film transistors, bottom gate thin film transistors, or dual gate thin film transistors. Electronic devices may also include, but are not limited to, fluorescent materials, phosphor materials, quantum dot (QD) materials, or other suitable materials as needed. Electronic devices may include peripheral systems such as drive systems, control systems, light source systems, etc. to support display devices, antenna devices, wearable devices (such as augmented reality or virtual reality devices), vehicle-mounted devices (such as car windshields), or splicing devices. It should be noted that the electronic device may be any combination of the aforementioned arrangements, but is not limited thereto. The following description of this disclosure will use semiconductor chips in electronic devices as an example, but is not limited thereto.
須知悉的是，以下所舉實施例可以在不脫離本揭露的精神下，可將數個不同實施例中的特徵進行替換、重組、混合以完成其他實施例。各實施例間特徵只要不違背發明精神或相衝突，均可任意混合搭配使用。It should be noted that the following embodiments may be implemented by replacing, recombining, or combining features from various embodiments to create other embodiments without departing from the spirit of the present disclosure. Features from various embodiments may be mixed and matched as needed, as long as they do not violate the spirit of the invention or conflict with it.
現將詳細地參考本揭露的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
圖1A至圖1D為本揭露第一實施例的半導體晶片的製造方法的剖面示意圖。其中，本實施例的半導體晶片100的製造方法可包括以下步驟：1A to 1D are cross-sectional schematic diagrams of a method for manufacturing a semiconductor chip according to a first embodiment of the present disclosure. The method for manufacturing a semiconductor chip 100 according to this embodiment may include the following steps:
首先，請參照圖1A，提供第一載板S1；接著，形成犧牲層RL於第一載板S1上；接著，將半導體晶粒110轉移至第一載板S1上。First, referring to FIG. 1A , a first carrier S1 is provided; then, a sacrificial layer RL is formed on the first carrier S1; and then, a semiconductor die 110 is transferred to the first carrier S1.
具體來說，在本實施例中，第一載板S1可以包括硬性基板、軟性基板或前述的組合，舉例來說，第一載板S1的材料可包括玻璃、石英、藍寶石(sapphire)、陶瓷、聚碳酸酯(polycarbonate，PC)、聚醯亞胺(polyimide，PI)、聚對苯二甲酸乙二酯(polyethylene terephthalate，PET)、樹脂(epoxy)、其它合適的載板材料或前述的組合，但不限於此。Specifically, in this embodiment, the first carrier S1 may include a rigid substrate, a flexible substrate, or a combination thereof. For example, the material of the first carrier S1 may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), epoxy, other suitable carrier materials, or a combination thereof, but is not limited thereto.
犧牲層RL設置於半導體晶粒110與第一載板S1之間，犧牲層RL可與第一載板S1一起在後續的步驟中被移除。在本實施例中，犧牲層RL的材料可包括在受熱時或被紫外光照射時會失去黏著特性的黏著材料、或是氮化矽或氧化矽等容易移除的材料，但不限於此。The sacrificial layer RL is disposed between the semiconductor die 110 and the first carrier S1. The sacrificial layer RL and the first carrier S1 can be removed in a subsequent step. In this embodiment, the sacrificial layer RL may be made of an adhesive material that loses its adhesive properties when exposed to heat or ultraviolet light, or an easily removable material such as silicon nitride or silicon oxide, but is not limited thereto.
半導體晶粒110可以為垂直式的半導體晶粒(vertical type chip)。在方向Z(例如是第一載板S1的法線方向)上，半導體晶粒110由下而上依序包括第一型態半導體層111、主動層112以及第二型態半導體層113。第一型態半導體層111比第二型態半導體層113更鄰近第一載板S1，且主動層112設置於第一型態半導體層111與第二型態半導體層113之間。半導體晶粒110具有表面114、另一表面115以及側表面116。表面114與另一表面115彼此相對，表面114比另一表面115更靠近第一載板S1，且側表面116連接表面114與另一表面115。在本實施例中，半導體晶粒110可以為發光元件(例如有機發光二極體、次毫米發光二極體、微發光二極體或量子點發光二極體，但不限於此)，但不限於此。在本實施例中，第一型態半導體層111可以為P型半導體層，且第二型態半導體層113可以為N型半導體層，但不限於此。在一些實施例中，第一型態半導體層也可以為N型半導體層，且第二型態半導體層也可以為P型半導體層。在本實施例中，主動層112可以為發光層，但不限於此。Semiconductor die 110 can be a vertical semiconductor chip. In direction Z (e.g., the normal direction to first carrier S1), semiconductor die 110 comprises, from bottom to top, a first-type semiconductor layer 111, an active layer 112, and a second-type semiconductor layer 113. The first-type semiconductor layer 111 is closer to first carrier S1 than the second-type semiconductor layer 113, and the active layer 112 is disposed between the first-type semiconductor layer 111 and the second-type semiconductor layer 113. Semiconductor die 110 has a surface 114, another surface 115, and a side surface 116. Surface 114 and another surface 115 are opposite to each other, with surface 114 being closer to the first carrier S1 than other surface 115. Side surface 116 connects surface 114 and other surface 115. In this embodiment, semiconductor die 110 may be a light-emitting device (e.g., an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro-light-emitting diode, or a quantum dot light-emitting diode), but is not limited thereto. In this embodiment, first-type semiconductor layer 111 may be a P-type semiconductor layer, and second-type semiconductor layer 113 may be an N-type semiconductor layer, but is not limited thereto. In some embodiments, the first-type semiconductor layer may also be an N-type semiconductor layer, and the second-type semiconductor layer may also be a P-type semiconductor layer. In this embodiment, the active layer 112 may be a light-emitting layer, but is not limited thereto.
然後，請參照圖1B，形成負型光阻PR1於犧牲層RL上；接著，形成填充層120於半導體晶粒110的側表面116上以及負型光阻PR1暴露出的犧牲層RL上；接著，移除負型光阻PR1。1B , a negative photoresist PR1 is formed on the sacrificial layer RL. Then, a filling layer 120 is formed on the side surface 116 of the semiconductor die 110 and on the sacrificial layer RL exposed by the negative photoresist PR1. Then, the negative photoresist PR1 is removed.
具體來說，在形成填充層120之前，負型光阻PR1可暴露出半導體晶粒110以及部分的犧牲層RL，且負型光阻PR1與半導體晶粒110之間具有間隙G。負型光阻PR1的形狀可以為倒梯型。在本實施例中，負型光阻PR1的材料可包括壓克力系(Acrylic)、環氧烷系(Epoxy)、矽氧烷(Siloxane)、二氧化矽(Silica)，但不限於此。Specifically, before forming the filler layer 120, the negative photoresist PR1 may expose the semiconductor die 110 and a portion of the sacrificial layer RL, with a gap G being formed between the negative photoresist PR1 and the semiconductor die 110. The negative photoresist PR1 may have an inverted trapezoidal shape. In this embodiment, the material of the negative photoresist PR1 may include, but is not limited to, acrylic, epoxy, siloxane, or silica.
填充層120可圍繞並接觸半導體晶粒110的側表面116。填充層120可包括第一表面121、第二表面122以及側表面123。第一表面121相對於第二表面122，且第一表面121比第二表面122更靠近第一載板S1。側表面123位於第一表面121與第二表面122之間，且側表面123連接第一表面121與第二表面122。在本實施例中，第一表面121與側表面123的夾角θ1具有角度(taper angle)。夾角θ1的角度可以為10度至80度，或30度至70度，以用於集中半導體晶粒110的出光、減少半導體晶粒110的出光角度或提高半導體晶粒110的出光效率，但不限於此。在本實施例中，填充層120的材料可包括壓克力系(Acrylic)、環氧烷系(Epoxy)、矽氧烷(Siloxane)、二氧化矽(Silica)、其他透明的填充材料或前述的組合，但不限於此。The filling layer 120 may surround and contact the side surface 116 of the semiconductor die 110. The filling layer 120 may include a first surface 121, a second surface 122, and a side surface 123. The first surface 121 is opposite to the second surface 122 and is closer to the first carrier S1 than the second surface 122. The side surface 123 is located between the first surface 121 and the second surface 122 and connects the first surface 121 and the second surface 122. In this embodiment, the angle θ1 between the first surface 121 and the side surface 123 is a taper angle. The angle θ1 can be between 10 and 80 degrees, or between 30 and 70 degrees, to concentrate light emitted from the semiconductor die 110, reduce the light emission angle of the semiconductor die 110, or improve the light extraction efficiency of the semiconductor die 110, but is not limited thereto. In this embodiment, the material of the filler layer 120 can include, but is not limited to, acrylic, epoxy, siloxane, silica, other transparent filler materials, or combinations thereof.
然後，請參照圖1C，形成反射層130於半導體晶粒110以及填充層120的側表面123上；接著，形成絕緣層140於反射層130上；接著，形成電極層150於反射層130上。Then, referring to FIG. 1C , a reflective layer 130 is formed on the semiconductor die 110 and the side surface 123 of the filling layer 120 ; then, an insulating layer 140 is formed on the reflective layer 130 ; then, an electrode layer 150 is formed on the reflective layer 130 .
具體來說，反射層130包括第一部分131與第二部分132。第一部分131設置於半導體晶粒110的另一表面115上。第一部分131可接觸並電性連接至半導體晶粒110的第二型態半導體層113。第二部分132設置於填充層120上。第二部分132設置於填充層120的側表面123與第二表面122上。第二部分132與第一部分131彼此分離。在本實施例中，反射層130的材料可包括具有高反射特性的材料，以用於集中半導體晶粒110的出光、減少半導體晶粒110的出光角度或提高半導體晶粒110的出光效率。Specifically, the reflective layer 130 includes a first portion 131 and a second portion 132. The first portion 131 is disposed on the other surface 115 of the semiconductor die 110. The first portion 131 can contact and electrically connect to the second type semiconductor layer 113 of the semiconductor die 110. The second portion 132 is disposed on the filling layer 120. The second portion 132 is disposed on the side surface 123 and the second surface 122 of the filling layer 120. The second portion 132 is separated from the first portion 131. In this embodiment, the material of the reflective layer 130 may include a material with high reflective properties to concentrate light emitted from the semiconductor die 110, reduce the light emission angle of the semiconductor die 110, or improve the light extraction efficiency of the semiconductor die 110.
絕緣層140圍繞反射層130，且絕緣層140可分隔反射層130的第一部分131與第二部分132。絕緣層140具有開口141與開口142。開口141可暴露出部分的第一部分131，且開口142可暴露出部分的第二部分132。在本實施例中，絕緣層140的材料可包括壓克力系、環氧烷系、矽氧烷、二氧化矽、氮化矽、氮氧化矽、其他合適的絕緣材料或前述的組合，但不限於此。The insulating layer 140 surrounds the reflective layer 130 and separates the first portion 131 from the second portion 132 of the reflective layer 130. The insulating layer 140 has an opening 141 and an opening 142. The opening 141 exposes a portion of the first portion 131, and the opening 142 exposes a portion of the second portion 132. In this embodiment, the insulating layer 140 may be made of, but is not limited to, acrylic, epoxy, silicone, silicon dioxide, silicon nitride, silicon oxynitride, other suitable insulating materials, or combinations thereof.
電極層150包括第一電極151與第二電極152。第一電極151與第二電極152彼此分離。第一電極151設置於絕緣層140上以及絕緣層140的開口141內，第一電極151可連接至第一部分131。第二電極152設置於絕緣層140上以及絕緣層140的開口142內，第二電極152可連接至第二部分132。在本實施例中，電極層150的材料可包括金、錫、銅、其他合適的電極材料或前述的組合，但不限於此。在本實施例中，第一電極151可以為N型電極，且第二電極152可以為P型電極，但不限於此。在一些實施例中，第一電極也可以為P型電極，且第二電極也可以為N型電極。其中，N型電極意指為與N型半導體層電性連接的電極，且P型電極意指為與P型半導體層電性連接的電極。The electrode layer 150 includes a first electrode 151 and a second electrode 152. The first electrode 151 and the second electrode 152 are separated from each other. The first electrode 151 is disposed on the insulating layer 140 and within the opening 141 of the insulating layer 140. The first electrode 151 can be connected to the first portion 131. The second electrode 152 is disposed on the insulating layer 140 and within the opening 142 of the insulating layer 140. The second electrode 152 can be connected to the second portion 132. In this embodiment, the material of the electrode layer 150 may include, but is not limited to, gold, tin, copper, other suitable electrode materials, or combinations thereof. In this embodiment, the first electrode 151 may be an N-type electrode, and the second electrode 152 may be a P-type electrode, but the present invention is not limited thereto. In some embodiments, the first electrode may also be a P-type electrode, and the second electrode may also be an N-type electrode. An N-type electrode refers to an electrode electrically connected to an N-type semiconductor layer, and a P-type electrode refers to an electrode electrically connected to a P-type semiconductor layer.
然後，請參照圖1D，將第二載板S2貼合至電極層150；接著，上下翻轉，移除第一載板S1，以將半導體晶粒110從第一載板S1轉移至第二載板S2上；接著，形成透明導電層160於半導體晶粒110的表面114上。Then, referring to FIG. 1D , the second carrier S2 is bonded to the electrode layer 150 . Next, the first carrier S1 is flipped upside down and removed to transfer the semiconductor die 110 from the first carrier S1 to the second carrier S2 . Next, a transparent conductive layer 160 is formed on the surface 114 of the semiconductor die 110 .
具體來說，第二載板S2包括基底S21與電路層S22。電路層S22設置於基底S21與電極層150之間。電路層S22可包括金屬走線(未繪示)，且電路層S22可用於驅動半導體晶粒110。在本實施例中，基底S21可以包括硬性基板、軟性基板或前述的組合。舉例來說，基底S21的材料可包括玻璃、石英、藍寶石、陶瓷、聚碳酸酯、聚醯亞胺、聚對苯二甲酸乙二酯、其他合適的基板材料、或前述的組合，但不限於此。Specifically, the second carrier S2 includes a substrate S21 and a circuit layer S22. The circuit layer S22 is disposed between the substrate S21 and the electrode layer 150. The circuit layer S22 may include metal traces (not shown) and may be used to drive the semiconductor die 110. In this embodiment, the substrate S21 may include a rigid substrate, a flexible substrate, or a combination thereof. For example, the material of the substrate S21 may include, but is not limited to, glass, quartz, sapphire, ceramic, polycarbonate, polyimide, polyethylene terephthalate, other suitable substrate materials, or a combination thereof.
在本實施例中，例如是透過施加雷射於犧牲層RL的方式，使犧牲層RL可與半導體晶粒110分離，以移除犧牲層RL與第一載板S1。In this embodiment, for example, laser is applied to the sacrificial layer RL so that the sacrificial layer RL can be separated from the semiconductor die 110, thereby removing the sacrificial layer RL and the first carrier S1.
透明導電層160設置於半導體晶粒110的表面114上以及填充層120的第一表面121上。透明導電層160可連接反射層130的第二部分132，且透明導電層160可接觸並電性連接至半導體晶粒110的第一型態半導體層111。藉此，使得半導體晶粒110的第一型態半導體層111可透過透明導電層160與第二部分132而電性連接至第二電極152。在本實施例中，透明導電層160的材料可包括透明導電氧化物(transparent conductive oxides，TCO)、石墨烯或金屬，但不限於此。透明導電氧化物的材料可包括氧化銦錫(indium tin Oxide，ITO)、氧化銦鋅(indium zinc oxide，IZO)或氧化銦鎵(indium gallium oxide，IGO)或前述的組合，但不限於此。金屬可包括薄金屬或金屬網格，例如，可形成很薄的金屬層(例如，鎂層或銀層)，或者，可通過網印或其他圖案化製程形成具有透光開口的金屬網格層。A transparent conductive layer 160 is disposed on the surface 114 of the semiconductor die 110 and on the first surface 121 of the filling layer 120. The transparent conductive layer 160 can be connected to the second portion 132 of the reflective layer 130 and can contact and electrically connect to the first-type semiconductor layer 111 of the semiconductor die 110. Thus, the first-type semiconductor layer 111 of the semiconductor die 110 can be electrically connected to the second electrode 152 through the transparent conductive layer 160 and the second portion 132. In this embodiment, the material of the transparent conductive layer 160 may include, but is not limited to, transparent conductive oxides (TCO), graphene, or metal. The transparent conductive oxide material may include, but is not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), or combinations thereof. The metal may include a thin metal or a metal grid. For example, a very thin metal layer (e.g., a magnesium layer or a silver layer) may be formed, or a metal grid layer with light-transmitting openings may be formed by screen printing or other patterning processes.
在本實施例中，形成透明導電層160的步驟可以是在形成反射層130的步驟之後，但不限於此。在一些實施例中，形成透明導電層160的步驟也可以是在形成反射層130的步驟之前。In this embodiment, the step of forming the transparent conductive layer 160 may be after the step of forming the reflective layer 130, but is not limited thereto. In some embodiments, the step of forming the transparent conductive layer 160 may also be before the step of forming the reflective layer 130.
至此，已大致上製造完成本實施例的半導體晶片100。At this point, the semiconductor chip 100 of this embodiment has been substantially manufactured.
在本實施例中，由於垂直式的半導體晶粒110的第一型態半導體層111與第二型態半導體層113可分別電性連接至第二電極152與第一電極151，且第二電極152與第一電極151可設置在半導體晶片100的同一側，因而使得半導體晶片100在轉移至第二載板S2上之後可以直接進行檢測或進行製程監控，進而可以提高轉移良率。In this embodiment, since the first-type semiconductor layer 111 and the second-type semiconductor layer 113 of the vertical semiconductor die 110 can be electrically connected to the second electrode 152 and the first electrode 151, respectively, and the second electrode 152 and the first electrode 151 can be arranged on the same side of the semiconductor chip 100, the semiconductor chip 100 can be directly tested or process monitored after being transferred to the second carrier S2, thereby improving the transfer yield.
在本實施例中，由於半導體晶片100可以為垂直嵌入式倒裝晶片(vertical embedded flip-chip，VEFC)，因而使得半導體晶片100在轉移至第二載板S2上之後可以直接進行檢測或進行製程監控，進而可以提高轉移良率。In this embodiment, since the semiconductor chip 100 can be a vertical embedded flip-chip (VEFC), the semiconductor chip 100 can be directly tested or subjected to process monitoring after being transferred to the second carrier S2, thereby improving the transfer yield.
以下將列舉其他實施例以作為說明。在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。Other embodiments are listed below for illustration. It should be noted that the following embodiments retain the same component numbers and some of the content as the previous embodiments, with the same reference numbers used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the previous embodiments, and the following embodiments will not be repeated.
圖2A至圖2E為本揭露第二實施例的半導體晶片的製造方法的剖面示意圖。圖2A至圖2E所示的第二實施例與圖1A至圖1D所示的第一實施例類似，因此，相同或相類似的構件得以採用相同的材料或方法來進行，故下文對於兩實施例中相同與相似的描述將不再贅述，且主要針對兩實施例之間的差異處進行說明。Figures 2A to 2E are schematic cross-sectional views of a method for fabricating a semiconductor chip according to a second embodiment of the present disclosure. The second embodiment shown in Figures 2A to 2E is similar to the first embodiment shown in Figures 1A to 1D . Therefore, identical or similar components may be fabricated using the same materials or methods. Therefore, the following description of the similarities and similarities between the two embodiments will not be repeated, and the focus will be on the differences between the two embodiments.
本實施例的半導體晶片100a的製造方法可包括以下步驟：The method for manufacturing the semiconductor chip 100a of this embodiment may include the following steps:
首先，請參照圖2A，提供第一載板S1；接著，形成犧牲層RL於第一載板S1上；接著，將半導體晶粒110a轉移至第一載板S1上。在本實施例中，在方向Z(例如是第一載板S1的法線方向)上，半導體晶粒110a由下而上依序包括第二型態半導體層113a、主動層112以及第一型態半導體層111a。第二型態半導體層113a比第一型態半導體層111a更鄰近第一載板S1，且主動層112設置於第一型態半導體層111a與第二型態半導體層113a之間。First, referring to Figure 2A , a first carrier S1 is provided. Next, a sacrificial layer RL is formed on the first carrier S1. Next, a semiconductor die 110a is transferred onto the first carrier S1. In this embodiment, in the direction Z (e.g., the normal direction to the first carrier S1), the semiconductor die 110a comprises, from bottom to top, a second-type semiconductor layer 113a, an active layer 112, and a first-type semiconductor layer 111a. The second-type semiconductor layer 113a is closer to the first carrier S1 than the first-type semiconductor layer 111a, and the active layer 112 is disposed between the first-type semiconductor layer 111a and the second-type semiconductor layer 113a.
然後，請參照圖2B，形成正型光阻PR2於犧牲層RL上；接著，形成填充層120a於半導體晶粒110a的側表面116上以及正型光阻PR2暴露出的犧牲層RL上；接著，形成透明導電層160於半導體晶粒110a的表面114上以及填充層120a的第一表面121上。在本實施例中，正型光阻PR2的形狀可以為正梯型，且正型光阻PR2的材料可包括壓克力系(Acrylic)、環氧烷系(Epoxy)、矽氧烷(Siloxane)、二氧化矽(Silica)，但不限於此。在本實施例中，填充層120a的第二表面122比第一表面121更靠近第一載板S1。Then, referring to FIG. 2B , a positive photoresist PR2 is formed on the sacrificial layer RL. A filler layer 120a is then formed on the side surface 116 of the semiconductor die 110a and on the sacrificial layer RL exposed by the positive photoresist PR2. A transparent conductive layer 160 is then formed on the surface 114 of the semiconductor die 110a and on the first surface 121 of the filler layer 120a. In this embodiment, the positive photoresist PR2 may have a positive step-shaped shape, and the material of the positive photoresist PR2 may include, but is not limited to, acrylic, epoxy, siloxane, or silica. In this embodiment, the second surface 122 of the filler layer 120a is closer to the first carrier S1 than the first surface 121.
然後，請參照圖2C，貼合第三載板S3於透明導電層160上；接著，上下翻轉，並移除第一載板S1；接著，移除正型光阻PR2。Then, referring to FIG. 2C , a third carrier S3 is attached to the transparent conductive layer 160 . Next, the carrier S1 is turned upside down and removed. Next, the positive photoresist PR2 is removed.
然後，請參照圖2D，形成反射層130於半導體晶粒110a的另一表面115上、填充層120a的側表面123上以及填充層120a的第二表面122上；接著，形成絕緣層140於反射層130上；接著，形成電極層150的第一電極151與第二電極152於反射層130上。Then, referring to FIG. 2D , a reflective layer 130 is formed on the other surface 115 of the semiconductor die 110 a, on the side surface 123 of the filling layer 120 a, and on the second surface 122 of the filling layer 120 a. Then, an insulating layer 140 is formed on the reflective layer 130. Then, a first electrode 151 and a second electrode 152 of the electrode layer 150 are formed on the reflective layer 130.
然後，請參照圖2E，將第二載板S2貼合至電極層150；接著，上下翻轉，移除第三載板S3，以將半導體晶粒110a從第三載板S3轉移至第二載板S2上。Then, referring to FIG. 2E , the second carrier S2 is bonded to the electrode layer 150 . Next, the third carrier S3 is removed by flipping it upside down, so as to transfer the semiconductor die 110 a from the third carrier S3 to the second carrier S2 .
至此，已大致上製造完成本實施例的半導體晶片100a。At this point, the semiconductor chip 100a of this embodiment has been substantially manufactured.
圖3A至圖3C為本揭露第三實施例的半導體晶片的製造方法的剖面示意圖。圖3A至圖3C所示的第三實施例與圖1A至圖1D所示的第一實施例類似，因此，相同或相類似的構件得以採用相同的材料或方法來進行，故下文對於兩實施例中相同與相似的描述將不再贅述，且主要針對兩實施例之間的差異處進行說明。Figures 3A to 3C are schematic cross-sectional views of a method for fabricating a semiconductor chip according to a third embodiment of the present disclosure. The third embodiment shown in Figures 3A to 3C is similar to the first embodiment shown in Figures 1A to 1D . Therefore, identical or similar components may be fabricated using the same materials or methods. Therefore, the following description of the similarities and similarities between the two embodiments will not be repeated, and the focus will be on the differences between the two embodiments.
本實施例的半導體晶片100b的製造方法可包括以下步驟：The method for manufacturing the semiconductor chip 100b of this embodiment may include the following steps:
首先，請參照圖3A，以類似圖1A的步驟，在提供第一載板S1並形成犧牲層RL於第一載板S1上之後，將半導體晶粒110b轉移至第一載板S1上，並將半導體晶粒110b部分嵌入於犧牲層RL中。接著，省略圖1B中使用負型光阻的步驟，將填充層120b設置於半導體晶粒110b的側表面116上後直接進行圖案化製程。First, referring to FIG3A , similar to FIG1A , after providing a first carrier S1 and forming a sacrificial layer RL thereon, a semiconductor die 110 b is transferred onto the first carrier S1 and partially embedded within the sacrificial layer RL. Next, omitting the negative photoresist step in FIG1B , a filler layer 120 b is deposited on the side surface 116 of the semiconductor die 110 b before directly performing a patterning process.
然後，請參照圖3B，形成反射層130於半導體晶粒110b的另一表面115上、填充層120b的側表面123上以及填充層120b的第二表面122上；接著，形成絕緣層140於反射層130上；接著，形成電極層150的第一電極151與第二電極152於反射層130上。Then, referring to FIG. 3B , a reflective layer 130 is formed on the other surface 115 of the semiconductor die 110 b, on the side surface 123 of the filling layer 120 b, and on the second surface 122 of the filling layer 120 b. Next, an insulating layer 140 is formed on the reflective layer 130. Next, a first electrode 151 and a second electrode 152 of an electrode layer 150 are formed on the reflective layer 130.
然後，請參照圖3C，將第二載板S2貼合至電極層150；接著，上下翻轉，移除第一載板S1，以將半導體晶粒110b從第一載板S1轉移至第二載板S2上；接著，在形成透明導電層160b的步驟之前，形成絕緣層170於半導體晶粒110b未形成有填充層120b的側表面116；接著，在形成絕緣層170的步驟之後，形成透明導電層160b於絕緣層170上，並使透明導電層160b連接反射層130的第二部分132。在本實施例中，絕緣層170可以為單層結構或多層結構，且絕緣層170的材料可包括有機材料、無機材料或前述的組合，但不限於此。Then, referring to FIG. 3C , the second carrier S2 is bonded to the electrode layer 150 . The first carrier S1 is then flipped upside down and removed to transfer the semiconductor die 110 b from the first carrier S1 to the second carrier S2 . Prior to forming the transparent conductive layer 160 b , an insulating layer 170 is formed on the side surface 116 of the semiconductor die 110 b where the filler layer 120 b is not formed. Following the step of forming the insulating layer 170 , a transparent conductive layer 160 b is formed on the insulating layer 170 and connected to the second portion 132 of the reflective layer 130 . In this embodiment, the insulating layer 170 may be a single-layer structure or a multi-layer structure, and the material of the insulating layer 170 may include organic materials, inorganic materials, or a combination thereof, but is not limited thereto.
至此，已大致上製造完成本實施例的半導體晶片100b。At this point, the semiconductor chip 100b of this embodiment has been substantially manufactured.
圖4為本揭露第四實施例的半導體晶片的剖面示意圖。請同時參照圖4與圖1C，本實施例的半導體晶片100c與圖1C的半導體晶片100相似，惟二者差異之處在於：在本實施例的半導體晶片100c中，在方向Z(例如是第一載板S1的法線方向)上，第一電極151c可高於第二電極152c。FIG4 is a schematic cross-sectional view of a semiconductor chip according to a fourth embodiment of the present disclosure. Referring to FIG4 and FIG1C , semiconductor chip 100c of this embodiment is similar to semiconductor chip 100 of FIG1C , except that, in semiconductor chip 100c of this embodiment, first electrode 151c may be higher than second electrode 152c in direction Z (e.g., the normal direction of first carrier S1).
具體來說，請參照圖4，在方向Z上，半導體晶粒110的另一表面115高於填充層120的第二表面122，且反射層130的第一部分131高於第二部分132。Specifically, referring to FIG. 4 , in the direction Z, the other surface 115 of the semiconductor die 110 is higher than the second surface 122 of the filling layer 120 , and the first portion 131 of the reflective layer 130 is higher than the second portion 132 .
第一電極151c具有背向半導體晶粒110的表面1511，且第二電極152c具有背向半導體晶粒110的表面1521。在方向Z上，第一電極151c與第二電極152c之間的高度差H可以大於0且小於或等於1微米(μm)(即0 ＜ H ≤ 1 μm)，但不限於此。其中，高度差H例如是第一電極151c的表面1511與第二電極152c的表面1521之間沿著方向Z進行量測到的最小距離。The first electrode 151c has a surface 1511 facing away from the semiconductor die 110, and the second electrode 152c has a surface 1521 facing away from the semiconductor die 110. In the direction Z, a height difference H between the first electrode 151c and the second electrode 152c can be greater than 0 and less than or equal to 1 micron (μm) (i.e., 0 < H ≤ 1 μm), but is not limited thereto. The height difference H is, for example, the minimum distance between the surface 1511 of the first electrode 151c and the surface 1521 of the second electrode 152c measured along the direction Z.
圖5為本揭露第五實施例的半導體晶片的剖面示意圖。請同時參照圖5與圖4，本實施例的半導體晶片100d與圖4的半導體晶片100c相似，惟二者差異之處在於：在本實施例的半導體晶片100d中，透過不同的步驟來分別形成第一電極151d與第二電極152d的方式，使得第一電極151d與第二電極152d在方向Z(例如是第一載板S1的法線方向)上可大致上等高。FIG5 is a schematic cross-sectional view of a semiconductor chip according to a fifth embodiment of the present disclosure. Referring to FIG5 and FIG4 together, the semiconductor chip 100d of this embodiment is similar to the semiconductor chip 100c of FIG4 , except that the first electrode 151d and the second electrode 152d are formed in different steps in the semiconductor chip 100d of this embodiment, so that the first electrode 151d and the second electrode 152d are substantially at the same height in the direction Z (e.g., the normal direction of the first carrier S1).
圖6A至圖6B為本揭露第六實施例的半導體晶片的剖面示意圖。圖6A至圖6B為接續圖1B並取代圖1C至圖1D的步驟。圖6A至圖6B的第六實施例與圖1A至圖1D的實施例中相同或相類似的構件得以採用相同的材料或方法來進行，故下文對於兩實施例中相同與相似的描述將不再贅述，且主要針對兩實施例之間的差異處進行說明。Figures 6A and 6B are schematic cross-sectional views of a semiconductor chip according to a sixth embodiment of the present disclosure. Figures 6A and 6B illustrate the steps following Figure 1B and replacing Figures 1C and 1D. The sixth embodiment of Figures 6A and 6B and the embodiment of Figures 1A and 1D share the same or similar components and are fabricated using the same materials or methods. Therefore, the following description of the similarities and similarities between the two embodiments will not be repeated, and the focus will be on the differences between the two embodiments.
本實施例的半導體晶片100e的製造方法可包括以下步驟：The method for manufacturing the semiconductor chip 100e of this embodiment may include the following steps:
首先，請參照圖6A，在形成圖1B的結構之後，形成反射層130e的第一部分131於半導體晶粒110的另一表面115上，並形成反射層130e的第二部分132e於填充層120的側表面123上；接著，形成絕緣層140e於反射層130e上，其中絕緣層140e具有可暴露出部分的第一部分131開口141；接著，形成電極層150e的第一電極151於絕緣層140e上以及絕緣層140e的開口141內。First, referring to FIG. 6A , after forming the structure of FIG. 1B , a first portion 131 of a reflective layer 130e is formed on the other surface 115 of the semiconductor die 110, and a second portion 132e of the reflective layer 130e is formed on the side surface 123 of the filler layer 120. Next, an insulating layer 140e is formed on the reflective layer 130e, wherein the insulating layer 140e has an opening 141 that exposes a portion of the first portion 131. Next, a first electrode 151 of an electrode layer 150e is formed on the insulating layer 140e and within the opening 141 of the insulating layer 140e.
然後，請參照圖6B，將第二載板S2貼合至電極層150e；接著，上下翻轉，移除第一載板S1，以將半導體晶粒110從第一載板S1轉移至第二載板S2上；接著，形成透明導電層160於半導體晶粒110的表面114上。Then, referring to FIG. 6B , the second carrier S2 is bonded to the electrode layer 150e. Next, the first carrier S1 is flipped upside down and removed to transfer the semiconductor die 110 from the first carrier S1 to the second carrier S2. Next, a transparent conductive layer 160 is formed on the surface 114 of the semiconductor die 110.
至此，已大致上製造完成本實施例的半導體晶片100e。其中，本實施例的半導體晶片100e可視為是垂直嵌入式晶片(vertical embedded chip，VEC)，但不限於此。At this point, the semiconductor chip 100e of this embodiment has been substantially manufactured. The semiconductor chip 100e of this embodiment can be regarded as a vertical embedded chip (VEC), but is not limited thereto.
圖7A至圖7B為本揭露第七實施例的半導體晶片的剖面示意圖。圖7A至圖7B所示的第七實施例與圖6A至圖6B所示的第六實施例類似，因此，相同或相類似的構件得以採用相同的材料或方法來進行，故下文對於兩實施例中相同與相似的描述將不再贅述，且主要針對兩實施例之間的差異處進行說明。Figures 7A and 7B are schematic cross-sectional views of a semiconductor chip according to a seventh embodiment of the present disclosure. The seventh embodiment shown in Figures 7A and 7B is similar to the sixth embodiment shown in Figures 6A and 6B . Therefore, identical or similar components may be fabricated using the same materials or methods. Therefore, the following description of the similarities and similarities between the two embodiments will not be repeated, and the focus will be on the differences between the two embodiments.
本實施例的半導體晶片100f的製造方法可包括以下步驟：The method for manufacturing the semiconductor chip 100f of this embodiment may include the following steps:
首先，請參照圖7A，本實施例的半導體晶粒110f可部分嵌入於犧牲層RL中；接著，以類似圖6A的步驟，形成反射層130f的第一部分131於半導體晶粒110f的另一表面115上，並形成反射層130f的第二部分132f於填充層120的側表面123上；接著，形成絕緣層140f於反射層130f上，其中絕緣層140f具有可暴露出部分的第一部分131開口141；接著，形成電極層150f的第一電極151於絕緣層140f上以及絕緣層140f的開口141內。First, referring to FIG7A , the semiconductor die 110 f of this embodiment may be partially embedded in the sacrificial layer RL. Then, similar to the steps in FIG6A , a first portion 131 of a reflective layer 130 f is formed on the other surface 115 of the semiconductor die 110 f, and a second portion 132 f of the reflective layer 130 f is formed on the side surface 123 of the filler layer 120. Next, an insulating layer 140 f is formed on the reflective layer 130 f, wherein the insulating layer 140 f has an opening 141 that exposes a portion of the first portion 131. Next, a first electrode 151 of an electrode layer 150 f is formed on the insulating layer 140 f and within the opening 141 of the insulating layer 140 f.
然後，請參照圖7B，將第二載板S2貼合至電極層150f；接著，上下翻轉，移除第一載板S1，以將半導體晶粒110f從第一載板S1轉移至第二載板S2上；接著，在形成透明導電層160f的步驟之前，形成絕緣層170於半導體晶粒110f未形成有填充層120的側表面116；接著，在形成絕緣層170的步驟之後，形成透明導電層160f於絕緣層170上，並使透明導電層160f連接反射層130f的第二部分132。在本實施例中，絕緣層170可以為單層結構或多層結構，且絕緣層170的材料可包括有機材料、無機材料或前述的組合，但不限於此。Then, referring to FIG. 7B , the second carrier S2 is bonded to the electrode layer 150 f . Next, the first carrier S1 is flipped upside down and removed to transfer the semiconductor die 110 f from the first carrier S1 to the second carrier S2 . Next, before forming the transparent conductive layer 160 f , an insulating layer 170 is formed on the side surface 116 of the semiconductor die 110 f where the filling layer 120 is not formed. Next, after forming the insulating layer 170 , a transparent conductive layer 160 f is formed on the insulating layer 170 and connected to the second portion 132 of the reflective layer 130 f . In this embodiment, the insulating layer 170 may be a single-layer structure or a multi-layer structure, and the material of the insulating layer 170 may include organic materials, inorganic materials, or a combination thereof, but is not limited thereto.
至此，已大致上製造完成本實施例的半導體晶片100f。At this point, the semiconductor chip 100f of this embodiment has been substantially manufactured.
綜上所述，在本揭露實施例的半導體晶片的製造方法中，由於垂直式的半導體晶粒的第一型態半導體層與第二型態半導體層可分別電性連接至第二電極與第一電極，且第二電極與第一電極可設置在半導體晶片的同一側，因而使得電子裝置中的半導體晶片在轉移至第一電路層上之後可以直接進行檢測或進行製程監控，進而可以提高轉移良率。In summary, in the semiconductor chip manufacturing method of the disclosed embodiment, since the first-type semiconductor layer and the second-type semiconductor layer of the vertical semiconductor die can be electrically connected to the second electrode and the first electrode, respectively, and the second electrode and the first electrode can be arranged on the same side of the semiconductor chip, the semiconductor chip in the electronic device can be directly tested or process monitored after being transferred to the first circuit layer, thereby improving the transfer yield.
雖然本揭露已以實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露的精神和範圍內，當可作些許的更動與潤飾，故本揭露的保護範圍當視後附的申請專利範圍所界定者為準。Although the present disclosure has been disclosed above with reference to the embodiments, they are not intended to limit the present disclosure. Anyone with ordinary skill in the art may make slight modifications and improvements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application.
100、100a、100b、100c、100d、100e、100f:半導體晶片 110、110a、110b、110f:半導體晶粒 111、111a:第一型態半導體層 112:主動層 113、113a:第二型態半導體層 114、1511、1521:表面 115:另一表面 116、123:側表面 120、120a、120b:填充層 121:第一表面 122:第二表面 130、130e、130f:反射層 131:第一部分 132、132e、132f:第二部分 140、140e、140f、170:絕緣層 141、142:開口 150、150e、150f:電極層 151、151c、151d:第一電極 152、152c、152d:第二電極 160、160b、160f:透明導電層 G:間隙 PR1:負型光阻 PR2:正型光阻 RL:犧牲層 S1:第一載板 S2:第二載板 S3:第三載板 S21:基底 S22:電路層 Z:方向 θ1:夾角100, 100a, 100b, 100c, 100d, 100e, 100f: Semiconductor chip110, 110a, 110b, 110f: Semiconductor die111, 111a: First type semiconductor layer112: Active layer113, 113a: Second type semiconductor layer114, 1511, 1521: Surface115: Other surface116, 123: Side surface120, 120a, 120b: Filling layer121: First surface122: Second surface130, 130e, 130f: Reflective layer131: First portion132, 132e, 132f: Second portion140, 140e, 140f, 170: Insulating layer141, 142: Opening150, 150e, 150f: Electrode layer151, 151c, 151d: First electrode152, 152c, 152d: Second electrode160, 160b, 160f: Transparent conductive layerG: GapPR1: Negative photoresistPR2: Positive photoresistRL: Sacrificial layerS1: First carrierS2: Second carrierS3: Third carrierS21: SubstrateS22: Circuit layerZ: Directionθ1: Intersection angle
圖1A至圖1D為本揭露第一實施例的半導體晶片的製造方法的剖面示意圖。 圖2A至圖2E為本揭露第二實施例的半導體晶片的製造方法的剖面示意圖。 圖3A至圖3C為本揭露第三實施例的半導體晶片的製造方法的剖面示意圖。 圖4為本揭露第四實施例的半導體晶片的剖面示意圖。 圖5為本揭露第五實施例的半導體晶片的剖面示意圖。 圖6A至圖6B為本揭露第六實施例的半導體晶片的剖面示意圖。 圖7A至圖7B為本揭露第七實施例的半導體晶片的剖面示意圖。Figures 1A to 1D are schematic cross-sectional views of a method for manufacturing a semiconductor chip according to a first embodiment of the present disclosure.Figures 2A to 2E are schematic cross-sectional views of a method for manufacturing a semiconductor chip according to a second embodiment of the present disclosure.Figures 3A to 3C are schematic cross-sectional views of a method for manufacturing a semiconductor chip according to a third embodiment of the present disclosure.Figure 4 is a schematic cross-sectional view of a semiconductor chip according to a fourth embodiment of the present disclosure.Figure 5 is a schematic cross-sectional view of a semiconductor chip according to a fifth embodiment of the present disclosure.Figures 6A to 6B are schematic cross-sectional views of a semiconductor chip according to a sixth embodiment of the present disclosure.Figures 7A to 7B are schematic cross-sectional views of a semiconductor chip according to a seventh embodiment of the present disclosure.
100:半導體晶片100: Semiconductor chip
110:半導體晶粒110: Semiconductor Die
111:第一型態半導體層111: First type semiconductor layer
112:主動層112: Active Layer
113:第二型態半導體層113: Second type semiconductor layer
114:表面114: Surface
120:填充層120: Filling layer
121:第一表面121: First Surface
130:反射層130: Reflective layer
131:第一部分131: Part 1
132:第二部分132: Part 2
140:絕緣層140: Insulating layer
150:電極層150:Electrode layer
151:第一電極151: First electrode
152:第二電極152: Second electrode
160:透明導電層160:Transparent conductive layer
RL:犧牲層RL: Sacrificial Layer
S1:第一載板S1: First carrier board
S2:第二載板S2: Second carrier board
S21:基底S21: Base
S22:電路層S22: Circuit layer
Z:方向Z: Direction
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/620,889 | 2024-01-15 |
| Publication Number | Publication Date |
|---|---|
| TW202531572Atrue TW202531572A (en) | 2025-08-01 |
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