本發明的一個實施方式係關於一種半導體裝置、記憶體裝置、顯示裝置及電子裝置。此外，本發明的一個實施方式係關於一種半導體裝置的製造方法。One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. In addition, one embodiment of the present invention relates to a method for manufacturing a semiconductor device.
注意，本發明的一個實施方式不限定於上述技術領域。作為本發明的一個實施方式的技術領域的一個例子，可以舉出半導體裝置、顯示裝置、發光裝置、蓄電裝置、記憶體裝置、電子裝置、照明設備、輸入裝置（例如，觸控感測器）、輸入輸出裝置（例如，觸控面板）、上述裝置的驅動方法或上述裝置的製造方法。Note that one embodiment of the present invention is not limited to the aforementioned technical fields. Examples of the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting equipment, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods for these devices, and manufacturing methods for these devices.
注意，在本說明書等中，半導體裝置是指利用半導體特性的裝置以及包括半導體元件（電晶體、二極體、光電二極體等）的電路及包括該電路的裝置等。此外，半導體裝置是指能夠利用半導體特性而發揮作用的所有裝置。例如，作為半導體裝置的例子，有積體電路、具有積體電路的晶片、封裝中容納有晶片的電子構件。此外，有時記憶體裝置、顯示裝置、發光裝置、照明設備以及電子裝置等本身是半導體裝置，或者包括半導體裝置。Note that in this specification and other documents, the term "semiconductor device" refers to devices that utilize semiconductor properties, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.), and devices that include such circuits. Furthermore, a semiconductor device refers to any device that utilizes semiconductor properties. For example, integrated circuits, chips containing integrated circuits, and electronic components containing chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting equipment, and electronic devices may themselves be semiconductor devices or include semiconductor devices.
近年來，已對半導體裝置進行開發，LSI（Large Scale Integration：大型積體電路）、CPU（Central Processing Unit：中央處理器）、記憶體（記憶體裝置）等主要用於半導體裝置。CPU是包括將半導體晶圓加工來形成晶片而成的積體電路（包括電晶體及記憶體）且形成有作為連接端子的電極的半導體元件的集合體。In recent years, semiconductor devices have been developed, with LSIs (Large Scale Integration), CPUs (Central Processing Units), and memories being the main semiconductor devices. A CPU is an assembly of semiconductor elements that includes integrated circuits (including transistors and memory) formed by processing semiconductor wafers into chips, and electrodes serving as connection terminals.
LSI、CPU或記憶體等的積體電路（IC晶片）安裝在電路板上，例如安裝在印刷線路板上，並被用作各種電子裝置的構件之一。Integrated circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.
此外，藉由使用形成在具有絕緣表面的基板上的半導體薄膜構成電晶體的技術受到注目。該電晶體被廣泛地應用於積體電路（IC）、顯示裝置等電子裝置。作為可以應用於電晶體的半導體材料，矽類半導體材料被廣泛地周知，作為其他材料，氧化物半導體受到關注。Furthermore, technology that creates transistors using semiconductor thin films formed on a substrate with an insulating surface is attracting attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and displays. Silicon-based semiconductor materials are widely known as semiconductor materials that can be used in transistors, while oxide semiconductors are also attracting attention as alternative materials.
此外，已知使用氧化物半導體的電晶體在關閉狀態下的洩漏電流極小。例如，專利文獻1已公開了應用使用氧化物半導體的電晶體的洩漏電流小的特性的低功耗CPU等。此外，例如，專利文獻2公開了利用使用氧化物半導體的電晶體的洩漏電流小的特性實現存儲內容的長期保持的記憶體裝置等。Furthermore, it is known that transistors using oxide semiconductors have extremely low leakage current when in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristics of transistors using oxide semiconductors. Furthermore, Patent Document 2 discloses a memory device that utilizes the low leakage current characteristics of transistors using oxide semiconductors to achieve long-term retention of stored data.
此外，近年來，隨著電子裝置的小型化和輕量化，對積體電路的進一步高密度化的要求提高。此外，有提高包含積體電路的半導體裝置的生產率的需求。例如，專利文獻3及非專利文獻1公開了一種技術，其中藉由層疊使用氧化物半導體膜的第一電晶體和使用氧化物半導體膜的第二電晶體，重疊地設置多個記憶單元，以實現積體電路的高密度化。此外，專利文獻4公開了一種技術，其中沿垂直方向配置使用氧化物半導體膜的電晶體的通道，以實現積體電路的高密度化。Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for further high-density integrated circuits. Furthermore, there is a need to improve the productivity of semiconductor devices containing integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are stacked by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to achieve high-density integrated circuits. Furthermore, Patent Document 4 discloses a technology in which the channels of transistors using oxide semiconductor films are arranged vertically to achieve high-density integrated circuits.
[專利文獻1]日本專利申請公開第2012-257187號公報 [專利文獻2]日本專利申請公開第2011-151383號公報 [專利文獻3]國際專利申請公開第2021/053473號 [專利文獻4]日本專利申請公開第2013-211537號公報[Patent Document 1] Japanese Patent Application Publication No. 2012-257187[Patent Document 2] Japanese Patent Application Publication No. 2011-151383[Patent Document 3] International Patent Application Publication No. 2021/053473[Patent Document 4] Japanese Patent Application Publication No. 2013-211537
[非專利文獻1]M.Oota et al.，“3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”，IEDM Tech. Dig.，2019，pp.50-53[Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53
本發明的一個實施方式的目的之一是提供一種電特性良好的電晶體。本發明的一個實施方式的目的之一是提供一種通態電流大的電晶體。本發明的一個實施方式的目的之一是提供一種寄生電容小的電晶體。本發明的一個實施方式的目的之一是提供一種可靠性高的電晶體、半導體裝置、記憶體裝置或顯示裝置。本發明的一個實施方式的目的之一是提供一種能夠實現微型化或高積體化的電晶體、半導體裝置或記憶體裝置。本發明的一個實施方式的目的之一是提供一種功耗低的半導體裝置、記憶體裝置或顯示裝置。本發明的一個實施方式的目的之一是提供一種工作速度快的記憶體裝置。本發明的一個實施方式的目的之一是提供一種高清晰或高開口率的顯示裝置。本發明的一個實施方式的目的之一是提供一種上述電晶體、半導體裝置、記憶體裝置或顯示裝置的製造方法。One of the purposes of one embodiment of the present invention is to provide a transistor with good electrical characteristics. One of the purposes of one embodiment of the present invention is to provide a transistor with large on-state current. One of the purposes of one embodiment of the present invention is to provide a transistor with small parasitic capacitance. One of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device, memory device or display device with high reliability. One of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device or memory device capable of miniaturization or high integration. One of the purposes of one embodiment of the present invention is to provide a semiconductor device, memory device or display device with low power consumption. One of the purposes of one embodiment of the present invention is to provide a memory device with fast operating speed. One of the purposes of one embodiment of the present invention is to provide a display device with high definition or high aperture ratio. One of the purposes of an embodiment of the present invention is to provide a method for manufacturing the above-mentioned transistor, semiconductor device, memory device or display device.
注意，這些目的的記載並不妨礙其他目的的存在。本發明的一個實施方式並不需要實現所有上述目的。可以從說明書、圖式、申請專利範圍的記載中抽取上述目的以外的目的。Note that the inclusion of these objectives does not preclude the existence of other objectives. An embodiment of the present invention does not necessarily achieve all of the aforementioned objectives. Objectives other than the aforementioned objectives may be extracted from the description, drawings, and patent application.
本發明的一個實施方式是一種半導體裝置，該半導體裝置包括第一及第二氧化物半導體層、氧化物層、第一至第三導電層以及第一及第二絕緣層。第一絕緣層位於第一導電層上。第二導電層位於第一絕緣層上。第一導電層包括第一凹部。第一絕緣層及第二導電層在與第一凹部重疊的位置上包括第一開口部。氧化物層具有覆蓋第一開口部的側壁的部分。第一氧化物半導體層具有位於第二導電層上的部分、在第一開口部內位於第一導電層上的部分以及在第一開口部內夾著氧化物層對置於第一絕緣層的部分。第二氧化物半導體層位於第一氧化物半導體層上。第二絕緣層位於第二氧化物半導體層上。第三導電層位於第二絕緣層上。第三導電層在第一開口部內夾著第二絕緣層對置於第一氧化物半導體層。氧化物層包含氧化鎵。第一氧化物半導體層包含氧化銦。第二氧化物半導體層包含鎵和銦中的一者或兩者。第一氧化物半導體層的銦的含有率比第二氧化物半導體層的銦的含有率高。One embodiment of the present invention is a semiconductor device comprising first and second oxide semiconductor layers, an oxide layer, first to third conductive layers, and first and second insulating layers. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first conductive layer includes a first recess. The first insulating layer and the second conductive layer include a first opening at a position overlapping the first recess. The oxide layer includes a portion covering a sidewall of the first opening. The first oxide semiconductor layer includes a portion located on the second conductive layer, a portion located within the first opening and located on the first conductive layer, and a portion within the first opening that faces the first insulating layer with the oxide layer interposed therebetween. The second oxide semiconductor layer is located on the first oxide semiconductor layer. The second insulating layer is located on the second oxide semiconductor layer. The third conductive layer is located on the second insulating layer. The third conductive layer is located opposite the first oxide semiconductor layer within the first opening, sandwiching the second insulating layer therebetween. The oxide layer comprises gallium oxide. The first oxide semiconductor layer comprises indium oxide. The second oxide semiconductor layer comprises one or both of gallium and indium. The indium content of the first oxide semiconductor layer is higher than the indium content of the second oxide semiconductor layer.
在上述半導體裝置中，利用二次離子質譜分析法得到的第一氧化物半導體層的氫濃度較佳為低於1×1020atoms/cm3。In the above semiconductor device, the hydrogen concentration of the first oxide semiconductor layer obtained by secondary ion mass spectrometry is preferably lower than 1×1020 atoms/cm3 .
在上述半導體裝置中，較佳的是，第二絕緣層具有兩層以上的疊層，第二絕緣層所包括的層中的與第二氧化物半導體層接觸的層包含氧化鋁。In the above semiconductor device, preferably, the second insulating layer has two or more stacked layers, and among the layers included in the second insulating layer, the layer in contact with the second oxide semiconductor layer contains aluminum oxide.
在上述半導體裝置中，較佳的是，氧化物層的導帶底位於比第一氧化物半導體層的導帶底更靠近真空能階一側，第二氧化物半導體層的導帶底位於比第一氧化物半導體層的導帶底更靠近真空能階一側。In the above semiconductor device, preferably, the conduction band bottom of the oxide layer is located closer to the vacuum energy level than the conduction band bottom of the first oxide semiconductor layer, and the conduction band bottom of the second oxide semiconductor layer is located closer to the vacuum energy level than the conduction band bottom of the first oxide semiconductor layer.
在上述半導體裝置中，較佳的是，氧化物層包含銦，並且氧化物層的銦的含有率比鎵的含有率低。In the above semiconductor device, preferably, the oxide layer contains indium, and the indium content of the oxide layer is lower than the gallium content.
在上述半導體裝置中，較佳的是，氧化物層中的除了氧之外的鎵的含有率為95%以上，第一氧化物半導體層中的除了氧之外的銦的含有率為95%以上。In the above semiconductor device, preferably, the content of gallium excluding oxygen in the oxide layer is 95% or more, and the content of indium excluding oxygen in the first oxide semiconductor layer is 95% or more.
本發明的另一個實施方式是一種半導體裝置，該半導體裝置包括第一及第二氧化物半導體層、氧化物層、第一至第四導電層以及第一至第三絕緣層。第一絕緣層位於第一導電層上。第二導電層位於第一絕緣層上。第一導電層包括第一凹部。第一絕緣層及第二導電層在與第一凹部重疊的位置上包括第一開口部。氧化物層具有覆蓋第一開口部的側壁的部分。第一氧化物半導體層具有位於第二導電層上的部分、在第一開口部內位於第一導電層上的部分以及在第一開口部內夾著氧化物層對置於第一絕緣層的部分。第二氧化物半導體層位於第一氧化物半導體層上。第二絕緣層位於第二氧化物半導體層上。第三絕緣層位於第二絕緣層上，並在與第一開口部重疊的位置上包括第二開口部。第三導電層具有在第一開口部內隔著第二絕緣層對置於第一氧化物半導體層的部分以及位於第二開口部內的部分。第四導電層配置在第三絕緣層上，並具有與第三導電層接觸的區域。氧化物層包含氧化鎵。第一氧化物半導體層包含氧化銦。第二氧化物半導體層包含鎵和銦中的一者或兩者。第一氧化物半導體層的銦的含有率比第二氧化物半導體層的銦的含有率高。Another embodiment of the present invention is a semiconductor device comprising first and second oxide semiconductor layers, an oxide layer, first to fourth conductive layers, and first to third insulating layers. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first conductive layer includes a first recess. The first insulating layer and the second conductive layer include a first opening at a position overlapping the first recess. The oxide layer includes a portion covering a sidewall of the first opening. The first oxide semiconductor layer includes a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion located opposite the first insulating layer within the first opening with the oxide layer interposed therebetween. The second oxide semiconductor layer is located on the first oxide semiconductor layer. The second insulating layer is located on the second oxide semiconductor layer. The third insulating layer is located on the second insulating layer and includes a second opening at a position overlapping the first opening. The third conductive layer has a portion within the first opening that faces the first oxide semiconductor layer via the second insulating layer, and a portion within the second opening. The fourth conductive layer is disposed on the third insulating layer and has a region in contact with the third conductive layer. The oxide layer includes gallium oxide. The first oxide semiconductor layer includes indium oxide. The second oxide semiconductor layer includes one or both of gallium and indium. The indium content of the first oxide semiconductor layer is higher than the indium content of the second oxide semiconductor layer.
在上述半導體裝置中，利用二次離子質譜分析法得到的第一氧化物半導體層的氫濃度較佳為低於1×1020atoms/cm3。In the above semiconductor device, the hydrogen concentration of the first oxide semiconductor layer obtained by secondary ion mass spectrometry is preferably lower than 1×1020 atoms/cm3 .
在上述半導體裝置中，較佳的是，第二絕緣層具有兩層以上的疊層，第二絕緣層所包括的層中的與第二氧化物半導體層接觸的層包含氧化鋁。In the above semiconductor device, preferably, the second insulating layer has two or more stacked layers, and among the layers included in the second insulating layer, the layer in contact with the second oxide semiconductor layer contains aluminum oxide.
在上述半導體裝置中，較佳的是，氧化物層的導帶底位於比第一氧化物半導體層的導帶底更靠近真空能階一側，第二氧化物半導體層的導帶底位於比第一氧化物半導體層的導帶底更靠近真空能階一側。In the above semiconductor device, preferably, the conduction band bottom of the oxide layer is located closer to the vacuum energy level than the conduction band bottom of the first oxide semiconductor layer, and the conduction band bottom of the second oxide semiconductor layer is located closer to the vacuum energy level than the conduction band bottom of the first oxide semiconductor layer.
在上述半導體裝置中，較佳的是，氧化物層包含銦，氧化物層的銦的含有率比鎵的含有率低。In the above semiconductor device, preferably, the oxide layer contains indium, and the indium content of the oxide layer is lower than the gallium content.
在上述半導體裝置中，較佳的是，氧化物層中的除了氧之外的鎵的含有率為95%以上，第一氧化物半導體層中的除了氧之外的銦的含有率為95%以上。In the above semiconductor device, preferably, the content of gallium excluding oxygen in the oxide layer is 95% or more, and the content of indium excluding oxygen in the first oxide semiconductor layer is 95% or more.
本發明的另一個實施方式是一種半導體裝置，該半導體裝置包括第一及第二氧化物半導體層、氧化物層、第一至第三導電層以及第一至第三絕緣層。第一絕緣層位於第一導電層上。第二導電層位於第一絕緣層上。第一導電層包括第一凹部。第一絕緣層及第二導電層在與第一凹部重疊的位置上包括第一開口部。氧化物層具有覆蓋第一開口部的側壁的部分。第一氧化物半導體層具有位於第二導電層上的部分、在第一開口部內位於第一導電層上的部分以及在第一開口部內夾著氧化物層對置於第一絕緣層的部分。第二氧化物半導體層位於第一氧化物半導體層上。第二絕緣層位於第二氧化物半導體層上。第三導電層位於第二絕緣層上。第三導電層在第一開口部內夾著第二絕緣層對置於第一氧化物半導體層。氧化物層包含氧化鎵。第一氧化物半導體層包含氧化銦。第二氧化物半導體層包含鎵和銦中的一者或兩者。第一氧化物半導體層的銦的含有率比第二氧化物半導體層的銦的含有率高。第三絕緣層位於第一絕緣層與氧化物層間。第三絕緣層包括與第一絕緣層接觸的第四絕緣層以及位於第四絕緣層與氧化物層間的第五絕緣層。第四絕緣層包含矽及氮。第五絕緣層包含矽及氧。Another embodiment of the present invention is a semiconductor device comprising first and second oxide semiconductor layers, an oxide layer, first to third conductive layers, and first to third insulating layers. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first conductive layer includes a first recess. The first insulating layer and the second conductive layer include a first opening at a position overlapping the first recess. The oxide layer includes a portion covering a sidewall of the first opening. The first oxide semiconductor layer includes a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion located opposite the first insulating layer within the first opening with the oxide layer interposed therebetween. The second oxide semiconductor layer is located on the first oxide semiconductor layer. The second insulating layer is located on the second oxide semiconductor layer. The third conductive layer is located on the second insulating layer. The third conductive layer is located opposite the first oxide semiconductor layer within the first opening, sandwiching the second insulating layer. The oxide layer includes gallium oxide. The first oxide semiconductor layer includes indium oxide. The second oxide semiconductor layer includes one or both of gallium and indium. The indium content of the first oxide semiconductor layer is higher than the indium content of the second oxide semiconductor layer. The third insulating layer is located between the first insulating layer and the oxide layer. The third insulating layer includes a fourth insulating layer in contact with the first insulating layer and a fifth insulating layer located between the fourth insulating layer and the oxide layer. The fourth insulating layer includes silicon and nitrogen. The fifth insulating layer includes silicon and oxygen.
在上述半導體裝置中，利用二次離子質譜分析法得到的第一氧化物半導體層的氫濃度較佳為低於1×1020atoms/cm3。In the above semiconductor device, the hydrogen concentration of the first oxide semiconductor layer obtained by secondary ion mass spectrometry is preferably lower than 1×1020 atoms/cm3 .
在上述半導體裝置中，較佳的是，第二絕緣層具有兩層以上的疊層，第二絕緣層所包括的層中的與第二氧化物半導體層接觸的層包含氧化鋁。In the above semiconductor device, preferably, the second insulating layer has two or more stacked layers, and among the layers included in the second insulating layer, the layer in contact with the second oxide semiconductor layer contains aluminum oxide.
在上述半導體裝置中，較佳的是，氧化物層的導帶底位於比第一氧化物半導體層的導帶底更靠近真空能階一側，第二氧化物半導體層的導帶底位於比第一氧化物半導體層的導帶底更靠近真空能階一側。In the above semiconductor device, preferably, the conduction band bottom of the oxide layer is located closer to the vacuum energy level than the conduction band bottom of the first oxide semiconductor layer, and the conduction band bottom of the second oxide semiconductor layer is located closer to the vacuum energy level than the conduction band bottom of the first oxide semiconductor layer.
在上述半導體裝置中，較佳的是，氧化物層包含銦，氧化物層的銦的含有率比鎵的含有率低。In the above semiconductor device, preferably, the oxide layer contains indium, and the indium content of the oxide layer is lower than the gallium content.
在上述半導體裝置中，較佳的是，氧化物層中的除了氧之外的鎵的含有率為95%以上，第一氧化物半導體層中的除了氧之外的銦的含有率為95%以上。In the above semiconductor device, preferably, the content of gallium excluding oxygen in the oxide layer is 95% or more, and the content of indium excluding oxygen in the first oxide semiconductor layer is 95% or more.
另外，在上述半導體裝置中，氧化物層也可以包含氧化鋁或氧化釔代替氧化鎵。In addition, in the above-mentioned semiconductor device, the oxide layer may contain aluminum oxide or yttrium oxide instead of gallium oxide.
本發明的另一個實施方式是一種半導體裝置，該半導體裝置包括第一及第二氧化物半導體層、氧化物層、第一至第三導電層以及第一及第二絕緣層，其中，第一絕緣層位於第一導電層上，第二導電層位於第一絕緣層上，第一導電層包括第一凹部，第一絕緣層及第二導電層在與第一凹部重疊的位置上包括第一開口部，氧化物層具有覆蓋第一開口部的側壁的部分，第一氧化物半導體層具有位於第二導電層上的部分、在第一開口部內位於第一導電層上的部分以及在第一開口部內夾著氧化物層對置於第一絕緣層的部分，第二氧化物半導體層位於第一氧化物半導體層上，第二絕緣層位於第二氧化物半導體層上，第三導電層位於第二絕緣層上，第三導電層在第一開口部內夾著第二絕緣層對置於第一氧化物半導體層。當對該半導體裝置在設定溫度為125℃、汲極電位Vd及源極電位Vs為0V、閘極電位Vg為+1.98V的測量條件下進行暗室下的閘極BT應力測試時，藉由經過100小時後的Id-Vg測量算出的臨界電壓的變化量為-500mV以上且500mV以下。Another embodiment of the present invention is a semiconductor device comprising first and second oxide semiconductor layers, an oxide layer, first to third conductive layers, and first and second insulating layers, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the first conductive layer includes a first recess, the first insulating layer and the second conductive layer include a first opening at a position overlapping the first recess, and the oxide layer has a sidewall covering the first opening. The first oxide semiconductor layer includes a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion located opposite to the first insulating layer with the oxide layer interposed therebetween within the first opening. The second oxide semiconductor layer is located on the first oxide semiconductor layer, the second insulating layer is located on the second oxide semiconductor layer, and the third conductive layer is located on the second insulating layer. The third conductive layer is located opposite to the first oxide semiconductor layer with the second insulating layer interposed therebetween within the first opening. When the semiconductor device was subjected to a gate BT stress test in a darkroom at a set temperature of 125°C, with the drain potential Vd and source potential Vs at 0V and the gate potential Vg at +1.98V, the change in critical voltage calculated from Id-Vg measurements after 100 hours was greater than -500mV and less than 500mV.
本發明的另一個實施方式是一種上述任一個半導體裝置的製造方法。較佳為藉由使用包含鎵的第一前驅物及第一氧化劑且利用ALD法形成氧化物層。較佳為藉由使用包含銦的第二前驅物及包含臭氧的第二氧化劑且利用ALD法形成第一氧化物半導體層。較佳為藉由使用包含銦及鎵的濺射靶材且利用濺射法形成第二氧化物半導體層。Another embodiment of the present invention is a method for manufacturing any of the aforementioned semiconductor devices. Preferably, the oxide layer is formed by using an ALD method using a first precursor containing gallium and a first oxidant. Preferably, the first oxide semiconductor layer is formed by using an ALD method using a second precursor containing indium and a second oxidant containing ozone. Preferably, the second oxide semiconductor layer is formed by sputtering using a sputtering target containing indium and gallium.
在上述半導體裝置的製造方法中，較佳為以不暴露於大氣的方式形成氧化物層及第一氧化物半導體層。In the above-mentioned method for manufacturing a semiconductor device, it is preferred that the oxide layer and the first oxide semiconductor layer are formed without being exposed to the atmosphere.
在上述半導體裝置的製造方法中，較佳為在形成第二氧化物半導體層之後進行微波電漿處理。較佳的是，微波電漿處理時的氧流量比為0.5%以上且5%以下，微波電漿處理時的基板的加熱溫度為300℃以上且450℃以下。In the above method for manufacturing a semiconductor device, microwave plasma treatment is preferably performed after forming the second oxide semiconductor layer. Preferably, the oxygen flow rate during the microwave plasma treatment is 0.5% to 5%, and the substrate heating temperature during the microwave plasma treatment is 300°C to 450°C.
在上述半導體裝置的製造方法中，較佳的是，第二絕緣層使用兩種以上的膜形成，兩種以上的膜中的與第二氧化物半導體層接觸的膜包含氧化鋁。In the above method for manufacturing a semiconductor device, preferably, the second insulating layer is formed using two or more films, and the film in contact with the second oxide semiconductor layer among the two or more films contains aluminum oxide.
根據本發明的一個實施方式，可以提供一種電特性良好的電晶體。根據本發明的一個實施方式，可以提供一種通態電流大的電晶體。根據本發明的一個實施方式，可以提供一種寄生電容小的電晶體。根據本發明的一個實施方式，可以提供一種可靠性高的電晶體、半導體裝置、記憶體裝置或顯示裝置。根據本發明的一個實施方式，可以提供一種能夠實現微型化或高積體化的電晶體、半導體裝置或記憶體裝置。根據本發明的一個實施方式，可以提供一種功耗低的半導體裝置、記憶體裝置或顯示裝置。根據本發明的一個實施方式，可以提供一種工作速度快的記憶體裝置。根據本發明的一個實施方式，可以提供一種高清晰或高開口率的顯示裝置。根據本發明的一個實施方式，可以提供一種上述電晶體、半導體裝置、記憶體裝置或顯示裝置的製造方法。According to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, memory device, or display device with high reliability can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device capable of miniaturization or high integration can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a high-definition or high-aperture display device can be provided. According to one embodiment of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, memory device, or display device can be provided.
注意，這些效果的記載並不妨礙其他效果的存在。本發明的一個實施方式並不需要具有所有上述效果。可以從說明書、圖式、申請專利範圍的記載中抽取上述效果以外的效果。Note that the description of these effects does not preclude the existence of other effects. A single embodiment of the present invention does not necessarily have all of the effects described above. Effects other than the effects described above may be extracted from the description in the specification, drawings, and patent application.
參照圖式對實施方式進行詳細說明。注意，本發明不侷限於以下說明，而所屬技術領域的通常知識者可以很容易地理解一個事實就是其方式及詳細內容在不脫離本發明的精神及其範圍的情況下可以被變換為各種各樣的形式。因此，本發明不應該被解釋為僅限定在以下所示的實施方式所記載的內容中。The embodiments are described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily appreciate that its methods and details can be modified in various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the following embodiments.
注意，在下面說明的發明結構中，在不同的圖式中共同使用相同的符號來表示相同的部分或具有同樣功能的部分，而省略反復說明。此外，當表示具有同樣功能的部分時有時使用相同的陰影線，而不特別附加符號。Note that in the invention structure described below, the same symbols are used in different drawings to represent the same parts or parts with the same function, and repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.
此外，為了便於理解，有時圖式中示出的各組件的位置、大小及範圍等並不表示其實際的位置、大小及範圍等。因此，所公開的發明並不必然限於圖式中公開的位置、大小及範圍等。In addition, for ease of understanding, the positions, sizes, and ranges of components shown in the drawings sometimes do not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.
注意，在本說明書等中，為了方便起見，附加了“第一”、“第二”等序數詞，而其並不限制組件的個數或組件的順序（例如，製程順序或疊層順序）。此外，在本說明書中的某一部分對組件附加的序數詞與在本說明書中的其他部分或申請專利範圍對該組件附加的序數詞有時不一致。Note that in this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of components (e.g., manufacturing order or stacking order). Furthermore, the ordinal numbers assigned to components in one section of this specification may not be consistent with the ordinal numbers assigned to the same components in other sections of this specification or in the patent claims.
電晶體是半導體元件的一種，並且可以實現放大電流或電壓的功能、控制導通或非導通的切換工作等。本說明書中的電晶體包括IGFET（Insulated Gate Field Effect Transistor：絕緣閘場效電晶體）和薄膜電晶體（TFT：Thin Film Transistor）。A transistor is a type of semiconductor device that can amplify current or voltage, control switching between conduction and non-conduction, and more. Transistors in this document include IGFETs (Insulated Gate Field Effect Transistors) and Thin Film Transistors (TFTs).
在本說明書等中，有時將氧化物半導體或金屬氧化物用於半導體層的電晶體及在通道形成區域中包含氧化物半導體或金屬氧化物的電晶體被稱為OS電晶體。此外，有時在通道形成區域中包含矽的電晶體被稱為Si電晶體。In this specification, transistors using oxide semiconductors or metal oxides for their semiconductor layers and transistors containing oxide semiconductors or metal oxides in their channel formation regions are sometimes referred to as OS transistors. Furthermore, transistors containing silicon in their channel formation regions are sometimes referred to as Si transistors.
在本說明書等中，電晶體是指至少包括閘極、汲極以及源極這三個端子的元件。電晶體在汲極（汲極端子、汲極區域或汲極電極）與源極（源極端子、源極區域或源極電極）之間具有形成通道的區域（也稱為通道形成區域），並且藉由通道形成區域電流能夠流過源極和汲極之間。注意，在本說明書等中，通道形成區域是指電流主要流過的區域。In this specification and other documents, a transistor refers to a device with at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel. Current flows between the source and drain through the channel-forming region. Note that in this specification and other documents, the channel-forming region refers to the region where current primarily flows.
此外，在採用不同極性的電晶體的情況或者電路工作中的電流方向變化的情況等下，“源極”和“汲極”的功能有時相互調換。因此，在本說明書中，“源極”和“汲極”可以相互調換。In addition, the functions of "source" and "drain" may be reversed when using transistors of different polarities or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" may be reversed.
注意，半導體的雜質例如是指構成半導體的主要成分之外的元素。例如，濃度低於0.1atomic%的元素可以說是雜質。在包含雜質時，例如有時發生半導體的缺陷態密度的增高或者結晶性的降低等。當半導體是氧化物半導體時，作為改變半導體的特性的雜質，例如有第1族元素、第2族元素、第13族元素、第14族元素、第15族元素以及除氧化物半導體的主要成分外的過渡金屬等。明確而言，例如，有氫、鋰、鈉、矽、硼、磷、碳及氮等。此外，有時水也作為雜質起作用。此外，例如有時雜質的混入導致氧化物半導體中的氧空位（還記載為VO）的形成。Note that the term "impurities" in a semiconductor refers to elements other than the main components of the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be considered an impurity. When impurities are present, for example, the defect state density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, for example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In addition, water sometimes acts as an impurity. In addition, for example, the mixing of impurities sometimes leads to the formation of oxygen vacancies (also recorded asVO ) in the oxide semiconductor.
注意，在本說明書等中，氧氮化物是指在其組成中含氧量多於含氮量的材料。氮氧化物是指在其組成中含氮量多於含氧量的材料。Note that in this specification and other documents, an oxynitride refers to a material containing more oxygen than nitrogen in its composition, and an oxynitride refers to a material containing more nitrogen than oxygen in its composition.
例如可以利用二次離子質譜分析法（SIMS：Secondary Ion Mass Spectrometry）或X射線光電子能譜法（XPS：X-ray Photoelectron Spectroscopy或者ESCA：Electron Spectroscopy for Chemical Analysis）分析出膜中的氫、氧、碳或氮等元素的含量。在目的元素的含有率高（例如為0.5atomic%以上或1atomic%以上）時，XPS很合適。另一方面，在目的元素的含有率低（例如為0.5atomic%以下或1atomic%以下）時，SIMS很合適。在比較元素含量時，更佳為採用SIMS和XPS的兩者分析技術進行複合分析。For example, the content of elements such as hydrogen, oxygen, carbon, or nitrogen in a film can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or ESCA (Electron Spectroscopy for Chemical Analysis). XPS is particularly suitable when the content of the target element is high (e.g., 0.5 atomic% or higher or 1 atomic% or higher). On the other hand, SIMS is particularly suitable when the content of the target element is low (e.g., 0.5 atomic% or lower or 1 atomic% or lower). When comparing elemental contents, a combined analysis using both SIMS and XPS is preferred.
注意，在本說明書等中，含有率是指膜中的成分的比例。例如，在氧化物半導體層包含金屬元素X、金屬元素Y、金屬元素Z且該氧化物半導體層所包含的金屬元素X、金屬元素Y、金屬元素Z各自的原子數分別為AX、AY、AZ時，金屬元素X的含有率可以表示為AX/（AX+AY+AZ）。另外，在氧化物半導體層中的金屬元素X、金屬元素Y、金屬元素Z各自的原子數的比例（原子數比）為BX：BY：BZ的情況下，金屬元素X的含有率可以表示為BX/（BX+BY+BZ）。Note that in this specification and other documents, the term "content" refers to the ratio of components in a film. For example, if an oxide semiconductor layer contains metal element X, metal element Y, and metal element Z, and the atomic numbers of metal element X, metal elementY , and metal element Z contained in the oxide semiconductor layer areAX , AY, andAZ , respectively, the content of metal element X can be expressed asAX /(AX +AY +AZ ). Furthermore, if the atomic ratio (atomic ratio) of metal element X, metal element Y, and metal element Z in the oxide semiconductor layer isBX :BY:BZ , the content of metal element X can be expressed asBX /(BX +BY +BZ ).
此外，根據情況或狀態，可以互相調換“膜”和“層”。例如，可以將“導電層”變換為“導電膜”。此外，例如可以將“絕緣膜”變換為“絕緣層”。Furthermore, depending on the situation or state, the terms "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced with "conductive film." Also, for example, "insulating film" can be replaced with "insulating layer."
在本說明書等中，“平行”是指兩條直線形成的角度為-10度以上且10度以下的狀態。因此，也包括該角度為-5度以上且5度以下的狀態。“大致平行”是指兩條直線形成的角度為-20度以上且20度以下的狀態。此外，“垂直”是指兩條直線的角度為80度以上且100度以下的狀態。因此，也包括該角度為85度以上且95度以下的狀態。“大致垂直”是指兩條直線形成的角度為70度以上且110度以下的狀態。In this specification, etc., "parallel" refers to a state in which the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, a state in which the angle is greater than -5 degrees and less than 5 degrees is also included. "Approximately parallel" refers to a state in which the angle formed by two straight lines is greater than -20 degrees and less than 20 degrees. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, a state in which the angle is greater than 85 degrees and less than 95 degrees is also included. "Approximately perpendicular" refers to a state in which the angle formed by two straight lines is greater than 70 degrees and less than 110 degrees.
作為本說明書中的“連接”的一個例子，包括“電連接”。注意，為了電路元件的連接關係作為物體規定，有時表示為“電連接”。另外，“電連接”包括“直接連接”及“間接連接”。“A與B直接連接”是指A與B不藉由電路元件（例如為電晶體、開關等。注意，佈線不是電路元件）而連接的情況。另一方面，“A與B間接連接”是指A與B藉由一個以上的電路元件而連接的情況。As used in this specification, "connection" is exemplified by "electrical connection." Note that to define the physical connection between circuit components, "electrical connection" is sometimes used. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit components (e.g., transistors, switches, etc.; note that wiring is not a circuit component). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit components.
例如，當假設為包括A及B的電路進行工作時，在電路的工作期間中有在A與B間發生電信號的授受或電位的相互作用的時序的情況下，作為物體可以規定為“A與B間接連接”。注意，即使在電路的工作期間中有在A與B間沒有發生電信號的授受或電位的相互作用的時序，只要在電路的工作期間中有在A與B間發生電信號的授受或電位的相互作用的時序，就可以規定為“A與B間接連接”。For example, assuming that a circuit including A and B operates, if there is a sequence in which electric signals are transferred or potentials are exchanged between A and B during the operation of the circuit, then the objects can be specified as "A and B are indirectly connected." Note that even if there is no sequence in which electric signals are transferred or potentials are exchanged between A and B during the operation of the circuit, as long as there is a sequence in which electric signals are transferred or potentials are exchanged between A and B during the operation of the circuit, it can be specified as "A and B are indirectly connected."
作為“A與B間接連接”的情況的例子，有A與B藉由一個以上的電晶體的源極及汲極而連接的情況。另一方面，作為不可以說“A與B間接連接”的情況的例子，有從A到B的路徑包括絕緣物的情況。明確而言，有A與B間連接有電容器的情況、A與B間包括電晶體的閘極絕緣膜等的情況等。由此，不可以說“電晶體的閘極（A）與電晶體的源極或汲極（B）間接連接”。Examples of situations where "A and B are indirectly connected" include cases where A and B are connected via the source and drain of one or more transistors. On the other hand, examples of situations where "A and B are not indirectly connected" include cases where the path from A to B includes an insulator. Specifically, there are cases where a capacitor is connected between A and B, or where a transistor gate insulating film, for example, is between A and B. Therefore, it cannot be said that "the transistor gate (A) is indirectly connected to the transistor source or drain (B)."
作為不可以說“A與B間接連接”的情況的另一個例子，有如下情況：在從A到B的路徑上多個電晶體藉由源極及汲極而連接，並且電晶體與其他電晶體間的節點被供應來自電源、GND等的固定電位V。As another example of a situation where it is not appropriate to say "A and B are indirectly connected," consider a situation where multiple transistors are connected via source and drain on a path from A to B, and a fixed potential V is supplied to the nodes between the transistors, such as from a power source or GND.
在本說明書等中，在沒有特別的說明的情況下，關態電流（off-state current）是指電晶體處於關閉狀態（也稱為非導通狀態、遮斷狀態）時的源極和汲極之間的洩漏電流。在沒有特別的說明的情況下，在n通道型電晶體中，關閉狀態是指閘極與源極間的電壓Vgs低於臨界電壓Vth（p通道型電晶體中Vgs高於Vth）的狀態。In this specification and other documents, unless otherwise specified, off-state current refers to the leakage current between the source and drain when a transistor is in the off state (also called the non-conducting state or the blocked state). Unless otherwise specified, for n-channel transistors, the off state refers to the state when the voltageVgs between the gate and source is below the critical voltageVth (for p-channel transistors,Vgs is higher thanVth ).
在本說明書等中，常開啟特性是指即使不對閘極施加電壓也存在通道，而電流流過電晶體的狀態。此外，常關閉特性是指在不對閘極施加電位或者對閘極供應接地電位時電流不流過電晶體的狀態。In this specification, the term "normally-on" refers to a state in which a channel exists and current flows through a transistor even when no voltage is applied to the gate. The term "normally-off" refers to a state in which current does not flow through a transistor when no potential is applied to the gate or when ground potential is applied to the gate.
另外，在本說明書等中，錐形形狀是指組件的側面的至少一部分相對於基板面或被形成面傾斜地設置的形狀。例如，較佳為具有傾斜的側面和基板面或被形成面所形成的角度（也被稱為錐角）大於0度且小於90度的區域。在此，組件的側面、基板面及被形成面不一定必須完全平坦，也可以是具有微小曲率的近似平面狀或具有微細凹凸的近似平面狀。In this specification, a tapered shape refers to a shape in which at least a portion of a component's side surface is inclined relative to the substrate surface or the surface being formed. For example, preferably, the angle formed between the inclined side surface and the substrate surface or the surface being formed (also referred to as a taper angle) is greater than 0 degrees and less than 90 degrees. The component's side surface, substrate surface, or surface being formed does not necessarily need to be completely flat; it may be a nearly flat surface with a slight curvature or a nearly flat surface with slight irregularities.
在本說明書等中，在記載為A位於B上的情況下，A的至少一部分位於B上。因此，例如，可以換稱為A具有位於B上的區域。同樣地，在記載為A與B接觸或者A與B重疊的情況下，A的至少一部分與B接觸或與B重疊。因此，分別可以換稱為A具有與B接觸的區域或者A具有與B重疊的區域。同樣地，在記載為A覆蓋B的情況下，A的至少一部分覆蓋B。因此，例如可以換稱為A具有覆蓋B的區域。In this specification, etc., when it is described that A is located on B, at least a portion of A is located on B. Therefore, for example, this can be replaced by saying that A has a region located on B. Similarly, when it is described that A is in contact with B or that A overlaps with B, at least a portion of A is in contact with B or overlaps with B. Therefore, these can be replaced by saying that A has a region in contact with B or that A has a region overlapping with B, respectively. Similarly, when it is described that A covers B, at least a portion of A covers B. Therefore, for example, this can be replaced by saying that A has a region covering B.
在本說明書等中，有時將使用金屬遮罩或FMM（Fine Metal Mask，高精細金屬遮罩）製造的器件稱為具有MM（Metal Mask）結構的器件。此外，在本說明書等中，有時將不使用金屬遮罩或FMM製造的器件稱為具有MML（Metal Mask Less）結構的器件。In this specification and other documents, devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as having an MM (Metal Mask) structure. Furthermore, devices manufactured without a metal mask or FMM are sometimes referred to as having an MML (Metal Mask Less) structure.
在本說明書等中，有時將在發光波長不同的發光元件（也稱為發光器件）中分別製造發光層的結構稱為SBS（Side By Side）結構。SBS結構由於可以在各發光元件中使材料及結構最佳化，因此材料及結構的選擇彈性得到提高，可以容易實現亮度及可靠性的提高。In this specification and other contexts, the structure in which the light-emitting layers of light-emitting elements (also called light-emitting devices) with different emission wavelengths are separately manufactured is sometimes referred to as an SBS (Side-by-Side) structure. The SBS structure allows for optimization of materials and structures for each light-emitting element, thus increasing flexibility in material and structure selection and facilitating improvements in brightness and reliability.
在本說明書等中，有時將電洞或電子表示為“載子”。明確而言，有時將電洞注入層或電子注入層稱為“載子注入層”，將電洞傳輸層或電子傳輸層稱為“載子傳輸層”，將電洞阻擋層或電子阻擋層稱為“載子阻擋層”。注意，有時無法明確地區分上述載子注入層、載子傳輸層及載子阻擋層。此外，有時一個層兼具載子注入層、載子傳輸層和載子阻擋層中的兩者或三者的功能。In this specification and other documents, holes or electrons are sometimes referred to as "carriers." Specifically, a hole-injection layer or electron-injection layer is sometimes referred to as a "carrier injection layer," a hole-transport layer or electron-transport layer is sometimes referred to as a "carrier transport layer," and a hole-blocking layer or electron-blocking layer is sometimes referred to as a "carrier blocking layer." Note that sometimes it is not possible to clearly distinguish between carrier-injection layers, carrier-transport layers, and carrier-blocking layers. Furthermore, a single layer may serve two or all three functions of a carrier-injection layer, a carrier-transport layer, and a carrier-blocking layer.
在本說明書等中，發光元件在一對電極間包括EL層。EL層至少包括發光層。在此，作為EL層所包括的層（也被稱為功能層），可以舉出發光層、載子注入層（電洞注入層及電子注入層）、載子傳輸層（電洞傳輸層及電子傳輸層）及載子阻擋層（電洞阻擋層及電子阻擋層）等。在本說明書等中，有時將一對電極中的一方記為像素電極且將另一方記為共用電極。In this specification and other documents, a light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification and other documents, one of the pair of electrodes is sometimes referred to as a pixel electrode, and the other as a common electrode.
在本說明書等中，犧牲層（也可以稱為遮罩層）至少位於發光層（更明確而言是構成EL層的層中被加工為島狀的層）的上方，並且在製程中具有保護該發光層的功能。In this specification and other documents, the sacrificial layer (also referred to as a mask layer) is located at least above the light-emitting layer (more specifically, the layer processed into an island shape among the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
在本說明書等中，斷開是指層、膜或電極因被形成面的形狀（例如，步階等）而斷開的現象。In this specification, etc., "breakage" refers to the phenomenon in which a layer, film, or electrode is broken due to the shape of the surface on which it is formed (e.g., steps, etc.).
注意，有時在本說明書的圖式等中附上表示X方向、Y方向以及Z方向的箭頭。注意，在本說明書等中，“X方向”是指沿著X軸的方向，除了明確指出的情況以外，有時不區別其順向及逆向。“Y方向”及“Z方向”也是同樣的。此外，X方向、Y方向以及Z方向是彼此交叉的方向。例如，X方向、Y方向以及Z方向是彼此正交的方向。Note that arrows indicating the X, Y, and Z directions may be included in the drawings and other figures in this specification. Note that in this specification and other figures, the "X direction" refers to the direction along the X axis, and unless otherwise specified, the distinction between the forward and reverse directions is not sometimes made. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions intersect with each other. For example, the X, Y, and Z directions are orthogonal to each other.
實施方式1 在本實施方式中，參照圖1A至圖18C說明本發明的一個實施方式的半導體裝置及其製造方法。Embodiment 1This embodiment describes a semiconductor device and a method for manufacturing the same according to one embodiment of the present invention with reference to Figures 1A to 18C.
本發明的一個實施方式的半導體裝置包括電晶體。另外，本發明的一個實施方式的半導體裝置包括氧化物半導體層、氧化物層、第一至第三導電層和第一及第二絕緣層。A semiconductor device according to one embodiment of the present invention includes a transistor. Furthermore, a semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer, an oxide layer, first to third conductive layers, and first and second insulating layers.
氧化物半導體層被用作電晶體的半導體層，第一導電層被用作電晶體的源極電極和汲極電極中的一個，第二導電層被用作電晶體的源極電極和汲極電極中的另一個，第三導電層被用作電晶體的閘極電極。第二絕緣層被用作電晶體的閘極絕緣層。The oxide semiconductor layer is used as the semiconductor layer of the transistor, the first conductive layer is used as one of the source electrode and the drain electrode of the transistor, the second conductive layer is used as the other of the source electrode and the drain electrode of the transistor, the third conductive layer is used as the gate electrode of the transistor, and the second insulating layer is used as the gate insulating layer of the transistor.
第一絕緣層位於第一導電層上，第二導電層位於第一絕緣層上，第一導電層包括第一凹部，第一絕緣層及第二導電層在與第一凹部重疊的位置上包括第一開口部。The first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the first conductive layer includes a first recess, and the first insulating layer and the second conductive layer include a first opening at a position overlapping the first recess.
氧化物層具有覆蓋第一開口部的側壁的部分。氧化物半導體層具有位於第二導電層上的部分、在第一開口部內位於第一導電層上的部分以及在第一開口部內夾著氧化物層對置於第一絕緣層的部分。第二絕緣層位於氧化物半導體層上，第三導電層位於第二絕緣層上。另外，氧化物半導體層在第一開口部內夾著氧化物層對置於第一絕緣層，第三導電層在第一開口部內夾著第二絕緣層對置於氧化物半導體層。The oxide layer has a portion covering the sidewalls of the first opening. The oxide semiconductor layer has a portion located on the second conductive layer, a portion located within the first opening on the first conductive layer, and a portion located within the first opening opposite the first insulating layer with the oxide layer interposed therebetween. The second insulating layer is located on the oxide semiconductor layer, and the third conductive layer is located on the second insulating layer. Furthermore, the oxide semiconductor layer is located within the first opening opposite the first insulating layer with the oxide layer interposed therebetween, and the third conductive layer is located within the first opening opposite the oxide semiconductor layer with the second insulating layer interposed therebetween.
氧化物半導體層較佳為具有第一氧化物半導體層及第一氧化物半導體層上的第二氧化物半導體層的兩層結構。再者，第二氧化物半導體層的Ga的含有率較佳為比第一氧化物半導體層的Ga的含有率高。The oxide semiconductor layer preferably has a two-layer structure of a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer. Furthermore, the Ga content of the second oxide semiconductor layer is preferably higher than the Ga content of the first oxide semiconductor layer.
藉由提高第二氧化物半導體層的Ga的含有率，可以提高第二氧化物半導體層的氫阻擋性。由此，可以抑制氫擴散到形成通道的第一氧化物半導體層中。另外，藉由提高第二氧化物半導體層的Ga的含有率，可以利用形成氧化物半導體層之後施加的熱等減少包含在氧化物半導體層中的氫或水等雜質。由此，可以提高電晶體的電特性，而可以提高電晶體的可靠性。By increasing the Ga content in the second oxide semiconductor layer, the hydrogen barrier properties of the second oxide semiconductor layer can be improved. This can suppress the diffusion of hydrogen into the first oxide semiconductor layer, which forms the channel. Furthermore, by increasing the Ga content in the second oxide semiconductor layer, impurities such as hydrogen and water contained in the oxide semiconductor layer can be reduced by heat application after the oxide semiconductor layer is formed. This can improve the electrical characteristics of the transistor and enhance transistor reliability.
另外，藉由提高第二氧化物半導體層的Ga的含有率，可以提高第二氧化物半導體層的氧阻擋性。由此，可以抑制從形成通道的第一氧化物半導體層釋放氧，而可以抑制在第一氧化物半導體層中形成氧空位或者在第一氧化物半導體層中氧空位量增加。由此，可以提高電晶體的電特性。Furthermore, by increasing the Ga content in the second oxide semiconductor layer, the oxygen barrier properties of the second oxide semiconductor layer can be enhanced. This can suppress the release of oxygen from the first oxide semiconductor layer, which forms the channel, and can prevent the formation of oxygen vacancies in the first oxide semiconductor layer or the increase in the amount of oxygen vacancies in the first oxide semiconductor layer. This can improve the electrical characteristics of the transistor.
另外，第一氧化物半導體層的In的含有率較佳為比第二氧化物半導體層的In的含有率高。藉由提高第一氧化物半導體層的In的含有率，可以增大通態電流並提高頻率特性。In addition, the In content of the first oxide semiconductor layer is preferably higher than the In content of the second oxide semiconductor layer. By increasing the In content of the first oxide semiconductor layer, the on-state current can be increased and the frequency characteristics can be improved.
在本發明的一個實施方式的電晶體中，第一導電層中設置有第一凹部。由此，與不設置第一凹部的情況相比，可以降低第一開口部內的第二絕緣層的底面的高度及第三導電層的底面的高度。因此，閘極電場容易到達氧化物半導體層，電晶體可以具有良好的電特性。在此，各面的高度例如可以以電晶體的被形成面為基準決定。In a transistor according to one embodiment of the present invention, a first recess is provided in the first conductive layer. This allows the height of the bottom surface of the second insulating layer and the bottom surface of the third conductive layer within the first opening to be lowered compared to a case without the first recess. This allows the gate electric field to more easily reach the oxide semiconductor layer, resulting in a transistor with excellent electrical characteristics. The height of each surface can be determined, for example, based on the surface on which the transistor is formed.
另外，當產生在源極電極或汲極電極與閘極佈線之間的寄生電容大時，有時電晶體的工作變慢而使用該電晶體的電路的頻率特性下降。Furthermore, when the parasitic capacitance generated between the source electrode or drain electrode and the gate wiring is large, the operation of the transistor may slow down, and the frequency characteristics of the circuit using the transistor may be degraded.
於是，本發明的一個實施方式的電晶體較佳為具有減少產生在第二導電層與第三導電層之間的寄生電容的結構。由此，可以實現電晶體的高速工作。此外，可以提供一種具有良好的電特性的半導體裝置。Therefore, the transistor of one embodiment of the present invention preferably has a structure that reduces parasitic capacitance generated between the second conductive layer and the third conductive layer. This allows for high-speed operation of the transistor and provides a semiconductor device with excellent electrical characteristics.
例如，本發明的一個實施方式的半導體裝置較佳為還包括第三絕緣層。此時，較佳的是，第二絕緣層在第一絕緣層上覆蓋氧化物半導體層的頂面及側面，第三絕緣層位於第二絕緣層上並在與第一開口部重疊的位置上具有第二開口部，第三導電層具有在第一開口部內隔著第二絕緣層對置於氧化物半導體層的部分及位於第二開口部內的部分。For example, a semiconductor device according to one embodiment of the present invention preferably further includes a third insulating layer. In this case, the second insulating layer preferably covers the top and side surfaces of the oxide semiconductor layer on the first insulating layer, the third insulating layer preferably includes a second opening located on the second insulating layer and overlapping the first opening, and the third conductive layer preferably includes a portion within the first opening that faces the oxide semiconductor layer across the second insulating layer and a portion located within the second opening.
第三導電層具有在第一開口部內隔著第二絕緣層對置於氧化物半導體層的部分及位於第二開口部內的部分。在此情況下，閘極佈線配置在第三絕緣層上，從而可以增加第二導電層和閘極佈線之間的物理距離。因此，可以減少產生在第二導電層與閘極佈線之間的寄生電容。另外，既可將第三導電層的一部分（位於第三絕緣層上的部分）用作閘極佈線，又可在第四絕緣層上設置與第三導電層不同的閘極佈線。The third conductive layer has a portion within the first opening that faces the oxide semiconductor layer across the second insulating layer, and a portion within the second opening. In this case, the gate wiring is arranged on the third insulating layer, thereby increasing the physical distance between the second conductive layer and the gate wiring. This reduces parasitic capacitance between the second conductive layer and the gate wiring. Furthermore, a portion of the third conductive layer (the portion located on the third insulating layer) can be used as a gate wiring, while a gate wiring separate from the third conductive layer can be provided on the fourth insulating layer.
另外，例如，本發明的一個實施方式的半導體裝置較佳為還包括第四絕緣層。第四絕緣層在第一開口部內位於第一絕緣層與氧化物層間。第四絕緣層較佳為具有氫阻擋性。藉由採用這種結構，由具有氫阻擋性的第四絕緣層以環狀圍繞氧化物半導體層的周圍，由此可以防止氫混入到氧化物半導體層中。因此，可以提高電晶體的電特性，而可以提高電晶體的可靠性。Furthermore, for example, the semiconductor device according to one embodiment of the present invention preferably further includes a fourth insulating layer. The fourth insulating layer is located within the first opening, between the first insulating layer and the oxide layer. The fourth insulating layer preferably has hydrogen-barrier properties. With this structure, the fourth insulating layer with hydrogen-barrier properties surrounds the oxide semiconductor layer in a ring shape, thereby preventing hydrogen from incorporating into the oxide semiconductor layer. Consequently, the electrical characteristics of the transistor can be improved, thereby enhancing transistor reliability.
另外，也可以由多個層構成第四絕緣層。例如，第四絕緣層可以由與第一絕緣層接觸的第一層以及位於第一層與氧化物層間的第二層這兩個層構成。此時，當第一層具有氫阻擋性且第二層具有俘獲或固定氫的功能時，可以降低氧化物半導體層的氫濃度。或者，當第一層具有氫阻擋性且第二層包括具有過量氧的區域時，可以減少氧化物半導體層中的氧空位和雜質中的一者或兩者。因此，可以提高電晶體的電特性，而可以提高電晶體的可靠性。Alternatively, the fourth insulating layer can be composed of multiple layers. For example, the fourth insulating layer can be composed of two layers: a first layer in contact with the first insulating layer and a second layer located between the first layer and the oxide layer. In this case, if the first layer has hydrogen barrier properties and the second layer has the function of trapping or fixing hydrogen, the hydrogen concentration in the oxide semiconductor layer can be reduced. Alternatively, if the first layer has hydrogen barrier properties and the second layer includes a region with excess oxygen, one or both of oxygen vacancies and impurities in the oxide semiconductor layer can be reduced. Consequently, the electrical characteristics of the transistor can be improved, thereby enhancing the reliability of the transistor.
在本發明的一個實施方式的電晶體中，源極電極與汲極電極位於不同的高度，因此流過半導體層的電流在高度方向上流過。也就可以說，通道長度方向具有高度方向（縱方向）的成分，因此本發明的一個實施方式的電晶體也可以被稱為VFET（Vertical Field Effect Transistor：垂直場效電晶體）、縱向電晶體或縱向通道電晶體等。In a transistor according to one embodiment of the present invention, the source and drain electrodes are located at different heights, so current flowing through the semiconductor layer flows vertically. In other words, the channel length direction has a vertical (vertical) component. Therefore, the transistor according to one embodiment of the present invention may also be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, or a vertical channel transistor.
本發明的一個實施方式的電晶體的源極電極、半導體層及汲極電極可以重疊設置，由此與將半導體層配置為平面狀的所謂的平面型電晶體相比可以大幅度減少佔有面積。In one embodiment of the present invention, the source electrode, semiconductor layer, and drain electrode of the transistor can be stacked, thereby significantly reducing the occupied area compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.
另外，本發明的一個實施方式的電晶體的通道長度可以由第一絕緣層的厚度等控制。因此，可以實現平面型電晶體難以實現的通道長度極短的電晶體。因此，可以實現佔有面積小且通態電流大的電晶體。Furthermore, the channel length of the transistor according to one embodiment of the present invention can be controlled by, for example, the thickness of the first insulating layer. Consequently, a transistor with an extremely short channel length, which is difficult to achieve with planar transistors, can be realized. Consequently, a transistor with a small footprint and high on-state current can be realized.
此外，由於使用氧化物半導體的電晶體的關態電流小，因此例如在用於記憶體裝置時可以長期保持存儲內容。換言之，由於不需要更新工作或更新工作的頻率極低，所以可以充分降低記憶體裝置的功耗。藉由將本發明的一個實施方式的電晶體用於記憶體裝置，可以實現記憶體裝置的高積體化及低功耗化。Furthermore, because transistors using oxide semiconductors have low off-state current, they can retain stored data for a long time when used in memory devices, for example. In other words, because refresh operations are unnecessary or performed at an extremely low frequency, the power consumption of the memory device can be significantly reduced. By using the transistor according to one embodiment of the present invention in a memory device, high integration and low power consumption can be achieved.
＜半導體裝置的結構例子1＞ 參照圖1A至圖16B說明本發明的一個實施方式的半導體裝置的結構。<Semiconductor Device Structure Example 1>The structure of a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 1A to 16B.
圖1A及圖1B是包括電晶體200的半導體裝置的立體圖。圖1B是切掉了圖1A的一部分的立體圖。此外，在圖1A及圖1B中，關於部分組件（層間絕緣層等），以虛線只示出其輪廓。FIG1A and FIG1B are perspective views of a semiconductor device including a transistor 200. FIG1B is a perspective view with a portion of FIG1A cut away. In FIG1A and FIG1B , the outlines of some components (such as interlayer insulating layers) are shown with dashed lines.
在圖1A及圖1B中，以箭頭示出X方向、Y方向及Z方向。注意，在圖1A及圖1B中使用相同的X、Y及Z的符號，但是其中表示的方向並不需要一致。1A and 1B , arrows indicate the X, Y, and Z directions. Note that the same X, Y, and Z symbols are used in FIG1A and FIG1B , but the directions indicated therein are not necessarily the same.
圖2A1是包括電晶體200的半導體裝置的平面圖。圖2A2是示出配置多個電晶體200的例子的平面圖。圖2B是沿著圖2A1的點劃線A1-A2的剖面圖。圖2C是沿著圖2A1的點劃線A3-A4的剖面圖。圖2D是沿著圖2B的點劃線A5-A6的剖面圖。注意，為了明確起見，在圖2A1及圖2A2的平面圖中省略部分組件。有時在後面的平面圖中也省略部分組件。FIG2A1 is a plan view of a semiconductor device including transistor 200. FIG2A2 is a plan view illustrating an example of configuring a plurality of transistors 200. FIG2B is a cross-sectional view taken along dotted line A1-A2 in FIG2A1. FIG2C is a cross-sectional view taken along dotted line A3-A4 in FIG2A1. FIG2D is a cross-sectional view taken along dotted line A5-A6 in FIG2B. Note that for clarity, some components are omitted in the plan views of FIG2A1 and FIG2A2. Some components may also be omitted in subsequent plan views.
另外，圖3A是沿著圖2A1的點劃線A3-A4的剖面圖。圖3B是沿著圖2B的點劃線A5-A6的剖面圖。圖3A及圖3B分別相當於圖2C及圖2D的放大圖的一個例子。3A is a cross-sectional view taken along the dotted line A3-A4 in FIG. 2A1 , and FIG. 3B is a cross-sectional view taken along the dotted line A5-A6 in FIG. FIG. 3A and FIG. 3B are examples of enlarged views of FIG. 2C and FIG. 2D , respectively.
圖1A至圖3B所示的半導體裝置包括基板（未圖示）上的絕緣層210、絕緣層210上的電晶體200以及絕緣層210上的絕緣層280。絕緣層210及絕緣層280被用作層間膜。1A to 3B include an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, and an insulating layer 280 on the insulating layer 210. The insulating layer 210 and the insulating layer 280 function as interlayer films.
[電晶體200] 電晶體200包括導電層220、絕緣層280上的導電層240、氧化物層227、氧化物層227上的氧化物半導體層230、氧化物半導體層230上的絕緣層250以及絕緣層250上的導電層260。絕緣層280位於導電層220上。[Transistor 200]Transistor 200 includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, an oxide layer 227, an oxide semiconductor layer 230 on oxide layer 227, an insulating layer 250 on oxide semiconductor layer 230, and a conductive layer 260 on insulating layer 250. Insulating layer 280 is located on conductive layer 220.
另外，在圖2B及圖2C中示出如下情況的例子：導電層220具有導電層220_1及導電層220_1上的導電層220_2的兩層結構，氧化物半導體層230具有氧化物半導體層230_1及氧化物半導體層230_1上的氧化物半導體層230_2的兩層結構，導電層240具有導電層240_1及導電層240_1上的導電層240_2的兩層結構，導電層260具有導電層260_1及導電層260_1上的導電層260_2的兩層結構。此外，氧化物半導體層230_1對應於上述第一氧化物半導體層，氧化物半導體層230_2對應於上述第二氧化物半導體層。2B and 2C illustrate an example in which the conductive layer 220 has a two-layer structure comprising a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1; the oxide semiconductor layer 230 has a two-layer structure comprising an oxide semiconductor layer 230_1 and an oxide semiconductor layer 230_2 on the oxide semiconductor layer 230_1; the conductive layer 240 has a two-layer structure comprising a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1; and the conductive layer 260 has a two-layer structure comprising a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1. In addition, the oxide semiconductor layer 230_1 corresponds to the first oxide semiconductor layer, and the oxide semiconductor layer 230_2 corresponds to the second oxide semiconductor layer.
在電晶體200中，氧化物半導體層230被用作半導體層，導電層260被用作閘極電極，絕緣層250被用作閘極絕緣層，導電層220被用作源極電極和汲極電極中的一個，導電層240被用作源極電極和汲極電極中的另一個。此外，導電層260具有用作閘極佈線的區域。In transistor 200, oxide semiconductor layer 230 serves as a semiconductor layer, conductive layer 260 serves as a gate electrode, insulating layer 250 serves as a gate insulating layer, conductive layer 220 serves as one of a source electrode and a drain electrode, and conductive layer 240 serves as the other of the source electrode and the drain electrode. Furthermore, conductive layer 260 has a region serving as a gate wiring.
如圖2B及圖2C所示，絕緣層280及導電層240中設置有到達導電層220的開口部290。As shown in FIG. 2B and FIG. 2C , the insulating layer 280 and the conductive layer 240 are provided with openings 290 that reach the conductive layer 220 .
開口部290具有絕緣層280所包括的開口部及導電層240所包括的開口部。換言之，絕緣層280在與導電層220重疊的區域中包括的開口部是開口部290的一部分，導電層240在與導電層220重疊的區域中包括的開口部是開口部290的另一部分。此外，各層的俯視時的開口部290的形狀及大小也可以不同。此外，當開口部290的頂面形狀為圓形時，各層中的開口部既可以是同心圓狀，也可以不是同心圓狀。Opening 290 includes an opening in insulating layer 280 and an opening in conductive layer 240. In other words, the opening in the region where insulating layer 280 overlaps with conductive layer 220 is part of opening 290, while the opening in the region where conductive layer 240 overlaps with conductive layer 220 is another part of opening 290. Furthermore, the shape and size of opening 290 can vary between layers when viewed from above. Furthermore, when the top surface of opening 290 is circular, the openings in each layer can be concentric or non-concentric.
電晶體200的組件的至少一部分配置在開口部290內。明確而言，氧化物層227、氧化物半導體層230、絕緣層250及導電層260各自的至少一部分位於開口部290內。另外，氧化物層227、氧化物半導體層230、絕緣層250及導電層260的配置在開口部290內的部分反映了開口部290的形狀。At least a portion of the components of transistor 200 is disposed within opening 290. Specifically, at least a portion of each of oxide layer 227, oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 is located within opening 290. Furthermore, the portions of oxide layer 227, oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 disposed within opening 290 reflect the shape of opening 290.
氧化物層227覆蓋開口部290的底部及側壁設置。另外，氧化物層227包括反映了開口部290的形狀的凹部。The oxide layer 227 is provided to cover the bottom and sidewalls of the opening 290. In addition, the oxide layer 227 includes a recessed portion reflecting the shape of the opening 290.
氧化物半導體層230覆蓋氧化物層227設置。也就是說，氧化物半導體層230具有在開口部290內夾著氧化物層227對置於絕緣層280的區域。此外，氧化物半導體層230包括反映了氧化物層227所包括的凹部的形狀的凹部。氧化物半導體層230具有位於導電層240上的部分以及在開口部290內位於導電層220上的部分。Oxide semiconductor layer 230 is provided to cover oxide layer 227. Specifically, oxide semiconductor layer 230 has a region facing insulating layer 280 within opening 290, sandwiching oxide layer 227. Furthermore, oxide semiconductor layer 230 includes a recessed portion that mirrors the shape of the recessed portion included in oxide layer 227. Oxide semiconductor layer 230 has a portion located on conductive layer 240 and a portion located on conductive layer 220 within opening 290.
在氧化物半導體層230具有氧化物半導體層230_1及氧化物半導體層230_2的兩層結構的情況下，氧化物半導體層230_1具有在開口部290內夾著氧化物層227對置於絕緣層280的區域。此外，氧化物半導體層230_2覆蓋氧化物半導體層230_1設置。When the oxide semiconductor layer 230 has a two-layer structure of the oxide semiconductor layer 230_1 and the oxide semiconductor layer 230_2, the oxide semiconductor layer 230_1 has a region facing the insulating layer 280 with the oxide layer 227 interposed therebetween within the opening 290. Furthermore, the oxide semiconductor layer 230_2 is provided to cover the oxide semiconductor layer 230_1.
絕緣層250覆蓋氧化物半導體層230設置。另外，絕緣層250在絕緣層280上覆蓋氧化物半導體層230的頂面及側面設置。此外，絕緣層250包括反映了氧化物半導體層230所包括的凹部的形狀的凹部。The insulating layer 250 is provided to cover the oxide semiconductor layer 230. Furthermore, the insulating layer 250 is provided on the insulating layer 280 to cover the top and side surfaces of the oxide semiconductor layer 230. Furthermore, the insulating layer 250 includes a recessed portion that reflects the shape of the recessed portion included in the oxide semiconductor layer 230.
導電層260以嵌入絕緣層250所包括的凹部的至少一部分的方式設置。此外，導電層260具有在開口部290內夾著絕緣層250對置於氧化物半導體層230的區域。The conductive layer 260 is provided so as to be embedded in at least a portion of the recessed portion included in the insulating layer 250. Furthermore, the conductive layer 260 has a region facing the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween within the opening 290.
氧化物半導體層230具有隔著絕緣層250與導電層260重疊的區域。該區域的至少一部分被用作電晶體200的通道形成區域。氧化物半導體層230的導電層220附近的區域和氧化物半導體層230的導電層240附近的區域中的一個被用作源極區域，另一個被用作汲極區域。也就是說，通道形成區域夾在源極區域與汲極區域之間。Oxide semiconductor layer 230 has a region that overlaps with conductive layer 260 via insulating layer 250. At least a portion of this region serves as the channel formation region of transistor 200. One of the regions near conductive layer 220 and the region near conductive layer 240 of oxide semiconductor layer 230 serves as a source region, while the other serves as a drain region. In other words, the channel formation region is sandwiched between the source and drain regions.
氧化物半導體層230設置在開口部290的內部。此外，在電晶體200中，源極電極和汲極電極中的一個（這裡為導電層220）位於下方，源極電極和汲極電極中的另一個（這裡為導電層240）位於上方，因此電流在上下方向上流過。也就是說，沿開口部290的側面形成通道。Oxide semiconductor layer 230 is provided within opening 290. Furthermore, in transistor 200, one of the source and drain electrodes (here, conductive layer 220) is located below, while the other (here, conductive layer 240) is located above. This allows current to flow in a vertical direction. In other words, a channel is formed along the side of opening 290.
電晶體200較佳為在包含通道形成區域的氧化物半導體層230中含有用作半導體的金屬氧化物（以下，也稱為氧化物半導體）。也就可以說，電晶體200為OS電晶體。Transistor 200 preferably contains a metal oxide (hereinafter also referred to as an oxide semiconductor) serving as a semiconductor in oxide semiconductor layer 230 including the channel formation region. In other words, transistor 200 is an OS transistor.
在OS電晶體中，當氧化物半導體的通道形成區域中存在氧空位（VO）及雜質時，電特性容易變動而有時可靠性下降。此外，形成氫進入氧空位中的缺陷（以下有時稱為VOH）而可能會產生成為載子的電子。因此，當在氧化物半導體的通道形成區域中包含氧空位時，OS電晶體容易具有常開啟特性。由此，在氧化物半導體的通道形成區域中，較佳為儘量減少氧空位及雜質。換言之，較佳的是，氧化物半導體中的通道形成區域的載子濃度得到降低，而使其i型化（本質化）或實質上i型化。In OS transistors, the presence of oxygen vacancies (VO ) and impurities in the channel-forming region of an oxide semiconductor can cause fluctuations in electrical characteristics and sometimes reduce reliability. Furthermore, hydrogen incorporation into oxygen vacancies (hereinafter sometimes referred to as VOH ) can create defects, potentially generating electrons that become carriers. Therefore, the presence of oxygen vacancies in the channel-forming region of an oxide semiconductor can easily lead to an OS transistor exhibiting normally-on characteristics. Therefore, it is desirable to minimize oxygen vacancies and impurities in the channel-forming region of an oxide semiconductor. In other words, it is desirable to reduce the carrier concentration in the channel-forming region of an oxide semiconductor, thereby rendering it intrinsically i-type or substantially i-type.
另一方面，OS電晶體的源極區域及汲極區域較佳為如下區域：由於與通道形成區域相比氧空位多、VOH多或者氫、氮或金屬元素等雜質濃度高而載子濃度增加，由此被低電阻化。也就是說，與通道形成區域相比，OS電晶體的源極區域及汲極區域較佳為載子濃度更高且電阻更低的n型區域。On the other hand, the source and drain regions of an OS transistor are preferably regions with lower resistance due to a higher carrier concentration, higher oxygen vacancies, or higher concentrations of impurities such as hydrogen,nitrogen , or metal elements, compared to the channel-forming region. In other words, the source and drain regions of an OS transistor are preferably n-type regions, exhibiting a higher carrier concentration and lower resistance than the channel-forming region.
注意，在氧化物半導體層230中存在的缺陷較多時，形成有起因於該缺陷的能階（也稱為缺陷態）。在對閘極施加負電壓的情況下，可推測為如下：由於該缺陷態導致的費米能階釘紮而能障的增高得到抑制，因此電子容易超過能障，即臨界電壓向負方向漂移或者關態電流增大。Note that when a large number of defects exist in the oxide semiconductor layer 230, energy levels (also called defect states) resulting from these defects are formed. When a negative voltage is applied to the gate, it is speculated that the Fermi level pinning caused by these defect states suppresses the increase in the energy barrier, making it easier for electrons to cross the energy barrier. This results in a negative shift in the critical voltage or an increase in the off-state current.
於是，較佳為在氧化物半導體層230與導電層220或導電層240間設置電阻率高的層。藉由設置該層，維持能障，而可以抑制臨界電壓向負方向漂移或者通態電流降低。因此，電晶體200的臨界電壓向正方向漂移，而可以實現電晶體200的常關閉化。如上所述，可以提高電晶體200的電特性，而可以提高電晶體200的可靠性。作為上述層，例如可以舉出圖2B及圖2C所示的氧化物層227。Therefore, it is preferable to provide a high-resistivity layer between oxide semiconductor layer 230 and conductive layer 220 or conductive layer 240. By providing this layer, an energy barrier is maintained, thereby suppressing a negative shift in the critical voltage or a decrease in the on-state current. As a result, the critical voltage of transistor 200 shifts in the positive direction, making transistor 200 normally off. As described above, the electrical characteristics of transistor 200 can be improved, thereby enhancing the reliability of transistor 200. An example of such a layer is oxide layer 227 shown in Figures 2B and 2C.
例如，氧化物層227的電阻率較佳為比氧化物半導體層230_1的電阻率高。明確而言，氧化物層227較佳為包含鋁、鎵和釔中的至少一個，更佳為包含鎵。例如，氧化物層227較佳為具有鎵的含有率比氧化物半導體層230_1高的區域。藉由採用這種結構，可以提供一種其電阻率比氧化物半導體層230_1高的氧化物層227。For example, the resistivity of oxide layer 227 is preferably higher than that of oxide semiconductor layer 230_1. Specifically, oxide layer 227 preferably contains at least one of aluminum, gallium, and yttrium, and more preferably contains gallium. For example, oxide layer 227 preferably has a region having a higher gallium content than oxide semiconductor layer 230_1. By adopting this structure, oxide layer 227 can be provided with a higher resistivity than oxide semiconductor layer 230_1.
注意，在氧化物層227包含鎵的情況下，可以說氧化物層227包含氧化鎵。另外，在氧化物層227包含鋁的情況下，可以說氧化物層227包含氧化鋁。另外，在氧化物層227包含釔的情況下，可以說氧化物層227包含氧化釔。Note that when the oxide layer 227 includes gallium, the oxide layer 227 can be said to include gallium oxide. Alternatively, when the oxide layer 227 includes aluminum, the oxide layer 227 can be said to include aluminum oxide. Alternatively, when the oxide layer 227 includes yttrium, the oxide layer 227 can be said to include yttrium oxide.
注意，包含鋁、鎵和釔中的至少一個的氧化物層有時具有抑制氧的透過的功能。在與氧化物半導體層230_1接觸的氧化物層227具有抑制氧的透過的功能時，可以抑制從氧化物半導體層230_1釋放氧，而可以抑制在氧化物半導體層230_1中形成氧空位或者在氧化物半導體層230_1中氧空位量增大。由此，可以提高電晶體200的電特性。Note that an oxide layer containing at least one of aluminum, gallium, and yttrium may have the function of inhibiting oxygen permeation. If oxide layer 227, which is in contact with oxide semiconductor layer 230_1, has the function of inhibiting oxygen permeation, oxygen release from oxide semiconductor layer 230_1 can be suppressed, thereby suppressing the formation of oxygen vacancies in oxide semiconductor layer 230_1 or the increase in the amount of oxygen vacancies in oxide semiconductor layer 230_1. As a result, the electrical characteristics of transistor 200 can be improved.
另外，在氧化物層227包含鋁、鎵和釔中的至少一個時，有時在汲極端部形成電子陷阱。因此，臨界電壓向正方向漂移，而可以實現電晶體200的常關閉化。In addition, when oxide layer 227 contains at least one of aluminum, gallium, and yttrium, an electron trap may be formed at the drain end. As a result, the critical voltage shifts toward the positive direction, making transistor 200 normally off.
另一方面，氧化物層227的厚度較佳為小。例如，氧化物層227的厚度較佳為比氧化物半導體層230的厚度小。藉由採用這種結構，可以抑制氧化物半導體層230與導電層220或導電層240間的接觸電阻增高。On the other hand, the thickness of oxide layer 227 is preferably small. For example, the thickness of oxide layer 227 is preferably smaller than the thickness of oxide semiconductor layer 230. By adopting this structure, the increase in contact resistance between oxide semiconductor layer 230 and conductive layer 220 or conductive layer 240 can be suppressed.
明確而言，氧化物層227較佳為具有其厚度為0.1nm以上且3nm以下的區域，更佳為具有其厚度為0.1nm以上且2nm以下的區域。或者，更佳為具有其厚度為0.5nm以上且3nm以下的區域，進一步較佳為具有其厚度為0.5nm以上且2nm以下的區域。Specifically, the oxide layer 227 preferably has a thickness of 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, or more preferably 0.5 nm to 3 nm, and even more preferably 0.5 nm to 2 nm.
注意，只要氧化物層227的電阻率比氧化物半導體層230_1的電阻率高，就對可用於氧化物層227的材料沒有特別的限制。氧化物層227可以使用絕緣材料或半導體材料。例如，氧化物層227可以使用可用於氧化物半導體層230的金屬氧化物材料。例如，氧化物層227可以包含鎵和鋅中的一者或兩者。藉由氧化物層227包含鋅，氧化物層227的結晶性得到提高，而可以提高設置在氧化物層227上的氧化物半導體層230的結晶性。Note that as long as the resistivity of oxide layer 227 is higher than that of oxide semiconductor layer 230_1, there is no particular limitation on the material that can be used for oxide layer 227. Oxide layer 227 can be made of either an insulating material or a semiconductor material. For example, oxide layer 227 can be made of the same metal oxide material that can be used for oxide semiconductor layer 230. For example, oxide layer 227 can contain one or both of gallium and zinc. By including zinc in oxide layer 227, the crystallinity of oxide layer 227 is improved, thereby improving the crystallinity of oxide semiconductor layer 230 disposed on oxide layer 227.
明確而言，作為氧化物層227，可以以單層或疊層使用氧化鎵、氧化鋅、銦鎵氧化物（In-Ga氧化物）、鎵鋅氧化物（Ga-Zn氧化物，也記為GZO）、鋁鋅氧化物（Al-Zn氧化物，也記為AZO）或銦鎵鋅氧化物（In-Ga-Zn氧化物，也記為IGZO）等。在作為氧化物層227使用In-Ga-Zn氧化物的情況下，在氧化物層227中銦的含有率較佳為比鎵的含有率低。作為氧化物層227，明確而言，可以使用In：Ga：Zn=1：3：2[原子數比]或其附近的組成或者In：Ga：Zn=1：3：4[原子數比]或其附近的組成的金屬氧化物。此時，氧化物層227至少包含銦及鎵。Specifically, the oxide layer 227 may be made of gallium oxide, zinc oxide, indium gallium oxide (In-Ga oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), or indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), either as a single layer or as a stacked layer. When an In-Ga-Zn oxide is used as the oxide layer 227, the indium content in the oxide layer 227 is preferably lower than the gallium content. Specifically, the oxide layer 227 may be made of a metal oxide having a composition of In:Ga:Zn in an atomic ratio of 1:3:2 or approximately thereabouts, or a composition of In:Ga:Zn in an atomic ratio of 1:3:4 or approximately thereabouts. At this time, the oxide layer 227 includes at least indium and gallium.
注意，在與氧化物半導體層230接觸地設置包含矽的氧化物層的情況下，有可能該氧化物中的部分矽的混入到氧化物半導體層230而在氧化物半導體層230中形成氧空位。由此，氧化物層227中的矽濃度較佳為低。例如，藉由SIMS得到的氧化物層227中的矽濃度為1.0×1021atoms/cm3以下，較佳為5.0×1020atoms/cm3以下，更佳為1.0×1020atoms/cm3以下。Note that when an oxide layer containing silicon is provided in contact with the oxide semiconductor layer 230, there is a possibility that some of the silicon in the oxide may be mixed into the oxide semiconductor layer 230, forming oxygen vacancies in the oxide semiconductor layer 230. Therefore, the silicon concentration in the oxide layer 227 is preferably low. For example, the silicon concentration in the oxide layer 227 obtained by SIMS is 1.0×1021 atoms/cm3 or less, preferably 5.0×1020 atoms/cm3 or less, and more preferably 1.0×1020 atoms/cm3 or less.
如上所述，藉由在氧化物半導體層230與導電層220或導電層240間設置氧化物層227，可以提高電晶體200的電特性，而可以提高電晶體200的可靠性。As described above, by providing the oxide layer 227 between the oxide semiconductor layer 230 and the conductive layer 220 or the conductive layer 240 , the electrical characteristics of the transistor 200 can be improved, thereby improving the reliability of the transistor 200 .
氧化物半導體層230_1較佳為包含銦（In），更佳的是其In含有率高。例如，氧化物半導體層230_1的In含有率較佳為比氧化物半導體層230_2的In含有率高。藉由作為氧化物半導體層230_1使用In含有率高的金屬氧化物，可以增大通態電流，而可以提高頻率特性。The oxide semiconductor layer 230_1 preferably contains indium (In), and more preferably has a high In content. For example, the In content of the oxide semiconductor layer 230_1 is preferably higher than the In content of the oxide semiconductor layer 230_2. By using a metal oxide with a high In content for the oxide semiconductor layer 230_1, the on-state current can be increased, thereby improving the frequency characteristics.
氧化物半導體層230_1的蝕刻速率較佳為低。例如，氧化物半導體層230_1的一個蝕刻劑的蝕刻速率較佳為比氧化物半導體層230_2的蝕刻速率低。另外，氧化物半導體層230_1的膜密度較佳為高。例如，氧化物半導體層230_1的膜密度較佳為比氧化物半導體層230_2的膜密度高。由此，可以減少氧化物半導體層230_1中的缺陷。因此，可以降低氧化物半導體層230_1中的缺陷態密度，而可以實現可靠性高的電晶體。The etching rate of the oxide semiconductor layer 230_1 is preferably low. For example, the etching rate of an etchant for the oxide semiconductor layer 230_1 is preferably lower than the etching rate of the oxide semiconductor layer 230_2. Furthermore, the film density of the oxide semiconductor layer 230_1 is preferably high. For example, the film density of the oxide semiconductor layer 230_1 is preferably higher than the film density of the oxide semiconductor layer 230_2. This reduces defects in the oxide semiconductor layer 230_1. Consequently, the defect state density in the oxide semiconductor layer 230_1 can be reduced, thereby achieving a highly reliable transistor.
另外，藉由將蝕刻速率低的氧化物膜用於氧化物半導體層230_1，可以抑制氧擴散到氧化物半導體層230_1中。由此，可以抑制過多的氧混入到氧化物半導體層230_1中以及氧化物半導體層230_1中的氧擴散到外方等。因此，可以實現可靠性高的電晶體。Furthermore, by using an oxide film with a low etching rate for oxide semiconductor layer 230_1, oxygen diffusion into oxide semiconductor layer 230_1 can be suppressed. This can prevent excessive oxygen from entering oxide semiconductor layer 230_1 and oxygen from oxide semiconductor layer 230_1 from diffusing outward. Consequently, a highly reliable transistor can be realized.
注意，氧化物半導體層230_1的蝕刻速率也可以高。此外，氧化物半導體層230_1的膜密度也可以低。由此，可以在蝕刻速率高的狀態下進行蝕刻，從而可以縮短氧化物半導體層230_1的蝕刻所需的時間。Note that the etching rate of the oxide semiconductor layer 230_1 can also be high. Furthermore, the film density of the oxide semiconductor layer 230_1 can also be low. Thus, etching can be performed at a high etching rate, thereby shortening the time required to etch the oxide semiconductor layer 230_1.
在對膜密度進行評價時，例如可以利用拉塞福背散射分析（RBS：Rutherford Backscattering Spectrometry）或X射線反射（XRR：X-Ray Reflection）。另外，有時可以使用剖面的透射電子顯微鏡（TEM：Transmission Electron Microscope）影像評價膜密度的不同｡在TEM觀察中，膜密度高則透射電子（TE）影像濃（暗），膜密度低則透射電子（TE）影像談（亮）。注意，即使絕緣層使用相同的材料，在膜密度不同的情況下，有時也可以在剖面的TEM影像中以對比度的不同觀察到它們的邊界。Film density can be evaluated using Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Transmission electron microscopy (TEM) images of cross-sections can also be used to assess differences in film density. In TEM observation, high film density results in darker (dark) transmission electron (TE) images, while low film density results in lighter (brighter) transmission electron (TE) images. Note that even when the insulating layer is made of the same material, differences in film density can sometimes reveal their boundary through differences in contrast in cross-sectional TEM images.
例如，氧化物半導體層230_1較佳為包含氧化銦。另外，氧化物半導體層230_1較佳為使用氧化銦。此外，作為氧化物半導體層230_1，也可以使用In-Zn氧化物。明確而言，可以使用In：Zn=1：1[原子數比]或其附近的組成、In：Zn=2：1[原子數比]或其附近的組成或者In：Zn=4：1[原子數比]或其附近的組成的金屬氧化物。For example, the oxide semiconductor layer 230_1 preferably includes indium oxide. Furthermore, indium oxide is preferably used for the oxide semiconductor layer 230_1. Furthermore, an In-Zn oxide may be used as the oxide semiconductor layer 230_1. Specifically, a metal oxide having an In:Zn atomic ratio of 1:1 or approximately thereabout, an In:Zn atomic ratio of 2:1 or approximately thereabout, or an In:Zn atomic ratio of 4:1 or approximately thereabout may be used.
另外，作為氧化物半導體層230_1也可以使用包含微量的元素M的In-Zn氧化物。注意，元素M為與氧的鍵能高的金屬元素或半金屬元素，例如為與氧的鍵能比銦高的金屬元素或半金屬元素。作為元素M，明確而言，可以舉出鋁、鎵、錫、釔、鈦、釩、鉻、錳、鐵、鈷、鎳、鋯、鉬、鉿、鉭、鎢、鑭、鈰、釹、鎂、鈣、鍶、鋇、硼、矽、鍺及銻等。金屬氧化物所包含的元素M較佳為上述元素中的一種或多種，更佳為選自鋁、鎵、錫和釔中的一種或多種，進一步較佳為選自鎵和錫中的一個以上。Alternatively, an In-Zn oxide containing a trace amount of element M may be used as the oxide semiconductor layer 230_1. Note that element M is a metal element or semimetal element having a high bonding energy with oxygen, for example, a metal element or semimetal element having a higher bonding energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, uranium, tungsten, tungsten, tantalum, arsenic, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and even more preferably one or more selected from gallium and tin.
例如，可以使用In：Ga：Zn=4：0.1：1[原子數比]或其附近的組成、In：Ga：Zn=2：0.1：1[原子數比]或其附近的組成或者In：Ga：Zn=1：0.1：1[原子數比]或其附近的組成的金屬氧化物。此外，例如可以使用In：Sn：Zn=4：0.1：1[原子數比]或其附近的組成、In：Sn：Zn=2：0.1：1[原子數比]或其附近的組成或者In：Sn：Zn=1：0.1：1[原子數比]或其附近的組成的金屬氧化物。For example, metal oxides having a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or a composition close thereto, In:Ga:Zn = 2:0.1:1 [atomic ratio] or a composition close thereto, or In:Ga:Zn = 1:0.1:1 [atomic ratio] or a composition close thereto can be used. Furthermore, metal oxides having a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or a composition close thereto, In:Sn:Zn = 2:0.1:1 [atomic ratio] or a composition close thereto, or In:Sn:Zn = 1:0.1:1 [atomic ratio] or a composition close thereto can be used.
作為氧化物半導體層230_2，較佳為使用與氧化物半導體層230_1相比Ga的含有率高的金屬氧化物。藉由提高Ga的含有率，可以提高氧化物半導體層230_2的氫阻擋性。由此，可以抑制氫從氧化物半導體層230_2的上方擴散到氧化物半導體層230_1。另外，藉由提高Ga的含有率，可以利用形成化物半導體層230之後施加到的熱等減少氧化物半導體層230中的氫或水等雜質。另外，在作為氧化物半導體層230_2使用與氧化物半導體層230_1相比In的含有率低的金屬氧化物時，有時具有同樣的效果。It is preferable to use a metal oxide having a higher Ga content than that of the oxide semiconductor layer 230_1 as the oxide semiconductor layer 230_2. Increasing the Ga content improves the hydrogen barrier properties of the oxide semiconductor layer 230_2. This prevents hydrogen from diffusing from above the oxide semiconductor layer 230_2 into the oxide semiconductor layer 230_1. Furthermore, increasing the Ga content allows the reduction of impurities such as hydrogen and water in the oxide semiconductor layer 230 by heat applied after the oxide semiconductor layer 230 is formed. A similar effect can also be achieved when a metal oxide having a lower In content than that of the oxide semiconductor layer 230_1 is used as the oxide semiconductor layer 230_2.
例如，作為氧化物半導體層230_2，較佳為使用In：Ga：Zn=1：1：1[原子數比]或其附近的組成、In：Ga：Zn=1：3：2[原子數比]或其附近的組成或者In：Ga：Zn=1：3：4[原子數比]或其附近的組成的金屬氧化物。此時，氧化物半導體層230_2包含銦及鎵。For example, the oxide semiconductor layer 230_2 preferably uses a metal oxide having an atomic ratio of In:Ga:Zn = 1:1:1 or a composition thereof, an atomic ratio of In:Ga:Zn = 1:3:2 or a composition thereof, or an atomic ratio of In:Ga:Zn = 1:3:4 or a composition thereof. In this case, the oxide semiconductor layer 230_2 contains indium and gallium.
典型的是，氧化物層227、氧化物半導體層230_1及氧化物半導體層230_2分別可以使用氧化鎵、氧化銦及In：Ga：Zn=1：1：1[原子數比]或其附近的組成的金屬氧化物。另外，氧化物層227、氧化物半導體層230_1及氧化物半導體層230_2的厚度分別為0.5nm以上且1nm以下、5nm及5nm。Typically, oxide layer 227, oxide semiconductor layer 230_1, and oxide semiconductor layer 230_2 can each use gallium oxide, indium oxide, or a metal oxide having a composition of In:Ga:Zn = 1:1:1 (atomic ratio) or a composition close thereto. Furthermore, the thicknesses of oxide layer 227, oxide semiconductor layer 230_1, and oxide semiconductor layer 230_2 are 0.5 nm to 1 nm, 5 nm, and 5 nm, respectively.
注意，在作為氧化物半導體層230_1使用氧化銦、In-Zn氧化物或者包含微量的元素M的In-Zn氧化物的情況下，氧化物層227的導帶底有時位於比氧化物半導體層230_1的導帶底更靠近真空能階一側。另外，藉由提高Ga的含有率，氧化物半導體層230_2的導帶底有時位於比氧化物半導體層230_1的導帶底更靠近真空能階一側。此時，氧化物半導體層230_1夾在其導帶底位於更靠近真空能階一側的氧化物層227和氧化物半導體層230_2間，並主要可被用作電流路徑（通道）。Note that when indium oxide, In-Zn oxide, or In-Zn oxide containing a trace amount of element M is used as oxide semiconductor layer 230_1, the conduction band bottom of oxide layer 227 may be located closer to the vacuum level than the conduction band bottom of oxide semiconductor layer 230_1. Furthermore, by increasing the Ga content, the conduction band bottom of oxide semiconductor layer 230_2 may be located closer to the vacuum level than the conduction band bottom of oxide semiconductor layer 230_1. In this case, oxide semiconductor layer 230_1 is sandwiched between oxide layer 227, whose conduction band bottom is located closer to the vacuum level, and oxide semiconductor layer 230_2, and can be used primarily as a current path (channel).
在氧化物半導體層230_1夾在氧化物層227和氧化物半導體層230_2間時，可以減少在氧化物半導體層230_1的介面及其附近被俘獲的載子。此外，可以使通道遠離絕緣層250的表面，由此可以減少表面散射或介面散射的影響。由此，可以實現通道遠離絕緣層介面的埋入通道型電晶體，從而可以提高場效移動率。When oxide semiconductor layer 230_1 is sandwiched between oxide layer 227 and oxide semiconductor layer 230_2, carriers trapped at and near the interface of oxide semiconductor layer 230_1 can be reduced. Furthermore, the channel can be distanced from the surface of insulating layer 250, thereby reducing the effects of surface scattering and interface scattering. This allows for a buried-channel transistor with a channel distanced from the insulating layer interface, thereby improving field-effect mobility.
在此，圖3C示出氧化物半導體層230及其附近的能帶圖。在圖3C中，縱軸表示能量，橫向方向表示通道形成區域中央部的厚度方向（A5-A6方向）。圖3C示出不將電壓施加到閘極與源極間的狀態下的氧化物層227、氧化物半導體層230_1、氧化物半導體層230_2及絕緣層250各自的價帶頂（VBM：Valence Band Maximum）及導帶底（CBM：Conduction Band Minimum）。此外，在圖3C中，以虛線示出真空能階Vac。Figure 3C shows an energy band diagram for the oxide semiconductor layer 230 and its vicinity. In Figure 3C , the vertical axis represents energy, and the horizontal axis represents the thickness direction (A5-A6 direction) of the central portion of the channel formation region. Figure 3C shows the valence band maximum (VBM) and conduction band minimum (CBM) of the oxide layer 227, oxide semiconductor layer 230_1, oxide semiconductor layer 230_2, and insulating layer 250, respectively, when no voltage is applied between the gate and source. Furthermore, the vacuum level Vac is indicated by a dashed line in Figure 3C .
注意，根據氧化物層227、氧化物半導體層230_1、氧化物半導體層230_2及絕緣層250各自的構成元素及其組成而價帶頂的能量及導帶底的能量變化，參照圖3C的能帶圖主要說明價帶頂的能量的高低關係及導帶底的能量的高低關係。Note that the energy of the valence band top and the energy of the conduction band bottom vary depending on the constituent elements and compositions of the oxide layer 227, the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, and the insulating layer 250. The energy band diagram of FIG3C mainly illustrates the high and low energy relationships of the valence band top and the conduction band bottom.
根據氧化物層227、氧化物半導體層230_1及氧化物半導體層230_2各自的構成元素及其組成，如圖3C所示，電晶體200具有氧化物半導體層230_1夾在其導帶底位於比氧化物半導體層230_1更靠近真空能階一側的氧化物層227和氧化物半導體層230_2間的結構。藉由採用該結構，可以實現埋入通道。也就是說，在具有該結構時，氧化物半導體層230_1中形成有更大電流（在圖3C中將電子表示為載子）流過的路徑。因此，可以實現通態電流的增大或者可靠性的提高等。Based on the constituent elements and compositions of oxide layer 227, oxide semiconductor layer 230_1, and oxide semiconductor layer 230_2, as shown in FIG3C , transistor 200 has a structure in which oxide semiconductor layer 230_1 is sandwiched between oxide layer 227, whose conduction band bottom is closer to the vacuum level than oxide semiconductor layer 230_1, and oxide semiconductor layer 230_2. This structure enables the realization of a buried channel. In other words, with this structure, a path for a larger current (electrons are represented as carriers in FIG3C ) is formed in oxide semiconductor layer 230_1. Consequently, increased on-state current and improved reliability can be achieved.
例如，氧化物層227的導帶底位於比氧化物半導體層230_1的導帶底更靠近真空能階一側，並且氧化物層227與氧化物半導體層230_1的能帶偏移較佳為0.01eV以上且1.0eV以下，更佳為0.01eV以上且0.7eV以下，進一步較佳為0.01eV以上且0.5eV以下。或者，較佳為0.1eV以上且1.0eV以下，更佳為0.1eV以上且0.7eV以下，進一步較佳為0.1eV以上且0.5eV以下。注意，在本說明書等中，第一層與第二層的能帶偏移是指第一層的導帶底與第二層的導帶底的能量差。For example, the conduction band bottom of the oxide layer 227 is located closer to the vacuum level than the conduction band bottom of the oxide semiconductor layer 230_1, and the band offset between the oxide layer 227 and the oxide semiconductor layer 230_1 is preferably 0.01 eV to 1.0 eV, more preferably 0.01 eV to 0.7 eV, and even more preferably 0.01 eV to 0.5 eV. Alternatively, it is preferably 0.1 eV to 1.0 eV, more preferably 0.1 eV to 0.7 eV, and even more preferably 0.1 eV to 0.5 eV. Note that in this specification, etc., the band offset between the first layer and the second layer refers to the energy difference between the conduction band bottom of the first layer and the conduction band bottom of the second layer.
與此同樣，氧化物半導體層230_2的導帶底位於比氧化物半導體層230_1的導帶底更靠近真空能階一側，並且氧化物半導體層230_2與氧化物半導體層230_1的能帶偏移較佳為0.01eV以上且1.0eV以下，更佳為0.01eV以上且0.7eV以下，進一步較佳為0.01eV以上且0.5eV以下。或者，較佳為0.1eV以上且1.0eV以下，更佳為0.1eV以上且0.7eV以下，進一步較佳為0.1eV以上且0.5eV以下。Similarly, the conduction band bottom of the oxide semiconductor layer 230_2 is located closer to the vacuum level than the conduction band bottom of the oxide semiconductor layer 230_1. The band offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is preferably 0.01 eV to 1.0 eV, more preferably 0.01 eV to 0.7 eV, and even more preferably 0.01 eV to 0.5 eV. Alternatively, the band offset is preferably 0.1 eV to 1.0 eV, more preferably 0.1 eV to 0.7 eV, and even more preferably 0.1 eV to 0.5 eV.
在評價金屬氧化物的能帶間隙時，可以利用使用分光光度計的光學評價、光譜橢偏術、光致發光法、X射線光電子能譜法或X射線吸收精細結構（XAFS：X-ray Absorption Fine Structure）。另外，還可以組合多個上述方法來分析。電子親和力或導帶底可以利用作為真空能階與價帶頂的能量差的游離電位以及能帶間隙來求得。在評價游離電位時，例如可以利用紫外光電子能譜（UPS：Ultraviolet Photoelectron Spectroscopy）。To evaluate the band gap of metal oxides, optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS) analysis can be used. Combinations of these methods are also possible. Electron affinity and the conduction band bottom can be determined using the ionization potential, which is the energy difference between the vacuum level and the valence band top, and the band gap. Ultraviolet photoelectron spectroscopy (UPS) can be used, for example, to evaluate the ionization potential.
如圖3A所示，導電層220_2中設置有凹部。換言之，導電層220包括凹部，該凹部的底面相當於導電層220_2的凹部的底面，該凹部的側面相當於導電層220_2的凹部的側面。As shown in FIG3A , a recess is provided in the conductive layer 220_2 . In other words, the conductive layer 220 includes a recess whose bottom surface is equivalent to the bottom surface of the recess of the conductive layer 220_2 , and whose side surfaces are equivalent to the side surfaces of the recess of the conductive layer 220_2 .
開口部290與導電層220_2的凹部重疊。在此，開口部290的底部包括導電層220_2的凹部的底面，開口部290的側壁包括導電層220_2的凹部的側面、絕緣層280的側面及導電層240的側面。The opening 290 overlaps with the recess of the conductive layer 220_2 . Here, the bottom of the opening 290 includes the bottom surface of the recess of the conductive layer 220_2 , and the sidewalls of the opening 290 include the side surfaces of the recess of the conductive layer 220_2 , the side surfaces of the insulating layer 280 , and the side surfaces of the conductive layer 240 .
當導電層220_2在與開口部290重疊的位置上包括凹部時，與不包括該凹部的情況相比，可以在以絕緣層210的頂面為基準時使開口部290內的絕緣層250的底面的高度及導電層260的底面的高度都低於導電層220_2的與絕緣層280接觸的頂面的高度。在此，各面的高度可以以電晶體的被形成面為基準決定。在此，可以以絕緣層210的頂面為基準。用於基準的面不侷限於電晶體的被形成面。例如，也可以以設置有電晶體或半導體裝置的基板的頂面為基準。When conductive layer 220_2 includes a recessed portion at a position overlapping opening 290, the height of the bottom surface of insulating layer 250 within opening 290 and the bottom surface of conductive layer 260 can both be lower than the height of the top surface of conductive layer 220_2 in contact with insulating layer 280, relative to the top surface of insulating layer 210, compared to a case where the recessed portion is not included. The height of each surface can be determined relative to the surface on which the transistor is formed. In this case, the top surface of insulating layer 210 can be used as the reference. The reference surface is not limited to the surface on which the transistor is formed. For example, the top surface of a substrate on which a transistor or semiconductor device is provided can also be used as the reference.
氧化物層227與導電層220_2的凹部的底面及側面以及導電層240_2的頂面接觸。藉由使導電層220_2具有凹部，可以增大氧化物半導體層230與導電層220_2夾著氧化物層227重疊的面積。因此，可以降低氧化物半導體層230與導電層220_2之間的接觸電阻。Oxide layer 227 contacts the bottom and side surfaces of the recess in conductive layer 220_2, as well as the top surface of conductive layer 240_2. By providing the recess in conductive layer 220_2, the area of overlap between oxide semiconductor layer 230 and conductive layer 220_2, with oxide layer 227 interposed between them, can be increased. Consequently, the contact resistance between oxide semiconductor layer 230 and conductive layer 220_2 can be reduced.
圖2B示出在開口部290的外側導電層240的端部、氧化物層227的端部及氧化物半導體層230的端部對齊的結構。導電層240、氧化物層227及氧化物半導體層230可以藉由使用相同的遮罩進行加工來製造。因此，可以減少半導體裝置的製造所需要的遮罩個數，所以是較佳的。注意，本發明不侷限於此。例如，在X方向或Y方向上，氧化物半導體層230的端部、氧化物層227的端部、導電層240_1的端部和導電層240_2的端部中的任一個也可以位於其他的內側或外側。FIG2B shows a structure in which the ends of the conductive layer 240, the ends of the oxide layer 227, and the ends of the oxide semiconductor layer 230 are aligned on the outer side of the opening 290. The conductive layer 240, the oxide layer 227, and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. Therefore, the number of masks required for manufacturing the semiconductor device can be reduced, which is preferable. Note that the present invention is not limited to this. For example, in the X direction or the Y direction, any of the ends of the oxide semiconductor layer 230, the end of the oxide layer 227, the end of the conductive layer 240_1, and the end of the conductive layer 240_2 can be located on the inner side or outer side of the other.
導電層240較佳為不位於絕緣層280所包括的開口部290的內部。也就是說，導電層240較佳為不具有與開口部290內的絕緣層280的側面接觸的區域。藉由採用這種結構，可以在導電層240及絕緣層280中一次形成開口部290。另外，當在開口部290內導電層240的側面及絕緣層280的側面對齊時，可以使設置在開口部290內部的氧化物層227、氧化物半導體層230等的厚度分佈均勻。此外，可以抑制氧化物層227、氧化物半導體層230等因導電層240與絕緣層280的步階等而分離。Conductive layer 240 is preferably not located within opening 290 included in insulating layer 280. In other words, conductive layer 240 preferably does not have any region that contacts the side surfaces of insulating layer 280 within opening 290. This structure allows opening 290 to be formed simultaneously in both conductive layer 240 and insulating layer 280. Furthermore, by aligning the side surfaces of conductive layer 240 and insulating layer 280 within opening 290, the thickness distribution of oxide layer 227, oxide semiconductor layer 230, and the like within opening 290 can be uniform. Furthermore, separation of the oxide layer 227, the oxide semiconductor layer 230, and the like due to a step between the conductive layer 240 and the insulating layer 280 can be suppressed.
如上所述，可以在開口部290內形成通道形成區域、源極區域及汲極區域。因此，與在XY平面上分別設置通道形成區域、源極區域及汲極區域的平面型電晶體相比，可以減小電晶體200的佔有面積。由此，可以實現半導體裝置的高積體化。此外，在將本發明的一個實施方式的半導體裝置用於記憶體裝置時，可以增大單位面積的記憶容量。As described above, the channel formation region, source region, and drain region can be formed within opening 290. Therefore, compared to a planar transistor in which the channel formation region, source region, and drain region are separately arranged on the XY plane, the area occupied by transistor 200 can be reduced. This allows for high integration of semiconductor devices. Furthermore, when a semiconductor device according to an embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.
另外，圖2A2示出將多個電晶體200配置為矩陣狀的例子。明確而言，圖2A2示出在X方向及Y方向上配置4個×4個電晶體的例子。如圖2A2所示，電晶體200設置在X方向上延伸的導電層260與Y方向上延伸的導電層240的交叉部。如圖2A2所示，可以使開口部290的直徑小於導電層240的短邊的寬度及導電層260的短邊的寬度的每一個。如此，可以說電晶體200具有能夠實現高積體化及微型化的結構。Figure 2A2 also shows an example of multiple transistors 200 arranged in a matrix. Specifically, Figure 2A2 illustrates an example of a 4 x 4 array of transistors arranged in the X and Y directions. As shown in Figure 2A2 , transistors 200 are arranged at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in Figure 2A2 , the diameter of opening 290 can be made smaller than both the width of the short side of conductive layer 240 and the width of the short side of conductive layer 260. Thus, transistor 200 has a structure that enables high integration and miniaturization.
如圖3B所示，氧化物層227、氧化物半導體層230、絕緣層250及導電層260設置為同心圓狀。因此，設置在中心的導電層260的側面隔著絕緣層250對置於氧化物半導體層230的側面。換言之，在俯視時氧化物半導體層230的外周整體成為通道形成區域。此時，例如，根據氧化物半導體層230的外周的長度決定電晶體200的通道寬度。也就可以說，根據開口部290的寬度（在開口部290的俯視時的形狀為圓形的情況下，直徑）的大小決定電晶體200的通道寬度。圖3A及圖3B示出開口部290的寬度D，圖3B示出電晶體200的通道寬度W。另外，由於氧化物層227的厚度小，所以可以將通道寬度W看作俯視時的開口部290的輪廓的長度。As shown in FIG3B , oxide layer 227, oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged concentrically. Therefore, the side surfaces of conductive layer 260, located at the center, face the side surfaces of oxide semiconductor layer 230 via insulating layer 250. In other words, the entire periphery of oxide semiconductor layer 230, when viewed from above, serves as the channel formation region. In this case, for example, the length of the periphery of oxide semiconductor layer 230 determines the channel width of transistor 200. In other words, the width of opening 290 (or, if opening 290 is circular in plan view, its diameter) determines the channel width of transistor 200. 3A and 3B show the width D of the opening 290, and FIG. 3B shows the channel width W of the transistor 200. Since the thickness of the oxide layer 227 is small, the channel width W can be regarded as the length of the outline of the opening 290 in a plan view.
藉由增大開口部290的寬度D的大小，可以增大單位面積的通道寬度，從而可以增大通態電流。另一方面，電晶體200的佔有面積，例如為俯視時的電晶體200的面積大致取決於開口部290的寬度。藉由縮小開口部290的寬度D的大小，可以減少電晶體200的佔有面積，而可以實現半導體裝置的高積體化。By increasing the width D of the opening 290, the channel width per unit area can be increased, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200, for example, the area of the transistor 200 when viewed from above, is largely determined by the width of the opening 290. By reducing the width D of the opening 290, the area occupied by the transistor 200 can be reduced, thereby enabling higher integration of semiconductor devices.
開口部290的寬度D有時在深度方向上發生變化。在此，尤其是，作為寬度D採用從剖面看時的導電層240的開口部290一側的兩個側面間的最短距離。換言之，作為開口部290的寬度D使用導電層240中的開口部290的寬度的最小值。另外，也可以將導電層240中的最高位置的開口部290的寬度、最低位置的開口部290的寬度、上述兩個位置的中間點的位置的開口部290的寬度或者上述三個寬度的平均值用作寬度D。在此，示出使用導電層240的開口部290的寬度決定寬度D的例子，但是對寬度D的決定方法沒有特別的限制。例如，作為寬度D，可以使用絕緣層280的開口部290一側的兩個側面間的最短距離。另外，也可以將絕緣層280中的位於最高位置的開口部290的寬度、位於最低位置的開口部290的寬度、述兩個位置的中間點的位置的開口部290的寬度或者這三個寬度的平均值用作寬度D。The width D of the opening 290 may vary in the depth direction. In particular, the shortest distance between the two sides of the opening 290 of the conductive layer 240, as viewed in cross section, is used as the width D of the opening 290. In other words, the minimum value of the width of the opening 290 in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening 290 at the highest position, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these two positions, or the average of these three widths may be used as the width D of the opening 290. While this example illustrates determining width D using the width of opening 290 in conductive layer 240, there are no particular limitations on the method for determining width D. For example, width D can be determined by the shortest distance between the two side surfaces of opening 290 in insulating layer 280. Alternatively, width D can be determined by the width of the highest opening 290 in insulating layer 280, the width of the lowest opening 290, the width of the opening 290 midway between these two positions, or the average of these three widths.
在利用光微影法形成開口部290時，根據光微影法的曝光極限設定開口部290的寬度D。此外，開口部290的寬度D根據設置在開口部290內的氧化物層227、氧化物半導體層230、絕緣層250及導電層260各自的厚度而設定。開口部290的寬度D例如較佳為5nm以上、10nm以上或20nm以上且100nm以下、60nm以下、50nm以下、40nm以下或30nm以下。當在俯視時開口部290為圓形的情況下，開口部290的寬度D相當於開口部290的直徑，通道寬度W可以算出為“D×π”。When forming opening 290 using photolithography, the width D of opening 290 is set based on the exposure limit of the photolithography method. Furthermore, the width D of opening 290 is set based on the thicknesses of oxide layer 227, oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 disposed within opening 290. The width D of opening 290 is preferably, for example, not less than 5 nm, not less than 10 nm, or not less than 20 nm and not more than 100 nm, not more than 60 nm, not more than 50 nm, not more than 40 nm, or not more than 30 nm. When opening 290 is circular in a plan view, the width D of opening 290 is equivalent to the diameter of opening 290, and the channel width W can be calculated as "D × π."
電晶體200的通道長度是源極區域與汲極區域間的距離。換言之，可以說電晶體200的通道長度取決於導電層220上的絕緣層280的厚度。在圖3A中，以虛線的雙箭頭示出電晶體200的通道長度L。注意，由於氧化物層227的厚度小，所以可以將通道長度L看作從剖面看時的氧化物半導體層230夾著氧化物層227對置於導電層220的區域的端部與氧化物半導體層230夾著氧化物層227對置於導電層240的區域的端部間的距離。此時，通道長度L相當於從剖面看時的絕緣層280的開口部290一側的側面的長度。The channel length of transistor 200 is the distance between the source and drain regions. In other words, the channel length of transistor 200 depends on the thickness of insulating layer 280 on conductive layer 220. In FIG3A , the channel length L of transistor 200 is indicated by a dotted double arrow. Note that because oxide layer 227 is thin, channel length L can be considered as the distance between the end of the region of oxide semiconductor layer 230 facing conductive layer 220 with oxide layer 227 sandwiched therebetween, and the end of the region of oxide semiconductor layer 230 facing conductive layer 240 with oxide layer 227 sandwiched therebetween, as viewed in cross section. At this time, the channel length L is equivalent to the length of the side of the opening 290 of the insulating layer 280 when viewed from the cross section.
平面型電晶體的通道長度受到光微影法的曝光極限的限制，因此難以實現進一步的微型化，但是電晶體200的通道長度可以根據絕緣層280的厚度設定。因此，可以將電晶體200的通道長度設定為光微影法的曝光極限以下的非常微細的結構（例如60nm以下、50nm以下、40nm以下、30nm以下、20nm以下或10nm以下且0.1nm以上、1nm以上或5nm以上）。因此，電晶體200的通態電流變大，從而可以提高頻率特性。The channel length of planar transistors is limited by the exposure limits of photolithography, making further miniaturization difficult. However, the channel length of transistor 200 can be set based on the thickness of insulating layer 280. Therefore, the channel length of transistor 200 can be set to a very fine structure below the exposure limit of photolithography (e.g., less than 60 nm, less than 50 nm, less than 40 nm, less than 30 nm, less than 20 nm, or less than 10 nm, and greater than 0.1 nm, greater than 1 nm, or greater than 5 nm). As a result, the on-state current of transistor 200 is increased, thereby improving frequency characteristics.
另外，電晶體200的通道長度取決於導電層220上的絕緣層280的厚度，因此該通道長度不會影響到電晶體200的佔有面積，例如為俯視時的電晶體200的面積。藉由將電晶體200的通道長度例如設為1μm以下、500nm以下或300nm以下，可以提高在形成絕緣層280時或者在將開口部290形成在絕緣層280中時等的產生率及良率等。Furthermore, the channel length of transistor 200 is determined by the thickness of insulating layer 280 on conductive layer 220. Therefore, this channel length does not affect the occupied area of transistor 200, for example, the area of transistor 200 when viewed from above. By setting the channel length of transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, the production rate and yield can be improved when forming insulating layer 280 or when forming opening 290 in insulating layer 280.
如上所述，本發明的一個實施方式的半導體裝置所包括的電晶體的通道長度較佳為0.1nm以上、1nm以上或5nm以上且1μm以下、500nm以下或300nm以下。As described above, the channel length of the transistor included in the semiconductor device according to one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more and 1 μm or less, 500 nm or less, or 300 nm or less.
電晶體200的通道長度L較佳為至少比電晶體200的通道寬度W小。電晶體200的通道長度L較佳為電晶體200的通道寬度W的0.1倍以上且0.99倍以下，更佳為0.5倍以上且0.8倍以下。藉由採用這種結構，可以實現具有良好的電特性及高可靠性的電晶體。The channel length L of transistor 200 is preferably at least smaller than the channel width W of transistor 200. The channel length L of transistor 200 is preferably greater than 0.1 times and less than 0.99 times, and more preferably greater than 0.5 times and less than 0.8 times, the channel width W of transistor 200. By adopting this structure, a transistor with excellent electrical characteristics and high reliability can be realized.
如上所述，藉由以在俯視時具有圓形形狀的方式形成開口部290，氧化物層227、氧化物半導體層230、絕緣層250及導電層260以同心圓狀設置。由此，導電層260與氧化物半導體層230間的距離大致均勻，所以可以對氧化物半導體層230大致均勻地施加閘極電場。As described above, by forming opening 290 to have a circular shape when viewed from above, oxide layer 227, oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged concentrically. This makes the distance between conductive layer 260 and oxide semiconductor layer 230 substantially uniform, allowing a substantially uniform gate electric field to be applied to oxide semiconductor layer 230.
注意，雖然在本實施方式中示出開口部290在俯視時具有圓形形狀的例子，但是本發明不侷限於此。開口部290可以在俯視時例如具有圓形或橢圓形等近似圓形、三角形、四邊形（包括長方形、菱形、正方形）、五邊形或星形多邊形等多邊形或者這些多邊形的角部呈圓形的形狀。另外，多邊形也可以是凹多邊形（至少一個內角超過180度的多邊形）或凸多邊形（內角都是180度以下的多邊形）。如圖2A1等所示，開口部290較佳為在俯視時具有圓形形狀。藉由採用圓形，可以提高形成開口部時的加工精度，可以形成微細尺寸的開口部。在本說明書等中，圓形不侷限於正圓。Note that although the present embodiment shows an example in which the opening portion 290 has a circular shape when viewed from above, the present invention is not limited thereto. The opening portion 290 may have, when viewed from above, a shape such as a circle or an ellipse, a polygon such as a triangle, a quadrilateral (including a rectangle, a rhombus, and a square), a pentagon, or a star-shaped polygon, or a polygon whose corners are rounded. In addition, the polygon may be a concave polygon (a polygon with at least one internal angle exceeding 180 degrees) or a convex polygon (a polygon with internal angles of less than 180 degrees). As shown in FIG. 2A1 and the like, the opening portion 290 preferably has a circular shape when viewed from above. By adopting a circular shape, the processing accuracy when forming the opening portion can be improved, and an opening portion of a fine size can be formed. In this specification and the like, the circular shape is not limited to a perfect circle.
＜半導體裝置的構成材料＞ 以下說明可用於本實施方式的半導體裝置的材料。另外，構成本實施方式的半導體裝置的各層既可具有單層結構又可具有疊層結構。<Materials Constituting the Semiconductor Device>The following describes materials that can be used in the semiconductor device of this embodiment. Furthermore, each layer constituting the semiconductor device of this embodiment may have either a single-layer structure or a stacked-layer structure.
[氧化物半導體層230] 如上所述，氧化物半導體層230具有通道形成區域。氧化物半導體層230還具有源極區域及汲極區域。源極區域及汲極區域是與通道形成區域相比載子濃度高的n型區域（低電阻區域）。氧化物半導體層230也可以具有兩層以上的疊層結構。[Oxide Semiconductor Layer 230]As described above, oxide semiconductor layer 230 includes a channel formation region. It also includes a source region and a drain region. The source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. Oxide semiconductor layer 230 may also have a stacked structure of two or more layers.
對用於氧化物半導體層230的半導體材料的結晶性沒有特別的限制，可以使用非晶半導體、單晶半導體或單晶以外的具有結晶性的半導體（微晶半導體、多晶半導體或其一部分具有晶體區域的半導體）。當使用單晶半導體或具有結晶性的半導體時可以抑制電晶體的特性劣化，所以是較佳的。There are no particular limitations on the crystallinity of the semiconductor material used for the oxide semiconductor layer 230. Amorphous semiconductors, single-crystal semiconductors, or semiconductors other than single-crystal semiconductors (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors partially containing crystalline regions) can be used. Single-crystal semiconductors or crystalline semiconductors are preferred because they can suppress degradation of transistor characteristics.
用作半導體的金屬氧化物的能帶間隙較佳為2.0eV以上，更佳為2.5eV以上。藉由將能帶間隙較寬的金屬氧化物用於氧化物半導體層230，可以減小電晶體200的關態電流。OS電晶體的關態電流小，所以可以充分降低半導體裝置的功耗。此外，OS電晶體的頻率特性高，所以可以使半導體裝置高速工作。The band gap of the metal oxide used as the semiconductor is preferably 2.0 eV or greater, more preferably 2.5 eV or greater. Using a metal oxide with a wide band gap for the oxide semiconductor layer 230 can reduce the off-state current of the transistor 200. The low off-state current of the OS transistor significantly reduces the power consumption of the semiconductor device. Furthermore, the high frequency characteristics of the OS transistor enable high-speed operation of the semiconductor device.
關於可以用作本發明的一個實施方式的電晶體的半導體層的氧化物半導體層，可以參照實施方式2的記載。在此省略其詳細說明。Regarding the oxide semiconductor layer that can be used as the semiconductor layer of the transistor according to one embodiment of the present invention, reference can be made to the description of Embodiment 2. Detailed description thereof will be omitted here.
此外，也可以將在通道形成區域中使用其他半導體材料的電晶體用於本實施方式的半導體裝置。作為該其他半導體材料，例如可以舉出由單個元素構成的半導體或化合物半導體。Furthermore, a transistor using other semiconductor materials in the channel forming region can also be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors composed of a single element or compound semiconductors.
作為可用作半導體材料的由單個元素構成的半導體，例如可以舉出矽及鍺。作為可用作電晶體的半導體材料的矽，可以舉出單晶矽、多晶矽、微晶矽及非晶矽。作為多晶矽，例如可以舉出低溫多晶矽（LTPS：Low Temperature Poly Silicon）。Examples of semiconductors composed of a single element that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as a semiconductor material for transistors include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).
作為可用作半導體材料的化合物半導體，可以舉出碳化矽、矽鍺、砷化鎵、磷化銦、氮化硼及砷化硼等。可用於半導體層的氮化硼較佳為具有非晶結構。可用於半導體層的砷化硼較佳為包含具有立方晶結構的晶體。此外，作為化合物半導體，例如可以舉出有機半導體及氮化物半導體。此外，上述氧化物半導體也是化合物半導體之一。注意，這些半導體材料也可以包含雜質作為摻雜物。Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used in semiconductor layers preferably has an amorphous structure. Boron arsenide that can be used in semiconductor layers preferably includes crystals with a cubic structure. Examples of compound semiconductors include organic semiconductors and nitride semiconductors. Furthermore, the aforementioned oxide semiconductors are also examples of compound semiconductors. Note that these semiconductor materials may also contain impurities as dopants.
另外，本實施方式的半導體裝置也可以使用將用作半導體的層狀物質用於通道形成區域的電晶體。另外，在實施方式5中說明層狀物質的詳細內容。Furthermore, the semiconductor device of this embodiment can also use a transistor in which a layered material serving as a semiconductor is used in the channel formation region. The details of the layered material are described in Embodiment 5.
[絕緣層] 作為半導體裝置所包括的絕緣層（絕緣層210、絕緣層250、絕緣層280等），較佳為使用無機絕緣膜。作為無機絕緣膜，例如可以舉出氧化絕緣膜、氮化絕緣膜、氧氮化絕緣膜及氮氧化絕緣膜。作為氧化絕緣膜，例如可以舉出氧化矽膜、氧化鋁膜、氧化鎂膜、氧化鎵膜、氧化鍺膜、氧化釔膜、氧化鋯膜、氧化鑭膜、氧化釹膜、氧化鉿膜、氧化鉭膜、氧化鈰膜、鎵鋅氧化物膜以及鋁酸鉿膜。作為氮化絕緣膜，例如可以舉出氮化矽膜及氮化鋁膜。作為氧氮化絕緣膜，例如可以舉出氧氮化矽膜、氧氮化鋁膜、氧氮化鎵膜、氧氮化釔膜以及氧氮化鉿膜。作為氮氧化絕緣膜，例如可以舉出氮氧化矽膜及氮氧化鋁膜。此外，作為半導體裝置所包括的絕緣層，也可以使用有機絕緣膜。[Insulating Layer]An inorganic insulating film is preferably used as the insulating layer included in the semiconductor device (insulating layer 210, insulating layer 250, insulating layer 280, etc.). Examples of such inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a tungsten oxide film, a neodymium oxide film, a uranium oxide film, a tungsten oxide film, a tungsten oxide film, a gallium-zinc oxide film, and an uranium-aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, a yttrium oxynitride film, and an uranium oxynitride film. Examples of the nitride oxide insulating film include a silicon oxynitride film and an aluminum oxynitride film. In addition, an organic insulating film can also be used as an insulating layer included in a semiconductor device.
例如，當進行電晶體的微型化及高積體化時，由於閘極絕緣層的薄膜化，有時發生洩漏電流等的問題。藉由作為閘極絕緣層使用相對介電常數高的（high-k）材料，可以在保持物理厚度的同時實現電晶體工作時的低電壓化。此外，可以減少閘極絕緣層的等效氧化物厚度（EOT：Equivalent Oxide Thickness）。另一方面，藉由將相對介電常數低的材料用於用作層間膜的絕緣層，可以減少產生在佈線之間的寄生電容。因此，較佳為根據絕緣層的功能選擇材料。此外，相對介電常數低的材料也是介電強度大的材料。For example, as transistors become increasingly miniaturized and highly integrated, the thinning of the gate insulating layer can sometimes cause problems such as leakage current. Using a high-k material for the gate insulating layer allows for lower transistor operating voltages while maintaining the physical thickness. Furthermore, the gate insulating layer's equivalent oxide thickness (EOT) can be reduced. Conversely, using a low-k material for the insulating layer used as an interlayer film can reduce parasitic capacitance between wiring lines. Therefore, it is best to select the insulating layer material based on its function. In addition, materials with relatively low dielectric constants also have high dielectric strength.
作為相對介電常數高的材料，例如可以舉出氧化鋁、氧化鎵、氧化鉿、氧化鉭、氧化鋯、鉿鋯氧化物、含有鋁及鉿的氧化物、含有鋁及鉿的氧氮化物、含有矽及鉿的氧化物、含有矽及鉿的氧氮化物以及含有矽及鉿的氮化物等。Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, einsteinium oxide, tantalum oxide, zirconium oxide, einsteinium zirconium oxide, oxides containing aluminum and einsteinium, oxynitrides containing aluminum and einsteinium, oxides containing silicon and einsteinium, oxynitrides containing silicon and einsteinium, and nitrides containing silicon and einsteinium.
作為相對介電常數低的材料，例如可以舉出氧化矽、氧氮化矽及氮氧化矽等無機絕緣材料、聚酯、聚烯烴、聚醯胺（尼龍及芳香族聚醯胺等）、聚醯亞胺、聚碳酸酯及丙烯酸樹脂等樹脂。此外，作為上述以外的相對介電常數低的無機絕緣材料，例如可以舉出包含氟的氧化矽、包含碳的氧化矽以及包含碳及氮的氧化矽等。此外，可以舉出具有多孔的氧化矽。此外，這些氧化矽也可以包含氮。Examples of materials with low relative dielectric constants include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride; and resins such as polyesters, polyolefins, polyamides (such as nylon and aromatic polyamides), polyimides, polycarbonates, and acrylic resins. Other examples of inorganic insulating materials with low relative dielectric constants include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Furthermore, porous silicon oxides are also possible. Furthermore, these silicon oxides may contain nitrogen.
此外，作為半導體裝置所包括的絕緣層，也可以使用可具有鐵電性的材料。作為可具有鐵電性的材料，可以舉出氧化鉿、氧化鋯、鉿鋯氧化物等金屬氧化物。此外，作為可具有鐵電性的材料，可以舉出對氧化鉿添加元素J1（在此，元素J1為選自鋯、矽、鋁、釓、釔、鑭和鍶等中的一個或多個）的材料。在此，可以適當地設定鉿的原子個數與元素J1的原子個數之比，例如，可以將鉿的原子個數與元素J1的原子個數之比設定為1：1或其附近。此外，作為可具有鐵電性的材料，可以舉出對氧化鋯添加元素J2（在此，元素J2為選自鉿、矽、鋁、釓、釔、鑭和鍶等中的一個或多個）的材料等。此外，可以適當地設定鋯的原子個數與元素J2的原子個數之比，例如，可以將鋯的原子個數與元素J2的原子個數之比設定為1：1或其附近。此外，作為可具有鐵電性的材料，也可以使用鈦酸鉛（PbTiOX）、鈦酸鋇鍶（BST）、鈦酸鍶、鋯鈦酸鉛（PZT）、鉭酸鍶鉍（SBT）、鐵酸鉍（BFO）或鈦酸鋇等具有鈣鈦礦結構的壓電陶瓷。Furthermore, materials capable of ferroelectricity can be used as the insulating layer included in the semiconductor device. Examples of such materials include metal oxides such as einsteinium oxide, zirconium oxide, and einsteinium zirconium oxide. Another example of a material capable of ferroelectricity is einsteinium oxide doped with an element J1 (wherein element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, yttrium, and strontium). The ratio of the number of einsteinium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or approximately thereabouts. Examples of materials that can exhibit ferroelectricity include materials obtained by adding an element J2 to zirconium oxide (herein, the element J2 is one or more selected from einsteinium, silicon, aluminum, gadolinium, yttrium, ruthenium, and strontium). Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or approximately thereabouts. Alternatively, as materials that can exhibit ferroelectric properties, piezoelectric ceramics with a calcium-titanium structure, such as lead titanium titanate (PbTiOx ), barium strontium titanate (BST), strontium titanate, lead zirconium titanate (PZT), bismuth strontium titanate (SBT), bismuth ferrite (BFO), or barium titanate, can be used.
此外，作為可具有鐵電性的材料，可以舉出包含元素M1、元素M2及氮的金屬氮化物。在此，元素M1為選自鋁、鎵和銦等中的一個或多個。此外，元素M2為選自硼、鈧、釔、鑭、鈰、釹、銪、鈦、鋯、鉿、釩、鈮、鉭和鉻等中的一個或多個。此外，可以適當地設定元素M1與元素M2的原子數比。此外，包含元素M1及氮的金屬氧化物即便不包含元素M2也有時具有鐵電性。此外，作為可具有鐵電性的材料，可以舉出對上述金屬氮化物添加元素M3的材料。注意，元素M3為選自鎂、鈣、鍶、鋅和鎘等中的一個或多個。在此，可以適當地設定元素M1、元素M2與元素M3的原子數比。In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2, and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, and indium. In addition, the element M2 is one or more selected from boron, arsenic, yttrium, arsenic, ruthenium, neodymium, ruthenium, titanium, zirconium, einsteinium, vanadium, niobium, tantalum, and chromium. In addition, the atomic ratio of element M1 to element M2 can be appropriately set. In addition, a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2. In addition, as a material that can have ferroelectricity, a material obtained by adding element M3 to the above-mentioned metal nitride can be cited. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium. Here, the atomic ratio of element M1, element M2, and element M3 can be appropriately set.
此外，作為可具有鐵電性的材料，可以舉出SrTaO2N及BaTaO2N等鈣鈦礦型氧氮化物、κ型氧化鋁的GaFeO3等。In addition, as materials that can have ferroelectric properties, there are calcium-titanate-type oxynitrides such as SrTaO2 N and BaTaO2 N, and GaFeO3 of κ-type alumina.
注意，在上述說明中，雖然示出金屬氧化物及金屬氮化物的例子，但是不侷限於此。例如，也可以使用對上述金屬氧化物添加氮的金屬氧氮化物或者對上述金屬氮化物添加氧的金屬氮氧化物等。Note that although metal oxides and metal nitrides are shown as examples in the above description, the present invention is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal oxynitrides obtained by adding oxygen to the above metal nitrides may also be used.
此外，作為可具有鐵電性的材料，例如，可以使用由選自上述材料中的多個材料構成的混合物或化合物。此外，將在實施方式3中說明的絕緣層130可以具有由選自上述材料中的多個材料構成的疊層結構。注意，上述所列舉的材料等的晶體結構（特性）可能不僅根據沉積條件而且還根據各種製程等而發生變化，由此在本說明書等中，呈現鐵電性的材料不僅被稱為鐵電體，而且還被稱為可具有鐵電性的材料。Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above materials can be used. Furthermore, the insulating layer 130 described in Embodiment 3 can have a stacked structure composed of multiple materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may vary not only depending on deposition conditions but also on various manufacturing processes. Therefore, in this specification, materials exhibiting ferroelectricity are referred to not only as ferroelectrics but also as materials capable of exhibiting ferroelectricity.
包含鉿和鋯中的一者或兩者的金屬氧化物即使被加工為幾nm的薄膜也可具有鐵電性。此外，包含鉿和鋯中的一者或兩者的金屬氧化物即使在其面積微小時也可具有鐵電性。因此，藉由使用包含鉿和鋯中的一者或兩者的金屬氧化物，可以實現半導體裝置的微型化。Metal oxides containing one or both of einsteinium and zirconium exhibit ferroelectricity even when processed into thin films of a few nanometers. Furthermore, metal oxides containing one or both of einsteinium and zirconium exhibit ferroelectricity even when their areas are minute. Therefore, the use of metal oxides containing one or both of einsteinium and zirconium can contribute to the miniaturization of semiconductor devices.
在本說明書等中，形成為層狀的可具有鐵電性的材料有時被稱為鐵電體層、金屬氧化物膜或金屬氮化物膜。此外，在本說明書等中，有時將包括鐵電體層、金屬氧化物膜或金屬氮化物膜的裝置稱為鐵電體器件。In this specification and other documents, a layered material that can exhibit ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, in this specification and other documents, a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.
此外，鐵電性被認為是因外加電場發生包含在鐵電層中的晶體的氧或氮的位移而呈現的。此外，呈現鐵電性被推定為依賴於包含在鐵電層中的晶體的結構。因此，為了使絕緣層呈現鐵電性，絕緣層需要包含晶體。尤其是，絕緣層較佳為具有正交晶系晶體結構的晶體，由此呈現鐵電性。包含在絕緣層中的晶體的晶體結構為選自四方晶系、正交晶系、單斜晶系和六方晶系中的一個或多個即可。此外，絕緣層也可以具有非晶結構。此時，絕緣層也可以具有非晶結構和晶體結構的複合結構。Furthermore, ferroelectricity is believed to be exhibited by displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an applied electric field. Furthermore, the exhibiting of ferroelectricity is presumed to depend on the structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to exhibit ferroelectricity, the insulating layer needs to include crystals. In particular, the insulating layer is preferably a crystal having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the tetragonal, orthorhombic, monoclinic, and hexagonal systems. Furthermore, the insulating layer may also have an amorphous structure. In this case, the insulating layer may also have a composite structure of an amorphous structure and a crystalline structure.
此外，藉由對包含鉿和鋯中的一者或兩者的氧化物添加元素週期表中的第3族元素，該氧化物中的氧空位濃度提高，由此容易形成具有正交晶系晶體結構的晶體。由此，具有正交晶系晶體結構的晶體所存在的比例提高，可以增強剩餘極化，所以是較佳的。另一方面，當第3族元素的添加量過多時，該氧化物的結晶性有可能降低，由此不容易呈現鐵電性。因此，包含鉿和鋯中的一者或兩者的氧化物中的第3族元素的含有率較佳為0.1atomic%以上且10atomic%以下，更佳為0.1atomic%以上且5atomic%以下，進一步較佳為0.1atomic%以上且3atomic%以下。在此，第3族元素的含有率是指層所包含的所有金屬元素的原子個數之和中的第3族元素的原子個數的佔比。第3族元素較佳為選自鈧、鑭和釔中的一個或多個，更佳為鑭和釔中的一者或兩者。Furthermore, by adding a Group 3 element from the Periodic Table of the Elements to an oxide containing one or both of einsteinium and zirconium, the oxygen vacancy concentration in the oxide increases, making it easier to form crystals with an orthorhombic crystal structure. This increases the proportion of crystals with an orthorhombic crystal structure, which can enhance residual polarization and is therefore preferred. On the other hand, when the amount of Group 3 element added is too high, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectric properties. Therefore, the content of the Group 3 element in the oxide containing one or both of einsteinium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the total number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from arsenic, onium, and yttrium, and more preferably one or both of onium and yttrium.
此外，藉由由具有抑制雜質及氧的透過的功能的絕緣層圍繞使用金屬氧化物的電晶體，可以使電晶體的電特性穩定。作為具有抑制雜質及氧的透過的功能的絕緣層，例如可以使用包含選自硼、碳、氮、氧、氟、鎂、鋁、矽、磷、氯、氬、鎵、鍺、釔、鋯、鑭、釹、鉿及鉭中的一個以上的絕緣層的單層或疊層。明確而言，作為具有抑制雜質及氧的透過的功能的絕緣層的材料，可以使用氧化鋁、氧化鎂、氧化鎵、氧化鍺、氧化釔、氧化鋯、氧化鑭、氧化釹、氧化鉿或氧化鉭等金屬氧化物、氮化鋁或氮化矽等氮化物、氮氧化矽等氮氧化物。Furthermore, by surrounding a transistor using a metal oxide with an insulating layer that inhibits the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, a single layer or a stack of insulating layers containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, yttrium, neodymium, yttrium, and tantalum can be used as the insulating layer that inhibits the permeation of impurities and oxygen. Specifically, as the material of the insulating layer having the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lumen oxide, neodymium oxide, einsteinium oxide or tantalum oxide, nitrides such as aluminum nitride or silicon nitride, and nitride oxides such as silicon oxynitride can be used.
明確而言，作為具有抑制水及氫等雜質和氧的透過的功能的絕緣層的材料，例如可以舉出氧化鋁、氧化鎂、氧化鎵、氧化鍺、氧化釔、氧化鋯、氧化鑭、氧化釹、氧化鉿、氧化鉭以及包含鋁及鉿的氧化物（鋁酸鉿）等金屬氧化物。此外，例如可以舉出氮化鋁、氮化鋁鈦及氮化矽等氮化物。此外，例如可以舉出氮氧化矽等金屬氮氧化物。Specifically, examples of materials for the insulating layer that function to inhibit the permeation of impurities such as water and hydrogen, as well as oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, tantalum oxide, neodymium oxide, einsteinium oxide, tantalum oxide, and oxides containing aluminum and einsteinium (einsteinium aluminate). Examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Furthermore, examples include metal oxynitrides such as silicon oxynitride.
此外，如閘極絕緣層等與氧化物半導體層接觸的絕緣層或設置在氧化物半導體層附近的絕緣層較佳為具有包含藉由加熱脫離的氧（以下有時稱為過量氧）的區域。例如，藉由使具有包含過量氧的區域的絕緣層接觸於氧化物半導體層或者位於氧化物半導體層附近，可以減少氧化物半導體層中的氧空位。作為容易形成包含過量氧的區域的絕緣層的材料，可以舉出氧化矽、氧氮化矽或具有多孔的氧化矽等。Furthermore, insulating layers such as gate insulating layers that are in contact with or located near an oxide semiconductor layer preferably have regions containing oxygen that is released by heat (hereinafter sometimes referred to as "excess oxygen"). For example, by placing an insulating layer having a region containing excess oxygen in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials that easily form insulating layers containing regions containing excess oxygen include silicon oxide, silicon oxynitride, and porous silicon oxide.
作為與氧化物半導體層接觸的絕緣層或設置在氧化物半導體層附近的絕緣層，較佳為使用氫阻擋絕緣層。在該絕緣層具有氫阻擋性時，可以抑制氫擴散到氧化物半導體層。A hydrogen-barrier insulating layer is preferably used as the insulating layer in contact with the oxide semiconductor layer or provided near the oxide semiconductor layer. When the insulating layer has hydrogen-barrier properties, it can suppress the diffusion of hydrogen into the oxide semiconductor layer.
作為具有俘獲或固定氫的功能的絕緣層的材料，可以舉出包含鉿的氧化物、包含鎂的氧化物、包含鋁的氧化物、包含鋁及鉿的氧化物（鋁酸鉿）、包含鉿及矽的氧化物（矽酸鉿）等金屬氧化物。此外，這些金屬氧化物還可以包含鋯，例如可以舉出包含鉿及鋯的氧化物等。Examples of materials for the insulating layer capable of capturing or fixing hydrogen include metal oxides such as oxides containing einsteinium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and einsteinium (einsteinium aluminate), and oxides containing einsteinium and silicon (einsteinium silicate). Furthermore, these metal oxides may contain zirconium, for example, oxides containing einsteinium and zirconium.
具有俘獲或固定氫的功能的絕緣層較佳為具有非晶結構。在具有非晶結構的金屬氧化物中部分氧原子具有懸空鍵，因此俘獲或固定氫的能力高。因此，在該絕緣層具有非晶結構時，可以提高俘獲或固定氫的功能。例如，也可以對上述金屬氧化物添加矽來實現非晶結構。例如，較佳為使用包含鉿及矽的氧化物（矽酸鉿）。The insulating layer capable of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides with an amorphous structure, some oxygen atoms have dangling bonds, resulting in a high ability to capture or fix hydrogen. Therefore, an amorphous structure in the insulating layer can enhance the hydrogen-capturing or fixing function. For example, an amorphous structure can be achieved by adding silicon to the metal oxide. For example, an oxide containing einsteinium and silicon (einsteinium silicate) is preferably used.
在上述絕緣層具有非晶結構時，可以抑制晶界的形成。藉由抑制晶界的形成，可以提高該絕緣層的平坦性。由此，可以使絕緣層的厚度分佈均勻，而可以減少厚度極薄的部分，因此可以提高絕緣層的耐壓性。另外，可以使設置在絕緣層上的膜的厚度分佈均勻。此外，藉由抑制上述絕緣層的晶界的形成，可以減少晶界的缺陷態導致的洩漏電流。因此，可以將絕緣層用作洩漏電流少的絕緣膜。When the insulating layer has an amorphous structure, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of the insulating layer can be improved. This allows the thickness of the insulating layer to be uniformly distributed, reducing the number of extremely thin portions, thereby improving the voltage resistance of the insulating layer. Furthermore, the thickness of the film provided on the insulating layer can be uniformly distributed. Furthermore, by suppressing the formation of grain boundaries in the insulating layer, leakage current caused by defects at the grain boundaries can be reduced. Therefore, the insulating layer can be used as an insulating film with low leakage current.
注意，上述絕緣層的一部分有時具有晶體區域和晶界中的一者或兩者。Note that a portion of the insulating layer may have one or both of a crystal region and a grain boundary.
此外，俘獲或固定所對應的物質的功能也可以說是具有所對應的物質不容易擴散的性質。因此，俘獲或固定所對應的物質的功能也可以被換稱為阻擋性。Furthermore, the ability to capture or immobilize a substance can also be described as having the property of preventing that substance from diffusing easily. Therefore, this ability to capture or immobilize a substance can also be referred to as barrier properties.
注意，在本說明書等中，阻擋絕緣層是指具有阻擋性的絕緣層。此外，阻擋性是指不容易擴散對應物質的性質（也被稱為不容易透過對應物質的性質、對應物質的透過性低的性質或者抑制對應物質擴散的功能）。此外，記為對應物質的氫例如是指氫原子、氫分子、水分子及OH-等與氫鍵合的物質等中的至少一個。此外，除非特別敘述，記為對應物質的雜質是指通道形成區域中或半導體層中的雜質，例如是指氫原子、氫分子、水分子、氮原子、氮分子、氧化氮分子（N2O、NO及NO2等）和銅原子等中的至少一個。此外，記為對應物質的氧例如是指氧原子和氧分子等中的至少一個。Note that in this specification, etc., a "blocking insulating layer" refers to an insulating layer having a blocking property. Furthermore, "blocking property" refers to the property of not easily diffusing a corresponding substance (also referred to as the property of not easily allowing the corresponding substance to pass through, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). Furthermore, "hydrogen" referred to as a corresponding substance refers to, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, and hydrogen-bonded substances such asOH- . Furthermore, unless otherwise specified, "impurities" referred to as corresponding substances refer to impurities in the channel formation region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (such asN₂O , NO, andNO₂ ), and copper atoms. Furthermore, oxygen described as a corresponding substance refers to at least one of oxygen atoms and oxygen molecules, for example.
作為氫阻擋絕緣層的材料，可以舉出氧化鋁、氧化鎂、氧化鉿、氧化鎵、氮化矽或氮氧化矽等。Examples of materials for the hydrogen barrier insulating layer include aluminum oxide, magnesium oxide, einsteinium oxide, gallium oxide, silicon nitride, and silicon oxynitride.
作為氧阻擋絕緣層的材料，例如可以舉出包含鋁和鉿中的一者或兩者的氧化物、氧化鎂、氧化鎵、鎵鋅氧化物、氮化矽及氮氧化矽等。此外，作為包含鋁和鉿中的一者或兩者的氧化物，例如可以舉出氧化鋁、氧化鉿、包含鋁及鉿的氧化物（鋁酸鉿）、包含鉿及矽的氧化物（矽酸鉿）等。Examples of materials for the oxygen-blocking insulating layer include oxides containing one or both of aluminum and eum, magnesium oxide, gallium oxide, gallium-zinc oxide, silicon nitride, and silicon oxynitride. Examples of oxides containing one or both of aluminum and eum include aluminum oxide, eum oxide, an oxide containing aluminum and eum (eum aluminate), and an oxide containing eum and silicon (eum silicate).
絕緣層210被用作層間膜，所以較佳為使用上述的相對介電常數低的材料。藉由將相對介電常數低的材料用於層間膜，可以減少產生在佈線之間的寄生電容。Since the insulating layer 210 is used as an interlayer film, it is preferable to use a material with a low relative dielectric constant as mentioned above. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.
絕緣層210較佳為使用氫阻擋絕緣層。在設置在氧化物半導體層230的下方的絕緣層210具有氫阻擋性時，可以抑制氫從電晶體200的下方擴散到氧化物半導體層230。例如，作為絕緣層210，較佳為使用氮化矽膜。A hydrogen-blocking insulating layer is preferably used as the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has hydrogen-blocking properties, hydrogen diffusion from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.
另外，絕緣層210較佳為使用具有俘獲或固定氫的功能的絕緣層。在絕緣層210具有俘獲或固定氫的功能時，氧化物半導體層230中的氫經由導電層220擴散到絕緣層210，而可以使用絕緣層210俘獲或固定該氫。因此，可以降低氧化物半導體層230中的氫濃度。Furthermore, insulating layer 210 preferably has the function of trapping or fixing hydrogen. When insulating layer 210 has this function, hydrogen in oxide semiconductor layer 230 diffuses into insulating layer 210 via conductive layer 220, and insulating layer 210 can trap or fix this hydrogen. Consequently, the hydrogen concentration in oxide semiconductor layer 230 can be reduced.
另外，絕緣層210中的氫或水等雜質的濃度較佳為得到降低。由此，可以抑制氫或水等雜質混入到氧化物半導體層230的通道形成區域。Furthermore, the concentration of impurities such as hydrogen and water in the insulating layer 210 is preferably reduced. This can prevent the infiltration of impurities such as hydrogen and water into the channel formation region of the oxide semiconductor layer 230.
圖3A示出絕緣層210具有單層結構的例子。另外，絕緣層210可以具有兩層以上的疊層結構。例如，絕緣層210可以具有第一絕緣層及第一絕緣層上的第二絕緣層的兩層結構。此時，例如，較佳的是，作為第一絕緣層使用氫阻擋絕緣層，作為第二絕緣層使用具有俘獲或固定氫的功能的絕緣層。明確而言，較佳的是，作為第一絕緣層使用氮化矽膜，作為第二絕緣層使用氧化鉿膜、矽酸鉿膜或氧化鋁膜。FIG3A illustrates an example in which insulating layer 210 has a single-layer structure. Alternatively, insulating layer 210 may have a stacked structure of two or more layers. For example, insulating layer 210 may have a two-layer structure comprising a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a hydrogen-blocking insulating layer as the first insulating layer and an insulating layer capable of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and to use a bismuth oxide film, a bismuth silicate film, or an aluminum oxide film as the second insulating layer.
由於絕緣層280被用作層間膜，所以較佳為使用上述的相對介電常數低的材料。藉由將相對介電常數低的材料用於層間膜，可以減少產生在佈線之間的寄生電容。作為絕緣層280，例如可以使用氧化矽或氧氮化矽。Since insulating layer 280 serves as an interlayer film, it is preferably made of a material with a low relative dielectric constant, as described above. Using a material with a low relative dielectric constant for the interlayer film can reduce parasitic capacitance between traces. For example, silicon oxide or silicon oxynitride can be used for insulating layer 280.
此外，絕緣層280中的氫或水等雜質的濃度較佳為得到降低。由此，可以抑制氫或水等雜質混入氧化物半導體層230的通道形成區域中。Furthermore, the concentration of impurities such as hydrogen and water in the insulating layer 280 is preferably reduced. This can prevent the infiltration of impurities such as hydrogen and water into the channel formation region of the oxide semiconductor layer 230.
例如，具有包含過量氧的區域的絕緣層可以在包含氧的氛圍下藉由濺射法沉積。藉由利用不需要使用包含氫的分子作為沉積氣體的濺射法，可以降低絕緣層280中的氫濃度。如此，藉由利用濺射法沉積構成絕緣層280的至少一部分的層，可以從絕緣層280向氧化物半導體層230的通道形成區域供應氧而可以減少氧空位及VoH。For example, an insulating layer having a region containing excess oxygen can be deposited by sputtering in an atmosphere containing oxygen. By utilizing a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in insulating layer 280 can be reduced. Thus, by sputtering the layer that constitutes at least a portion of insulating layer 280, oxygen can be supplied from insulating layer 280 to the channel formation region of oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.
注意，導電層220上的絕緣層280的厚度影響到電晶體200的通道長度，所以根據電晶體200的通道長度的設計值適當地設定絕緣層280的厚度。Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200 , so the thickness of the insulating layer 280 is appropriately set according to the design value of the channel length of the transistor 200 .
圖3A示出絕緣層280具有單層結構的例子。注意，絕緣層280可以具有兩層以上的疊層結構。例如，如圖4A所示，絕緣層280可以具有絕緣層280_1、絕緣層280_1上的絕緣層280_2以及絕緣層280_2上的絕緣層280_3的三層結構。此時，較佳的是，作為絕緣層280_2使用上述的相對介電常數低的材料，作為絕緣層280_1及絕緣層280_3使用氧阻擋絕緣層。由此，可以抑制導電層220及導電層240的氧化，從而可以抑制高電阻化。FIG3A illustrates an example in which insulating layer 280 has a single-layer structure. Note that insulating layer 280 may have a stacked structure of two or more layers. For example, as shown in FIG4A , insulating layer 280 may have a three-layer structure comprising insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. In this case, it is preferable to use the aforementioned low relative dielectric constant material for insulating layer 280_2, and to use oxygen-blocking insulating layers for insulating layer 280_1 and insulating layer 280_3. This can suppress oxidation of the conductive layer 220 and the conductive layer 240, thereby suppressing an increase in resistance.
例如，較佳的是，作為絕緣層280_1及絕緣層280_3使用氮化矽膜或氧化鋁膜，作為絕緣層280_2使用氧化矽膜。另外，絕緣層280_1及絕緣層280_3都可以具有兩層以上的疊層結構。For example, it is preferable to use a silicon nitride film or an aluminum oxide film as the insulating layer 280_1 and the insulating layer 280_3, and to use a silicon oxide film as the insulating layer 280_2. In addition, the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.
絕緣層250較佳為使用氫阻擋絕緣層。在設置在氧化物半導體層230上的絕緣層250具有氫阻擋性時，可以抑制導電層260中的氫擴散到氧化物半導體層230。例如，氮化矽膜的氫阻擋性高，所以適合用於絕緣層250。A hydrogen-barrier insulating layer is preferably used as insulating layer 250. When insulating layer 250 disposed on oxide semiconductor layer 230 has hydrogen-barrier properties, it can suppress the diffusion of hydrogen in conductive layer 260 into oxide semiconductor layer 230. For example, silicon nitride films have high hydrogen-barrier properties and are therefore suitable for use as insulating layer 250.
另外，絕緣層250與氧化物半導體層230接觸，所以較佳為使用具有俘獲或固定氫的功能的絕緣層。由此，可以進一步高效地俘獲或固定氧化物半導體層230中的氫。因此，可以降低氧化物半導體層230的氫濃度（尤其是，電晶體的通道形成區域中的氫濃度）。因此，藉由減少通道形成區域中的VOH，可以使通道形成區域成為i型或實質上i型。Furthermore, since insulating layer 250 is in contact with oxide semiconductor layer 230, it is preferable to use an insulating layer that has the function of trapping or fixing hydrogen. This allows for more efficient trapping or fixing of hydrogen in oxide semiconductor layer 230. Consequently, the hydrogen concentration in oxide semiconductor layer 230 (particularly in the channel formation region of the transistor) can be reduced. Consequently, by reducingVOH in the channel formation region, the channel formation region can be made i-type or substantially i-type.
另外，絕緣層250較佳為使用具有包含過量氧的區域的絕緣層。由此，可以將氧從絕緣層250供應到氧化物半導體層230，來減少氧化物半導體層230中的氧空位。氧化矽膜或氧氮化矽膜等具有對熱穩定的結構，因此適合用於絕緣層250。Furthermore, insulating layer 250 preferably has a region containing excess oxygen. This allows oxygen to be supplied from insulating layer 250 to oxide semiconductor layer 230, reducing oxygen vacancies in oxide semiconductor layer 230. Silicon oxide films or silicon oxynitride films, for example, have thermally stable structures and are therefore suitable for use as insulating layer 250.
圖3A示出絕緣層250具有單層結構的例子。另外，絕緣層250可以具有兩層以上的疊層結構。此時，絕緣層250較佳為由兩種以上的膜形成。在絕緣層250具有兩種以上的膜時，可以使絕緣層250具有多個功能。作為絕緣層250所具有的功能，例如可以舉出從氧化物半導體層230抽出氫的功能及抑制氫擴散到氧化物半導體層230的功能等。FIG3A illustrates an example in which insulating layer 250 has a single-layer structure. Alternatively, insulating layer 250 may have a stacked structure of two or more layers. In this case, insulating layer 250 is preferably formed from two or more film types. When insulating layer 250 comprises two or more film types, it can have multiple functions. Examples of the functions of insulating layer 250 include extracting hydrogen from oxide semiconductor layer 230 and suppressing the diffusion of hydrogen into oxide semiconductor layer 230.
例如，絕緣層250可以具有第一絕緣層以及第一絕緣層上的第二絕緣層的兩層結構。此時，第一絕緣層與氧化物半導體層230接觸。例如，較佳的是，作為第一絕緣層使用具有俘獲或固定氫的功能的絕緣層，作為第二絕緣層使用氫阻擋絕緣層。藉由採用這種結構，可以降低氧化物半導體層230中的氫濃度，而可以抑制氫擴散到氧化物半導體層230。因此，可以實現可靠性高的電晶體。For example, insulating layer 250 can have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer contacts oxide semiconductor layer 230. For example, it is preferable to use an insulating layer capable of trapping or fixing hydrogen as the first insulating layer, and a hydrogen-blocking insulating layer as the second insulating layer. This structure reduces the hydrogen concentration in oxide semiconductor layer 230 and suppresses hydrogen diffusion into oxide semiconductor layer 230. Consequently, a highly reliable transistor can be achieved.
或者，例如，較佳的是，作為第一絕緣層使用具有包含過量氧的區域的絕緣層，作為第二絕緣層使用氫阻擋絕緣層。或者，例如，較佳的是，作為第一絕緣層使用具有包含過量氧的區域的絕緣層，作為第二絕緣層使用具有俘獲或固定氫的功能的絕緣層。藉由採用這種結構，可以降低氧化物半導體層230中的氧空位量及氫濃度，而可以抑制氫擴散到氧化物半導體層230。因此，可以實現可靠性高的電晶體。Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a hydrogen-blocking insulating layer as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having the function of trapping or fixing hydrogen as the second insulating layer. By adopting this structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, thereby suppressing the diffusion of hydrogen into the oxide semiconductor layer 230. As a result, a highly reliable transistor can be realized.
此外，例如，絕緣層250可以在氧化物半導體層230與第一絕緣層間包括第三絕緣層。換言之，絕緣層250可以具有第三絕緣層、第三絕緣層上的第一絕緣層以及第一絕緣層上的第二絕緣層的三層結構。In addition, for example, the insulating layer 250 may include a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 may have a triple-layer structure of a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.
例如，較佳的是，作為第三絕緣層使用具有包含過量氧的區域的絕緣層或包含相對介電常數低的材料的絕緣層，作為第一絕緣層使用具有俘獲或固定氫的功能的絕緣層，作為第二絕緣層使用具有氫阻擋性及氧阻擋性的絕緣層。第三絕緣層較佳為使用氧化矽膜或氧氮化矽膜。藉由作為與氧化物半導體層230接觸的第三絕緣層使用氧化膜，可以對氧化物半導體層230供應氧。此外，藉由設置第二絕緣層，可以抑制第三絕緣層中的氧擴散到導電層260，而可以抑制導電層260的氧化。此外，可以抑制從第三絕緣層供應到氧化物半導體層230的氧量的減少。For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer made of a material with a relatively low dielectric constant as the third insulating layer, an insulating layer capable of trapping or fixing hydrogen as the first insulating layer, and an insulating layer having both hydrogen and oxygen barrier properties as the second insulating layer. A silicon oxide film or a silicon oxynitride film is preferably used as the third insulating layer. By using an oxide film as the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, by providing the second insulating layer, diffusion of oxygen in the third insulating layer into the conductive layer 260 can be suppressed, thereby suppressing oxidation of the conductive layer 260. Furthermore, a reduction in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.
另外，例如，絕緣層250可以在氧化物半導體層230與第三絕緣層間包括第四絕緣層。換言之，絕緣層250可以具有第四絕緣層、第四絕緣層上的第三絕緣層、第三絕緣層上的第一絕緣層以及第一絕緣層上的第二絕緣層的四層結構。第四絕緣層是絕緣層250所具有的兩層以上的疊層中的與氧化物半導體層230接觸的層。Alternatively, for example, insulating layer 250 may include a fourth insulating layer between oxide semiconductor layer 230 and the third insulating layer. In other words, insulating layer 250 may have a four-layer structure comprising a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer. The fourth insulating layer is the layer in contact with oxide semiconductor layer 230 among the two or more stacked layers of insulating layer 250.
作為第四絕緣層，較佳為使用具有氧阻擋性的絕緣層。注意，第一至第三絕緣層可以採用與上述的用於三層結構的層同樣的結構。第四絕緣層是與氧化物半導體層230及導電層240接觸的層。藉由第四絕緣層具有氧阻擋性，可以抑制氧從氧化物半導體層230脫離。此外，還可以抑制因導電層240的側面被氧化而在該側面上形成氧化膜。因此，可以抑制電晶體200的通態電流下降或者場效移動率下降。As the fourth insulating layer, an insulating layer having oxygen barrier properties is preferably used. Note that the first to third insulating layers can adopt the same structure as the layers used for the three-layer structure described above. The fourth insulating layer is a layer that contacts the oxide semiconductor layer 230 and the conductive layer 240. By having oxygen barrier properties, the fourth insulating layer can suppress the escape of oxygen from the oxide semiconductor layer 230. In addition, the formation of an oxide film on the side surface of the conductive layer 240 due to oxidation can be suppressed. Therefore, a decrease in the on-state current of the transistor 200 or a decrease in the field-effect mobility can be suppressed.
作為第四絕緣層，例如較佳為使用氧化鋁膜。氧化鋁膜具有俘獲或固定氫的功能或氫阻擋性，因此適合用於與氧化物半導體層230接觸的第四絕緣層。明確而言，絕緣層250較佳為具有從氧化物半導體層230一側依次層疊氧化鋁膜、氧化矽膜、氧化鉿膜、氮化矽膜的四層結構。For example, an aluminum oxide film is preferably used as the fourth insulating layer. Aluminum oxide films have the ability to capture or immobilize hydrogen, or possess hydrogen barrier properties, making them suitable for use as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure comprising an aluminum oxide film, a silicon oxide film, a bismuth oxide film, and a silicon nitride film stacked in this order from the side of the oxide semiconductor layer 230.
另外，在作為第四絕緣層使用氧化鋁膜且作為氧化物半導體層230_2使用In-Zn氧化物時，有時可以抑制氫擴散到氧化物半導體層230_1。In addition, when an aluminum oxide film is used as the fourth insulating layer and In—Zn oxide is used as the oxide semiconductor layer 230_2, diffusion of hydrogen into the oxide semiconductor layer 230_1 can sometimes be suppressed.
絕緣層250較佳為薄膜。例如，藉由將絕緣層250的厚度設定為1nm以上且20nm以下，較佳為3nm以上且10nm以下，可以減小電晶體特性之一的次臨界擺幅值（也稱為S值）。注意，S值是指：在次臨界值區域中，在恆定的汲極電壓下使汲極電流變化一個位數時的閘極電壓的變化量。The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to between 1 nm and 20 nm, preferably between 3 nm and 10 nm, the subcritical swing (also known as the S value), a characteristic of the transistor, can be reduced. Note that the S value is the change in gate voltage when the drain current changes by one digit at a constant drain voltage in the subcritical region.
此外，構成絕緣層250的各層的厚度較佳為0.1nm以上且10nm以下，更佳為0.1nm以上且5nm以下，進一步較佳為0.5nm以上且5nm以下，還進一步較佳為1nm以上且小於5nm，更進一步較佳為1nm以上且3nm以下。另外，構成絕緣層250的各層的至少一部分包括具有上述厚度的區域即可。The thickness of each layer constituting insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, even more preferably 0.5 nm to 5 nm, even more preferably 1 nm to less than 5 nm, even more preferably 1 nm to 3 nm. Furthermore, at least a portion of each layer constituting insulating layer 250 may include a region having the aforementioned thickness.
典型地是，第四絕緣層、第三絕緣層、第一絕緣層及第二絕緣層的厚度分別為1nm、2nm、2nm及1nm。藉由採用這種結構，在電晶體被微型化或高積體化的情況下也可以具有良好的電特性。Typically, the thicknesses of the fourth insulating layer, third insulating layer, first insulating layer, and second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. This structure allows for excellent electrical properties even when transistors are miniaturized or highly integrated.
另外，在四層結構的絕緣層250中，也可以不設置第二絕緣層。例如，作為第四絕緣層可以使用氧阻擋絕緣層，作為第三絕緣層可以使用包含相對介電常數低的材料的絕緣層，作為第一絕緣層可以使用具有俘獲或固定氫的功能的絕緣層。明確而言，可以採用從氧化物半導體層230一側依次層疊氧化鋁膜、氧化矽膜、氧化鉿膜的三層結構。Furthermore, the second insulating layer may not be provided in the four-layer insulating layer 250. For example, an oxygen-blocking insulating layer may be used as the fourth insulating layer, an insulating layer composed of a material with a relatively low dielectric constant may be used as the third insulating layer, and an insulating layer capable of trapping or fixing hydrogen may be used as the first insulating layer. Specifically, a three-layer structure may be employed in which an aluminum oxide film, a silicon oxide film, and a cobalt oxide film are stacked in this order from the side of the oxide semiconductor layer 230.
另外，在形成具有多個絕緣膜的疊層結構的絕緣層250時，較佳為進行兩次以上的原子層沉積（ALD：Atomic Layer Deposition）製程。例如，絕緣層250所包括的多個絕緣膜中的兩種以上較佳為利用ALD製程來形成。藉由利用ALD製程形成至少兩種以上的絕緣膜，可以提高絕緣層250的覆蓋性及厚度的均勻性。此外，在利用ALD製程連續形成兩種以上的膜，例如形成兩種以上的絕緣膜時，可以提高生產率。Furthermore, when forming insulating layer 250 having a stacked structure of multiple insulating films, it is preferred to perform two or more atomic layer deposition (ALD) processes. For example, two or more of the multiple insulating films included in insulating layer 250 are preferably formed using an ALD process. Forming at least two or more insulating films using an ALD process improves the coverage and thickness uniformity of insulating layer 250. Furthermore, when forming two or more films sequentially using an ALD process, such as forming two or more insulating films, productivity can be improved.
[導電層] 作為半導體裝置所包括的導電層（導電層220、導電層240、導電層260等），較佳為使用選自鋁、鉻、銅、銀、金、鉑、鋅、鉭、鎳、鈦、鐵、鈷、鉬、鎢、鉿、釩、鈮、錳、鎂、鋯、鈹、銦、釕、銥、鍶和鑭等中的金屬元素、以上述金屬元素為成分的合金或者組合上述金屬元素的合金等。作為以上述金屬元素為成分的合金，也可以使用該合金的氮化物或該合金的氧化物。例如，較佳為使用氮化鉭、氮化鈦、包含鈦和鋁的氮化物、包含鉭和鋁的氮化物、氧化釕、氮化釕、包含鍶和釕的氧化物、包含鑭和鎳的氧化物等。此外，也可以使用以包含磷等雜質元素的多晶矽為代表的導電率高的半導體以及鎳矽化物等矽化物。[Conductive Layer]The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tungsten, nickel, titanium, iron, cobalt, molybdenum, tungsten, tantalum, niobium, manganese, magnesium, zirconium, curium, indium, ruthenium, iridium, strontium, and lumber, an alloy containing these metal elements, or an alloy containing a combination of these metal elements. As alloys containing these metal elements, nitrides or oxides of these alloys may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing ruthenium and nickel are preferably used. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.
此外，包含鉭的氮化物、包含鈦的氮化物、包含鉬的氮化物，包含鎢的氮化物、包含釕的氮化物、包含鉭和鋁的氮化物或包含鈦和鋁的氮化物等包含氮的導電材料、氧化釕、包含鍶和釕的氧化物或包含鑭和鎳的氧化物等包含氧的導電材料、包含鈦、鉭或釕等金屬元素的材料是不容易被氧化的導電材料、具有抑制氧擴散的功能的導電材料或者吸收氧也保持導電性的材料，所以是較佳的。作為包含氧的導電材料，可以舉出包含氧化鎢的銦氧化物、包含氧化鈦的銦氧化物、銦錫氧化物（In-Sn氧化物，也稱為ITO）、包含氧化鈦的銦錫氧化物、包含氧化矽的銦錫氧化物（也稱為ITSO）、銦鋅氧化物（In-Zn氧化物，也稱為IZO（註冊商標））以及包含氧化鎢的銦鋅氧化物等。在本說明書等中，有時將使用包含氧的導電材料沉積的導電膜稱為氧化物導電膜。In addition, conductive materials containing nitrogen, such as nitrides containing tungsten, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tungsten and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing ruthenium and nickel; and materials containing metal elements such as titanium, tungsten, or ruthenium are conductive materials that are not easily oxidized, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen, and are therefore preferred. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In-Sn oxide, also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also known as ITSO), indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.
以鎢、銅或鋁為主要成分的導電材料的導電性高，所以是較佳的。Conductive materials based on tungsten, copper, or aluminum are preferred due to their high electrical conductivity.
此外，也可以層疊多個由上述材料形成的導電層。例如，也可以採用組合包含上述金屬元素的材料和包含氧的導電材料的疊層結構。此外，也可以採用組合包含上述金屬元素的材料和包含氮的導電材料的疊層結構。此外，也可以採用組合包含上述金屬元素的材料、包含氧的導電材料和包含氮的導電材料的疊層結構。Furthermore, multiple conductive layers formed from the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a stacked structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a stacked structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
此外，在將金屬氧化物用於電晶體的通道形成區域的情況下，作為用作閘極電極的導電層較佳為採用組合包含上述金屬元素的材料和包含氧的導電材料的疊層結構。在此情況下，較佳為將包含氧的導電材料設置在通道形成區域一側。藉由將包含氧的導電材料設置在通道形成區域一側，從該導電材料脫離的氧容易被供應到通道形成區域。Furthermore, when a metal oxide is used in the channel-forming region of a transistor, a stacked structure combining a material containing the aforementioned metal element and a conductive material containing oxygen is preferably employed as the conductive layer serving as the gate electrode. In this case, the conductive material containing oxygen is preferably positioned on the channel-forming region side. Positioning the conductive material containing oxygen on the channel-forming region side facilitates the supply of oxygen released from the conductive material to the channel-forming region.
導電層220及導電層240都是與氧化物層227接觸的導電層，所以較佳為使用不容易被氧化的導電材料、即使被氧化也保持低電阻的導電材料、具有導電性的金屬氧化物（也稱為氧化物導電體）或具有抑制氧擴散的功能的導電材料。作為該導電材料例如可以舉出包含氮的導電材料及包含氧的導電材料。由此，可以抑制導電層220及導電層240的導電率下降。Conductive layer 220 and conductive layer 240 are both conductive layers in contact with oxide layer 227. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even when oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that inhibits oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress a decrease in the conductivity of conductive layer 220 and conductive layer 240.
藉由作為導電層220使用包含氧的導電材料，即使導電層220吸收氧也可以保持導電性。同樣地，藉由作為導電層240使用包含氧的導電材料，即使導電層240吸收氧也可以保持導電性。此外，在作為絕緣層210使用氧化鉿等包含氧的絕緣層時，導電層220也可以保持導電性，所以是較佳的。作為導電層220及導電層240，例如較佳為使用ITO、ITSO、In-Zn氧化物等。By using a conductive material containing oxygen for conductive layer 220, conductivity is maintained even if conductive layer 220 absorbs oxygen. Similarly, by using a conductive material containing oxygen for conductive layer 240, conductivity is maintained even if conductive layer 240 absorbs oxygen. Furthermore, using an insulating layer containing oxygen, such as e.g., bismuth oxide, as insulating layer 210 is preferred because conductive layer 220 also maintains conductivity. For example, ITO, ITSO, or In-Zn oxide is preferably used for conductive layer 220 and conductive layer 240.
在導電層220及導電層240都具有疊層結構的情況下，藉由將包含氧的導電材料用於該疊層結構中的與氧化物層227的接觸面積最大的層，可以降低導電層220與氧化物半導體層230間以及導電層240與氧化物半導體層230間的接觸電阻。When both conductive layer 220 and conductive layer 240 have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with oxide layer 227, the contact resistance between conductive layer 220 and oxide semiconductor layer 230 and between conductive layer 240 and oxide semiconductor layer 230 can be reduced.
圖4A示出導電層220_1具有導電層220_11及導電層220_11上的導電層220_12的兩層結構的例子。換言之，圖4A所示的導電層220具有導電層220_11、導電層220_11上的導電層220_12以及導電層220_12上的導電層220_2的三層結構。此時，例如，較佳的是，作為導電層220_11使用不容易被氧化的導電材料或具有抑制氧的擴散的功能的導電材料，作為導電層220_12使用導電性高的材料，作為導電層220_2使用包含氧的導電材料（更佳為氧化物導電體）。明確而言，較佳的是，作為導電層220_11使用氮化鈦，作為導電層220_12使用鎢，作為導電層220_2使用氧化物導電體（例如，ITO、ITSO或In-Zn氧化物）。在此情況下，氮化鈦膜與絕緣層210接觸，氧化物導電膜與氧化物半導體層230接觸。此外，將氧化物導電體用於離氧化物半導體層230的通道形成區域最近的層。與鎢相比，氧化物導電體的與氧化物半導體層230的接觸電阻低，因此可以縮短源極與汲極間的電流路徑，從而可以增大電晶體200的通態電流。藉由採用這種結構，即使導電層220與氧化物層227接觸，也可以保持導電性。此外，在作為絕緣層210使用氧化絕緣層的情況下，可以抑制導電層220因絕緣層210而被過度氧化。此外，藉由作為導電層220_12使用其導電性比氧化物導電體及氮化鈦高的金屬材料（在此為鎢），可以提高導電層220的導電性。FIG4A illustrates an example in which conductive layer 220_1 has a two-layer structure: conductive layer 220_11 and conductive layer 220_12 on conductive layer 220_11. In other words, conductive layer 220 shown in FIG4A has a three-layer structure: conductive layer 220_11, conductive layer 220_12 on conductive layer 220_11, and conductive layer 220_2 on conductive layer 220_12. In this case, for example, it is preferable to use a conductive material that is not easily oxidized or a conductive material that suppresses oxygen diffusion for conductive layer 220_11, a highly conductive material for conductive layer 220_12, and a conductive material containing oxygen (more preferably, an oxide conductor) for conductive layer 220_2. Specifically, it is preferable to use titanium nitride for conductive layer 220_11, tungsten for conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for conductive layer 220_2. In this case, the titanium nitride film contacts insulating layer 210, and the oxide conductive film contacts oxide semiconductor layer 230. Furthermore, the oxide conductor is used for the layer closest to the channel formation region of oxide semiconductor layer 230. Compared to tungsten, the oxide conductor has lower contact resistance with oxide semiconductor layer 230, thereby shortening the current path between the source and drain, thereby increasing the on-state current of transistor 200. By adopting this structure, conductivity can be maintained even when conductive layer 220 contacts oxide layer 227. Furthermore, when an oxide insulating layer is used as insulating layer 210, excessive oxidation of conductive layer 220 by insulating layer 210 can be suppressed. Furthermore, by using a metal material (here, tungsten) with higher conductivity than oxide conductors and titanium nitride as conductive layer 220_12, the conductivity of conductive layer 220 can be improved.
圖3A所示的導電層240具有導電層240_1及導電層240_1上的導電層240_2的兩層結構。此時，例如，較佳的是，作為導電層240_2使用包含氧的導電材料，作為導電層240_1使用與導電層240_2相比導電性高的材料。明確而言，例如，較佳的是，作為導電層240_2使用氧化物導電體（例如，ITO、ITSO或In-Zn氧化物），作為導電層240_1使用鎢。另外，作為導電層240_1，也可以使用釕、氮化鈦或氮化鉭等。在作為主要與氧化物層227接觸的導電層240_2使用氧化物導電體時，可以降低與氧化物半導體層230間的接觸電阻。另外，藉由將與氧化物導電體相比導電性高的材料用於構成導電層240的層，可以提高導電層240的導電性。Conductive layer 240 shown in FIG3A has a two-layer structure: conductive layer 240_1 and conductive layer 240_2 on conductive layer 240_1. For example, it is preferable to use a conductive material containing oxygen for conductive layer 240_2, and to use a material having higher conductivity than conductive layer 240_2 for conductive layer 240_1. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for conductive layer 240_2, and to use tungsten for conductive layer 240_1. Alternatively, materials such as ruthenium, titanium nitride, and tantalum nitride may be used for conductive layer 240_1. When an oxide conductor is used as the conductive layer 240_2 that is mainly in contact with the oxide layer 227, the contact resistance with the oxide semiconductor layer 230 can be reduced. In addition, by using a material having higher conductivity than the oxide conductor for the layer constituting the conductive layer 240, the conductivity of the conductive layer 240 can be improved.
此外，作為導電層240_1也可以使用含氧的導電材料，作為導電層240_2也可以使用其導電性比導電層240_1高的材料。此時，將氧化物導電體用於導電層240中的離氧化物半導體層230的通道形成區域最近的層。因此，可以縮短源極與汲極間的電流路徑，而可以提高電晶體200的通態電流。Alternatively, conductive layer 240_1 may be made of a conductive material containing oxygen, and conductive layer 240_2 may be made of a material with higher conductivity than conductive layer 240_1. In this case, the oxide conductor is used in the layer closest to the channel formation region of oxide semiconductor layer 230 within conductive layer 240. This shortens the current path between the source and drain, thereby increasing the on-state current of transistor 200.
導電層260具有用作閘極佈線的區域。作為導電層260，較佳為使用鎢等導電性高的材料。此外，作為導電層260，較佳為使用不容易被氧化的導電材料或者具有抑制氧擴散的功能的導電材料等。如上所述，作為該導電材料，可以舉出包含氮的導電材料（例如，氮化鈦或氮化鉭等）及包含氧的導電材料（例如，氧化釕等）等。由此，可以抑制導電層260的導電率下降。Conductive layer 260 has a region serving as a gate wiring. A highly conductive material, such as tungsten, is preferably used for conductive layer 260. Furthermore, it is also preferable to use a conductive material that is not easily oxidized or that inhibits oxygen diffusion. As mentioned above, examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of conductive layer 260.
尤其是，作為導電層260較佳為使用包含形成通道的金屬氧化物所包含的金屬元素及氧的導電材料。此外，也可以使用包含上述金屬元素及氮的導電材料（例如，氮化鈦、氮化鉭等）。此外，也可以使用ITO、包含氧化鎢的銦氧化物、包含氧化鎢的銦鋅氧化物、包含氧化鈦的銦氧化物、包含氧化鈦的銦錫氧化物、In-Zn氧化物和ITSO中的一個或多個。此外，也可以使用包含氮的銦鎵鋅氧化物。藉由使用上述材料，有時可以俘獲形成通道的金屬氧化物所包含的氫。或者，有時可以俘獲從外方的絕緣層等混入的氫。In particular, conductive materials containing the metal elements contained in the channel-forming metal oxide and oxygen are preferably used as conductive layer 260. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen (e.g., titanium nitride, tungsten nitride, etc.) may be used. Furthermore, one or more of ITO, indium oxide containing tungsten oxide, indium-zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium-tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. Furthermore, indium-gallium-zinc oxide containing nitrogen may be used. Using these materials may sometimes allow hydrogen contained in the channel-forming metal oxide to be captured. Alternatively, hydrogen intruded from an external insulating layer, etc., may be captured.
圖3A所示的導電層260具有導電層260_1及導電層260_1上的導電層260_2的兩層結構。此時，例如，較佳的是，作為導電層260_1使用氮化鈦膜，作為導電層260_2使用鎢膜。或者，較佳的是，作為導電層260_1使用氮化鉭膜，作為導電層260_2使用銅膜。藉由採用這種結構，可以提高導電層260的導電率。Conductive layer 260 shown in FIG3A has a two-layer structure: conductive layer 260_1 and conductive layer 260_2 on conductive layer 260_1. For example, it is preferable to use a titanium nitride film for conductive layer 260_1 and a tungsten film for conductive layer 260_2. Alternatively, it is preferable to use a tungsten nitride film for conductive layer 260_1 and a copper film for conductive layer 260_2. This structure can improve the conductivity of conductive layer 260.
此外，導電層260也可以具有三層以上的疊層結構。導電層260例如也可以具有氮化鉭膜、氮化鉭膜上的氮化鈦膜及氮化鈦膜上的鎢膜的三層結構。Alternatively, the conductive layer 260 may have a stacked structure of three or more layers. For example, the conductive layer 260 may have a three-layer structure of a tungsten nitride film, a titanium nitride film on the tungsten nitride film, and a tungsten film on the titanium nitride film.
[基板] 作為形成電晶體的基板例如可以使用絕緣體基板、半導體基板或導電體基板。作為絕緣體基板，例如可以舉出玻璃基板、石英基板、藍寶石基板、穩定氧化鋯基板（釔安定氧化鋯基板等）、樹脂基板等。此外，作為半導體基板，例如可以舉出以矽或鍺為材料的半導體基板、或者由碳化矽、矽鍺、砷化鎵、磷化銦、氧化鋅或氧化鎵構成的化合物半導體基板等。並且，還可以舉出在上述半導體基板內部具有絕緣體區域的半導體基板，例如SOI（Silicon On Insulator：絕緣層上覆矽）基板等。作為導電體基板，可以舉出石墨基板、金屬基板、合金基板或導電樹脂基板等。或者，可以舉出包含金屬氮化物的基板、包含金屬氧化物的基板等。此外，還可以舉出設置有導電體或半導體的絕緣體基板、設置有導電體或絕緣體的半導體基板、設置有半導體或絕緣體的導電體基板等。或者，也可以使用在這些基板上設置有元件的基板。作為設置在基板上的元件，可以舉出電容器、電阻器、切換元件、發光元件或記憶元件等。[Substrate]The substrate used to form transistors can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttrium-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having an insulating region within these semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides and metal oxides. Furthermore, examples include insulating substrates provided with conductors or semiconductors, semiconductor substrates provided with conductors or insulators, and conductive substrates provided with semiconductors or insulators. Alternatively, substrates with components provided on these substrates may be used. Components provided on the substrates include capacitors, resistors, switching elements, light-emitting elements, and memory elements.
以上是關於可用於本實施方式的半導體裝置的材料的說明。The above is a description of the materials that can be used for the semiconductor device of this embodiment.
如圖4A所示，本發明的一個實施方式的半導體裝置也可以在電晶體200上包括絕緣層283。明確而言，也可以在導電層260及絕緣層250上設置有絕緣層283。As shown in FIG4A , the semiconductor device according to one embodiment of the present invention may also include an insulating layer 283 on the transistor 200. Specifically, the insulating layer 283 may also be provided on the conductive layer 260 and the insulating layer 250.
作為絕緣層283，較佳為使用氫阻擋絕緣層。藉由採用這種結構，可以抑制氫從電晶體200的上方擴散到氧化物半導體層230。A hydrogen blocking insulating layer is preferably used as the insulating layer 283. By adopting such a structure, hydrogen diffusion from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.
在圖3A所示的電晶體200中，導電層260_1和導電層260_2的兩者位於開口部290內。注意，藉由電晶體200的微型化進展，開口部290的寬度變得越小，越難以將構成導電層260的所有層配置在開口部290中。根據開口部290的寬度以及氧化物層227、氧化物半導體層230、絕緣層250及導電層260_1的各厚度等，有時，導電層260_1設置在開口部290內且導電層260_2設置在與開口部290重疊的位置上（參照圖4B）。In transistor 200 shown in FIG3A , both conductive layer 260_1 and conductive layer 260_2 are located within opening 290. Note that as miniaturization of transistor 200 progresses, the width of opening 290 decreases, making it increasingly difficult to fit all layers constituting conductive layer 260 within opening 290. Depending on the width of opening 290 and the thicknesses of oxide layer 227, oxide semiconductor layer 230, insulating layer 250, and conductive layer 260_1, conductive layer 260_1 may be located within opening 290 while conductive layer 260_2 is located overlapping opening 290 (see FIG4B ).
圖4A示出開口部290內的導電層240的側面與開口部290內的絕緣層280的側面一致（也可以說對齊或大致對齊）的結構，但是本發明不侷限於此。例如，開口部290內的導電層240的側面與開口部290內的絕緣層280的側面也可以不連續。另外，開口部290內的導電層240的側面的傾斜度與開口部290內的絕緣層280的側面的傾斜度也可以互不相同。此時，開口部290的側壁的一部分具有錐形形狀。FIG4A illustrates a structure in which the side surfaces of the conductive layer 240 within the opening 290 are aligned (or aligned or substantially aligned) with the side surfaces of the insulating layer 280 within the opening 290. However, the present invention is not limited to this configuration. For example, the side surfaces of the conductive layer 240 within the opening 290 and the side surfaces of the insulating layer 280 within the opening 290 may not be continuous. Furthermore, the slopes of the side surfaces of the conductive layer 240 within the opening 290 and the insulating layer 280 within the opening 290 may differ. In this case, a portion of the sidewall of the opening 290 has a tapered shape.
圖5A及圖5B示出開口部290的側壁的至少一部分具有錐形形狀的例子。圖5A示出開口部290內的導電層240的側面具有錐形形狀的例子，圖5B示出開口部290內的導電層240的側面以及開口部290內的絕緣層280的側面都具有錐形形狀的例子。Figures 5A and 5B illustrate an example in which at least a portion of the sidewall of opening 290 has a tapered shape. Figure 5A illustrates an example in which the sidewall of conductive layer 240 within opening 290 has a tapered shape, while Figure 5B illustrates an example in which both the sidewall of conductive layer 240 within opening 290 and the sidewall of insulating layer 280 within opening 290 have tapered shapes.
藉由使開口部290的側壁具有錐形形狀，可以提高氧化物層227、氧化物半導體層230、絕緣層250等的覆蓋性，由此可以減少空洞等缺陷。在開口部290的側壁具有錐形形狀時，例如，開口部290內的導電層240的側面的錐角（角θ240）以及開口部290內的絕緣層280的側面的錐角（角θ280）較佳為45度以上且小於90度。明確而言，在該錐角為80度以上且小於90度時，如上所述，可以實現半導體裝置的微型化或高積體化，所以是較佳的。此外，在該錐角為45度以上或50度以上且小於80度、為75度以下、70度以下、65度以下或60度以下時，形成在開口部290內的膜的覆蓋性得到提高，所以是較佳的。By making the sidewalls of opening 290 have a tapered shape, coverage with oxide layer 227, oxide semiconductor layer 230, insulating layer 250, and the like can be improved, thereby reducing defects such as voids. When the sidewalls of opening 290 have a tapered shape, for example, the taper angle (angle θ240) of the side surface of conductive layer 240 within opening 290 and the taper angle (angle θ280) of the side surface of insulating layer 280 within opening 290 are preferably 45 degrees or greater and less than 90 degrees. Specifically, a taper angle of 80 degrees or greater and less than 90 degrees is preferred because, as described above, miniaturization and high integration of semiconductor devices can be achieved. In addition, when the taper angle is greater than 45 degrees, greater than 50 degrees and less than 80 degrees, less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees, the covering property of the film formed in the opening portion 290 is improved, which is preferable.
另外，例如，角θ240較佳為比角θ280小。藉由採用這種結構，氧化物層227及氧化物半導體層230等的對開口部290內的導電層240的側面的覆蓋性得到提高，從而可以減少空洞等缺陷。此外，在絕緣層280具有疊層結構的情況下，開口部290內的各層的側面的傾斜度也可以不同。同樣地，在導電層240具有疊層結構的情況下，開口部290內的各層的側面的傾斜度也可以不同。Furthermore, for example, angle θ240 is preferably smaller than angle θ280. This structure improves the coverage of oxide layer 227 and oxide semiconductor layer 230 with the side surfaces of conductive layer 240 within opening 290, thereby reducing defects such as voids. Furthermore, if insulating layer 280 has a stacked structure, the side surfaces of each layer within opening 290 may have different inclinations. Similarly, if conductive layer 240 has a stacked structure, the side surfaces of each layer within opening 290 may have different inclinations.
另外，如圖6所示，在氧化物半導體層230中，有時導電層240或導電層220的頂面為被形成面的部分的厚度（以下，稱為第一厚度）與開口部290的側壁為被形成面的部分的厚度（以下，稱為第二厚度）的比例不同。例如，在利用濺射法沉積氧化物半導體層230的一部分的情況下，在氧化物半導體層230中，有時第一厚度與第二厚度的比例不同。例如，如圖6所示，有時相對於第一厚度的第二厚度的比例小於1、0.8或0.5。尤其是，有如下傾向：角θ280越接近於90度，氧化物半導體層230中的相對於第一厚度的第二厚度的比例越小。Furthermore, as shown in FIG6 , in oxide semiconductor layer 230, the ratio between the thickness of the portion where the top surface of conductive layer 240 or conductive layer 220 is formed (hereinafter referred to as the first thickness) and the thickness of the portion where the sidewall of opening 290 is formed (hereinafter referred to as the second thickness) may differ. For example, when a portion of oxide semiconductor layer 230 is deposited by sputtering, the ratio of the first thickness to the second thickness may differ in oxide semiconductor layer 230. For example, as shown in FIG6 , the ratio of the second thickness to the first thickness may be less than 1, 0.8, or 0.5. In particular, the closer angle θ280 is to 90 degrees, the smaller the ratio of the second thickness to the first thickness in oxide semiconductor layer 230.
下面，參照圖7A1至圖16B說明其結構的一部分與電晶體200不同的電晶體的結構例子。注意，省略與上述重複的部分的説明，而只對不同之處進行詳細說明。另外，即使組件的位置或形狀不同，只要具有相同的功能，就有時對其附上相同的符號而省略其說明。Below, referring to Figures 7A1 to 16B , an example transistor structure that differs in part from transistor 200 will be described. Note that overlapping descriptions will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of a component differs, as long as it has the same function, it may be assigned the same reference numeral and its description will be omitted.
[電晶體200A] 圖7A1是包括電晶體200A的半導體裝置的平面圖。圖7A2是示出配置多個電晶體200A的例子的平面圖。圖7B是沿著圖7A1的點劃線A1-A2的剖面圖。圖7C是沿著圖7A1的點劃線A3-A4的剖面圖。注意，沿著圖7B的點劃線A5-A6的剖面圖可以參照圖2D。另外，圖8A是圖7C的放大圖。[Transistor 200A]Figure 7A1 is a plan view of a semiconductor device including transistor 200A. Figure 7A2 is a plan view showing an example of configuring multiple transistors 200A. Figure 7B is a cross-sectional view taken along dotted line A1-A2 in Figure 7A1. Figure 7C is a cross-sectional view taken along dotted line A3-A4 in Figure 7A1. Note that the cross-sectional view taken along dotted line A5-A6 in Figure 7B can be referenced to Figure 2D. Figure 8A is an enlarged view of Figure 7C.
圖7A1至圖7C所示的半導體裝置包括基板（未圖示）上的絕緣層210、絕緣層210上的電晶體200A、絕緣層210上的絕緣層280、絕緣層284、絕緣層284上的絕緣層285以及電晶體200A上、絕緣層284上及絕緣層285上的導電層265。絕緣層210、絕緣層280、絕緣層284及絕緣層285被用作層間膜。The semiconductor device shown in Figures 7A1 to 7C includes an insulating layer 210 on a substrate (not shown), a transistor 200A on insulating layer 210, an insulating layer 280 on insulating layer 210, an insulating layer 284, an insulating layer 285 on insulating layer 284, and a conductive layer 265 on transistor 200A, on insulating layer 284, and on insulating layer 285. Insulating layer 210, insulating layer 280, insulating layer 284, and insulating layer 285 serve as interlayer films.
圖7A1至圖7C所示的半導體裝置與圖2A1至圖2D所示的半導體裝置的不同之處在於：前者包括導電層265、絕緣層284及絕緣層285。The semiconductor device shown in FIG. 7A1 to FIG. 7C differs from the semiconductor device shown in FIG. 2A1 to FIG. 2D in that the former includes a conductive layer 265 , an insulating layer 284 , and an insulating layer 285 .
導電層265被用作閘極佈線。導電層265可以使用可用於導電層260的材料。作為導電層265，例如可以使用兼具耐熱性及導電性的鎢或鉬等高熔點材料。此外，還可以使用鋁或銅等低電阻導電材料。藉由使用低電阻導電材料，可以降低佈線電阻。Conductive layer 265 serves as a gate wiring. The same material used for conductive layer 260 can be used for conductive layer 265. For example, high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and electrical conductivity, can be used for conductive layer 265. Alternatively, low-resistance conductive materials such as aluminum or copper can be used. Using low-resistance conductive materials can reduce wiring resistance.
電晶體200A包括導電層220、絕緣層280上的導電層240、氧化物層227、氧化物層227上的氧化物半導體層230、氧化物半導體層230上的絕緣層250以及絕緣層250上的導電層260。導電層265具有與導電層260接觸的區域。另外，也可以將導電層265看作電晶體200A的組件。另外，絕緣層284設置在絕緣層250上。Transistor 200A includes conductive layer 220, conductive layer 240 on insulating layer 280, oxide layer 227, oxide semiconductor layer 230 on oxide layer 227, insulating layer 250 on oxide semiconductor layer 230, and conductive layer 260 on insulating layer 250. Conductive layer 265 has a region in contact with conductive layer 260. Conductive layer 265 can also be considered a component of transistor 200A. Insulating layer 284 is also provided on insulating layer 250.
在電晶體200A中，導電層220至絕緣層250的疊層結構與上述電晶體200同樣，因此省略詳細說明。In transistor 200A, the stacked structure from conductive layer 220 to insulating layer 250 is the same as that of transistor 200 described above, and thus detailed description thereof is omitted.
如圖7B及圖7C所示，絕緣層284位於絕緣層250上。另外，絕緣層284的與開口部290重疊的位置上設置有到達絕緣層250的開口部270。導電層260的至少一部分配置在開口部270內。導電層260在開口部270內與絕緣層250接觸。As shown in Figures 7B and 7C , insulating layer 284 is located on insulating layer 250. Furthermore, opening 270 is provided at a position of insulating layer 284 that overlaps with opening 290, reaching insulating layer 250. At least a portion of conductive layer 260 is disposed within opening 270. Conductive layer 260 is in contact with insulating layer 250 within opening 270.
導電層260以嵌入開口部290及開口部270的方式設置。導電層260在開口部290內具有隔著絕緣層250對置於氧化物半導體層230的部分以及位於開口部270內的部分。The conductive layer 260 is provided so as to be embedded in the opening 290 and the opening 270. The conductive layer 260 has a portion in the opening 290 that faces the oxide semiconductor layer 230 via the insulating layer 250, and a portion located in the opening 270.
圖7B及圖7C示出開口部290內設置有導電層260_1及導電層260_2的兩者的例子。注意，藉由電晶體的微型化的進展，開口部290的寬度及開口部270的寬度變得越小，越難以將構成導電層260的所有層配置在開口部290及開口部270中。例如，有時開口部290內只設置有導電層260_1，且開口部270內設置有導電層260_1及導電層260_2。另外，有時開口部270內只設置有導電層260_1。Figures 7B and 7C illustrate examples in which both conductive layer 260_1 and conductive layer 260_2 are disposed within opening 290. Note that as transistor miniaturization progresses, the widths of opening 290 and opening 270 decrease, making it increasingly difficult to fit all layers comprising conductive layer 260 within opening 290 and opening 270. For example, in some cases, only conductive layer 260_1 may be disposed within opening 290, while both conductive layer 260_1 and conductive layer 260_2 may be disposed within opening 270. Alternatively, in some cases, only conductive layer 260_1 may be disposed within opening 270.
導電層265的不與開口部290重疊的部分主要位於絕緣層285上。因此，導電層265主要隔著絕緣層284及絕緣層285與導電層240重疊。由此，可以增加導電層265與導電層240之間的物理距離，可以減少產生在導電層265與導電層240之間的寄生電容。此外，導電層240與導電層265也可以具有不隔著絕緣層285重疊的部分。The portion of conductive layer 265 that does not overlap with opening 290 is primarily located on insulating layer 285. Therefore, conductive layer 265 primarily overlaps conductive layer 240 via insulating layers 284 and 285. This increases the physical distance between conductive layer 265 and conductive layer 240, reducing parasitic capacitance generated between conductive layer 265 and conductive layer 240. Alternatively, conductive layer 240 and conductive layer 265 may have portions that do not overlap via insulating layer 285.
圖8A示出開口部270的寬度比開口部290的寬度D小的例子。開口部270的寬度越小，導電層240與導電層260的物理距離越大，從而可以減少產生在導電層240與導電層260之間的寄生電容，所以是較佳的。例如，開口部270的寬度較佳為相等於或小於開口部290的寬度。FIG8A illustrates an example in which the width D of opening 270 is smaller than the width D of opening 290. A smaller width of opening 270 increases the physical distance between conductive layer 240 and conductive layer 260, thereby reducing parasitic capacitance generated between conductive layers 240 and 260. For example, the width of opening 270 is preferably equal to or smaller than the width of opening 290.
導電層260的頂面的高度與絕緣層285的頂面的高度較佳為一致或大致一致。導電層265設置在絕緣層285上、絕緣層284上及導電層260上，並與導電層260的頂面接觸。導電層260與導電層265也可以說是彼此連接。The height of the top surface of conductive layer 260 is preferably the same or substantially the same as the height of the top surface of insulating layer 285. Conductive layer 265 is disposed on insulating layer 285, insulating layer 284, and conductive layer 260, and contacts the top surface of conductive layer 260. Conductive layer 260 and conductive layer 265 can also be said to be connected to each other.
也就是說，電晶體200A具有減少產生在源極電極和汲極電極中的另一個與閘極佈線之間的寄生電容的結構。因此，可以提高使用該電晶體的電路的頻率特性。That is, the transistor 200A has a structure that reduces parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring. Therefore, the frequency characteristics of the circuit using this transistor can be improved.
注意，本實施方式示出開口部270的俯視時的形狀為圓形的例子，但本發明不侷限於此。可用於開口部270的形狀與上述可用於開口部290的形狀同樣。Note that, although this embodiment shows an example in which the shape of the opening portion 270 in a plan view is circular, the present invention is not limited thereto. The shape that can be used for the opening portion 270 is the same as the shape that can be used for the opening portion 290 described above.
開口部270的寬度有時在深度方向上發生變化。在此，尤其是作為開口部270的寬度，使用從剖面看時的設置在絕緣層284中的開口部270的寬度的最大值。The width of the opening 270 may vary in the depth direction. In particular, the maximum value of the width of the opening 270 provided in the insulating layer 284 when viewed from a cross section is used as the width of the opening 270.
作為絕緣層284，較佳為使用具有俘獲或固定氫的功能的絕緣層。藉由採用這種結構，可以抑制氫從絕緣層284的上方擴散到氧化物半導體層230，並俘獲或固定包含在氧化物半導體層230中的氫。因此，可以降低氧化物半導體層230的氫濃度。作為絕緣層284，可以使用氧化鋁膜、氧化鉿膜或矽酸鉿膜等。Insulating layer 284 is preferably an insulating layer capable of capturing or fixing hydrogen. This structure suppresses the diffusion of hydrogen from above insulating layer 284 into oxide semiconductor layer 230, and captures or fixes hydrogen contained in oxide semiconductor layer 230. Consequently, the hydrogen concentration in oxide semiconductor layer 230 can be reduced. Examples of insulating layer 284 include aluminum oxide, ferrous oxide, and ferrous silicate films.
此外，作為絕緣層284，可以使用氫阻擋絕緣層。由此，可以抑制氫從絕緣層284的上方擴散到氧化物半導體層230。由於氮化矽膜及氮氧化矽膜都具有從本身釋放的雜質（例如，水及氫）少且氧及氫不容易透過的特徵，所以可以適合用於絕緣層284。Furthermore, a hydrogen-blocking insulating layer can be used as insulating layer 284. This can suppress the diffusion of hydrogen from above insulating layer 284 into oxide semiconductor layer 230. Silicon nitride films and silicon oxynitride films are suitable for insulating layer 284 because they release little impurities (e.g., water and hydrogen) and are less susceptible to oxygen and hydrogen permeation.
在作為絕緣層284使用氮化矽膜的情況下，較佳為藉由濺射法沉積該氮化矽膜。因為濺射法不需要將包含氫的分子用於沉積氣體，所以可以降低絕緣層284的氫濃度。藉由使用濺射法沉積絕緣層284，可以形成密度高的氮化矽膜。When a silicon nitride film is used as insulating layer 284, it is preferably deposited by sputtering. Because sputtering does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulating layer 284 can be reduced. By depositing insulating layer 284 by sputtering, a high-density silicon nitride film can be formed.
此外，作為絕緣層284，也可以採用具有俘獲或固定氫的功能的絕緣層與氫阻擋絕緣層的疊層結構。例如，作為絕緣層284，也可以使用氧化鋁膜和該氧化鋁膜上的氮化矽膜的疊層膜。Alternatively, a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a hydrogen blocking insulating layer may be employed as insulating layer 284. For example, a stacked film of an aluminum oxide film and a silicon nitride film on the aluminum oxide film may be employed as insulating layer 284.
絕緣層285被用作層間膜，因此較佳為使用上述相對介電常數低的材料。例如，絕緣層285較佳為具有氧化矽膜。Since the insulating layer 285 serves as an interlayer film, it is preferably made of a material having a low relative dielectric constant. For example, the insulating layer 285 is preferably a silicon oxide film.
另外，可以將與電晶體200同樣的結構用於電晶體200A。例如，如圖8B所示，絕緣層280可以具有絕緣層280_1、絕緣層280_1上的絕緣層280_2及絕緣層280_2上的絕緣層280_3的三層結構。此外，可以在絕緣層285及導電層265上設置絕緣層283。此外，導電層220_1可以具有導電層220_11及導電層220_11上的導電層220_12的兩層結構。Alternatively, transistor 200A may have the same structure as transistor 200. For example, as shown in FIG8B , insulating layer 280 may have a three-layer structure comprising insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. Furthermore, insulating layer 283 may be provided on insulating layer 285 and conductive layer 265. Furthermore, conductive layer 220_1 may have a two-layer structure comprising conductive layer 220_11 and conductive layer 220_12 on conductive layer 220_11.
[電晶體200B] 圖9A1是包括電晶體200B的半導體裝置的平面圖。圖9A2是示出配置有多個電晶體200B的例子的平面圖。圖9B是沿著圖9A1的點劃線A1-A2的剖面圖。圖9C是沿著圖9A1的點劃線A3-A4的剖面圖。圖9D是沿著圖9B的點劃線A5-A6的剖面圖。圖9D也可以說是包括絕緣層280的XY平面的剖面圖。[Transistor 200B]Figure 9A1 is a plan view of a semiconductor device including transistor 200B. Figure 9A2 is a plan view showing an example of a configuration in which multiple transistors 200B are arranged. Figure 9B is a cross-sectional view taken along dotted line A1-A2 in Figure 9A1. Figure 9C is a cross-sectional view taken along dotted line A3-A4 in Figure 9A1. Figure 9D is a cross-sectional view taken along dotted line A5-A6 in Figure 9B. Figure 9D can also be considered a cross-sectional view taken along the XY plane including insulating layer 280.
此外，圖10A及圖10B分別是圖9C的放大圖及圖9D的放大圖。此外，圖11A及圖11B都是沿著圖9A1的點劃線A3-A4的剖面圖。圖11A及圖11B相當於圖9C的放大圖的一個例子，並更詳細地示出各層的結構例子。Figures 10A and 10B are enlarged views of Figures 9C and 9D, respectively. Figures 11A and 11B are cross-sectional views taken along dotted line A3-A4 in Figure 9A1. Figures 11A and 11B are examples of the enlarged view of Figure 9C and show a more detailed structural example of each layer.
圖9A1至圖9D所示的半導體裝置包括基板（未圖示）上的絕緣層210、絕緣層210上的電晶體200B以及絕緣層210上的絕緣層280。The semiconductor device shown in FIG. 9A1 to FIG. 9D includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210 , and an insulating layer 280 on the insulating layer 210 .
電晶體200B包括導電層220、絕緣層280上的導電層240、絕緣層225、氧化物層227、氧化物層227上的氧化物半導體層230、氧化物半導體層230上的絕緣層250以及絕緣層250上的導電層260。Transistor 200B includes a conductive layer 220 , a conductive layer 240 on an insulating layer 280 , an insulating layer 225 , an oxide layer 227 , an oxide semiconductor layer 230 on the oxide layer 227 , an insulating layer 250 on the oxide semiconductor layer 230 , and a conductive layer 260 on the insulating layer 250 .
圖9A1至圖9D所示的電晶體200B與圖2A1至圖2D所示的電晶體200的不同之處在於：前者包括絕緣層225。The transistor 200B shown in FIG. 9A1 to FIG. 9D differs from the transistor 200 shown in FIG. 2A1 to FIG. 2D in that the former includes an insulating layer 225.
如圖9D所示，電晶體200B具有在俯視時絕緣層280與氧化物層227間配置有絕緣層225的結構。As shown in FIG9D , the transistor 200B has a structure in which an insulating layer 225 is disposed between the insulating layer 280 and the oxide layer 227 in a plan view.
絕緣層225以沿著開口部290的側壁的至少一部分的方式設置。絕緣層225至少具有位於氧化物半導體層230與絕緣層280間的區域。絕緣層225可以被稱為側壁、側壁絕緣層或側壁保護層等。The insulating layer 225 is provided along at least a portion of the sidewall of the opening 290. The insulating layer 225 has at least a region between the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 225 may be referred to as a sidewall, a sidewall insulating layer, or a sidewall protective layer.
如上所述，較佳為在氧化物半導體的通道形成區域中儘量減少氧空位及雜質。尤其是，較佳為在氧化物半導體的通道形成區域中儘量減少氫。As described above, it is preferable to minimize oxygen vacancies and impurities in the channel formation region of an oxide semiconductor. In particular, it is preferable to minimize hydrogen in the channel formation region of an oxide semiconductor.
於是，設置在氧化物半導體層230的外側的絕緣層225較佳為使用氫阻擋絕緣層。由此，可以抑制氫擴散到氧化物半導體層230中，而可以提高電晶體200的可靠性。例如，作為絕緣層225，較佳為使用氮化矽膜、氮氧化矽膜或氧化鋁膜，更佳為使用氮化矽膜。Therefore, a hydrogen-blocking insulating layer is preferably used as the insulating layer 225 disposed outside the oxide semiconductor layer 230. This can suppress the diffusion of hydrogen into the oxide semiconductor layer 230, thereby improving the reliability of the transistor 200. For example, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film is preferably used as the insulating layer 225, and a silicon nitride film is more preferably used.
注意，氮化矽膜具有氧阻擋性。由此，藉由將氮化矽膜用於絕緣層225，可以抑制氧從氧化物半導體層230抽出而氧空位形成在氧化物半導體層230中。另外，藉由將氮化矽膜用於絕緣層225，可以防止過多的氧供應到氧化物半導體層230。由此，可以防止氧化物半導體層230的通道形成區域成為氧過剩的狀態，因此可以實現電晶體200B的可靠性的提高。另外，有時，絕緣層225與開口部290中的導電層240的側面接觸。此時，藉由將氮化矽膜用於絕緣層225，可以抑制由於開口部290中的導電層240的側面被氧化而氧化膜形成在該側面上。Note that silicon nitride films have oxygen barrier properties. Therefore, using a silicon nitride film for insulating layer 225 can suppress the extraction of oxygen from oxide semiconductor layer 230 and the formation of oxygen vacancies in oxide semiconductor layer 230. Furthermore, using a silicon nitride film for insulating layer 225 can prevent excessive oxygen from being supplied to oxide semiconductor layer 230. This prevents the channel formation region of oxide semiconductor layer 230 from becoming oxygen-excessive, thereby improving the reliability of transistor 200B. Furthermore, insulating layer 225 may sometimes contact the side surface of conductive layer 240 within opening 290. At this time, by using a silicon nitride film for the insulating layer 225, it is possible to suppress the formation of an oxide film on the side surface of the conductive layer 240 in the opening 290 due to oxidation of the side surface.
絕緣層225所包括的氮化矽膜較佳為利用PEALD法形成。由此，可以提高絕緣層225對開口部290的側壁的覆蓋性，從而可以形成厚度均勻的絕緣層225。The silicon nitride film included in the insulating layer 225 is preferably formed using a PEALD method. This can improve the coverage of the insulating layer 225 on the sidewalls of the opening 290, thereby forming the insulating layer 225 with a uniform thickness.
另外，絕緣層225也可以使用上述可具有鐵電性的材料。In addition, the insulating layer 225 may also be made of the aforementioned ferroelectric material.
如圖9B等所示，導電層220_2包括第一凹部及位於第一凹部的外側的第二凹部。第一凹部的深度比第二凹部的深度深。換言之，第一凹部的底面位於第二凹部的底面的下方（絕緣層210一側）。在形成開口部290時，在導電層220_2中設置第二凹部，然後在對絕緣層225進行加工時在導電層220_2中設置第一凹部。因此，在圖9B等中，第二凹部的側面與開口部290中的絕緣層280的側面對齊，第一凹部的側面與絕緣層225的氧化物層227一側的面對齊。以下，有時將第一凹部和第二凹部統稱為凹部。As shown in FIG9B and other figures, conductive layer 220_2 includes a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located below the bottom surface of the second recess (on the insulating layer 210 side). The second recess is provided in conductive layer 220_2 when opening 290 is formed, and the first recess is then provided in conductive layer 220_2 when insulating layer 225 is processed. Therefore, in FIG9B and other figures, the side surface of the second recess is aligned with the side surface of insulating layer 280 in opening 290, and the side surface of the first recess is aligned with the side surface of insulating layer 225 on the oxide layer 227 side. Hereinafter, the first recess and the second recess may be collectively referred to as a recess.
在圖9B等中，絕緣層225與導電層220的凹部（明確而言，第二凹部）的底面及側面接觸，並在開口部290中與絕緣層280的側面、導電層240_1的側面及導電層240_2的側面接觸。氧化物層227與導電層220的凹部（明確而言，第一凹部）的底面及側面、絕緣層225以及導電層240_2的頂面接觸。氧化物半導體層230在開口290內位於氧化物層227的內側，絕緣層250在開口部290內位於氧化物半導體層230的內側，導電層260在開口部290內位於絕緣層250的內側。In FIG. 9B and other figures, insulating layer 225 contacts the bottom and side surfaces of the recess (specifically, the second recess) of conductive layer 220, and contacts the side surfaces of insulating layer 280, the side surfaces of conductive layer 240_1, and the side surfaces of conductive layer 240_2 within opening 290. Oxide layer 227 contacts the bottom and side surfaces of the recess (specifically, the first recess) of conductive layer 220, insulating layer 225, and the top surface of conductive layer 240_2. The oxide semiconductor layer 230 is located inside the oxide layer 227 in the opening 290 , the insulating layer 250 is located inside the oxide semiconductor layer 230 in the opening 290 , and the conductive layer 260 is located inside the insulating layer 250 in the opening 290 .
如圖10A所示，從絕緣層210的頂面到導電層220_2的與絕緣層280接觸的頂面的最短距離Tc較佳為比從絕緣層210的頂面到絕緣層250的底面的最短距離Ta長。由此，可以增大夾著氧化物層227而導電層220_2的側面與氧化物半導體層230對置的面積，從而可以降低導電層220_2與氧化物半導體層230間的接觸電阻。因此，可以抑制起因於導電層220_2與氧化物半導體層230間的接觸電阻的電晶體200B的通態電流的降低。另外，最短距離Ta可以根據開口部290內的絕緣層250的底面決定。As shown in FIG10A , the shortest distance Tc from the top surface of insulating layer 210 to the top surface of conductive layer 220_2 in contact with insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of insulating layer 210 to the bottom surface of insulating layer 250. This increases the area where the side surface of conductive layer 220_2 faces oxide semiconductor layer 230 with oxide layer 227 interposed therebetween, thereby reducing the contact resistance between conductive layer 220_2 and oxide semiconductor layer 230. Therefore, it is possible to suppress a decrease in the on-state current of the transistor 200B caused by the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. In addition, the shortest distance Ta can be determined by the bottom surface of the insulating layer 250 in the opening 290.
此外，如圖10A所示，最短距離Tc較佳為從絕緣層210的頂面到導電層260的底面的最短距離Tb以上，更佳為比最短距離Tb長。由此，閘極電場容易施加到氧化物半導體層230的通道形成區域，從而可以提高電晶體200B的電特性。再者，閘極電場還容易施加到氧化物半導體層230的夾著氧化物層227對置於導電層220_2的區域，因此可以增大電晶體200B的通態電流。此外，無論將導電層220還是導電層240用作汲極電極，都可以提高電晶體200B的電特性。另外，最短距離Tb可以根據開口部290內的導電層260的底面決定。Furthermore, as shown in FIG10A , the shortest distance Tc is preferably greater than the shortest distance Tb from the top surface of insulating layer 210 to the bottom surface of conductive layer 260, and more preferably, longer than the shortest distance Tb. This facilitates the application of a gate electric field to the channel-forming region of oxide semiconductor layer 230, thereby improving the electrical characteristics of transistor 200B. Furthermore, the gate electric field is also easily applied to the region of oxide semiconductor layer 230 that faces conductive layer 220_2 with oxide layer 227 interposed therebetween, thereby increasing the on-state current of transistor 200B. Furthermore, regardless of whether conductive layer 220 or conductive layer 240 is used as the drain electrode, the electrical characteristics of transistor 200B can be improved. In addition, the shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 within the opening 290.
在此，如圖10A所示，將絕緣層225的寬度（厚度）設為寬度TSW。寬度TSW較佳為小。藉由減小寬度TSW，可以抑制電晶體200B的通道寬度減小，而可以抑制通態電流的下降。另一方面，藉由增大寬度TSW，可以提高絕緣層225所具有的功能。由此，寬度TSW例如較佳為1nm以上且20nm以下，更佳為2nm以上且15nm以下，進一步較佳為3nm以上且10nm以下。Here, as shown in FIG10A , the width (thickness) of insulating layer 225 is set to width TSW . Width TSW is preferably small. By reducing width TSW , the reduction in the channel width of transistor 200B can be suppressed, thereby reducing the decrease in on-state current. On the other hand, by increasing width TSW , the function of insulating layer 225 can be enhanced. Therefore, width TSW is preferably, for example, 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.
另外，圖10B示出電晶體200B的通道寬度W。在俯視時的開口部290為圓形的情況下，開口部290的寬度D相當於開口部290的直徑，通道寬度W可以算出為“（D-2×TSW）×π”。10B shows the channel width W of transistor 200B. When the opening 290 is circular in a plan view, the width D of the opening 290 is equivalent to the diameter of the opening 290 , and the channel width W can be calculated as “(D-2×TSW )×π”.
電晶體200B的通道長度可以被看作源極區域與汲極區域間的距離。換言之，可以說電晶體200B的通道長度取決於絕緣層225的高度。此外，可以說電晶體200B的通道長度取決於導電層220的凹部（明確而言，第二凹部）的深度、導電層220上的絕緣層280的厚度及導電層240的厚度。在將電晶體200B的通道長度看作源極區域與汲極區域間的距離的情況下，電晶體200B的通道長度可以說是圖10A所示的長度L。The channel length of transistor 200B can be considered the distance between the source and drain regions. In other words, the channel length of transistor 200B is determined by the height of insulating layer 225. Furthermore, the channel length of transistor 200B is determined by the depth of the recess (specifically, the second recess) of conductive layer 220, the thickness of insulating layer 280 on conductive layer 220, and the thickness of conductive layer 240. If the channel length of transistor 200B is considered the distance between the source and drain regions, the channel length of transistor 200B can be described as length L as shown in FIG10A.
在圖10A所示的例子中，導電層220_2包括第一凹部及第二凹部，但是本發明不侷限於此。例如，如圖11A所示，電晶體200B也可以具有在導電層220_2中只設置一個凹部的結構。In the example shown in FIG10A , the conductive layer 220_2 includes a first recess and a second recess, but the present invention is not limited thereto. For example, as shown in FIG11A , the transistor 200B may also have a structure in which only one recess is provided in the conductive layer 220_2.
在導電層220_2中，有可能在開口部290的形成製程和絕緣層225的形成製程中的一者或兩者中形成凹部。在圖10A的電晶體200B所示的例子中，在上述製程的兩者中凹部形成在導電層220_2中，另一方面，在圖11A的電晶體200B所示的例子中，不在開口部290的形成製程中形成凹部，而在絕緣層225的形成製程中凹部形成在導電層220_2中。A recessed portion may be formed in the conductive layer 220_2 during one or both of the processes for forming the opening 290 and the insulating layer 225. In the example of the transistor 200B shown in FIG10A , the recessed portion is formed in the conductive layer 220_2 during both of the processes. In the example of the transistor 200B shown in FIG11A , the recessed portion is not formed during the process for forming the opening 290, but is formed in the conductive layer 220_2 during the process for forming the insulating layer 225.
在圖11A所示的電晶體200B中，絕緣層225在開口部290內與絕緣層280的側面、導電層240_1的側面、導電層240_2的側面以及導電層220_2的頂面接觸。此外，氧化物層227與導電層220_2的凹部的底面及側面接觸。In transistor 200B shown in FIG11A , insulating layer 225 contacts the side surfaces of insulating layer 280, the side surfaces of conductive layer 240_1, the side surfaces of conductive layer 240_2, and the top surface of conductive layer 220_2 within opening 290. Furthermore, oxide layer 227 contacts the bottom and side surfaces of the recess of conductive layer 220_2.
當在開口部290的形成製程和絕緣層225的形成製程的至少一方中凹部形成在導電層220_2中時，可以使開口部290內的導電層260_1的底面的高度變低，由此閘極電場容易施加到氧化物半導體層230的通道形成區域，而可以提高電晶體200B的電特性。When a recessed portion is formed in the conductive layer 220_2 during at least one of the processes for forming the opening 290 and forming the insulating layer 225, the bottom surface height of the conductive layer 260_1 within the opening 290 can be lowered, thereby making it easier for the gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B.
當在絕緣層225的形成製程中凹部形成在導電層220_2中時，氧化物層227可以與導電層220_2的凹部的底面及側面接觸，由此氧化物半導體層230與導電層220_2夾著氧化物層227重疊的面積變大，而可以降低氧化物半導體層230與導電層220間的接觸電阻，所以是較佳的。When a recess is formed in the conductive layer 220_2 during the formation process of the insulating layer 225, the oxide layer 227 can contact the bottom and side surfaces of the recess in the conductive layer 220_2. As a result, the overlapping area of the oxide semiconductor layer 230 and the conductive layer 220_2 with the oxide layer 227 sandwiched therebetween increases, thereby reducing the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, which is preferred.
另外，例如，如圖11B所示，電晶體200B也可以具有絕緣層225不覆蓋導電層240_2的側面的結構。Alternatively, for example, as shown in FIG. 11B , transistor 200B may have a structure in which insulating layer 225 does not cover the side surface of conductive layer 240_2.
圖11B所示的絕緣層225與導電層220的凹部的底面及側面接觸，並在開口部290內與絕緣層280的側面接觸。另外，絕緣層225與導電層240_1的側面的一部分接觸，而不與導電層240_2的側面接觸。絕緣層225在開口部290內可以與絕緣層280的側面、導電層240_1的側面和導電層240_2的側面中的一個以上接觸，也可以覆蓋各側面的一部分或整體。Insulating layer 225 shown in FIG11B contacts the bottom and side surfaces of the recessed portion of conductive layer 220 and contacts the side surfaces of insulating layer 280 within opening 290. Furthermore, insulating layer 225 contacts a portion of the side surface of conductive layer 240_1, but does not contact the side surface of conductive layer 240_2. Within opening 290, insulating layer 225 may contact one or more of the side surfaces of insulating layer 280, conductive layer 240_1, and conductive layer 240_2, or may cover a portion or all of each side surface.
在導電層240_2的側面的至少一部分不被絕緣層225覆蓋的情況下，該部分與氧化物層227接觸。由此，可以增大氧化物半導體層230與導電層240夾著氧化物層227重疊的面積，而可以降低氧化物半導體層230與導電層240間的接觸電阻。與此同樣，在絕緣層225不覆蓋導電層240_2的側面以及導電層240_1的側面的至少一部分的情況下，該部分與氧化物層227接觸。由此，可以增大氧化物半導體層230與導電層240夾著氧化物層227重疊的面積，而可以降低氧化物半導體層230與導電層240間的接觸電阻。When at least a portion of the side surface of conductive layer 240_2 is not covered by insulating layer 225, that portion is in contact with oxide layer 227. This increases the area of overlap between oxide semiconductor layer 230 and conductive layer 240 with oxide layer 227 interposed therebetween, thereby reducing the contact resistance between oxide semiconductor layer 230 and conductive layer 240. Similarly, when insulating layer 225 does not cover at least a portion of the side surface of conductive layer 240_2 and the side surface of conductive layer 240_1, that portion is in contact with oxide layer 227. As a result, the overlapping area of the oxide semiconductor layer 230 and the conductive layer 240 with the oxide layer 227 interposed therebetween can be increased, thereby reducing the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.
圖10A示出絕緣層225具有單層結構的例子。另外，絕緣層225可以具有兩層以上的疊層結構。例如，如圖12所示，絕緣層225可以具有絕緣層225_1及絕緣層225_2的兩層結構。FIG10A shows an example in which the insulating layer 225 has a single-layer structure. Alternatively, the insulating layer 225 may have a stacked structure of two or more layers. For example, as shown in FIG12 , the insulating layer 225 may have a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2.
圖12示出絕緣層225由與絕緣層280接觸的絕緣層225_1及位於絕緣層225_1與氧化物層227間的絕緣層225_2的兩層構成的例子。圖12所示的絕緣層225可以說是絕緣層225_1及絕緣層225_1上的絕緣層225_2的兩層結構。12 shows an example in which the insulating layer 225 is composed of two layers: an insulating layer 225_1 in contact with the insulating layer 280 and an insulating layer 225_2 located between the insulating layer 225_1 and the oxide layer 227. The insulating layer 225 shown in FIG12 can be said to have a two-layer structure: the insulating layer 225_1 and the insulating layer 225_2 on the insulating layer 225_1.
較佳的是，與開口部290中的絕緣層280的側面接觸的絕緣層225_1使用氫阻擋絕緣層，與氧化物層227接觸的絕緣層225_2使用具有俘獲或固定氫的功能的絕緣層。藉由採用這種結構，可以使氫經過氧化物層227而可以降低氧化物半導體層230中的氫濃度。因此，可以提高電晶體的電特性，而可以提高電晶體的可靠性。例如，較佳的是，絕緣層225_1使用氮化矽膜，絕緣層225_2使用氧化鉿膜、矽酸鉿膜或氧化鋁膜。此時，絕緣層225_1包含矽及氮，絕緣層225_2包含鉿和鋁中的一者或兩者及氧。Preferably, insulating layer 225_1, which contacts the side surface of insulating layer 280 in opening 290, is a hydrogen-blocking insulating layer, while insulating layer 225_2, which contacts oxide layer 227, is an insulating layer capable of capturing or fixing hydrogen. This structure allows hydrogen to pass through oxide layer 227, reducing the hydrogen concentration in oxide semiconductor layer 230. This improves the electrical characteristics of the transistor and enhances its reliability. For example, preferably, insulating layer 225_1 is made of a silicon nitride film, and insulating layer 225_2 is made of a bismuth oxide film, a bismuth silicate film, or an aluminum oxide film. In this case, insulating layer 225_1 contains silicon and nitrogen, and insulating layer 225_2 contains one or both of bismuth and aluminum, and oxygen.
另外，絕緣層225_1可以使用氫阻擋絕緣層，絕緣層225_2可以使用具有包含過量氧的區域的絕緣層。藉由採用這種結構，可以降低氧化物半導體層230中的氧空位和氫中的一者或兩者。由此，可以提高電晶體的電特性，而可以提高電晶體的可靠性。例如，較佳的是，絕緣層225_1使用氮化矽膜，絕緣層225_2使用氧化矽膜、氧氮化矽膜或氧化鋁膜。此時，絕緣層225_1包含矽及氮，絕緣層225_2包含矽和鋁中的一者或兩者及氧。尤其是，在作為絕緣層225_2使用氧化矽膜的情況下，絕緣層225_2包含矽及氧。Alternatively, insulating layer 225_1 may be a hydrogen-blocking insulating layer, and insulating layer 225_2 may be an insulating layer having a region containing excess oxygen. By adopting this structure, one or both of oxygen vacancies and hydrogen in oxide semiconductor layer 230 can be reduced. This improves the electrical characteristics of the transistor and increases transistor reliability. For example, preferably, insulating layer 225_1 is a silicon nitride film, and insulating layer 225_2 is a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. In this case, insulating layer 225_1 contains silicon and nitrogen, and insulating layer 225_2 contains one or both of silicon and aluminum, and oxygen. In particular, when a silicon oxide film is used as the insulating layer 225_2, the insulating layer 225_2 contains silicon and oxygen.
典型的是，絕緣層225_1及絕緣層225_2分別可以使用氮化矽膜及氧化矽膜。另外，將絕緣層225_1及絕緣層225_2的厚度分別設定為2nm及2nm。Typically, the insulating layer 225_1 and the insulating layer 225_2 can be made of a silicon nitride film and a silicon oxide film, respectively. Furthermore, the thicknesses of the insulating layer 225_1 and the insulating layer 225_2 are set to 2 nm and 2 nm, respectively.
如上所述，使用氫阻擋絕緣層以環狀圍繞氧化物半導體層230的周圍，並且在氧化物半導體層230附近設置具有俘獲或固定氫的功能的絕緣層或者具有包含過量氧的區域的絕緣層，由此可以減少氧化物半導體層230中的氧空位和雜質中的一者或兩者。因此，可以提高電晶體的電特性，而可以提高電晶體的可靠性。As described above, by using a hydrogen-blocking insulating layer to surround the oxide semiconductor layer 230 in a ring shape, and providing an insulating layer capable of trapping or fixing hydrogen or having a region containing excess oxygen near the oxide semiconductor layer 230, one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230 can be reduced. Consequently, the electrical characteristics of the transistor can be improved, thereby enhancing the reliability of the transistor.
另外，絕緣層225可以具有第一絕緣層、第二絕緣層及第三絕緣層的三層結構。例如，較佳的是，作為選自第一至第三絕緣層中的一個使用氫阻擋絕緣層，作為另一個使用具有俘獲或固定氫的功能的絕緣層，作為剩下的一個使用具有包含過量氧的區域的絕緣層。藉由採用這種結構，可以提高電晶體的電特性，而可以提高電晶體的可靠性。Alternatively, insulating layer 225 may have a three-layer structure comprising a first insulating layer, a second insulating layer, and a third insulating layer. For example, it is preferred that one of the first to third insulating layers be a hydrogen-blocking insulating layer, another be an insulating layer capable of trapping or fixing hydrogen, and the remaining insulating layer be an insulating layer having a region containing excess oxygen. By adopting this structure, the electrical characteristics of the transistor can be improved, thereby enhancing the reliability of the transistor.
在此，圖13A及圖13B示出圖12所示的絕緣層225的其他的結構例子。Here, FIG. 13A and FIG. 13B show other structural examples of the insulating layer 225 shown in FIG. 12 .
圖13A所示的電晶體200B示出如下例子：絕緣層225_1與導電層220_2所包括的凹部的底面的一部分及側面接觸，絕緣層225_2在開口部290中位於絕緣層225_1的內側並與導電層220_2所包括的凹部的底面的其他一部分接觸。13A shows an example in which the insulating layer 225_1 contacts a portion of the bottom and side surfaces of the recess included in the conductive layer 220_2, and the insulating layer 225_2 is located inside the insulating layer 225_1 in the opening 290 and contacts another portion of the bottom of the recess included in the conductive layer 220_2.
在圖13B所示的電晶體200B中，導電層220_2包括第一凹部、位於第一凹部的外側的第二凹部以及位於第二凹部的外側的第三凹部。第一凹部的深度比第二凹部深，第二凹部的深度比第三凹部深。在形成開口部290時在導電層220_2中設置第三凹部，然後在對絕緣層225_1進行加工時在導電層220_2中設置第二凹部，然後在對絕緣層225_2進行加工時在導電層220_2中設置第一凹部。由此，在圖13B中，第三凹部的側面與開口部290中的絕緣層280的側面對齊，第二凹部的側面與絕緣層225_1的絕緣層225_2一側的面對齊，第一凹部的側面與絕緣層225_2的氧化物層227一側的面對齊。In transistor 200B shown in FIG13B , conductive layer 220_2 includes a first recess, a second recess located outside the first recess, and a third recess located outside the second recess. The first recess is deeper than the second recess, which in turn is deeper than the third recess. The third recess is provided in conductive layer 220_2 when opening 290 is formed. The second recess is then provided in conductive layer 220_2 when insulating layer 225_1 is processed. The first recess is then provided in conductive layer 220_2 when insulating layer 225_2 is processed. 13B , the side surface of the third recess is aligned with the side surface of the insulating layer 280 in the opening 290 , the side surface of the second recess is aligned with the surface of the insulating layer 225_2 side of the insulating layer 225_1 , and the side surface of the first recess is aligned with the surface of the oxide layer 227 side of the insulating layer 225_2 .
在圖13B所示的電晶體200B中，絕緣層225_1與導電層220_2的第三凹部的底面及側面接觸地設置，絕緣層225_2與導電層220_2的第二凹部的底面及側面接觸地設置。In the transistor 200B shown in FIG13B , the insulating layer 225_1 is provided in contact with the bottom and side surfaces of the third recess of the conductive layer 220_2 , and the insulating layer 225_2 is provided in contact with the bottom and side surfaces of the second recess of the conductive layer 220_2 .
例如，在將絕緣層225_1設置在開口部290的側壁之後，形成將成為絕緣層225_2的絕緣膜並對其進行加工，由此可以形成圖13A或圖13B所示的結構的絕緣層225。與圖12所示的電晶體200B相比，絕緣層225_1與氧化物層227接觸的區域減少，由此可以實現氧化物層227與絕緣層225_2接觸的結構。For example, after insulating layer 225_1 is disposed on the sidewalls of opening 290, an insulating film to become insulating layer 225_2 is formed and processed, thereby forming insulating layer 225 having the structure shown in FIG13A or FIG13B. Compared to transistor 200B shown in FIG12, the area where insulating layer 225_1 contacts oxide layer 227 is reduced, thereby achieving a structure in which oxide layer 227 contacts insulating layer 225_2.
注意，電晶體200B也可以採用與電晶體200和電晶體200A中的至少一個同樣的結構。例如，如圖14A所示，在圖10A所示的半導體裝置中，絕緣層280可以具有絕緣層280_1、絕緣層280_1上的絕緣層280_2及絕緣層280_2上的絕緣層280_3的三層結構。此外，可以在絕緣層250及導電層260上設置絕緣層283。此外，導電層220_1可以具有導電層220_11及導電層220_11上的導電層220_12的兩層結構。另外，圖14B示出將上述結構用於圖12所示的半導體裝置的例子。Note that transistor 200B may also have the same structure as at least one of transistor 200 and transistor 200A. For example, as shown in FIG14A , in the semiconductor device shown in FIG10A , insulating layer 280 may have a three-layer structure comprising insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. Furthermore, insulating layer 283 may be provided on insulating layer 250 and conductive layer 260. Alternatively, the conductive layer 220_1 may have a two-layer structure of a conductive layer 220_11 and a conductive layer 220_12 on the conductive layer 220_11. FIG14B shows an example in which the above structure is applied to the semiconductor device shown in FIG12.
[電晶體200C] 圖15A1是包括電晶體200C的半導體裝置的平面圖。圖15A2是示出配置有多個電晶體200C的例子的平面圖。圖15B是沿著圖15A1的點劃線A1-A2的剖面圖。圖15C是沿著圖15A1的點劃線A3-A4的剖面圖。圖15D是沿著圖15B的點劃線A5-A6的剖面圖。圖15D也可以說是包括絕緣層280的XY平面的剖面圖。此外，圖16A是圖15C的放大圖。[Transistor 200C]Figure 15A1 is a plan view of a semiconductor device including transistor 200C. Figure 15A2 is a plan view showing an example of a configuration of multiple transistors 200C. Figure 15B is a cross-sectional view taken along dotted line A1-A2 in Figure 15A1. Figure 15C is a cross-sectional view taken along dotted line A3-A4 in Figure 15A1. Figure 15D is a cross-sectional view taken along dotted line A5-A6 in Figure 15B. Figure 15D can also be considered a cross-sectional view taken along the XY plane including insulating layer 280. Furthermore, Figure 16A is an enlarged view of Figure 15C.
圖15A1至圖15D所示的半導體裝置包括基板（未圖示）上的絕緣層210、絕緣層210上的電晶體200C、絕緣層210上的絕緣層280以及絕緣層280上的絕緣層281。The semiconductor device shown in FIG. 15A1 to FIG. 15D includes an insulating layer 210 on a substrate (not shown), a transistor 200C on the insulating layer 210 , an insulating layer 280 on the insulating layer 210 , and an insulating layer 281 on the insulating layer 280 .
電晶體200C包括導電層220、絕緣層280上的導電層255、絕緣層281上的導電層240、絕緣層225、氧化物層227、氧化物層227上的氧化物半導體層230、氧化物半導體層230上的絕緣層250以及絕緣層250上的導電層260。Transistor 200C includes conductive layer 220 , conductive layer 255 on insulating layer 280 , conductive layer 240 on insulating layer 281 , insulating layer 225 , oxide layer 227 , oxide semiconductor layer 230 on oxide layer 227 , insulating layer 250 on oxide semiconductor layer 230 , and conductive layer 260 on insulating layer 250 .
圖15A1至圖15D所示的半導體裝置與圖2A1至圖2D所示的半導體裝置的主要不同之處在於：前者包括導電層255及絕緣層281。此外，圖15A1至圖15D所示的電晶體200C與圖9A1至圖9D所示的電晶體200B的主要不同之處在於：前者包括導電層255。The semiconductor device shown in Figures 15A1 to 15D differs primarily from the semiconductor device shown in Figures 2A1 to 2D in that the former includes a conductive layer 255 and an insulating layer 281. Furthermore, the transistor 200C shown in Figures 15A1 to 15D differs primarily from the transistor 200B shown in Figures 9A1 to 9D in that the former includes a conductive layer 255.
導電層255位於絕緣層280上，絕緣層281位於導電層255及絕緣層280上。此外，導電層240_1位於絕緣層281上。The conductive layer 255 is located on the insulating layer 280 , and the insulating layer 281 is located on the conductive layer 255 and the insulating layer 280 . In addition, the conductive layer 240_1 is located on the insulating layer 281 .
如圖16A所示，絕緣層280、導電層255、絕緣層281及導電層240中設置有到達導電層220的開口部290。As shown in FIG. 16A , openings 290 that reach the conductive layer 220 are provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .
在電晶體200C中，氧化物半導體層230被用作半導體層，導電層260被用作第一閘極電極，絕緣層250被用作第一閘極絕緣層，導電層220被用作源極電極和汲極電極中的一個，導電層240被用作源極電極和汲極電極中的另一個，導電層255被用作第二閘極電極，絕緣層225被用作第二閘極絕緣層。In transistor 200C, oxide semiconductor layer 230 is used as a semiconductor layer, conductive layer 260 is used as a first gate electrode, insulating layer 250 is used as a first gate insulating layer, conductive layer 220 is used as one of a source electrode and a drain electrode, conductive layer 240 is used as the other of the source electrode and the drain electrode, conductive layer 255 is used as a second gate electrode, and insulating layer 225 is used as a second gate insulating layer.
氧化物半導體層230具有隔著氧化物層227及絕緣層225與導電層255重疊且隔著絕緣層250與導電層260重疊的區域。該區域的至少一部分被用作電晶體200C的通道形成區域。The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 via the oxide layer 227 and the insulating layer 225, and overlaps with the conductive layer 260 via the insulating layer 250. At least a portion of this region is used as a channel formation region of the transistor 200C.
電晶體200C包括用作背閘極電極的導電層，因此可以根據施加到該導電層的電位而控制電晶體200C的臨界電壓。由此，藉由控制臨界電壓，容易實現常關閉特性的電晶體。Transistor 200C includes a conductive layer serving as a back gate electrode, so the critical voltage of transistor 200C can be controlled by the potential applied to the conductive layer. Thus, by controlling the critical voltage, a normally-off transistor can be easily realized.
注意，在電晶體200C中，也可以將導電層255和導電層260中的一個用作閘極電極並將另一個用作背閘極電極。有時，在電晶體200C中，尤其較佳為將導電層260用作閘極電極並將導電層255用作背閘極電極。藉由將包括與導電層255相比更大的對置於氧化物半導體層230的區域的導電層260用作閘極電極，閘極電場進一步高效地施加到氧化物半導體層230，因此有時可以提高電晶體的電特性。另外，在導電層260被用作閘極電極且導電層255被用作背閘極電極的情況下，絕緣層250被用作閘極絕緣層，絕緣層225被用作背閘極絕緣層。Note that in transistor 200C, one of conductive layer 255 and conductive layer 260 can be used as a gate electrode and the other as a back-gate electrode. In some cases, in transistor 200C, it is particularly preferable to use conductive layer 260 as a gate electrode and conductive layer 255 as a back-gate electrode. By using conductive layer 260, which includes a larger area facing oxide semiconductor layer 230 than conductive layer 255, as a gate electrode, the gate electric field is more efficiently applied to oxide semiconductor layer 230, thereby sometimes improving the electrical characteristics of the transistor. In addition, when the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode, the insulating layer 250 is used as a gate insulating layer and the insulating layer 225 is used as a back gate insulating layer.
導電層255可以使用可用於導電層260的導電材料。The conductive layer 255 may use the same conductive material as that used for the conductive layer 260 .
絕緣層281被用作層間膜。絕緣層281可以使用可用於絕緣層280的絕緣材料。The insulating layer 281 is used as an interlayer film and can use the insulating material that can be used for the insulating layer 280.
圖16A示出絕緣層281具有單層結構的例子。另外，絕緣層281可以具有兩層以上的疊層結構。例如，如圖16B所示，絕緣層281可以具有絕緣層281_1、絕緣層281_1上的絕緣層281_2及絕緣層281_2上的絕緣層281_3的三層結構。此時，較佳的是，作為絕緣層281_2使用上述的相對介電常數低的材料，作為絕緣層281_1及絕緣層281_3使用氧阻擋絕緣層。由此，可以抑制導電層255及導電層240的氧化，來抑制高電阻化。FIG16A shows an example in which insulating layer 281 has a single-layer structure. Alternatively, insulating layer 281 may have a stacked structure of two or more layers. For example, as shown in FIG16B , insulating layer 281 may have a three-layer structure comprising insulating layer 281_1, insulating layer 281_2 on insulating layer 281_1, and insulating layer 281_3 on insulating layer 281_2. In this case, preferably, insulating layer 281_2 is made of the aforementioned low relative dielectric constant material, and insulating layers 281_1 and 281_3 are oxygen-blocking insulating layers. This can suppress oxidation of the conductive layer 255 and the conductive layer 240, thereby suppressing an increase in resistance.
另外，電晶體200C可以採用與電晶體200、電晶體200A和電晶體200B中的至少一個同樣的結構。例如，如圖16B所示，在圖16A所示的半導體裝置中，絕緣層280可以具有絕緣層280_1、絕緣層280_1上的絕緣層280_2及絕緣層280_2上的絕緣層280_3的三層結構。另外，可以在絕緣層250及導電層260上設置絕緣層283。另外，導電層220_1可以具有導電層220_11及導電層220_11上的導電層220_12的兩層結構。Furthermore, transistor 200C may have the same structure as at least one of transistor 200, transistor 200A, and transistor 200B. For example, as shown in FIG16B , in the semiconductor device shown in FIG16A , insulating layer 280 may have a three-layer structure comprising insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. Furthermore, insulating layer 283 may be provided on insulating layer 250 and conductive layer 260. In addition, the conductive layer 220_1 may have a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 on the conductive layer 220_11.
＜半導體裝置的製造方法例子＞ 接著，參照圖17A至圖18C說明本發明的一個實施方式的半導體裝置的製造方法。注意，關於各組件的材料及形成方法，有時省略與已說明的部分同樣的部分。<Example of a Semiconductor Device Manufacturing Method>Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 17A to 18C. Note that details regarding the materials and formation methods of various components, which are identical to those already described, may be omitted.
構成半導體裝置的薄膜（絕緣膜、半導體膜及導電膜等）可以利用濺射法、化學氣相沉積（CVD：Chemical Vapor Deposition）法、真空蒸鍍法、分子束磊晶（MBE：Molecular Beam Epitaxy）法、脈衝雷射沉積（PLD：Pulsed Laser Deposition）法、ALD法等形成。Thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD.
另外，作為濺射法，可以舉出將高頻電源用於濺射用電源的RF濺射法、利用直流電源的DC濺射法、以脈衝方式改變施加到電極的電壓的脈衝DC濺射法。RF濺射法主要在沉積絕緣膜時使用，DC濺射法主要在沉積金屬導電膜時使用。此外，脈衝DC濺射法主要在利用反應性濺射法沉積氧化物、氮化物及碳化物等化合物時使用。Examples of sputtering methods include RF sputtering, which uses a high-frequency power source for the sputtering power source; DC sputtering, which utilizes a direct current power source; and pulsed DC sputtering, which varies the voltage applied to the electrodes in a pulsed manner. RF sputtering is primarily used for depositing insulating films, while DC sputtering is primarily used for depositing metallic conductive films. Furthermore, pulsed DC sputtering is primarily used for depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.
此外，CVD法可以分為利用電漿的電漿CVD（PECVD）法、利用熱的熱CVD（TCVD：Thermal CVD）法、利用光的光CVD（Photo CVD）法等。再者，可以根據使用的源氣體分為金屬CVD（MCVD：Metal CVD）法、有機金屬CVD（MOCVD：Metal Organic CVD）法。CVD can be categorized into plasma CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD (photo CVD) using light. Furthermore, it can be categorized into metal CVD (MCVD) and metal organic CVD (MOCVD) based on the source gas used.
藉由利用電漿CVD法，可以以較低的溫度得到高品質的膜。此外，因為不使用電漿，熱CVD法是能夠減少對被處理物造成的電漿損傷的沉積方法。例如，包括在半導體裝置中的佈線、電極、元件（電晶體、電容器等）等有時因從電漿接收電荷而會產生電荷積聚。此時，有時由於所累積的電荷而使包括在半導體裝置中的佈線、電極、元件等受損傷。另一方面，因為在利用不使用電漿的熱CVD法的情況下不產生上述電漿損傷，所以能夠提高半導體裝置的良率。此外，在熱CVD法中，不產生形成時的電漿損傷，因此能夠得到缺陷較少的膜。Plasma CVD can produce high-quality films at relatively low temperatures. Furthermore, because it doesn't use plasma, thermal CVD is a deposition method that can reduce plasma damage to the substrate. For example, the wiring, electrodes, and components (transistors, capacitors, etc.) included in semiconductor devices sometimes receive charge from plasma, causing charge accumulation. This accumulated charge can damage the wiring, electrodes, and components within the semiconductor device. On the other hand, because thermal CVD, which doesn't use plasma, avoids this plasma damage, it can improve the yield of semiconductor devices. In addition, thermal CVD does not cause plasma damage during formation, so films with fewer defects can be obtained.
作為ALD法，可以採用只利用熱能使前驅物及反應物起反應的熱ALD法、使用受到電漿激發的反應物的PEALD法等。As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method in which a reactant is excited by plasma, and the like can be adopted.
另外，ALD法中使用的前驅物有時包含碳或氯等元素。因此，利用ALD法設置的膜有時與利用其他的沉積方法設置的膜相比包含更多的碳或氯等元素。此外，這些元素的定量可以利用XPS或SIMS進行。注意，作為本發明的一個實施方式的金屬氧化物的沉積方法利用ALD法，但是由於採用沉積時的基板溫度高的條件和雜質去除處理中的一者或兩者，所以與不採用上述條件而利用ALD法的情況相比有時包含在膜中的碳及氯的量少。In addition, the precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films formed using the ALD method may contain more elements such as carbon or chlorine than films formed using other deposition methods. In addition, the quantitative determination of these elements can be performed using XPS or SIMS. Note that the metal oxide deposition method of one embodiment of the present invention utilizes the ALD method, but due to the use of either or both of high substrate temperature conditions and impurity removal treatment during deposition, the amount of carbon and chlorine contained in the film may be less than when the ALD method is used without these conditions.
ALD法不同於從靶材等中被釋放的粒子沉積的沉積方法，是因被處理物表面的反應而形成膜的沉積方法。因此，ALD法是不易受被處理物的形狀的影響而具有良好的步階覆蓋性的沉積方法。尤其是，ALD法具有良好的步階覆蓋性和厚度均勻性，所以適合用於覆蓋縱橫比高的開口部的表面的情況等。Unlike deposition methods that deposit particles released from a target, ALD forms a film through a reaction on the surface of the substrate. Therefore, ALD is less susceptible to the shape of the substrate and offers excellent step coverage. ALD's excellent step coverage and thickness uniformity make it particularly suitable for coating surfaces with openings that have high aspect ratios.
CVD法及ALD法不同於從靶材等中被釋放的粒子沉積的濺射法。因此，ALD法是不易受被處理物的形狀的影響而具有良好的步階覆蓋性的沉積方法。尤其是，ALD法具有良好的步階覆蓋性和厚度均勻性，所以ALD法適合用於覆蓋縱橫比高的開口部的表面的情況等。但是，ALD法的沉積速率比較慢，所以有時較佳為與沉積速率快的CVD法等其他沉積方法組合而使用。CVD and ALD differ from sputtering methods, which deposit particles released from a target. Therefore, ALD is less susceptible to the shape of the workpiece and offers excellent step coverage. In particular, ALD's excellent step coverage and thickness uniformity make it suitable for coating surfaces with high-aspect-ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes best used in combination with other deposition methods, such as CVD, which have faster deposition rates.
此外，當使用CVD法時，可以根據源氣體的流量比沉積任意組成的膜。例如，當使用CVD法時，可以藉由在進行沉積的同時改變源氣體的流量比來沉積其組成連續變化的膜。當在改變源氣體的流量比的同時進行沉積時，因為不需要傳送或調整壓力所需的時間，所以與使用多個沉積室進行沉積的情況相比可以縮短沉積時間。因此，有時可以提高半導體裝置的生產率。Furthermore, using CVD allows for deposition of films of varying composition depending on the source gas flow ratio. For example, by varying the source gas flow ratio during deposition, a film with a continuously changing composition can be deposited. By performing deposition while varying the source gas flow ratio, deposition can be shortened compared to deposition using multiple deposition chambers, as the time required for transfer and pressure adjustment is eliminated. Consequently, semiconductor device productivity can sometimes be improved.
當使用ALD法時，藉由同時導入不同的多種前驅物，可以沉積任意組成的膜。或者，在導入不同的多種前驅物時，藉由控制各前驅物的循環次數可以沉積任意組成的膜。When using ALD, films of any composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when introducing multiple different precursors, films of any composition can be deposited by controlling the number of cycles of each precursor.
構成半導體裝置的薄膜（絕緣膜、半導體膜及導電膜等）可以利用旋塗法、浸漬法、噴塗法、噴墨法、分配器法、網版印刷法、平板印刷法、刮刀（doctor knife）法、狹縫式塗佈法、輥塗法、簾式塗佈法或刮刀式塗佈法等濕式沉積方法形成。Thin films (such as insulating films, semiconductor films, and conductive films) that make up semiconductor devices can be formed using wet deposition methods such as spin coating, immersion coating, inkjet coating, dispenser coating, screen printing, lithographic printing, doctor knife coating, slit coating, roll coating, curtain coating, or doctor blade coating.
此外，當對構成半導體裝置的薄膜進行加工時，可以利用光微影法等。或者，可以利用奈米壓印法、噴砂法、剝離法等對薄膜進行加工。此外，也可以藉由利用使用金屬遮罩等陰影遮罩的沉積方法直接形成島狀的薄膜。Furthermore, thin films constituting semiconductor devices can be processed using methods such as photolithography. Alternatively, thin films can be processed using methods such as nanoimprinting, sandblasting, and lift-off. Furthermore, island-shaped thin films can be directly formed using a deposition method that utilizes a shadow mask such as a metal mask.
光微影法典型地有如下兩種方法。一個是在要進行加工的薄膜上形成光阻遮罩，藉由蝕刻等對該薄膜進行加工，並去除光阻遮罩的方法。另一個是沉積具有感光性的薄膜之後進行曝光、顯影，來將該薄膜加工為所希望的形狀的方法。There are two typical photolithography methods. One involves forming a photoresist mask on the film to be processed, processing the film by etching, etc., and then removing the photoresist mask. The other involves depositing a photosensitive film, then exposing and developing it to the desired shape.
在光微影法中，作為用於曝光的光，例如可以使用i線（波長365nm）、g線（波長436nm）、h線（波長405nm）或混合了這些射線的光。此外，還可以使用紫外線、KrF雷射或ArF雷射等。此外，也可以利用液浸曝光技術進行曝光。此外，作為用於曝光的光，也可以使用極紫外（EUV：Extreme Ultra-violet）光或X射線。此外，代替用於曝光的光，也可以使用電子束。當使用極紫外光、X射線或電子束時，可以進行極其精細的加工，所以是較佳的。注意，在藉由利用電子束等光束進行掃描而進行曝光時，不需要光罩。In photolithography, as light used for exposure, for example, i-rays (wavelength 365nm), g-rays (wavelength 436nm), h-rays (wavelength 405nm), or light mixed with these rays can be used. In addition, ultraviolet rays, KrF lasers, ArF lasers, etc. can also be used. In addition, exposure can also be performed using liquid immersion exposure technology. In addition, as light used for exposure, extreme ultraviolet (EUV) light or X-rays can also be used. In addition, instead of light used for exposure, an electron beam can also be used. When extreme ultraviolet light, X-rays, or electron beams are used, extremely fine processing can be performed, so it is preferable. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.
作為薄膜的蝕刻方法，可以利用乾蝕刻法、濕蝕刻法及噴砂法等。Thin film etching methods include dry etching, wet etching, and sandblasting.
參照圖17A至圖18C說明上述的包括電晶體200B的半導體裝置（參照圖9A1至圖9D）的製造方法例子。注意，絕緣層225具有圖12所示的絕緣層225_1及絕緣層225_2的兩層結構。An example of a method for manufacturing the semiconductor device including the transistor 200B (see FIG. 9A1 to FIG. 9D ) will be described with reference to FIG. 17A to FIG. 18C Note that the insulating layer 225 has a two-layer structure of the insulating layer 225_1 and the insulating layer 225_2 shown in FIG.
首先，如圖17A所示，在基板（未圖示）上形成絕緣層210，在絕緣層210上形成導電層220_1，在導電層220_1上形成導電層220_2，在導電層220_2上形成絕緣層280。First, as shown in FIG17A , an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220_1 is formed on the insulating layer 210 , a conductive layer 220_2 is formed on the conductive layer 220_1 , and an insulating layer 280 is formed on the conductive layer 220_2 .
另外，絕緣層280可以利用兩種沉積方法形成。例如，作為絕緣層280，可以在利用ALD法形成氮化矽膜之後利用濺射法形成氮化矽膜。ALD法是步階覆蓋性高且厚度的均勻性高的沉積方法，因此適合用於沉積厚度小的膜的情況或者覆蓋縱橫比高的開口部或層的表面的情況。濺射法的沉積速率比ALD法高，因此可以提高產生率。Furthermore, insulating layer 280 can be formed using two deposition methods. For example, insulating layer 280 can be formed using ALD followed by sputtering. ALD offers high step coverage and thickness uniformity, making it suitable for depositing thin films or covering openings or surfaces with high aspect ratios. Sputtering offers a higher deposition rate than ALD, thus improving productivity.
此外，較佳為在沉積絕緣層280之後進行平坦化處理來使絕緣層280的頂面平坦化。作為平坦化處理，利用化學機械拋光（CMP：Chemical Mechanical Polishing）法的平坦化處理（也稱為CMP處理）是較佳的。此外，也可以進行利用蝕刻的平坦化處理（也稱為回蝕處理）。藉由進行絕緣層280的平坦化處理，可以使導電層240a的被形成面平坦，由此可以抑制導電層240a的斷開。此外，也可以不進行平坦化處理，此時可以降低製造成本。After depositing the insulating layer 280, it is preferable to perform a planarization process to flatten the top surface of the insulating layer 280. Chemical mechanical polishing (CMP) (also known as CMP) is a preferred planarization process. Alternatively, etching (also known as etch-back) can be performed. By performing a planarization process on the insulating layer 280, the surface on which the conductive layer 240a is formed can be flattened, thereby preventing breakage of the conductive layer 240a. Alternatively, the planarization process can be omitted, thereby reducing manufacturing costs.
接著，如圖17A所示，在絕緣層280上形成導電層240_1，在導電層240_1上形成導電層240_2。Next, as shown in FIG17A , a conductive layer 240_1 is formed on the insulating layer 280 , and a conductive layer 240_2 is formed on the conductive layer 240_1 .
接著，如圖17B所示，在導電層240_2、導電層240_1、絕緣層280的與導電層220_1重疊的位置形成開口部290。此時，較佳為在導電層220_2的與開口部290重疊的位置設置凹部。較佳為藉由形成開口部290使導電層220_2的凹部的底面及側面露出。Next, as shown in FIG17B , openings 290 are formed in conductive layer 240_2, conductive layer 240_1, and insulating layer 280 at locations where they overlap with conductive layer 220_1. At this point, a recess is preferably formed in conductive layer 220_2 at the location where it overlaps with opening 290. The formation of opening 290 preferably exposes the bottom and side surfaces of the recess in conductive layer 220_2.
為了進行微型加工並縮小電晶體的尺寸，較佳為在形成開口部290時利用各向異性蝕刻對導電層220_2的一部分、導電層240_1的一部分、導電層240_2的一部分及絕緣層280的一部分進行加工。尤其是，利用乾蝕刻法的加工適合於微型加工，所以是較佳的。此外，也可以在根據各層而不同的加工條件下形成開口部290。此外，根據導電層220_2、導電層240_1、導電層240_2及絕緣層280的材料及加工條件等，有時開口部290內的導電層220_2的側面的傾斜度、導電層240_1的側面的傾斜度、導電層240_2的側面的傾斜度及絕緣層280的側面的傾斜度彼此不同。To achieve microfabrication and reduce transistor size, it is preferable to use anisotropic etching to process a portion of conductive layer 220_2, a portion of conductive layer 240_1, a portion of conductive layer 240_2, and a portion of insulating layer 280 when forming opening 290. Dry etching is particularly preferred because it is well-suited for microfabrication. Alternatively, opening 290 can be formed under different processing conditions for each layer. Furthermore, depending on the materials and processing conditions of the conductive layer 220_2, the conductive layer 240_1, the conductive layer 240_2, and the insulating layer 280, the inclination of the side surface of the conductive layer 220_2, the inclination of the side surface of the conductive layer 240_1, the inclination of the side surface of the conductive layer 240_2, and the inclination of the side surface of the insulating layer 280 within the opening 290 may be different from each other.
此外，藉由開口部290的形成製程等，有時導電層220_2的凹部的底面及側面、絕緣層280的側面、導電層240_1的側面以及導電層240_2的頂面及側面中的至少一個上設置有包含鹵素的區域。作為該區域，例如可以舉出包含氟的區域、包含氯的區域或包含氟及氯的區域等。例如，有時來源於乾蝕刻中使用的蝕刻氣體的鹵素殘留在該區域中。Furthermore, due to the process of forming opening 290, a region containing halogens may be formed on at least one of the bottom and side surfaces of the recess of conductive layer 220_2, the side surfaces of insulating layer 280, the side surfaces of conductive layer 240_1, and the top and side surfaces of conductive layer 240_2. Examples of such regions include regions containing fluorine, regions containing chlorine, or regions containing both fluorine and chlorine. For example, halogens from the etching gas used in dry etching may remain in such regions.
接著，較佳為進行加熱處理。作為加熱處理，例如，可以以250℃以上且650℃以下，較佳為以300℃以上且500℃以下，更佳為以320℃以上且450℃以下進行。Next, a heat treatment is preferably performed. The heat treatment can be performed at, for example, 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C.
在氮氣體或非活性氣體的氛圍或包含10ppm以上、1%以上或10%以上的氧化性氣體的氛圍下進行加熱處理。例如，當在氮氣體和氧氣體的混合氛圍下進行加熱處理時，將氧氣體的比率較佳為設為20%左右。加熱處理也可以在減壓狀態下進行。或者，也可以在氮氣體或非活性氣體氛圍下進行加熱處理之後為了填補脫離了的氧在包含10ppm以上、1%以上或10%以上的氧化性氣體的氛圍下進行加熱處理。藉由進行上述加熱處理，可以在沉積氧化物半導體層230之前減少包含在絕緣層280等中的氫或水等雜質。Heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more. For example, when heat treatment is performed in a mixed atmosphere of nitrogen and oxygen, the ratio of oxygen is preferably set to approximately 20%. Heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an atmosphere of an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more in order to replenish the oxygen released after heat treatment in an atmosphere of nitrogen or an inert gas. By performing the above-mentioned heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 and the like can be reduced before the oxide semiconductor layer 230 is deposited.
此外，在上述加熱處理中使用的氣體較佳為被高度純化。例如，在上述加熱處理中使用的氣體所包含的水分量較佳為1ppb以下，更佳為0.1ppb以下，進一步較佳為0.05ppb以下。藉由使用高度純化了的氣體進行加熱處理，可以儘可能地防止水分等被絕緣層280等吸收。Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment minimizes absorption of moisture and other substances by the insulating layer 280 and the like.
接著，如圖17C所示，以覆蓋開口部290的方式依次沉積絕緣層225_1、絕緣層225_2。絕緣層225_1與導電層220_2的凹部的底面及側面、絕緣層280的側面、導電層240_1的側面以及導電層240_2的頂面及側面接觸。絕緣層225_2設置在絕緣層225_1上。Next, as shown in FIG17C , insulating layer 225_1 and insulating layer 225_2 are sequentially deposited to cover opening 290. Insulating layer 225_1 contacts the bottom and side surfaces of the recess in conductive layer 220_2, the side surfaces of insulating layer 280, the side surfaces of conductive layer 240_1, and the top and side surfaces of conductive layer 240_2. Insulating layer 225_2 is disposed on insulating layer 225_1.
絕緣層225_1及絕緣層225_2是設置在開口部290內的層，因此較佳為利用CVD法或ALD法沉積，更佳為利用ALD法沉積。由此，可以以高覆蓋性設置絕緣層225_1及絕緣層225_2。The insulating layer 225_1 and the insulating layer 225_2 are provided within the opening 290 and are therefore preferably deposited using CVD or ALD, more preferably ALD. This allows the insulating layer 225_1 and the insulating layer 225_2 to be provided with high coverage.
在本實施方式中，作為絕緣層225_1利用PEALD法沉積氮化矽膜，作為絕緣層225_2利用PEALD法沉積氧化矽膜。In this embodiment, a silicon nitride film is deposited as the insulating layer 225_1 using the PEALD method, and a silicon oxide film is deposited as the insulating layer 225_2 using the PEALD method.
另外，絕緣層225_1及絕緣層225_2較佳為以不暴露於大氣的方式連續地沉積。藉由以不暴露於大氣的方式連續地沉積絕緣層225_1及絕緣層225_2，可以提高產生率。另外，可以減少引入到絕緣層225_1與絕緣層225_2的介面及其附近的雜質（典型的為水分等）。Furthermore, insulating layer 225_1 and insulating layer 225_2 are preferably deposited continuously without being exposed to the atmosphere. By depositing insulating layer 225_1 and insulating layer 225_2 continuously without being exposed to the atmosphere, productivity can be improved. Furthermore, impurities (typically moisture, etc.) introduced into and near the interface between insulating layer 225_1 and insulating layer 225_2 can be reduced.
接著，如圖17D所示，對絕緣層225_1及絕緣層225_2進行加工，來使導電層240_2的頂面露出並在開口部290中使導電層220_2露出。較佳為在開口部290中導電層220_2的凹部的底面露出。17D , the insulating layer 225_1 and the insulating layer 225_2 are processed to expose the top surface of the conductive layer 240_2 and expose the conductive layer 220_2 in the opening 290. Preferably, the bottom surface of the recessed portion of the conductive layer 220_2 is exposed in the opening 290.
藉由各向異性蝕刻對絕緣層225_1及絕緣層225_2進行加工，來去除絕緣層225_1及絕緣層225_2中的位於導電層240_2的頂面的區域及位於開口部290的底面的區域，由此可以使絕緣層225_1及絕緣層225_2只殘留在開口部290內的側面。絕緣層225_1及絕緣層225_2較佳為利用乾蝕刻法進行各向異性高的蝕刻來加工。By processing insulating layers 225_1 and 225_2 using anisotropic etching, the regions of insulating layers 225_1 and 225_2 located on the top surface of conductive layer 240_2 and the regions located on the bottom surface of opening 290 are removed. This allows insulating layers 225_1 and 225_2 to remain only on the side surfaces within opening 290. Insulating layers 225_1 and 225_2 are preferably processed using dry etching with high anisotropy.
另外，如圖17D所示，在對絕緣層225_1及絕緣層225_2進行加工時，導電層220_2的一部分也可以被去除，並且也可以在導電層220_2中設置凹部（上述第一凹部）。17D , when the insulating layer 225_1 and the insulating layer 225_2 are processed, a portion of the conductive layer 220_2 may be removed, and a recess (the first recess described above) may be provided in the conductive layer 220_2 .
較佳為在沉積絕緣層225_2之後且在對絕緣層225_2進行加工之前（參照圖17C）進行供應氧的處理。由此，可以將氧供應到絕緣層225_2，並藉由形成氧化物半導體層230之後施加到的熱等將氧從絕緣層225_2供應到氧化物半導體層230。另外，藉由設置具有氧阻擋性的絕緣層225_1，可以抑制氧擴散到導電層220及導電層240中，而可以抑制導電層220及導電層240的導電性下降。由此，可以擴大導電層220及導電層240的材料選擇範圍。It is preferable to perform oxygen supply processing after depositing insulating layer 225_2 and before processing insulating layer 225_2 (see FIG. 17C ). This allows oxygen to be supplied to insulating layer 225_2, and oxygen can be supplied from insulating layer 225_2 to oxide semiconductor layer 230 by heat applied after forming oxide semiconductor layer 230. Furthermore, by providing insulating layer 225_1 having oxygen barrier properties, oxygen diffusion into conductive layer 220 and conductive layer 240 can be suppressed, thereby preventing a decrease in the conductivity of conductive layer 220 and conductive layer 240. Thus, the range of material selection for the conductive layer 220 and the conductive layer 240 can be expanded.
或者，也可以在對絕緣層225_2進行加工之後（參照圖17D）進行供應氧的處理。由此，可以將氧供應到絕緣層225_2，並藉由形成氧化物半導體層230之後施加到的熱等將氧從絕緣層225_2供應到氧化物半導體層230。另外，藉由作為導電層220_2及導電層240_2使用氧化物導電體，即使在對絕緣層225_2進行加工之後進行供應氧的處理，也可以抑制導電層220_2及導電層240_2的導電率下降。Alternatively, an oxygen supply process may be performed after processing the insulating layer 225_2 (see FIG. 17D ). This allows oxygen to be supplied to the insulating layer 225_2, and oxygen can be supplied from the insulating layer 225_2 to the oxide semiconductor layer 230 by heat applied after forming the oxide semiconductor layer 230. Furthermore, by using an oxide conductor as the conductive layer 220_2 and the conductive layer 240_2, even if the oxygen supply process is performed after processing the insulating layer 225_2, a decrease in the conductivity of the conductive layer 220_2 and the conductive layer 240_2 can be suppressed.
作為供應氧的處理，例如可以舉出含氧氛圍下的加熱處理或者含氧氛圍下的電漿處理（包括微波電漿處理）等，或者，也可以利用濺射法在含氧氛圍下沉積氧化物膜（較佳為沉積金屬氧化物膜）來將氧供應到絕緣層225_2。沉積的氧化物膜可以立刻去除，也可以殘留。在使沉積的氧化物膜殘留的情況下，可以將該氧化物膜用作氧化物層227。另外，作為含氧氛圍，除了氧氣體（O2）以外，還包括含有臭氧（O3）或一氧化二氮（N2O）等包含氧的化合物的氣體的氛圍。另外，電漿處理時的基板溫度為室溫（25℃）以上且450℃以下。Examples of oxygen supplying processes include heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere (including microwave plasma treatment). Alternatively, oxygen can be supplied to the insulating layer 225_2 by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film may be removed immediately or left as a residue. If the deposited oxide film is left as a residue, the oxide film can be used as the oxide layer 227. Furthermore, the oxygen-containing atmosphere includes, in addition to oxygen gas (O2 ), an atmosphere containing a gas containing an oxygen compound such as ozone (O3 ) or nitrous oxide (N2O ). The substrate temperature during the plasma treatment is preferably above room temperature (25°C) and below 450°C.
接著，如圖18A所示，以覆蓋開口部290的方式形成氧化物層227。氧化物層227與導電層220_2的凹部的底面及側面、絕緣層225_2的側面、導電層240_1的側面以及導電層240_2的頂面及側面接觸地設置。18A , an oxide layer 227 is formed to cover the opening 290. The oxide layer 227 is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220_2, the side surfaces of the insulating layer 225_2, the side surfaces of the conductive layer 240_1, and the top and side surfaces of the conductive layer 240_2.
氧化物層227是設置在開口部290內的層，所以較佳為利用CVD法或ALD法形成，更佳為利用ALD法形成。由此，可以以高覆蓋性設置氧化物層227。Since the oxide layer 227 is provided within the opening 290, it is preferably formed by CVD or ALD, and more preferably by ALD, so that the oxide layer 227 can be provided with high coverage.
接著，如圖18A所示，在氧化物層227上依次形成氧化物半導體層230_1、氧化物半導體層230_2。氧化物半導體層230_1較佳為以沿著氧化物層227的頂面且具有儘量均勻的厚度的方式形成。藉由利用ALD法沉積，可以以高可控性沉積較薄的膜。因此，氧化物半導體層230_1較佳為利用ALD法沉積。Next, as shown in FIG18A , oxide semiconductor layer 230_1 and oxide semiconductor layer 230_2 are sequentially formed on oxide layer 227. Oxide semiconductor layer 230_1 is preferably formed along the top surface of oxide layer 227 and with a thickness as uniform as possible. ALD deposition allows for the deposition of thin films with high controllability. Therefore, oxide semiconductor layer 230_1 is preferably deposited using ALD.
此外，當氧化物半導體層230的結晶性高時，氧化物半導體層230中的雜質的擴散得到抑制，因此電晶體的電特性不容易變動，從而可以提高可靠性。藉由利用濺射法沉積氧化物半導體層230_2，與利用ALD法的情況相比，容易形成結晶性高的層，所以是較佳的。Furthermore, when the oxide semiconductor layer 230 has high crystallinity, the diffusion of impurities in the oxide semiconductor layer 230 is suppressed, thus minimizing fluctuations in the transistor's electrical characteristics and improving reliability. Depositing the oxide semiconductor layer 230_2 by sputtering is preferred because it facilitates the formation of a highly crystalline layer compared to ALD.
例如，在利用濺射法形成氧化物半導體層230_2的情況下，作為濺射氣體使用氧或者氧和稀有氣體的混合氣體。藉由提高濺射氣體所包含的氧的比率，可以增加沉積的氧化膜中的過量氧。此外，在利用濺射法沉積上述氧化膜的情況下，可以使用In-M-Zn氧化物靶材等。For example, when forming the oxide semiconductor layer 230_2 by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the oxygen content of the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the oxide film by sputtering, an In-M-Zn oxide target or the like can be used.
在使用濺射法形成氧化物半導體層230_2的情況下，藉由在包含在濺射氣體中的氧的比率為超過30%且100%以下，較佳為70%以上且100%以下的條件下進行沉積，可以形成氧過剩型氧化物半導體。將氧過剩型氧化物半導體用於通道形成區域的電晶體可以得到比較高的可靠性。注意，本發明的一個實施方式不侷限於此。當將濺射氣體所包含的氧的比率設定為1%以上且30%以下，較佳為設定為5%以上且20%以下時，可以形成氧缺乏型氧化物半導體。將氧缺乏型氧化物半導體用於通道形成區域的電晶體可以具有較高的場效移動率。此外，藉由在加熱基板的同時進行沉積，可以提高氧化物半導體層的結晶性。When the oxide semiconductor layer 230_2 is formed by sputtering, an oxygen-excess oxide semiconductor can be formed by performing deposition under conditions where the ratio of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably greater than 70% and less than 100%. A transistor using an oxygen-excess oxide semiconductor in a channel formation region can achieve relatively high reliability. Note that one embodiment of the present invention is not limited thereto. When the ratio of oxygen contained in the sputtering gas is set to greater than 1% and less than 30%, preferably greater than 5% and less than 20%, an oxygen-deficient oxide semiconductor can be formed. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have a higher field-effect mobility. Furthermore, by heating the substrate during deposition, the crystallinity of the oxide semiconductor layer can be improved.
另外，在利用濺射法形成氧化物半導體層230_2時，有時由於被形成面受到的損傷而導電層220所包含的元素混入到氧化物半導體層230的導電層220附近的區域。在該元素為錫的情況下，由於錫混入到氧化物半導體層230的導電層220附近的區域而產生載子，導電層220可以與氧化物半導體層230接觸，由此可以實現電特性良好的電晶體。與此同樣，導電層240所包含的元素有時混入到氧化物半導體層230的導電層240附近的區域。由此，導電層240可以與氧化物半導體層230接觸，而可以實現電特性良好的電晶體。Furthermore, when forming oxide semiconductor layer 230_2 by sputtering, damage to the surface being formed may cause elements contained in conductive layer 220 to infiltrate into the region of oxide semiconductor layer 230 near conductive layer 220. In the case of tin, the infiltration of tin into the region of oxide semiconductor layer 230 near conductive layer 220 generates carriers, allowing conductive layer 220 to contact oxide semiconductor layer 230, thereby realizing a transistor with excellent electrical characteristics. Similarly, elements contained in conductive layer 240 may infiltrate into the region of oxide semiconductor layer 230 near conductive layer 240. Thus, the conductive layer 240 can contact the oxide semiconductor layer 230, thereby realizing a transistor with good electrical characteristics.
此外，關於氧化物半導體層230的製造方法，可以參照實施方式2的記載。In addition, regarding the manufacturing method of the oxide semiconductor layer 230, reference can be made to the description of Embodiment 2.
在本實施方式中，作為氧化物層227利用熱ALD法沉積氧化鎵膜，作為氧化物半導體層230_1利用熱ALD法沉積氧化銦膜，作為氧化物半導體層230_2利用濺射法沉積In-Ga-Zn氧化物膜。此時，氧化物層227可以使用包含鎵的前驅物及氧化劑且利用ALD法沉積，氧化物半導體層230_1可以使用包含銦的前驅物及包含臭氧的氧化劑且利用ALD法沉積，氧化物半導體層230_2可以使用包含銦及鎵的濺射靶材且利用濺射法沉積。In this embodiment, a gallium oxide film is deposited as oxide layer 227 using thermal ALD, an indium oxide film is deposited as oxide semiconductor layer 230_1 using thermal ALD, and an In—Ga—Zn oxide film is deposited as oxide semiconductor layer 230_2 using sputtering. In this case, oxide layer 227 can be deposited using a precursor containing gallium and an oxidizing agent using ALD, oxide semiconductor layer 230_1 can be deposited using a precursor containing indium and an oxidizing agent containing ozone using ALD, and oxide semiconductor layer 230_2 can be deposited using a sputtering target containing indium and gallium using sputtering.
利用ALD法沉積的氧化銦膜的蝕刻速率低，因此在將氧化銦膜用於氧化物半導體層230_1時，可以實現可靠性高的電晶體。The indium oxide film deposited using the ALD method has a low etching rate. Therefore, when the indium oxide film is used for the oxide semiconductor layer 230_1, a highly reliable transistor can be realized.
另外，氧化物層227及氧化物半導體層230_1較佳為以不暴露於大氣的方式連續地沉積。藉由以不暴露於大氣的方式連續地沉積氧化物層227及氧化物半導體層230_1，可以提高產生率。此外，可以減少引入到氧化物層227與氧化物半導體層230_1的介面及其附近的雜質（典型的為水分等）。Furthermore, the oxide layer 227 and the oxide semiconductor layer 230_1 are preferably deposited continuously without being exposed to the atmosphere. By depositing the oxide layer 227 and the oxide semiconductor layer 230_1 continuously without being exposed to the atmosphere, productivity can be improved. Furthermore, impurities (typically moisture, etc.) introduced into and near the interface between the oxide layer 227 and the oxide semiconductor layer 230_1 can be reduced.
此外，也可以在沉積氧化物半導體層230_1之後進行對氧化物半導體層230_1供應氧的處理。由此，可以藉由該處理之後施加到的熱等將氧供應到氧化物半導體層230。注意，關於供應氧的處理的詳細內容，可以參照上述記載。Alternatively, a process for supplying oxygen to the oxide semiconductor layer 230_1 may be performed after the oxide semiconductor layer 230_1 is deposited. Thus, oxygen can be supplied to the oxide semiconductor layer 230 by heat or the like applied after the process. For details on the process for supplying oxygen, refer to the above description.
接著，較佳為進行加熱處理。藉由進行加熱處理可以減少氧化物半導體層230（尤其是氧化物半導體層230_1）所包含的氫或水等雜質。加熱處理的溫度較佳為100℃以上且650℃以下，更佳為250℃以上且600℃以下，進一步較佳為300℃以上且500℃以下或350℃以上且550℃以下。加熱處理的詳細內容可以參照上述記載。Next, a heat treatment is preferably performed. This heat treatment can reduce impurities such as hydrogen and water contained in the oxide semiconductor layer 230 (particularly the oxide semiconductor layer 230_1). The heat treatment temperature is preferably 100°C to 650°C, more preferably 250°C to 600°C, and even more preferably 300°C to 500°C or 350°C to 550°C. Details of the heat treatment can be found in the above description.
此外，在上述加熱處理中使用的氣體較佳為被高度純化。藉由使用高度純化了的氣體進行加熱處理，可以儘可能地防止水分等被氧化物半導體層230吸收。Furthermore, the gas used in the heat treatment is preferably highly purified. By using highly purified gas for the heat treatment, it is possible to prevent moisture and the like from being absorbed by the oxide semiconductor layer 230 as much as possible.
藉由上述加熱處理，可以減少氧化物半導體層230中的碳、氫或水等雜質。如此，藉由減少膜中的雜質，提高氧化物半導體層230的結晶性而可以得到密度更高的緻密結構。因此，可以增大氧化物半導體層230中的晶體區域，可以降低氧化物半導體層230中的晶體區域的面內不均勻。因此，可以降低電晶體的電特性的面內不均勻。The heat treatment described above can reduce impurities such as carbon, hydrogen, and water in the oxide semiconductor layer 230. By reducing impurities in the film, the crystallinity of the oxide semiconductor layer 230 is improved, resulting in a denser structure. Consequently, the crystalline region in the oxide semiconductor layer 230 can be increased, and the in-plane variation in the crystalline region in the oxide semiconductor layer 230 can be reduced. Consequently, in-plane variation in the electrical characteristics of the transistor can be reduced.
此外，在絕緣層225_2和氧化物層227中的至少一個包含氧的情況下，較佳為藉由上述加熱處理從該包含氧的絕緣層向氧化物半導體層230的通道形成區域供應氧。由此，可以減少氧空位及VoH。Furthermore, when at least one of the insulating layer 225_2 and the oxide layer 227 contains oxygen, it is preferable to supply oxygen from the insulating layer containing oxygen to the channel formation region of the oxide semiconductor layer 230 through the above-mentioned heat treatment. This can reduce oxygen vacancies and VoH.
如此，有時將過量氧從與氧化物半導體層230接觸的絕緣層或位於氧化物半導體層230附近的氧化物層供應到氧化物半導體層230。過量氧具有俘獲電子的功能，所以容易形成負電荷。因此，藉由使電晶體的臨界電壓向正方向漂移，可以實現常關閉特性的電晶體。In this way, excess oxygen is sometimes supplied to oxide semiconductor layer 230 from an insulating layer in contact with oxide semiconductor layer 230 or an oxide layer located near oxide semiconductor layer 230. Excess oxygen has the function of trapping electrons, thus easily forming negative charges. Therefore, by shifting the critical voltage of the transistor in the positive direction, a normally-off transistor can be realized.
此外，也可以在沉積氧化物半導體層230_1或氧化物半導體層230_2之後進行微波電漿處理。藉由進行該微波電漿處理，可以降低氧化物半導體層230中的氫或水等雜質的濃度。此外，有時氧化物半導體層230的晶體區域生長。另外，將在實施方式2中說明微波電漿處理的詳細內容。Alternatively, microwave plasma treatment may be performed after depositing oxide semiconductor layer 230_1 or oxide semiconductor layer 230_2. This microwave plasma treatment can reduce the concentration of impurities such as hydrogen and water in oxide semiconductor layer 230. Furthermore, it may cause crystalline regions to grow in oxide semiconductor layer 230. The details of microwave plasma treatment will be described in Embodiment 2.
接著，如圖18B所示，將氧化物半導體層230_2、氧化物半導體層230_1、氧化物層227、導電層240_2及導電層240_1加工為島狀，來使絕緣層280的頂面的一部分露出。氧化物半導體層230_2、氧化物半導體層230_1、氧化物層227、導電層240_2及導電層240_1可以使用相同遮罩來加工。由此，可以減少半導體裝置的製造所需要的遮罩個數，所以是較佳的。Next, as shown in FIG18B , oxide semiconductor layer 230_2, oxide semiconductor layer 230_1, oxide layer 227, conductive layer 240_2, and conductive layer 240_1 are processed into island shapes, exposing a portion of the top surface of insulating layer 280. Oxide semiconductor layer 230_2, oxide semiconductor layer 230_1, oxide layer 227, conductive layer 240_2, and conductive layer 240_1 can be processed using the same mask. This is preferred because it reduces the number of masks required to manufacture semiconductor devices.
此外，為了去除藉由上述加工而附著於氧化物半導體層230的表面的雜質等，較佳為進行洗滌處理。作為洗滌方法，有使用洗滌液等的濕洗滌（也可以稱為濕蝕刻處理）、使用電漿的電漿處理、利用熱處理的洗滌等，也可以適當地組合上述洗滌而進行。Furthermore, a cleaning process is preferably performed to remove impurities and the like adhered to the surface of the oxide semiconductor layer 230 by the above-described processing. Examples of cleaning methods include wet cleaning using a cleaning solution (also referred to as wet etching), plasma treatment using plasma, and cleaning using heat treatment. These cleaning methods may also be appropriately combined.
濕洗滌也可以使用用純水或碳酸水稀釋氨水、草酸、磷酸和氫氟酸中的一個或多個而成的水溶液來進行。另外，濕洗滌也可以使用純水或碳酸水等來進行。或者，也可以進行使用上述水溶液、純水或碳酸水的超聲波洗滌。或者，也可以適當地組合上述洗滌而進行。Wet cleaning can also be performed using an aqueous solution prepared by diluting one or more of ammonia, oxalic acid, phosphoric acid, and hydrofluoric acid with pure water or carbonated water. Alternatively, wet cleaning can be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning using the above aqueous solutions, pure water, or carbonated water can be performed. Alternatively, a suitable combination of the above cleaning methods can be used.
注意，在本說明書等中，有時，將用純水或碳酸水稀釋氫氟酸而成的水溶液稱為稀氫氟酸，將用純水稀釋氨水而成的水溶液稱為稀氨水。另外，根據要去除的雜質、被洗滌的半導體裝置的結構等，適當地調整該水溶液的濃度或溫度等。稀氨水的氨濃度較佳為0.01%以上且5%以下，更佳為0.1%以上且0.5%以下。此外，稀氫氟酸的氟化氫濃度較佳為0.01ppm以上且100ppm以下，更佳為0.1ppm以上且10ppm以下。Note that in this specification and other documents, an aqueous solution of hydrofluoric acid diluted with pure water or carbonated water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia solution. The concentration and temperature of the aqueous solution should be appropriately adjusted depending on the impurities to be removed, the structure of the semiconductor device being cleaned, and other factors. The ammonia concentration of dilute ammonia solution is preferably from 0.01% to 5%, more preferably from 0.1% to 0.5%. Furthermore, the hydrogen fluoride concentration of dilute hydrofluoric acid is preferably from 0.01 ppm to 100 ppm, more preferably from 0.1 ppm to 10 ppm.
超聲波洗滌較佳為採用200kHz以上的頻率，更佳為採用900kHz以上的頻率。藉由採用該頻率，可以降低對氧化物半導體層230等帶來的損傷。Ultrasonic cleaning preferably uses a frequency of 200 kHz or higher, more preferably 900 kHz or higher. By using this frequency, damage to the oxide semiconductor layer 230 and the like can be reduced.
另外，可以進行上述洗滌處理多次，也可以按每個洗滌處理改變洗滌液。例如，作為第一洗滌處理可以進行使用稀氫氟酸或稀氨水的處理，作為第二洗滌處理可以進行使用純水或碳酸水的處理。Furthermore, the above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, the first washing treatment may be performed using dilute hydrofluoric acid or dilute ammonia water, and the second washing treatment may be performed using pure water or carbonated water.
接著，如圖18C所示，以覆蓋開口部290的方式形成絕緣層250。並且，在絕緣層250上形成導電層260_1，在導電層260_1上形成導電層260_2。絕緣層250以與氧化物半導體層230接觸的方式設置。導電層260_1及導電層260_2較佳為以嵌入開口部290的方式設置。注意，根據開口部290的徑及導電層260_1的厚度等，有時導電層260_2不會設置在開口部290內。Next, as shown in FIG18C , insulating layer 250 is formed to cover opening 290. Furthermore, conductive layer 260_1 is formed on insulating layer 250, and conductive layer 260_2 is formed on conductive layer 260_1. Insulating layer 250 is provided so as to contact oxide semiconductor layer 230. Conductive layers 260_1 and 260_2 are preferably provided so as to be embedded in opening 290. Note that, depending on the diameter of opening 290 and the thickness of conductive layer 260_1, conductive layer 260_2 may not be provided within opening 290.
絕緣層250、導電層260_1及導電層260_2都形成在縱橫比高的開口部290內。因此，在沉積絕緣層250、導電層260_1及導電層260_2時，較佳為利用覆蓋性高的沉積方法，更佳為利用CVD法或ALD法等。The insulating layer 250, the conductive layer 260_1, and the conductive layer 260_2 are all formed in the high-aspect-ratio opening 290. Therefore, when depositing the insulating layer 250, the conductive layer 260_1, and the conductive layer 260_2, it is preferable to use a deposition method with high coverage, more preferably CVD or ALD.
較佳為在沉積絕緣層250之後進行微波電漿處理。藉由進行該微波電漿處理，可以降低氧化物半導體層230中的氫或水等雜質的濃度。此外，有時氧化物半導體層230的晶體區域生長。注意，將在實施方式2中說明微波電漿處理的詳細內容。It is preferred to perform microwave plasma treatment after depositing the insulating layer 250. This microwave plasma treatment can reduce the concentration of impurities such as hydrogen and water in the oxide semiconductor layer 230. Furthermore, it may cause crystalline regions to grow in the oxide semiconductor layer 230. The details of the microwave plasma treatment will be described in Embodiment 2.
另外，在絕緣層250具有第四絕緣層、第四絕緣層上的第三絕緣層、第三絕緣層上的第一絕緣層及第一絕緣層上的第二絕緣層的四層結構的情況下，也可以在沉積第三絕緣層之後進行微波電漿處理。並且，也可以在沉積第一絕緣層之後再次進行微波電漿處理。如此，含氧氛圍下的微波電漿處理也可以進行多次（至少兩次以上）。Furthermore, if the insulating layer 250 has a four-layer structure comprising a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, the microwave plasma treatment may be performed after the third insulating layer is deposited. Furthermore, the microwave plasma treatment may be performed again after the first insulating layer is deposited. In this manner, the microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice).
此外，也可以在沉積第三絕緣層之後進行對第三絕緣層供應氧的處理。由此，可以將氧供應到氧化物半導體層230。注意，關於供應氧的處理的詳細內容可以參照上述記載。Alternatively, a process for supplying oxygen to the third insulating layer may be performed after the third insulating layer is deposited. This allows oxygen to be supplied to the oxide semiconductor layer 230. For details on the process for supplying oxygen, refer to the above description.
在本實施方式中，作為絕緣層250，利用ALD法依次沉積氧化鋁膜、氧化矽膜、氧化鉿膜、氮化矽膜。In this embodiment, an aluminum oxide film, a silicon oxide film, a cobalt oxide film, and a silicon nitride film are sequentially deposited as the insulating layer 250 using the ALD method.
如上所述，可以製造本發明的一個實施方式的半導體裝置。As described above, a semiconductor device according to one embodiment of the present invention can be manufactured.
在本實施方式所示的例子中，在沉積絕緣層225的至少一部分、氧化物層227、氧化物半導體層230_1及絕緣層250的至少一部分時，利用ALD法。另外，還示出將氧化矽、氧化鎵、氧化銦、氧化鋁或氧化鉿用於絕緣層225的至少一部分、氧化物層227、氧化物半導體層230_1及絕緣層250的至少一部分的每一個的例子。換言之，絕緣層225的至少一部分、氧化物層227、氧化物半導體層230_1及絕緣層250的至少一部分的每一個使用利用ALD法沉積的氧化物膜形成。並且，該氧化物膜包含氧以及氧以外的一種元素。In the example shown in this embodiment, ALD is used to deposit at least a portion of the insulating layer 225, the oxide layer 227, the oxide semiconductor layer 230_1, and at least a portion of the insulating layer 250. Examples are also shown in which silicon oxide, gallium oxide, indium oxide, aluminum oxide, or barium oxide is used for each of at least a portion of the insulating layer 225, the oxide layer 227, the oxide semiconductor layer 230_1, and at least a portion of the insulating layer 250. In other words, at least a portion of the insulating layer 225, the oxide layer 227, the oxide semiconductor layer 230_1, and at least a portion of the insulating layer 250 are each formed using an oxide film deposited using ALD. Furthermore, the oxide film contains oxygen and an element other than oxygen.
注意，在本說明書等中，包含氧以及氧以外的一種元素的氧化物膜有時被稱為單個氧化物膜。另外，單個氧化物膜是指氧以外的該元素的含有率為95%以上的氧化物膜。Note that in this specification, an oxide film containing oxygen and one element other than oxygen may be referred to as a single oxide film. A single oxide film refers to an oxide film in which the content of the element other than oxygen is 95% or more.
在ALD製程中，將前驅物導入處理室並使前驅物吸附到基板表面。在此，在前驅物吸附到基板表面時，表面化學反應的自停止機制起作用，因此在基板上的前驅物的層上不再吸附前驅物。另外，表面化學反應的自停止機制起作用的基板溫度的適當範圍也被稱為ALD窗（ALD Window）。ALD窗取決於前驅物的溫度特性、蒸氣壓、分解溫度等。也就是說，ALD窗根據每個前驅物而不同。因此，在沉積除了氧以外還包含多種元素的氧化物膜的情況下，需要考慮各前驅物的ALD窗而調整沉積條件。另一方面，在沉積單個氧化物膜的情況下，只要考慮一種前驅物的ALD窗就可以調整沉積條件，因此容易調整沉積條件，從而可以沉積高品質的氧化物膜。In the ALD process, a precursor is introduced into the processing chamber and adsorbed onto the substrate surface. Here, when the precursor is adsorbed onto the substrate surface, the self-stop mechanism of the surface chemical reaction takes effect, so that the precursor is no longer adsorbed on the layer of precursor on the substrate. In addition, the appropriate range of substrate temperature in which the self-stop mechanism of the surface chemical reaction takes effect is also called the ALD window. The ALD window depends on the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor. In other words, the ALD window is different for each precursor. Therefore, when depositing an oxide film containing multiple elements in addition to oxygen, it is necessary to adjust the deposition conditions by considering the ALD window of each precursor. On the other hand, when depositing a single oxide film, the deposition conditions can be adjusted by considering the ALD window of only one precursor. This makes it easy to adjust the deposition conditions, enabling the deposition of high-quality oxide films.
例如，用於氧化物層227的氧化鎵膜較佳為單個氧化物膜。另外，例如，可用於氧化物半導體層230_1的氧化銦膜較佳為單個氧化物膜。For example, the gallium oxide film used for the oxide layer 227 is preferably a single oxide film. Also, for example, the indium oxide film used for the oxide semiconductor layer 230_1 is preferably a single oxide film.
在本發明的一個實施方式的半導體裝置中，藉由將其電阻率比氧化物半導體層高的氧化物層設置在源極電極或汲極電極與氧化物半導體層間，可以提高電晶體的電特性，而可以提高電晶體的可靠性。In a semiconductor device according to an embodiment of the present invention, by providing an oxide layer having a higher resistivity than the oxide semiconductor layer between a source electrode or a drain electrode and the oxide semiconductor layer, the electrical characteristics of the transistor can be improved, thereby improving the reliability of the transistor.
在本發明的一個實施方式的半導體裝置中，藉由使用氫阻擋絕緣層圍繞氧化物半導體層的周圍，並在氧化物半導體層附近設置具有俘獲或固定氫的功能的絕緣層和具有包含過量氧的區域的絕緣層中的一者或兩者，可以減少氧化物半導體層中的氧空位和雜質中的一者或兩者。因此，可以提高電晶體的電特性，而可以提高電晶體的可靠性。In a semiconductor device according to one embodiment of the present invention, a hydrogen-blocking insulating layer is provided around an oxide semiconductor layer, and one or both of an insulating layer capable of trapping or fixing hydrogen and an insulating layer having a region containing excess oxygen are provided near the oxide semiconductor layer. This reduces one or both of oxygen vacancies and impurities in the oxide semiconductor layer. Consequently, the electrical characteristics of the transistor can be improved, thereby enhancing the reliability of the transistor.
本發明的一個實施方式的半導體裝置具有產生在源極電極和汲極電極中的另一個與閘極電極間的寄生電容以及產生在源極電極和汲極電極中的另一個與閘極佈線間的寄生電容得到降低的結構。因此，可以提高使用該半導體裝置的電路的頻率特性。A semiconductor device according to one embodiment of the present invention has a structure in which parasitic capacitance generated between the other of the source and drain electrodes and the gate electrode, and parasitic capacitance generated between the other of the source and drain electrodes and the gate wiring, is reduced. Consequently, the frequency characteristics of a circuit using the semiconductor device can be improved.
本實施方式可以與其他實施方式或實施例適當地組合。此外，在本說明書中，在一個實施方式中示出多個結構例子的情況下，可以適當地組合該結構例子。This embodiment can be appropriately combined with other embodiments or examples. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.
實施方式2 在本實施方式中，說明能夠用作電晶體的半導體層的氧化物半導體層。另外，本發明的一個實施方式的氧化物半導體層具有疊層結構。注意，如後面所述，有時難以確認到層疊的膜之間的邊界。Embodiment 2This embodiment describes an oxide semiconductor layer that can be used as a semiconductor layer in a transistor. In one embodiment of the present invention, the oxide semiconductor layer has a stacked structure. Note that, as described later, the boundaries between stacked films may be difficult to identify.
[氧化物半導體層] 本發明的一個實施方式的氧化物半導體層較佳為包含具有結晶性的金屬氧化物。作為具有結晶性的金屬氧化物的結構，例如可以舉出CAAC（c-axis aligned crystalline：c軸配向結晶）結構、多晶（Poly-crystalline）結構、微晶（nc：nano-crystalline）結構。藉由將具有結晶性的金屬氧化物用於氧化物半導體層，可以降低氧化物半導體層中的缺陷態密度。因此，可以提高使用本發明的一個實施方式的氧化物半導體層的電晶體的可靠性，從而可以提高安裝有電晶體的半導體裝置的可靠性。[Oxide Semiconductor Layer]The oxide semiconductor layer of one embodiment of the present invention preferably comprises a crystalline metal oxide. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystalline), polycrystalline (poly-crystalline), and nanocrystalline (nc) structures. Using a crystalline metal oxide for the oxide semiconductor layer can reduce the defect state density in the oxide semiconductor layer. Consequently, the reliability of transistors using the oxide semiconductor layer of one embodiment of the present invention can be improved, thereby improving the reliability of semiconductor devices incorporating the transistors.
本發明的一個實施方式的氧化物半導體層較佳為包含具有CAAC結構的金屬氧化物。CAAC結構是多個微晶（典型的是，多個具有六方晶系晶體結構的微晶）具有c軸配向性且在a-b面上上述多個微晶不配向而連接的晶體結構。當使用高解析度TEM影像（也稱為多波干涉影像）觀察具有CAAC結構的氧化物半導體層的剖面時，可確認到在結晶部中金屬原子排列為層狀。因此，也可以說具有CAAC結構的氧化物半導體層具有層狀結晶部。The oxide semiconductor layer of one embodiment of the present invention preferably comprises a metal oxide having a CAAC structure. A CAAC structure is a crystalline structure in which multiple crystallites (typically, multiple crystallites having a hexagonal crystal structure) have c-axis alignment and are connected without orientation on the a-b plane. High-resolution TEM imaging (also known as multi-wave interference imaging) of a cross-section of an oxide semiconductor layer having a CAAC structure reveals that the metal atoms are arranged in layers within the crystalline portion. Therefore, the oxide semiconductor layer having a CAAC structure can be said to have a layered crystalline portion.
CAAC結構例如以c軸垂直或大致垂直於氧化物半導體層的被形成面或表面的方式形成。在CAAC結構中，金屬原子在平行或大致平行於被形成面的方向上排列為層狀。在具有CAAC結構的區域中，c軸與被形成面所形成的角度較佳為90°±20°以內（70°以上且110°以下），更佳為90°±15°以內（75°以上且105°以下），進一步較佳為90°±10°以內（80°以上且100°以下），更進一步較佳為90°±5°以內（85°以上且95°以下）。The CAAC structure is formed, for example, with the c-axis perpendicular or approximately perpendicular to the formed surface or surface of the oxide semiconductor layer. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or approximately parallel to the formed surface. In the region having the CAAC structure, the angle formed by the c-axis and the formed surface is preferably within 90°±20° (above 70° and below 110°), more preferably within 90°±15° (above 75° and below 105°), further preferably within 90°±10° (above 80° and below 100°), and even more preferably within 90°±5° (above 85° and below 95°).
氧化物半導體層的結晶性例如可以藉由X射線繞射（XRD：X-Ray Diffraction）、TEM或電子繞射（ED：Electron Diffraction）分析。此外，也可以組合多個上述方法進行分析。The crystallinity of the oxide semiconductor layer can be analyzed, for example, using X-ray diffraction (XRD), TEM, or electron diffraction (ED). Furthermore, a combination of these methods can be used.
在氧化物半導體層具有CAAC結構的情況下，在使用TEM影像觀察的氧化物半導體層的剖面中觀察到反映了金屬原子的層狀排列的亮點群（明確而言，排列為層狀的亮點）。明確而言，觀察到在平行或大致平行於被形成面的方向上亮點排列為層狀的狀態。When an oxide semiconductor layer has a CAAC structure, a group of bright spots reflecting the layered arrangement of metal atoms (specifically, bright spots arranged in layers) is observed in a cross-section of the oxide semiconductor layer observed using TEM imaging. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which they are formed.
當對具有CAAC結構的氧化物半導體層進行電子繞射時，在電子繞射圖案中觀察到表示c軸配向性的斑點（亮點）。When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright spots) indicating c-axis alignment are observed in the electron diffraction pattern.
此外，藉由對TEM影像進行快速傅立葉變換（FFT：Fast Fourier Transform）處理而得到的FFT圖案反映與電子繞射圖案同樣的倒易空間資訊。Furthermore, the FFT pattern obtained by performing Fast Fourier Transform (FFT) processing on TEM images reflects the same reciprocal spatial information as the electron diffraction pattern.
藉由取得具有CAAC結構的氧化物半導體層的剖面TEM影像，並對剖面TEM影像中的各區域進行FFT處理來製作FFT圖案，可以根據所製作的FFT圖案算出各區域的晶軸方向。明確而言，在所製作的FFT圖案中觀察到的斑點中，將亮度高且離中心有大致相等的距離的兩個斑點連接的線段的方向為晶軸方向。可以將從FFT圖案算出的各區域的晶軸方向與被形成面所形成的角度較佳為70°以上且110°以下（90°±20°以內），更佳為75°以上且105°以下（90°±15°以內），進一步較佳為80°以上且100°以下（90°±10°以內），更進一步較佳為85°以上且95°以下（90°±5°以內）的區域看作CAAC結構。By obtaining a cross-sectional TEM image of an oxide semiconductor layer with a CAAC structure and performing FFT processing on each region in the cross-sectional TEM image to create an FFT pattern, the crystal axis direction of each region can be calculated from the generated FFT pattern. Specifically, the direction of the crystal axis is the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center of the spots observed in the generated FFT pattern. The angle formed by the crystal axis direction of each region calculated from the FFT pattern and the formed surface is preferably greater than 70° and less than 110° (within 90°±20°), more preferably greater than 75° and less than 105° (within 90°±15°), further preferably greater than 80° and less than 100° (within 90°±10°), and further preferably greater than 85° and less than 95° (within 90°±5°) as a CAAC structure.
當使用TEM影像從垂直於被形成面的方向觀察具有CAAC結構的氧化物半導體層時，在a-b面上觀察到三角形狀或六邊形狀的原子排列且具有結晶性。When an oxide semiconductor layer having a CAAC structure is observed using TEM images from a direction perpendicular to the formed surface, triangular or hexagonal atomic arrangements are observed on the a-b plane, indicating crystallinity.
注意，對氧化物半導體層所包含的金屬氧化物的結晶性沒有特別的限制。例如，氧化物半導體層有時包含非晶半導體（具有非晶結構的半導體）、單晶半導體（具有單晶結構的半導體）和單晶以外的具有結晶性的半導體（微晶半導體、多晶半導體或部分具有晶體區域的半導體）中的一個以上。當氧化物半導體層具有結晶性時，有時可以抑制電晶體特性的劣化。Note that there are no particular restrictions on the crystallinity of the metal oxide contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having partial crystalline regions). Crystallinity in the oxide semiconductor layer may suppress degradation of transistor characteristics.
根據本發明的一個實施方式的金屬氧化物較佳為至少包含銦（In）或鋅（Zn），尤其較佳為包含銦作為主要成分。此外，金屬氧化物較佳為包含選自銦、元素M和鋅中的兩個或三個，尤其較佳為包含銦及鋅作為主要成分。在此，金屬氧化物可以包含銦及鋅作為主要成分，還可以包含元素M。在金屬氧化物所包含的元素M為鎵的情況下，根據本發明的一個實施方式的金屬氧化物較佳為包含選自銦、鎵和鋅中的一個或多個。另外，在本說明書等中，有時將金屬元素與半金屬元素統稱為“金屬元素”，本說明書等所記載的“金屬元素”有時包括半金屬元素。The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components and may also contain element M. When element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In addition, in this specification, etc., metallic elements and semimetallic elements may be collectively referred to as "metallic elements," and the "metallic elements" described in this specification, etc. may include semimetallic elements.
作為本發明的一個實施方式的金屬氧化物，例如可以使用In-Zn氧化物、ITO、銦鈦氧化物（In-Ti氧化物）、In-Ga氧化物、銦鎵鋁氧化物（In-Ga-Al氧化物）、銦鎵錫氧化物（In-Ga-Sn氧化物，也記為IGTO）、銦鋁鋅氧化物（In-Al-Zn氧化物，也記為IAZO）、銦錫鋅氧化物（也記為In-Sn-Zn氧化物）、銦鈦鋅氧化物（In-Ti-Zn氧化物）、In-Ga-Zn氧化物、ITSO、銦鎵錫鋅氧化物（In-Ga-Sn-Zn氧化物，也記為IGZTO）、銦鎵鋁鋅氧化物（In-Ga-Al-Zn氧化物，也記為IGAZO或IAGZO）等。或者，還可以使用Ga-Zn氧化物、Al-Zn氧化物、鎵錫氧化物（Ga-Sn氧化物）、鋁錫氧化物（Al-Sn氧化物）等。此外，作為本發明的一個實施方式的金屬氧化物，可以使用氧化銦。此外，作為本發明的一個實施方式的金屬氧化物，可以使用氧化鎵、氧化鋅等。As a metal oxide of an embodiment of the present invention, for example, In-Zn oxide, ITO, indium titanium oxide (In-Ti oxide), In-Ga oxide, indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (also referred to as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), In-Ga-Zn oxide, ITSO, indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, Ga-Zn oxide, Al-Zn oxide, gallium-tin oxide (Ga-Sn oxide), aluminum-tin oxide (Al-Sn oxide), etc. may be used. Furthermore, indium oxide may be used as the metal oxide in one embodiment of the present invention. Furthermore, gallium oxide, zinc oxide, etc. may be used as the metal oxide in one embodiment of the present invention.
藉由提高金屬氧化物的銦含有率，電晶體可以獲得大通態電流及高頻率特性。By increasing the indium content of metal oxide, the transistor can achieve high on-state current and high frequency characteristics.
注意，金屬氧化物也可以包含元素週期表中的週期數大的金屬元素中的一種或多種代替銦。或者，金屬氧化物也可以除了銦以外還包含元素週期表中的週期數大的金屬元素中的一種或多種。有金屬元素的軌域的重疊越大金屬氧化物中的載子傳導越大的趨勢。因此，藉由包含元素週期表中的週期數大的金屬元素，有時可以提高電晶體的場效移動率。作為元素週期表中的週期數大的金屬元素，可以舉出屬於第5週期的金屬元素以及屬於第6週期的金屬元素等。作為該金屬元素，明確而言，可以舉出釔、鋯、銀、鎘、錫、銻、鋇、鉛、鉍、鑭、鈰、鐠、釹、鉕、釤及銪等。注意，鑭、鈰、鐠、釹、鉕、釤及銪被稱為輕稀土元素。Note that the metal oxide may contain one or more metal elements with large periods in the periodic table of elements instead of indium. Alternatively, the metal oxide may contain one or more metal elements with large periods in the periodic table of elements in addition to indium. The greater the overlap of the metal element domains, the greater the carrier conduction in the metal oxide. Therefore, by including metal elements with large periods in the periodic table of elements, the field-effect mobility of the transistor can sometimes be improved. Examples of metal elements with large periods in the periodic table of elements include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, examples of these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lutetium, ruthenium, erbium, neodymium, bismuth, samarium, and mechanium. Note that lutetium, ruthenium, erbium, neodymium, bismuth, samarium, and mechanium are known as light rare earth elements.
此外，金屬氧化物也可以包含非金屬元素中的一種或多種。在金屬氧化物包含非金屬元素時有時可以提高電晶體的場效移動率。作為非金屬元素，例如可以舉出碳、氮、磷、硫、硒、氟、氯、溴及氫等。Furthermore, the metal oxide may also contain one or more non-metallic elements. Including non-metallic elements in the metal oxide can sometimes improve the field-effect mobility of the transistor. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
此外，藉由提高金屬氧化物中的鋅的含有率，可以使金屬氧化物具有高結晶性，由此可以抑制金屬氧化物中的雜質的擴散。由此，電晶體的電特性的變動得到抑制，而可以提高可靠性。Furthermore, increasing the zinc content in the metal oxide can enhance its crystallinity, thereby suppressing the diffusion of impurities within the metal oxide. This reduces fluctuations in the transistor's electrical characteristics and improves reliability.
此外，藉由提高金屬氧化物中的元素M的含有率，可以抑制金屬氧化物中形成氧空位。因此，起因於氧空位的載子生成得到抑制，由此可以實現關態電流小的電晶體。此外，電晶體的電特性的變動得到抑制而可以提高可靠性。Furthermore, increasing the content of element M in the metal oxide can suppress the formation of oxygen vacancies in the metal oxide. This suppresses carrier generation due to oxygen vacancies, enabling the realization of a transistor with a low off-state current. Furthermore, fluctuations in the transistor's electrical characteristics are suppressed, improving reliability.
在本實施方式中，作為金屬氧化物，有時以In-M-Zn氧化物為例進行說明。In this embodiment, In-M-Zn oxide is sometimes used as an example of a metal oxide for explanation.
[氧化物半導體層的製造方法] 本發明的一個實施方式的氧化物半導體層例如可以藉由使用兩種沉積方法形成金屬氧化物來製造。也就是說，本發明的一個實施方式的氧化物半導體層可以藉由使用第一沉積方法及第二沉積方法形成金屬氧化物來製造。[Method for Manufacturing an Oxide Semiconductor Layer]The oxide semiconductor layer according to one embodiment of the present invention can be manufactured by forming a metal oxide using two deposition methods. That is, the oxide semiconductor layer according to one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method.
作為一個例子，在氧化物半導體層具有第一層及第一層上的第二層的兩層結構的情況下，可以藉由在被形成面上利用第二沉積方法形成第一層之後在其上利用第一沉積方法形成第二層而製造該氧化物半導體層。As an example, in the case where the oxide semiconductor layer has a two-layer structure of a first layer and a second layer on the first layer, the oxide semiconductor layer can be manufactured by forming the first layer on the surface to be formed using the second deposition method and then forming the second layer thereon using the first deposition method.
另外，作為一個例子，在氧化物半導體層具有第一層、第一層上的第二層及第二層上的第三層的三層結構的情況下，可以藉由在被形成面上利用第二沉積方法形成第一層之後利用第一沉積方法形成第二層且利用第二沉積方法形成第三層而製造該氧化物半導體層。In addition, as an example, in the case where the oxide semiconductor layer has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the oxide semiconductor layer can be manufactured by forming the first layer on the formed surface using a second deposition method, then forming the second layer using a first deposition method and forming the third layer using a second deposition method.
作為第二沉積方法，較佳為利用與第一沉積方法相比對被形成面帶來的損傷小的沉積方法。由此，可以抑制在氧化物半導體層與作為該氧化物半導體層的被形成面的層的介面形成混合層。另外，可以抑制矽等雜質混入到形成在第一層上的第二層，由此有時可以進一步提高氧化物半導體層的結晶性。As the second deposition method, it is preferable to utilize a deposition method that causes less damage to the surface being formed than the first deposition method. This method can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer serving as the surface on which the oxide semiconductor layer is formed. Furthermore, it can suppress the incorporation of impurities such as silicon into the second layer formed on the first layer, thereby further improving the crystallinity of the oxide semiconductor layer.
作為第二沉積方法，例如可以舉出ALD法、CVD法、MBE法等。另外，作為CVD法，可以舉出電漿CVD（PECVD：Plasma Enhanced CVD）法、熱CVD法、光CVD法、MOCVD法等。MBE法是使具有反映基板的晶系的晶體結構的薄膜生長的沉積方法，可以說是對被形成面的損傷少的沉積方法之一。此外，作為第二沉積方法，可以使用濕處理。濕處理是對被形成面的損傷少的沉積方法之一。作為濕處理，例如可以舉出噴塗法等。Examples of the second deposition method include ALD, CVD, and MBE. CVD methods include plasma CVD (PECVD), thermal CVD, optical CVD, and MOCVD. MBE is a deposition method that grows thin films with a crystalline structure that reflects the substrate's crystal system and is considered one of the deposition methods that causes minimal damage to the surface being formed. Furthermore, wet treatment can be used as the second deposition method. Wet treatment is one of the deposition methods that causes minimal damage to the surface being formed. Examples of wet treatment methods include spray coating.
作為第一沉積方法，較佳為採用能夠沉積具有結晶性的金屬氧化物的方法。此時沉積的金屬氧化物尤其較佳為具有CAAC結構。作為第一沉積方法，例如可以舉出濺射法、PLD法等。利用濺射法沉積的金屬氧化物容易具有結晶性，因此濺射法適合用作第一沉積方法。As the first deposition method, it is preferred to employ a method capable of depositing a crystalline metal oxide. In this case, the deposited metal oxide preferably has a CAAC structure. Examples of first deposition methods include sputtering and PLD. Metal oxides deposited using sputtering tend to crystallize, making sputtering a suitable first deposition method.
注意，當在被形成面上利用第一沉積方法形成金屬氧化物時，有時因被形成面受到的損傷而發生金屬氧化物的成分與作為被形成面的層的成分的合金化。在發生合金化的情況下，有時在該金屬氧化物與作為被形成面的層的介面形成混合層。該混合層可以說是合金化區域。此外，混合層的形成可以說是合金化。Note that when a metal oxide is formed on a target surface using the first deposition method, damage to the target surface may cause alloying between the metal oxide components and the target layer. When alloying occurs, a mixed layer may form at the interface between the metal oxide and the target layer. This mixed layer can be considered an alloyed region. Furthermore, the formation of the mixed layer can be considered alloying.
例如，在作為第一沉積方法利用濺射法的情況下，有時由於從靶材等釋放的粒子（也稱為濺射粒子）或由濺射粒子等施加到基板一側的能量等而形成混合層。明確而言，在以氧化矽膜等包含矽的絕緣層為被形成面而利用第一沉積方法沉積金屬氧化物的情況下，有矽混入到金屬氧化物中的擔憂。在矽等雜質混入到金屬氧化物時，有可能金屬氧化物的結晶化受阻。另外，在將混入有雜質的氧化物半導體層用於電晶體時，有可能對電晶體的初始特性或可靠性帶來負面影響。另外，在進行後述的熱處理的情況下，也難以提高合金化區域的結晶性。For example, when sputtering is used as the primary deposition method, a mixed layer may form due to particles released from a target (also called sputtered particles) or energy applied to the substrate by the sputtered particles. Specifically, when a metal oxide is deposited using the primary deposition method on an insulating layer containing silicon, such as a silicon oxide film, there is a concern that silicon may be mixed into the metal oxide. When impurities such as silicon are mixed into the metal oxide, crystallization of the metal oxide may be hindered. Furthermore, when an oxide semiconductor layer containing impurities is used in a transistor, it may negatively impact the transistor's initial characteristics and reliability. Furthermore, even when heat treatment described later is performed, it is difficult to improve the crystallinity of the alloyed region.
於是，如上所述，藉由在利用第一沉積方法形成金屬氧化物之前利用第二沉積方法形成金屬氧化物，可以抑制雜質混入到氧化物半導體層。此外，還可以抑制合金化。因此，可以提高電晶體的初始特性及可靠性。此外，可以進一步提高氧化物半導體層的結晶性。Therefore, as described above, by forming the metal oxide using the second deposition method before forming the metal oxide using the first deposition method, the incorporation of impurities into the oxide semiconductor layer can be suppressed. Furthermore, alloying can be suppressed. Consequently, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor layer can be further enhanced.
與濺射法相比，ALD法可以抑制對被形成面帶來的損傷，所以適合用作第二沉積方法。另外，ALD法是其覆蓋性比濺射法高的沉積方法，藉由作為第一層及第三層的沉積方法利用ALD法，可以提高氧化物半導體層的覆蓋性。因此，可以使用氧化物半導體層良好地覆蓋縱橫比高的步階及開口部等上。Compared to sputtering, ALD minimizes damage to the surface being deposited, making it suitable for use as a secondary deposition method. Furthermore, ALD offers higher coverage than sputtering. By utilizing ALD for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Consequently, the oxide semiconductor layer can effectively cover high-aspect-ratio steps and openings.
在此，說明作為第一層或第三層利用ALD法形成In-M-Zn氧化物的方法。Here, a method of forming In-M-Zn oxide as the first layer or the third layer using the ALD method is described.
首先，將包括包含銦的前驅物的源氣體引入反應室（也稱為處理室），並使該前驅物吸附到被形成面。接著，將作為反應物的氧化劑引入反應室，並使其與吸附的前驅物起反應，並且在使銦吸附到基板的狀態下使銦以外的成分脫離，由此形成銦與氧鍵合的層。First, a source gas containing a precursor containing indium is introduced into a reaction chamber (also called a processing chamber), and the precursor is adsorbed onto the substrate. Next, an oxidizing agent is introduced into the reaction chamber and reacts with the adsorbed precursor. While indium is adsorbed onto the substrate, components other than indium are removed, forming a layer of indium and oxygen bonds.
接著，將包括包含元素M的前驅物的源氣體引入反應室，並使其吸附到銦與氧鍵合的層上。然後，將作為反應物的氧化劑引入反應室，並使其與吸附的前驅物起反應，並且在使元素M吸附到基板的狀態下使元素M以外的成分脫離，由此形成元素M與氧鍵合的層。Next, a source gas containing a precursor containing element M is introduced into the reaction chamber and adsorbed onto the layer where indium and oxygen are bonded. An oxidizing agent is then introduced into the reaction chamber as a reactant and reacts with the adsorbed precursor. While element M is adsorbed onto the substrate, components other than element M are desorbed, thereby forming a layer where element M and oxygen are bonded.
接著，將包括包含鋅的前驅物的源氣體引入反應室，並使其吸附到元素M與氧鍵合的層上。然後，將作為反應物的氧化劑引入反應室，並使其與吸附的前驅物起反應，並且在使鋅吸附到基板的狀態下使鋅以外的成分脫離，由此形成鋅與氧鍵合的層。Next, a source gas containing a precursor containing zinc is introduced into the reaction chamber and adsorbed onto the layer where the element M is bonded to oxygen. An oxidizing agent is then introduced into the reaction chamber as a reactant and reacts with the adsorbed precursor. While zinc is adsorbed on the substrate, components other than zinc are desorbed, thereby forming a layer where zinc is bonded to oxygen.
藉由重複進行上述方法，可以在作為被形成面的層上利用ALD法形成In-M-Zn氧化物作為氧化物半導體層。By repeating the above method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on the layer to be formed using the ALD method.
在利用ALD法形成氧化物半導體層的情況下，作為氧化劑可以使用臭氧（O3）、氧（O2）、水（H2O）等。藉由使用不包含氫的臭氧（O3）、氧（O2）等作為氧化劑，可以減少混入到氧化物半導體層的氫量。When forming an oxide semiconductor layer using ALD, ozone (O3 ), oxygen (O2 ), water (H2 O), etc. can be used as an oxidizing agent. By using hydrogen-free ozone (O3 ) or oxygen (O2 ) as an oxidizing agent, the amount of hydrogen incorporated into the oxide semiconductor layer can be reduced.
在此，將前驅物引入反應室時的基板加熱的溫度設為第一溫度，將氧化劑引入反應室時的基板加熱的溫度設為第二溫度。Here, the temperature at which the substrate is heated when the precursor is introduced into the reaction chamber is set as the first temperature, and the temperature at which the substrate is heated when the oxidizing agent is introduced into the reaction chamber is set as the second temperature.
第一溫度較佳為對應於前驅物的分解溫度的溫度。在此，在利用熱ALD法的情況下，第一溫度例如為100℃以上且350℃以下，較佳為150℃以上且300℃以下，在上述熱ALD法中作為包含銦的前驅物使用三乙基銦（TEI），作為包含鎵的前驅物使用三乙基鎵（TEG），且作為包含鋅的前驅物使用二乙基鋅。The first temperature is preferably a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method, the first temperature is, for example, 100°C to 350°C, preferably 150°C to 300°C. In the thermal ALD method, triethylindium (TEI) is used as a precursor containing indium, triethylgallium (TEG) is used as a precursor containing gallium, and diethylzinc is used as a precursor containing zinc.
注意，第二溫度較佳為比第一溫度高。例如，在氧化劑包含臭氧的情況下，第二溫度較佳為高於200℃且小於450℃，更佳為250℃以上且400℃以下，進一步較佳為300℃以上且350℃以下。藉由採用這種結構，可以降低氧化物半導體層中的氫濃度。此外，藉由使第一溫度低於第二溫度，可以抑制因前驅物的分解而產生的微粒。Note that the second temperature is preferably higher than the first temperature. For example, when the oxidizing agent includes ozone, the second temperature is preferably higher than 200°C and lower than 450°C, more preferably higher than 250°C and lower than 400°C, and even more preferably higher than 300°C and lower than 350°C. This structure reduces the hydrogen concentration in the oxide semiconductor layer. Furthermore, by keeping the first temperature lower than the second temperature, the generation of particles due to the decomposition of the precursor can be suppressed.
引入前驅物的反應室較佳為與引入氧化劑的反應室相同。藉由採用這種結構，可以沉積膜而不需要基板的搬出和搬入，由此可以提高產生率。另外，引入前驅物的反應室也可以與引入氧化劑的反應室不同。藉由準備採用第一溫度的第一反應室和採用第二溫度的第二反應室，可以保持第一溫度和第二溫度。因此，容易進行溫度控制，從而可以提高工作效率及安全性。The reaction chamber for introducing the precursor is preferably the same as the reaction chamber for introducing the oxidant. This structure allows film deposition without moving the substrate in and out, thereby improving productivity. Alternatively, the reaction chamber for introducing the precursor can be different from the reaction chamber for introducing the oxidant. By preparing a first reaction chamber for a first temperature and a second reaction chamber for a second temperature, the first and second temperatures can be maintained. This facilitates temperature control, improving both efficiency and safety.
在上述中，較佳的是，在使前驅物吸附之後停止包括前驅物的源氣體的引入，並且在反應室內進行吹掃之後從反應室排除剩餘的前驅物及反應生成物等。另外，在上述中，較佳的是，在使吸附的前驅物與氧化劑起反應之後停止氧化劑的引入，並且在反應室內進行吹掃之後從反應室排除剩餘的反應物及反應生成物等。In the above, it is preferred that after the precursor is adsorbed, the introduction of the source gas including the precursor is stopped, and after the reaction chamber is purged, the remaining precursor and reaction products are removed from the reaction chamber. Furthermore, in the above, it is preferred that after the adsorbed precursor reacts with the oxidant, the introduction of the oxidant is stopped, and after the reaction chamber is purged, the remaining reactant and reaction products are removed from the reaction chamber.
另外，在本說明書等的記載中沒有特別說明時，在作為反應物或氧化劑使用臭氧、氧、水的情況下它們不侷限處於氣體或分子的狀態，也處於電漿狀態、自由基狀態及離子狀態。In addition, unless otherwise specified in the description of this specification, when ozone, oxygen, or water is used as a reactant or oxidant, they are not limited to being in a gaseous or molecular state, but may also be in a plasma state, a radical state, or an ionic state.
藉由採用上述結構，可以將混合層的厚度減薄，或者可以將合金化區域減薄到觀察不到的厚度。例如，合金化區域的厚度可以為0nm以上且3nm以下，較佳為0nm以上且2nm以下，更佳為0nm以上且1nm以下，進一步較佳為0nm以上且小於0.3nm。By adopting the above structure, the thickness of the mixed layer can be reduced, or the alloyed region can be reduced to an undetectable thickness. For example, the thickness of the alloyed region can be from 0 nm to 3 nm, preferably from 0 nm to 2 nm, more preferably from 0 nm to 1 nm, and even more preferably from 0 nm to less than 0.3 nm.
此外，合金化區域的厚度有時可以藉由對該區域及其周邊利用SIMS或能量色散X射線光譜法（EDX：Energy Dispersive X-ray Spectroscopy）進行組成的線分析來算出。The thickness of the alloyed region can sometimes be calculated by analyzing the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).
例如，以垂直於第一層的被形成面的方向為深度方向，對合金化區域及其周邊進行EDX的線分析。接著，在藉由該分析得到的相對於深度方向的各元素的定量值的分佈中，將是第一層的主要成分而不是作為被形成面的層的主要成分的金屬（在第一層包含In時為In）的定量值達到半值的深度定義為上述區域與第一層的介面的深度（位置）。此外，將是成為被形成面的層的主要成分而不是第一層的主要成分的元素（例如Si）的定量值達到半值的深度定義為上述區域與成為被形成面的層的介面的深度（位置）。藉由上述步驟，可以算出合金化區域的厚度。For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the first layer's surface being formed as the depth direction. Next, within the distribution of quantitative values for each element relative to the depth direction obtained from this analysis, the depth at which the quantitative value for a metal that is a primary component of the first layer but not the primary component of the layer forming the surface (In, if the first layer contains In) reaches half its value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value for an element that is a primary component of the layer forming the surface but not the primary component of the first layer (e.g., Si) reaches half its value is defined as the depth (position) of the interface between the region and the layer forming the surface. Through these steps, the thickness of the alloyed region can be calculated.
在本發明的一個實施方式的氧化物半導體層中，在利用EDX分析觀察合金化區域的厚度的情況下，例如，其厚度為0nm以上且3nm以下，較佳為0nm以上且2nm以下，更佳為0nm以上且1nm以下，進一步較佳為0nm以上且小於0.3nm。In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, its thickness is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm.
此外，例如，在對形成在作為被形成面的氧化矽膜上的氧化物半導體層進行SIMS分析的情況下，以矽濃度達到氧化矽膜中的濃度最大值的50%的深度為介面，並且以矽濃度減少到1.0×1021atoms/cm3，較佳為減少到5.0×1020atoms/cm3，更佳為減少到1.0×1020atoms/cm3的深度與介面的距離為厚度t_s2。厚度t_s2較佳為3nm以下，更佳為2nm以下。Furthermore, for example, when performing SIMS analysis on an oxide semiconductor layer formed on a silicon oxide film serving as a formation surface, the depth at which the silicon concentration reaches 50% of the maximum concentration in the silicon oxide film is defined as the interface. Furthermore, the distance from the depth at which the silicon concentration decreases to 1.0×1021 atoms/cm3 , preferably to 5.0×1020 atoms/cm3 , and more preferably to 1.0×1020 atoms/cm3 , to the interface is defined as thickness t_s2 . Thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.
藉由減薄合金化區域的厚度，從而可以將厚度t_s2設定為上述範圍內的值。By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.
此外，藉由減薄合金化區域，可以在被形成面附近形成CAAC結構。在此，被形成面附近例如是指離氧化物半導體層的被形成面在大致垂直方向上有大於0nm且3nm以下，較佳為大於0nm且為2nm以下，更佳為1nm以上且2nm以下的區域。Furthermore, by thinning the alloyed region, a CAAC structure can be formed near the surface being formed. Here, near the surface being formed refers to, for example, a region approximately perpendicular to the surface being formed of the oxide semiconductor layer that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and even more preferably greater than 1 nm and less than 2 nm.
注意，有時在使用TEM的觀察中可以確認到被形成面附近的CAAC結構。例如，當使用高解析度TEM對氧化物半導體層進行剖面觀察時，在被形成面附近確認到在平行於被形成面的方向上排列為層狀的亮點。Note that CAAC structures can sometimes be observed near the surface being formed during TEM observation. For example, when observing a cross section of an oxide semiconductor layer using a high-resolution TEM, bright spots can be observed near the surface being formed, arranged in a layer parallel to the surface.
作為第一層，例如有時形成具有其結晶性比CAAC結構低的微晶結構或非晶結構的金屬氧化物。藉由在結晶性低的第一層上形成結晶性高的第二層或者在形成第二層之後進行熱處理，有時以第二層為核提高第一層的結晶性。由此，有時可以提高包括與被形成面的介面附近的整個氧化物半導體層的結晶性。For example, a metal oxide having a microcrystalline or amorphous structure with lower crystallinity than a CAAC structure may be formed as the first layer. By forming a highly crystalline second layer on the low-crystalline first layer, or by performing a heat treatment after forming the second layer, the crystallinity of the first layer can be improved using the second layer as a core. This can sometimes improve the crystallinity of the entire oxide semiconductor layer, including near the interface with the surface being formed.
由於第二層具有高結晶性，所以第三層可以以第二層的結晶為核或種進行結晶生長。因此，即使在不使用容易具有結晶性的沉積方法作為第三層的沉積方法的情況下，也可以使第三層結晶化。在此，例如，藉由作為第三層的沉積方法使用覆蓋性比第二層高的沉積方法，可以使整個氧化物半導體層具有高結晶性和高覆蓋性的兩者。Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even when a deposition method that easily achieves crystallinity is not used as the deposition method for the third layer, the third layer can be crystallized. For example, by using a deposition method with higher coverage than the second layer as the deposition method for the third layer, the entire oxide semiconductor layer can have both high crystallinity and high coverage.
此外，藉由設置第一層來減少被形成面的影響，第二層的結晶性得到提高，從而得到極為優異的結晶性。因此，可以期待在以第二層為核或種而結晶化的第三層中也形成結晶性極為優異的層。Furthermore, by providing the first layer, the influence of the surface being formed is reduced, and the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that the third layer, which crystallizes using the second layer as a nucleus or seed, will also have extremely excellent crystallinity.
注意，在將氧化物半導體層用作電晶體的半導體層的情況下，有時作為氧化物半導體層的最上層的第三層與閘極絕緣層接觸。藉由提高與閘極絕緣層接觸的層的結晶性，可以在電晶體處於開啟狀態的情況下提高載子移動率。Note that when an oxide semiconductor layer is used as the semiconductor layer of a transistor, the third layer, which is the topmost layer of the oxide semiconductor layer, may be in contact with the gate insulating layer. By improving the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility can be improved when the transistor is in the on state.
本實施方式的氧化物半導體層可以被用作實施方式1中說明的各電晶體所包括的氧化物半導體層230等。另外，作為被形成面的層相當於實施方式1中說明的導電層220、絕緣層280、導電層240和絕緣層225等中的一個或多個。The oxide semiconductor layer of this embodiment can be used as the oxide semiconductor layer 230 included in each transistor described in Embodiment 1. The layer on which it is formed corresponds to one or more of the conductive layer 220, insulating layer 280, conductive layer 240, and insulating layer 225 described in Embodiment 1.
作為被形成面的層例如為氧化矽膜、氧氮化矽膜、氮化矽膜、氮氧化矽膜、氧化鋁膜、氧化鉿膜等絕緣膜或者氮化鈦膜、鎢膜、ITSO膜等導電膜。此外，作為被形成面的層並不需要具有結晶性。另外，在該層具有結晶性的情況下，該層也可以具有與氧化物半導體層所包含的金屬氧化物的晶格整合性低的晶體結構。Examples of the layer serving as the surface to be formed include insulating films such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxynitride, aluminum oxide, and einsteinium oxide, or conductive films such as titanium nitride, tungsten, and ITSO. Furthermore, the layer serving as the surface to be formed does not necessarily need to be crystalline. Furthermore, if the layer is crystalline, it may have a crystalline structure with low lattice compatibility with the metal oxide contained in the oxide semiconductor layer.
再者，在形成氧化物半導體層之後，較佳為進行熱處理。藉由進行熱處理，可以提高氧化物半導體層的結晶性。在此，熱處理不侷限於加熱處理。例如，也可以為在製程中施加的熱等。After forming the oxide semiconductor layer, it is preferably subjected to heat treatment. This heat treatment can improve the crystallinity of the oxide semiconductor layer. The heat treatment is not limited to heat treatment. For example, it can also be heat applied during the manufacturing process.
較佳為在形成第一層之後進行微波電漿處理。Preferably, the microwave plasma treatment is performed after forming the first layer.
在本說明書等中，微波是指頻率為300MHz以上且300GHz以下的電磁波。另外，微波電漿處理例如是指使用包括利用微波產生高密度電漿的電源的裝置的處理。另外，微波電漿處理也可以說是微波激發高密度電漿處理。In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower. Furthermore, microwave plasma treatment, for example, refers to treatment using an apparatus that includes a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be referred to as microwave-excited high-density plasma treatment.
藉由在含氧氛圍下進行微波電漿處理，可以降低氧化物半導體層230中的雜質濃度。另外，作為雜質，尤其可以舉出氫及碳。另外，上面示出對金屬氧化物進行含氧氛圍下的微波電漿處理的例子，但是不侷限於此。例如，也可以對設置在金屬氧化物附近的絕緣膜，更具體地為氧化矽膜進行含氧氛圍下的微波電漿處理。另外，有時由於藉由微波電漿處理的熱而氧化物半導體層的結晶性得到提高。By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the oxide semiconductor layer 230 can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates microwave plasma treatment of a metal oxide in an oxygen-containing atmosphere, the present invention is not limited thereto. For example, microwave plasma treatment of an insulating film, more specifically a silicon oxide film, disposed near the metal oxide can also be performed in an oxygen-containing atmosphere. Furthermore, the heat generated by the microwave plasma treatment may improve the crystallinity of the oxide semiconductor layer.
微波電漿處理較佳為在減壓下進行，其壓力較佳為10Pa以上且1000Pa以下，更佳為50Pa以上且700Pa以下，進一步較佳為100Pa以上且400Pa以下。另外，處理溫度較佳為室溫（25℃）以上且750℃以下，更佳為300℃以上且500℃以下，可以為400℃以上且450℃以下。Microwave plasma treatment is preferably performed under reduced pressure, preferably 10 Pa to 1000 Pa, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. Furthermore, the treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.
在進行微波電漿處理時，也可以對基板進行加熱。較佳為將基板的加熱溫度設為室溫（例如為25℃）以上、100℃以上、200℃以上、300℃以上或400℃以上，且為500℃以下或450℃以下。例如，較佳為將基板的加熱溫度設為室溫以上且500℃以下，更佳為100℃以上450℃以下，進一步較佳為200℃以上且450℃以下，更進一步較佳為300℃以上且450℃以下，還進一步較佳為400℃以上且450℃以下。During microwave plasma treatment, the substrate may be heated. The substrate heating temperature is preferably set to be above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate heating temperature is preferably set to be above room temperature and below 500°C, more preferably above 100°C and below 450°C, even more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.
例如，可以使用氧氣體及氬氣體進行微波電漿處理。在使用氧氣體及氬氣體的微波電漿處理中，主要的氧自由基可能處於三重態氧（O（3Pj））、單重態氧（O（1D2））及氧離子（O2+）這三種狀態。另外，在藉由微波電漿處理而氧化物膜中的氫濃度下降時，氧離子有效地起作用。另外，各狀態下的氧自由基量根據微波電漿處理的氧流量比或壓力而變化。例如，在氧流量比低且壓力低的條件下，有氧離子量增加的傾向。另一方面，在氧流量比或壓力過度降低的情況下，氧流量的控制變得不穩定，因此有難以穩定放電、氧化物膜被蝕刻等的擔憂。因此，例如，將微波電漿處理中的氧流量比（O2/（O2+Ar））較佳為設為大於0%且10%以下，更佳為設為0.5%以上且5%以下，進一步較佳為設為0.5%以上且3%以下，典型地較佳為設為1%。For example, microwave plasma treatment can be performed using oxygen and argon gases. In microwave plasma treatment using oxygen and argon gases, the main oxygen radicals can be in three states: triplet oxygen (O(3Pj )), singlet oxygen (O (1D2 )), and oxygen ions (O2+ ). Furthermore, when the hydrogen concentration inthe oxide film decreases due to microwave plasma treatment, oxygen ions effectively act. Furthermore, the amount of oxygen radicals in each state varies depending on the oxygen flow rate and pressure of the microwave plasma treatment. For example, under conditions of low oxygen flow rate and low pressure, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively reduced, oxygen flow rate control becomes unstable, leading to difficulty in stabilizing discharge and concerns about etching of the oxide film. Therefore, for example, the oxygen flow rate ratio (O₂ /(O₂ + Ar)) during microwave plasma processing is preferably set to greater than 0% and less than 10%, more preferably to between 0.5% and less than 5%, even more preferably to between 0.5% and less than 3%, and typically preferably to 1%.
微波電漿處理的處理時間越短，越可以抑制導電層220或導電層240等的氧化。另外，產生率得到提高。由此，例如，微波電漿處理的處理時間較佳為1分鐘以上且60分鐘以下，更佳為1分鐘以上且30分鐘以下，進一步較佳為1分鐘以上且10分鐘以下。The shorter the microwave plasma treatment time, the more oxidation of conductive layer 220 or conductive layer 240 can be suppressed. Furthermore, the yield rate is improved. Therefore, for example, the microwave plasma treatment time is preferably 1 minute to 60 minutes, more preferably 1 minute to 30 minutes, and even more preferably 1 minute to 10 minutes.
當在含氧氛圍下進行微波電漿處理時，可以使用微波或RF等高頻使氧氣體電漿化，並將藉由使氧氣體電漿化而產生的氧自由基作用於氧化物半導體層。藉由電漿、微波或氧自由基等的作用，可以將氧化物半導體層中的氫進入氧空位的缺陷（以下，有時被稱為VOH）分為氧空位及氫，而可以從氧化物半導體層去除作為雜質的氫。如此，可以減少氧化物半導體層中的VOH。另外，此時，有時還可以去除與氧或氫等鍵合的碳。如此，藉由進行微波電漿處理，可以減少碳或氫等雜質。另外，藉由對形成在氧化物半導體層中的氧空位供應上述氧自由基，可以進一步減少氧化物半導體層中的氧空位。When microwave plasma treatment is performed in an oxygen-containing atmosphere, oxygen gas is converted to a plasma using high-frequency radiation, such as microwaves or RF. The oxygen radicals generated by this plasma treatment act on the oxide semiconductor layer. The plasma, microwaves, or oxygen radicals separate defects (hereinafter sometimes referred to asVOH ) in the oxide semiconductor layer, where hydrogen enters oxygen vacancies, into oxygen vacancies and hydrogen, thereby removing hydrogen, an impurity, from the oxide semiconductor layer. This reducesVOH in the oxide semiconductor layer. Furthermore, carbon bonded to oxygen or hydrogen can sometimes be removed. Thus, microwave plasma treatment can reduce impurities such as carbon and hydrogen. In addition, by supplying the above-mentioned oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.
另外，藉由進行微波電漿處理，可以提高第一層的結晶性。在此，說明藉由微波電漿處理而氧化物半導體層的結晶性得到提高的原理。首先，由微波被激發的氧自由基等活性種到達氧化物半導體層表面，而發生該活性種與氧化物半導體層中的氧的取代反應。此時，形成核或種。此外，還發生核或種的橫向生長。另外，在由微波被激發的活性種包含容易吸附到核或種的側面的氧（典型為氧離子）時，促進上述橫向生長，所以是較佳的。藉由進行微波電漿處理，發生核或種的形成及核或種的橫向生長，由此氧化物半導體層的結晶性得到提高。In addition, the crystallinity of the first layer can be improved by performing microwave plasma treatment. Here, the principle of improving the crystallinity of the oxide semiconductor layer by microwave plasma treatment is explained. First, active species such as oxygen free radicals excited by microwaves reach the surface of the oxide semiconductor layer, and a substitution reaction occurs between the active species and the oxygen in the oxide semiconductor layer. At this time, a core or seed is formed. In addition, lateral growth of the core or seed also occurs. In addition, when the active species excited by microwaves contain oxygen (typically oxygen ions) that is easily adsorbed to the side of the core or seed, the above-mentioned lateral growth is promoted, so it is better. By performing microwave plasma treatment, the formation of the core or seed and the lateral growth of the core or seed occur, thereby improving the crystallinity of the oxide semiconductor layer.
另一方面，微波電漿處理之前存在的氧化物半導體中的氧的一部分與氧化物半導體中的氫起反應，換言之，發生“2H+O→H2O↑”的反應，由此可以去除該氫作為H2O（也可以說脫水化或脫氫化）。H2O是阻礙結晶性的提高的原因之一，因此較佳為從氧化物半導體中去除。藉由去除氧化物半導體中的氫作為H2O來降低氧化物半導體中的氫濃度，可以促進結晶性的提高。另外，藉由提高微波電漿處理時的溫度，可以進一步降低氧化物半導體中的氫濃度。On the other hand, some of the oxygen present in the oxide semiconductor before microwave plasma treatment reacts with hydrogen in the oxide semiconductor. In other words, a "2H + O → H2 O ↑" reaction occurs, removing the hydrogen as H2 O (also known as dehydration or dehydrogenation). H2 O is one of the factors that hinder the improvement of crystallinity, so it is preferably removed from the oxide semiconductor. By removing hydrogen from the oxide semiconductor as H2 O, the hydrogen concentration in the oxide semiconductor is reduced, which can promote the improvement of crystallinity. In addition, by increasing the temperature during microwave plasma treatment, the hydrogen concentration in the oxide semiconductor can be further reduced.
另外，也可以在進行微波電漿處理之後，以不暴露於外部空氣的方式連續地進行加熱處理。加熱處理的溫度例如較佳為100℃以上且750℃以下，更佳為300℃以上且500℃以下，進一步較佳為400℃以上且450℃以下。Alternatively, after the microwave plasma treatment, a heat treatment may be performed continuously without exposure to the outside air. The temperature of the heat treatment is preferably 100°C to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C.
另外，即使在不進行微波電漿處理的情況下，也可以藉由進行包含氧氣體的電漿處理提高結晶性。In addition, even without microwave plasma treatment, crystallinity can be improved by performing plasma treatment containing oxygen gas.
在第一層的結晶性得到提高時，可以進一步提高形成在第一層上的第二層的結晶性。因此，可以提高氧化物半導體層整體的結晶性。When the crystallinity of the first layer is improved, the crystallinity of the second layer formed on the first layer can be further improved. Therefore, the crystallinity of the entire oxide semiconductor layer can be improved.
供應到氧化物半導體層的氧處於氧原子、氧分子、氧離子（帶電荷的氧原子或氧分子）及氧自由基（具有不成對電子的氧原子、氧分子或氧離子）等各種形態。注意，注入到氧化物半導體層中的氧較佳為處於上述形態中的一個或多個，尤其較佳為處於氧自由基。Oxygen supplied to the oxide semiconductor layer can be in various forms, including oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with unpaired electrons). Note that the oxygen implanted into the oxide semiconductor layer is preferably in one or more of the above forms, with oxygen radicals being particularly preferred.
第二層較佳為利用濺射法形成。The second layer is preferably formed by sputtering.
作為濺射法的靶材，可以使用In-M-Zn氧化物。例如，在使用濺射法形成金屬氧化物的情況下，作為濺射氣體使用氧或者氧和稀有氣體的混合氣體。此外，藉由提高濺射氣體所包含的氧的比例，可以增加沉積的氧化膜中的過量氧。In-M-Zn oxide can be used as a target for sputtering. For example, when forming a metal oxide using sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. Furthermore, by increasing the oxygen content of the sputtering gas, the excess oxygen in the deposited oxide film can be reduced.
此外，有時相對於在形成時使用的沉積氣體整體的氧氣體的流量比例（以下，也稱為氧流量比）越高，越可以形成結晶性高的金屬氧化物。In addition, a higher flow rate ratio of oxygen gas to the entire deposition gas used during formation (hereinafter also referred to as oxygen flow rate ratio) may result in the formation of a metal oxide with higher crystallinity.
在使用濺射法形成金屬氧化物的情況下，藉由在包含在濺射氣體中的氧的比例為高於30%且100%以下，較佳為70%以上且100%以下的條件下進行沉積，有時可以形成氧過剩型金屬氧化物。將氧過剩型氧化物半導體用於通道形成區域的電晶體可以得到較高的可靠性。注意，本發明的一個實施方式不侷限於此。藉由在包含在濺射氣體中的氧的比例為1%以上且30%以下，較佳為5%以上且20%以下的條件下進行沉積，形成氧缺乏型金屬氧化物。將氧缺乏型金屬氧化物用於通道形成區域的電晶體可以具有較高的場效移動率。When a metal oxide is formed by sputtering, an oxygen-excess metal oxide may be formed by depositing the metal oxide under conditions where the proportion of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably greater than 70% and less than 100%. Transistors using oxygen-excess oxide semiconductors in the channel formation region can achieve higher reliability. Note that one embodiment of the present invention is not limited to this. Oxygen-deficient metal oxide may be formed by depositing the metal oxide under conditions where the proportion of oxygen contained in the sputtering gas is greater than 1% and less than 30%, preferably greater than 5% and less than 20%. Transistors using oxygen-deficient metal oxides in the channel formation region can have higher field-effect mobility.
當使用濺射法形成金屬氧化物時，較佳為對基板進行加熱。藉由提高形成金屬氧化物時的基板溫度（載物台溫度），有時可以形成結晶性高的金屬氧化物。當使用濺射法形成金屬氧化物時，基板加熱溫度例如較佳為100℃以上且400℃以下，更佳為200℃以上且300℃以下。When forming metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a highly crystalline metal oxide can sometimes be formed. When forming metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C to 400°C, and more preferably 200°C to 300°C.
當在具有CAAC結構的第二層上使用ALD法形成第三層時，有時第三層以第二層為核而磊晶生長。因此，當形成第三層時，有時第三層包括具有CAAC結構的區域。此外，具有CAAC結構的該區域較佳為形成在整個第三層中。When forming a third layer using ALD on a second layer having a CAAC structure, the third layer may epitaxially grow using the second layer as a nucleus. Therefore, when the third layer is formed, it may include a region having a CAAC structure. Furthermore, the region having a CAAC structure is preferably formed throughout the entire third layer.
在形成第三層之後，也可以進行熱處理製程。After forming the third layer, a heat treatment process may also be performed.
熱處理溫度例如可以為100℃以上且800℃以下，較佳為250℃以上且650℃以下，更佳為350℃以上且550℃以下。典型地，可以為400℃±25℃（375℃以上且425℃以下）。此外，可以將處理時間設為10小時以下，例如，可以將其設為1分鐘以上且5小時以下或者1分鐘以上且2小時以下。此外，在使用RTA裝置的情況下，處理時間例如可以為1秒以上且5分鐘以下。藉由該熱處理，可以期待第二層的CAAC結構所具有的原子級的結晶部的空隙被第三層修復。The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). In addition, the treatment time can be set to 10 hours or less, for example, 1 minute to 5 hours or 1 minute to 2 hours. In addition, when using an RTA device, the treatment time can be, for example, 1 second to 5 minutes. By this heat treatment, it can be expected that the voids in the atomic-level crystallized portion of the CAAC structure of the second layer will be repaired by the third layer.
對用於熱處理的加熱裝置沒有特別的限制，也可以為利用來自電阻發熱體等發熱體的熱傳導或熱輻射加熱被處理物的裝置。例如，可以使用電爐或如LRTA（Lamp Rapid Thermal Anneal：燈快速熱退火）裝置、GRTA（Gas Rapid Thermal Anneal：氣體快速熱退火）裝置等RTA（Rapid Thermal Anneal：快速熱退火）裝置。LRTA裝置是利用從燈如鹵素燈、金屬鹵化物燈、氙弧燈、碳弧燈、高壓鈉燈或高壓汞燈等發出的光（電磁波）的輻射加熱被處理物的裝置。GRTA裝置是使用高溫氣體進行加熱處理的裝置。The heating device used for heat treatment is not particularly limited and may utilize heat conduction or thermal radiation from a heating element such as a resistance heater to heat the material being treated. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device heats the material being treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device utilizes high-temperature gas for heat treatment.
藉由該熱處理製程，有時在第三層中具有CAAC結構的該區域的結晶性得到提高。此外，當在使用ALD法進行沉積之後該區域只形成在第三層的下方時，有時由於該熱處理製程而該區域向上方擴展。也就是說，藉由進行該熱處理，有時在整個第三層中形成具有CAAC結構的區域。This heat treatment process sometimes improves the crystallinity of the region with the CAAC structure in the third layer. Furthermore, when this region is formed only below the third layer after ALD deposition, the heat treatment process sometimes causes this region to expand upward. In other words, this heat treatment sometimes forms a region with the CAAC structure throughout the entire third layer.
此外，較佳為藉由該熱處理製程，第一層的至少一部分發生CAAC化。可以期待以在形成第二層時形成在第一層中的混合層為核或種而容易發生CAAC化。第一層中的CAAC化區域較佳為大，較佳為到達被形成面附近。Furthermore, it is preferred that at least a portion of the first layer undergoes CAAC formation during this heat treatment process. It is expected that the mixed layer formed in the first layer during the formation of the second layer will serve as a nucleus or seed to facilitate CAAC formation. The CAAC-formed region in the first layer is preferably large, preferably reaching near the surface being formed.
此外，由於從第一層的上部向下部發生CAAC化，因此不受被形成面的層的材料或結晶性的限制，CAAC化可以到達該層附近。例如，即使該層具有非晶結構，也可以形成結晶性高的第一層。因此，本發明的一個實施方式的氧化物半導體層的製造方法尤其適合於作為被形成面的層具有非晶結構的情況。Furthermore, because CAAC formation occurs from the top to the bottom of the first layer, it can reach close to the layer being formed, regardless of the material or crystallinity of the layer being formed. For example, even if the layer has an amorphous structure, a highly crystalline first layer can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for cases where the layer being formed has an amorphous structure.
另外，在形成第三層之後，也可以進行微波電漿處理。Alternatively, microwave plasma treatment can be performed after forming the third layer.
另外，藉由進行上述的加熱處理和微波電漿處理中的一者或兩者，可以提高氧化物半導體層整體的結晶性。In addition, by performing one or both of the above-mentioned heat treatment and microwave plasma treatment, the crystallinity of the entire oxide semiconductor layer can be improved.
如上所述，可以減少氧化物半導體層中的雜質。藉由在氧化物半導體層中的雜質濃度得到降低的狀態下進行結晶生長，可以進一步提高結晶性。As described above, impurities in the oxide semiconductor layer can be reduced. By performing crystal growth in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.
另外，上述的加熱處理和微波電漿處理中的一者或兩者可以在氧化物半導體層上直接進行，也可以在將絕緣膜等形成在氧化物半導體層上之後進行。In addition, one or both of the above-mentioned heat treatment and microwave plasma treatment may be performed directly on the oxide semiconductor layer, or may be performed after forming an insulating film or the like on the oxide semiconductor layer.
第一層及第三層的結晶性以結晶性高的第二層為核或種而得到提高。明確而言，有時藉由沉積第二層時或者沉積第三層之後的熱處理，第一層的結晶性得到提高。另外，有時藉由沉積第三層時或者沉積第三層之後的熱處理，第三層的結晶性得到提高。此外，上述熱處理具有提高結晶性的輔助作用。The crystallinity of the first and third layers is enhanced by the highly crystalline second layer acting as a nucleus or seed. Specifically, the crystallinity of the first layer is sometimes enhanced by heat treatment during or after deposition of the second layer. Similarly, the crystallinity of the third layer is sometimes enhanced by heat treatment during or after deposition of the third layer. Furthermore, these heat treatments have a secondary effect in enhancing crystallinity.
如此，在本發明的一個實施方式的金屬氧化物的沉積方法中，可以以包含結晶性高的金屬氧化物（亦即，CAAC）的第二層為核或種的方式提高上下的金屬氧化物（這裡為第一層及第三層）的結晶性。由此，可以提高整個氧化物半導體的結晶性。換言之，以第二層為核或種的方式使上下的金屬氧化物固相生長，由此可以形成結晶性高的氧化物半導體層。利用上述沉積方法來形成的氧化物半導體層，這裡為CAAC膜可以被稱為軸向生長（Axial Growth）CAAC（AG CAAC）。Thus, in the metal oxide deposition method according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (here, the first and third layers) can be improved by using the second layer containing a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This improves the crystallinity of the entire oxide semiconductor. In other words, by solid-phase growing the upper and lower metal oxides using the second layer as a nucleus or seed, a highly crystalline oxide semiconductor layer can be formed. The oxide semiconductor layer formed using this deposition method, here a CAAC film, can be referred to as axially grown CAAC (AG CAAC).
在氧化物半導體層中，具有CAAC結構的區域較佳為在層整體廣泛地存在。在第一層的具有CAAC結構的區域與第二層的具有CAAC結構的區域間晶體連接。在第三層的具有CAAC結構的區域與第二層的具有CAAC結構的區域間晶體連接。由此，有時觀察不到第一層與第二層的邊界。此外，有時也觀察不到第二層與第三層的邊界。氧化物半導體層有時可以表達為觀察不到明確的介面的一個層。氧化物半導體層有時可以表達為單個層。In an oxide semiconductor layer, the region having a CAAC structure is preferably present throughout the entire layer. The region having the CAAC structure in the first layer is crystal-connected to the region having the CAAC structure in the second layer. The region having the CAAC structure in the third layer is crystal-connected to the region having the CAAC structure in the second layer. As a result, the boundary between the first and second layers is sometimes not observable. Furthermore, the boundary between the second and third layers is sometimes not observable. An oxide semiconductor layer can sometimes be expressed as a single layer with no clear interface. An oxide semiconductor layer can sometimes be expressed as a single layer.
在第一至第三層的每一個的具有CAAC結構的區域中，例如在使用高解析度TEM進行剖面觀察的情況下，觀察到與被形成面平行或大致平行排列的亮點。另外，第一至第三層的每一個所具有的CAAC結構的c軸較佳為與氧化物半導體層的被形成面或表面的法線方向平行或大致平行。In regions having a CAAC structure in each of the first to third layers, bright spots aligned parallel or substantially parallel to the formed surface are observed, for example, when observing a cross section using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or substantially parallel to the normal to the formed surface or surface of the oxide semiconductor layer.
此外，第一層或第三層的一部分有時不被結晶化。In addition, a portion of the first layer or the third layer may not be crystallized.
藉由提高氧化物半導體層的結晶性，使用氧化物半導體層的電晶體的半導體層的電阻增加得到抑制或者電晶體的初始特性（尤其是通態電流）得到提高，由此可以期待實現適合於高速驅動的電晶體。此外，可以提高電晶體的可靠性並增大通態電流。By improving the crystallinity of the oxide semiconductor layer, transistors using the oxide semiconductor layer can suppress the increase in semiconductor layer resistance and improve the transistor's initial characteristics (particularly on-state current), thereby potentially achieving transistors suitable for high-speed driving. Furthermore, transistor reliability can be improved while on-state current can be increased.
本發明的一個實施方式的氧化物半導體層在整體上具有高結晶性。因此，在氧化物半導體層中，有時沒確認到第一至第三層中的層疊膜之間的邊界。尤其是，在進行熱處理之後，有時難以確認層疊膜之間的邊界。例如，可以使用剖面TEM、剖面STEM（掃描穿透式電子顯微鏡）等確認層疊膜之間的邊界的有無。The oxide semiconductor layer of one embodiment of the present invention has high crystallinity overall. Therefore, the boundaries between the first to third layers of the oxide semiconductor layer may not be visible. In particular, after heat treatment, the boundaries between the layers may be difficult to identify. For example, the presence of boundaries between the layers can be confirmed using cross-sectional TEM or cross-sectional STEM (scanning transmission electron microscopy).
如上所述，藉由將In的含量率高的金屬氧化物用於電晶體，可以提高電晶體的場效移動率。另一方面，有In的含有率高的氧化物半導體具有立方晶系的晶體結構的傾向。因此，藉由將In的含有率高的氧化物半導體用於與第二層接觸的第一層和第三層中的一者或兩者，可以形成反映了第二層所具有的晶體的配向的晶體。As described above, using a metal oxide with a high indium content in a transistor can improve the transistor's field-effect mobility. On the other hand, oxide semiconductors with a high indium content tend to have a cubic crystal structure. Therefore, using an oxide semiconductor with a high indium content in one or both of the first layer and the third layer, which are in contact with the second layer, can form a crystal that reflects the crystal orientation of the second layer.
另外，第二層所具有的晶體與第一層或第三層所具有的晶體的晶格失配度較佳為低。由此，第一層或第三層可以形成反映了第二層所具有的晶體的配向的晶體。此時，例如，在對氧化物半導體層進行使用高解析度TEM的剖面觀察時，在第一層或第三層中觀察到在與被形成面平行的方向上排列為層狀的亮點。Furthermore, the lattice mismatch between the crystals of the second layer and the crystals of the first or third layer is preferably low. This allows the first or third layer to form crystals that reflect the orientation of the crystals of the second layer. In this case, for example, when observing a cross section of the oxide semiconductor layer using a high-resolution TEM, bright spots are observed in the first or third layer, arranged in layers parallel to the surface on which they are formed.
只要第二層所具有的晶體與第一層或第三層所具有的晶體的晶格失配度低，就對第一層或第三層的晶體結構沒有特別的限制。第一層或第三層的晶體結構可以為立方晶系、四方晶系、正交晶系、六方晶系、單斜晶系和三方晶系中的任意個。There are no particular restrictions on the crystal structure of the first or third layer, as long as the lattice mismatch between the crystals of the second layer and the crystals of the first or third layer is low. The crystal structure of the first or third layer can be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.
另外，有時，藉由在被形成面的層與氧化物半導體層間設置實施方式1中說明的氧化物層227，可以製造本發明的一個實施方式的氧化物半導體層，而不需要形成第一層。此時，氧化物半導體層具有第二層及第三層的兩層結構。例如，藉由利用ALD法形成氧化物層227，有時氧化物層227可以抑制發生氧化物半導體層的成分與被形成面的層的成分的合金化。因此，有時可以提高氧化物半導體層整體的結晶性。Furthermore, by providing the oxide layer 227 described in Embodiment 1 between the layer on the surface to be formed and the oxide semiconductor layer, the oxide semiconductor layer according to one embodiment of the present invention can be produced without forming the first layer. In this case, the oxide semiconductor layer has a two-layer structure comprising a second layer and a third layer. For example, by forming the oxide layer 227 using ALD, the oxide layer 227 can sometimes suppress alloying between the components of the oxide semiconductor layer and the components of the layer on the surface to be formed. Consequently, the crystallinity of the entire oxide semiconductor layer can sometimes be improved.
如上所述，在不設置第一層的結構中，也可以以第二層為核或種的方式使上方的氧化物半導體固相生長，來形成結晶性高的氧化物半導體。利用上述沉積方法形成的氧化物半導體也可以被稱為AG CAAC。As described above, even in a structure without a first layer, it is possible to solid-phase grow an oxide semiconductor using the second layer as a nucleus or seed to form a highly crystalline oxide semiconductor. The oxide semiconductor formed using this deposition method is also referred to as AG CAAC.
另外，在作為氧化物層227使用可用於第一層的金屬氧化物的情況下，可以將第一層換稱為氧化物層227。In addition, when a metal oxide that can be used for the first layer is used as the oxide layer 227, the first layer can be referred to as the oxide layer 227.
在上述結構中，典型的是，作為氧化物層227可以使用In：Ga：Zn=1：3：2[原子數比]或其附近的組成的金屬氧化物或鎵氧化物，作為第二層可以使用包含微量的元素M的金屬氧化物，作為第三層可以使用In-Zn氧化物。In the above structure, typically, a metal oxide or gallium oxide with an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereof can be used as the oxide layer 227, a metal oxide containing a trace amount of element M can be used as the second layer, and an In-Zn oxide can be used as the third layer.
此外，本發明的一個實施方式的氧化物半導體層有時可以利用第二沉積方法及微波電漿處理和加熱處理中的一者或兩者來製造。換言之，有時可以以不形成第二層的方式形成本發明的一個實施方式的氧化物半導體層。此時，氧化物半導體層具有第一層及第三層的兩層結構。例如，藉由在形成第一層之後進行微波電漿處理和加熱處理中的一者或兩者，可以提高第一層的結晶性，並且可以以第一層為核或種的方式提高第三層的結晶性。此外，藉由在形成第三層之後進行微波電漿處理和加熱處理中的一者或兩者，可以提高氧化物半導體層的結晶性。由此，可以在氧化物半導體層中形成CAAC結構。In addition, the oxide semiconductor layer of an embodiment of the present invention can sometimes be manufactured using the second deposition method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor layer of an embodiment of the present invention can sometimes be formed in a manner without forming the second layer. In this case, the oxide semiconductor layer has a two-layer structure of a first layer and a third layer. For example, by performing one or both of microwave plasma treatment and heat treatment after forming the first layer, the crystallinity of the first layer can be improved, and the crystallinity of the third layer can be improved in a manner using the first layer as a core or seed. In addition, by performing one or both of microwave plasma treatment and heat treatment after forming the third layer, the crystallinity of the oxide semiconductor layer can be improved. Thus, a CAAC structure can be formed in the oxide semiconductor layer.
此外，例如，藉由在被形成面的層與氧化物半導體層間設置實施方式1中說明的氧化物層227，可以以氧化物層227為核或種的方式提高第一層的結晶性。此外，藉由在形成第一層之後及/或在形成第三層之後進行微波電漿處理和加熱處理中的一者或兩者，可以提高氧化物半導體層的結晶性。因此，可以在氧化物半導體層中形成CAAC結構。Furthermore, for example, by providing the oxide layer 227 described in Embodiment 1 between the layer to be formed and the oxide semiconductor layer, the crystallinity of the first layer can be improved using the oxide layer 227 as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the first layer and/or after forming the third layer, the crystallinity of the oxide semiconductor layer can be improved. Consequently, a CAAC structure can be formed in the oxide semiconductor layer.
如上所述，也可以在不設置第二層的結構中以第一層為核或種的方式使上方的氧化物半導體固相生長，由此形成結晶性高的氧化物半導體。利用上述沉積方法形成的氧化物半導體也可以被稱為AG CAAC。As described above, in a structure without a second layer, the oxide semiconductor can be solid-phase grown using the first layer as a nucleus or seed, thereby forming a highly crystalline oxide semiconductor. The oxide semiconductor formed by the above deposition method can also be called AG CAAC.
另外，如實施方式1所述，氧化物半導體層可以具有利用第二沉積方法形成的第一層及利用第一沉積方法形成在第一層上的第二層的兩層結構，並且可以在該氧化物半導體層與被形成面的層間設置氧化物層227。此時，第一層對應於實施方式1中說明的氧化物半導體層230_1，第二層對應於實施方式1中說明的氧化物半導體層230_2。Alternatively, as described in Embodiment 1, the oxide semiconductor layer may have a two-layer structure comprising a first layer formed using the second deposition method and a second layer formed on the first layer using the first deposition method, and an oxide layer 227 may be provided between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is formed. In this case, the first layer corresponds to the oxide semiconductor layer 230_1 described in Embodiment 1, and the second layer corresponds to the oxide semiconductor layer 230_2 described in Embodiment 1.
[氧化物半導體層的組成] 第二層的組成較佳為與第一層的組成不同。此外，第二層的組成較佳為與第三層的組成不同。另外，第一層可以採用與第三層相同的組成。或者，第一層及第三層也可以採用互不相同的組成。[Composition of the Oxide Semiconductor Layer]The composition of the second layer is preferably different from that of the first layer. Furthermore, the composition of the second layer is preferably different from that of the third layer. Alternatively, the first layer and the third layer may have different compositions.
第二層較佳為包含In，更佳的是In的含有率高。藉由作為第二層使用In的含有率高的金屬氧化物，可以在將氧化物半導體層用於電晶體的情況下實現大通態電流及高頻率特性。The second layer preferably contains In, and more preferably has a high In content. By using a metal oxide with a high In content as the second layer, a large on-state current and high-frequency characteristics can be achieved when the oxide semiconductor layer is used in a transistor.
如上所述，第二層較佳為採用適合於形成CAAC結構的組成。第二層例如較佳為包含鋅。藉由包含鋅，可以得到結晶性高的金屬氧化物。As described above, the second layer preferably has a composition suitable for forming a CAAC structure. For example, the second layer preferably contains zinc. By including zinc, a highly crystalline metal oxide can be obtained.
第二層例如也可以使用In-Zn氧化物。明確而言，可以採用In：Zn=1：1[原子數比]或其附近的組成、In：Zn=2：1[原子數比]或其附近的組成或者In：Zn=4：1[原子數比]或其附近的組成。或者，也可以使用銦氧化物。此外，附近的組成包括所希望的原子數比的±30%的範圍。作為元素M，較佳為使用鎵、鋁和錫中的一個或多個。The second layer can also be made of, for example, an In-Zn oxide. Specifically, a composition with an atomic ratio of In:Zn = 1:1 or near 1:1, an atomic ratio of In:Zn = 2:1 or near 1:1, or an atomic ratio of In:Zn = 4:1 or near 1:1 can be used. Alternatively, indium oxide can be used. Furthermore, the composition within this range falls within a range of ±30% of the desired atomic ratio. Element M is preferably one or more of gallium, aluminum, and tin.
第二層較佳為包含元素M。在第二層包含元素M時，例如可以抑制在金屬氧化物中形成氧空位。因此，可以提高使用氧化物半導體層的電晶體的可靠性。作為第二層，明確而言，可以使用In：M：Zn=1：1：1[原子數比]或其附近的組成、In：M：Zn=1：1：1.2[原子數比]或其附近的組成、In：M：Zn=1：1：0.5[原子數比]或其附近的組成、In：M：Zn=1：1：2[原子數比]或其附近的組成、In：M：Zn=4：2：3[原子數比]或其附近的組成、In：M：Zn=1：3：2[原子數比]或其附近的組成或者In：M：Zn=1：3：4[原子數比]或其附近的組成的金屬氧化物。The second layer preferably contains element M. When the second layer contains element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of the transistor using the oxide semiconductor layer can be improved. Specifically, as the second layer, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition thereof, a composition of In:M:Zn=1:1:1.2 [atomic ratio] or a composition thereof, a composition of In:M:Zn=1:1:0.5 [atomic ratio] or a composition thereof, a composition of In:M:Zn=1:1:2 [atomic ratio] or a composition thereof, a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition thereof, a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition thereof, or a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition thereof can be used.
此外，第二層也可以具有包含微量的元素M的結構。例如，可以採用In：Ga：Zn=4：0.1：1[原子數比]或其附近的組成、In：Ga：Zn=2：0.1：1[原子數比]或其附近的組成或者In：Ga：Zn=1：0.1：1[原子數比]或其附近的組成。此外，例如可以採用In：Sn：Zn=4：0.1：1[原子數比]或其附近的組成、In：Sn：Zn=2：0.1：1[原子數比]或其附近的組成或者In：Sn：Zn=1：0.1：1[原子數比]或其附近的組成。Furthermore, the second layer may have a structure containing a trace amount of element M. For example, a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or a composition thereof, a composition of In:Ga:Zn = 2:0.1:1 [atomic ratio] or a composition thereof, or a composition of In:Ga:Zn = 1:0.1:1 [atomic ratio] or a composition thereof may be employed. Furthermore, for example, a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or a composition thereof, a composition of In:Sn:Zn = 2:0.1:1 [atomic ratio] or a composition thereof, or a composition of In:Sn:Zn = 1:0.1:1 [atomic ratio] or a composition thereof may be employed.
在利用濺射法形成金屬氧化物時，有時形成後的金屬氧化物的組成與濺射靶材的組成不同。尤其是，形成後的金屬氧化物中的鋅的含有率有時減低到濺射靶材的50%程度。When metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content of the formed metal oxide may drop to approximately 50% of that of the sputtering target.
第一層及第三層都可以使用可用於第二層的金屬氧化物。The metal oxides used for the second layer can be used for both the first and third layers.
例如，第一層及第三層可以是與第二層相比In的含有率高的金屬氧化物。藉由使用In的含有率高的金屬氧化物，可以在將氧化物半導體層用於電晶體的情況下實現大通態電流及高頻率特性。For example, the first and third layers can be metal oxides with a higher In content than the second layer. Using a metal oxide with a high In content allows for high on-state current and high-frequency characteristics when the oxide semiconductor layer is used in a transistor.
另外，例如，作為第一層及第三層，也可以使用Ga的含有率比第二層高的金屬氧化物。例如，第一層及第三層較佳為使用In：Ga：Zn=1：1：1[原子數比]或其附近的組成的金屬氧化物、In：Ga：Zn=1：3：2[原子數比]或其附近的組成的金屬氧化物或者In：Ga：Zn=1：3：4[原子數比]或其附近的組成的金屬氧化物。藉由提高Ga的含有率，例如有時可以使第一層及第三層的能帶間隙都大於第二層。由此，第二層被能帶間隙大的第一層及第三層夾持，第二層主要被用作電流路徑（通道）。藉由第二層被第一層及第三層夾持，可以減少第二層的介面及其附近的陷阱能階。由此，可以實現通道遠離絕緣層介面的埋入通道型電晶體，從而可以提高場效移動率。此外，可形成在背通道一側的介面能階的影響得到降低，可以抑制電晶體的光劣化（例如，光負偏壓劣化），從而可以提高電晶體的可靠性。Alternatively, for example, a metal oxide with a higher Ga content than the second layer can be used for the first and third layers. For example, the first and third layers preferably use a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or near 1:1:1, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:2 or near 1:3:2, or a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or near 1:3:4. By increasing the Ga content, for example, the band gaps of the first and third layers can sometimes be made larger than those of the second layer. This allows the second layer to be sandwiched between the first and third layers, which have larger band gaps, and to function primarily as a current path. By sandwiching the second layer between the first and third layers, the trap levels at and near the interface of the second layer can be reduced. This enables the realization of a buried-channel transistor in which the channel is far from the insulating layer interface, thereby improving field-effect mobility. Furthermore, the influence of the interface energy level formed on the back channel side is reduced, suppressing light degradation of the transistor (for example, degradation caused by negative photobias), thereby improving transistor reliability.
此外，也可以作為第一層和第三層中的一個使用In的含有率高於第二層的金屬氧化物，作為另一個使用Ga的含有率高於第二層的金屬氧化物。Alternatively, a metal oxide having a higher In content than that of the second layer may be used as one of the first layer and the third layer, and a metal oxide having a higher Ga content than that of the second layer may be used as the other.
此外，也可以在第一層、第二層及第三層中層疊有多個具有上述組成的層。例如，第三層也可以具有In的含有率高的金屬氧化物上層疊有Ga的含有率高的金屬氧化物的結構。Alternatively, a plurality of layers having the above-mentioned composition may be stacked in the first, second, and third layers. For example, the third layer may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content.
另外，在利用ALD法沉積In-Ga-Zn氧化物等包含多種金屬元素的金屬氧化物膜的情況下，可以根據所希望的組成設定包含各金屬元素的前驅物的循壞數的比例。例如，在沉積In：Ga：Zn=1：3：2[原子數比]的In-Ga-Zn氧化物的情況下，可以進行包含In的前驅物的沉積和使用氧化劑的處理的循壞一次，進行包含Ga的前驅物的沉積和使用氧化劑的處理的循壞三次，且進行包含Zn的前驅物的沉積和使用氧化劑的處理的循壞兩次。但是，有時包含各金屬元素的前驅物的循環數的比例與沉積的金屬氧化物膜中的各金屬元素的原子數比不一致。Furthermore, when depositing a metal oxide film containing multiple metal elements, such as an In-Ga-Zn oxide, using ALD, the ratio of the number of cycles of precursors containing each metal element can be set according to the desired composition. For example, when depositing an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2, one cycle of depositing an In precursor and treating with an oxidizing agent can be performed, three cycles of depositing a Ga precursor and treating with an oxidizing agent can be performed, and two cycles of depositing a Zn precursor and treating with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element may not correspond to the atomic ratio of the metal elements in the deposited metal oxide film.
在本發明的一個實施方式的氧化物半導體層中，即使作為第一層及第三層採用在形成單層時不容易形成CAAC結構的組成，藉由以第二層為核而發生結晶生長，也可以使包括第一層及第三層的整個氧化物半導體層具有CAAC結構。或者，包括第一層及第三層各自的至少一部分的區域至第二層的區域可以具有CAAC結構。In one embodiment of the present invention, even if the first and third layers of the oxide semiconductor layer have compositions that do not readily form a CAAC structure when formed as a single layer, the entire oxide semiconductor layer including the first and third layers can have a CAAC structure by crystal growth using the second layer as a nucleus. Alternatively, the region from a region including at least a portion of each of the first and third layers to a region of the second layer can have a CAAC structure.
尤其是，在第一層及第三層採用In的含有率高的組成的情況下，也可以得到適合於電晶體的半導體層的結晶性。在本發明的一個實施方式的氧化物半導體層中，可以在提高In的含有率來提高電晶體的開啟特性的同時藉由採用結晶性高的CAAC結構提高可靠性。In particular, even when the first and third layers employ compositions with high In content, the semiconductor layer can achieve crystallinity suitable for transistors. In one embodiment of the present invention, the oxide semiconductor layer can improve transistor turn-on characteristics by increasing the In content, while also improving reliability by employing a highly crystalline CAAC structure.
此外，第一層及第三層也可以使用其組成與第二層相同的金屬氧化物。藉由採用相同的組成，有時容易發生進行熱處理後的CAAC化。Alternatively, the first and third layers may be made of a metal oxide having the same composition as the second layer. Using the same composition may facilitate CAAC formation after heat treatment.
此外，與使用一種沉積方法形成的具有CAAC結構的氧化物半導體層相比，使用上述兩種沉積方法形成的具有CAAC結構的氧化物半導體層的膜的相對介電常數、膜密度和膜的硬度中的一個或多個有時更高。In addition, compared with the oxide semiconductor layer with a CAAC structure formed using one deposition method, the oxide semiconductor layer with a CAAC structure formed using the above-mentioned two deposition methods sometimes has one or more of the relative dielectric constant, film density and film hardness higher.
藉由將使用上述兩種沉積方法形成的具有CAAC結構的氧化物半導體層用於電晶體的通道形成區域，可以實現具有優良特性的電晶體（例如，通態電流大的電晶體、場效移動率高的電晶體、S值小的電晶體、頻率特性（也稱為f特性）高的電晶體、可靠性高的電晶體等）。By using the oxide semiconductor layer having a CAAC structure formed using the above two deposition methods for the channel formation region of the transistor, a transistor with excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) and a transistor with high reliability can be realized.
用於氧化物半導體層的金屬氧化物的組成的分析例如可以使用EDX、XPS、感應耦合電漿質譜分析法（ICP-MS：Inductively Coupled Plasma-Mass Spectrometry）或感應耦合電漿原子發射光譜法（ICP-AES：Inductively Coupled Plasma-Atomic Emission Spectrometry）。或者，也可以組合多個上述方法而分析。注意，含有率低的元素有時受分析精度的影響，實際上的含有率與分析所得的含有率不同。例如，當元素M的含有率低時，有時分析所得的元素M的含有率低於實際上的含有率。The composition of the metal oxide used in the oxide semiconductor layer can be analyzed using, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these methods can be used. Note that the actual content of low-content elements may differ from the analyzed content due to the influence of analytical accuracy. For example, when the content of element M is low, the analyzed content of element M may be lower than the actual content.
[電晶體的氧化物半導體層] 本實施方式的氧化物半導體層可以被用作電晶體的半導體層。[Transistor Oxide Semiconductor Layer]The oxide semiconductor layer of this embodiment can be used as a transistor semiconductor layer.
本實施方式的氧化物半導體層具有CAAC結構。在具有CAAC結構的氧化物半導體層中，在結晶部中金屬原子在平行或大致平行於被形成面的方向上排列為層狀。The oxide semiconductor layer of this embodiment has a CAAC structure. In an oxide semiconductor layer having a CAAC structure, metal atoms are arranged in layers in a crystal portion in a direction parallel or substantially parallel to the surface on which they are formed.
可以推測具有CAAC結構的氧化物半導體層呈現電流各向異性。例如，在IGZO晶體中，電流與c軸方向相比更容易流在a軸方向上。也就是說，可以推測在具有CAAC結構的氧化物半導體層中電流與縱向方向相比更容易流在橫向方向上。It is speculated that oxide semiconductor layers with a CAAC structure exhibit current anisotropy. For example, in an IGZO crystal, current tends to flow more along the a-axis than the c-axis. In other words, it is speculated that in oxide semiconductor layers with a CAAC structure, current tends to flow more horizontally than vertically.
在上面的實施方式中說明的半導體裝置中，在氧化物半導體層230中，金屬原子在平行於或大致平行於被形成面的方向上排列為層狀。此外，也可以表現為CAAC結構的a-b面在平行於或大致平行於被形成面的方向上設置。在此，氧化物半導體層230隔著被形成面的一部分的氧化物層227沿著開口部290的側壁設置。因此，在氧化物半導體層230中，金屬原子在平行於或大致平行於開口部290的側壁的方向上排列為層狀。藉由採用這種結構，可以在電晶體的通道中沿電流流過的方向設置CAAC結構的a-b面。由此，可以增大電晶體的通態電流。In the semiconductor device described in the above embodiment, in the oxide semiconductor layer 230, metal atoms are arranged in layers in a direction parallel to or approximately parallel to the formed surface. In addition, it can also be expressed that the a-b plane of the CAAC structure is arranged in a direction parallel to or approximately parallel to the formed surface. Here, the oxide semiconductor layer 230 is arranged along the side wall of the opening 290 via the oxide layer 227 which is a part of the formed surface. Therefore, in the oxide semiconductor layer 230, the metal atoms are arranged in layers in a direction parallel to or approximately parallel to the side wall of the opening 290. By adopting this structure, the a-b plane of the CAAC structure can be arranged in the direction of current flow in the channel of the transistor. As a result, the on-state current of the transistor can be increased.
在將本實施方式的氧化物半導體層用作電晶體的半導體層的情況下，氧化物半導體層的厚度例如較佳為3nm以上且200nm以下，較佳為3nm以上且100nm以下，更佳為5nm以上且100nm以下，更佳為10nm以上且100nm以下，更佳為10nm以上且70nm以下，更佳為15nm以上且70nm以下，更佳為15nm以上且50nm以下，進一步較佳為20nm以上且50nm以下。另外，在用於更微型的半導體裝置的電晶體中，氧化物半導體層230的厚度較佳為1nm以上且20nm以下，較佳為3nm以上且15nm以下，較佳為5nm以上且12nm以下，較佳為5nm以上且10nm以下。另外，尤其較佳的是，電晶體的通道形成區域中的氧化物半導體層的平均厚度例如為2nm以上且15nm以下。When the oxide semiconductor layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 10 nm to 70 nm, more preferably 15 nm to 70 nm, more preferably 15 nm to 50 nm, and even more preferably 20 nm to 50 nm. Furthermore, in transistors used in even smaller semiconductor devices, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, more preferably 5 nm to 12 nm, and even more preferably 5 nm to 10 nm. In addition, it is particularly preferred that the average thickness of the oxide semiconductor layer in the channel formation region of the transistor is, for example, greater than or equal to 2 nm and less than or equal to 15 nm.
第二層例如較佳為200nm以下。此外，在第二層為層狀的情況下，厚度例如較佳為1nm以上且200nm以下，更佳為1nm以上且100nm以下，進一步較佳為2nm以上且100nm以下。The second layer is preferably 200 nm or less, for example. When the second layer is layered, the thickness is preferably 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.
或者，如果第二層能夠起到晶核的作用，則有時第二層不以層狀存在，而作為島狀區域的集合體存在。在此情況下，例如，第二層所包括的島狀區域分散地存在。Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered state but may exist as a collection of island-like regions. In this case, for example, the island-like regions included in the second layer may exist dispersedly.
第一層及第三層的厚度例如較佳為0.5nm以上且50nm以下，更佳為0.5nm以上且30nm以下，進一步較佳為0.5nm以上且20nm以下，更進一步較佳為1nm以上且50nm以下，還進一步較佳為1nm以上且30nm以下，進一步較佳為1nm以上且20nm以下，進一步較佳為2nm以上且20nm以下。此外，第一層的厚度更佳為0.5nm以上且3nm以下。The thickness of the first layer and the third layer is, for example, preferably 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, even more preferably 0.5 nm to 20 nm, even more preferably 1 nm to 50 nm, even more preferably 1 nm to 30 nm, even more preferably 1 nm to 20 nm, even more preferably 2 nm to 20 nm. Furthermore, the thickness of the first layer is even more preferably 0.5 nm to 3 nm.
[氧化物半導體中的雜質] 在此，說明氧化物半導體中的各雜質的影響。[Impurities in Oxide Semiconductors]Here, we explain the effects of various impurities in oxide semiconductors.
如上面的實施方式所述，在將氧化物半導體用於半導體層的電晶體中，當在氧化物半導體的通道形成區域中存在氧空位（VO）及雜質時，電特性容易變動而有可能可靠性下降。因此，為了使OS電晶體的電特性穩定，降低氧化物半導體中的雜質濃度是有效的。另外，為了降低氧化物半導體中的雜質濃度，較佳為還降低附近膜中的雜質濃度。作為雜質，可以舉出氫、碳、氮等。As described in the above embodiments, in transistors using oxide semiconductors for their semiconductor layers, the presence of oxygen vacancies (VO ) and impurities in the channel-forming region of the oxide semiconductor can easily cause fluctuations in electrical characteristics, potentially leading to reduced reliability. Therefore, to stabilize the electrical characteristics of OS transistors, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, to reduce the impurity concentration in the oxide semiconductor, it is also preferable to reduce the impurity concentration in nearby films. Examples of impurities include hydrogen, carbon, and nitrogen.
在氧化物半導體包含第14族元素之一的矽或碳時，在氧化物半導體中形成缺陷態。由此，將利用SIMS測得的氧化物半導體的通道形成區域中的碳濃度設定為1×1020atoms/cm3以下，較佳為5×1019atoms/cm3以下，更佳為3×1019atoms/cm3以下，更佳為1×1019atoms/cm3以下，更佳為3×1018atoms/cm3以下，進一步較佳為1×1018atoms/cm3以下。此外，將利用SIMS測得的氧化物半導體的通道形成區域中的矽濃度設定為1×1020atoms/cm3以下，較佳為5×1019atoms/cm3以下，更佳為3×1019atoms/cm3以下，更佳為1×1019atoms/cm3以下，更佳為3×1018atoms/cm3以下，進一步較佳為1×1018atoms/cm3以下。When an oxide semiconductor contains silicon or carbon, which is a Group 14 element, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1×1020 atoms/cm3 or less, preferably 5×1019 atoms/cm3 or less, more preferably 3×1019 atoms/cm3 or less, even more preferably 1×1019 atoms/cm3 or less, even more preferably 3×1018 atoms/cm3 or less, and even more preferably 1×1018 atoms/cm3 or less. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1×1020 atoms/cm3 or less, preferably 5×1019 atoms/cm3 or less, more preferably 3×1019 atoms/cm3 or less, even more preferably 1×1019 atoms/cm3 or less, even more preferably 3×1018 atoms/cm3 or less, and further preferably 1×1018 atoms/cm3 or less.
此外，當氧化物半導體包含氮時，產生作為載子的電子，載子濃度得到增高，而容易被n型化。其結果是，將含有氮的氧化物半導體用於半導體的電晶體容易成為常開啟特性。或者，在氧化物半導體包含氮時，有時形成陷阱態。其結果是，有時電晶體的電特性不穩定。因此，將利用SIMS測得的氧化物半導體的通道形成區域中的氮濃度設定為1×1020atoms/cm3以下，較佳為5×1019atoms/cm3以下，更佳為1×1019atoms/cm3以下，更佳為5×1018atoms/cm3以下，更佳為1×1018atoms/cm3以下，進一步較佳為5×1017atoms/cm3以下。Furthermore, when oxide semiconductors contain nitrogen, electrons acting as carriers are generated, increasing the carrier concentration and facilitating n-type conversion. Consequently, semiconductor transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, when oxide semiconductors contain nitrogen, trap states may form, resulting in unstable transistor electrical characteristics. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1×1020 atoms/cm3 or less, preferably 5×1019 atoms/cm3 or less, more preferably 1×1019 atoms/cm3 or less, even more preferably 5×1018 atoms/cm3 or less, even more preferably 1×1018 atoms/cm3 or less, and even more preferably 5×1017 atoms/cm3 or less.
此外，包含在氧化物半導體中的氫與鍵合於金屬原子的氧起反應生成水，因此有時形成氧空位。當氫進入該氧空位時，有時產生作為載子的電子。此外，有時由於氫的一部分與鍵合於金屬原子的氧鍵合，產生作為載子的電子。因此，使用含有氫的氧化物半導體的電晶體容易成為常開啟特性。由此，較佳為儘可能減少氧化物半導體的通道形成區域中的氫。明確而言，將利用SIMS測得的氧化物半導體的通道形成區域中的氫濃度設定小於1×1020atoms/cm3，較佳為小於5×1019atoms/cm3，更佳為小於1×1019atoms/cm3，進一步較佳為小於5×1018atoms/cm3，更進一步較佳為小於1×1018atoms/cm3，還進一步較佳為小於1×1017atoms/cm3。另外，對氧化物半導體的通道形成區域的氫濃度的下限值沒有特別的限制，例如可以將其設為1×1016atoms/cm3以上。Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to produce water, sometimes forming oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons, which serve as carriers, are sometimes generated. Furthermore, some of the hydrogen sometimes bonds with oxygen bonded to metal atoms, generating electrons that also serve as carriers. Consequently, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. Therefore, it is desirable to minimize hydrogen in the channel-forming region of oxide semiconductors. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to less than 1×1020 atoms/cm3 , preferably less than 5×1019 atoms/cm3 , more preferably less than 1×1019 atoms/cm3 , further preferably less than 5×1018 atoms/cm3 , further preferably less than 1×1018 atoms/cm3 , and even more preferably less than 1×1017 atoms/cm3 . There is no particular limitation on the lower limit of the hydrogen concentration in the channel formation region of the oxide semiconductor; for example, it can be set to 1×1016 atoms/cm3 or higher.
此外，當氧化物半導體包含鹼金屬或鹼土金屬時，有時形成缺陷態而產生載子。因此，使用包含鹼金屬或鹼土金屬的氧化物半導體的電晶體容易成為常開啟特性。由此，將利用SIMS測得的氧化物半導體的通道形成區域中的鹼金屬或鹼土金屬的濃度設定為1×1018atoms/cm3以下，較佳為2×1016atoms/cm3以下。Furthermore, when oxide semiconductors contain alkali metals or alkali-earth metals, defect states may form, generating carriers. Consequently, transistors using oxide semiconductors containing alkali metals or alkali-earth metals tend to exhibit normally-on characteristics. Therefore, the concentration of alkali metals or alkali-earth metals in the channel-forming region of the oxide semiconductor, as measured by SIMS, is set to 1×1018 atoms/cm3 or less, preferably 2×1016 atoms/cm3 or less.
藉由將雜質被充分降低的氧化物半導體用於電晶體的通道形成區域，可以使電晶體具有穩定的電特性。By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.
本實施方式可以與其他實施方式或實施例適當地組合。此外，在本說明書中，在一個實施方式中示出多個結構例子的情況下，可以適當地組合該結構例子。This embodiment can be appropriately combined with other embodiments or examples. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.
實施方式3 在本實施方式中，參照圖19A至圖24說明本發明的一個實施方式的記憶體裝置。本發明的一個實施方式的記憶體裝置包括記憶單元。該記憶單元包括電晶體及電容器。Embodiment 3In this embodiment, a memory device according to one embodiment of the present invention is described with reference to Figures 19A to 24 . The memory device according to one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.
＜記憶體裝置的結構例子1＞ 參照圖19A至圖19C說明包括電晶體及電容器的記憶體裝置的結構。圖19A是包括電晶體200及電容器100的記憶體裝置的平面圖。圖19B是沿著圖19A所示的點劃線A1-A2的剖面圖。圖19C是沿著圖19A所示的點劃線A3-A4的剖面圖。<Memory Device Structure Example 1>The structure of a memory device including a transistor and a capacitor is described with reference to Figures 19A to 19C. Figure 19A is a plan view of a memory device including transistor 200 and capacitor 100. Figure 19B is a cross-sectional view taken along dotted line A1-A2 in Figure 19A. Figure 19C is a cross-sectional view taken along dotted line A3-A4 in Figure 19A.
圖19A至圖19C所示的記憶體裝置包括基板（未圖示）上的絕緣層140、絕緣層140上的導電層110、導電層110上的記憶單元150、導電層110上的絕緣層180及絕緣層280。絕緣層140、絕緣層180及絕緣層280被用作層間膜。導電層110被用作佈線。The memory device shown in Figures 19A to 19C includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on insulating layer 140, a memory cell 150 on conductive layer 110, and insulating layers 180 and 280 on conductive layer 110. Insulating layers 140, 180, and 280 serve as interlayer films. Conductive layer 110 serves as wiring.
記憶單元150包括導電層110上的電容器100以及電容器100上的電晶體200。The memory cell 150 includes a capacitor 100 on a conductive layer 110 and a transistor 200 on the capacitor 100.
電容器100包括導電層110上的導電層115、導電層115上的絕緣層130以及絕緣層130上的導電層220_1。導電層220_1被用作一對電極中的一個（有時稱為上部電極），導電層115被用作一對電極中的另一個（有時稱為下部電極），絕緣層130被用作介電質。也就是說，電容器100構成MIM（Metal-Insulator-Metal：金屬-絕緣體-金屬）電容器。此外，也可以將設置在導電層220_1上的導電層220_2看作電容器100的上部電極的一部分。Capacitor 100 includes a conductive layer 115 on a conductive layer 110, an insulating layer 130 on a conductive layer 115, and a conductive layer 220_1 on a conductive layer 130. Conductive layer 220_1 serves as one electrode (sometimes referred to as the upper electrode), conductive layer 115 serves as the other electrode (sometimes referred to as the lower electrode), and insulating layer 130 serves as a dielectric. In other words, capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor. Furthermore, conductive layer 220_2, disposed on conductive layer 220_1, can also be considered part of the upper electrode of capacitor 100.
如圖19B及圖19C所示，絕緣層180設置有到達導電層110的開口部190。導電層115的至少一部分配置在開口部190中。注意，導電層115具有在開口部190中接觸於導電層110的頂面的區域、在開口部190中接觸於絕緣層180的側面的區域以及接觸於絕緣層180的頂面的至少一部分的區域。絕緣層130以其至少一部分位於開口部190中的方式配置。導電層220_1以其至少一部分位於開口部190中的方式配置。此外，如圖19B及圖19C所示，導電層220_1較佳為以嵌入開口部190的方式設置。此外，設置在開口部190內部的膜都較佳為利用ALD法形成。由此，該膜具有良好覆蓋性。例如，導電層115、絕緣層130及導電層220_1都較佳為利用ALD法形成。As shown in Figures 19B and 19C , insulating layer 180 is provided with opening 190 that reaches conductive layer 110. At least a portion of conductive layer 115 is disposed within opening 190. Note that conductive layer 115 has a region in contact with the top surface of conductive layer 110 within opening 190, a region in contact with a side surface of insulating layer 180 within opening 190, and a region in contact with at least a portion of the top surface of insulating layer 180. Insulating layer 130 is disposed so that at least a portion thereof is located within opening 190. Conductive layer 220_1 is disposed so that at least a portion thereof is located within opening 190. Furthermore, as shown in Figures 19B and 19C , conductive layer 220_1 is preferably embedded within opening 190. Furthermore, any films disposed within opening 190 are preferably formed using ALD. This provides excellent coverage. For example, conductive layer 115, insulating layer 130, and conductive layer 220_1 are preferably formed using ALD.
電容器100具有在開口部190中不僅在底面上而且在側面上上部電極與下部電極隔著介電體對置的結構，因此可以增加單位面積的靜電電容。由此，開口部190的深度越深，電容器100的靜電電容可以越大。如此，藉由增加電容器100的單位面積的靜電電容，可以使記憶體裝置的讀出工作穩定。此外，可以推進記憶體裝置的微型化或高積體化。Capacitor 100 has a structure where the upper and lower electrodes face each other through a dielectric not only on the bottom surface but also on the sides of opening 190. This increases the electrostatic capacitance per unit area. As a result, the deeper the opening 190, the greater the electrostatic capacitance of capacitor 100. By increasing the electrostatic capacitance per unit area of capacitor 100, the read operation of the memory device can be stabilized. Furthermore, this can promote the miniaturization and high integration of memory devices.
圖19B及圖19C示出開口部190的側壁垂直於導電層110的頂面的例子。此時，開口部190具有圓筒形狀。藉由採用這種結構，可以實現記憶體裝置的微型化或高積體化。19B and 19C show an example in which the sidewalls of opening 190 are perpendicular to the top surface of conductive layer 110. In this case, opening 190 has a cylindrical shape. By adopting this structure, miniaturization or high integration of memory devices can be achieved.
沿著開口部190的側壁及導電層110的頂面層疊設置有導電層115和絕緣層130。此外，絕緣層130上以嵌入開口部190中的方式設置有導電層220_1。具有這種結構的電容器100可以被稱為溝槽型電容器或溝槽電容器。Conductive layer 115 and insulating layer 130 are stacked along the sidewalls of opening 190 and the top of conductive layer 110. Furthermore, conductive layer 220_1 is disposed on insulating layer 130 so as to be embedded in opening 190. Capacitor 100 having this structure may be referred to as a trench capacitor or trench capacitor.
此外，電容器100上配置有絕緣層280。絕緣層280具有位於絕緣層130上的部分及位於導電層220_2上的部分。Furthermore, an insulating layer 280 is disposed on the capacitor 100. The insulating layer 280 includes a portion located on the insulating layer 130 and a portion located on the conductive layer 220_2.
電晶體200包括具有導電層220_1及導電層220_2的導電層220、絕緣層280上的導電層240、氧化物層227、氧化物層227上的氧化物半導體層230、氧化物半導體層230上的絕緣層250以及絕緣層250上的導電層260。Transistor 200 includes a conductive layer 220 including a conductive layer 220_1 and a conductive layer 220_2 , a conductive layer 240 on an insulating layer 280 , an oxide layer 227 , an oxide semiconductor layer 230 on the oxide layer 227 , an insulating layer 250 on the oxide semiconductor layer 230 , and a conductive layer 260 on the insulating layer 250 .
在電晶體200中，氧化物半導體層230被用作半導體層，導電層260被用作閘極電極，絕緣層250被用作閘極絕緣層，導電層220被用作源極電極和汲極電極中的一個，導電層240被用作源極電極和汲極電極中的另一個。In transistor 200 , oxide semiconductor layer 230 is used as a semiconductor layer, conductive layer 260 is used as a gate electrode, insulating layer 250 is used as a gate insulating layer, conductive layer 220 is used as one of a source electrode and a drain electrode, and conductive layer 240 is used as the other of the source electrode and the drain electrode.
關於電晶體200，可以參照實施方式1（圖3A）中的說明，所以省略詳細說明。此外，記憶單元150所包括的電晶體不侷限於電晶體200，也可以應用實施方式1所示的各電晶體。Regarding transistor 200, reference can be made to the description in Embodiment 1 (FIG. 3A), so a detailed description is omitted. Furthermore, the transistor included in memory cell 150 is not limited to transistor 200, and the transistors shown in Embodiment 1 can also be applied.
如圖19A至圖19C所示，電晶體200重疊於電容器100。此外，被設置電晶體200的部分組件的開口部290具有與被設置電容器100的部分組件的開口部190重疊的區域。尤其是，導電層220具有電晶體200的源極電極和汲極電極中的一個的功能及電容器100的上部電極的功能，由此電晶體200及電容器100共用部分組件。藉由採用這種結構，可以在俯視時不以大幅度增大佔有面積的方式設置電晶體200及電容器100。由此，可以減小記憶單元150的佔有面積，從而可以以高密度配置記憶單元150來增大記憶體裝置的記憶容量。換言之，可以實現記憶體裝置的高積體化。圖19B及圖19C示出開口部190的寬度小於開口部290的寬度的例子。對開口部190的寬度與開口部290的寬度的大小關係沒有特別的限制。從微型化的觀點來看，開口部190的寬度較佳為等於或小於開口部290的寬度。As shown in Figures 19A to 19C , transistor 200 overlaps capacitor 100. Furthermore, opening 290 of the portion of the component where transistor 200 is located overlaps opening 190 of the portion of the component where capacitor 100 is located. In particular, conductive layer 220 functions as either the source or drain electrode of transistor 200, as well as the top electrode of capacitor 100. Thus, transistor 200 and capacitor 100 share some components. This structure allows transistor 200 and capacitor 100 to be arranged without significantly increasing their occupied area when viewed from above. This reduces the area occupied by memory cells 150, allowing memory cells 150 to be arranged at a high density to increase the memory capacity of the memory device. In other words, high integration of the memory device can be achieved. Figures 19B and 19C show examples in which the width of opening 190 is smaller than the width of opening 290. There is no particular limitation on the size relationship between the widths of opening 190 and opening 290. From the perspective of miniaturization, the width of opening 190 is preferably equal to or smaller than the width of opening 290.
此外，藉由將電晶體200設置在電容器100的上方，電晶體200不會受到製造電容器100時的熱處理的影響。因此，可以抑制電晶體200的電特性劣化諸如臨界電壓變動及寄生電阻增大等以及因該電特性劣化導致的電特性不均勻增大等。Furthermore, by placing transistor 200 above capacitor 100, transistor 200 is not affected by the heat treatment during the manufacturing of capacitor 100. Therefore, degradation of the electrical characteristics of transistor 200, such as fluctuations in critical voltage and increases in parasitic resistance, and the resulting increase in electrical characteristic variations can be suppressed.
圖20A至圖20C示出作為記憶單元150所包括的電晶體採用實施方式1中說明的電晶體200A的記憶體裝置。圖20A是包括電晶體200A及電容器100的記憶體裝置的平面圖。圖20B是沿著圖20A所示的點劃線A1-A2的剖面圖。圖20C是沿著圖20A所示的點劃線A3-A4的剖面圖。Figures 20A to 20C illustrate a memory device in which the transistor 200A described in Embodiment 1 is used as the transistor included in memory cell 150. Figure 20A is a plan view of the memory device including transistor 200A and capacitor 100. Figure 20B is a cross-sectional view taken along dotted line A1-A2 in Figure 20A. Figure 20C is a cross-sectional view taken along dotted line A3-A4 in Figure 20A.
此外，如圖20B及圖20C所示，也可以採用絕緣層130的側端部與導電層220的側端部一致的結構。藉由採用這種結構，可以使用相同遮罩形成絕緣層130及導電層220，由此可以簡化記憶體裝置的製程。20B and 20C , a structure can also be employed in which the side edges of insulating layer 130 coincide with the side edges of conductive layer 220. This structure allows insulating layer 130 and conductive layer 220 to be formed using the same mask, thereby simplifying the memory device manufacturing process.
圖26A示出本實施方式所示的記憶體裝置的電路圖。如圖26A所示，圖19A至圖19C所示的結構被用作記憶單元。記憶單元951包括電晶體M1及電容器CA。在此，電晶體M1對應於電晶體200，電容器CA對應於電容器100。FIG26A shows a circuit diagram of a memory device according to this embodiment. As shown in FIG26A , the structure shown in FIG19A to FIG19C is used as a memory cell. Memory cell 951 includes transistor M1 and capacitor CA. Here, transistor M1 corresponds to transistor 200, and capacitor CA corresponds to capacitor 100.
電晶體M1的源極和汲極中的一個與電容器CA的一對電極中的一個連接。電晶體M1的源極和汲極中的另一個與佈線BIL連接。電晶體M1的閘極與佈線WOL連接。電容器CA的一對電極中的另一個與佈線CAL連接。One of the source and drain of transistor M1 is connected to one of the pair of electrodes of capacitor CA. The other of the source and drain of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The other of the pair of electrodes of capacitor CA is connected to wiring CAL.
在此，佈線BIL對應於導電層240，佈線WOL對應於導電層260，佈線CAL對應於導電層110。如圖19A至圖19C所示，較佳的是，導電層260延伸在X方向上，導電層240延伸在Y方向上。藉由採用這種結構，佈線BIL與佈線WOL彼此交叉。此外，在圖19A中佈線CAL（導電層110）平行於佈線WOL（導電層260）。注意，但是本發明不侷限於此。例如，佈線CAL也可以平行於佈線BIL（導電層240）。Here, wiring BIL corresponds to conductive layer 240, wiring WOL corresponds to conductive layer 260, and wiring CAL corresponds to conductive layer 110. As shown in Figures 19A to 19C, it is preferred that conductive layer 260 extend in the X direction and conductive layer 240 extend in the Y direction. With this structure, wiring BIL and wiring WOL intersect with each other. Furthermore, in Figure 19A , wiring CAL (conductive layer 110) is parallel to wiring WOL (conductive layer 260). Note, however, that the present invention is not limited to this. For example, wiring CAL may also be parallel to wiring BIL (conductive layer 240).
注意，將在後面的實施方式中詳細地說明記憶單元。Note that the memory unit will be described in detail in the following embodiments.
[電容器100] 電容器100包括導電層115、絕緣層130、導電層220_1。此外，導電層115的下方設置有導電層110。導電層115具有接觸於導電層110的區域。[Capacitor 100]Capacitor 100 includes conductive layer 115, insulating layer 130, and conductive layer 220_1. Furthermore, conductive layer 110 is disposed beneath conductive layer 115. Conductive layer 115 has a region in contact with conductive layer 110.
導電層110設置在絕緣層140上。導電層110被用作佈線CAL，例如可以以帶狀設置。注意，帶狀是指具有延伸在某個方向（例如，X方向、Y方向或Z方向）上的區域的形狀。Conductive layer 110 is provided on insulating layer 140. Conductive layer 110 is used as a wiring CAL and can be provided in a strip shape, for example. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, the Y direction, or the Z direction).
作為導電層110，可以使用實施方式1的[導電體]中記載的導電材料的單層或疊層。作為導電層110，例如可以使用鎢等導電性高的導電材料。藉由如此使用導電性高的導電材料，可以提高導電層110的導電性而使導電層110充分發揮作為佈線CAL的功能。Conductive layer 110 can be made of a single layer or a stack of layers of the conductive materials described in "Conductor" in Embodiment 1. For example, a highly conductive material such as tungsten can be used for conductive layer 110. Using such a highly conductive material improves the conductivity of conductive layer 110, allowing conductive layer 110 to fully function as a wiring CAL.
此外，作為導電層115，較佳為以單層或疊層使用不容易被氧化的導電材料或者具有抑制氧擴散的功能的導電材料等。例如，也可以使用氮化鈦或ITSO等。或者，例如也可以具有鎢上層疊有氮化鈦的結構。或者，例如也可以具有依次層疊第一氮化鈦、鎢和第二氮化鈦的結構。藉由採用這種結構，可以抑制在絕緣層130使用氧化物時因絕緣層130而導電層110被氧化。此外，可以抑制在作為絕緣層180使用氧化物時因絕緣層180而導電層110被氧化。Furthermore, it is preferable to use a conductive material that is not easily oxidized or a conductive material that inhibits oxygen diffusion, either as a single layer or as a stacked layer. For example, titanium nitride or ITSO can be used. Alternatively, a structure can be formed in which titanium nitride is stacked on top of tungsten. Alternatively, a structure can be formed in which a first titanium nitride, a tungsten, and a second titanium nitride are stacked in this order. By adopting such a structure, when an oxide is used as insulating layer 130, oxidation of conductive layer 110 due to insulating layer 130 can be suppressed. Furthermore, when an oxide is used as insulating layer 180, oxidation of conductive layer 110 due to insulating layer 180 can be suppressed.
絕緣層130設置在導電層115上。絕緣層130以接觸於導電層115的頂面及側面的方式設置。也就是說，絕緣層130較佳為覆蓋導電層110的側端部。由此，可以防止導電層115與導電層220_1短路。Insulating layer 130 is disposed on conductive layer 115. Insulating layer 130 is disposed in contact with the top and side surfaces of conductive layer 115. In other words, insulating layer 130 preferably covers the side portions of conductive layer 115. This prevents short circuits between conductive layer 115 and conductive layer 220_1.
此外，也可以採用絕緣層130的側端部與導電層115的側端部一致的結構。藉由採用這種結構，可以使用相同遮罩形成絕緣層130及導電層115，由此可以簡化記憶體裝置的製程。Alternatively, a structure may be employed in which the side edges of the insulating layer 130 coincide with the side edges of the conductive layer 115. With this structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, thereby simplifying the memory device manufacturing process.
作為絕緣層130較佳為使用相對介電常數高（high-k）的材料。藉由絕緣層130使用high-k材料，可以將絕緣層130的厚度增加到能夠抑制洩漏電流的程度且可以充分確保電容器100的靜電電容。A material with a high relative dielectric constant (high-k) is preferably used for the insulating layer 130. By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a level that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 100.
此外，作為絕緣層130，較佳為層疊由high-k材料構成的絕緣層而使用，較佳為使用相對介電常數高的（high-k）材料與介電強度大於該high-k材料的材料的疊層結構。例如，作為絕緣層130，可以使用依次層疊有氧化鋯、氧化鋁及氧化鋯的絕緣膜。此外，例如，可以使用依次層疊有氧化鋯、氧化鋁、氧化鋯及氧化鋁的絕緣膜。此外，例如，可以使用依次層疊有鉿鋯氧化物、氧化鋁、鉿鋯氧化物、氧化鋁的絕緣膜。藉由層疊氧化鋁等介電強度較大的絕緣層而使用，可以提高介電強度而可以抑制電容器100的靜電破壞。Furthermore, insulating layer 130 is preferably a stacked structure of insulating layers composed of high-k materials. A stacked structure of a high-k material and a material having a dielectric strength greater than that of the high-k material is preferred. For example, insulating layer 130 may include an insulating film comprising zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, an insulating film comprising zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order may be used. Alternatively, an insulating film comprising zirconia, aluminum oxide, zirconia, and aluminum oxide in this order may be used. By stacking an insulating layer with a high dielectric strength such as aluminum oxide, the dielectric strength can be increased and electrostatic damage to the capacitor 100 can be suppressed.
此外，作為絕緣層130，也可以使用可具有鐵電性的材料。關於可具有鐵電性的材料的詳細內容，也可以參照實施方式1的記載。Furthermore, a material having ferroelectricity may be used as the insulating layer 130. For details of the material having ferroelectricity, refer to the description of the first embodiment.
包含鉿和鋯中的一者或兩者的金屬氧化物即使為幾nm的薄膜也可具有鐵電性，所以較佳為用於絕緣層130。絕緣層130的厚度較佳為100nm以下，更佳為50nm以下，進一步較佳為20nm以下，還進一步較佳為10nm以下（典型的是，2nm以上且9nm以下）。此外，例如，厚度較佳為8nm以上且12nm以下。藉由使用可以被薄膜化的鐵電層，可以將電容器100與被微型化了的電晶體等半導體元件組合來形成半導體裝置。Metal oxides containing one or both of einsteinium and zirconium exhibit ferroelectric properties even in thin films of a few nanometers, making them suitable for use in insulating layer 130. The thickness of insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). For example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, capacitor 100 can be combined with miniaturized semiconductor elements such as transistors to form a semiconductor device.
此外，包含鉿和鋯中的一者或兩者的金屬氧化物即使在其面積微小時也可具有鐵電性，所以較佳為用於絕緣層130。例如，鐵電層即使在俯視時的面積（佔有面積）為100μm2以下，10μm2以下，1μm2以下或0.1μm2以下也可以具有鐵電性。此外，有時鐵電層即使在俯視時的面積（佔有面積）為10000nm2以下或1000nm2以下也具有鐵電性。藉由使鐵電層的面積小，可以縮小電容器100的佔有面積。Furthermore, metal oxides containing one or both of einsteinium and zirconium are preferred for use in insulating layer 130 because they exhibit ferroelectricity even when their area is very small. For example, a ferroelectric layer can exhibit ferroelectricity even when its area (occupied area) in plan view is 100μm² or less,10 μm² or less, 1μm² or less, or 0.1μm² or less. Furthermore, a ferroelectric layer can sometimes exhibit ferroelectricity even when its area (occupied area) in plan view is 10,000nm² or less, or 1,000nm² or less. By reducing the area of the ferroelectric layer, the occupied area of capacitor 100 can be reduced.
鐵電體為絕緣體，具有因從外部被施加的電場而在內部發生極化，並在該電場為0時也保持極化的性質。因此，藉由使用將該材料用作介電質的電容器（以下，有時稱為鐵電電容器），可以形成非揮發性記憶元件。使用鐵電電容器的非揮發性記憶元件有時被稱為FeRAM（Ferroelectric Random Access Memory：鐵電隨機存取記憶體）、鐵電記憶體等。例如，鐵電記憶體包括電晶體及鐵電電容器，電晶體的源極和汲極中的一個與鐵電電容器的一個端子連接。由此，在作為電容器100使用鐵電電容器的情況下，本實施方式所示的記憶體裝置被用作鐵電記憶體。Ferroelectrics are insulators that become internally polarized by an externally applied electric field and maintain this polarization even when the electric field is zero. Therefore, using capacitors (sometimes referred to as ferroelectric capacitors) using these materials as dielectrics allows for the formation of non-volatile memory devices. Non-volatile memory devices using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, etc. For example, ferroelectric memories consist of a transistor and a ferroelectric capacitor, with one of the transistor's source and drain connected to one terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as the capacitor 100, the memory device shown in this embodiment is used as a ferroelectric memory.
導電層220_1以接觸於絕緣層130的頂面的一部分的方式設置。導電層220_1的側端部較佳為在X方向及Y方向上都位於導電層115的側端部的內側。注意，在絕緣層130覆蓋導電層115的側端部的結構中，導電層220_1的側端部也可以位於導電層115的側端部的外側。Conductive layer 220_1 is provided so as to contact a portion of the top surface of insulating layer 130. The side edges of conductive layer 220_1 are preferably located inward of the side edges of conductive layer 115 in both the X and Y directions. Note that in a structure where insulating layer 130 covers the side edges of conductive layer 115, the side edges of conductive layer 220_1 may also be located outside the side edges of conductive layer 115.
絕緣層180被用作層間膜，所以其相對介電常數較佳為低。藉由將相對介電常數低的材料用於層間膜，可以減少產生在佈線之間的寄生電容。作為絕緣層180，可以使用包含相對介電常數低的材料的絕緣層的單層或疊層。氧化矽及氧氮化矽具有熱穩定性，所以是較佳的。Insulating layer 180 serves as an interlayer film, so its relative dielectric constant is preferably low. Using a material with a low relative dielectric constant for the interlayer film can reduce parasitic capacitance between traces. Insulating layer 180 can be a single layer or a stack of layers made of a material with a low relative dielectric constant. Silicon oxide and silicon oxynitride are preferred due to their thermal stability.
注意，在圖19B及圖19C示出絕緣層180為單層的結構，但是本發明不侷限於此。絕緣層180也可以具有兩層結構，又可以具有三層以上的疊層結構。Note that although FIG19B and FIG19C show the insulating layer 180 as a single-layer structure, the present invention is not limited thereto and the insulating layer 180 may have a two-layer structure or a stacked structure of three or more layers.
＜記憶體裝置的結構例子2＞ 圖21A及圖21B是包括電晶體200a及電晶體200b的記憶體裝置的剖面圖。<Memory Device Structure Example 2>Figures 21A and 21B are cross-sectional views of a memory device including transistors 200a and 200b.
圖21A及圖21B所示的記憶體裝置包括基板（未圖示）上的絕緣層140、絕緣層140上的記憶單元150、絕緣層140上的絕緣層280a及位於絕緣層280a的上方的絕緣層280b。絕緣層140、絕緣層280a及絕緣層280b被用作層間膜。The memory device shown in Figures 21A and 21B includes an insulating layer 140 on a substrate (not shown), a memory cell 150 on insulating layer 140, an insulating layer 280a on insulating layer 140, and an insulating layer 280b located above insulating layer 280a. Insulating layer 140, insulating layer 280a, and insulating layer 280b function as interlayer films.
記憶單元150包括絕緣層140上的電晶體200a以及電晶體200a上的電晶體200b。The memory cell 150 includes a transistor 200a on the insulating layer 140 and a transistor 200b on the transistor 200a.
關於電晶體200a及電晶體200b，可以參照實施方式1中的電晶體200（圖3A）的說明，因此省略詳細說明。例如，藉由將導電層220替換為導電層220a且將氧化物半導體層230替換為氧化物半導體層230a，圖21A及圖21B所示的導電層220a及氧化物半導體層230a等的結構可以參照圖3A的說明。此外，例如藉由將導電層220替換為導電層220b且將氧化物半導體層230替換為氧化物半導體層230b，圖21A及圖21B所示的導電層220b及氧化物半導體層230b等的結構可以參照圖3A的說明。Regarding transistors 200a and 200b, reference can be made to the description of transistor 200 ( FIG. 3A ) in Embodiment 1, and thus a detailed description thereof will be omitted. For example, by replacing conductive layer 220 with conductive layer 220a and oxide semiconductor layer 230 with oxide semiconductor layer 230a, the structures of conductive layer 220a and oxide semiconductor layer 230a shown in FIG. 21A and FIG. 21B can be similar to the description of FIG. 3A . In addition, for example, by replacing the conductive layer 220 with the conductive layer 220b and the oxide semiconductor layer 230 with the oxide semiconductor layer 230b, the structures of the conductive layer 220b and the oxide semiconductor layer 230b shown in FIG. 21A and FIG. 21B can refer to the description of FIG. 3A.
絕緣層280a及絕緣層280b可以採用與可用於絕緣層280的結構同樣的結構。The insulating layer 280 a and the insulating layer 280 b may employ the same structure as that of the insulating layer 280 .
記憶單元150所包括的電晶體不侷限於電晶體200a及電晶體200b的組合，可以使用實施方式1所示的各電晶體中的一種或多種。The transistors included in the memory cell 150 are not limited to the combination of the transistor 200a and the transistor 200b, and one or more of the transistors shown in the first embodiment may be used.
在圖21A及圖21B所示的記憶單元150中，可以利用產生在導電層220b與導電層240a間的電容，因此可以保持資料而不需要另行形成電容器。In the memory cell 150 shown in FIG. 21A and FIG. 21B , the capacitance generated between the conductive layer 220 b and the conductive layer 240 a can be utilized, thereby retaining data without forming a separate capacitor.
導電層240a的頂面至導電層220b的最短距離較佳為比導電層240b的頂面至閘極佈線（圖21A中的導電層260b）的最短距離短。由此，可以增大產生在導電層220b與導電層240a間的電容。此外，還可以減小產生在導電層240b與閘極佈線間的寄生電容。例如，作為電晶體200b可以採用實施方式1中說明的電晶體200A的結構。The shortest distance from the top surface of conductive layer 240a to conductive layer 220b is preferably shorter than the shortest distance from the top surface of conductive layer 240b to the gate wiring (conductive layer 260b in FIG. 21A ). This increases the capacitance between conductive layer 220b and conductive layer 240a. Furthermore, it reduces the parasitic capacitance between conductive layer 240b and the gate wiring. For example, transistor 200b can employ the structure of transistor 200A described in Embodiment 1.
如圖21A及圖21B所示，電晶體200b與電晶體200a重疊。此外，設置有電晶體200b的部分組件的開口部290具有與設置有電晶體200a的部分組件的開口部290a重疊的區域。尤其是，由於導電層220b被用作電晶體200b的源極電極和汲極電極中的一個以及電晶體200a的閘極電極，所以電晶體200b及電晶體200a共用部分組件。藉由採用這種結構，可以在俯視時不以大幅度地增大佔有面積的方式設置電晶體200b及電晶體200a。由此，可以減小記憶單元150的佔有面積，從而可以以高密度配置記憶單元150來增大記憶體裝置的記憶容量。換言之，可以實現記憶體裝置的高積體化。As shown in Figures 21A and 21B, transistor 200b overlaps with transistor 200a. Furthermore, opening 290, where a portion of the components of transistor 200b are located, overlaps with opening 290a, where a portion of the components of transistor 200a are located. In particular, because conductive layer 220b serves as one of the source and drain electrodes of transistor 200b, as well as the gate electrode of transistor 200a, transistors 200b and 200a share some components. This structure allows transistors 200b and 200a to be arranged without significantly increasing their footprint when viewed from above. This can reduce the area occupied by the memory cells 150, thereby enabling the memory cells 150 to be arranged at a high density to increase the memory capacity of the memory device. In other words, high integration of the memory device can be achieved.
圖26E示出本實施方式所示的記憶體裝置的電路圖。如圖26E所示，圖21A及圖21B所示的結構被用作記憶單元。記憶單元955包括電晶體M2及電晶體M3。在此，電晶體M2對應於電晶體200b，電晶體M3對應於電晶體200a。FIG26E shows a circuit diagram of a memory device according to this embodiment. As shown in FIG26E , the structure shown in FIG21A and FIG21B is used as a memory cell. Memory cell 955 includes transistor M2 and transistor M3. Here, transistor M2 corresponds to transistor 200 b, and transistor M3 corresponds to transistor 200 a.
電晶體M2的源極和汲極中的一個與電晶體M3的閘極連接。電晶體M1的源極和汲極中的另一個與佈線WBL連接。電晶體M2的閘極與佈線WOL連接。電晶體M3的源極和汲極中的一個與佈線RBL連接。電晶體M3的源極和汲極中的另一個與佈線SL連接。One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M1 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring RBL. The other of the source and drain of transistor M3 is connected to wiring SL.
在此，佈線WBL對應於導電層240b，佈線WOL對應於導電層260b。如圖21A及圖21B所示，較佳的是，導電層260b延伸在X方向上，導電層240b延伸在Y方向上。藉由採用這種結構，佈線WBL與佈線WOL彼此交叉。Here, wiring WBL corresponds to conductive layer 240b, and wiring WOL corresponds to conductive layer 260b. As shown in Figures 21A and 21B, it is preferred that conductive layer 260b extend in the X direction and conductive layer 240b extend in the Y direction. With this structure, wiring WBL and wiring WOL intersect each other.
此外，電晶體M2也可以包括背閘極。同樣地，電晶體M3也可以包括背閘極。In addition, transistor M2 may also include a back gate. Similarly, transistor M3 may also include a back gate.
＜記憶體裝置的結構例子3＞ 可以將本實施方式所示的包括電晶體200及電容器100的記憶單元150用作記憶體裝置的記憶單元。電晶體200是其通道形成在包含氧化物半導體的半導體層中的電晶體。由於電晶體200的關態電流小，所以藉由將該電晶體用於記憶體裝置，可以長期保持存儲內容。也就是說，由於不需要更新工作或更新工作的頻率極低，所以可以充分降低記憶體裝置的功耗。此外，由於電晶體200的頻率特性高，所以可以高速地進行記憶體裝置的讀出及寫入。<Memory Device Structure Example 3>The memory cell 150 including transistor 200 and capacitor 100 shown in this embodiment can be used as a memory cell of a memory device. Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing an oxide semiconductor. Because transistor 200 has a low off-state current, using this transistor in a memory device can maintain stored data for a long period of time. In other words, since refresh operations are unnecessary or occur at an extremely low frequency, the power consumption of the memory device can be significantly reduced. Furthermore, due to the high frequency characteristics of transistor 200, data can be read from and written to the memory device at high speed.
藉由以三維方式且以矩陣狀配置記憶單元150，可以構成記憶單元陣列。By arranging the memory cells 150 in a three-dimensional matrix, a memory cell array can be constructed.
圖22A是記憶體裝置的平面圖。圖22A示出在X方向及Y方向上配置2個×2個記憶單元（記憶單元150a至記憶單元150d）的例子。Fig. 22A is a plan view of a memory device. Fig. 22A shows an example in which 2×2 memory cells (memory cells 150a to 150d) are arranged in the X and Y directions.
圖22B是沿著圖22A所示的點劃線A3-A4的剖面圖。在圖22A和圖22B中，兩個記憶單元（在圖22B中，記憶單元150a及記憶單元150b）連接到相同的佈線（導電層246）。Fig. 22B is a cross-sectional view taken along dotted line A3-A4 shown in Fig. 22A. In Fig. 22A and Fig. 22B, two memory cells (memory cell 150a and memory cell 150b in Fig. 22B) are connected to the same wiring (conductive layer 246).
圖26B示出對應於兩個記憶單元的電路圖。如圖26B所示，記憶體裝置952包括兩個記憶單元，一個記憶單元包括電晶體M1及電容器CA1，另一個記憶單元包括電晶體M2及電容器CA2。例如，在使圖26B和圖22B對應的情況下，電晶體M1對應於電晶體200a，電容器CA1對應於電容器100a，電晶體M2對應於電晶體200b，電容器CA2對應於電容器100b。FIG26B shows a circuit diagram corresponding to two memory cells. As shown in FIG26B , memory device 952 includes two memory cells, one of which includes transistor M1 and capacitor CA1, and the other includes transistor M2 and capacitor CA2. For example, when FIG26B corresponds to FIG22B , transistor M1 corresponds to transistor 200a, capacitor CA1 corresponds to capacitor 100a, transistor M2 corresponds to transistor 200b, and capacitor CA2 corresponds to capacitor 100b.
電晶體M1的源極和汲極中的一個與電容器CA1的一對電極中的一個連接。電晶體M1的源極和汲極中的另一個與佈線BIL連接。電晶體M1的閘極與佈線WOL1連接。電容器CA1的一對電極中的另一個與佈線CAL連接。電晶體M2的源極和汲極中的一個與電容器CA2的一對電極中的一個連接。電晶體M2的源極和汲極中的另一個與佈線BIL連接。電晶體M2的閘極與佈線WOL2連接。電容器CA2的一對電極中的另一個與佈線CAL連接。One of the source and drain of transistor M1 is connected to one of the pair of electrodes of capacitor CA1. The other of the source and drain of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL1. The other of the pair of electrodes of capacitor CA1 is connected to wiring CAL. One of the source and drain of transistor M2 is connected to one of the pair of electrodes of capacitor CA2. The other of the source and drain of transistor M2 is connected to wiring BIL. The gate of transistor M2 is connected to wiring WOL2. The other of the pair of electrodes of capacitor CA2 is connected to wiring CAL.
在此，佈線BIL對應於導電層240，佈線WOL1對應於導電層260，佈線WOL2對應於另一導電層260，佈線CAL對應於導電層110。Here, the wiring BIL corresponds to the conductive layer 240 , the wiring WOL1 corresponds to the conductive layer 260 , the wiring WOL2 corresponds to another conductive layer 260 , and the wiring CAL corresponds to the conductive layer 110 .
圖22A及圖22B所示的記憶單元150a及記憶單元150b都具有與記憶單元150同樣的結構。記憶單元150a包括電容器100a及電晶體200a，記憶單元150b包括電容器100b及電晶體200b。此外，圖22A所示的記憶單元150c及記憶單元150d也具有與記憶單元150同樣的結構。因此，在圖22A及圖22B所示的記憶體裝置中，對具有與圖19所示的記憶體裝置的組件相同的功能的組件附上相同符號。此外，關於記憶單元150a至記憶單元150d的詳細內容，可以參照＜記憶體裝置的結構例子1＞中的記憶單元150的記載。Memory cells 150a and 150b shown in Figures 22A and 22B have the same structure as memory cell 150. Memory cell 150a includes capacitor 100a and transistor 200a, while memory cell 150b includes capacitor 100b and transistor 200b. Furthermore, memory cells 150c and 150d shown in Figure 22A also have the same structure as memory cell 150. Therefore, in the memory devices shown in Figures 22A and 22B, components having the same functions as those of the memory device shown in Figure 19 are denoted by the same reference numerals. For details of the memory cells 150a to 150d, refer to the description of the memory cell 150 in <Configuration Example 1 of Memory Device>.
如圖22A及圖22B所示，用作佈線WOL的導電層260分別設置在記憶單元150a及記憶單元150b中。此外，如圖22A所示，以記憶單元150a與記憶單元150c之間共用的方式設置一個導電層260，以記憶單元150b與記憶單元150d之間共用的方式設置另一個導電層260。此外，以記憶單元150a與記憶單元150b之間共用的方式設置用作佈線BIL的一部分的一個導電層240。換言之，導電層240與記憶單元150a的氧化物半導體層230及記憶單元150b的氧化物半導體層230接觸。此外，以記憶單元150c與記憶單元150d之間共用的方式設置另一個導電層240。As shown in Figures 22A and 22B , conductive layers 260 serving as the WOL wiring are provided in memory cells 150a and 150b, respectively. Furthermore, as shown in Figure 22A , one conductive layer 260 is provided so as to be shared between memory cells 150a and 150c, and another conductive layer 260 is provided so as to be shared between memory cells 150b and 150d. Furthermore, one conductive layer 240 serving as part of the BIL wiring is provided so as to be shared between memory cells 150a and 150b. In other words, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the memory cell 150a and the oxide semiconductor layer 230 of the memory cell 150b. In addition, another conductive layer 240 is provided in a manner shared between the memory cell 150c and the memory cell 150d.
圖22B示出導電層240具有導電層240_1及導電層240a_1上的導電層240_2的兩層結構的例子。FIG22B shows an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240a_1.
在此，圖22A及圖22B所示的記憶體裝置包括連接於記憶單元150a及記憶單元150b來用作插頭（也可以被稱為連接電極）的導電層245及導電層246。導電層245配置在形成在絕緣層140、絕緣層180、絕緣層130及絕緣層280中的開口部內並與導電層240_1的底面接觸。此外，導電層246配置在形成在絕緣層286、絕緣層250、氧化物半導體層230及氧化物層227中的開口部內並與導電層240_2的頂面接觸。作為導電層245及導電層246，可以使用可用於導電層240的導電材料等。The memory device shown in Figures 22A and 22B includes conductive layers 245 and 246 connected to memory cells 150a and 150b, serving as plugs (also referred to as connection electrodes). Conductive layer 245 is disposed within openings formed in insulating layers 140, 180, 130, and 280, and contacts the bottom surface of conductive layer 240_1. Conductive layer 246 is disposed within openings formed in insulating layer 286, insulating layer 250, oxide semiconductor layer 230, and oxide layer 227 and contacts the top surface of conductive layer 240_2. Conductive materials such as those used for conductive layer 240 can be used for conductive layers 245 and 246.
導電層246也可以與導電層240_1的頂面接觸。或者，導電層246也可以與氧化物半導體層230的頂面接觸。也就是說，導電層240_2也可以在與導電層246重疊的位置具有開口部。此外，氧化物半導體層230也可以在與導電層246重疊的位置不具有開口部。作為記憶單元與插頭的連接部分，構成導電層240及氧化物半導體層230的各層中的與導電層246的接觸電阻較低的層較佳為與導電層246接觸。Conductive layer 246 may also contact the top surface of conductive layer 240_1. Alternatively, conductive layer 246 may contact the top surface of oxide semiconductor layer 230. In other words, conductive layer 240_2 may have an opening at the location where it overlaps with conductive layer 246. Furthermore, oxide semiconductor layer 230 may not have an opening at the location where it overlaps with conductive layer 246. As the connection between the memory cell and the plug, the layer that has the lowest contact resistance with conductive layer 246 among the layers that make up conductive layer 240 and oxide semiconductor layer 230 is preferably in contact with conductive layer 246.
同樣地，導電層245也可以與導電層240_2的底面或氧化物半導體層230的底面接觸。也就是說，導電層240_1也可以在與導電層246重疊的位置具有開口部。構成導電層240及氧化物半導體層230的層中的與導電層245的接觸電阻較低的層較佳為與導電層245接觸。Similarly, conductive layer 245 may also contact the bottom surface of conductive layer 240_2 or the bottom surface of oxide semiconductor layer 230. In other words, conductive layer 240_1 may also have an opening at a location where it overlaps with conductive layer 246. Among the layers constituting conductive layer 240 and oxide semiconductor layer 230, the layer with the lowest contact resistance with conductive layer 245 is preferably in contact with conductive layer 245.
此外，構成導電層240及氧化物半導體層230的層中的佈線電阻較低的層較佳為與導電層245及導電層246接觸。Furthermore, among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230 , a layer having a lower wiring resistance is preferably in contact with the conductive layer 245 and the conductive layer 246 .
導電層245及導電層246被用作連接開關、電晶體、電容器、電感器、電阻器及二極體等電路元件、佈線、電極或端子與記憶單元150a及記憶單元150b的插頭或佈線。例如，可以採用如下結構：導電層245與設置在圖22B所示的記憶體裝置下的感測放大器（未圖示）連接，並且導電層246與設置在圖22B所示的記憶體裝置上的同樣的記憶體裝置（未圖示）連接。在此情況下，導電層245及導電層246被用作佈線BIL的一部分。如此，藉由在圖22B所示的記憶體裝置之上或下設置記憶體裝置等，可以增大單位面積的記憶容量。Conductive layers 245 and 246 serve as connectors or wirings that connect circuit components, wirings, electrodes, or terminals, such as switches, transistors, capacitors, inductors, resistors, and diodes, to memory cells 150a and 150b. For example, a structure in which conductive layer 245 is connected to a sense amplifier (not shown) disposed below the memory device shown in FIG22B , and conductive layer 246 is connected to a similar memory device (not shown) disposed above the memory device shown in FIG22B , can be employed. In this case, conductive layers 245 and 246 serve as part of the wiring BIL. In this way, by providing a memory device above or below the memory device shown in FIG. 22B , the memory capacity per unit area can be increased.
此外，記憶單元150a和記憶單元150b以點劃線A3-A4的垂直平分線為對稱軸呈軸對稱。因此，電晶體200a和電晶體200b也夾著導電層245及導電層246配置為對稱。在此，導電層240被用作電晶體200a的源極電極和汲極電極中的另一個以及電晶體200b的源極電極和汲極電極中的另一個。此外，電晶體200a及電晶體200b共同使用用作插頭的導電層245及導電層246。如此，藉由作為兩個電晶體與插頭的連接關係採用上述結構，可以提供一種能夠實現微型化或高積體化的記憶體裝置。Furthermore, memory cells 150a and 150b are symmetrical about the perpendicular bisector of dotted line A3-A4. Consequently, transistors 200a and 200b are also arranged symmetrically with conductive layers 245 and 246 sandwiched between them. Conductive layer 240 serves as the other of the source and drain electrodes for transistor 200a and the other of the source and drain electrodes for transistor 200b. Furthermore, transistors 200a and 200b share conductive layers 245 and 246, which serve as plugs. Thus, by adopting the above structure as the connection relationship between the two transistors and the plug, a memory device capable of achieving miniaturization or high integration can be provided.
此外，用作佈線CAL的導電層110既可以分別設置在記憶單元150a及記憶單元150b中，也可以共同設置在記憶單元150a及記憶單元150b中。注意，如圖22B所示，導電層110以與導電層245分離的方式設置免得導電層110與導電層245短路。Furthermore, conductive layer 110 serving as wiring CAL may be provided in memory cell 150a and memory cell 150b, or may be provided in both memory cell 150a and memory cell 150b. Note that, as shown in FIG22B , conductive layer 110 is provided separately from conductive layer 245 to prevent short circuit between conductive layer 110 and conductive layer 245.
作為圖22A及圖22B所示的記憶單元，也可以採用圖20A至圖20C所示的記憶單元150。藉由採用絕緣層130的側端部與導電層220的側端部一致的結構，絕緣層130不與導電層245重疊。因此，比較容易進行形成設置導電層245的開口部時的加工。Memory cell 150 shown in Figures 20A to 20C can also be used as the memory cell shown in Figures 22A and 22B. By adopting a structure in which the side ends of insulating layer 130 coincide with the side ends of conductive layer 220, insulating layer 130 does not overlap with conductive layer 245. This makes it easier to process the opening for conductive layer 245.
此外，圖23示出Z方向上層疊有n層（n為3以上的整數）的圖22A所示的四個記憶單元的例子。圖23是沿著圖22A所示的點劃線A3-A4的剖面圖。23 shows an example of the four memory cells shown in FIG22A stacked in n layers (n is an integer greater than or equal to 3) in the Z direction. FIG23 is a cross-sectional view taken along the dotted line A3-A4 shown in FIG22A.
圖23所示的記憶體裝置包括n層的記憶體層160。明確而言，記憶體層160[1]上設置有記憶體層160[2]，記憶體層160[2]上還設置有（n-2）層的記憶體層，最上層設置有記憶體層160[n]。對一層記憶體層160所包括的記憶單元的個數沒有特別的限制，可以包括兩個以上的記憶單元。藉由導電層245、導電層246及導電層247等，n層的記憶體層160所包括的記憶單元與設置在n層的記憶體層160下的感測放大器（未圖示）連接。The memory device shown in FIG23 includes n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are provided on memory layer 160[2], with memory layer 160[n] being provided on the top. There is no particular limit on the number of memory cells included in a memory layer 160, and memory layer 160 may include more than two memory cells. The memory cells included in the n-layer memory layer 160 are connected to a sense amplifier (not shown) provided under the n-layer memory layer 160 via the conductive layer 245 , the conductive layer 246 , and the conductive layer 247 .
圖23示出導電層245與導電層240的底面接觸且導電層246與氧化物半導體層230的頂面接觸的例子。如上所述，導電層245及導電層246等插頭與各記憶單元的連接部分可以採用各種方式，不侷限於圖23的結構。Figure 23 shows an example where conductive layer 245 contacts the bottom surface of conductive layer 240 and conductive layer 246 contacts the top surface of oxide semiconductor layer 230. As described above, the connection between the plugs such as conductive layers 245 and 246 and each memory cell can be implemented in various ways and is not limited to the structure shown in Figure 23.
如圖23所示，藉由層疊多個記憶單元，可以集成地配置單元而無需增大記憶單元陣列的佔有面積。就是說，可以構成3D記憶單元陣列。As shown in Figure 23, by stacking multiple memory cells, the cells can be integrated without increasing the memory cell array footprint. In other words, a 3D memory cell array can be constructed.
圖24示出設置有包括感測放大器的驅動電路的層上層疊設置有包括記憶單元的層的記憶體裝置的剖面結構例子。FIG24 shows an example of a cross-sectional structure of a memory device in which a layer including memory cells is stacked on a layer including a driver circuit including a sense amplifier.
在圖24中，電晶體300的上方設置有記憶單元150（電晶體200及電容器100）。In FIG24 , a memory cell 150 (transistor 200 and capacitor 100 ) is provided above a transistor 300 .
電晶體300是感測放大器所包括的電晶體之一。Transistor 300 is one of the transistors included in the sense amplifier.
關於圖24所示的記憶單元150，可以參照＜記憶體裝置的結構例子1＞中的記憶單元150的記載。For the memory unit 150 shown in FIG. 24 , reference can be made to the description of the memory unit 150 in <Configuration Example 1 of Memory Device>.
如圖24所示，藉由採用以重疊於記憶單元150的方式設置感測放大器的結構，可以縮短位元線。由此，可以減小位元線電容，從而可以實現記憶體裝置的高速驅動。As shown in FIG24 , by adopting a structure in which sense amplifiers are provided in a stacked manner on memory cells 150, the bit lines can be shortened. This reduces the bit line capacitance, thereby enabling high-speed driving of the memory device.
圖24所示的記憶體裝置可以對應於實施方式4中說明的半導體裝置900。明確而言，電晶體300相當於半導體裝置900中的感測放大器927所包括的電晶體。此外，記憶單元150對應於記憶單元950。The memory device shown in FIG24 may correspond to the semiconductor device 900 described in Embodiment 4. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. Furthermore, the memory cell 150 corresponds to the memory cell 950.
電晶體300設置在基板311上，並包括用作閘極的導電層316、用作閘極絕緣層的絕緣層315、由基板311的一部分構成的半導體區域313以及用作源極區域或汲極區域的低電阻區域314a及低電阻區域314b。電晶體300可以是p通道型或n通道型。基板311較佳為包含矽類半導體，明確而言，較佳為包含單晶矽。Transistor 300 is disposed on substrate 311 and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulation layer, a semiconductor region 313 formed from a portion of substrate 311, and low-resistance regions 314a and 314b serving as source and drain regions. Transistor 300 can be a p-channel transistor or an n-channel transistor. Substrate 311 preferably comprises a silicon-based semiconductor, specifically, single-crystal silicon.
在此，在圖24所示的電晶體300中，形成通道的半導體區域313（基板311的一部分）具有凸形狀。此外，以隔著絕緣層315覆蓋半導體區域313的側面及頂面的方式設置導電層316。此外，導電層316也可以使用調整功函數的材料。因為利用半導體基板的凸部，所以這種電晶體300也被稱為FIN型電晶體。此外，也可以以與凸部的上部接觸的方式具有用來形成凸部的遮罩的絕緣層。此外，雖然在此示出對半導體基板的一部分進行加工來形成凸部的情況，但是也可以對SOI基板進行加工來形成具有凸部的半導體膜。Here, in transistor 300 shown in FIG24 , semiconductor region 313 (a portion of substrate 311) forming the channel has a convex shape. Furthermore, conductive layer 316 is provided to cover the side and top surfaces of semiconductor region 313 via insulating layer 315. Conductive layer 316 can also be made of a material that adjusts the work function. Because it utilizes the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Furthermore, an insulating layer can be provided to cover the convex portion, contacting the upper portion. Furthermore, while this illustrates the case where the convex portion is formed by processing a portion of the semiconductor substrate, a semiconductor film having a convex portion can also be formed by processing an SOI substrate.
注意，圖24所示的電晶體300的結構只是一個例子，不侷限於上述結構，可以根據電路結構或驅動方法使用適當的電晶體。Note that the structure of transistor 300 shown in FIG24 is merely an example and is not limited to the above structure. An appropriate transistor may be used depending on the circuit structure or driving method.
在各結構體之間也可以設置有包括層間膜、佈線及插頭等的佈線層。此外，根據設計，可以設置多個佈線層。在此，在具有插頭或佈線的功能的導電層中，有時使用同一符號表示多個組件。此外，在本說明書等中，佈線和連接於佈線的插頭也可以是一個組件。就是說，導電層的一部分有時被用作佈線，並且導電層的一部分有時被用作插頭。A wiring layer, including interlayer films, wiring, and plugs, may be provided between the various structures. Furthermore, multiple wiring layers may be provided depending on the design. In the case of a conductive layer that functions as a plug or wiring, the same symbol may sometimes be used to represent multiple components. Furthermore, in this specification and other text, the wiring and the plug connected to the wiring may be referred to as a single component. In other words, a portion of a conductive layer may function as wiring, and a portion of the conductive layer may also function as a plug.
例如，在電晶體300上，作為層間膜依次層疊地設置有絕緣層320、絕緣層322、絕緣層324及絕緣層326。此外，在絕緣層320及絕緣層322中嵌入導電層328，並且在絕緣層324及絕緣層326中嵌入導電層330。此外，導電層328及導電層330被用作插頭或佈線。For example, insulating layer 320, insulating layer 322, insulating layer 324, and insulating layer 326 are stacked in this order as interlayer films on transistor 300. Furthermore, conductive layer 328 is embedded in insulating layer 320 and insulating layer 322, and conductive layer 330 is embedded in insulating layer 324 and insulating layer 326. Furthermore, conductive layer 328 and conductive layer 330 function as connectors or wiring.
此外，用作層間膜的絕緣層可以被用作覆蓋其下方的凹凸形狀的平坦化膜。例如，為了提高平坦性，絕緣層322的頂面也可以藉由利用CMP法等的平坦化處理被平坦化。Furthermore, the insulating layer used as an interlayer film can be used as a planarization film to cover the uneven shape below it. For example, in order to improve the flatness, the top surface of the insulating layer 322 can also be planarized by a planarization process such as CMP.
在絕緣層326及導電層330上也可以設置佈線層。例如，在圖24中，依次層疊有絕緣層350、絕緣層352及絕緣層354。此外，在絕緣層350、絕緣層352及絕緣層354中形成有導電層356。導電層356被用作插頭或佈線。A wiring layer may also be provided on insulating layer 326 and conductive layer 330. For example, in FIG24 , insulating layer 350, insulating layer 352, and insulating layer 354 are stacked in this order. Furthermore, conductive layer 356 is formed between insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 serves as a connector or wiring.
作為用作層間膜的絕緣層352以及絕緣層354等，可以使用上述可用於半導體裝置或記憶體裝置的絕緣層。As the insulating layer 352 and the insulating layer 354 serving as an interlayer film, the insulating layers used in the above-mentioned semiconductor devices or memory devices can be used.
作為用作插頭或佈線的導電層，例如，導電層328、導電層330以及導電層356等，可以使用可用於導電層240的導電材料。較佳為使用兼具耐熱性和導電性的鎢或鉬等高熔點材料，較佳為使用鎢。或者，較佳為使用鋁或銅等低電阻導電材料形成。藉由使用低電阻導電材料可以降低佈線電阻。Conductive layers used as connectors or wiring, such as conductive layer 328, conductive layer 330, and conductive layer 356, can use the same conductive materials as those used for conductive layer 240. High-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and electrical conductivity, are preferred, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials can reduce wiring resistance.
電晶體200所包括的導電層240藉由導電層643、導電層642、導電層644、導電層645、導電層646、導電層356、導電層330及導電層328與用作電晶體300的源極區域或汲極區域的低電阻區域314b連接。The conductive layer 240 included in the transistor 200 is connected to the low resistance region 314 b serving as the source region or the drain region of the transistor 300 through the conductive layers 643 , 642 , 644 , 645 , 646 , 356 , 330 , and 328 .
導電層643嵌入於絕緣層280中。導電層642設置在絕緣層130上並嵌入於絕緣層280中。導電層642可以使用與導電層220相同的材料及製程製造。導電層644嵌入於絕緣層180及絕緣層130中。導電層645嵌入於絕緣層180中。導電層645可以使用與導電層110相同的材料及製程製造。導電層646嵌入於絕緣層648中。電晶體300與導電層110被絕緣層648絕緣。Conductive layer 643 is embedded in insulating layer 280. Conductive layer 642 is disposed on insulating layer 130 and embedded in insulating layer 280. Conductive layer 642 can be fabricated using the same materials and processes as conductive layer 220. Conductive layer 644 is embedded in insulating layer 180 and insulating layer 130. Conductive layer 645 is embedded in insulating layer 180. Conductive layer 645 can be fabricated using the same materials and processes as conductive layer 110. Conductive layer 646 is embedded in insulating layer 648. Transistor 300 is insulated from conductive layer 110 by insulating layer 648.
本實施方式可以與其他實施方式適當地組合。此外，在本說明書中，在一個實施方式中示出多個結構例子的情況下，可以適當地組合該結構例子。This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.
實施方式4 在本實施方式中，說明根據本發明的一個實施方式的半導體裝置900。半導體裝置900可以被用作記憶體裝置。Embodiment 4This embodiment describes a semiconductor device 900 according to one embodiment of the present invention. Semiconductor device 900 can be used as a memory device.
圖25是示出半導體裝置900的結構例子的方塊圖。圖25所示的半導體裝置900包括驅動電路910及記憶體陣列920。記憶體陣列920包括一個以上的記憶單元950。圖25示出記憶體陣列920包括配置為矩陣狀的多個記憶單元950的例子。FIG25 is a block diagram showing an example of the structure of a semiconductor device 900. The semiconductor device 900 shown in FIG25 includes a driver circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. FIG25 shows an example in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.
作為記憶單元950，可以使用實施方式3中說明的記憶體裝置（記憶單元150等）。As the memory unit 950, the memory device (memory unit 150, etc.) described in Embodiment 3 can be used.
驅動電路910包括PSW931（功率開關）、PSW932及週邊電路915。週邊電路915包括週邊電路911、控制電路912及電壓生成電路928。The driver circuit 910 includes a PSW 931 (power switch), a PSW 932 , and a peripheral circuit 915 . The peripheral circuit 915 includes a peripheral circuit 911 , a control circuit 912 , and a voltage generation circuit 928 .
在半導體裝置900中，根據需要可以適當地取捨各電路、各信號及各電壓。或者，也可以追加其它電路或其它信號。信號BW、信號CE、信號GW、信號CLK、信號WAKE、信號ADDR、信號WDA、信號PON1、信號PON2為從外部輸入的信號，信號RDA為輸出到外部的信號。信號CLK為時脈信號。In semiconductor device 900, circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, while signal RDA is an external output signal. Signal CLK is a clock signal.
此外，信號BW、信號CE及信號GW為控制信號。信號CE為晶片賦能信號，信號GW為全局寫入賦能信號，信號BW為位元組寫入賦能信號。信號ADDR為位址信號。信號WDA為寫入資料，信號RDA為讀出資料。信號PON1、PON2為電源閘控控制用信號。此外，信號PON1、PON2也可以在控制電路912中生成。Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are used for power gate control. Signals PON1 and PON2 can also be generated in control circuit 912.
控制電路912為具有控制半導體裝置900的整體工作的功能的邏輯電路。例如，控制電路912對信號CE、信號GW及信號BW進行邏輯運算來決定半導體裝置900的工作模式（例如，寫入工作、讀出工作）。或者，控制電路912生成週邊電路911的控制信號，以執行上述工作模式。Control circuit 912 is a logic circuit that controls the overall operation of semiconductor device 900. For example, control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of semiconductor device 900 (e.g., write mode or read mode). Alternatively, control circuit 912 generates control signals for peripheral circuit 911 to implement the aforementioned operating mode.
電壓生成電路928具有生成負電壓的功能。信號WAKE具有控制對電壓生成電路928輸入信號CLK的功能。例如，當信號WAKE被施加H位準的信號時，信號CLK被輸入到電壓生成電路928，電壓生成電路928生成負電壓。Voltage generating circuit 928 generates a negative voltage. Signal WAKE controls the input of signal CLK to voltage generating circuit 928. For example, when an H-level signal is applied to signal WAKE, signal CLK is input to voltage generating circuit 928, causing voltage generating circuit 928 to generate a negative voltage.
週邊電路911是用來對記憶單元950進行資料的寫入及讀出的電路。週邊電路911包括行解碼器941、列解碼器942、行驅動器923、列驅動器924、輸入電路925、輸出電路926及感測放大器927。The peripheral circuit 911 is used to write and read data from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
行解碼器941及列解碼器942具有對信號ADDR進行解碼的功能。行解碼器941是用來指定要訪問行的電路，列解碼器942是用來指定要訪問列的電路。行驅動器923具有選擇由行解碼器941指定的行的功能。列驅動器924具有如下功能：將資料寫入記憶單元950的功能；從記憶單元950讀出資料的功能；保持所讀出的資料的功能等。The row decoder 941 and column decoder 942 decode the ADDR signal. The row decoder 941 specifies the row to be accessed, while the column decoder 942 specifies the column to be accessed. The row driver 923 selects the row specified by the row decoder 941. The column driver 924 writes data to the memory cell 950, reads data from the memory cell 950, and stores the read data.
輸入電路925具有保持信號WDA的功能。輸入電路925中保持的資料輸出到列驅動器924。輸入電路925的輸出資料是寫入記憶單元950的資料（Din）。列驅動器924從記憶單元950讀出的資料（Dout）被輸出至輸出電路926。輸出電路926具有保持Dout的功能。此外，輸出電路926具有將Dout輸出到半導體裝置900的外部的功能。從輸出電路926輸出的資料為信號RDA。Input circuit 925 holds signal WDA. Data held in input circuit 925 is output to column driver 924. The output data from input circuit 925 is data (Din) written to memory cell 950. Data (Dout) read from memory cell 950 by column driver 924 is output to output circuit 926. Output circuit 926 holds Dout and then outputs Dout to the outside of semiconductor device 900. Data output from output circuit 926 is signal RDA.
PSW931具有控制向週邊電路915供給VDD的功能。PSW932具有控制向行驅動器923供給VHM的功能。在此，半導體裝置900的高電源電位為VDD，低電源電位為GND（接地電位）。此外，VHM是用來使字線成為高位準的高電源電位，其高於VDD。利用信號PON1控制PSW931的開啟及關閉，利用信號PON2控制PSW932的開啟及關閉。在圖25中，週邊電路915中被供應VDD的電源域的個數為1，但是也可以為多個。此時，可以對各電源域設置功率開關。PSW 931 controls the supply of VDD to the peripheral circuit 915. PSW 932 controls the supply of VHM to the active driver 923. The high power supply potential of semiconductor device 900 is VDD , and the low power supply potential is GND (ground). VHM is a high power supply potential used to drive the word line high, and is higher than VDD . Signal PON1 controls the opening and closing of PSW 931, while signal PON2 controls the opening and closing of PSW 932. In Figure 25 , the number of power domains supplied with VDD in the peripheral circuit 915 is one, but multiple power domains are possible. In this case, a power switch can be provided for each power domain.
參照圖26A至圖26G說明可用於記憶單元950的記憶單元的結構例子。An example of a memory cell structure that can be used for the memory cell 950 is described with reference to FIG. 26A to FIG. 26G .
[DOSRAM] 圖26A示出DRAM的記憶單元的電路結構例子。在本說明書等中，將使用OS電晶體的DRAM稱為DOSRAM（Dynamic Oxide Semiconductor Random Access Memory：氧化物半導體動態隨機存取記憶體）。記憶單元951包括電晶體M1和電容器CA。[DOSRAM]Figure 26A shows an example circuit structure of a DRAM memory cell. In this specification and other documents, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.
電晶體M1也可以包括前閘極（有時簡稱為閘極）及背閘極。此時，背閘極也可以與被供應恆定電位或信號的佈線連接，並且前閘極與背閘極也可以連接。Transistor M1 may also include a front gate (sometimes referred to simply as a gate) and a back gate. In this case, the back gate may also be connected to a wiring supplied with a constant potential or signal, and the front gate and back gate may also be connected.
電晶體M1的第一端子與電容器CA的第一端子連接，電晶體M1的第二端子與佈線BIL連接，電晶體M1的閘極與佈線WOL連接。電容器CA的第二端子與佈線CAL連接。A first terminal of transistor M1 is connected to a first terminal of capacitor CA, a second terminal of transistor M1 is connected to wiring BIL, a gate of transistor M1 is connected to wiring WOL, and a second terminal of capacitor CA is connected to wiring CAL.
佈線BIL被用作位元線，佈線WOL被用作字線。佈線CAL被用作用來對電容器CA的第二端子施加指定的電位的佈線。在資料的寫入及讀出時，較佳為對佈線CAL施加低位準電位（有時稱為參考電位）。The wiring BIL serves as a bit line, and the wiring WOL serves as a word line. The wiring CAL is used to apply a specified potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low potential (sometimes called a reference potential) to the wiring CAL.
資料的寫入及讀出藉由對佈線WOL施加高位準電位使電晶體M1成為開啟狀態而使佈線BIL與電容器CA的第一端子之間成為導通狀態（可以使電流流過）而進行。Data is written and read by applying a high potential to the wiring WOL, turning on the transistor M1 and establishing conduction (current flow) between the wiring BIL and the first terminal of the capacitor CA.
此外，可用作記憶單元950的記憶單元不侷限於記憶單元951，也可以改變電路結構。例如，記憶單元951也可以不包括電容器CA及佈線CAL，電晶體M1的第一端子也可以處於電浮動狀態。Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure may be changed. For example, memory cell 951 may not include capacitor CA and wiring CAL, and the first terminal of transistor M1 may be in an electrically floating state.
作為電晶體M1，較佳為使用OS電晶體。OS電晶體具有關態電流極小的特性。藉由作為電晶體M1使用OS電晶體，可以使電晶體M1的洩漏電流變得非常低。也就是說，可以利用電晶體M1長時間地保持寫入資料，由此可以降低記憶單元的更新頻率。此外，可以省略記憶單元的更新工作。此外，由於洩漏電流非常低，所以可以在記憶單元951中保持多值資料或類比資料。Transistor M1 is preferably an OS transistor. OS transistors have extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, transistor M1 can be used to retain written data for a long time, thereby reducing the memory cell update frequency. In addition, the memory cell update process can be omitted. In addition, because the leakage current is very low, multi-valued data or analog data can be retained in memory cell 951.
此外，如圖26B所示，可以對兩個以上的DRAM的記憶單元共同設置一個佈線BIL。Furthermore, as shown in FIG26B, one wiring BIL may be provided in common for two or more memory cells of the DRAM.
[NOSRAM] 圖26C示出包括2個電晶體和1個電容器的增益單元型的記憶單元的電路結構例子。記憶單元953包括電晶體M2、電晶體M3和電容器CB。在本說明書等中，有時將包括將OS電晶體用於電晶體M2的增益單元型記憶單元的記憶體裝置稱為NOSRAM（Nonvolatile Oxide Semiconductor RAM：氧化物半導體非揮發性隨機存取記憶體）。[NOSRAM]Figure 26C shows an example circuit structure of a gain-cell memory cell consisting of two transistors and one capacitor. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and other documents, a memory device including a gain-cell memory cell that uses an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).
電晶體M2的第一端子與電容器CB的第一端子連接，電晶體M2的第二端子與佈線WBL連接，電晶體M2的閘極與佈線WOL連接。電容器CB的第二端子與佈線CAL連接。電晶體M3的第一端子與佈線RBL連接，電晶體M3的第二端子與佈線SL連接，電晶體M3的閘極與電容器CB的第一端子連接。A first terminal of transistor M2 is connected to a first terminal of capacitor CB, a second terminal of transistor M2 is connected to wiring WBL, and a gate of transistor M2 is connected to wiring WOL. A second terminal of capacitor CB is connected to wiring CAL. A first terminal of transistor M3 is connected to wiring RBL, a second terminal of transistor M3 is connected to wiring SL, and a gate of transistor M3 is connected to a first terminal of capacitor CB.
佈線WBL被用作寫入位元線，佈線RBL被用作讀出位元線，佈線WOL被用作字線。佈線CAL被用作對電容器CB的第二端子施加預定電位的佈線。資料寫入時、正在進行資料保持時、資料讀出時，較佳為對佈線CAL施加低位準電位（有時稱為參考電位）。Wiring WBL serves as a write bit line, wiring RBL serves as a read bit line, and wiring WOL serves as a word line. Wiring CAL applies a predetermined potential to the second terminal of capacitor CB. When writing data, retaining data, and reading data, a low potential (sometimes called a reference potential) is preferably applied to wiring CAL.
資料的寫入藉由對佈線WOL施加高位準電位使電晶體M2成為開啟狀態而使佈線WBL與電容器CB的第一端子成為導通狀態來進行。明確地說，在電晶體M2為開啟狀態時，對佈線WBL施加對應於要記錄的資訊的電位來對電容器CB的第一端子及電晶體M3的閘極寫入該電位。然後，對佈線WOL施加低位準電位來使電晶體M2成為關閉狀態，由此儲存電容器CB的第一端子的電位及電晶體M3的閘極的電位。Data is written by applying a high voltage to wire WOL, turning on transistor M2 and bringing wire WBL and the first terminal of capacitor CB into a conductive state. Specifically, while transistor M2 is on, a potential corresponding to the data to be recorded is applied to wire WBL, writing that potential to the first terminal of capacitor CB and the gate of transistor M3. Subsequently, applying a low voltage to wire WOL turns off transistor M2, storing the potential of the first terminal of capacitor CB and the gate of transistor M3.
資料的讀出藉由對佈線SL施加預定電位來進行。由於電晶體M3的源極-汲極間流過的電流及電晶體M3的第一端子的電位由電晶體M3的閘極的電位及電晶體M3的第二端子的電位決定，所以藉由讀出與電晶體M3的第一端子連接的佈線RBL的電位，可以讀出電容器CB的第一端子（或電晶體M3的閘極）所保持的電位。也就是說，可以從電容器CB的第一端子（或電晶體M3的閘極）所保持的電位讀出寫入在該記憶單元中的資訊。Data is read by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential at the first terminal of transistor M3 are determined by the potentials of its gate and second terminals, the potential held at the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held at the first terminal of capacitor CB (or the gate of transistor M3).
例如，也可以採用將佈線WBL與佈線RBL合為一個佈線BIL的結構。圖26D示出該情況下的記憶單元的電路結構例子。在記憶單元954中，記憶單元953的佈線WBL與佈線RBL合為一個佈線BIL，電晶體M2的第二端子及電晶體M3的第一端子與佈線BIL連接。也就是說，記憶單元954將寫入位元線和讀出位元線合為一個佈線BIL工作。For example, a structure can also be adopted in which the wiring WBL and the wiring RBL are combined into a single wiring BIL. Figure 26D shows an example of the circuit structure of a memory cell in this case. In memory cell 954, the wiring WBL and the wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 operates as a single wiring BIL, combining the write bit line and the read bit line.
圖26E所示的記憶單元955是省略記憶單元953中的電容器CB及佈線CAL的情況的例子。此外，圖26F所示的記憶單元956是省略記憶單元954中的電容器CB及佈線CAL的情況的例子。藉由採用這種結構，可以提高記憶單元的積體度。Memory cell 955 shown in FIG26E is an example of a case where capacitor CB and wiring CAL are omitted from memory cell 953. Furthermore, memory cell 956 shown in FIG26F is an example of a case where capacitor CB and wiring CAL are omitted from memory cell 954. By adopting this structure, the integration of memory cells can be improved.
注意，較佳為將OS電晶體至少用作電晶體M2。尤其是，較佳為將OS電晶體用作電晶體M2及電晶體M3。Note that it is preferable to use an OS transistor as at least the transistor M2. In particular, it is preferable to use an OS transistor as the transistor M2 and the transistor M3.
因為OS電晶體具有關態電流極小的特性，所以可以利用電晶體M2長時間地保持寫入資料，由此可以降低記憶單元的更新頻率。或者，可以省略記憶單元的更新工作。此外，由於洩漏電流非常低，所以可以在記憶單元953、記憶單元954、記憶單元955及記憶單元956中保持多值資料或類比資料。Because the OS transistor has an extremely low off-state current, transistor M2 can be used to hold written data for a long time, thereby reducing the memory cell update frequency. Alternatively, the memory cell update process can be omitted. Furthermore, due to the extremely low leakage current, multi-valued data or analog data can be held in memory cells 953, 954, 955, and 956.
作為電晶體M2使用OS電晶體的記憶單元953、記憶單元954、記憶單元955及記憶單元956是NOSRAM的一個實施方式。Memory cells 953, 954, 955, and 956 using an OS transistor as transistor M2 are one embodiment of a NOSRAM.
另外，作為電晶體M3也可以使用Si電晶體。Si電晶體可以提高場效移動率並可以為p通道型電晶體，所以可以提高電路設計的彈性。Alternatively, a Si transistor can be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing circuit design flexibility.
此外，當作為電晶體M3使用OS電晶體時，記憶單元可以只由n通道型電晶體構成。Furthermore, when an OS transistor is used as the transistor M3, the memory cell can be composed of only n-channel transistors.
此外，圖26G示出3個電晶體1個電容器的增益單元型記憶單元957。記憶單元957包括電晶體M4至電晶體M6及電容器CC。26G shows a gain unit type memory cell 957 having three transistors and one capacitor. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.
電晶體M4的第一端子與電容器CC的第一端子連接，電晶體M4的第二端子與佈線BIL連接，電晶體M4的閘極與佈線WOL連接。電容器CC的第二端子與電晶體M5的第一端子、佈線GNDL連接。電晶體M5的第二端子與電晶體M6的第一端子連接，電晶體M5的閘極與電容器CC的第一端子連接。電晶體M6的第二端子與佈線BIL連接，電晶體M6的閘極與佈線RWL連接。The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.
佈線BIL被用作位元線，佈線WOL被用作寫入字線，佈線RWL被用作讀出字線。佈線GNDL是供應低位準電位的佈線。The wiring BIL is used as a bit line, the wiring WOL is used as a write word line, and the wiring RWL is used as a read word line. The wiring GNDL is a wiring that supplies a low-level potential.
資料的寫入藉由對佈線WOL施加高位準電位使電晶體M4成為開啟狀態而使佈線BIL與電容器CC的第一端子成為導通狀態來進行。明確地說，在電晶體M4為開啟狀態時，對佈線BIL施加對應於要記錄的資訊的電位來對電容器CC的第一端子及電晶體M5的閘極寫入該電位。然後，對佈線WOL施加低位準電位使電晶體M4成為關閉狀態，由此儲存電容器CC的第一端子的電位及電晶體M5的閘極的電位。Data is written by applying a high voltage to line WOL, turning on transistor M4 and placing line BIL and the first terminal of capacitor CC in a conductive state. Specifically, while transistor M4 is on, a potential corresponding to the data to be recorded is applied to line BIL, writing that potential to the first terminal of capacitor CC and the gate of transistor M5. Subsequently, applying a low voltage to line WOL turns off transistor M4, storing the potential of the first terminal of capacitor CC and the gate of transistor M5.
資料的讀出藉由將佈線BIL預充電至預定電位之後使佈線BIL變為電浮動狀態並對佈線RWL施加高位準電位來進行。藉由使佈線RWL變為高位準電位，電晶體M6成為開啟狀態，佈線BIL與電晶體M5的第二端子成為導通狀態。此時，電晶體M5的第二端子被施加佈線BIL的電位，但是電晶體M5的第二端子的電位及佈線BIL的電位根據電容器CC的第一端子（或電晶體M5的閘極）所保持的電位變化。這裡，可以藉由讀出佈線BIL的電位來讀出電容器CC的第一端子（或電晶體M5的閘極）所保持的電位。也就是說，可以從電容器CC的第一端子（或電晶體M5的閘極）所保持的電位讀出寫入在該記憶單元的資訊。Data is read by precharging wiring BIL to a predetermined potential, then placing it in an electrically floating state and applying a high potential to wiring RWL. This high potential on wiring RWL turns on transistor M6, bringing wiring BIL and the second terminal of transistor M5 into a conductive state. At this point, the potential of wiring BIL is applied to the second terminal of transistor M5. However, the potential of the second terminal of transistor M5 and the potential of wiring BIL vary depending on the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Therefore, by reading the potential of wiring BIL, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read. That is, the information written in the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).
注意，較佳為將OS電晶體至少用作電晶體M4。Note that it is preferable to use an OS transistor as at least transistor M4.
作為電晶體M5及M6也可以使用Si電晶體。如上所述，根據用於半導體層的矽的結晶狀態等，有時Si電晶體的場效移動率比OS電晶體的場效移動率高。Si transistors can also be used as transistors M5 and M6. As mentioned above, depending on the crystal state of silicon used for the semiconductor layer, the field effect mobility of Si transistors may be higher than that of OS transistors.
此外，當作為電晶體M5及M6使用OS電晶體時，記憶單元可以只使用n通道型電晶體構成。Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-channel transistors.
半導體裝置900所具有的驅動電路910及記憶體陣列920設置在同一平面上。此外，如圖27A所示，驅動電路910與記憶體陣列920也可以重疊。藉由使驅動電路910與記憶體陣列920重疊，可以縮短信號傳輸距離。如圖27B所示，也可以在驅動電路910上層疊多個記憶體陣列920。The driver circuit 910 and memory array 920 of semiconductor device 900 are arranged on the same plane. Furthermore, as shown in FIG27A , the driver circuit 910 and memory array 920 can be overlapped. Overlapping the driver circuit 910 and memory array 920 can shorten signal transmission distance. As shown in FIG27B , multiple memory arrays 920 can also be stacked on the driver circuit 910.
接著，說明可以包括上述記憶體裝置等半導體裝置的運算處理裝置的一個例子。Next, an example of an arithmetic processing device that can include a semiconductor device such as the above-mentioned memory device will be described.
圖28是運算裝置960的方塊圖。圖28所示的運算裝置960例如可以用於CPU。此外，運算裝置960也可以用於包括比CPU多（數十個至數百個）的能夠進行並行處理的處理器核心的GPU（Graphics Processing Unit：圖形處理器）及TPU（Tensor Processing Unit：張量處理器）、NPU（Neural Processing Unit：神經處理器）等處理器。Figure 28 is a block diagram of computing device 960. The computing device 960 shown in Figure 28 can be used, for example, in a CPU. Furthermore, computing device 960 can also be used in processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which include more processor cores (tens to hundreds) than a CPU capable of parallel processing.
圖28所示的運算裝置960在基板990上具有：ALU991（ALU：Arithmetic logic unit：算術邏輯單元、運算電路）、ALU控制器992、指令解碼器993、中斷控制器994、時序控制器995、暫存器996、暫存器控制器997、匯流排介面998、快取999以及快取介面989。作為基板990使用半導體基板、SOI基板、玻璃基板等。還可以包括能夠改寫的ROM及ROM介面。快取999及快取介面989也可以設置在不同的晶片上。The arithmetic device 960 shown in Figure 28 includes an ALU 991 (arithmetic logic unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, registers 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. Substrate 990 can be made of a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also include a rewritable ROM and a ROM interface. Cache 999 and cache interface 989 can also be located on separate chips.
快取999藉由快取介面989與設置在不同晶片上的主記憶體連接。快取介面989具有將保持在主記憶體中的資料的一部分供應到快取999的功能。此外，快取介面989具有將保持在快取999中的資料的一部分藉由匯流排介面998輸出到ALU991或暫存器996等的功能。Cache 999 is connected to main memory, which is located on a different chip, via cache interface 989. Cache interface 989 has the function of supplying a portion of the data held in main memory to cache 999. Cache interface 989 also has the function of outputting a portion of the data held in cache 999 to ALU 991, registers 996, and the like via bus interface 998.
如後面所述，可以以層疊在運算裝置960上的方式設置記憶體陣列920。記憶體陣列920可以被用作快取。此時，快取介面989可以具有將保持在記憶體陣列920中的資料供應到快取999的功能。此外，此時，較佳為在快取介面989的一部分包括驅動電路910。As described later, the memory array 920 can be stacked on the computing device 960. Memory array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data stored in the memory array 920 to the cache 999. Furthermore, in this case, it is preferable that a driver circuit 910 be included as part of the cache interface 989.
注意，也可以不設置快取999而僅將記憶體陣列920用作快取。Note that it is also possible not to set cache 999 and only use memory array 920 as cache.
圖28所示的運算裝置960只是簡化其結構而示出的一個例子而已，所以實際上的運算裝置960根據其用途具有各種各樣的結構。例如，較佳為採用以包括圖28所示的運算裝置960的結構為一個核心而設置多個該核心並使其同時工作的所謂的多核結構。核心個數越多，越可以提高運算性能。核心個數越多越佳，例如較佳為2個，更佳為4個，進一步較佳為8個，更進一步較佳為12個，還進一步較佳為16個或其以上。此外，當在伺服器中使用時等需要非常高的運算性能時，較佳為採用包括16個以上、較佳為包括32個以上、更佳為包括64個以上的核心的多核結構。此外，在運算裝置960的內部運算電路、資料匯流排等中能夠處理的位數例如可以為8位元、16位元、32位元、64位元等。The computing device 960 shown in FIG28 is merely an example of a simplified structure, and the actual computing device 960 has various structures depending on its application. For example, it is preferable to adopt a so-called multi-core structure in which a structure including the computing device 960 shown in FIG28 is used as one core and a plurality of such cores are provided and operated simultaneously. The more cores there are, the higher the computing performance can be. The more cores there are, the better, for example, 2 is preferable, 4 is more preferable, 8 is further preferable, 12 is further preferable, and 16 or more is further preferable. In addition, when extremely high computing performance is required, such as when used in a server, it is preferable to adopt a multi-core structure including 16 or more cores, preferably 32 or more cores, and more preferably 64 or more cores. In addition, the number of bits that can be processed in the internal operation circuits, data buses, etc. of the operation device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.
藉由匯流排介面998輸入到運算裝置960的指令在輸入到指令解碼器993並被解碼後輸入到ALU控制器992、中斷控制器994、暫存器控制器997、時序控制器995。The instructions input to the arithmetic device 960 via the bus interface 998 are input to the instruction decoder 993 and decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.
ALU控制器992、中斷控制器994、暫存器控制器997、時序控制器995根據被解碼的指令進行各種控制。明確而言，ALU控制器992生成用來控制ALU991的工作的信號。此外，在運算裝置960執行程式時，中斷控制器994根據其優先度、遮罩狀態等判斷來自外部的輸入輸出裝置、週邊電路等的中斷要求而對該要求進行處理。暫存器控制器997生成暫存器996的位址，並根據運算裝置960的狀態進行暫存器996的讀出及寫入。The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on decoded instructions. Specifically, the ALU controller 992 generates signals used to control the operation of the ALU 991. Furthermore, when the arithmetic device 960 executes a program, the interrupt controller 994 identifies interrupt requests from external I/O devices, peripheral circuits, etc. based on their priority, mask status, and other factors, and processes these requests. The register controller 997 generates addresses for registers 996 and reads and writes to registers 996 based on the status of the arithmetic device 960.
此外，時序控制器995生成用來控制ALU991、ALU控制器992、指令解碼器993、中斷控制器994以及暫存器控制器997的工作時序的信號。例如，時序控制器995具有根據基準時脈信號來生成內部時脈信號的內部時脈生成器，並將內部時脈信號供應到上述各種電路。The timing controller 995 also generates signals for controlling the operation timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generator that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
在圖28所示的運算裝置960中，暫存器控制器997根據ALU991的指令進行暫存器996中的保持工作的選擇。換言之，暫存器控制器997選擇在暫存器996所具有的記憶單元中由正反器保持資料還是由電容器保持資料。在選擇由正反器保持資料的情況下，對暫存器996中的記憶單元供應電源電位。在選擇由電容器保持資料的情況下，對電容器進行資料的改寫，而可以停止對暫存器996中的記憶單元供應電源電位。In the arithmetic device 960 shown in Figure 28, register controller 997 selects the retention operation for register 996 based on instructions from ALU 991. In other words, register controller 997 selects whether the data in the memory cells of register 996 is to be retained by flip-flops or by capacitors. If data retention is selected by flip-flops, power is supplied to the memory cells in register 996. If data retention is selected by capacitors, data is rewritten to the capacitors, and power supply to the memory cells in register 996 can be stopped.
記憶體陣列920與運算裝置960可以重疊地設置。圖29A及圖29B是半導體裝置970A的立體圖。半導體裝置970A在運算裝置960上包括設置有記憶體陣列的層930。層930設置有記憶體陣列920L1、記憶體陣列920L2及記憶體陣列920L3。運算裝置960與各記憶體陣列具有彼此重疊的區域。為了容易理解半導體裝置970A的結構，在圖29B中分離地示出運算裝置960和層930。Memory array 920 and computing device 960 may be arranged overlapping. Figures 29A and 29B are perspective views of semiconductor device 970A. Semiconductor device 970A includes layer 930 on which memory arrays are arranged, above computing device 960. Layer 930 includes memory array 920L1, memory array 920L2, and memory array 920L3. Computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, computing device 960 and layer 930 are shown separately in Figure 29B.
藉由重疊地設置包括記憶體陣列的層930和運算裝置960，可以縮短兩者的連接距離。由此，可以提高兩者之間的通訊速度。此外，因為連接距離較短，所以可以降低功耗。By stacking the memory array layer 930 and the computing device 960, the distance between them can be shortened. This improves communication speed between them. Furthermore, the shorter distance reduces power consumption.
作為包括記憶體陣列的層930和運算裝置960的疊層方法，可以採用如下方法：在運算裝置960上直接層疊包括記憶體陣列的層930（也稱為單片（monolithic）疊層）；或者將運算裝置960和層930分別形成在互不相同的基板上，將兩個基板貼合在一起，而使用穿孔或導電膜的接合技術（Cu-Cu接合等）連接。前者方法中不需要考慮貼合時的錯位，因此不但可以減小晶片尺寸，而且還可以降低製造成本。Methods for stacking the memory array layer 930 and the computing device 960 include: directly stacking the memory array layer 930 on the computing device 960 (also known as monolithic stacking); or forming the computing device 960 and layer 930 on separate substrates, laminating the two substrates, and connecting them using through-hole bonding or conductive film bonding techniques (such as Cu-Cu bonding). The former method eliminates the need to consider misalignment during lamination, thus reducing both chip size and manufacturing costs.
在此，在運算裝置960中可以不包括快取999，並且設置在層930中的記憶體陣列920L1、920L2及920L3都可以被用作快取。此時，例如可以將記憶體陣列920L1、記憶體陣列920L2以及記憶體陣列920L3分別用作L1快取（也稱為一級快取）、L2快取（也稱為二級快取）以及L3快取（也稱為三級快取）。在三個記憶體陣列中，記憶體陣列920L3具有最大的容量及最低的存取頻率。此外，記憶體陣列920L1具有最小的容量及最高的存取頻率。Here, computing device 960 may not include cache 999, and memory arrays 920L1, 920L2, and 920L3 in layer 930 may all be used as caches. In this case, for example, memory array 920L1, memory array 920L2, and memory array 920L3 may be used as an L1 cache (also known as a first-level cache), an L2 cache (also known as a second-level cache), and an L3 cache (also known as a third-level cache), respectively. Of the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.
注意，在將設置在運算裝置960中的快取999用作L1快取時，可以將設置在層930中的各記憶體陣列用作下級快取或主記憶體。主記憶體是具有比快取更大的容量及更低的存取頻率的記憶體。Note that when the cache 999 provided in the computing device 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or main memory. Main memory is a memory having a larger capacity and a lower access frequency than the cache.
此外，如圖29B所示，設置有驅動電路910L1、驅動電路910L2及驅動電路910L3。驅動電路910L1藉由連接電極940L1與記憶體陣列920L1連接。同樣地，驅動電路910L2藉由連接電極940L2與記憶體陣列920L2連接，驅動電路910L3藉由連接電極940L3與記憶體陣列920L3連接。As shown in FIG29B , driver circuits 910L1, 910L2, and 910L3 are provided. Driver circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, driver circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and driver circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.
注意，雖然在此示出用作快取的記憶體陣列為三個的情況，但是也可以為一個、兩個或四個以上。Note that although three memory arrays are shown here as caches, the number may be one, two, or four or more.
在將記憶體陣列920L1用作快取時，驅動電路910L1可以被用作快取介面989的一部分，也可以與快取介面989連接。同樣地，驅動電路910L2、驅動電路910L3也可以被用作快取介面989的一部分或者與快取介面989的一部分連接。When memory array 920L1 is used as a cache, driver circuit 910L1 may be used as part of cache interface 989 or may be connected to cache interface 989. Similarly, driver circuits 910L2 and 910L3 may also be used as part of cache interface 989 or may be connected to a part of cache interface 989.
將記憶體陣列920用作快取還是用作主記憶體取決於各驅動電路910所包括的控制電路912。控制電路912可以根據從運算裝置960供應的信號而將半導體裝置900所包括的多個記憶單元950的一部分用作RAM。Whether the memory array 920 is used as a cache or a main memory depends on the control circuit 912 included in each driver circuit 910. The control circuit 912 can use a portion of the plurality of memory cells 950 included in the semiconductor device 900 as RAM based on a signal supplied from the operation device 960.
在半導體裝置900中，可以將多個記憶單元950的一部分用作快取並將其他一部分用作主記憶體。也就是說，半導體裝置900可以具有作為快取的功能和作為主記憶體的功能。根據本發明的一個實施方式的半導體裝置900例如可以被用作通用記憶體。In semiconductor device 900, some of the multiple memory cells 950 can be used as cache, while others can be used as main memory. In other words, semiconductor device 900 can function as both a cache and a main memory. For example, semiconductor device 900 according to one embodiment of the present invention can be used as general-purpose memory.
此外，也可以以與運算裝置960重疊的方式設置包括一個記憶體陣列920的層930。圖30A是半導體裝置970B的立體圖。Alternatively, a layer 930 including a memory array 920 may be provided in an overlapping manner with the computing device 960. FIG30A is a perspective view of a semiconductor device 970B.
在半導體裝置970B中，可以將一個記憶體陣列920分割為多個區域並對該多個區域賦予不同功能而使用。圖30A示出將區域L1、區域L2以及區域L3分別用作L1快取、L2快取以及L3快取的情況的例子。In the semiconductor device 970B, a memory array 920 can be divided into multiple areas and each area can be assigned different functions. FIG30A shows an example where area L1, area L2, and area L3 are used as L1 cache, L2 cache, and L3 cache, respectively.
此外，在半導體裝置970B中，可以根據狀況改變區域L1至區域L3的每一個的容量。例如，在想要增大L1快取的容量時，藉由增大區域L1的面積來實現。藉由採用這種結構，可以實現運算處理的高效化而提高處理速度。Furthermore, in semiconductor device 970B, the capacity of each of areas L1 through L3 can be adjusted according to circumstances. For example, if the capacity of the L1 cache is desired to be increased, this can be achieved by increasing the area of area L1. This structure improves computational efficiency and increases processing speed.
此外，也可以層疊多個記憶體陣列。圖30B是半導體裝置970C的立體圖。In addition, multiple memory arrays can also be stacked. Figure 30B is a perspective view of a semiconductor device 970C.
半導體裝置970C中層疊有包括記憶體陣列920L1的層930L1、其上的包括記憶體陣列920L2的層930L2以及其上的包括記憶體陣列920L3的層930L3。可以將物理上最靠近運算裝置960的記憶體陣列920L1用作上級快取並將最遠離運算裝置960的記憶體陣列920L3用作下級快取或主記憶體。藉由採用這種結構，可以增大各記憶體陣列的容量，因此可以進一步提高處理能力。Semiconductor device 970C has stacked layers: layer 930L1, which includes memory array 920L1; layer 930L2, which includes memory array 920L2; and layer 930L3, which includes memory array 920L3. Memory array 920L1, which is physically closest to computing device 960, can be used as an upper-level cache, while memory array 920L3, which is farthest from computing device 960, can be used as a lower-level cache or main memory. This structure increases the capacity of each memory array, further improving processing capabilities.
本實施方式可以與其他實施方式適當地組合。此外，在本說明書中，在一個實施方式中示出多個結構例子的情況下，可以適當地組合該結構例子。This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.
實施方式5 在本實施方式中，參照圖31A至圖31C說明本發明的一個實施方式的包括OS電晶體的電路結構的一個例子及使用本發明的一個實施方式的半導體裝置的電子構件的一個例子。Embodiment 5This embodiment describes an example of a circuit structure including an OS transistor according to an embodiment of the present invention and an example of an electronic component using a semiconductor device according to an embodiment of the present invention, with reference to Figures 31A to 31C.
＜電路結構例子＞ 圖31A及圖31B示出包括本發明的一個實施方式的OS電晶體的電路結構的一個例子。圖31A所示的電路圖示出由所謂的CMOS（Complementary Metal Oxide Semiconductor：互補金屬氧化物半導體）電路構成的反相器電路的結構，其中n通道型電晶體3102與p通道型電晶體3104串聯連接且各閘極連接。此外，圖31B所示的電路圖示出n通道型電晶體3102與p通道型電晶體3104的各源極及汲極連接且用作所謂的類比開關的電路的結構。<Circuit Structure Example>Figures 31A and 31B illustrate an example of a circuit structure including an OS transistor according to one embodiment of the present invention. The circuit diagram shown in Figure 31A illustrates the structure of an inverter circuit formed using a so-called CMOS (Complementary Metal Oxide Semiconductor) circuit, in which an n-channel transistor 3102 and a p-channel transistor 3104 are connected in series with their gates connected. Furthermore, the circuit diagram shown in Figure 31B illustrates the structure of a circuit functioning as a so-called analog switch, in which the source and drain electrodes of the n-channel transistor 3102 and the p-channel transistor 3104 are connected.
＜電晶體結構＞ 作為圖31A和圖31B所示的n通道型電晶體3102及p通道型電晶體3104，可以使用各種類型的電晶體。明確而言，可以使用平面型電晶體、垂直電晶體（VFET：Vertical Field Effect Transistor）、Fin（鰭）型電晶體、GAA（Gate All Around：全環繞閘極）型電晶體等作為n通道型電晶體3102及p通道型電晶體3104。此外，也可以使用組合n通道型電晶體3102和p通道型電晶體3104的CFET（Complementary Field Effect Transistor：互補場效電晶體）。<Transistor Structure>N-channel transistor 3102 and p-channel transistor 3104 shown in Figures 31A and 31B can be made of various types of transistors. Specifically, planar transistors, vertical transistors (VFETs), fin transistors, GAA (Gate All Around) transistors, and the like can be used as n-channel transistor 3102 and p-channel transistor 3104. Furthermore, a CFET (Complementary Field Effect Transistor) combining n-channel transistor 3102 and p-channel transistor 3104 can also be used.
在本說明書等中，平面型電晶體是指源極電極和汲極電極位於相同或大致相同的高度且流過半導體的電流具有橫向成分的結構。此外，在本說明書等中，VFET是指源極電極和汲極電極位於不同高度且流過半導體的電流具有高度方向成分的結構。因為VFET可以層疊源極電極、半導體和汲極電極中的兩個以上，所以可以與平面型電晶體相比大幅度地縮小佔有面積。In this specification and other documents, a planar transistor refers to a structure in which the source and drain electrodes are located at the same or approximately the same height, and the current flowing through the semiconductor has a lateral component. Furthermore, a VFET refers to a structure in which the source and drain electrodes are located at different heights, and the current flowing through the semiconductor has a vertical component. Because a VFET can stack two or more of the source electrode, semiconductor, and drain electrode, it can significantly reduce its footprint compared to a planar transistor.
此外，在本說明書等中，Fin型電晶體是指在通道寬度方向的剖視中閘極電極隔著閘極絕緣膜覆蓋通道的兩個面以上的結構。尤其是，在通道寬度方向的剖視中，當通道高度（H）大於通道寬度（W）時，可以增大單位面積的通道寬度，所以是較佳的。此外，在本說明書等中，GAA型電晶體是指在通道寬度方向的剖視中閘極電極隔著閘極絕緣膜覆蓋通道的四個面的結構。In this specification, etc., the term "Fin-type transistor" refers to a structure in which, when viewed in a cross-section along the channel width, the gate electrode covers two or more sides of the channel via a gate insulating film. In particular, when viewed in a cross-section along the channel width, a channel height (H) greater than the channel width (W) is preferred because it increases the channel width per unit area. Furthermore, in this specification, etc., the term "GaAs-type transistor" refers to a structure in which, when viewed in a cross-section along the channel width, the gate electrode covers all four sides of the channel via a gate insulating film.
＜n通道型電晶體＞ 作為圖31A及圖31B所示的n通道型電晶體3102，可以使用本發明的一個實施方式的OS電晶體。OS電晶體具有關態電流極小的特性，所以可以使電晶體3102的洩漏電流極為小。此外，作為n通道型電晶體3102的半導體材料，可以使用矽或鍺等單個元素的半導體、砷化鎵等化合物半導體或者用作半導體的層狀物質等。尤其是，較佳為使用用作半導體的層狀物質作為半導體材料。<N-Channel Transistor>As n-channel transistor 3102 shown in Figures 31A and 31B , an OS transistor according to one embodiment of the present invention can be used. OS transistors have extremely low off-state current, thus minimizing leakage current in transistor 3102. Furthermore, the semiconductor material for n-channel transistor 3102 can include single-element semiconductors such as silicon or germanium, compound semiconductors such as gallium arsenide, or semiconductor layered materials. In particular, the use of semiconductor layered materials is preferred.
在本說明書等中，層狀物質是具有層狀晶體結構的材料群的總稱。層狀晶體結構是由共價鍵或離子鍵形成的層藉由如凡得瓦鍵那樣的比共價鍵及離子鍵弱的鍵合層疊的結構。層狀物質在單位層中具有高導電性，亦即，具有高二維導電性。藉由將用作半導體並具有高二維導電性的材料用於通道形成區域，可以提供通態電流大的電晶體。In this specification and other documents, "layered materials" is a general term for materials with a layered crystal structure. A layered crystal structure consists of layers formed by covalent or ionic bonds, stacked together through bonds weaker than these bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within their individual layers, i.e., high two-dimensional conductivity. By using a semiconductor material with high two-dimensional conductivity in the channel-forming region, transistors with high on-state current can be provided.
此外，在本說明書等中，有時將上述層狀物質稱為二維材料。作為可用於本發明的一個實施方式的二維材料，可以將石墨烯、矽烯（使用矽原子代替石墨烯的碳原子的物質）、鍺烯（使用鍺原子代替石墨烯的碳原子的物質）、過渡金屬硫族化物（Transition Metal Dichalcogenides：TMDs）、氮化硼（BN）、黑磷等分別用於n通道型電晶體3102及p通道型電晶體3104。另外，藉由使用上述二維材料，與矽或鍺等單個元素的半導體相比，可以提高電子移動率、機械強度和熱傳導率中的一個或多個物性。此外，因為上述二維材料的物性比單個元素的半導體優異，所以也可以將上述二維材料稱為NMC（New Materials Channel：新材料通道）。In this specification and other documents, the layered materials described above are sometimes referred to as two-dimensional materials. Two-dimensional materials that can be used in one embodiment of the present invention include graphene, silicene (a material in which silicon atoms replace the carbon atoms in graphene), germane (a material in which germanium atoms replace the carbon atoms in graphene), transition metal dichalcogenides (TMDs), boron nitride (BN), and black phosphorus, which can be used for the n-channel transistor 3102 and the p-channel transistor 3104, respectively. Furthermore, the use of these two-dimensional materials can improve one or more of the following physical properties: electron mobility, mechanical strength, and thermal conductivity, compared to semiconductors composed of a single element, such as silicon or germanium. Furthermore, because these two-dimensional materials have superior physical properties compared to semiconductors made from a single element, they can also be referred to as NMC (New Materials Channel).
另外，作為層狀物質，有硫族化物等。硫族化物是包含硫族元素的化合物。此外，硫族元素是屬於第16族的元素的總稱，其中包括氧、硫、硒、碲、釙、鉝。此外，作為硫族化物，可以舉出過渡金屬硫族化物、第13族硫族化物等。Other layered materials include chalcogenides. Chalcogenides are compounds containing chalcogen elements. Chalcogen elements are a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, prodigium, and lead. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
此外，作為可用於電晶體3102的材料，例如較佳為使用用作半導體的過渡金屬硫族化物。作為該過渡金屬硫族化物，具體地可以舉出硫化鉬（典型的是MoS2）、硒化鉬（典型的是MoSe2）、碲化鉬（典型的是MoTe2）、硫化鎢（典型的是WS2）、硒化鎢（典型的是WSe2）、碲化鎢（典型的是WTe2）、硫化鉿（典型的是HfS2）、硒化鉿（典型的是HfSe2）、硫化鋯（典型的是ZrS2）、硒化鋯（典型的是ZrSe2）等。Furthermore, a transition metal chalcogenide used as a semiconductor is preferably used as a material that can be used for the transistor 3102. Specific examples of such transition metal chalcogenides include molybdenum sulfide (typicallyMoS2 ), molybdenum selenide (typicallyMoSe2 ), molybdenum telluride (typically MoTe2), tungsten sulfide (typicallyWS2) , tungsten selenide (typicallyWSe2 ), tungsten telluride (typicallyWTe2 ), eumium sulfide (typicallyHfS2 ), eumium selenide (typicallyHfSe2 ), zirconium sulfide (typicallyZrS2 ), and zirconium selenide (typicallyZrSe2 ).
＜p通道型電晶體＞ 作為圖31A及圖31B所示的p通道型電晶體3104的半導體材料，可以使用矽或鍺等單個元素的半導體、砷化鎵等化合物半導體或者用作半導體的層狀物質等。尤其是，較佳為使用用作半導體的層狀物質作為半導體材料。<P-Channel Transistor>The semiconductor material for the p-channel transistor 3104 shown in Figures 31A and 31B can be a single element semiconductor such as silicon or germanium, a compound semiconductor such as gallium arsenide, or a semiconductor layered material. In particular, a semiconductor layered material is preferably used as the semiconductor material.
此外，作為可用於電晶體3104的材料，例如較佳為使用用作半導體的過渡金屬硫族化物。作為該過渡金屬硫族化物，具體地可以舉出硫化鉬（典型的是MoS2）、硒化鉬（典型的是MoSe2）、硫化鎢（典型的是WS2）、硒化鎢（典型的是WSe2）等。Furthermore, a transition metal chalcogenide used as a semiconductor is preferably used as a material that can be used for the transistor 3104. Specific examples of such transition metal chalcogenides include molybdenum sulfide (typically MoS2 ), molybdenum selenide (typically MoSe2 ), tungsten sulfide (typically WS2 ), and tungsten selenide (typically WSe2 ).
此外，作為可用於電晶體3104的材料，除了上述二維材料之外，還可以使用3-5族化合物半導體（典型的是，鎵-砷化合物半導體、銦-磷化合物半導體、銦-鎵-砷化合物半導體、銦-砷化合物半導體等）、碳奈米管（CNT）、硫化錫（典型的是SnS）、硒化錫（典型的是SnSe）等。注意，也可以將第3-5族化合物半導體用於電晶體3102。In addition to the two-dimensional materials described above, materials that can be used for the transistor 3104 include Group III-V compound semiconductors (typically, gallium-arsenic compound semiconductors, indium-phosphorus compound semiconductors, indium-gallium-arsenic compound semiconductors, indium-arsenic compound semiconductors, etc.), carbon nanotubes (CNTs), tin sulfide (typically SnS), and tin selenide (typically SnSe). Note that Group III-V compound semiconductors can also be used for the transistor 3102.
＜電子構件例子＞ 圖31C示出使用本發明的一個實施方式的半導體裝置的電子構件的一個例子。使用本發明的一個實施方式的半導體裝置的電子構件是對低功耗化及高性能化有效果的。<Example of Electronic Component>Figure 31C shows an example of an electronic component using a semiconductor device according to an embodiment of the present invention. An electronic component using a semiconductor device according to an embodiment of the present invention is effective in achieving low power consumption and high performance.
圖31C是安裝有電子構件3110的基板（安裝基板3210）的立體圖。圖31C所示的電子構件3110在模子3111內包括記憶體裝置3112。為了示出電子構件3110的內部，在圖31C中省略部分記載。電子構件3110在模子3111的外側包括連接盤3113。連接盤3113與電極焊盤3114連接，電極焊盤3114與記憶體裝置3112藉由引線3115連接。電子構件3110例如安裝在印刷電路板3212中。藉由組合多個上述電子構件並在印刷電路板3212上使該多個電子構件彼此連接，由此製造安裝基板3210。Figure 31C is a perspective view of a substrate (mounting substrate 3210) on which electronic component 3110 is mounted. Electronic component 3110 shown in Figure 31C includes a memory device 3112 within a mold 3111. To illustrate the interior of electronic component 3110, some parts are omitted in Figure 31C. Electronic component 3110 includes connection pads 3113 on the outside of mold 3111. Connection pads 3113 are connected to electrode pads 3114, which are in turn connected to memory device 3112 via leads 3115. Electronic component 3110 is mounted on, for example, a printed circuit board 3212. The mounting substrate 3210 is manufactured by combining a plurality of the above-mentioned electronic components and connecting the plurality of electronic components to each other on the printed circuit board 3212 .
另外，記憶體裝置3112包括具有運算核的層3121及具有記憶體的層3122。例如，層3121和層3122的兩者可以使用上述n通道型電晶體及p通道型電晶體。尤其較佳的是，藉由將p通道型電晶體用於層3121且將n通道型電晶體用於層3122，構成CMOS電路。但是，本發明的一個實施方式不侷限於此，也可以採用在層3121中使用n通道型電晶體和p通道型電晶體的兩者且在層3122中使用n通道型電晶體的結構。Memory device 3112 includes layer 3121 having a computing core and layer 3122 having a memory. For example, both layer 3121 and layer 3122 may use the aforementioned n-channel transistors and p-channel transistors. It is particularly preferred that a CMOS circuit be constructed by using p-channel transistors for layer 3121 and n-channel transistors for layer 3122. However, one embodiment of the present invention is not limited to this, and a structure using both n-channel and p-channel transistors in layer 3121 and n-channel transistors in layer 3122 may also be employed.
明確而言，較佳為採用層3121包括p通道型電晶體3301且層3122包括n通道型電晶體3302的結構。在圖31C中，藉由作為電晶體3301所包括的半導體層3311使用p型矽且作為電晶體3302所包括的半導體層3312使用n型氧化物半導體，可以形成Si電晶體與OS電晶體的疊層結構。Specifically, it is preferable to adopt a structure in which layer 3121 includes p-channel transistor 3301 and layer 3122 includes n-channel transistor 3302. In FIG31C , by using p-type silicon as semiconductor layer 3311 included in transistor 3301 and using n-type oxide semiconductor as semiconductor layer 3312 included in transistor 3302, a stacked structure of Si transistors and OS transistors can be formed.
或者，在圖31C中，藉由作為電晶體3301所包括的半導體層3311使用p通道型二維材料（例如，WS2）且作為電晶體3302所包括的半導體層3312使用n通道型氧化物半導體，可以形成WS2電晶體與OS電晶體的疊層結構。藉由採用該疊層結構，可以提供一種功耗低且性能高的記憶體裝置。Alternatively, in FIG31C , by using a p-channel two-dimensional material (e.g., WS2 ) as semiconductor layer 3311 included in transistor 3301 and an n-channel oxide semiconductor as semiconductor layer 3312 included in transistor 3302, a stacked structure of WS2 transistors and OS transistors can be formed. This stacked structure can provide a memory device with low power consumption and high performance.
如此，藉由層疊兩種電晶體，電路的佔有面積得到降低，可以以更高密度配置多個電路。注意，圖31C示出電晶體3301為Fin型電晶體且電晶體3302為VFET的結構，但是不侷限於此，也可以將Fin型電晶體用作電晶體3301且將Fin型電晶體用作電晶體3302。藉由使電晶體3301的結構與電晶體3302的結構不同，可以獲得對應於各電晶體結構的特性，所以是較佳的。另外，在電晶體3301的結構與電晶體3302的結構相同時，可以共同使用部分製造裝置，所以是較佳的。By stacking the two transistors in this way, the circuit area occupied is reduced, allowing multiple circuits to be arranged at a higher density. Note that FIG31C shows a structure in which transistor 3301 is a Fin-type transistor and transistor 3302 is a VFET, but the present invention is not limited to this. A Fin-type transistor can also be used as transistor 3301 and a Fin-type transistor can be used as transistor 3302. By making the structures of transistor 3301 and transistor 3302 different, characteristics corresponding to the structures of each transistor can be obtained, which is preferable. In addition, when the structures of transistor 3301 and transistor 3302 are the same, some manufacturing equipment can be shared, which is also preferable.
另外，包括記憶體的層3122具有層疊有多個記憶單元陣列的結構。層疊包括運算核的層3121與包括記憶體的層3122而成的結構可以說是單片疊層結構。在單片疊層結構中，可以不使用TSV（Through Silicon Via）等穿孔電極技術及Cu-Cu直接接合等接合技術而連接各層間。藉由以單片的方式層疊包括運算核的層3121與包括記憶體的層3122，例如可以實現在處理器上直接形成記憶體的所謂的晶載記憶體的結構。藉由採用晶載記憶體的結構，可以實現處理器與記憶體的介面部分的高速工作。此外，也可以使包括記憶體的層3122的一部分具有包括運算核的層3121的功能的一部分（運算功能的一部分）。Furthermore, layer 3122 including memory has a structure with multiple memory cell arrays stacked on top of each other. The structure formed by stacking layer 3121 including computing cores and layer 3122 including memory can be described as a monolithic stacked structure. In a monolithic stacked structure, it is possible to connect the layers without using through-hole electrode technologies such as TSV (Through Silicon Via) or bonding technologies such as Cu-Cu direct bonding. By stacking layer 3121 including computing cores and layer 3122 including memory on a monolithic basis, a so-called on-chip memory structure can be achieved, in which memory is directly formed on the processor. By adopting an on-chip memory structure, the interface between the processor and memory can operate at high speed. In addition, a portion of the layer 3122 including the memory can also have a portion of the functions of the layer 3121 including the computing core (a portion of the computing function).
另外，在採用晶載記憶體的結構時，與使用TSV等穿孔電極的技術相比，可以進一步縮小連接佈線等的尺寸，因此可以增加引腳數量。藉由增加引腳數量可以進行並聯工作，由此可以提高記憶體的頻寬（也稱為記憶體頻寬）。Furthermore, when using an on-chip memory structure, the dimensions of the connection wiring can be further reduced compared to technologies using through-hole vias such as TSV, thereby increasing the number of pins. Increasing the number of pins allows for parallel operation, thereby increasing the memory bandwidth (also known as memory bandwidth).
另外，較佳的是，使用OS電晶體形成包括記憶體的層3122所包括的多個記憶單元陣列，並使該多個記憶單元陣列具有單片疊層結構。藉由使多個記憶單元陣列具有單片疊層結構，可以提高記憶體的頻寬和記憶體的訪問延遲中的一者或兩者。注意，頻寬是指單位時間的資料傳輸量，訪問延遲是指訪問和開始資料的交換之間的時間。注意，當在包括記憶體的層3122中使用Si電晶體時，與使用OS電晶體的情況相比，難以實現單片疊層結構。因此，在單片疊層結構中，可以說OS電晶體是比Si電晶體優異的結構。In addition, it is preferable to use OS transistors to form the multiple memory cell arrays included in the layer 3122 including the memory, and to give the multiple memory cell arrays a monolithic stacked structure. By giving the multiple memory cell arrays a monolithic stacked structure, one or both of the memory bandwidth and the memory access delay can be improved. Note that bandwidth refers to the amount of data transferred per unit time, and access delay refers to the time between access and the start of data exchange. Note that when Si transistors are used in the layer 3122 including the memory, it is more difficult to achieve a monolithic stacked structure than when OS transistors are used. Therefore, in a monolithic stacked structure, it can be said that OS transistors are superior to Si transistors.
本實施方式可以與其他實施方式適當地組合。此外，在本說明書中，在一個實施方式中示出多個結構例子的情況下，可以適當地組合該結構例子。This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.
實施方式6 在本實施方式中說明本發明的一個實施方式的顯示裝置。Embodiment 6This embodiment describes a display device according to one embodiment of the present invention.
本發明的一個實施方式的半導體裝置可以用於顯示裝置或包括該顯示裝置的模組。作為包括該顯示裝置的模組，可以舉出該顯示裝置安裝有軟性印刷電路板（Flexible printed circuit，下面記為FPC）或TCP（Tape Carrier Package：捲帶式封裝）等連接器的模組、藉由COG（Chip On Glass：晶粒玻璃接合）方式或COF（Chip On Film：薄膜覆晶封裝）方式等安裝有積體電路（IC）的模組等。A semiconductor device according to one embodiment of the present invention can be used in a display device or a module including such a display device. Examples of such a module include a module in which a connector such as a flexible printed circuit (FPC) or TCP (Tape Carrier Package) is mounted on the display device, and a module in which an integrated circuit (IC) is mounted using a COG (Chip On Glass) or COF (Chip On Film) method.
此外，本實施方式的顯示裝置也可以具有觸控面板的功能。例如，可以將能夠檢測出手指等檢測物件的接近或接觸的各種檢測元件（也可以稱為感測器元件）用於顯示裝置。In addition, the display device of this embodiment may also have the function of a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection object such as a finger can be used in the display device.
例如，作為感測器的方式，可以舉出靜電電容式、電阻膜式、表面聲波式、紅外線式、光學式及壓敏式。For example, as sensor types, there are electrostatic capacitance type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
作為靜電電容式，例如有表面型靜電電容式、投影型靜電電容式。此外，作為投影型靜電電容式，例如有自電容式、互電容式。較佳為使用互電容式，由此可以同時進行多點檢測。Examples of electrostatic capacitance methods include surface electrostatic capacitance and projected electrostatic capacitance. Projected electrostatic capacitance methods also include self-capacitance and mutual capacitance. Mutual capacitance is preferred because it allows for simultaneous multi-point detection.
作為觸控面板，例如可以舉出Out-Cell型、On-Cell型及In-Cell型。注意，In-Cell型觸控面板是指在支撐顯示元件的基板和相對基板中的一者或兩者設置有構成檢測元件的電極的結構。Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel has electrodes forming a detection element disposed on one or both of a substrate supporting a display element and a counter substrate.
[顯示模組] 圖32A示出顯示模組170的立體圖。顯示模組170包括顯示裝置600A及FPC298。注意，該顯示模組170所包括的顯示裝置不侷限於顯示裝置600A，也可以為後面說明的顯示裝置600B。[Display Module]Figure 32A shows a perspective view of display module 170. Display module 170 includes display device 600A and FPC 298. Note that the display device included in display module 170 is not limited to display device 600A and can also be display device 600B, described later.
顯示模組170包括基板291及基板299。顯示模組170包括顯示部297。顯示部297是顯示模組170中的影像顯示區域，並是可以看到來自設置在下述像素部294中的各像素的光的區域。The display module 170 includes a substrate 291 and a substrate 299. The display module 170 includes a display portion 297. The display portion 297 is an image display region in the display module 170 and is a region where light from each pixel provided in the pixel portion 294 described below can be seen.
圖32B是基板291一側的結構的立體示意圖。基板291上層疊有電路部292、電路部292上的像素電路部293及像素電路部293上的像素部294。此外，基板291的不與像素部294重疊的部分上設置有用來連接到FPC298的端子部295。端子部295與電路部292藉由由多個佈線構成的佈線部296連接。Figure 32B is a schematic three-dimensional diagram of the structure of one side of substrate 291. Stacked on substrate 291 are a circuit section 292, a pixel circuit section 293 on circuit section 292, and a pixel section 294 on pixel circuit section 293. Furthermore, a terminal section 295 for connecting to an FPC 298 is provided on the portion of substrate 291 that does not overlap with pixel section 294. Terminal section 295 is connected to circuit section 292 via a wiring section 296 composed of multiple wiring lines.
本發明的一個實施方式的半導體裝置可以應用於電路部292和像素電路部293中的一者或兩者。The semiconductor device according to one embodiment of the present invention can be applied to one or both of the circuit portion 292 and the pixel circuit portion 293.
像素部294包括週期性地排列的多個像素294a。圖32B的右側示出一個像素294a的放大圖。圖32B示出一個像素294a包括呈現紅色光的子像素130R、呈現綠色光的子像素130G及呈現藍色光的子像素130B的例子。The pixel portion 294 includes a plurality of pixels 294a arranged periodically. An enlarged view of one pixel 294a is shown on the right side of FIG32B. FIG32B shows an example in which one pixel 294a includes a sub-pixel 130R that emits red light, a sub-pixel 130G that emits green light, and a sub-pixel 130B that emits blue light.
子像素包括顯示元件。作為顯示元件可以使用各種元件，例如可以舉出液晶元件及發光元件。除此之外，還可以使用快門方式或光干涉方式的MEMS（Micro Electro Mechanical Systems：微機電系統）元件、採用微囊方式、電泳方式、電潤濕方式或電子粉流體（註冊商標）方式等的顯示元件等。此外，也可以使用利用光源以及採用量子點材料的顏色轉換技術的QLED（Quantum-dot LED：量子點發光二極體）。Subpixels include display elements. Various elements can be used as display elements, including liquid crystal elements and light-emitting elements. Other possible display elements include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, and display elements using microcapsule, electrophoresis, electrowetting, or electronic powder fluid (registered trademark) methods. Furthermore, QLEDs (Quantum-dot LEDs), which utilize color conversion technology using quantum dot materials as a light source, can also be used.
作為發光元件，例如可以舉出LED（Light Emitting Diode：發光二極體）、OLED（Organic LED：有機發光二極體）或半導體雷射器等自發光性發光元件。作為LED，例如可以使用小型LED或微型LED等。Examples of light-emitting elements include self-luminous elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. Examples of LEDs include miniature LEDs and microLEDs.
對本實施方式的顯示裝置中的像素的排列沒有特別的限制，可以採用各種方法。作為像素的排列，例如可以舉出條紋排列、S條紋排列、矩陣狀排列、Delta排列、拜耳排列（Bayer arrangement）及Pentile排列。圖32B示出像素的排列採用條紋排列的情況的例子。There are no particular restrictions on the arrangement of pixels in the display device of this embodiment; various methods can be employed. Examples of pixel arrangements include stripe, S-stripe, matrix, delta, Bayer, and Pentile arrangements. Figure 32B illustrates an example of a stripe arrangement.
像素電路部293包括週期性地排列的多個像素電路293a。The pixel circuit portion 293 includes a plurality of pixel circuits 293a arranged periodically.
一個像素電路293a控制一個像素294a所包括的多個元件的驅動。一個像素電路293a中可以設置有三個控制一個發光元件的發光的電路。例如，像素電路293a可以採用對於一個發光元件至少具有一個選擇電晶體、一個電流控制用電晶體（驅動電晶體）和電容器的結構。此時，選擇電晶體的閘極被輸入閘極信號，源極被輸入源極信號。由此，實現主動矩陣型顯示裝置。A pixel circuit 293a controls the driving of multiple elements within a pixel 294a. A single pixel circuit 293a can include three circuits for controlling the emission of a single light-emitting element. For example, pixel circuit 293a can employ a structure comprising at least one select transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting element. A gate signal is input to the gate of the select transistor, and a source signal is input to its source. This creates an active matrix display device.
電路部292包括驅動像素電路部293的各像素電路293a的電路。例如，較佳為包括閘極線驅動電路和源極線驅動電路中的一者或兩者。此外，還可以具有運算電路、記憶體電路和電源電路等中的至少一個。The circuit section 292 includes a circuit for driving each pixel circuit 293a of the pixel circuit section 293. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, it may also include at least one of a calculation circuit, a memory circuit, and a power supply circuit.
FPC298被用作從外部向電路部292供給視頻信號或電源電位等的佈線。此外，也可以在FPC298上安裝IC。The FPC 298 is used as a wiring for supplying video signals or power potential from the outside to the circuit portion 292. In addition, an IC can also be mounted on the FPC 298.
顯示模組170可以採用像素部294的下側重疊設置有像素電路部293和電路部292中的一者或兩者的結構，所以可以使顯示部297具有極高的開口率（有效顯示面積比）。此外，能夠極高密度地配置像素294a，由此可以使顯示部297具有極高的清晰度。Display module 170 can employ a structure in which one or both of pixel circuit portion 293 and circuit portion 292 are stacked below pixel portion 294. This allows display portion 297 to have an extremely high aperture ratio (effective display area ratio). Furthermore, pixels 294a can be arranged at an extremely high density, thereby achieving extremely high definition on display portion 297.
這種清晰度極高的顯示模組170適合用於HMD等VR用設備或眼鏡型AR用設備。例如，因為顯示模組170具有清晰度極高的顯示部297，所以即使在透過透鏡觀看顯示模組170的顯示部的情況下用透鏡放大顯示部也看不到像素，由此可以實現沉浸感高的的顯示。此外，顯示模組170不侷限於此，還可以應用於具有較小型的顯示部的電子裝置。例如，適合用於手錶型裝置等可穿戴式電子裝置的顯示部。This extremely high-definition display module 170 is suitable for use in VR devices such as HMDs or glasses-type AR devices. For example, because display module 170 has an extremely high-definition display portion 297, even when viewing the display portion of display module 170 through a lens, the pixels are invisible when the lens is magnified, thus achieving a highly immersive display. Furthermore, display module 170 is not limited to this application and can also be applied to electronic devices with relatively small display portions. For example, it is suitable for use in the display portion of wearable electronic devices such as watches.
[顯示裝置的結構例子1] 圖33是顯示裝置600A的剖面圖。顯示裝置600A是採用MML（Metal Mask Less）結構的顯示裝置的一個例子。也就是說，顯示裝置600A包括不用高精細金屬遮罩製造的發光元件。[Display Device Structure Example 1]Figure 33 is a cross-sectional view of display device 600A. Display device 600A is an example of a display device employing an MML (Metal Mask Less) structure. In other words, display device 600A includes light-emitting elements manufactured without using a high-precision metal mask.
採用MML結構的顯示裝置所包括的發光元件中的島狀發光層藉由在整個面上沉積發光層之後利用光微影法進行加工來形成。因此，可以實現至今難以實現的高清晰的顯示裝置或高開口率的顯示裝置。再者，由於可以按每種顏色分別形成發光層，所以可以實現極為鮮明、對比度高且顯示品質高的顯示裝置。例如，在使用發射藍色光的發光元件、發射綠色光的發光元件及發射紅色光的發光元件這三種構成顯示裝置時，可以藉由反復進行三次的發光層的沉積及利用光微影的加工來形成三種島狀發光層。The island-shaped light-emitting layers in the light-emitting elements included in a display device using an MML structure are formed by depositing the light-emitting layer over the entire surface and then processing it using photolithography. This makes it possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layer can be formed separately for each color, a display device with extremely bright colors, high contrast, and high display quality can be realized. For example, when a display device is composed of three light-emitting elements: a light-emitting element that emits blue light, a light-emitting element that emits green light, and a light-emitting element that emits red light, the three island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and the photolithography process three times.
因為具有MML結構的器件可以不使用金屬遮罩製造，所以可以超過起因於金屬遮罩的對準精度的清晰度的上限。此外，在不使用金屬遮罩製造器件的情況下，可以不需要與金屬遮罩的製造有關的設備及金屬遮罩的清洗製程。此外，在利用光微影的加工中，可以使用與在製造電晶體時使用的設備共同或同樣的設備，從而不需要為了製造具有MML結構的器件而導入特別的設備。如此，借助於MML結構，可以降低製造成本，所以適合於器件的大量生產。Because devices with an MML structure can be manufactured without a metal mask, the upper limit of resolution due to the metal mask's alignment accuracy can be exceeded. Furthermore, when devices are manufactured without a metal mask, the equipment associated with metal mask manufacturing and the metal mask cleaning process are no longer required. Furthermore, photolithography processing can utilize the same or identical equipment used in transistor manufacturing, eliminating the need for specialized equipment specifically designed for MML device manufacturing. Thus, the MML structure can reduce manufacturing costs, making it suitable for mass production of devices.
在具有MML結構的顯示裝置中，例如不需要採用Pentile排列等特殊像素排列來以偽方式提高清晰度，由此可以實現一種顯示裝置，該顯示裝置採用將R、G、B的各子像素排列在一個方向上的所謂的條紋排列且具有高清晰度（例如，500ppi以上，1000ppi以上，2000ppi以上，3000ppi以上或5000ppi以上）。In a display device having an MML structure, for example, there is no need to adopt a special pixel arrangement such as a Pentile arrangement to pseudo-enhance definition. Thus, a display device can be realized that adopts a so-called stripe arrangement in which R, G, and B sub-pixels are arranged in one direction and has high definition (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more).
此外，藉由在發光層上設置犧牲層，可以降低在顯示裝置的製程中發光層受到的損傷，而可以提高發光元件的可靠性。另外，犧牲層可以殘留在完成的顯示裝置中，也可以在製程中被去除。例如，圖33及圖34所示的犧牲層618a是設置在發光層上的犧牲層的一部分。Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the display device manufacturing process can be reduced, thereby improving the reliability of the light-emitting element. Furthermore, the sacrificial layer can remain in the finished display device or be removed during the manufacturing process. For example, the sacrificial layer 618a shown in Figures 33 and 34 is a portion of the sacrificial layer provided on the light-emitting layer.
此外，藉由採用使用範圍遮罩的沉積製程及使用光阻遮罩的加工製程，可以以較簡單的製程製造發光元件。Furthermore, by adopting a deposition process using a range mask and a processing process using a photoresist mask, a light-emitting element can be manufactured using a simpler process.
圖33所示的顯示裝置600A是本發明的一個實施方式的顯示裝置（半導體裝置）的剖面示意圖。在顯示裝置600A中，基板410上設置有像素電路、驅動電路等。在圖33的顯示裝置600A中，除了元件層620、元件層630及元件層660以外，還示出佈線層670。佈線層670是設置有佈線的層。Display device 600A shown in Figure 33 is a schematic cross-sectional view of a display device (semiconductor device) according to one embodiment of the present invention. In display device 600A, pixel circuits, driver circuits, and the like are provided on substrate 410. Display device 600A in Figure 33 also includes a wiring layer 670 in addition to element layer 620, element layer 630, and element layer 660. Wiring layer 670 is a layer where wiring is provided.
在元件層630中，較佳為設置有顯示裝置的像素電路。在元件層620中，較佳為設置有顯示裝置的驅動電路（閘極驅動器和源極驅動器中的一者或兩者）。此外，在元件層620中，也可以設置有運算電路、記憶體電路等各種電路中的一種以上。Pixel circuits of a display device are preferably provided in the device layer 630. Driver circuits (one or both of a gate driver and a source driver) of the display device are preferably provided in the device layer 620. Furthermore, one or more circuits of various types, such as arithmetic circuits and memory circuits, may also be provided in the device layer 620.
作為一個例子，元件層620包括基板410，基板410上形成有電晶體400d。此外，電晶體400d的上方設置有佈線層670，佈線層670中設置有使電晶體400d與設置在元件層630中的導電層或電晶體等（圖33中的導電層514）連接的佈線。此外，佈線層670的上方設置有元件層630及元件層660，元件層630例如包括電晶體MTCK等。元件層660包括發光元件650（圖33中的發光元件650R、發光元件650G及發光元件650B）等。As an example, element layer 620 includes substrate 410, on which transistor 400d is formed. Furthermore, wiring layer 670 is provided above transistor 400d. Wiring layer 670 includes wiring that connects transistor 400d to a conductive layer or transistors (e.g., conductive layer 514 in FIG33 ) provided in element layer 630. Furthermore, element layer 630 and element layer 660 are provided above wiring layer 670. Element layer 630 includes, for example, transistor MTCK. Element layer 660 includes light-emitting elements 650 (e.g., light-emitting elements 650R, 650G, and 650B in FIG33 ).
電晶體400d是元件層620所包括的電晶體的一個例子。此外，電晶體MTCK是元件層630所包括的電晶體的一個例子。此外，發光元件（發光元件650R、發光元件650G及發光元件650B）是元件層660所包括的發光元件的一個例子。Transistor 400 d is an example of a transistor included in element layer 620 . Furthermore, transistor MTCK is an example of a transistor included in element layer 630 . Furthermore, the light-emitting elements (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B) are an example of light-emitting elements included in element layer 660 .
作為基板410，例如可以使用半導體基板（例如，以矽或鍺為材料的單晶基板）。此外，作為基板410，除了半導體基板以外，例如還可以使用SOI基板、玻璃基板、石英基板、塑膠基板、藍寶石玻璃基板、金屬基板、不鏽鋼基板、包含不鏽鋼箔的基板、鎢基板、包含鎢箔的基板、撓性基板、貼合薄膜、包含纖維狀材料的紙或基材薄膜。另外，在本實施方式中，說明基板410是包含矽作為材料的半導體基板的情況。因此，元件層620中的電晶體可以為Si電晶體。For example, a semiconductor substrate (e.g., a single crystal substrate made of silicon or germanium) can be used as substrate 410. Furthermore, in addition to semiconductor substrates, substrate 410 may also include, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate made of stainless steel foil, a tungsten substrate, a substrate made of tungsten foil, a flexible substrate, a laminate film, or paper or base film made of a fibrous material. Furthermore, in this embodiment, the case where substrate 410 is a semiconductor substrate made of silicon is described. Therefore, the transistors in element layer 620 may be Si transistors.
電晶體400d包括元件分離層412、導電層416、絕緣層415、絕緣層417、由基板410的一部分構成的半導體區域413、用作源極區域或汲極區域的低電阻區域414a以及低電阻區域414b。因此，電晶體400d為Si電晶體。雖然圖33示出電晶體400d的源極和汲極中的一個藉由導電層428、導電層430及導電層456連接於設置在元件層630中的導電層514的結構，但是本發明的一個實施方式的顯示裝置的連接結構不侷限於此。Transistor 400d includes an element isolation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 formed from a portion of substrate 410, a low-resistance region 414a serving as a source or drain region, and a low-resistance region 414b. Therefore, transistor 400d is a Si transistor. Although FIG33 illustrates a structure in which one of the source and drain of transistor 400d is connected to conductive layer 514 disposed in element layer 630 via conductive layer 428, conductive layer 430, and conductive layer 456, the connection structure of the display device according to one embodiment of the present invention is not limited to this.
電晶體400d例如藉由採用半導體區域413的頂面及通道寬度方向的側面隔著用作閘極絕緣層的絕緣層415被導電層416覆蓋的結構而可以實現Fin型結構。藉由形成Fin型電晶體400d，可以增加實效上的通道寬度，所以可以提高電晶體400d的通態特性。此外，由於可以增強閘極電極的電場的作用，所以可以提高電晶體400d的關態特性。此外，電晶體400d也可以是平面型電晶體而不是Fin型電晶體。Transistor 400d can achieve a fin-type structure, for example, by employing a structure in which the top surface of semiconductor region 413 and the side surfaces in the channel width direction are covered by conductive layer 416 via insulating layer 415, which serves as a gate insulation layer. Forming fin-type transistor 400d increases the effective channel width, thereby improving the on-state characteristics of transistor 400d. Furthermore, since the electric field effect of the gate electrode can be enhanced, the off-state characteristics of transistor 400d can be improved. Furthermore, transistor 400d can also be a planar transistor rather than a fin-type transistor.
此外，電晶體400d既可為p通道型電晶體又可為n通道型電晶體。此外，也可以設置多個電晶體400d，並其中使用p通道型電晶體和n通道型電晶體的兩者。Furthermore, the transistor 400d may be either a p-channel transistor or an n-channel transistor. Furthermore, a plurality of transistors 400d may be provided, and both p-channel transistors and n-channel transistors may be used.
半導體區域413的通道形成區域、其附近的區域、用作源極區域或汲極區域的低電阻區域414a及低電阻區域414b較佳為包含矽類半導體，明確而言較佳為包含單晶矽。或者，上述各區域例如也可以使用鍺、矽鍺、砷化鎵、砷化鋁鎵或氮化鎵形成。可以使用對晶格施加應力以改變晶面間距來控制有效質量的矽。此外，電晶體400d例如也可以為使用砷化鎵及砷化鋁鎵的HEMT（High Electron Mobility Transistor：高電子移動率電晶體）。The channel-forming region of semiconductor region 413, the region adjacent thereto, and low-resistance regions 414a and 414b, serving as source and drain regions, preferably comprise a silicon-based semiconductor, specifically, preferably single-crystalline silicon. Alternatively, each of these regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Silicon, in which the effective mass is controlled by applying stress to the crystal lattice to change the interplanar spacing, may also be used. Furthermore, transistor 400d may be a HEMT (High Electron Mobility Transistor) using, for example, gallium arsenide or aluminum gallium arsenide.
作為用作閘極電極的導電層416，可以使用包含砷或磷等賦予n型導電性的元素或者硼或鋁等賦予p型導電性的元素的矽等半導體材料。或者，作為導電層416，例如可以使用金屬材料、合金材料或金屬氧化物材料等導電材料。Conductive layer 416, which serves as a gate electrode, can be made of a semiconductor material such as silicon containing an element imparting n-type conductivity, such as arsenic or phosphorus, or an element imparting p-type conductivity, such as boron or aluminum. Alternatively, conductive material such as a metal material, an alloy material, or a metal oxide material can be used as conductive layer 416.
此外，由於導電層的材料決定功函數，所以藉由選擇該導電層的材料，可以調整電晶體的臨界電壓。明確而言，作為導電層較佳為使用氮化鈦和氮化鉭中的一者或兩者的材料。為了兼具導電性和嵌入性，作為導電層較佳為使用鎢和鋁中的一者或兩者的金屬材料的疊層，尤其在耐熱性方面上較佳為使用鎢。Furthermore, since the material of the conductive layer determines the work function, the critical voltage of the transistor can be adjusted by selecting the material for the conductive layer. Specifically, the conductive layer is preferably made of one or both of titanium nitride and tantalum nitride. To achieve both conductivity and embedding properties, a stack of one or both of tungsten and aluminum is preferred for the conductive layer, with tungsten being particularly preferred for its heat resistance.
元件分離層412是為了使形成在基板410上的多個電晶體彼此分離而設置的。元件分離層例如可以使用LOCOS（Local Oxidation of Silicon：矽局部氧化）法、STI（Shallow Trench Isolation：淺溝槽隔離）法或檯面隔離法等形成。The device isolation layer 412 is provided to isolate the plurality of transistors formed on the substrate 410. The device isolation layer can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or a surface isolation method.
圖33所示的電晶體400d上從基板410一側依次層疊設置有絕緣層420及絕緣層422。In the transistor 400d shown in FIG33 , an insulating layer 420 and an insulating layer 422 are stacked in sequence from one side of the substrate 410.
作為絕緣層420及絕緣層422，例如可以使用選自氧化矽、氧氮化矽、氮氧化矽、氮化矽、氧化鋁、氧氮化鋁、氮氧化鋁及氮化鋁中的一個以上。As the insulating layer 420 and the insulating layer 422, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.
絕緣層422也可以被用作使因被絕緣層420及絕緣層422覆蓋的電晶體400d等而產生的步階平坦化的平坦化膜。例如，為了提高平坦性，絕緣層422的頂面也可以藉由利用CMP法等的平坦化處理被平坦化。The insulating layer 422 may also be used as a planarization film to planarize steps generated by the insulating layer 420 and the transistor 400d covered by the insulating layer 422. For example, to improve planarity, the top surface of the insulating layer 422 may be planarized by a planarization process such as CMP.
在絕緣層420及絕緣層422中嵌入與設置在絕緣層422的上方的電晶體MTCK等連接的導電層428。此外，導電層428具有插頭或佈線的功能。A conductive layer 428 connected to the transistor MTCK and the like provided above the insulating layer 422 is embedded in the insulating layer 420 and the insulating layer 422. The conductive layer 428 also functions as a connector or a wiring.
在顯示裝置600A中，電晶體400d上設置有佈線層670。佈線層670例如包括絕緣層424、絕緣層426、導電層430、絕緣層450、絕緣層452、絕緣層454及導電層456。In the display device 600A, a wiring layer 670 is provided on the transistor 400d. The wiring layer 670 includes, for example, the insulating layer 424, the insulating layer 426, the conductive layer 430, the insulating layer 450, the insulating layer 452, the insulating layer 454, and the conductive layer 456.
絕緣層422及導電層428上依次層疊設置有絕緣層424及絕緣層426。此外，在與導電層428重疊的區域中，絕緣層424及絕緣層426中形成有開口部。此外，該開口部嵌入有導電層430。Insulating layer 424 and insulating layer 426 are sequentially stacked on insulating layer 422 and conductive layer 428. Furthermore, openings are formed in insulating layer 424 and insulating layer 426 in the regions overlapping conductive layer 428. Furthermore, conductive layer 430 is embedded in these openings.
此外，絕緣層426及導電層430上依次層疊設置有絕緣層450、絕緣層452及絕緣層454。此外，在與導電層430重疊的區域中，絕緣層450、絕緣層452及絕緣層454中形成有開口部。此外，該開口部嵌入有導電層456。Furthermore, insulating layer 450, insulating layer 452, and insulating layer 454 are sequentially stacked on insulating layer 426 and conductive layer 430. Furthermore, openings are formed in insulating layer 450, insulating layer 452, and insulating layer 454 in the regions overlapping conductive layer 430. Furthermore, conductive layer 456 is embedded in these openings.
導電層430及導電層456例如具有與電晶體400d連接的插頭或佈線的功能。The conductive layer 430 and the conductive layer 456 function as, for example, a plug or wiring connected to the transistor 400d.
另外，與後述絕緣層592同樣，絕緣層424及絕緣層450例如較佳為使用具有選自氫、氧和水中的一個以上的阻擋性的絕緣層。此外，與後述絕緣層594同樣，絕緣層426、絕緣層452及絕緣層454較佳為使用相對介電常數較低的絕緣層以減少產生在佈線間的寄生電容。此外，絕緣層426、絕緣層452及絕緣層454被用作層間絕緣膜及平坦化膜。In addition, similar to insulating layer 592 described later, insulating layers 424 and 450 are preferably made of insulating layers having a barrier property to one or more of hydrogen, oxygen, and water. Furthermore, similar to insulating layer 594 described later, insulating layers 426, 452, and 454 are preferably made of insulating layers with a relatively low dielectric constant to reduce parasitic capacitance generated between wirings. Furthermore, insulating layers 426, 452, and 454 function as interlayer insulating films and planarizing films.
此外，導電層456較佳為包括具有選自氫、氧和水中的一個以上的阻擋性的導電層。Furthermore, the conductive layer 456 preferably includes a conductive layer having a barrier property of at least one selected from hydrogen, oxygen, and water.
注意，作為具有氫阻擋性的導電層，例如較佳為使用氮化鉭。此外，藉由層疊氮化鉭和導電性高的鎢，可以在保持作為佈線的導電性的同時抑制氫從電晶體400d擴散。此時，具有氫阻擋性的氮化鉭層較佳為與具有氫阻擋性的絕緣層450接觸。Note that tantalum nitride, for example, is preferably used as the conductive layer having hydrogen barrier properties. Furthermore, by stacking tungsten with tungsten, which has high conductivity, hydrogen diffusion from transistor 400d can be suppressed while maintaining the conductivity of the wiring. In this case, the tantalum nitride layer having hydrogen barrier properties is preferably in contact with insulating layer 450 having hydrogen barrier properties.
此外，絕緣層454及導電層456的上方設置有絕緣層513。此外，絕緣層513上設置有絕緣層IS1。此外，絕緣層IS1及絕緣層513中嵌入有用作插頭或佈線的導電層。由此，可以使電晶體400d與設置在元件層630中的導電層514連接。或者，也可以使電晶體MTCK的源極和汲極中的一個與電晶體400d的源極和汲極中的一個連接。Furthermore, insulating layer 513 is provided above insulating layer 454 and conductive layer 456. Furthermore, insulating layer IS1 is provided on insulating layer 513. Furthermore, a conductive layer serving as a plug or wiring is embedded in insulating layer IS1 and insulating layer 513. This allows transistor 400d to be connected to conductive layer 514 provided in element layer 630. Alternatively, one of the source and drain of transistor MTCK can be connected to one of the source and drain of transistor 400d.
絕緣層IS1上設置有電晶體MTCK。此外，電晶體MTCK上依次層疊有絕緣層IS4、絕緣層574及絕緣層581。此外，絕緣層IS3、絕緣層IS4、絕緣層574及絕緣層581中嵌入有用作插頭或佈線的導電層MPG。導電層MPG較佳為藉由設置在絕緣層250及氧化物半導體層230中的開口部與導電層240接觸。當導電層MPG與導電層240接觸時，可以降低接觸電阻，所以是較佳的。或者，也可以使導電層MPG與氧化物半導體層230接觸來使導電層MPG藉由氧化物半導體層230連接於導電層240。A transistor MTCK is disposed on insulating layer IS1. Furthermore, insulating layers IS4, 574, and 581 are stacked on top of transistor MTCK in this order. Furthermore, a conductive layer MPG, used as a plug or wiring, is embedded within insulating layers IS3, IS4, 574, and 581. Conductive layer MPG preferably contacts conductive layer 240 through openings provided in insulating layer 250 and oxide semiconductor layer 230. When the conductive layer MPG contacts the conductive layer 240, the contact resistance can be reduced, which is preferable. Alternatively, the conductive layer MPG can be contacted with the oxide semiconductor layer 230 to connect the conductive layer MPG to the conductive layer 240 via the oxide semiconductor layer 230.
絕緣層574較佳為具有抑制水及氫（例如，氫原子和氫分子中的一者或兩者）等雜質的擴散的功能。換言之，絕緣層574較佳為被用作抑制該雜質混入電晶體MTCK中的阻擋絕緣膜。此外，絕緣層574較佳為具有抑制氧（例如，氧原子和氧分子中的一者或兩者）的擴散的功能。例如，絕緣層574的氧透過性較佳為比絕緣層IS2、絕緣層IS3及絕緣層IS4低。The insulating layer 574 preferably functions to inhibit the diffusion of impurities such as water and hydrogen (e.g., one or both of hydrogen atoms and molecules). In other words, the insulating layer 574 preferably functions as a barrier insulating film to prevent these impurities from infiltrating into the transistor MTCK. Furthermore, the insulating layer 574 preferably functions to inhibit the diffusion of oxygen (e.g., one or both of oxygen atoms and molecules). For example, the oxygen permeability of the insulating layer 574 is preferably lower than that of the insulating layers IS2, IS3, and IS4.
因此，絕緣層574較佳為被用作抑制水及氫等雜質的擴散的阻擋絕緣膜。因此，絕緣層574較佳為使用具有抑制氫原子、氫分子、水分子、氮原子、氮分子、氧化氮分子（例如，N2O、NO及NO2）及銅原子等雜質的擴散的功能（不容易使上述雜質透過）的絕緣材料。或者，較佳為使用具有抑制氧（例如，氧原子和氧分子中的一者或兩者）的擴散的功能（不容易使上述氧透過）的絕緣材料。Therefore, insulating layer 574 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen. Therefore, insulating layer 574 is preferably made of an insulating material that inhibits the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g.,N₂O , NO, andNO₂ ), and copper atoms (restricting the passage of these impurities). Alternatively, an insulating material that inhibits the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (restricting the passage of oxygen) is preferably used.
作為具有抑制水及氫等雜質及氧的透過的功能的絕緣層，可以使用實施方式1所示的可用於具有抑制雜質及氧的透過的功能的絕緣層的材料。As the insulating layer having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, the materials usable for the insulating layer having the function of inhibiting the permeation of impurities and oxygen described in Embodiment 1 can be used.
尤其較佳的是，作為絕緣層574使用氧化鋁或氮化矽。由此，可以抑制水及氫等雜質從絕緣層574的上方擴散到電晶體MTCK。或者，可以抑制包含在絕緣層IS3等中的氧擴散到絕緣層574的上方。It is particularly preferable to use aluminum oxide or silicon nitride as the insulating layer 574. This can suppress the diffusion of impurities such as water and hydrogen from above the insulating layer 574 into the transistor MTCK. Alternatively, it can suppress the diffusion of oxygen contained in the insulating layer IS3 and the like from above the insulating layer 574.
絕緣層581較佳為被用作層間膜且其介電常數比絕緣層574低。藉由將介電常數低的材料用於層間膜，可以減少產生在佈線之間的寄生電容。例如，絕緣層581的相對介電常數較佳為低於4，更佳為低於3。例如，絕緣層581的相對介電常數較佳為絕緣層574的相對介電常數的0.7倍以下，更佳為0.6倍以下。藉由作為絕緣層581使用介電常數低的材料，可以減少產生在佈線之間的寄生電容。Insulating layer 581 is preferably used as an interlayer film and has a lower dielectric constant than insulating layer 574. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between traces can be reduced. For example, the relative dielectric constant of insulating layer 581 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of insulating layer 581 is preferably no greater than 0.7 times the relative dielectric constant of insulating layer 574, and more preferably no greater than 0.6 times. By using a material with a low dielectric constant for insulating layer 581, parasitic capacitance generated between traces can be reduced.
此外，絕緣層581中的水、氫等雜質的濃度較佳為得到降低。此時，作為絕緣層581，例如可以使用氧化矽、氧氮化矽、氮氧化矽或氮化矽。此外，作為絕緣層581，例如可以使用添加有氟的氧化矽、添加有碳的氧化矽、添加有碳及氮的氧化矽或者具有多孔的氧化矽。尤其是，氧化矽及氧氮化矽具有熱穩定性，所以是較佳的。尤其是，因為氧化矽、氧氮化矽、具有多孔的氧化矽等材料容易形成包含過量氧的區域，所以是較佳的。此外，作為絕緣層581，可以使用樹脂。此外，作為可用於絕緣層581的材料，也可以適當地組合上述材料。Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 581 is preferably reduced. In this case, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used as the insulating layer 581. Furthermore, for example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide with a porous structure can be used as the insulating layer 581. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with a porous structure are preferred because they easily form regions containing excess oxygen. Furthermore, a resin can be used as the insulating layer 581. Furthermore, as a material that can be used for the insulating layer 581, the above-mentioned materials can be appropriately combined.
絕緣層574及絕緣層581上依次層疊有絕緣層592及絕緣層594。The insulating layer 592 and the insulating layer 594 are sequentially stacked on the insulating layer 574 and the insulating layer 581.
此外，絕緣層592較佳為使用防止水及氫等雜質從基板410、電晶體MTCK向絕緣層592的上方的區域（例如，設置有發光元件650R、發光元件650G及發光元件650B等的區域）擴散的阻擋絕緣層。因此，絕緣層592較佳為使用具有抑制氫原子、氫分子及水分子等雜質的擴散的功能（不容易使上述雜質透過）的絕緣材料。此外，根據情況，絕緣層592較佳為使用具有抑制氮原子、氮分子、氧化氮分子（例如，N2O、NO及NO2）及銅原子等雜質的擴散的功能（不容易使上述雜質透過）的絕緣材料。或者，較佳為具有抑制氧（例如，氧原子和氧分子中的一者或兩者）的擴散的功能。Furthermore, the insulating layer 592 is preferably formed of a barrier insulating layer that prevents impurities such as water and hydrogen from diffusing from the substrate 410 and the transistor MTCK toward the region above the insulating layer 592 (e.g., the region where the light-emitting elements 650R, 650G, and 650B are located). Therefore, the insulating layer 592 is preferably formed of an insulating material that inhibits the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (preventing these impurities from easily penetrating). Furthermore, depending on circumstances, insulating layer 592 is preferably made of an insulating material that inhibits the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g.,N₂O , NO, andNO₂ ), and copper atoms (preventing these impurities from permeating). Alternatively, it is preferably made of an insulating material that inhibits the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules).
作為具有氫阻擋性的膜的一個例子，例如可以使用藉由CVD法形成的氮化矽。As an example of a film having hydrogen barrier properties, silicon nitride formed by a CVD method can be used.
與絕緣層581同樣，絕緣層594較佳為介電常數低的層間膜。因此，絕緣層594可以使用可用於絕緣層581的材料。Like the insulating layer 581, the insulating layer 594 is preferably an interlayer film having a low dielectric constant. Therefore, the insulating layer 594 can use the same material as the insulating layer 581.
此外，絕緣層594的介電常數較佳為比絕緣層592低。例如，絕緣層594的相對介電常數較佳為低於4，更佳為低於3。此外，例如，絕緣層594的相對介電常數較佳為絕緣層592的相對介電常數的0.7倍以下，更佳為0.6倍以下。藉由作為絕緣層594使用介電常數低的材料，可以減少產生在佈線之間的寄生電容。Furthermore, the dielectric constant of insulating layer 594 is preferably lower than that of insulating layer 592. For example, the relative dielectric constant of insulating layer 594 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of insulating layer 594 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of insulating layer 592. By using a material with a low dielectric constant for insulating layer 594, parasitic capacitance generated between wirings can be reduced.
此外，絕緣層IS3、絕緣層IS4、絕緣層574及絕緣層581中嵌入有用作插頭或佈線的導電層MPG，絕緣層592及絕緣層594中嵌入有用作插頭或佈線的導電層596。尤其是，導電層MPG及導電層596與設置在絕緣層594上方的發光元件等連接。注意，有時使用同一符號表示用作插頭或佈線的多個導電層。此外，在本說明書等中，佈線和與佈線連接的插頭也可以是一個組件。就是說，導電層的一部分有時被用作佈線，並且導電層的一部分有時被用作插頭。Furthermore, insulating layers IS3, IS4, 574, and 581 have conductive layers MPG embedded within them, serving as plugs or wiring. Insulating layers 592 and 594 have conductive layers 596 embedded within them, serving as plugs or wiring. In particular, conductive layers MPG and 596 are connected to light-emitting elements and the like disposed above insulating layer 594. Note that the same symbol may sometimes be used to represent multiple conductive layers serving as plugs or wiring. Furthermore, in this specification and other text, wiring and the plug connected to the wiring may be considered a single component. That is, part of the conductive layer is sometimes used as wiring, and part of the conductive layer is sometimes used as a plug.
作為各插頭及佈線（例如，導電層MPG、導電層428、導電層430、導電層456、導電層514及導電層596）的材料，可以使用選自金屬材料、合金材料、金屬氮化物材料和金屬氧化物材料中的一個以上的導電材料的單層或疊層。較佳為使用兼具耐熱性和導電性的鎢或鉬等高熔點材料，較佳為使用鎢。此外，較佳為使用鋁或銅等低電阻導電材料形成。藉由使用低電阻導電材料可以降低佈線電阻。The materials for each plug and wiring (e.g., conductive layer MPG, conductive layer 428, conductive layer 430, conductive layer 456, conductive layer 514, and conductive layer 596) can be a single layer or a stack of one or more conductive materials selected from metals, alloys, metal nitrides, and metal oxides. High-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and electrical conductivity, are preferred, with tungsten being particularly preferred. Furthermore, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials can reduce wiring resistance.
絕緣層594及導電層596上依次形成有絕緣層598及絕緣層599。An insulating layer 598 and an insulating layer 599 are sequentially formed on the insulating layer 594 and the conductive layer 596 .
與絕緣層592同樣，作為一個例子，絕緣層598較佳為使用具有氫、氧和水中的一個以上的阻擋性的絕緣層。此外，與絕緣層594同樣，絕緣層599較佳為使用相對介電常數較低的絕緣層以減少產生在佈線間的寄生電容。此外，絕緣層599被用作層間絕緣膜及平坦化膜。As with insulating layer 592, insulating layer 598 is preferably formed of an insulating layer having barrier properties to one or more of hydrogen, oxygen, and water, for example. Furthermore, as with insulating layer 594, insulating layer 599 is preferably formed of an insulating layer having a relatively low dielectric constant to reduce parasitic capacitance generated between wirings. Furthermore, insulating layer 599 functions as an interlayer insulating film and a planarizing film.
絕緣層599上形成有發光元件650及連接部640。The light emitting element 650 and the connecting portion 640 are formed on the insulating layer 599 .
連接部640有時被稱為陰極接觸部，與發光元件650R、發光元件650G及發光元件650B的每一個的陰極電極連接。在圖33所示的連接部640中，使用與導電層611a至導電層611c相同的製程及材料形成的導電層與後述共用電極615連接。雖然圖33示出該導電層藉由後述共用層614連接於共用電極615的例子，但是該導電層也可以與共用電極615直接接觸。Connecting portion 640, sometimes referred to as a cathode contact portion, is connected to the cathode electrodes of each of light-emitting elements 650R, 650G, and 650B. In connecting portion 640 shown in FIG33 , a conductive layer formed using the same process and materials as conductive layers 611a through 611c is connected to a common electrode 615, described later. Although FIG33 illustrates an example where this conductive layer is connected to common electrode 615 via common layer 614, described later, this conductive layer may also be in direct contact with common electrode 615.
另外，連接部640既可以俯視時以圍繞顯示部的四個邊的方式設置，又可以設置在顯示部內（例如，相鄰發光元件650間）（未圖示）。In addition, the connecting portion 640 may be disposed around the four sides of the display portion in a plan view, or may be disposed within the display portion (eg, between adjacent light emitting elements 650 ) (not shown).
發光元件650R包括導電層611a作為像素電極。同樣地，發光元件650G包括導電層611b作為像素電極，發光元件650B包括導電層611c作為像素電極。The light-emitting element 650R includes a conductive layer 611a as a pixel electrode. Similarly, the light-emitting element 650G includes a conductive layer 611b as a pixel electrode, and the light-emitting element 650B includes a conductive layer 611c as a pixel electrode.
導電層611a、導電層611b、導電層611c分別藉由嵌入絕緣層599中的導電層（插頭）與嵌入絕緣層594中的導電層596連接。Conductive layer 611a, conductive layer 611b, and conductive layer 611c are connected to conductive layer 596 embedded in insulating layer 594 via conductive layers (plugs) embedded in insulating layer 599, respectively.
發光元件650R包括層613a、層613a上的共用層614以及共用層614上的共用電極615。此外，發光元件650G包括層613b、層613b上的共用層614以及共用層614上的共用電極615。此外，發光元件650B包括層613c、層613c上的共用層614以及共用層614上的共用電極615。Light-emitting element 650R includes layer 613a, a common layer 614 on layer 613a, and a common electrode 615 on common layer 614. Furthermore, light-emitting element 650G includes layer 613b, a common layer 614 on layer 613b, and a common electrode 615 on common layer 614. Furthermore, light-emitting element 650B includes layer 613c, a common layer 614 on layer 613c, and a common electrode 615 on common layer 614.
作為形成發光元件的一對電極（像素電極及共用電極）的材料，可以適當地使用金屬、合金、導電化合物及它們的混合物等。作為該材料，具體地可以舉出鋁、鎂、鈦、鉻、錳、鐵、鈷、鎳、銅、鎵、鋅、銦、錫、鉬、鉭、鎢、鈀、金、鉑、銀、釔及釹等金屬以及適當地組合它們的合金。此外，作為該材料，可以舉出ITO、ITSO、In-Zn氧化物及In-W-Zn氧化物等。此外，作為該材料，可以舉出鋁、鎳和鑭的合金（Al-Ni-La）等含鋁合金（鋁合金）以及銀和鎂的合金及銀、鈀和銅的合金（Ag-Pd-Cu，也記作APC）等含銀合金。此外，作為該材料，可以舉出以上沒有列舉的屬於元素週期表中第1族或第2族的元素（例如，鋰、銫、鈣及鍶）、銪及鐿等稀土金屬、適當地組合它們的合金以及石墨烯等。As materials forming the pair of electrodes (pixel electrode and common electrode) of the light-emitting element, metals, alloys, conductive compounds, and mixtures thereof can be appropriately used. Specific examples of such materials include aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys of suitable combinations thereof. Other examples include ITO, ITSO, In-Zn oxide, and In-W-Zn oxide. Examples of such materials include aluminum-containing alloys (aluminum alloys) such as alloys of aluminum, nickel, and lumber (Al-Ni-La), and silver-containing alloys such as alloys of silver and magnesium and alloys of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Examples of such materials include elements not listed above that belong to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as ammonium and ferromagnetic metals, alloys of these elements in appropriate combinations, and graphene.
顯示裝置600A採用SBS結構。SBS結構由於可以在各發光元件中使材料及結構最佳化，材料及結構的選擇彈性得到提高，由此可以容易實現亮度及可靠性的提高。Display device 600A employs an SBS structure. The SBS structure allows for optimization of materials and structures in each light-emitting element, increasing flexibility in material and structure selection, thereby easily achieving improved brightness and reliability.
此外，顯示裝置600A採用頂部發射型。在頂部發射型中，可以以與發光元件的發光區域重疊的方式配置電晶體等，所以與底部發射型相比可以進一步提高像素的開口率。Furthermore, display device 600A employs a top-emission type. In a top-emission type, transistors and the like can be arranged so as to overlap with the light-emitting region of the light-emitting element, thereby further increasing the pixel aperture ratio compared to a bottom-emission type.
另外，層613a以覆蓋導電層611a的頂面及側面的方式形成。同樣地，層613b以覆蓋導電層611b的頂面及側面的方式形成。此外，同樣地，層613c以覆蓋導電層611c的頂面及側面的方式形成。因此，可以將設置有導電層611a、導電層611b及導電層611c的整個區域用作發光元件650R、發光元件650G及發光元件650B的發光區域，由此可以提高像素的開口率。Furthermore, layer 613a is formed to cover the top and side surfaces of conductive layer 611a. Similarly, layer 613b is formed to cover the top and side surfaces of conductive layer 611b. Similarly, layer 613c is formed to cover the top and side surfaces of conductive layer 611c. Therefore, the entire region where conductive layers 611a, 611b, and 611c are provided can be used as the light-emitting region for light-emitting elements 650R, 650G, and 650B, thereby increasing the pixel aperture ratio.
在發光元件650R中，可以將層613a及共用層614統稱為EL層。此外，同樣地，在發光元件650G中，可以將層613b及共用層614統稱為EL層。此外，同樣地，在發光元件650B中，可以將層613c及共用層614統稱為EL層。In the light-emitting element 650R, the layer 613a and the common layer 614 can be collectively referred to as the EL layer. Similarly, in the light-emitting element 650G, the layer 613b and the common layer 614 can be collectively referred to as the EL layer. Similarly, in the light-emitting element 650B, the layer 613c and the common layer 614 can be collectively referred to as the EL layer.
EL層至少包括發光層。發光層包含一種或多種發光物質。作為發光物質，適當地使用呈現藍色、紫色、藍紫色、綠色、黃綠色、黃色、橙色或紅色等發光顏色的光的物質。此外，作為發光物質，也可以使用發射近紅外光的物質。The EL layer includes at least a luminescent layer. The luminescent layer contains one or more luminescent substances. Suitable luminescent substances include those that emit light in colors such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red. Furthermore, substances that emit near-infrared light may also be used.
作為發光元件含有的發光物質，例如可以舉出發射螢光的物質（螢光材料）、發射磷光的物質（磷光材料）、呈現熱活化延遲螢光的物質（熱活化延遲螢光（Thermally activated delayed fluorescence：TADF）材料）及無機化合物（量子點材料等）。Examples of the luminescent substance contained in a luminescent element include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (TADF materials), and inorganic compounds (quantum dot materials, etc.).
發光層除了發光物質（客體材料）以外還可以包含一種或多種有機化合物（主體材料、輔助材料等）。作為一種或多種有機化合物，可以使用電洞傳輸性高的物質（電洞傳輸材料）和電子傳輸性高的物質（電子傳輸材料）中的一或兩者。此外，作為一種或多種有機化合物，也可以使用雙極性物質（電子傳輸性及電洞傳輸性高的物質）或TADF材料。The luminescent layer may contain one or more organic compounds (host material, auxiliary material, etc.) in addition to the luminescent substance (guest material). The one or more organic compounds may be either or both substances with high hole transport properties (hole transport materials) or substances with high electron transport properties (electron transport materials). Furthermore, bipolar substances (substances with high electron and hole transport properties) or TADF materials may also be used as the one or more organic compounds.
EL層除了發光層之外還可以包括包含電洞注入性高的物質的層（電洞注入層）、包含電洞傳輸材料的層（電洞傳輸層）、包含電子阻擋性高的物質的層（電子阻擋層）、包含電子注入性高的物質的層（電子注入層）、包含電子傳輸材料的層（電子傳輸層）和包含電洞阻擋性高的物質的層（電洞阻擋層）中的一個或多個。除此之外，EL層也可以包含雙極性物質和TADF材料中的一者或兩者。In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer). Furthermore, the EL layer may include one or both of a bipolar substance and a TADF material.
發光元件可以使用低分子化合物或高分子化合物，還可以包含無機化合物。構成發光元件的層可以藉由蒸鍍法（包括真空蒸鍍法）、轉印法、印刷法、噴墨法、塗佈法等方法形成。Light-emitting elements can use low-molecular-weight or high-molecular-weight compounds, and may also contain inorganic compounds. The layers that make up the light-emitting element can be formed by methods such as evaporation (including vacuum evaporation), transfer, printing, inkjet, and coating.
發光元件可以採用單結構（只有一個發光單元的結構），也可以採用串聯結構（包括多個發光單元的結構）。發光單元至少包括一個發光層。串聯結構具有多個發光單元藉由電荷產生層串聯連接的結構。電荷產生層具有在對一對的電極間施加電壓時向兩個發光單元中的一方注入電子且向另一方注入電洞的功能。藉由採用串聯結構，可以實現能夠以高亮度發光的發光元件。此外，串聯結構由於與單結構相比可以降低為了得到相同亮度所需的電流，所以可以提高可靠性。此外，也可以將串聯結構稱為疊層結構。A light-emitting element can have either a single structure (a structure with only one light-emitting unit) or a series structure (a structure comprising multiple light-emitting units). A light-emitting unit includes at least one light-emitting layer. A series structure has multiple light-emitting units connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By adopting a series structure, a light-emitting element capable of emitting light with high brightness can be realized. In addition, the series structure can improve reliability because it can reduce the current required to achieve the same brightness compared to a single structure. The series structure can also be referred to as a stacked structure.
此外，當發光元件具有微腔結構時，可以進一步提高色純度。In addition, when the light-emitting element has a microcavity structure, the color purity can be further improved.
層613a、層613b及層613c藉由光微影法被加工為島狀。因此，層613a、層613b及層613c在各端部處頂面與側面所形成的角度近於90度。另一方面，例如，使用FMM（高精細金屬遮罩）形成的有機膜的厚度有越接近端部越減薄的傾向，例如其頂面在離端部有1μm以上且10μm以下的範圍內形成為坡狀，因此難以區別頂面與側面。Layers 613a, 613b, and 613c were processed into island shapes using photolithography. Consequently, the angles formed between the top and side surfaces of layers 613a, 613b, and 613c at each end are close to 90 degrees. On the other hand, organic films formed using, for example, FMM (fine metal mask) tend to become thinner toward the ends. For example, the top surface is sloped within a range of 1 μm to 10 μm from the end, making it difficult to distinguish between the top and side surfaces.
在層613a、層613b及層613c中，頂面與側面的區別明確。因此，在相鄰的層613a與層613b中，層613a的一個側面與層613b的一個側面彼此對置。層613a、層613b及層613c中的任何組合都與該情況同樣。In layers 613a, 613b, and 613c, the top surface and the side surface are clearly distinguished. Therefore, in adjacent layers 613a and 613b, one side surface of layer 613a and one side surface of layer 613b face each other. This is also true for any combination of layers 613a, 613b, and 613c.
層613a、層613b及層613c至少包括發光層。例如，較佳為具有層613a、層613b及層613c分別包括發射紅色光的發光層、發射綠色光的發光層及發射藍色光的發光層的結構。此外，各發光層除了上述顏色以外可以採用青色、洋紅色、黃色或白色。Layers 613a, 613b, and 613c include at least one luminescent layer. For example, preferably, layer 613a, layer 613b, and layer 613c include a red-emitting layer, a green-emitting layer, and a blue-emitting layer, respectively. Furthermore, each luminescent layer may be cyan, magenta, yellow, or white in addition to the aforementioned colors.
層613a、層613b及層613c較佳為包括發光層以及發光層上的載子傳輸層（電子傳輸層或電洞傳輸層）。因為層613a、層613b及層613c的表面有時在顯示裝置的製程中露出，所以藉由在發光層上設置載子傳輸層，可以抑制發光層露出於最表面而降低發光層受到的損傷。由此，可以提高發光元件的可靠性。Layers 613a, 613b, and 613c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) above the light-emitting layer. Because the surfaces of layers 613a, 613b, and 613c are sometimes exposed during the display device manufacturing process, providing a carrier transport layer above the light-emitting layer prevents the light-emitting layer from being exposed to the outermost surface, thereby reducing damage to the light-emitting layer. This improves the reliability of the light-emitting device.
共用層614例如包括電子注入層或電洞注入層。或者，共用層614既可以具有電子傳輸層與電子注入層的疊層，又可以具有電洞傳輸層與電洞注入層的疊層。發光元件650R、發光元件650G、發光元件650B共同包括共用層614。此外，也可以不設置共用層614，發光元件所包括的EL層整體也可以像層613a、層613b及層613c那樣設置為島狀。Common layer 614 may include, for example, an electron injection layer or a hole injection layer. Alternatively, common layer 614 may comprise a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. Light-emitting elements 650R, 650G, and 650B all include common layer 614. Alternatively, common layer 614 may be omitted, and the entire EL layer included in the light-emitting elements may be arranged in an island shape, similar to layers 613a, 613b, and 613c.
此外，發光元件650R、發光元件650G及發光元件650B共同包括共用電極615。此外，如圖33所示，多個發光元件共同包括的共用電極615與連接部640中的導電層連接。Furthermore, the light emitting element 650R, the light emitting element 650G, and the light emitting element 650B all include a common electrode 615. Furthermore, as shown in FIG33 , the common electrode 615 included in the plurality of light emitting elements is connected to the conductive layer in the connection portion 640.
絕緣層625較佳為被用作水和氧中的一者或兩者的阻擋絕緣層。此外，絕緣層625較佳為具有抑制水和氧中的一者或兩者的擴散的功能。此外，絕緣層625較佳為具有俘獲或固定水和氧中的一者或兩者（也稱為吸雜）的功能。在絕緣層625具有這些功能中的至少一個時，可以具有抑制可能會從外部擴散到各發光元件的雜質（典型的是，水和氧中的一者或兩者）的進入的結構。藉由採用該結構，可以提供一種可靠性高的發光元件，並且可以提供一種可靠性高的顯示裝置。Insulating layer 625 preferably functions as a barrier insulating layer against one or both of water and oxygen. Furthermore, insulating layer 625 preferably has the function of inhibiting the diffusion of one or both of water and oxygen. Furthermore, insulating layer 625 preferably has the function of capturing or immobilizing one or both of water and oxygen (also known as impurity gettering). When insulating layer 625 has at least one of these functions, it can have a structure that inhibits the ingress of impurities (typically, one or both of water and oxygen) that might diffuse from the outside into each light-emitting element. By adopting this structure, a highly reliable light-emitting element and, therefore, a highly reliable display device can be provided.
作為絕緣層625，可以使用上述氧阻擋絕緣層，較佳為使用氧化鋁或氮化矽。As the insulating layer 625, the above-mentioned oxygen barrier insulating layer can be used, and preferably aluminum oxide or silicon nitride is used.
此外，絕緣層625的雜質濃度較佳為低。由此，可以抑制雜質從絕緣層625混入到EL層而EL層劣化。此外，藉由降低絕緣層625中的雜質濃度，可以提高對水和氧中的一者或兩者的阻擋性。例如，較佳的是，絕緣層625中的氫濃度和碳濃度中的一方充分低，較佳為氫濃度和碳濃度中的兩者較佳為充分低。Furthermore, the impurity concentration in the insulating layer 625 is preferably low. This prevents impurities from entering the EL layer from the insulating layer 625 and degrading the EL layer. Furthermore, by reducing the impurity concentration in the insulating layer 625, the barrier properties against one or both of water and oxygen can be improved. For example, it is preferred that either the hydrogen concentration or the carbon concentration in the insulating layer 625 be sufficiently low, and more preferably, both the hydrogen concentration and the carbon concentration be sufficiently low.
作為絕緣層627，可以適當地使用包含有機材料的絕緣層。作為有機材料，較佳為使用感光樹脂，例如可以使用含有丙烯酸樹脂的感光樹脂組成物。注意，在本說明書等中，丙烯酸樹脂不是僅指聚甲基丙烯酸酯或甲基丙烯酸樹脂，有時也指廣義上的丙烯酸類聚合物整體。An insulating layer composed of an organic material can be suitably used as the insulating layer 627. A photosensitive resin is preferably used as the organic material, and for example, a photosensitive resin composition containing an acrylic resin can be used. Note that in this specification, the term "acrylic resin" does not refer solely to polymethacrylate or methacrylic resin, but may also refer to acrylic polymers in a broad sense.
可用於絕緣層627的有機材料不侷限於上述材料。例如，有時作為絕緣層627可以使用丙烯酸樹脂、聚醯亞胺樹脂、環氧樹脂、聚醯胺樹脂、聚醯亞胺醯胺樹脂、矽酮樹脂、矽氧烷樹脂、苯并環丁烯類樹脂、酚醛樹脂及上述樹脂的先質。此外，作為絕緣層627，有時可以使用聚乙烯醇（PVA）、聚乙烯醇縮丁醛（PVB）、聚乙烯吡咯烷酮、聚乙二醇、聚甘油、普魯蘭、水溶性纖維素或者醇可溶性聚醯胺樹脂等有機材料。此外，作為絕緣層627，有時例如可以使用光阻劑作為感光樹脂。作為感光樹脂，可以舉出正型材料或負型材料。Organic materials that can be used for insulating layer 627 are not limited to those described above. For example, acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, silicone resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins may be used for insulating layer 627. Furthermore, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resins may also be used for insulating layer 627. In addition, a photoresist may be used as a photosensitive resin, for example, as the insulating layer 627. As the photosensitive resin, either a positive-type material or a negative-type material can be used.
作為絕緣層627也可以使用吸收可見光的材料。藉由絕緣層627吸收來自發光元件的發光，可以抑制光從發光元件經過絕緣層627洩漏到相鄰的發光元件（雜散光）。由此，可以提高顯示面板的顯示品質。此外，即使在顯示裝置中不使用偏光板也可以提高顯示品質，所以可以實現顯示裝置的輕量化及薄型化。Insulating layer 627 can also be made of a material that absorbs visible light. By absorbing the light emitted by the light-emitting element, insulating layer 627 can suppress light leakage from the light-emitting element through insulating layer 627 to adjacent light-emitting elements (stray light). This improves the display quality of the display panel. Furthermore, even without using a polarizing plate in the display device, display quality can be improved, thereby achieving a lighter and thinner display device.
作為吸收可見光的材料，可以舉出包括黑色等的顏料的材料、包括染料的材料、包括光吸收性的樹脂材料（例如，聚醯亞胺）以及可用於濾色片的樹脂材料（濾色片材料）。尤其是，在使用層疊或混合兩種顏色或三種以上的顏色的濾色片材料而成的樹脂材料時可以提高遮蔽可見光的效果，所以是較佳的。尤其是，藉由混合三種以上的顏色的濾色片材料，可以實現黑色或近似於黑色的樹脂層。Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). Resin materials that are layered or blended with two or more color filter materials are particularly preferred because they enhance the visible light shielding effect. In particular, blending three or more color filter materials can create a black or nearly black resin layer.
絕緣層627例如可以利用旋塗法、浸漬法、噴塗法、噴墨法、分配器法、網版印刷法、平板印刷法、刮刀法、狹縫式塗佈法、輥塗法、簾式塗佈法、刮刀式塗佈法等濕式沉積方法形成。尤其是，較佳為藉由旋塗法形成將成為絕緣層627的有機絕緣膜。The insulating layer 627 can be formed using a wet deposition method such as spin coating, dipping, spray coating, inkjet coating, dispenser coating, screen printing, lithographic printing, doctor blade coating, slit coating, roll coating, curtain coating, or blade coating. In particular, the organic insulating film to become the insulating layer 627 is preferably formed by spin coating.
絕緣層627在低於EL層的耐熱溫度的溫度下形成。形成絕緣層627時的基板溫度典型地為室溫以上且200℃以下，較佳為180℃以下，更佳為160℃以下，進一步較佳為150℃以下，更進一步較佳為140℃以下。The insulating layer 627 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature during the formation of the insulating layer 627 is typically above room temperature and below 200°C, preferably below 180°C, more preferably below 160°C, further preferably below 150°C, and even more preferably below 140°C.
此外，絕緣層627的側面較佳為具有錐形形狀。藉由使絕緣層627的側面端部具有正錐形形狀（小於90度，較佳為60度以下，更佳為45度以下），可以以設置在絕緣層627的側面端部上的共用層614及共用電極615中不發生斷開或局部性的薄膜化等的方式高覆蓋性地進行沉積。由此，可以提高共用層614及共用電極615的面內均勻性而提高顯示裝置的顯示品質。Furthermore, the side surfaces of the insulating layer 627 are preferably tapered. By making the side edges of the insulating layer 627 have a right tapered angle (less than 90 degrees, preferably less than 60 degrees, and more preferably less than 45 degrees), the common layer 614 and common electrode 615 provided on the side edges of the insulating layer 627 can be deposited with high coverage without causing any breaks or localized thinning. This improves the in-plane uniformity of the common layer 614 and common electrode 615, thereby enhancing the display quality of the display device.
此外，在顯示裝置的剖面圖中，絕緣層627的頂面較佳為具有凸曲面形狀。絕緣層627的頂面的凸曲面形狀較佳為向中心平緩地突出的形狀。藉由作為絕緣層627採用上述形狀，可以將共用層614及共用電極615以高覆蓋性沉積在絕緣層627的整個頂面。Furthermore, in the cross-sectional view of the display device, the top surface of insulating layer 627 preferably has a convex surface shape. The convex surface shape of the top surface of insulating layer 627 preferably protrudes gently toward the center. By adopting this shape for insulating layer 627, common layer 614 and common electrode 615 can be deposited with high coverage over the entire top surface of insulating layer 627.
此外，絕緣層627形成在兩個EL層間的區域（例如，層613a與層613b間的區域）。此時，絕緣層627的一部分夾在一個EL層（例如，層613a）的側面端部與另一個EL層（例如，層613b）的側面端部間。Furthermore, the insulating layer 627 is formed in a region between two EL layers (e.g., between layer 613a and layer 613b). In this case, a portion of the insulating layer 627 is sandwiched between a side edge of one EL layer (e.g., layer 613a) and a side edge of the other EL layer (e.g., layer 613b).
較佳的是，絕緣層627的一個端部與用作像素電極的導電層611a重疊，絕緣層627的另一個端部與用作像素電極的導電層611b重疊。藉由採用上述結構，可以將絕緣層627的端部形成在層613a（層613b）的平坦或大致平坦的區域上。因此，如上所述那樣較容易地加工絕緣層627的錐形形狀。Preferably, one end of insulating layer 627 overlaps with conductive layer 611a, which serves as the pixel electrode, and the other end overlaps with conductive layer 611b, which serves as the pixel electrode. This structure allows the ends of insulating layer 627 to be formed on a flat or substantially flat area of layer 613a (layer 613b). Consequently, as described above, the tapered shape of insulating layer 627 can be easily processed.
如上所述，藉由設置絕緣層627等，可以防止從層613a的平坦或大致平坦的區域到層613b的平坦或大致平坦的區域的共用層614及共用電極615中產生斷開部分及厚度局部性地減薄的部分。因此，可以抑制在各發光元件間的共用層614及共用電極615中發生起因於斷開部分的連接不良以及起因於局部厚度較薄的部分的電阻上升。As described above, the provision of insulating layer 627 and the like prevents the occurrence of disconnected portions and locally thinned portions in common layer 614 and common electrode 615 from the flat or substantially flat region of layer 613a to the flat or substantially flat region of layer 613b. Consequently, poor connection due to disconnected portions and increased resistance due to locally thinned portions in common layer 614 and common electrode 615 between light-emitting elements can be suppressed.
在本實施方式的顯示裝置中，可以縮小發光元件間的距離。明確而言，可以使發光元件間的距離、EL層間的距離或像素電極間的距離減小到小於10μm、8μm以下、5μm以下、3μm以下、2μm以下、1μm以下、500nm以下、200nm以下、100nm以下、90nm以下、70nm以下、50nm以下、30nm以下、20nm以下、15nm以下或10nm以下。換言之，本實施方式的顯示裝置具有相鄰的兩個島狀EL層的間隔為1μm以下的區域，較佳為具有該間隔為0.5μm（500nm）以下的區域，更佳為具有該間隔為100nm以下的區域。藉由如上述那樣減小各發光元件間的距離，可以提供一種高清晰度及高開口率的顯示裝置。In the display device of this embodiment, the distance between light-emitting elements can be reduced. Specifically, the distance between light-emitting elements, the distance between EL layers, or the distance between pixel electrodes can be reduced to less than 10μm, less than 8μm, less than 5μm, less than 3μm, less than 2μm, less than 1μm, less than 500nm, less than 200nm, less than 100nm, less than 90nm, less than 70nm, less than 50nm, less than 30nm, less than 20nm, less than 15nm, or less than 10nm. In other words, the display device of this embodiment has a region where the distance between two adjacent island-shaped EL layers is less than 1μm, preferably less than 0.5μm (500nm), and even more preferably less than 100nm. By reducing the distance between the light-emitting elements as described above, a display device with high definition and high aperture ratio can be provided.
發光元件650上設置有保護層631。保護層631被用作保護發光元件650的鈍化膜。藉由形成覆蓋發光元件的保護層631，可以抑制水及氧等雜質進入發光元件，由此可以提高發光元件650的可靠性。保護層631較佳為採用至少包含無機絕緣膜的單層結構或疊層結構。作為無機絕緣膜，例如可以舉出氧化矽膜、氧氮化矽膜、氮氧化矽膜、氮化矽膜、氧化鋁膜、氧氮化鋁膜或氧化鉿膜等氧化物膜或氮化物膜。此外，作為保護層631，也可以使用銦鎵氧化物或銦鎵鋅氧化物（IGZO）等半導體材料。作為保護層631，可以使用ALD法、CVD法及濺射法等形成。注意，雖然作為保護層631示出包括無機絕緣膜的結構，但是不侷限於此。例如，作為保護層631，也可以採用無機絕緣膜和有機絕緣膜的疊層結構。A protective layer 631 is provided on the light-emitting element 650. Protective layer 631 serves as a passivation film to protect the light-emitting element 650. By forming protective layer 631 covering the light-emitting element, impurities such as water and oxygen can be prevented from entering the light-emitting element, thereby improving the reliability of the light-emitting element 650. Protective layer 631 preferably has a single-layer structure or a stacked-layer structure comprising at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride film, aluminum oxide, aluminum oxynitride, or alumina. Alternatively, semiconductor materials such as indium gallium oxide or indium gallium zinc oxide (IGZO) can be used as the protective layer 631. The protective layer 631 can be formed using methods such as ALD, CVD, and sputtering. Note that while the protective layer 631 is shown as including an inorganic insulating film, the present invention is not limited to this. For example, a stacked structure of an inorganic insulating film and an organic insulating film can also be used as the protective layer 631.
保護層631和基板610由黏合層607黏合。作為發光元件的密封可以採用固體密封結構或中空密封結構等。在圖33中，基板410與基板610之間的空間被黏合層607填充，即採用固體密封結構。或者，也可以採用使用非活性氣體（氮或氬等）填充該空間的中空密封結構。此時，黏合層607也可以以不與發光元件重疊的方式設置。此外，也可以使用與設置為框狀的黏合層607不同的樹脂填充該空間。Protective layer 631 and substrate 610 are bonded together by adhesive layer 607. The light-emitting element can be sealed using either a solid sealing structure or a hollow sealing structure. In Figure 33 , the space between substrates 410 and 610 is filled with adhesive layer 607, employing a solid sealing structure. Alternatively, a hollow sealing structure can be employed, in which the space is filled with an inert gas (such as nitrogen or argon). In this case, adhesive layer 607 can be positioned so that it does not overlap the light-emitting element. Furthermore, a different resin than the frame-shaped adhesive layer 607 can be used to fill the space.
作為黏合層607，可以使用紫外線硬化型黏合劑等光硬化型黏合劑、反應硬化型黏合劑、熱固性黏合劑或厭氧黏合劑等各種硬化型黏合劑。作為這些黏合劑，例如可以舉出環氧樹脂、丙烯酸樹脂、矽酮樹脂、酚醛樹脂、聚醯亞胺樹脂、PVC（聚氯乙烯）樹脂、PVB（聚乙烯醇縮丁醛）樹脂、EVA（乙烯-醋酸乙烯酯）樹脂。尤其是，較佳為使用環氧樹脂等透濕性低的材料。此外，也可以使用兩液混合型樹脂。此外，也可以使用黏合薄片。Adhesive layer 607 can be made from a variety of curing adhesives, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, epoxy resins with low moisture permeability are preferred. Two-component mixed resins can also be used. Alternatively, an adhesive sheet can be used.
顯示裝置600A具有頂部發射結構。發光元件將光發射到基板610一側。因此，基板610較佳為使用對可見光的透過性高的材料。例如，作為基板610，較佳為選擇可應用於基板410的基板中可見光透過性高的基板。像素電極包含反射可見光的材料，相對電極（共用電極615）包含使可見光透過的材料。Display device 600A has a top-emitting structure. The light-emitting elements emit light toward one side of substrate 610. Therefore, substrate 610 is preferably made of a material with high visible light transmittance. For example, a substrate with high visible light transmittance, such as that used in substrate 410, is preferably selected for substrate 610. The pixel electrode is made of a material that reflects visible light, while the counter electrode (common electrode 615) is made of a material that transmits visible light.
注意，本發明的一個實施方式的顯示裝置也可以採用發光元件所發射的光射出到基板410一側的底部發射結構而不採用頂部發射結構。在此情況下，作為基板410選擇對可見光具有高透過性的基板即可。Note that the display device of one embodiment of the present invention may also adopt a bottom-emitting structure, in which light emitted by the light-emitting element is emitted to one side of the substrate 410, rather than a top-emitting structure. In this case, a substrate having high transmittance to visible light can be selected as the substrate 410.
[顯示裝置的結構例子2] 圖34示出顯示裝置600B的剖面圖。[Display Device Structure Example 2]Figure 34 shows a cross-sectional view of a display device 600B.
藉由將具有撓性的基板用於基板541及基板610，顯示裝置600B可以為具有撓性的顯示裝置（也稱為撓性顯示器）。使用黏合層543將基板541與絕緣層545貼合。基板610由黏合層607與保護層631貼合。By using flexible substrates for substrate 541 and substrate 610, display device 600B can be a flexible display device (also called a flexible display). Adhesive layer 543 is used to bond substrate 541 to insulating layer 545. Adhesive layer 607 is used to bond substrate 610 to protective layer 631.
顯示裝置600B的元件層660與顯示裝置600A的元件層660的不同之處主要在於：在顯示裝置600B中，層613a、層613b及層613c採用同一結構，並且設置有彩色層628R、彩色層628G及彩色層628B。The main difference between the device layer 660 of the display device 600B and the device layer 660 of the display device 600A is that in the display device 600B, the layers 613a, 613b, and 613c have the same structure, and the color layer 628R, the color layer 628G, and the color layer 628B are provided.
層613a、層613b及層613c使用同一製程及同一材料形成。此外，層613a、層613b及層613c彼此分離。藉由在各發光元件中設置島狀的EL層，可以抑制相鄰的發光元件間的洩漏電流（有時稱為橫方向洩漏電流、橫洩漏電流或橫向洩漏電流）。由此，可以防止串擾所引起的非意圖的發光，並且可以抑制相鄰的發光元件間的顏色混色，從而可以實現對比度極高的顯示裝置。Layers 613a, 613b, and 613c are formed using the same process and materials. Furthermore, layers 613a, 613b, and 613c are isolated from one another. Providing island-shaped EL layers in each light-emitting element suppresses leakage current (sometimes referred to as lateral leakage, horizontal leakage, or horizontal leakage) between adjacent light-emitting elements. This prevents unintended emission caused by crosstalk and suppresses color mixing between adjacent light-emitting elements, enabling the realization of a display device with extremely high contrast.
例如，圖34所示的發光元件650R、650G、650B發射白色光。發光元件650R、650G、650B所發射的白色光透過彩色層628R、彩色層628G及彩色層628B，由此可以得到所希望的顏色的光。For example, light emitting elements 650R, 650G, and 650B shown in Fig. 34 emit white light. The white light emitted by light emitting elements 650R, 650G, and 650B passes through color layers 628R, 628G, and 628B, thereby obtaining light of a desired color.
此外，藉由採用微腔結構，具有發射白色光的結構的發光元件有時加強紅色、綠色或藍色等特定顏色而發光。Furthermore, by employing a microcavity structure, a light-emitting element having a structure for emitting white light can sometimes emit light with a specific color such as red, green, or blue enhanced.
發光元件650R的發光藉由彩色層628R作為紅色光提取到顯示裝置600B的外部。同樣地，發光元件650G的發光藉由彩色層628G作為綠色光提取到顯示裝置600B的外部。發光元件650B的發光藉由彩色層628B作為藍色光提取到顯示裝置600B的外部。Light emitted by light-emitting element 650R is extracted as red light outside display device 600B via color layer 628R. Similarly, light emitted by light-emitting element 650G is extracted as green light outside display device 600B via color layer 628G. Light emitted by light-emitting element 650B is extracted as blue light outside display device 600B via color layer 628B.
發射白色光的發光元件較佳為採用串聯結構。The light-emitting elements emitting white light preferably adopt a series structure.
或者，例如圖34所示的發光元件650R、650G、650B發射藍色光。此時，層613a、層613b及層613c包括一層以上的發射藍色光的發光層。關於呈現藍色光的子像素，可以提取發光元件650B所發射的藍色光。此外，關於呈現紅色光的子像素及呈現綠色光的子像素，藉由在發光元件650R與彩色層628R之間及發光元件650G與彩色層628G之間設置顏色轉換層，可以使發光元件650R或發光元件650G所發射的藍色光轉換為更長波長的光而提取為紅色光或綠色光。藉由經由彩色層提取透過顏色轉換層的光，可以由彩色層吸收所希望的顏色光之外的光而提高子像素所呈現的光的色純度。Alternatively, for example, light-emitting elements 650R, 650G, and 650B shown in FIG34 emit blue light. In this case, layers 613a, 613b, and 613c include one or more light-emitting layers that emit blue light. For sub-pixels that emit blue light, the blue light emitted by light-emitting element 650B can be extracted. Furthermore, for sub-pixels that emit red light and sub-pixels that emit green light, by providing color conversion layers between light-emitting element 650R and color layer 628R, and between light-emitting element 650G and color layer 628G, the blue light emitted by light-emitting element 650R or light-emitting element 650G can be converted into light of a longer wavelength and extracted as red or green light. By extracting light that has passed through the color conversion layer through the color layer, the color layer can absorb light other than the desired color light, thereby improving the color purity of the light presented by the sub-pixel.
彩色層是選擇性地透過特定波長區域的光而吸收其他波長區域的光的有色層。例如，可以使用透過紅色波長區域的光的紅色（R）濾色片、透過綠色波長區域的光的綠色（G）濾色片、透過藍色波長區域的光的藍色（B）濾色片等。各彩色層可以使用金屬材料、樹脂材料、顏料、染料中的一種或多種。彩色層利用印刷法、噴墨法、使用光微影法的蝕刻方法等在所需的位置形成。Color layers selectively transmit light of specific wavelengths while absorbing light of other wavelengths. For example, a red (R) filter that transmits red light, a green (G) filter that transmits green light, and a blue (B) filter that transmits blue light can be used. Each color layer can be made of one or more of a metal material, resin material, pigment, or dye. The color layers are formed in the desired locations using methods such as printing, inkjet printing, and etching using photolithography.
顯示裝置600B的元件層630具有與顯示裝置600A的元件層630同樣的結構，所以省略詳細說明。The device layer 630 of the display device 600B has the same structure as the device layer 630 of the display device 600A, so detailed description is omitted.
顯示裝置600B與顯示裝置600A的不同之處在於：前者不包括元件層620而包括元件層635。元件層635具有與元件層630同樣的結構。The display device 600B differs from the display device 600A in that the former does not include the device layer 620 but includes a device layer 635. The device layer 635 has the same structure as the device layer 630.
元件層635所包括的電晶體的至少一部分藉由插頭及佈線等與元件層630所包括的導電層或電晶體連接。此外，也可以在元件層630與元件層635之間設置有佈線層670。At least a portion of the transistors included in the device layer 635 is connected to the conductive layer or transistors included in the device layer 630 via plugs, wiring, etc. Furthermore, a wiring layer 670 may be provided between the device layer 630 and the device layer 635 .
元件層635較佳為設置有顯示裝置的像素電路和驅動電路中的一者或兩者。The device layer 635 is preferably provided with one or both of the pixel circuit and the driver circuit of the display device.
雖然圖34示出層疊兩個包括OS電晶體的元件層的例子（元件層630及元件層635），但是元件層的疊層個數不侷限於此，也可以為三個以上。例如，在層疊三層以上的包括OS電晶體的元件層的情況下，較佳的是，將最下層用於顯示裝置的驅動電路（閘極驅動器和源極驅動器中的一者或兩者），將最上層用於顯示裝置的像素電路，並且將位於它們之間的層用於像素電路或驅動電路。Although FIG34 illustrates an example of stacking two device layers including OS transistors (device layer 630 and device layer 635), the number of stacked device layers is not limited to this and may be three or more. For example, when stacking three or more device layers including OS transistors, it is preferred that the bottom layer be used for the driver circuit (one or both of the gate driver and the source driver) of the display device, the top layer be used for the pixel circuit of the display device, and the layers between these layers be used for the pixel circuit or the driver circuit.
注意，Si電晶體典型地形成在單晶Si晶圓上，所以難以採用具有撓性的結構。另一方面，如圖34所示，在只使用OS電晶體而不使用Si電晶體構成顯示裝置的情況下，可以藉由較簡單的製造程序實現具有撓性的結構。Note that Si transistors are typically formed on single-crystal Si wafers, making it difficult to adopt a flexible structure. On the other hand, as shown in Figure 34, when a display device is constructed using only OS transistors without Si transistors, a flexible structure can be achieved through a simpler manufacturing process.
[發光元件的結構例子] 接著，對可用於本發明的一個實施方式的顯示裝置的發光元件進行說明。以下，主要說明與圖33及圖34所示的結構不同的發光元件的結構例子。[Example Light-Emitting Element Structure]Next, a light-emitting element that can be used in a display device according to one embodiment of the present invention will be described. The following mainly describes an example light-emitting element structure that differs from the structure shown in Figures 33 and 34.
圖35A示出包括多個發光元件的顯示部的一部分的俯視示意圖。顯示部包括呈現紅色光的多個發光元件61R、呈現綠色光的多個發光元件61G及呈現藍色光的多個發光元件61B。在圖35A中為了便於區別各發光元件，在各發光元件的發光區域內附上符號R、G、B。此外，圖35A示出採用具有紅色（R）、綠色（G）及藍色（B）這三個發光顏色的結構作為一個例子，但不侷限於此。例如，也可以採用具有四個以上的顏色的結構。Figure 35A shows a schematic top view of a portion of a display unit comprising multiple light-emitting elements. The display unit includes multiple light-emitting elements 61R that emit red light, multiple light-emitting elements 61G that emit green light, and multiple light-emitting elements 61B that emit blue light. In Figure 35A , the light-emitting regions of each light-emitting element are labeled R, G, and B to facilitate identification. While Figure 35A illustrates a structure with three light-emitting colors—red (R), green (G), and blue (B)—as an example, the present invention is not limited to this. For example, a structure with four or more colors may also be employed.
圖35B是沿著圖35A所示的點劃線A1-A2的剖面圖。圖35B所示的發光元件61R、發光元件61G及發光元件61B都設置在絕緣層363上並包括用作像素電極的導電層171及用作共用電極的導電層173。作為絕緣層363，可以使用無機絕緣膜和有機絕緣膜中的一者或兩者。FIG35B is a cross-sectional view taken along dotted line A1-A2 in FIG35A. Light-emitting element 61R, light-emitting element 61G, and light-emitting element 61B shown in FIG35B are all provided on insulating layer 363 and include conductive layer 171 serving as a pixel electrode and conductive layer 173 serving as a common electrode. Insulating layer 363 can be made of either an inorganic insulating film or an organic insulating film, or both.
發光元件61R在用作像素電極的導電層171與用作共用電極的導電層173之間包括EL層172R。EL層172R包含發射在紅色波長區域具有峰的光的發光性化合物。發光元件61G中的EL層172G包含發射在綠色波長區域具有峰的光的發光性化合物。發光元件61B中的EL層172B包含發射在藍色波長區域具有峰的光的發光性化合物。Light-emitting element 61R includes an EL layer 172R between conductive layer 171, which serves as a pixel electrode, and conductive layer 173, which serves as a common electrode. EL layer 172R contains a luminescent compound that emits light with a peak in the red wavelength region. EL layer 172G in light-emitting element 61G contains a luminescent compound that emits light with a peak in the green wavelength region. EL layer 172B in light-emitting element 61B contains a luminescent compound that emits light with a peak in the blue wavelength region.
每個發光元件都設置有用作像素電極的導電層171。此外，用作共用電極的導電層173為各發光元件共同使用的連續的層。用作像素電極的導電層171和用作共用電極的導電層173中的任一個使用對可見光具有透光性的導電膜，另一個使用具有反射性的導電膜。Each light-emitting element is provided with a conductive layer 171 serving as a pixel electrode. Furthermore, a conductive layer 173 serving as a common electrode is a continuous layer shared by all light-emitting elements. Either conductive layer 171 serving as a pixel electrode or conductive layer 173 serving as a common electrode is made of a conductive film that is transmissive to visible light, while the other is made of a reflective conductive film.
例如，在發光元件61R具有頂部發射結構時，來自發光元件61R的光175R被發射到導電層173一側。在發光元件61G具有頂部發射結構時，來自發光元件61G的光175G被發射到導電層173一側。在發光元件61B具有頂部發射結構時，來自發光元件61B的光175B被發射到導電層173一側。For example, when light-emitting element 61R has a top-emitting structure, light 175R from light-emitting element 61R is emitted toward conductive layer 173. When light-emitting element 61G has a top-emitting structure, light 175G from light-emitting element 61G is emitted toward conductive layer 173. When light-emitting element 61B has a top-emitting structure, light 175B from light-emitting element 61B is emitted toward conductive layer 173.
以覆蓋用作像素電極的導電層171的端部的方式設置絕緣層272。絕緣層272的端部較佳具有錐形形狀。作為絕緣層272可以使用無機絕緣膜和有機絕緣膜中的一者或兩者。The insulating layer 272 is provided so as to cover the end of the conductive layer 171 serving as the pixel electrode. The end of the insulating layer 272 preferably has a tapered shape. As the insulating layer 272, one or both of an inorganic insulating film and an organic insulating film can be used.
絕緣層272是為了防止相鄰的發光元件之間非意圖地短路並從發光元件非意圖地發光而設置的。此外，絕緣層272還具有當使用金屬遮罩形成EL層時不使金屬遮罩與導電層171接觸的功能。The insulating layer 272 is provided to prevent unintentional short circuits between adjacent light-emitting elements and unintentional light emission from the light-emitting elements. In addition, the insulating layer 272 also has the function of preventing the metal mask from contacting the conductive layer 171 when the EL layer is formed using the metal mask.
EL層172R、EL層172G及EL層172B各自包括與用作像素電極的導電層171的頂面接觸的區域以及與絕緣層272的表面接觸的區域。此外，EL層172R、EL層172G及EL層172B的端部位於絕緣層272上。EL layer 172R, EL layer 172G, and EL layer 172B each include a region in contact with the top surface of conductive layer 171 serving as a pixel electrode and a region in contact with the surface of insulating layer 272. Furthermore, the ends of EL layer 172R, EL layer 172G, and EL layer 172B are located on insulating layer 272.
如圖35B所示，在顏色不同的發光元件之間，在兩個EL層之間設置間隙。如此，較佳為以互不接觸的方式設置EL層172R、EL層172G及EL層172B。由此，可以適當地防止電流流過相鄰的兩個EL層而產生非意圖性發光（也稱為串擾）。因此，可以提高對比度並實現顯示品質高的顯示裝置。As shown in Figure 35B, a gap is provided between the two EL layers between light-emitting elements of different colors. In this way, EL layers 172R, 172G, and 172B are preferably arranged so as not to contact each other. This effectively prevents current from flowing through adjacent EL layers and causing unintended emission (also known as crosstalk). This improves contrast and enables a high-quality display device.
藉由利用使用金屬遮罩等陰影遮罩的真空蒸鍍法等，可以分開製造EL層172R、EL層172G及EL層172B。此外，也可以藉由光微影法分開製造上述EL層。藉由利用光微影法，可以實現在使用金屬遮罩時難以實現的高清晰度的顯示裝置。EL layer 172R, EL layer 172G, and EL layer 172B can be fabricated separately by vacuum evaporation using a shadow mask such as a metal mask. Alternatively, these EL layers can be fabricated separately using photolithography. Photolithography enables the realization of high-definition display devices, which is difficult to achieve using a metal mask.
此外，在用作共用電極的導電層173上以覆蓋發光元件61R、發光元件61G及發光元件61B的方式設置保護層271。保護層271具有防止水等雜質從上方擴散到各發光元件的功能。關於保護層271的材料，可以參照上述保護層631的材料。Furthermore, a protective layer 271 is provided on conductive layer 173, which serves as a common electrode, to cover light-emitting elements 61R, 61G, and 61B. Protective layer 271 prevents impurities such as water from diffusing from above into each light-emitting element. The material for protective layer 271 can be referenced to the material for protective layer 631 described above.
圖35C示出呈現白色光的發光元件61W。發光元件61W在用作像素電極的導電層171與用作共用電極的導電層173之間包括呈現白色光的EL層172W。35C shows a light-emitting element 61W that emits white light. The light-emitting element 61W includes an EL layer 172W that emits white light between a conductive layer 171 that serves as a pixel electrode and a conductive layer 173 that serves as a common electrode.
作為EL層172W，例如可以採用層疊有以各自的發光顏色成為補色關係的方式選擇的兩個以上的發光層的結構。此外，也可以使用在發光層之間夾有電荷產生層的串聯型EL層。The EL layer 172W may have a structure in which two or more light-emitting layers are stacked, for example, selected so that their luminescent colors are complementary to each other. Alternatively, a tandem EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.
圖35C並列地示出三個發光元件61W。左邊的發光元件61W的上部設置有彩色層264R。彩色層264R被用作使紅色光透過的帶通濾光片。同樣地，中間的發光元件61W的上部設置有使綠色光透過的彩色層264G，右邊的發光元件61W的上部設置有使藍色光透過的彩色層264B。由此，可以使顯示裝置顯示彩色影像。Figure 35C shows three light-emitting elements 61W side by side. A color layer 264R is provided on top of the left light-emitting element 61W. Color layer 264R functions as a bandpass filter that transmits red light. Similarly, a color layer 264G that transmits green light is provided on top of the center light-emitting element 61W, and a color layer 264B that transmits blue light is provided on top of the right light-emitting element 61W. This allows the display device to display color images.
在此，在相鄰的兩個發光元件61W之間EL層172W被分開。由此，可以防止在相鄰的兩個發光元件61W中電流藉由EL層172W流過而產生非意圖性發光。特別是在作為EL層172W使用兩個發光層之間設有電荷產生層的疊層型EL層時具有如下問題：當清晰度越高，即相鄰的像素間的距離越小時，串擾的影響越明顯，而對比度降低。因此，藉由採用這種結構，可以實現兼具高清晰度和高對比的顯示裝置。Here, the EL layer 172W is separated between two adjacent light-emitting elements 61W. This prevents unintended light emission caused by current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when using a stacked EL layer 172W with a charge-generating layer between the two light-emitting layers, the effect of crosstalk becomes more pronounced, resulting in a decrease in contrast, as the resolution increases—that is, the distance between adjacent pixels decreases. Therefore, adopting this structure enables a display device that achieves both high resolution and high contrast.
較佳為利用光微影法分開EL層172W。由此，可以縮小發光元件之間的間隙，例如與使用金屬遮罩等陰影遮罩時相比，可以實現具有高開口率的顯示裝置。Preferably, the EL layer 172W is separated using photolithography. This can reduce the gap between the light-emitting elements, and can achieve a display device with a higher aperture ratio than when using a shadow mask such as a metal mask.
本實施方式可以與其他實施方式適當地組合。此外，在本說明書中，在一個實施方式中示出多個結構例子的情況下，可以適當地組合該結構例子。This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.
實施方式7 在本實施方式中，使用圖36至圖40說明本發明的一個實施方式的半導體裝置的應用例子。Embodiment 7This embodiment describes an application example of a semiconductor device according to one embodiment of the present invention using Figures 36 to 40.
例如，可以將本發明的一個實施方式的半導體裝置用於電子構件、大型電腦、太空設備及資料中心（Data Center：也稱為DC）及各種電子裝置。藉由使用本發明的一個實施方式的半導體裝置，可以實現電子構件、大型電腦、太空設備、資料中心及各種電子裝置的低功耗化及高性能化。For example, the semiconductor device according to one embodiment of the present invention can be used in electronic components, mainframe computers, space equipment, data centers (also known as DCs), and various other electronic devices. By using the semiconductor device according to one embodiment of the present invention, it is possible to achieve lower power consumption and higher performance in electronic components, mainframe computers, space equipment, data centers, and various other electronic devices.
此外，可以將包括本發明的一個實施方式的半導體裝置的顯示裝置用於各種電子裝置的顯示部。包括本發明的一個實施方式的半導體裝置的顯示裝置容易實現高清晰化及高解析度化。Furthermore, a display device including the semiconductor device according to one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device according to one embodiment of the present invention can easily achieve high definition and high resolution.
作為電子裝置，例如除了電視機、桌上型或筆記本型電腦、用於電腦等的顯示器、數位看板、彈珠機等大型遊戲機等具有較大的螢幕的電子裝置以外，還可以舉出數位相機、數位攝影機、數位相框、行動電話機、可攜式遊戲機、可攜式資訊終端、音頻再生裝置等。Examples of electronic devices include televisions, desktop or laptop computers, monitors for computers, digital signage, large-scale game consoles such as pinball machines, and other electronic devices with large screens. In addition, other electronic devices include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and audio playback devices.
特別是，因為本發明的一個實施方式的顯示裝置可以提高清晰度，所以可以適當地用於包括較小的顯示部的電子裝置。作為這種電子裝置可以舉出手錶型及手鐲型資訊終端設備（可穿戴裝置）、可戴在頭上的可穿戴裝置等諸如頭戴顯示器等VR用設備、眼鏡型AR用設備及MR用設備等。In particular, because the display device according to one embodiment of the present invention can achieve improved clarity, it is suitable for use in electronic devices with relatively small display units. Examples of such electronic devices include watch-type and bracelet-type information terminals (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, and glasses-type AR and MR devices.
本發明的一個實施方式的顯示裝置較佳為具有極高的解析度諸如HD（像素數為1280×720）、FHD（像素數為1920×1080）、WQHD（像素數為2560×1440）、WQXGA（像素數為2560×1600）、4K（像素數為3840×2160）、8K（像素數為7680×4320）等。尤其是，較佳為設定為4K、8K或其以上的解析度。此外，本發明的一個實施方式的顯示裝置的像素密度（清晰度）較佳為100ppi以上、300ppi以上、500ppi以上、1000ppi以上、2000ppi以上、3000ppi以上、5000ppi以上或7000ppi以上。藉由使用上述具有高解析度和高清晰度中的一者或兩者的顯示裝置，可以進一步提高真實感及縱深感等。此外，對本發明的一個實施方式的顯示裝置的螢幕比例（縱橫比）沒有特別的限制。例如，顯示裝置可以適應1：1（正方形）、4：3、16：9或16：10等各種螢幕比例。The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K (3840×2160 pixels), or 8K (7680×4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention preferably is 100 ppi or higher, 300 ppi or higher, 500 ppi or higher, 1000 ppi or higher, 2000 ppi or higher, 3000 ppi or higher, 5000 ppi or higher, or 7000 ppi or higher. By using a display device with either or both high resolution and high definition, the sense of realism and depth can be further enhanced. Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display device in one embodiment of the present invention. For example, the display device can accommodate various screen ratios, such as 1:1 (square), 4:3, 16:9, or 16:10.
本實施方式的電子裝置也可以包括感測器（該感測器具有感測、檢測、測量如下因素的功能：力、位移、位置、速度、加速度、角速度、轉速、距離、光、液、磁、溫度、化學物質、聲音、時間、硬度、電場、電流、電壓、電力、輻射線、流量、濕度、傾斜度、振動、氣味或紅外線）。The electronic device of this embodiment may also include a sensor (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor, or infrared).
本實施方式的電子裝置可以具有各種功能。例如，可以具有如下功能：將各種資訊（靜態影像、動態影像或文字影像等）顯示在顯示部上的功能；觸控面板的功能；顯示日曆、日期或時間等的功能；執行各種軟體（程式）的功能；進行無線通訊的功能；讀出儲存在存儲介質中的程式或資料的功能；等。The electronic device of this embodiment can have various functions. For example, it can have the following functions: the function of displaying various information (still images, moving images, text images, etc.) on a display unit; the function of using a touch panel; the function of displaying a calendar, date, or time; the function of executing various software (programs); the function of conducting wireless communication; the function of reading programs or data stored in a storage medium; etc.
[電子構件] 接著，圖36示出電子構件730的立體圖。電子構件730是SiP（System in Package：系統封裝）或MCM（Multi Chip Module：多晶片模組）的一個例子。在電子構件730中，封裝基板732（印刷電路板）上設置有插板（interposer）731，插板731上設置有半導體裝置735及多個半導體裝置710。[Electronic Component]Figure 36 shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). In electronic component 730, an interposer 731 is mounted on a package substrate 732 (printed circuit board). A semiconductor device 735 and multiple semiconductor devices 710 are mounted on interposer 731.
半導體裝置710可以使用實施方式5中說明的記憶體裝置3112。The semiconductor device 710 can use the memory device 3112 described in the fifth embodiment.
電子構件730示出將半導體裝置710用作高頻寬記憶體（HBM：High Bandwidth Memory）的例子。此外，半導體裝置735可以用於CPU、GPU或FPGA（Field Programmable Gate Array：現場可程式邏輯閘陣列）等積體電路。Electronic component 730 illustrates an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Alternatively, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs, and FPGAs.
封裝基板732例如可以使用陶瓷基板、塑膠基板或玻璃環氧基板。插板731例如可以使用矽插板或樹脂插板。The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicone interposer or a resin interposer.
插板731具有多個佈線並具有連接端子間距不同的多個積體電路的功能。多個佈線由單層或多層構成。此外，插板731具有將設置於插板731上的積體電路與設置於封裝基板732上的電極連接的功能。因此，有時將插板也稱為“重佈線基板（rewiring substrate）”或“中間基板”。此外，有時藉由在插板731中設置貫通電極，藉由該貫通電極使積體電路與封裝基板732連接。此外，在使用矽插板的情況下，也可以使用TSV作為貫通電極。Interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. These wirings may be composed of a single layer or multiple layers. Interposer 731 also functions to connect the integrated circuits provided on interposer 731 to electrodes provided on package substrate 732. Therefore, interposers are sometimes referred to as "rewiring substrates" or "intermediate substrates." Furthermore, through-electrodes are sometimes provided in interposer 731 to connect the integrated circuits to package substrate 732. Furthermore, when using a silicon interposer, TSVs can also be used as through-electrodes.
在HBM中，為了實現寬記憶體頻寬需要連接許多佈線。為此，要求安裝HBM的插板上能夠高密度地形成微細的佈線。因此，作為安裝HBM的插板較佳為使用矽插板。To achieve high memory bandwidth in HBM, numerous interconnects are required. This requires the ability to form fine wiring at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is the preferred interposer for mounting the HBM.
此外，在使用矽插板的SiP及MCM等中，不容易發生因積體電路與插板間的膨脹係數的不同而導致的可靠性下降。此外，由於矽插板的表面平坦性高，所以設置在矽插板上的積體電路與矽插板間不容易產生連接不良。尤其較佳為將矽插板用於2.5D封裝（2.5D安裝），其中多個積體電路橫著排放並配置於插板上。Furthermore, in SiPs and MCMs using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. Furthermore, due to the high surface flatness of the silicon interposer, poor connections between the integrated circuits mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly well-suited for 2.5D packaging (2.5D mounting), in which multiple integrated circuits are arranged horizontally on the interposer.
另一方面，當利用矽插板及TSV等使端子間距不同的多個積體電路連接時，需要該端子間距的寬度等的空間。因此，當想要縮小電子構件730的尺寸時，有上述端子間距的寬度的問題，有時難以設置為實現寬記憶體頻寬需要的多個佈線。於是，如上所述，使用OS電晶體的單片疊層結構是較佳的。此外，也可以採用組合利用TSV層疊的記憶單元陣列與以單片的方式層疊的記憶單元陣列的複合結構。On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when trying to reduce the size of electronic component 730, the width of the terminal pitch mentioned above becomes an issue, and it is sometimes difficult to set up the multiple wiring required to achieve wide memory bandwidth. Therefore, as mentioned above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can be adopted.
此外，也可以與電子構件730重疊地設置散熱器（散熱板）。在設置散熱器的情況下，較佳為使設置於插板731上的積體電路的高度一致。例如，在本實施方式所示的電子構件730中，較佳為使半導體裝置710與半導體裝置735的高度一致。Alternatively, a heat sink (heat sink plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor devices 710 and 735.
為了將電子構件730安裝在其他基板上，也可以在封裝基板732的底部設置電極733。圖36示出用焊球形成電極733的例子。藉由在封裝基板732的底部以矩陣狀設置焊球，可以實現BGA（Ball Grid Array：球柵陣列）的安裝。此外，電極733也可以使用導電針形成。藉由在封裝基板732的底部以矩陣狀設置導電針，可以實現PGA（Pin Grid Array：針柵陣列）的安裝。To mount electronic component 730 on another substrate, electrodes 733 can be provided on the bottom of package substrate 732. Figure 36 shows an example of electrodes 733 formed using solder balls. By arranging solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 can be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
電子構件730可以藉由各種安裝方式安裝在其他基板上，而不侷限於BGA及PGA。作為安裝方法例如可以舉出SPGA（Staggered Pin Grid Array：交錯針柵陣列）、LGA（Land Grid Array：地柵陣列）、QFP（Quad Flat Package：四面扁平封裝）、QFJ（Quad Flat J-leaded package：四側J形引腳扁平封裝）及QFN（Quad Flat Non-leaded package：四側無引腳扁平封裝）。Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded Package), and QFN (Quad Flat Non-leaded Package).
半導體裝置710可以被稱為裸片。注意，在本說明書等中，裸片是指在半導體晶片的製程中例如在圓盤狀的基板（也稱為晶圓）等上形成電路圖案，切割成矩形小片而得的晶片。作為可用於裸片的半導體材料，例如可以舉出矽（Si）、碳化矽（SiC）或氮化鎵（GaN）等。例如，有時將從矽基板（也稱為矽晶圓）得到的裸片稱為矽晶圓。Semiconductor device 710 may be referred to as a bare die. Note that in this specification and other documents, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) during semiconductor chip manufacturing, for example, and then cutting it into rectangular pieces. Examples of semiconductor materials that can be used for bare chips include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.
[大型電腦] 接著，圖37A示出大型電腦5600的立體圖。在圖37A所示的大型電腦5600中，多個機架式電腦5620收納在機架5610中。此外，也可以將大型電腦5600稱為超級電腦。[Mainframe]Next, Figure 37A shows a perspective view of a mainframe computer 5600. In mainframe computer 5600 shown in Figure 37A, multiple rack-mount computers 5620 are housed in a rack 5610. Mainframe computer 5600 can also be referred to as a supercomputer.
電腦5620例如可以具有圖37B所示的立體圖的結構。在圖37B中，電腦5620包括主機板5630，主機板5630包括多個插槽5631以及多個連接端子等。插槽5631插入有個人電腦卡5621。並且，個人電腦卡5621包括連接端子5623、連接端子5624、連接端子5625，它們連接到主機板5630。Computer 5620 can, for example, have the structure shown in the three-dimensional diagram of FIG37B . In FIG37B , computer 5620 includes a motherboard 5630, which includes multiple slots 5631 and multiple connectors. A personal computer card 5621 is inserted into slot 5631. Furthermore, personal computer card 5621 includes connectors 5623, 5624, and 5625, which connect to motherboard 5630.
圖37C所示的個人電腦卡5621是包括CPU、GPU、記憶體裝置等的處理板的一個例子。個人電腦卡5621具有板5622。此外，板5622包括連接端子5623、連接端子5624、連接端子5625、半導體裝置5626、半導體裝置5627、半導體裝置5628以及連接端子5629。注意，圖37C示出半導體裝置5626、半導體裝置5627以及半導體裝置5628以外的半導體裝置，關於這些半導體裝置的說明，可以參照以下記載的半導體裝置5626、半導體裝置5627以及半導體裝置5628的說明。Figure 37C shows a personal computer card 5621, which is an example of a processing board that includes a CPU, a GPU, a memory device, and the like. Personal computer card 5621 includes a board 5622. Board 5622 also includes connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and connection terminal 5629. Note that Figure 37C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628. For descriptions of these semiconductor devices, refer to the descriptions of semiconductor devices 5626, 5627, and 5628 described below.
連接端子5629具有可以插入主機板5630的插槽5631的形狀，連接端子5629被用作連接個人電腦卡5621與主機板5630的介面。作為連接端子5629的規格例如可以舉出PCIe等。The connector 5629 is shaped to be inserted into a slot 5631 of a motherboard 5630 and serves as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connector 5629 include PCIe.
連接端子5623、連接端子5624、連接端子5625例如可以被用作用來對個人電腦卡5621供電或輸入信號等的介面。此外，例如，可以被用作用來進行個人電腦卡5621所計算的信號的輸出等的介面。作為連接端子5623、連接端子5624、連接端子5625各自的規格例如可以舉出USB（Universal Serial Bus：通用序列匯流排）、SATA（Serial ATA：串列ATA）、SCSI（Small Computer System Interface：小型電腦系統介面）等。此外，當從連接端子5623、連接端子5624、連接端子5625輸出視頻信號時，作為各規格可以舉出HDMI（註冊商標）等。Connectors 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to PC card 5621 or inputting signals. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by PC card 5621. Examples of the standards for connectors 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connectors 5623, 5624, and 5625, the standards used can be HDMI (registered trademark).
半導體裝置5626包括進行信號的輸入及輸出的端子（未圖示），藉由將該端子插入板5622所包括的插座（未圖示），可以連接半導體裝置5626與板5622。The semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting the terminals into sockets (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be connected.
半導體裝置5627包括多個端子，例如藉由將該端子以回流焊方式銲接到板5622所包括的佈線，可以連接半導體裝置5627與板5622。作為半導體裝置5627，例如，可以舉出FPGA、GPU、CPU等。作為半導體裝置5627，例如可以使用電子構件730。Semiconductor device 5627 includes a plurality of terminals, and these terminals can be connected to wiring included in board 5622 by, for example, reflow soldering. Examples of semiconductor device 5627 include FPGAs, GPUs, and CPUs. Electronic component 730 can also be used as semiconductor device 5627.
半導體裝置5628包括多個端子，例如藉由將該端子以回流焊方式銲接到板5622所包括的佈線，可以連接半導體裝置5628與板5622。作為半導體裝置5628，例如，可以舉出記憶體裝置等。作為半導體裝置5628，例如可以使用電子構件3110。Semiconductor device 5628 includes a plurality of terminals, and these terminals can be connected to wiring included in board 5622 by, for example, reflow soldering. Examples of semiconductor device 5628 include memory devices. Electronic component 3110 can also be used as semiconductor device 5628.
大型電腦5600可以被用作平行電腦。藉由將大型電腦5600用作平行電腦，例如可以進行人工智慧的學習及推論所需要的大規模計算。The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.
[太空設備] 可以將本發明的一個實施方式的半導體裝置適用於太空設備。[Space Equipment]A semiconductor device according to one embodiment of the present invention can be used in space equipment.
本發明的一個實施方式的半導體裝置包括OS電晶體。OS電晶體的因被照射輻射線而導致的電特性變動小。換言之，對於輻射線的耐性高，所以可以在輻射線有可能入射的環境下適當地使用OS電晶體。例如，可以在宇宙空間中使用的情況下適當地使用OS電晶體。明確而言，可以將OS電晶體用作構成設置在太空梭、人造衛星或太空探測器中的半導體裝置的電晶體。作為輻射線，例如可以舉出X射線及中子輻射等。注意，宇宙空間例如是指高度100km以上，但是本說明書所示的宇宙空間可以包括熱層、中間層和平流層中的一個或多個。A semiconductor device according to one embodiment of the present invention includes an OS transistor. The electrical characteristics of the OS transistor change little due to exposure to radiation. In other words, the OS transistor has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, the OS transistor can be appropriately used when used in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron radiation. Note that outer space, for example, refers to an altitude of 100 km or more, but the outer space shown in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.
在圖37D中，作為太空設備的一個例子示出人造衛星6800。人造衛星6800包括主體6801、太陽能電池板6802、天線6803、二次電池6805以及控制裝置6807。此外，圖37D示出在宇宙空間有行星6804的例子。FIG37D shows an artificial satellite 6800 as an example of a space device. Artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. FIG37D also shows an example of a planet 6804 in outer space.
此外，雖然圖37D中未圖示，但是也可以將電池管理系統（也稱為BMS）或電池控制電路設置到二次電池6805。當將OS電晶體用於上述電池管理系統或電池控制電路時，可以具有低功耗，並且即使在宇宙空間也可以實現高可靠性，所以是較佳的。Although not shown in FIG37D , a battery management system (also called a BMS) or a battery control circuit may also be incorporated into the secondary battery 6805. Using OS transistors in such a battery management system or battery control circuit is preferred because it allows for low power consumption and high reliability even in outer space.
此外，宇宙空間是其輻射劑量為地面的100倍以上的環境。作為輻射線，例如可以舉出：以X射線及γ射線為代表的電磁波（電磁輻射線）；以及以α射線、β射線、中子射線、質子射線、重離子射線、介子射線等為代表的粒子輻射線。Furthermore, outer space is an environment with a radiation dose over 100 times greater than that of Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation), represented by X-rays and gamma rays, and particle radiation, represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and muon rays.
在陽光照射到太陽能電池板6802時產生人造衛星6800進行工作所需的電力。然而，例如在陽光不照射到太陽能電池板的情況或者在照射到太陽能電池板的陽光量較少的情況下，所產生的電力量減少。因此，有可能不會產生人造衛星6800進行工作所需的電力。為了在所產生的電力較少的情況下也使人造衛星6800工作，較佳為在人造衛星6800中設置二次電池6805。此外，有時將太陽能電池板稱為太陽能電池模組。When sunlight strikes solar panels 6802, they generate the electricity necessary to operate satellite 6800. However, if sunlight is not striking the panels or if the amount of sunlight striking the panels is low, the amount of electricity generated decreases. Consequently, satellite 6800 may not generate the electricity required for operation. To enable satellite 6800 to operate even when the generated electricity is low, secondary batteries 6805 are preferably provided in satellite 6800. Solar panels are sometimes referred to as solar cell modules.
人造衛星6800可以生成信號。該信號藉由天線6803傳送，例如地面上的接收機或其他人造衛星可以接收該信號。藉由接收人造衛星6800所傳送的信號，可以測量接收該信號的接收機的位置。由此，人造衛星6800可以構成衛星定位系統。Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received by a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver can be measured. Thus, satellite 6800 can constitute a satellite positioning system.
此外，控制裝置6807具有控制人造衛星6800的功能。控制裝置6807例如使用選自CPU、GPU和記憶體裝置中的一個或多個構成。此外，作為控制裝置6807較佳為使用包括本發明的一個實施方式的OS電晶體的半導體裝置。與Si電晶體相比，OS電晶體的因被照射輻射線而導致的電特性變動小。因此，OS電晶體在輻射線有可能入射的環境下也具有高可靠性且可以適當地使用。Furthermore, control device 6807 has the function of controlling artificial satellite 6800. Control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a memory device. Furthermore, control device 6807 is preferably a semiconductor device including an OS transistor according to one embodiment of the present invention. Compared to Si transistors, OS transistors exhibit less fluctuation in electrical characteristics due to exposure to radiation. Therefore, OS transistors are highly reliable and can be suitably used even in environments where radiation is likely to enter.
此外，人造衛星6800可以包括感測器。例如藉由包括可見光感測器，人造衛星6800可以具有被檢測地面上的物體反射的陽光的功能。或者，藉由包括熱紅外線感測器，人造衛星6800可以具有檢測從地表釋放的熱紅外線的功能。由此，人造衛星6800例如可以被用作地球觀測衛星。Furthermore, artificial satellite 6800 may include sensors. For example, by including a visible light sensor, artificial satellite 6800 can detect sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, artificial satellite 6800 can detect thermal infrared radiation emitted from the Earth's surface. Thus, artificial satellite 6800 can be used, for example, as an Earth observation satellite.
注意，在本實施方式中，作為太空設備的一個例子示出人造衛星，但是不侷限於此。例如，本發明的一個實施方式的半導體裝置可以適當地應用於太空船、太空艙、太空探測器等太空設備。Note that while this embodiment shows an artificial satellite as an example of space equipment, the present invention is not limited thereto. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.
如以上的說明那樣，與Si電晶體相比，OS電晶體具有優異的效果，諸如可以實現寬記憶體頻寬、對於輻射線的高耐性。As explained above, OS transistors offer superior benefits compared to Si transistors, such as achieving wide memory bandwidth and high resistance to radiation.
[資料中心] 例如，可以將本發明的一個實施方式的半導體裝置適用於資料中心等採用的儲存系統。資料中心被要求保證資料不變性等進行資料的長期管理。在進行資料的長期管理時需要使設施大型化，諸如設置用來儲存龐大的資料的儲存及伺服器、確保穩定的電源以保持資料或者確保在資料的保持中需要的冷卻設備等。[Data Center]For example, a semiconductor device according to one embodiment of the present invention can be applied to storage systems used in data centers and the like. Data centers are required to manage data over a long period of time, ensuring data immutability. This long-term data management requires large-scale facilities, such as storage and servers to store large amounts of data, ensuring a stable power supply to maintain data, and ensuring the cooling equipment required to maintain data.
藉由將本發明的一個實施方式的半導體裝置用於資料中心採用的儲存系統，可以實現資料保持所需的功率的降低、保持資料的半導體裝置小型化。因此，可以實現儲存系統的小型化、用來保持資料的電源的小型化、冷卻設備規模的縮小等。由此，可以實現資料中心的省空間。By using a semiconductor device according to one embodiment of the present invention in a storage system employed in a data center, it is possible to reduce the power required to retain data and miniaturize the semiconductor device that retains data. This can lead to smaller storage systems, smaller power supplies for data retention, and smaller cooling equipment. This can also save space in the data center.
此外，本發明的一個實施方式的半導體裝置的功耗低，因此可以降低電路發熱。由此，可以減少因該發熱而給電路本身、週邊電路及模組帶來的負面影響。此外，藉由使用本發明的一個實施方式的半導體裝置，可以實現高溫環境下也穩定工作的資料中心。因此，可以提高資料中心的可靠性。Furthermore, the semiconductor device according to one embodiment of the present invention has low power consumption, thereby reducing circuit heat generation. This reduces the negative impact of this heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device according to one embodiment of the present invention, a data center that operates stably even in high-temperature environments can be realized, thereby improving the reliability of the data center.
圖37E示出可用於資料中心的儲存系統。圖37E所示的儲存系統7010作為主機7001包括多個伺服器7001sb。此外，作為儲存7003包括多個記憶體裝置7003md。示出主機7001和儲存7003藉由儲存區域網路7004及儲存控制電路7002連接的形態。Figure 37E shows a storage system that can be used in a data center. The storage system 7010 shown in Figure 37E includes multiple servers 7001sb as a host 7001 and multiple memory devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.
主機7001相當於訪問儲存在儲存7003中的資料的電腦。主機7001彼此也可以藉由網路連接。Host 7001 is equivalent to a computer that accesses data stored in storage 7003. Hosts 7001 can also be connected to each other via a network.
在儲存7003中，藉由使用快閃記憶體縮短資料的存取速度，即縮短資料的儲存及輸出所需要的時間，但是該時間比可用作儲存中的快取記憶體的DRAM所需要的時間長得多。在儲存系統中，為了解決儲存7003的存取速度較長的問題，一般在儲存中設置快取記憶體來縮短資料的儲存及輸出所需要的時間。In storage 7003, the use of flash memory reduces data access speed, that is, shortens the time required to store and output data. However, this time is much longer than the time required by DRAM, which can be used as cache memory in storage. In storage systems, to solve the problem of the long access speed of storage 7003, cache memory is generally set up in the storage to shorten the time required to store and output data.
在儲存控制電路7002及儲存7003中使用上述快取記憶體。主機7001和儲存7003交換的資料在儲存在儲存控制電路7002及儲存7003中的該快取記憶體之後輸出到主機7001或儲存7003。The cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host computer 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host computer 7001 or the storage 7003.
當作為用來儲存上述快取記憶體的資料的電晶體使用OS電晶體來保持對應於資料的電位時，可以減少更新頻率來降低功耗。此外，藉由層疊記憶單元陣列可以實現小型化。When OS transistors are used as transistors for storing cache data to maintain a potential corresponding to the data, the refresh frequency can be reduced, thereby lowering power consumption. Furthermore, miniaturization can be achieved by stacking memory cell arrays.
[電子裝置] 使用圖38A至圖38F說明可戴在頭上的可穿戴裝置的一個例子。這些可穿戴裝置具有顯示AR內容的功能、顯示VR內容的功能、顯示SR內容的功能和顯示MR內容的功能中的至少一個。當電子裝置具有顯示AR、VR、SR和MR等中的至少一個內容的功能時，可以提高使用者的沉浸感。[Electronic Device]Figures 38A to 38F illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: AR content, VR content, SR content, and MR content. Electronic devices that have the ability to display at least one of AR, VR, SR, and MR content can enhance the user's sense of immersion.
圖38A所示的電子裝置700A包括一對顯示面板751、一對外殼721、通訊部（未圖示）、一對安裝部723、控制部（未圖示）、成像部（未圖示）、一對光學構件753、邊框757以及一對鼻墊758。The electronic device 700A shown in Figure 38A includes a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, a frame 757 and a pair of nose pads 758.
顯示面板751可以應用本發明的一個實施方式的顯示裝置。因此，可以實現能夠進行清晰度極高的顯示的電子裝置。此外，控制部（未圖示）可以使用本發明的一個實施方式的半導體裝置。由此，可以降低電子裝置的功耗。The display panel 751 can employ a display device according to one embodiment of the present invention. This allows for an electronic device capable of displaying extremely high-definition images. Furthermore, the control unit (not shown) can employ a semiconductor device according to one embodiment of the present invention. This reduces the power consumption of the electronic device.
電子裝置700A可以將由顯示面板751顯示的影像投影於光學構件753中的顯示區域756。因為光學構件753具有透光性，所以使用者可以與藉由光學構件753看到的透過影像重疊地看到顯示於顯示區域的影像。因此，電子裝置700A是能夠進行AR顯示的電子裝置。Electronic device 700A can project the image displayed by display panel 751 onto display area 756 within optical component 753. Because optical component 753 is light-transmissive, the user can see the image displayed on the display area superimposed on the image seen through optical component 753. Therefore, electronic device 700A is capable of AR display.
電子裝置700A上作為成像部也可以設置有能夠拍攝前方的照相機。此外，藉由在電子裝置700A上設置陀螺儀感測器等的加速度感測器，可以檢測使用者的頭部的方向並將對應該影像顯示在顯示區域756上。The electronic device 700A may also be provided with a camera capable of capturing images of the front as an imaging unit. Furthermore, by providing an acceleration sensor such as a gyro sensor on the electronic device 700A, the direction of the user's head can be detected and the corresponding image can be displayed on the display area 756.
通訊部具有無線通訊裝置，藉由該無線通訊裝置可以供應影像信號等。此外，代替無線通訊裝置或者除了無線通訊裝置以外還可以包括能夠連接供應影像信號及電源電位的電纜的連接器。The communication unit includes a wireless communication device, through which image signals, etc. can be supplied. In addition, a connector capable of connecting a cable for supplying image signals and power potential may be included instead of or in addition to the wireless communication device.
此外，電子裝置700A設置有電池，可以以無線方式和有線方式中的一者或兩者進行充電。Furthermore, the electronic device 700A is provided with a battery and can be charged wirelessly, wiredly, or both.
外殼721也可以設置有觸控感測器模組。觸控感測器模組具有檢測外殼721的外側的面是否被觸摸的功能。藉由觸控感測器模組，可以檢測使用者的點按操作或滑動操作等而執行各種處理。例如，藉由點按操作可以執行動態影像的暫時停止或再生等的處理，藉由滑動操作可以執行快進、快退等的處理等。此外，藉由在兩個外殼721的每一個設置觸控感測器模組，可以擴大操作範圍。Housing 721 may also be equipped with a touch sensor module. This module detects whether the outer surface of housing 721 is touched. The touch sensor module can detect user taps or slides and perform various operations. For example, a tap can temporarily pause or replay a moving image, while a slide can fast-forward or rewind. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
圖38B所示的電子裝置800A以及圖38C所示的電子裝置800B都包括一對顯示部820、外殼821、通訊部822、一對安裝部823、控制部824、一對成像部825以及一對透鏡832。The electronic device 800A shown in FIG. 38B and the electronic device 800B shown in FIG. 38C both include a pair of display portions 820 , a housing 821 , a communication portion 822 , a pair of mounting portions 823 , a control portion 824 , a pair of imaging portions 825 , and a pair of lenses 832 .
顯示部820可以應用本發明的一個實施方式的顯示裝置。因此，可以實現能夠進行清晰度極高的顯示的電子裝置。由此，使用者可以感受高沉浸感。此外，可以將本發明的一個實施方式的半導體裝置用於控制部824。由此，可以降低電子裝置的功耗。The display unit 820 can employ a display device according to one embodiment of the present invention. This enables an electronic device capable of displaying extremely high-definition images, providing the user with a high sense of immersion. Furthermore, a semiconductor device according to one embodiment of the present invention can be employed in the control unit 824, thereby reducing the electronic device's power consumption.
顯示部820設置在外殼821內部的藉由透鏡832能看到的位置上。此外，藉由在一對顯示部820的每一個上顯示不同影像，可以進行利用視差的三維顯示。The display unit 820 is provided in a position visible through the lens 832 inside the housing 821. In addition, by displaying different images on each of the pair of display units 820, a three-dimensional display utilizing parallax can be performed.
可以將電子裝置800A以及電子裝置800B都稱為面向VR的電子裝置。裝上電子裝置800A或電子裝置800B的使用者藉由透鏡832能看到顯示在顯示部820上的影像。The electronic device 800A and the electronic device 800B can both be referred to as VR-compatible electronic devices. A user wearing the electronic device 800A or 800B can view images displayed on the display unit 820 through the lens 832 .
電子裝置800A及電子裝置800B較佳為具有一種機構，其中能夠調整透鏡832及顯示部820的左右位置，以根據使用者的眼睛的位置使透鏡832及顯示部820位於最合適的位置上。此外，較佳為具有一種機構，其中藉由改變透鏡832及顯示部820之間的距離來調整焦點。Electronic devices 800A and 800B preferably have a mechanism that allows for adjustment of the left and right positions of lens 832 and display 820, thereby locating lens 832 and display 820 in the most appropriate position based on the user's eye position. Furthermore, they preferably have a mechanism that adjusts the focus by changing the distance between lens 832 and display 820.
使用者可以使用安裝部823將電子裝置800A或電子裝置800B裝在頭上。注意，例如在圖38B等中，安裝部823具有如眼鏡的鏡腳（也稱為腳絲等）那樣的形狀，但是不侷限於此。只要使用者能夠裝上，安裝部823就例如可以具有頭盔型或帶型的形狀。The user can use mounting portion 823 to attach electronic device 800A or 800B to their head. Note that, for example, in FIG. 38B , mounting portion 823 has a shape similar to the temples of glasses (also called "wires" or the like), but this is not limiting. Mounting portion 823 may also have a helmet-like or strap-like shape, as long as the user can attach it.
成像部825具有取得外部的資訊的功能。可以將成像部825所取得的資料輸出到顯示部820。在成像部825中可以使用影像感測器。此外，也可以設置多個相機以能夠對應望遠及廣角等多種視角。The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras can be provided to support various viewing angles such as telephoto and wide-angle.
注意，在此示出包括成像部825的例子，設置能夠測量出與對象物的距離的測距感測器（以下，也稱為檢測部）即可。換言之，成像部825是檢測部的一個實施方式。作為檢測部例如可以使用影像感測器或雷射雷達（LIDAR：Light Detection and Ranging）等距離影像感測器。藉由使用由相機取得的影像以及由距離影像感測器取得的影像，可以取得更多的資訊，可以實現精度更高的姿態操作。Note that while this example includes an imaging unit 825, a distance-measuring sensor (hereinafter referred to as a detection unit) capable of measuring the distance to an object may be provided. In other words, the imaging unit 825 is one embodiment of the detection unit. For example, a distance-measuring sensor such as an image sensor or a laser radar (LIDAR) can be used as the detection unit. By utilizing images captured by a camera and a distance-measuring sensor, more information can be obtained, enabling more accurate gesture manipulation.
電子裝置800A也可以包括用作骨傳導耳機的振動機構。例如，作為顯示部820、外殼821和安裝部823中的一個或多個可以採用包括該振動機構的結構。由此，不需要另行設置頭戴式耳機、耳機或揚聲器等音響設備，而只裝上電子裝置800A就可以享受影像和聲音。Electronic device 800A may also include a vibration mechanism for use as a bone conduction earphone. For example, one or more of the display unit 820, housing 821, and mounting unit 823 may include a structure including this vibration mechanism. This eliminates the need for separate audio equipment such as headphones, earphones, or speakers; simply attaching electronic device 800A allows for the enjoyment of both visuals and sound.
電子裝置800A以及電子裝置800B也可以都包括輸入端子。例如可以將供應來自影像輸出設備等的影像信號以及用於對設置在電子裝置內的電池進行充電的電力等的電纜連線到輸入端子。Electronic device 800A and electronic device 800B may also include input terminals. For example, cables for supplying image signals from image output equipment and power for charging batteries installed in the electronic devices may be connected to the input terminals.
本發明的一個實施方式的電子裝置也可以具有與耳機750進行無線通訊的功能。耳機750包括通訊部（未圖示），並具有無線通訊功能。耳機750藉由無線通訊功能可以從電子裝置接收資訊（例如聲音資料）。例如，圖38A所示的電子裝置700A具有藉由無線通訊功能將資訊發送到耳機750的功能。An electronic device according to one embodiment of the present invention may also have the ability to wirelessly communicate with a headset 750. The headset 750 includes a communication unit (not shown) and has wireless communication capabilities. Using this wireless communication capability, the headset 750 can receive information (e.g., audio data) from the electronic device. For example, the electronic device 700A shown in FIG38A has the ability to transmit information to the headset 750 via wireless communication.
此外，電子裝置也可以包括耳機部。圖38C所示的電子裝置800B包括耳機部827。例如，可以採用以有線方式連接耳機部827和控制部824的結構。連接耳機部827和控制部824的佈線的一部分也可以配置在外殼821或安裝部823的內部。此外，耳機部827和安裝部823也可以包括磁鐵。由此，可以用磁力將耳機部827固定到安裝部823，收納變得容易，所以是較佳的。Furthermore, the electronic device may also include an earphone unit. Electronic device 800B shown in FIG38C includes an earphone unit 827. For example, a structure may be employed in which the earphone unit 827 and the control unit 824 are connected by wire. A portion of the wiring connecting the earphone unit 827 and the control unit 824 may be located within the housing 821 or the mounting portion 823. Furthermore, the earphone unit 827 and the mounting portion 823 may include magnets. This allows the earphone unit 827 to be magnetically secured to the mounting portion 823, making storage easier and therefore preferable.
電子裝置也可以包括能夠與耳機或頭戴式耳機等連接的聲音輸出端子。此外，電子裝置也可以包括聲音輸入端子和聲音輸入機構中的一者或兩者。作為聲音輸入機構，例如可以使用麥克風等收音裝置。藉由將聲音輸入機構設置到電子裝置，可以使電子裝置具有所謂的耳麥的功能。The electronic device may also include an audio output terminal capable of connecting to earphones or headphones. Furthermore, the electronic device may include one or both of an audio input terminal and an audio input mechanism. For example, a microphone or other sound receiving device may be used as the audio input mechanism. By incorporating the audio input mechanism into the electronic device, the electronic device can be given the functionality of a headset.
圖38D及圖38E是VR用護目鏡型電子裝置850A的立體圖。圖38D及圖38E示出外殼845內分別包括彎曲的一對顯示裝置840（顯示裝置840_R及顯示裝置840_L）的例子。電子裝置850A包括運動檢測部841、視線檢測部842、運算部843、通訊部844、透鏡848、操作按鈕851、安裝工具854、感測器855以及刻度盤856等。Figures 38D and 38E are perspective views of a VR goggle-type electronic device 850A. Figures 38D and 38E illustrate an example in which a pair of curved display devices 840 (display device 840_R and display device 840_L) are housed within a housing 845. Electronic device 850A includes a motion detection unit 841, a line of sight detection unit 842, a calculation unit 843, a communication unit 844, a lens 848, operation buttons 851, an installation tool 854, a sensor 855, and a dial 856.
由於包括兩個顯示裝置840，使用者的雙眼可以分別看兩個顯示裝置。由此，在用視差進行三維顯示等的情況下，也可以顯示高解析度影像。此外，顯示裝置840彎曲為以使用者的眼睛大致為中心的圓弧狀。由此，從使用者的眼睛到顯示部的顯示面的距離固定，因此使用者可以看更自然的影像。此外，即使顯示裝置840具有光的亮度或色度根據所看的角度而變化的所謂的視角依賴性，也可以採用使用者的眼睛在顯示裝置840的顯示面的法線方向上的結構，由此尤其是在水平方向上實質上可以忽略其影響，所以可以顯示更有現實感的影像。Since two display devices 840 are included, the user's eyes can view the two display devices separately. This allows high-resolution images to be displayed even when using parallax for three-dimensional display. In addition, the display device 840 is curved into an arc shape with the user's eyes roughly as the center. As a result, the distance from the user's eyes to the display surface of the display unit is fixed, so the user can view more natural images. In addition, even if the display device 840 has so-called viewing angle dependence, in which the brightness or chromaticity of light changes depending on the viewing angle, the user's eyes can be arranged in the normal direction of the display surface of the display device 840. As a result, the influence of this effect can be substantially ignored, especially in the horizontal direction, so that more realistic images can be displayed.
如圖38E所示，透鏡848位於顯示裝置840與使用者的眼睛之間。圖38E示出包括為了調節視度而改變透鏡位置的刻度盤856的例子。此外，在電子裝置850A具有自動聚焦功能的情況下，也可以不包括用來調節視度的刻度盤856。As shown in FIG38E , lens 848 is positioned between display device 840 and the user's eye. FIG38E shows an example of including a dial 856 for adjusting the lens position to adjust the diopter. Alternatively, if electronic device 850A has an autofocus function, dial 856 for adjusting the diopter may not be included.
圖38F示出包括一個顯示裝置840的護目鏡型電子裝置850B。藉由採用上述結構，可以減少構件數。38F shows a goggle-type electronic device 850B including a display device 840. By adopting the above structure, the number of components can be reduced.
顯示裝置840在左右兩個區域中分別並排顯示右眼用影像和左眼用影像的兩個影像。由此可以顯示利用兩眼視差的立體影像。在顯示裝置840上，既可並排顯示利用視差的兩個不同的影像，又可不利用視差而並排顯示兩個相同的影像。Display device 840 displays two images, one for the right eye and one for the left eye, side by side in the left and right areas, respectively. This allows for a stereoscopic image that utilizes binocular parallax. Display device 840 can display two different images side by side using parallax, or it can display two identical images side by side without using parallax.
此外，也可以在顯示裝置840的整個區域顯示可用兩個眼睛看的一個影像。由此，可以顯示跨視野的兩端的全景影像，因此現實感得到提高。Alternatively, a single image that can be viewed with both eyes may be displayed across the entire area of the display device 840. This allows a panoramic image spanning both ends of the visual field to be displayed, thereby enhancing the sense of reality.
可以對顯示裝置840應用本發明的一個實施方式的顯示裝置。因為本發明的一個實施方式的顯示裝置具有極高的清晰度，所以即使使用透鏡848放大影像，也可以不使使用者看到像素而可以顯示真實感更高的影像。The display device of one embodiment of the present invention can be applied to the display device 840. Since the display device of one embodiment of the present invention has extremely high definition, even when the lens 848 is used to magnify the image, the user does not see pixels and a more realistic image can be displayed.
圖39A所示的電子裝置6500是可以用作智慧手機的可攜式資訊終端設備。The electronic device 6500 shown in FIG39A is a portable information terminal device that can be used as a smartphone.
電子裝置6500包括外殼6501、顯示部6502、電源按鈕6503、按鈕6504、揚聲器6505、麥克風6506、相機6507、光源6508及控制裝置6509等。The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509.
圖39B所示的電子裝置6520是可以用作平板終端的可攜式資訊終端設備。The electronic device 6520 shown in FIG39B is a portable information terminal device that can be used as a tablet terminal.
電子裝置6520包括外殼6501、顯示部6502、按鈕6504、揚聲器6505、麥克風6506、相機6507、控制裝置6509及連接端子6519等。The electronic device 6520 includes a housing 6501, a display portion 6502, buttons 6504, a speaker 6505, a microphone 6506, a camera 6507, a control device 6509, and connection terminals 6519.
在電子裝置6500及電子裝置6520中，顯示部6502都具有觸控面板功能。此外，控制裝置6509例如包括選自CPU、GPU及記憶體裝置中的一個或多個。本發明的一個實施方式的半導體裝置可用於顯示部6502及控制裝置6509中的一者或兩者。In both electronic devices 6500 and 6520, the display unit 6502 has a touch panel function. Furthermore, the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. A semiconductor device according to one embodiment of the present invention can be used for one or both of the display unit 6502 and the control device 6509.
圖39C是電子裝置6500及電子裝置6520中的外殼6501的包括麥克風6506一側的端部的剖面示意圖。FIG39C is a schematic cross-sectional view of the end portion of the housing 6501 in the electronic device 6500 and the electronic device 6520, including the side with the microphone 6506.
外殼6501的顯示面一側設置有具有透光性的保護構件6510，被外殼6501及保護構件6510圍繞的空間內配置有顯示面板6511、光學構件6512、觸控感測器面板6513、印刷電路板6517以及電池6518等。A light-transmitting protective member 6510 is provided on the display side of the housing 6501. The space surrounded by the housing 6501 and the protective member 6510 contains a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, and a battery 6518.
顯示面板6511、光學構件6512及觸控感測器面板6513使用黏合層（未圖示）固定到保護構件6510。The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).
在顯示部6502的外側的區域中，顯示面板6511的一部分疊回，且該疊回部分連接有FPC6515。FPC6515安裝有IC6516。FPC6515與設置於印刷電路板6517的端子連接。In an area outside the display portion 6502, a portion of the display panel 6511 is stacked, and an FPC 6515 is connected to the stacked portion. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on a printed circuit board 6517.
顯示面板6511可以使用本發明的一個實施方式的顯示裝置。由此，可以實現極輕量的電子裝置。此外，由於顯示面板6511極薄，所以可以在抑制電子裝置的厚度的情況下安裝大容量的電池6518。此外，藉由折疊顯示面板6511的一部分以在像素部的背面設置與FPC6515的連接部，可以實現窄邊框的電子裝置。The display panel 6511 can use a display device according to one embodiment of the present invention. This allows for an extremely lightweight electronic device. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while minimizing the thickness of the electronic device. Furthermore, by folding a portion of the display panel 6511 to provide a connection to the FPC 6515 on the back of the pixel portion, a narrow-frame electronic device can be achieved.
圖39D示出電視機的一個例子。在電視機7100中，外殼7101中組裝有顯示部7000。在此示出利用支架7103支撐外殼7101的結構。39D shows an example of a television set. In a television set 7100, a display portion 7000 is incorporated into a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.
顯示部7000可以使用本發明的一個實施方式的顯示裝置。The display portion 7000 can use a display device according to an embodiment of the present invention.
可以藉由利用外殼7101所具有的操作開關以及另外提供的遙控器7111進行圖39D所示的電視機7100的操作。或者，也可以在顯示部7000中具有觸控感測器，也可以藉由用指頭等觸摸顯示部7000進行電視機7100的操作。此外，也可以在遙控器7111中具有顯示從遙控器7111輸出的資料的顯示部。藉由利用遙控器7111所具有的操作鍵或觸控面板，可以進行頻道及音量的操作，並可以對顯示在顯示部7000上的影像進行操作。Television set 7100 shown in FIG39D can be operated using the operation switches included in housing 7101 and a separately provided remote control 7111. Alternatively, display unit 7000 may include a touch sensor, allowing operation of television set 7100 by touching display unit 7000 with a finger or the like. Furthermore, remote control 7111 may include a display unit for displaying data output from remote control 7111. Using the operation keys or touch panel included in remote control 7111, channel and volume control can be performed, and images displayed on display unit 7000 can be manipulated.
此外，電視機7100具有接收機及數據機等。可以藉由利用接收機接收一般的電視廣播。再者，藉由數據機連接到有線或無線方式的通訊網路，從而進行單向（從發送者到接收者）或雙向（發送者和接收者之間或接收者之間等）的資訊通訊。Television 7100 also includes a receiver and a modem. The receiver can receive standard television broadcasts. Furthermore, the modem connects to a wired or wireless communication network, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) communication.
圖39E示出筆記本型電腦的一個例子。筆記本型電腦7200包括外殼7211、鍵盤7212、指向裝置7213、外部連接埠7214及控制裝置7215等。外殼7211中組裝有顯示部7000。控制裝置7215例如包括選自CPU、GPU及記憶體裝置中的一個或多個。本發明的一個實施方式的半導體裝置可用於顯示部7000及控制裝置7215中的一者或兩者。FIG39E illustrates an example of a laptop computer. Laptop computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and a control device 7215. Housing 7211 incorporates display unit 7000. Control device 7215 includes, for example, one or more components selected from a CPU, a GPU, and a memory device. A semiconductor device according to an embodiment of the present invention may be used for either or both of display unit 7000 and control device 7215.
圖39F和圖39G示出數位看板的一個例子。Figures 39F and 39G show an example of a digital signage.
圖39F所示的數位看板7300包括外殼7301、顯示部7000及揚聲器7303等。此外，還可以包括LED燈、操作鍵（包括電源開關或操作開關）、連接端子、各種感測器、麥克風等。The digital signage 7300 shown in FIG39F includes a housing 7301, a display unit 7000, and a speaker 7303. Furthermore, it may include LED lights, operating keys (including a power switch or an operating switch), connection terminals, various sensors, a microphone, and the like.
圖39G示出設置於圓柱狀柱子7401上的數位看板7400。數位看板7400包括沿著柱子7401的曲面設置的顯示部7000。FIG39G shows a digital signage 7400 mounted on a cylindrical pillar 7401. The digital signage 7400 includes a display portion 7000 disposed along the curved surface of the pillar 7401.
在圖39F和圖39G中，可以將本發明的一個實施方式的顯示裝置用於顯示部7000。In Figures 39F and 39G, a display device according to an embodiment of the present invention can be used for the display portion 7000.
顯示部7000越大，一次能夠提供的資訊量越多。顯示部7000越大，越容易吸引人的注意，例如可以提高廣告宣傳效果。The larger the display unit 7000 is, the more information it can provide at one time. The larger the display unit 7000 is, the easier it is to attract people's attention, for example, it can improve the effectiveness of advertising.
藉由將觸控面板用於顯示部7000，不僅可以在顯示部7000上顯示靜態影像或動態影像，使用者還能夠直覺性地進行操作，所以是較佳的。此外，在用於提供路線資訊或交通資訊等資訊的用途時，可以藉由直覺性的操作提高易用性。Using a touch panel for display portion 7000 is advantageous because it not only allows for displaying still or moving images on display portion 7000 but also allows for intuitive user operation. Furthermore, when used to provide information such as route information or traffic information, intuitive operation improves usability.
如圖39F和圖39G所示，數位看板7300或數位看板7400較佳為可以藉由無線通訊與使用者所攜帶的智慧手機等資訊終端設備7311或資訊終端設備7411聯動。例如，顯示在顯示部7000上的廣告資訊可以顯示在資訊終端設備7311或資訊終端設備7411的螢幕上。此外，藉由操作資訊終端設備7311或資訊終端設備7411，可以切換顯示部7000的顯示。As shown in Figures 39F and 39G , digital signage 7300 or 7400 can preferably communicate wirelessly with a user's information terminal device 7311 or 7411, such as a smartphone. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or 7411. Furthermore, the display on display unit 7000 can be switched by operating information terminal device 7311 or 7411.
此外，可以在數位看板7300或數位看板7400上以資訊終端設備7311或資訊終端設備7411的螢幕為操作單元（控制器）執行遊戲。由此，不特定多個使用者可以同時參加遊戲，享受遊戲的樂趣。Furthermore, the game can be played on the digital signage 7300 or 7400 using the screen of the information terminal device 7311 or 7411 as an operating unit (controller). This allows an unspecified number of users to participate in the game and enjoy the fun of the game simultaneously.
此外，本發明的一個實施方式的半導體裝置及顯示裝置可以應用於作為移動體的汽車的駕駛座位周邊。Furthermore, the semiconductor device and display device according to one embodiment of the present invention can be applied to the periphery of a driver's seat of a car as a mobile object.
圖40A是示出汽車室內的前擋風玻璃附近的圖。圖40A示出安裝在儀表板上的顯示面板9001a、顯示面板9001b、顯示面板9001c及安裝在支柱上的顯示面板9001d。Fig. 40A shows the vicinity of the front windshield in a car interior. Fig. 40A shows display panel 9001a, display panel 9001b, and display panel 9001c mounted on the instrument panel, and display panel 9001d mounted on a pillar.
顯示面板9001a至顯示面板9001c藉由顯示導航資訊、速度表、轉速計、行駛距離、燃料表、排檔狀態或空調的設定等，可以提供各種資訊。此外，使用者可以根據喜好適當地改變顯示面板所顯示的顯示內容及佈局，可以提高設計性。顯示面板9001a至顯示面板9001c還可以被用作照明設備。Display panels 9001a through 9001c can provide a variety of information by displaying navigation information, a speedometer, a tachometer, distance traveled, a fuel gauge, gear status, and air conditioning settings. Furthermore, users can customize the display content and layout of the display panels to enhance design. Display panels 9001a through 9001c can also function as lighting.
藉由將由設置在車體的攝像單元拍攝的影像顯示在顯示面板9001d上，可以補充被支柱遮擋的視野（死角）。也就是說，藉由顯示由設置在汽車外側的攝像單元拍攝的影像，可以補充死角，從而可以提高安全性。此外，藉由顯示彌補看不到的部分的影像，可以更自然且更舒適地確認安全。顯示面板9001d還可以被用作照明設備。By displaying images captured by a vehicle-mounted camera on display panel 9001d, it is possible to fill in blind spots blocked by pillars. In other words, by displaying images captured by a camera mounted on the vehicle's exterior, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that fill in unseen areas, safety confirmation is made more natural and comfortable. Display panel 9001d can also be used as a lighting device.
圖40B是示出手錶型可攜式資訊終端9200的立體圖。可以將可攜式資訊終端9200例如用作智慧手錶（註冊商標）。此外，顯示部9001的顯示面彎曲，可沿著其彎曲的顯示面進行顯示。此外，可攜式資訊終端9200例如藉由與可進行無線通訊的耳麥相互通訊可以進行免提通話。此外，藉由利用連接端子9006，可攜式資訊終端9200可以與其他資訊終端進行資料傳輸或進行充電。充電也可以藉由無線供電進行。Figure 40B is a perspective view of a watch-type portable information terminal 9200. Portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Furthermore, the display surface of display portion 9001 is curved, enabling display along the curved display surface. Furthermore, portable information terminal 9200 can communicate with a headset capable of wireless communication, for example, for hands-free conversations. Furthermore, by utilizing connection terminal 9006, portable information terminal 9200 can transmit data with other information terminals and charge the device. Charging can also be performed via wireless power supply.
圖40B所示的可攜式資訊終端9200包括外殼9000、顯示部9001、揚聲器9003、操作鍵9005（包括電源開關或操作開關）、連接端子9006、感測器9007（該感測器具有檢測、檢出或測量如下因素的功能：力、位移、位置、速度、加速度、角速度、轉速、距離、光、液、磁、溫度、化學物質、聲音、時間、硬度、電場、電流、電壓、電力、輻射線、流量、濕度、傾斜度、振動、氣味或紅外線）、麥克風9008等。The portable information terminal 9200 shown in FIG40B includes a housing 9000, a display portion 9001, a speaker 9003, operating keys 9005 (including a power switch or an operating switch), a connection terminal 9006, a sensor 9007 (the sensor has the function of detecting, detecting or measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared), a microphone 9008, etc.
圖40C是示出能夠折疊的可攜式資訊終端9201的立體圖。可攜式資訊終端9201包括外殼9000a、外殼9000b、顯示部9001及操作按鈕9056。40C is a perspective view showing a foldable portable information terminal 9201. The portable information terminal 9201 includes a housing 9000a, a housing 9000b, a display portion 9001, and operation buttons 9056.
外殼9000a和外殼9000b由鉸鏈9055彼此鍵合，並且可以由鉸鏈9055對折。Housing 9000a and housing 9000b are keyed to each other by hinge 9055 and can be folded in half by hinge 9055.
可攜式資訊終端9201所包括的顯示部9001被由鉸鏈9055連結的兩個外殼（外殼9000a及外殼9000b）支撐。The portable information terminal 9201 includes a display portion 9001 supported by two housings (housing 9000a and housing 9000b) connected by a hinge 9055.
圖40D至圖40F是示出可以折疊的可攜式資訊終端9202的立體圖。此外，圖40D是將可攜式資訊終端9202展開的狀態的立體圖、圖40F是折疊的狀態的立體圖、圖40E是從圖40D的狀態和圖40F的狀態中的一個轉換成另一個時中途的狀態的立體圖。如此，可以將可攜式資訊終端9202三折。Figures 40D to 40F are three-dimensional diagrams showing a foldable portable information terminal 9202. Figure 40D shows the portable information terminal 9202 unfolded, Figure 40F shows it folded, and Figure 40E shows it midway through transitioning from one of Figures 40D and 40F. In this manner, the portable information terminal 9202 can be folded into three parts.
可攜式資訊終端9202所包括的顯示部9001被由鉸鏈9055連結的三個外殼9000支撐。The display portion 9001 included in the portable information terminal 9202 is supported by three housings 9000 connected by hinges 9055.
在圖40C至圖40F中，可以將本發明的一個實施方式的顯示裝置用於顯示部9001。顯示部9001例如可以在曲率半徑0.1mm以上且150mm以下的範圍彎曲。40C to 40F , the display device according to one embodiment of the present invention can be used for a display portion 9001. The display portion 9001 can be bent within a curvature radius of, for example, 0.1 mm to 150 mm.
可攜式資訊終端9201及可攜式資訊終端9202在折疊狀態下可攜性好，而在展開狀態下因為具有無縫拼接較大的顯示區域所以顯示的瀏覽性強。Portable information terminal 9201 and portable information terminal 9202 are highly portable when folded, and offer enhanced browsability when unfolded due to their seamlessly connected, larger display area.
注意，藉由將本發明的一個實施方式的半導體裝置用於選自電子構件、大型電腦、太空設備、資料中心和電子裝置中的一個或多個，可以降低功耗。因此，目前被認為隨著半導體裝置的高性能化或高積體化能量需求增加，藉由使用本發明的一個實施方式的半導體裝置，也可以減少以二氧化碳（CO2）為代表的溫室氣體的排放量。此外，本發明的一個實施方式的半導體裝置具有低功耗，因此作為全球暖化的措施也有效。Note that by using a semiconductor device according to an embodiment of the present invention in one or more of electronic components, mainframe computers, space equipment, data centers, and electronic devices, power consumption can be reduced. Therefore, as energy demand increases with the performance and integration of semiconductor devices, the use of a semiconductor device according to an embodiment of the present invention is expected to reduce greenhouse gas emissions, including carbon dioxide (CO2 ). Furthermore, due to its low power consumption, the semiconductor device according to an embodiment of the present invention is also effective as a measure to combat global warming.
本實施方式可以與其他實施方式適當地組合。此外，在本說明書中，在一個實施方式中示出多個結構例子的情況下，可以適當地組合該結構例子。 實施例1This embodiment can be combined with other embodiments as appropriate. Furthermore, in this specification, when multiple structural examples are shown in a single embodiment, those structural examples can be combined as appropriate.Example 1
在本實施例中，對沉積在矽基板上的氧化物半導體膜進行濕蝕刻處理，來比較蝕刻速率。In this embodiment, an oxide semiconductor film deposited on a silicon substrate was wet-etched to compare etching rates.
首先，說明本實施例的樣品1A至樣品1C的製造方法。First, the manufacturing method of samples 1A to 1C of this embodiment is described.
首先，在樣品1A至樣品1C中，在矽基板上沉積氧化物半導體膜。在樣品1A中，作為氧化物半導體膜，使用以In：Ga：Zn=1：1：1.2[原子數比]的氧化物靶材沉積的In-Ga-Zn氧化物膜（記為IGZO（111.2）膜）。此外，在樣品1B中，作為氧化物半導體膜，使用利用ALD法以In：Ga：Zn=1：1：1[原子數比]沉積的In-Ga-Zn氧化物膜（記為IGZO（111）膜）。此外，在樣品1C中，作為氧化物半導體膜，使用利用ALD法沉積的銦氧化物膜（記為InOx膜）。First, in samples 1A to 1C, oxide semiconductor films were deposited on a silicon substrate. In sample 1A, an In-Ga-Zn oxide film (referred to as an IGZO (111.2) film) deposited using an oxide target with an In:Ga:Zn ratio of 1:1:1.2 was used as the oxide semiconductor film. Furthermore, in sample 1B, an In-Ga-Zn oxide film (referred to as an IGZO (111) film) deposited using the ALD method with an In:Ga:Zn ratio of 1:1:1 was used as the oxide semiconductor film. Furthermore, in sample 1C, an indium oxide film (referred to as an InOx film) was deposited using the ALD method as the oxide semiconductor film.
利用濺射法沉積其厚度為15nm的IGZO（111.2）膜。沉積條件為如下：作為沉積氣體使用10sccm的Ar氣體及90sccm的O2氣體；壓力為0.5Pa；用RF電源將沉積功率設為2000W；基板溫度為250℃。A 15nm thick IGZO (111.2) film was deposited using sputtering. Deposition conditions were as follows: 10sccm of Ar and 90sccm ofO₂ as the deposition gas; a pressure of 0.5Pa; an RF power source set to 2000W; and a substrate temperature of 250°C.
利用ALD法沉積其厚度為20nm的IGZO（111）膜。在利用ALD法沉積時，作為前驅物使用三乙基銦、三乙基鎵及二乙基鋅。此外，作為氧化劑使用臭氧氣體及氧氣體。在此，將基板溫度設為200℃。An IGZO (111) film with a thickness of 20 nm was deposited using the ALD method. Triethylindium, triethylgallium, and diethylzinc were used as precursors during the ALD deposition process. Ozone gas and oxygen gas were used as oxidants. The substrate temperature was set to 200°C.
利用ALD法沉積其厚度為20nm的InOx膜。在利用ALD法沉積時，作為前驅物使用三乙基銦，作為氧化劑使用臭氧氣體及氧氣體。在此，將基板溫度設為200℃。A 20nm thick InOx film was deposited using ALD. Triethylindium was used as a precursor, and ozone and oxygen gases were used as oxidants. The substrate temperature was set at 200°C.
接著，使用由碳酸水稀釋氫氟酸而成的水溶液（以下，稱為稀氫氟酸）對樣品1A至樣品1C進行濕蝕刻處理。在此，作為稀氫氟酸的濃度採用7ppm左右、10ppm左右、23ppm左右及52ppm左右這四個條件。在使1.5MHz的超聲波作用於稀氫氟酸的狀態下進行30秒的濕蝕刻處理。Next, samples 1A through 1C were wet-etched using an aqueous solution of hydrofluoric acid diluted with carbonated water (hereinafter referred to as dilute hydrofluoric acid). Four dilute hydrofluoric acid concentrations were used: approximately 7 ppm, approximately 10 ppm, approximately 23 ppm, and approximately 52 ppm. The wet-etching process was performed for 30 seconds while applying 1.5 MHz ultrasonic waves to the dilute hydrofluoric acid.
根據在濕蝕刻處理前後的樣品1A至樣品1C的氧化物半導體膜的厚度的差異，算出濕蝕刻處理的蝕刻速率。圖41示出樣品1A至樣品1C的蝕刻速率。在圖41中，橫軸表示各樣品的濕蝕刻條件，縱軸表示蝕刻速率[nm/分]。The etching rate of the wet etching process was calculated based on the difference in thickness of the oxide semiconductor film of Samples 1A to 1C before and after the wet etching process. Figure 41 shows the etching rates of Samples 1A to 1C. In Figure 41, the horizontal axis represents the wet etching conditions for each sample, and the vertical axis represents the etching rate [nm/min].
如圖41所示，樣品1C的InOx膜的蝕刻速率極低，由此可知InOx膜是緻密且堅固的膜。藉由將InOx膜用作氧化物半導體膜，即使對氧化物半導體膜進行使用稀氫氟酸的洗滌處理，也可以防止氧化物半導體膜過度被蝕刻。因此，可以以高精度加工氧化物半導體膜，來製造具有微型結構的半導體裝置。As shown in Figure 41, the etching rate of the InOx film in sample 1C is extremely low, demonstrating its dense and robust nature. Using an InOx film as the oxide semiconductor film prevents excessive etching of the oxide semiconductor film even when it is cleaned with dilute hydrofluoric acid. Consequently, the oxide semiconductor film can be processed with high precision, enabling the fabrication of semiconductor devices with microstructures.
本實施例可以與實施方式及其他實施例適當地組合。 實施例2This embodiment can be appropriately combined with the embodiments and other embodiments.Example 2
在本實施例中，製造包括電晶體的樣品並對該電晶體進行EDX線分析。In this embodiment, a sample including a transistor is manufactured and EDX line analysis is performed on the transistor.
[樣品的製造] 作為半導體裝置，製造樣品2。圖42示出樣品2所包括的電晶體200的結構。樣品2所包括的電晶體200與圖4A所示的電晶體的不同之處在於：在前者中，氧化物半導體層230具有三層結構。[Sample Fabrication]Sample 2 was fabricated as a semiconductor device. Figure 42 shows the structure of transistor 200 included in Sample 2. Transistor 200 included in Sample 2 differs from the transistor shown in Figure 4A in that, in the former, oxide semiconductor layer 230 has a three-layer structure.
在絕緣層210上利用濺射法沉積其厚度為5nm的氮化鈦膜，接著利用濺射法沉積其厚度為20nm的鎢膜，然後利用濺射法沉積其厚度為20nm的ITSO膜，並且對由氮化鈦膜、鎢膜及ITSO膜構成的疊層膜進行加工，由此形成導電層220。也就是說，導電層220具有氮化鈦膜、該氮化鈦膜上的鎢膜以及該鎢膜上的ITSO膜的疊層結構。另外，氮化鈦膜相當於導電層220_11，鎢膜相當於導電層220_12，ITSO膜相當於導電層220_2。A 5nm-thick titanium nitride film is sputter-deposited on insulating layer 210, followed by a 20nm-thick tungsten film. Finally, a 20nm-thick ITSO film is sputter-deposited. The stacked film consisting of the titanium nitride, tungsten, and ITSO films is then processed to form conductive layer 220. In other words, conductive layer 220 has a stacked structure consisting of a titanium nitride film, a tungsten film on the titanium nitride film, and an ITSO film on the tungsten film. The titanium nitride film corresponds to conductive layer 220_11, the tungsten film corresponds to conductive layer 220_12, and the ITSO film corresponds to conductive layer 220_2.
接著，利用PEALD法沉積其厚度為5nm的第一氮化矽膜。接著，利用濺射法沉積其厚度為135nm的氧化矽膜，然後在該氧化矽膜上利用濺射法沉積其厚度為100nm的第二氮化矽膜，並且對其進行CMP處理來去除第二氮化矽膜，由此使氧化矽膜的頂面平坦化。藉由進行該CMP處理，形成導電層220上的其厚度為80nm的氧化矽膜。接著，利用濺射法沉積其厚度為10nm的第三氮化矽膜。由此，形成絕緣層280。也就是說，絕緣層280具有第一氮化矽膜、第一氮化矽膜上的氧化矽膜以及該氧化矽膜上的第三氮化矽膜的疊層結構。另外，第一氮化矽膜相當於絕緣層280_1，氧化矽膜相當於絕緣層280_2，第三氮化矽膜相當於絕緣層280_3。Next, a first silicon nitride film with a thickness of 5 nm is deposited using the PEALD method. A silicon oxide film with a thickness of 135 nm is then deposited using the sputtering method. A second silicon nitride film with a thickness of 100 nm is then deposited on this silicon oxide film using the sputtering method. This second silicon nitride film is then removed using a CMP process, thereby flattening the top surface of the silicon oxide film. This CMP process forms an 80 nm thick silicon oxide film on the conductive layer 220. Next, a third silicon nitride film with a thickness of 10 nm is deposited using the sputtering method. This forms the insulating layer 280. In other words, insulating layer 280 has a stacked structure of a first silicon nitride film, a silicon oxide film on the first silicon nitride film, and a third silicon nitride film on the silicon oxide film. The first silicon nitride film corresponds to insulating layer 280_1, the silicon oxide film corresponds to insulating layer 280_2, and the third silicon nitride film corresponds to insulating layer 280_3.
接著，使用利用濺射法沉積的其厚度為15nm的鎢膜形成導電層240_1，並且使用利用濺射法沉積的其厚度為10nm的ITSO膜形成導電層240_2。Next, the conductive layer 240_1 is formed using a tungsten film deposited by sputtering to a thickness of 15 nm, and the conductive layer 240_2 is formed using an ITSO film deposited by sputtering to a thickness of 10 nm.
接著，利用乾蝕刻法形成開口部290。Next, the opening 290 is formed by dry etching.
接著，使用利用熱ALD法沉積的其厚度為0.5nm的氧化鎵膜形成氧化物層227。作為包含鎵的前驅物使用三乙基鎵，作為氧化劑使用臭氧（O3）及氧（O2）。將基板加熱的溫度設為200℃。Next, a 0.5 nm thick gallium oxide film was deposited by thermal ALD to form an oxide layer 227. Triethyl gallium was used as a precursor containing gallium, and ozone (O3 ) and oxygen (O2 ) were used as oxidants. The substrate was heated at a temperature of 200°C.
然後，使用其厚度為2nm的第一層、第一層上的其厚度為5nm的第二層以及第二層上的其厚度為3nm的第三層的疊層膜形成氧化物半導體層230。第一層對應於圖42所示的氧化物半導體層230_1，第二層對應於圖42所示的氧化物半導體層230_2，第三層對應於圖42所示的氧化物半導體層230_3。Then, an oxide semiconductor layer 230 is formed using a stacked film of a first layer having a thickness of 2 nm, a second layer having a thickness of 5 nm on the first layer, and a third layer having a thickness of 3 nm on the second layer. The first layer corresponds to the oxide semiconductor layer 230_1 shown in FIG42, the second layer corresponds to the oxide semiconductor layer 230_2 shown in FIG42, and the third layer corresponds to the oxide semiconductor layer 230_3 shown in FIG42.
作為氧化物半導體層230的第一層及第三層，利用熱ALD法沉積銦鋅氧化物膜。作為包含銦的前驅物使用三乙基銦，作為包含鋅的前驅物使用二乙基鋅。另外，作為氧化劑使用臭氧（O3）及氧（O2）。將基板加熱的溫度設為200℃。Indium-zinc oxide films were deposited as the first and third layers of the oxide semiconductor layer 230 using thermal ALD. Triethylindium was used as a precursor containing indium, and diethylzinc was used as a precursor containing zinc. Ozone (O₃ ) and oxygen (O₂ ) were used as oxidants. The substrate was heated to 200°C.
作為氧化物半導體層230的第二層，利用RF濺射法沉積In-Sn-Zn氧化物膜。注意，在沉積第二層時，使用In：Sn：Zn=4：0.1：1[原子數比]的氧化物靶材。作為沉積氣體使用氧及氬，將相對於氧及氬的流量總和的氧流量比設為10%。另外，將基板加熱的溫度設為250℃。As the second layer of the oxide semiconductor layer 230, an In-Sn-Zn oxide film was deposited using RF sputtering. Note that an oxide target with an atomic ratio of In:Sn:Zn = 4:0.1:1 was used for the deposition of the second layer. Oxygen and argon were used as the deposition gases, with the oxygen flow rate ratio set to 10% relative to the total flow rate of oxygen and argon. The substrate was heated to 250°C.
接著，使用由第四絕緣層、第四絕緣層上的第三絕緣層、第三絕緣層上的第一絕緣層以及第一絕緣層上的第二絕緣層構成的疊層膜形成絕緣層250。Next, the insulating layer 250 is formed using a laminated film composed of a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.
在絕緣層250中，作為第四絕緣層，利用熱ALD法沉積其厚度為1nm的氧化鋁膜。作為前驅物使用三甲基鋁。作為氧化劑使用臭氧。將基板加熱的溫度設為300℃。另外，作為第三絕緣層，利用PEALD法沉積其厚度為2nm的氧化矽膜。作為前驅物使用胺基矽烷化合物。作為氧化劑使用氧，並進行氬電漿處理。將基板加熱的溫度設為350℃。另外，作為第一絕緣層，利用熱ALD法沉積其厚度為2nm的氧化鉿膜。作為前驅物使用四氯化鉿。作為氧化劑使用臭氧。將基板加熱的溫度設為250℃。另外，作為第二絕緣層，利用PEALD法沉積其厚度為1nm的氮化矽膜。將基板加熱的溫度設為400℃。In insulating layer 250, a 1 nm thick aluminum oxide film was deposited as the fourth insulating layer using a thermal ALD method. Trimethylaluminum was used as a precursor. Ozone was used as an oxidizing agent. The substrate was heated at a temperature of 300°C. Furthermore, a 2 nm thick silicon oxide film was deposited as the third insulating layer using a PEALD method. An aminosilane compound was used as a precursor. Oxygen was used as an oxidizing agent, and an argon plasma treatment was performed. The substrate was heated at a temperature of 350°C. Furthermore, a 2 nm thick cobalt oxide film was deposited as the first insulating layer using a thermal ALD method. Cobalt tetrachloride was used as a precursor. Ozone was used as an oxidizing agent. The substrate was heated at 250°C. A 1nm-thick silicon nitride film was deposited as a second insulating layer using PEALD. The substrate was heated at 400°C.
接著，使用由利用CVD法沉積的其厚度為5nm的氮化鈦膜和利用CVD法沉積的其厚度為20nm的鎢膜構成的疊層膜形成導電層260。也就是說，導電層260具有氮化鈦膜及該氮化鈦膜上的鎢膜的疊層結構。另外，氮化鈦膜相當於導電層260_1，鎢膜相當於導電層260_2。Next, conductive layer 260 is formed using a stacked film composed of a 5nm thick titanium nitride film deposited by CVD and a 20nm thick tungsten film deposited by CVD. In other words, conductive layer 260 has a stacked structure of a titanium nitride film and a tungsten film on the titanium nitride film. The titanium nitride film corresponds to conductive layer 260_1, and the tungsten film corresponds to conductive layer 260_2.
接著，利用PEALD法沉積其厚度為5nm的氮化矽膜。氮化矽膜相當於絕緣層283。Next, a silicon nitride film with a thickness of 5 nm is deposited using the PEALD method. The silicon nitride film serves as the insulating layer 283.
如此，製造包括電晶體的樣品2。In this way, a sample 2 including a transistor was manufactured.
[EDX分析] 對樣品2進行EDX線分析。明確而言，對圖42中的以點劃線圍繞的區域P及圖42中的以雙點劃線圍繞的區域Q進行EDX線分析。在EDX線分析中，作為安裝在STEM裝置中的EDX檢測器使用EDAX的Octane T Ultra W（Dual EDS）。作為STEM裝置使用由日本電子株式會社製造的“JEM-ARM200F NEOARM”，將加速電壓設為200kV，將倍率精度設為±10%，將束徑設為0.1nmφ左右。[EDX Analysis]EDX analysis was performed on sample 2. Specifically, EDX analysis was performed on area P (surrounded by the dotted line) and area Q (surrounded by the double-dotted line) in Figure 42. For EDX analysis, an EDAX Octane T Ultra W (Dual EDS) detector was used as the EDX detector installed in the STEM instrument. The STEM instrument used was the JEM-ARM200F NEOARM manufactured by JEOL Ltd. The accelerating voltage was set to 200 kV, the magnification accuracy was set to ±10%, and the beam diameter was set to approximately 0.1 nm.
圖43A及圖43B示出EDX線分析的結果。在圖43A及圖43B中，縱軸表示藉由EDX線分析得到的濃度[atomic%]，橫軸表示從測量開始點起的距離。圖43A是區域P的結果，圖43B是區域Q的結果。注意，圖43A的分析方向平行於圖42所示的Z方向，圖43B的分析方向平行於圖42所示的Z方向。Figures 43A and 43B show the results of EDX analysis. In Figures 43A and 43B, the vertical axis represents the concentration (atomic %) obtained by EDX analysis, and the horizontal axis represents the distance from the measurement start point. Figure 43A shows the results for region P, and Figure 43B shows the results for region Q. Note that the analysis direction in Figure 43A is parallel to the Z direction shown in Figure 42, and the analysis direction in Figure 43B is parallel to the Z direction shown in Figure 42.
在圖43A及圖43B中，在與開口部290重疊的導電層220上及位於開口部290的外側的導電層240上，在氧化物層227的檢測出Ga的區域中，檢測出In及Sn。因此，可以推測為氧化物層227的導電層220附近的區域及氧化物層227的導電層240附近的區域中形成有合金化部分。可知：在形成合金化部分時，導電層220與氧化物半導體層230間的接觸電阻及導電層240與氧化物半導體層230間的接觸電阻得到降低，因此可以實現電特性良好的電晶體。In Figures 43A and 43B , In and Sn are detected in the region where Ga is detected in oxide layer 227, on conductive layer 220 overlapping opening 290, and on conductive layer 240 located outside opening 290. Therefore, it is inferred that alloyed portions are formed in the region of oxide layer 227 near conductive layer 220 and in the region of oxide layer 227 near conductive layer 240. The formation of alloyed portions reduces the contact resistance between conductive layer 220 and oxide semiconductor layer 230, and the contact resistance between conductive layer 240 and oxide semiconductor layer 230, thereby achieving a transistor with excellent electrical characteristics.
另外，例如與ITO同樣，藉由在合金化部分中包括Sn混入氧化銦中的部分，由於混入的Sn而產生載子，而可以降低接觸電阻。此外，藉由作為合金化部分使用其導電性比氧化鎵高的IGZO，可以降低接觸電阻。另外，藉由減薄氧化物層227的厚度，也可以降低接觸電阻。Similarly to ITO, by including a portion where Sn is mixed into indium oxide in the alloyed portion, the mixed Sn generates carriers, thereby reducing contact resistance. Furthermore, by using IGZO, which has higher conductivity than gallium oxide, as the alloyed portion, contact resistance can be reduced. Furthermore, by reducing the thickness of the oxide layer 227, contact resistance can also be reduced.
本實施例可以與實施方式及其他實施例適當地組合。 實施例3This embodiment can be appropriately combined with the embodiments and other embodiments.Example 3
在本實施例中，製造樣品，並對各樣品進行SIMS分析。In this example, samples were prepared and SIMS analysis was performed on each sample.
首先，說明本實施例中製造的10個樣品（樣品3A、樣品3B、樣品3C、樣品3D、樣品3E、樣品4A、樣品4B、樣品4C、樣品4D及樣品4E）。First, the 10 samples manufactured in this embodiment (sample 3A, sample 3B, sample 3C, sample 3D, sample 3E, sample 4A, sample 4B, sample 4C, sample 4D and sample 4E) are described.
在10個樣品中，同樣地在矽基板上利用熱氧化處理形成其厚度為100nm的氧化矽膜。該氧化矽膜是使用氯化氫形成的氧化膜，因此有時將該氧化矽膜記為HCl-SiOx。In all 10 samples, a 100nm-thick silicon oxide film was formed on a silicon substrate using thermal oxidation. This silicon oxide film is formed using hydrogen chloride and is sometimes referred to as HCl-SiOx.
接著，在上述氧化矽膜上利用ALD法沉積其厚度為20nm的第一氧化物膜。沉積第一氧化物膜時使用的前驅物為三乙基銦。另外，作為氧化劑使用臭氧（O3）及氧（O2）的混合氣體。也就是說，第一氧化物膜是利用ALD法沉積的氧化銦膜，因此有時將第一氧化物膜記為ALD-InOx。Next, a 20nm-thick first oxide film is deposited on the silicon oxide film using ALD. The precursor used for depositing the first oxide film is triethyl indium. A mixed gas of ozone (O₃ ) and oxygen (O₂ ) is used as the oxidizing agent. In other words, the first oxide film is an indium oxide film deposited using ALD, and is therefore sometimes referred to as ALD-InOx.
接著，在樣品4A至樣品4E中，在第一氧化物膜上利用濺射法沉積其厚度為5nm的第二氧化物膜。注意，在沉積第二氧化物膜時，使用In：Ga：Zn=1：1：1.2[原子數比]的氧化物靶材。作為沉積氣體使用氧及氬，並且將相對於氧和氬的流量總和的氧流量比設為90%。另外，將基板加熱的溫度設為250℃。換言之，由於第二氧化物膜是利用濺射法沉積的In-Ga-Zn膜，所以有時將第二氧化物膜記為SP-IGZO。Next, for samples 4A to 4E, a second oxide film with a thickness of 5 nm was deposited on the first oxide film using a sputtering method. Note that an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2 was used for depositing the second oxide film. Oxygen and argon were used as deposition gases, with the oxygen flow rate ratio relative to the combined oxygen and argon flow rates set to 90%. Furthermore, the substrate heating temperature was set to 250°C. In other words, since the second oxide film is an In-Ga-Zn film deposited using the sputtering method, it is sometimes referred to as SP-IGZO.
然後，在使氮氣體和氧氣體的混合氣體（氧濃度20%）流過的同時，對樣品3B至樣品3E及樣品4B至樣品4E進行加熱處理。對樣品3B及樣品4B以400℃進行1小時的該加熱處理，對樣品3C及樣品4C以400℃進行8小時的該加熱處理，對樣品3D及樣品4D以450℃進行1小時的該加熱處理，並且對樣品3E及樣品4E以450℃進行8小時的該加熱處理。另外，不對樣品3A及樣品4A進行該加熱處理。Then, while a mixture of nitrogen and oxygen (oxygen concentration 20%) was passed through, samples 3B to 3E and 4B to 4E were heated. Samples 3B and 4B were heated at 400°C for 1 hour, samples 3C and 4C were heated at 400°C for 8 hours, samples 3D and 4D were heated at 450°C for 1 hour, and samples 3E and 4E were heated at 450°C for 8 hours. Samples 3A and 4A were not heated.
由此，製造10個樣品（樣品3A至樣品4E）。Thus, 10 samples (samples 3A to 4E) were manufactured.
[SIMS分析] 對上述10個樣品都進行SIMS分析。注意，SIMS分析的分析方向是從氧化物膜向基板的方向。藉由SIMS分析，取得上述10個樣品各自的氫（H）濃度的深度分佈。另外，在SIMS分析中，使用由ULVAC-PHI公司製造的四極質譜分析儀裝置（ADEPT1010）。下面，有時將氫濃度的深度分佈記為H分佈。[SIMS Analysis]SIMS analysis was performed on all ten samples described above. Note that SIMS analysis was conducted from the oxide film toward the substrate. SIMS analysis yielded depth distributions of hydrogen (H) concentrations for each of the ten samples. A quadrupole mass spectrometer (ADEPT1010) manufactured by ULVAC-PHI was used for SIMS analysis. Below, the depth distribution of hydrogen concentrations will sometimes be referred to as the H distribution.
圖44A及圖44B示出各樣品的H分佈的結果。在圖44A及圖44B中，縱軸表示H濃度[atoms/cm3]，橫軸表示厚度方向的深度[nm]。另外，作為定量層使用第一氧化物膜（ALD-InOx）。此外，該SIMS分析中的氫的本底水準（B.G.）為2.1×1018atoms/cm3。Figures 44A and 44B show the hydrogen distribution results for each sample. In Figures 44A and 44B, the vertical axis represents hydrogen concentration (atoms/cm³ ), and the horizontal axis represents depth in the thickness direction (nm). The first oxide film (ALD-InOx) was used as the quantitative layer. The hydrogen background level (BG) in this SIMS analysis was 2.1×1018 atoms/cm³ .
圖44A所示的虛線是樣品3A的H分佈，圖44A所示的實線是樣品3B的H分佈，圖44A所示的點劃線是樣品3C的H分佈，圖44A所示的點線是樣品3D的H分佈，圖44A所示的雙點劃線是樣品3E的H分佈。The dotted line shown in FIG44A is the H distribution of sample 3A, the solid line shown in FIG44A is the H distribution of sample 3B, the dotted line shown in FIG44A is the H distribution of sample 3C, the dotted line shown in FIG44A is the H distribution of sample 3D, and the double-dotted line shown in FIG44A is the H distribution of sample 3E.
圖44B所示的虛線是樣品4A的H分佈，圖44B所示的實線是樣品4B的H分佈，圖44B所示的點劃線是樣品4C的H分佈，圖44B所示的點線是樣品4D的H分佈，圖44B所示的雙點劃線是樣品4E的H分佈。The dotted line shown in FIG44B is the H distribution of sample 4A, the solid line shown in FIG44B is the H distribution of sample 4B, the dotted line shown in FIG44B is the H distribution of sample 4C, the dotted line shown in FIG44B is the H distribution of sample 4D, and the double-dotted line shown in FIG44B is the H distribution of sample 4E.
根據圖44A及圖44B可知：與樣品3A相比，樣品4A的第一氧化物膜中的氫濃度低。因此可知，藉由在第一氧化物膜上設置第二氧化物膜，向第一氧化物膜的氫的擴散得到抑制。此外，還可知：形成在第一氧化物膜上的第二氧化物膜具有氫阻擋性。Figures 44A and 44B show that the hydrogen concentration in the first oxide film of sample 4A is lower than that of sample 3A. Therefore, it is clear that providing the second oxide film on the first oxide film suppresses the diffusion of hydrogen into the first oxide film. Furthermore, it is also clear that the second oxide film formed on the first oxide film has hydrogen barrier properties.
根據圖44A可知：與樣品3A相比，樣品3B至樣品3E的第一氧化物膜中的氫濃度低。因此可知，藉由在形成第一氧化物膜之後進行加熱處理，可以降低第一氧化物膜中的氫濃度。但是，樣品3B至樣品3E的第一氧化物膜中的氫濃度不會降低到1×1020atoms/cm3以下。FIG44A shows that the hydrogen concentration in the first oxide film of samples 3B through 3E is lower than that of sample 3A. This indicates that the hydrogen concentration in the first oxide film can be reduced by performing a heat treatment after forming the first oxide film. However, the hydrogen concentration in the first oxide film of samples 3B through 3E does not drop below 1×1020 atoms/cm3 .
根據圖44B可知：與樣品4A相比，樣品4B至樣品4E的第一氧化物膜中的氫濃度低。因此可知，藉由在第一氧化物膜上形成第二氧化物膜之後進行加熱處理，可以降低第一氧化物膜中的氫濃度。明確而言，加熱處理之前的第一氧化物膜中的氫濃度為1×1020atoms/cm3以上，但是藉由在形成第二氧化物膜之後進行加熱處理，可以將第一氧化物膜中的氫濃度降低到低於1×1020atoms/cm3。FIG44B shows that the hydrogen concentration in the first oxide film of samples 4B to 4E is lower than that of sample 4A. This indicates that the hydrogen concentration in the first oxide film can be reduced by performing a heat treatment after forming the second oxide film on the first oxide film. Specifically, the hydrogen concentration in the first oxide film before the heat treatment was above 1×1020 atoms/cm3 , but by performing a heat treatment after forming the second oxide film, the hydrogen concentration in the first oxide film can be reduced to below 1×1020 atoms/cm3 .
如上所述，藉由在第一氧化物膜上形成第二氧化物膜之後進行加熱處理，可以降低第一氧化物膜中的氫濃度。並且，藉由在第一氧化物膜上設置第二氧化物膜，可以防止氫混入到氫濃度得到降低的第一氧化物膜中。換言之，可知：可以防止氫及水再次吸附到第一氧化物膜或者再次被第一氧化物膜吸收。另外，第二氧化物膜較佳為其In的含有率比第一氧化物膜低的膜。另外，第二氧化物膜可以使用半導體材料，也可以使用絕緣材料。As described above, by performing a heat treatment after forming the second oxide film on the first oxide film, the hydrogen concentration in the first oxide film can be reduced. Furthermore, by providing the second oxide film on the first oxide film, hydrogen can be prevented from incorporating into the first oxide film, whose hydrogen concentration has been reduced. In other words, it is possible to prevent hydrogen and water from being re-adsorbed into or absorbed by the first oxide film. Furthermore, the second oxide film preferably has a lower indium content than the first oxide film. The second oxide film can be made of either a semiconductor material or an insulating material.
本實施例可以與實施方式及其他實施例適當地組合。 實施例4This embodiment can be appropriately combined with the embodiments and other embodiments.Example 4
在本實施例中，製造包括記憶單元的記憶體裝置並對記憶單元所包括的電晶體的電特性進行評價。In this embodiment, a memory device including a memory cell is manufactured and the electrical characteristics of a transistor included in the memory cell are evaluated.
[記憶體裝置的製造] 參照圖20A至圖20C所示的記憶單元150的結構，作為記憶體裝置製造樣品5。圖45A示出本實施例中製造的樣品所包括的記憶單元的立體示意圖。圖45A示出配置有2個×2個的記憶單元的例子。圖45A所示的“字線”對應於導電層265，圖45A所示的“位元線”對應於導電層240。[Memory Device Fabrication]Sample 5 was fabricated as a memory device, referring to the structure of memory cell 150 shown in Figures 20A to 20C. Figure 45A shows a schematic three-dimensional diagram of the memory cells included in the sample fabricated in this embodiment. Figure 45A illustrates an example of a 2x2 array of memory cells. The "word line" shown in Figure 45A corresponds to conductive layer 265, and the "bit line" shown in Figure 45A corresponds to conductive layer 240.
圖46A示出樣品5所包括的記憶單元的平面圖，圖46B及圖46C示出樣品5所包括的記憶單元的剖面圖。圖46A至圖46C所示的記憶單元150除了圖20A至圖20C所示的記憶單元150的結構以外還包括絕緣層185。在將氧化物用於絕緣層180的情況下，藉由設置絕緣層185，可以抑制因絕緣層180而導電層115被氧化。FIG46A shows a plan view of a memory cell included in Sample 5, and FIG46B and FIG46C show cross-sectional views of the memory cell included in Sample 5. Memory cell 150 shown in FIG46A to FIG46C includes an insulating layer 185 in addition to the structure of memory cell 150 shown in FIG20A to FIG20C. When an oxide is used for insulating layer 180, the provision of insulating layer 185 can suppress oxidation of conductive layer 115 due to insulating layer 180.
另外，圖46A至圖46C所示的記憶單元150具有由絕緣層130覆蓋導電層115的頂面的結構。明確而言，導電層115的頂面的高度與絕緣層180的頂面的高度一致或大致一致，並且以覆蓋導電層115的方式設置絕緣層130。藉由採用這種結構，可以防止導電層115與導電層220的短路。Memory cell 150 shown in Figures 46A to 46C has a structure in which the top surface of conductive layer 115 is covered by insulating layer 130. Specifically, the height of the top surface of conductive layer 115 is the same or substantially the same as the height of the top surface of insulating layer 180, and insulating layer 130 is provided so as to cover conductive layer 115. This structure prevents short circuits between conductive layer 115 and conductive layer 220.
在氮化矽膜上設置氧化矽膜，在該氧化矽膜中形成開口。接著，以嵌入該開口的方式設置氮化鈦膜及鎢膜的疊層膜並對其進行CMP處理，由此形成導電層110。也就是說，導電層110具有氮化鈦膜及該氮化矽膜上的鎢膜的疊層結構。A silicon oxide film is formed on the silicon nitride film, and an opening is formed in the silicon oxide film. Next, a stack of titanium nitride and tungsten films is formed to fill the opening and subjected to CMP treatment, thereby forming conductive layer 110. In other words, conductive layer 110 has a stack of titanium nitride and tungsten films on the silicon nitride film.
接著，藉由在氧化矽膜及導電層110上設置氮化矽膜、氧化矽膜及氮化矽膜的疊層膜，形成絕緣層180。換言之，絕緣層180具有氮化矽膜、該氮化矽膜上的氧化矽膜及該氧化矽膜上的氮化矽膜的疊層結構。Next, insulating layer 180 is formed by providing a silicon nitride film and a stacked film of a silicon oxide film and a silicon nitride film on the silicon oxide film and conductive layer 110. In other words, insulating layer 180 has a stacked structure of a silicon nitride film, a silicon oxide film on the silicon nitride film, and a silicon nitride film on the silicon oxide film.
接著，利用乾蝕刻法形成開口部190。Next, the opening 190 is formed by dry etching.
接著，形成氮化矽膜並對其進行CMP處理，由此沿著開口部190的側壁設置側壁狀的氮化矽膜。該氮化矽膜相當於絕緣層185。Next, a silicon nitride film is formed and CMP-treated, thereby forming a sidewall-shaped silicon nitride film along the sidewall of the opening 190. This silicon nitride film corresponds to the insulating layer 185.
接著，利用CVD法沉積其厚度為5nm的氮化鈦膜並對該氮化鈦膜進行加工，由此形成導電層115。Next, a titanium nitride film was deposited to a thickness of 5 nm by CVD and processed to form a conductive layer 115.
接著，作為絕緣層130，利用ALD法形成其厚度為10nm的氧化鉿鋯膜。Next, a 10 nm thick elongated zirconium oxide film was formed as the insulating layer 130 by ALD.
接著，在利用CVD法沉積其厚度為5nm的氮化鈦膜，接著利用CVD法沉積其厚度為50nm的鎢膜，然後利用濺射法沉積其厚度為20nm的ITSO膜，並且對氮化鈦膜、鎢膜及ITSO膜的疊層膜進行加工，由此形成導電層220。也就是說，導電層220具有氮化鈦膜、該氮化鈦膜上的鎢膜及該鎢膜上的ITSO膜的疊層結構。另外，氮化鈦膜相當於導電層220_11，鎢膜相當於導電層220_12，ITSO膜相當於導電層220_2。Next, a titanium nitride film is deposited to a thickness of 5 nm using CVD, followed by a tungsten film to a thickness of 50 nm using CVD, and then a 20 nm thick ITSO film is deposited using sputtering. The stack of titanium nitride, tungsten, and ITSO films is then processed to form conductive layer 220. In other words, conductive layer 220 has a stacked structure of a titanium nitride film, a tungsten film on the titanium nitride film, and an ITSO film on the tungsten film. The titanium nitride film corresponds to conductive layer 220_11, the tungsten film corresponds to conductive layer 220_12, and the ITSO film corresponds to conductive layer 220_2.
接著，利用PEALD法沉積其厚度為5nm的第一氮化矽膜。接著，利用濺射法沉積其厚度為175nm的氧化矽膜，然後在該氧化矽膜上利用濺射法沉積其厚度為140nm的第二氮化矽膜，並且進行CMP處理來去除第二氮化矽膜，由此使氧化矽膜的頂面平坦化。藉由進行該CMP處理，形成導電層220上的其厚度為80nm的氧化矽膜。接著，利用濺射法沉積其厚度為10nm的第三氮化矽膜。如此，形成絕緣層280。也就是說，絕緣層280具有第一氮化矽膜、第一氮化矽膜上的氧化矽膜及該氧化矽膜上的第三氮化矽的疊層結構。另外，第一氮化矽膜相當於絕緣層280_1，氧化矽膜相當於絕緣層280_2，第三氮化矽膜相當於絕緣層280_3。Next, a first silicon nitride film with a thickness of 5 nm is deposited using the PEALD method. A silicon oxide film with a thickness of 175 nm is then deposited using the sputtering method. A second silicon nitride film with a thickness of 140 nm is then deposited on this silicon oxide film using the sputtering method. A CMP process is then performed to remove the second silicon nitride film, thereby flattening the top surface of the silicon oxide film. This CMP process forms an 80 nm thick silicon oxide film on the conductive layer 220. Next, a third silicon nitride film with a thickness of 10 nm is deposited using the sputtering method. In this manner, insulating layer 280 is formed. In other words, insulating layer 280 has a stacked structure consisting of a first silicon nitride film, a silicon oxide film on the first silicon nitride film, and a third silicon nitride film on the silicon oxide film. The first silicon nitride film corresponds to insulating layer 280_1, the silicon oxide film corresponds to insulating layer 280_2, and the third silicon nitride film corresponds to insulating layer 280_3.
接著，使用利用濺射法沉積的其厚度為15nm的鎢膜形成導電層240a，使用利用濺射法沉積的其厚度為10nm的ITSO膜形成導電層240b。Next, a conductive layer 240a was formed using a tungsten film deposited to a thickness of 15 nm by sputtering, and a conductive layer 240b was formed using an ITSO film deposited to a thickness of 10 nm by sputtering.
接著，利用乾蝕刻法形成開口部290。Next, the opening 290 is formed by dry etching.
接著，使用利用熱ALD法沉積的其厚度為0.5nm的氧化鎵膜形成氧化物層227。作為包含鎵的前驅物使用三乙基鎵，作為氧化劑使用臭氧（O3）及氧（O2）。將基板加熱的溫度設為200℃。Next, a 0.5 nm thick gallium oxide film was deposited by thermal ALD to form an oxide layer 227. Triethyl gallium was used as a precursor containing gallium, and ozone (O3 ) and oxygen (O2 ) were used as oxidants. The substrate was heated at a temperature of 200°C.
接著，使用其厚度為5nm的第一層及第一層上的其厚度為5nm的第二層的疊層膜形成氧化物半導體層230。Next, an oxide semiconductor layer 230 is formed using a stacked film of a first layer having a thickness of 5 nm and a second layer having a thickness of 5 nm on the first layer.
作為氧化物半導體層230的第一層，利用熱ALD法沉積氧化銦膜。作為包含銦的前驅物使用三乙基銦。另外，作為氧化劑使用臭氧（O3）及氧（O2）。將基板加熱的溫度設為200℃。As the first layer of the oxide semiconductor layer 230, an indium oxide film was deposited using thermal ALD. Triethyl indium was used as a precursor containing indium. Ozone (O3 ) and oxygen (O2 ) were used as oxidants. The substrate was heated to 200°C.
作為氧化物半導體層230的第二層，利用RF濺射法沉積In-Ga-Zn氧化物膜。注意，在沉積第二層時，使用In：Ga：Zn=1：1：1.2[原子數比]的氧化物靶材。作為沉積氣體使用氧及氬，並且將相對於氧和氬的流量總和的氧流量比設為90%。此外，將基板加熱的溫度設為250℃。As the second layer of the oxide semiconductor layer 230, an In—Ga—Zn oxide film was deposited using RF sputtering. Note that an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2 was used for the deposition of the second layer. Oxygen and argon were used as deposition gases, with the oxygen flow rate ratio set to 90% relative to the total flow rate of oxygen and argon. Furthermore, the substrate heating temperature was set to 250°C.
接著，使用第一層、第一層上的第二層、第二層上的第三層及第三層上的第四層的疊層膜形成絕緣層250。Next, an insulating layer 250 is formed using a stacked film of a first layer, a second layer on the first layer, a third layer on the second layer, and a fourth layer on the third layer.
在絕緣層250中，作為第一層，利用熱ALD法沉積其厚度為1nm的氧化鋁膜。另外，作為第二層，利用PEALD法沉積其厚度為2nm的氧化矽膜。另外，作為第三層，利用熱ALD法沉積其厚度為2nm的氧化鉿膜。另外，作為第四層，利用PEALD法沉積其厚度為1nm的氮化矽膜。In insulating layer 250, a 1 nm thick aluminum oxide film is deposited using thermal ALD as the first layer. A 2 nm thick silicon oxide film is deposited using PEALD as the second layer. A 2 nm thick ferrite oxide film is deposited using thermal ALD as the third layer. A 1 nm thick silicon nitride film is deposited using PEALD as the fourth layer.
接著，使用利用ALD法沉積的其厚度為3nm的氧化鋁膜形成絕緣層284。Next, an insulating layer 284 is formed using an aluminum oxide film deposited to a thickness of 3 nm by an ALD method.
然後，在利用濺射法沉積氧化矽膜，接著在該氧化矽膜上利用濺射法沉積氮化矽膜，並且對其進行CMP處理來去除該氮化矽膜，由此使該氧化矽膜的頂面平坦化。藉由進行該CMP處理可以形成導電層240上的其厚度為65nm的氧化矽膜。如此，形成絕緣層285。也就是說，絕緣層285包括氧化矽膜。Next, a silicon oxide film is deposited by sputtering, followed by a silicon nitride film deposited over the silicon oxide film by sputtering. A CMP process is then performed to remove the silicon nitride film, thereby flattening the top surface of the silicon oxide film. This CMP process forms a 65nm thick silicon oxide film on conductive layer 240. In this manner, insulating layer 285 is formed. In other words, insulating layer 285 comprises a silicon oxide film.
接著，形成利用CVD法沉積的其厚度為5nm的氮化鈦膜及利用CVD法沉積的鎢膜的疊層膜並對其進行CMP處理，由此形成導電層260。也就是說，導電層260具有氮化鈦膜及該氮化鈦膜上的鎢膜的疊層結構。另外，氮化鈦膜相當於導電層260_1，鎢膜相當於導電層260_2。Next, a stack of a titanium nitride film deposited by CVD to a thickness of 5 nm and a tungsten film deposited by CVD is formed and CMP treated, thereby forming conductive layer 260. In other words, conductive layer 260 has a stack of a titanium nitride film and a tungsten film on the titanium nitride film. The titanium nitride film corresponds to conductive layer 260_1, and the tungsten film corresponds to conductive layer 260_2.
接著，使用利用濺射法沉積的其厚度為30nm的鎢膜形成導電層265。Next, a conductive layer 265 was formed using a tungsten film deposited to a thickness of 30 nm by sputtering.
如上所述，製造作為記憶體裝置的樣品5所包括的電晶體及電容器。樣品5所包括的記憶單元以6.9個/μm2的密度製造。另外，在部分電晶體下不設置電容器。As described above, the transistors and capacitors included in Sample 5, a memory device, were manufactured. The memory cells included in Sample 5 were manufactured at a density of 6.9 cells/μm² . Furthermore, capacitors were not provided under some of the transistors.
[STEM影像的取得] 以使用由日立高新技術公司製造的“HD-2700”且將加速電壓設為200kV的方式對製造的樣品5進行剖面STEM影像的拍攝。圖45B示出樣品5的剖面STEM影像。圖45B所示的“溝槽電容器”對應於樣品5所包括的電容器，圖45B所示的“VFET”對應於樣品5所包括的電晶體。圖45B所示的“閘極”對應於導電層265，圖45B所示的“OS”對應於氧化物半導體層230，圖45B所示的“汲極”對應於導電層240，圖45B所示的“源極”對應於導電層220，圖45B所示的“FE”對應於絕緣層130，圖45B所示的“板線”對應於導電層110。[STEM Image Acquisition]A cross-sectional STEM image of fabricated Sample 5 was captured using the HD-2700, manufactured by Hitachi High-Technologies Corporation, at an accelerating voltage of 200 kV. Figure 45B shows a cross-sectional STEM image of Sample 5. The "trench capacitor" shown in Figure 45B corresponds to the capacitor included in Sample 5, and the "VFET" shown in Figure 45B corresponds to the transistor included in Sample 5. The "gate" shown in FIG45B corresponds to the conductive layer 265, the "OS" shown in FIG45B corresponds to the oxide semiconductor layer 230, the "drain" shown in FIG45B corresponds to the conductive layer 240, the "source" shown in FIG45B corresponds to the conductive layer 220, the "FE" shown in FIG45B corresponds to the insulating layer 130, and the "plate line" shown in FIG45B corresponds to the conductive layer 110.
在圖45B中可確認到：製造的電容器具有相當於圖46B及圖46C所示的電容器100的結構，並且製造的電晶體具有相當於圖20B及圖20C所示的電晶體200A的結構。As can be seen in FIG45B, the fabricated capacitor has a structure equivalent to that of capacitor 100 shown in FIG46B and FIG46C, and the fabricated transistor has a structure equivalent to that of transistor 200A shown in FIG20B and FIG20C.
[電晶體的電特性評價] 測量本實施例中製造的樣品5所包括的一個電晶體的Id-Vg特性。在此，使用開口部290的寬度（圖8A所示的寬度D）為60nm且俯視時的開口的形狀為近似圓形的電晶體來評價。[Evaluation of Transistor Electrical Characteristics]The Id-Vg characteristics of a transistor included in Sample 5 fabricated in this embodiment were measured. This evaluation was performed using a transistor with an opening 290 width (width D shown in Figure 8A) of 60 nm and a substantially circular opening shape when viewed from above.
在測量中，將汲極電位Vd設為1.2V或0.1V，將源極電位Vs設為0V，並且將閘極電位從-4V到+4V每隔0.1V掃描。將測量溫度設為室溫。圖47示出樣品5所包括的電晶體的Id-Vg特性。在圖47中，縱軸表示汲極電流Id[A]，橫軸表示閘極電位Vg[V]。在圖47中，以點線示出Vd=0.1V的Id-Vg曲線，以實線示出Vd=1.2V的Id-Vg曲線。During the measurement, the drain potential Vd was set to 1.2V or 0.1V, the source potential Vs was set to 0V, and the gate potential was swept from -4V to +4V in 0.1V increments. The measurement temperature was set to room temperature. Figure 47 shows the Id-Vg characteristics of the transistor included in Sample 5. In Figure 47, the vertical axis represents the drain current Id [A], and the horizontal axis represents the gate potential Vg [V]. In Figure 47, the Id-Vg curve for Vd = 0.1V is shown as a dotted line, and the Id-Vg curve for Vd = 1.2V is shown as a solid line.
另外，測量與上述同樣的結構的八個電晶體的Id-Vg特性。注意，在該八個電晶體下不設置電容器。In addition, the Id-Vg characteristics of eight transistors with the same structure as above were measured. Note that no capacitors were provided under these eight transistors.
在測量八個電晶體的Id-Vg特性時，利用與上述同樣的方法。圖48A示出八個電晶體的Id-Vg特性。在圖48A中，縱軸表示汲極電流Id[A]，橫軸表示閘極電位Vg[V]。在圖48A中，以虛線示出Vd=0.1V的Id-Vg曲線，以實線示出Vd=1.2V的Id-Vg曲線。The Id-Vg characteristics of the eight transistors were measured using the same method as described above. Figure 48A shows the Id-Vg characteristics of the eight transistors. In Figure 48A, the vertical axis represents the drain current Id [A], and the horizontal axis represents the gate potential Vg [V]. In Figure 48A, the Id-Vg curve for Vd = 0.1V is shown as a dashed line, and the Id-Vg curve for Vd = 1.2V is shown as a solid line.
Vg=Vsh+2.5V時的汲極電流為69.9A，此時可以獲得良好的值。注意，在本實施例中，將漂移電壓Vsh定義為Id-Vg曲線的傾斜度最大時的切線與Id=1.0×10-12A相交處的Vg的值。The drain current at Vg = Vsh + 2.5V is 69.9A, which is a good value. Note that in this embodiment, the drift voltage Vsh is defined as the Vg value where the tangent line of the Id-Vg curve, where the slope is maximum, intersects Id = 1.0×10-12 A.
另外，同樣地還測量其下設置有電容器的電晶體，換稱為構成記憶單元的電晶體的Id-Vg特性。還測量其下設置有電容器的八個電晶體的Id-Vg特性。Similarly, the Id-Vg characteristics of the transistors with capacitors placed underneath them (also referred to as the transistors that constitute the memory cell) were measured. The Id-Vg characteristics of eight transistors with capacitors placed underneath them were also measured.
在測量其下設置有電容器的電晶體的Id-Vg特性時，也利用與上述同樣的方法。圖48B示出其下設置有電容器的八個電晶體的Id-Vg特性。在圖48B中，縱軸表示汲極電流Id[A]，橫軸表示閘極電位Vg[V]。在圖48B中，以虛線示出Vd=0.1V的Id-Vg曲線，以實線示出Vd=1.2V的Id-Vg曲線。The same method as above was used to measure the Id-Vg characteristics of transistors with capacitors placed underneath them. Figure 48B shows the Id-Vg characteristics of eight transistors with capacitors placed underneath them. In Figure 48B, the vertical axis represents drain current Id [A], and the horizontal axis represents gate potential Vg [V]. In Figure 48B, the Id-Vg curve for Vd = 0.1V is shown as a dashed line, and the Id-Vg curve for Vd = 1.2V is shown as a solid line.
如圖48B所示，確認到其下設置有電容器的電晶體也具有與不設置電容器的電晶體相等的電特性。另外，Vg=Vsh+2.5V時的汲極電流為62.4A，此時獲得良好的值。如此，藉由使用汲極電流大的電晶體，可以使記憶體裝置高速工作。As shown in Figure 48B, it was confirmed that the transistor with the capacitor underneath had electrical characteristics equivalent to those without the capacitor. Furthermore, the drain current at Vg = Vsh + 2.5V was 62.4A, a good value. Thus, using transistors with high drain current allows for high-speed operation of the memory device.
由此，如圖47、圖48A及圖48B所示，確認到本實施例的樣品5所包括的電晶體呈現良好的電特性。Therefore, as shown in FIG. 47 , FIG. 48A and FIG. 48B , it was confirmed that the transistor included in Sample 5 of this embodiment exhibited good electrical characteristics.
＜P-V特性＞ 在樣品5所包括的電容器中，對上部電極與下部電極間施加三角波，由此測量介電質的自發極化的變化（P-V特性）。在施加的三角波中，將頻率設為1kHz，將電壓設為-2.5V至+2.5V的範圍。在此，使用開口部190的深度為415nm、開口部190的寬度為60nm且俯視時的開口部190的形狀為近似圓形的電容器來評價。<P-V Characteristics>In the capacitor included in Sample 5, a triangular wave was applied between the upper and lower electrodes to measure the change in the spontaneous polarization of the dielectric (P-V characteristics). The frequency of the applied triangular wave was set to 1 kHz, and the voltage was set to a range of -2.5 V to +2.5 V. The evaluation was conducted using a capacitor with an opening 190 depth of 415 nm, a width of 60 nm, and a substantially circular shape when viewed from above.
圖49示出樣品5所包括的電容器的P-V特性的測量結果。圖49示出循環數為1×104次時的P-V特性的測量結果。在圖49中，縱軸表示極化P[μC/cm2]，橫軸表示電壓[V]。注意，在本說明書等中，極化有時是指單位面積的殘留極化量。Figure 49 shows the results of measuring the PV characteristics of the capacitor included in Sample 5. Figure 49 shows the results of measuring the PV characteristics at a cycle number of 1×104 . In Figure 49 , the vertical axis represents polarization P [μC/cm2 ], and the horizontal axis represents voltage [V]. Note that in this specification, etc., polarization sometimes refers to the amount of residual polarization per unit area.
在圖49中，確認到樣品5所包括的電容器具有滯後特性。明確而言，循環數為1×104次時的2Pr為28.8μC/cm2。因此，確認到本實施例的樣品5所包括的電容器具有良好的鐵電體特性。FIG49 shows that the capacitor included in Sample 5 exhibits hysteresis characteristics. Specifically, 2Pr at a cycle number of 1×104 times is 28.8 μC/cm2 . Therefore, it is confirmed that the capacitor included in Sample 5 of this embodiment exhibits excellent ferroelectric characteristics.
＜疲勞特性＞ 說明對樣品5所包括的電容器進行的疲勞（Endurance）特性的測量結果。<Fatigue Characteristics>This section describes the fatigue (endurance) characteristics measurement results for the capacitor included in Sample 5.
在疲勞特性的測量中，以將1週期的梯形波施加到電容器的上部電極與下部電極間的製程為1次循環，直到達到規定循環數為止重複施加該梯形波。按每個規定循環數利用上述三角波雙脈衝法測量自發極化的變化（P-E特性），由此取得電場強度E為0時的最小極化與最大極化之差2Pr。In fatigue characteristics measurements, a single cycle of a trapezoidal wave applied between the upper and lower electrodes of the capacitor is considered one cycle. This trapezoidal wave is applied repeatedly until a specified number of cycles are reached. The change in spontaneous polarization (P-E characteristics) is measured using the triangular wave double-pulse method described above after each specified number of cycles. The difference between the minimum and maximum polarizations when the electric field intensity E is 0, 2Pr, is obtained.
在此，使用圖50A說明三角波雙脈衝法。圖50A示出輸入電壓波形。如圖50A所示，三角波雙脈衝法是如下方法：施加兩個正的三角波脈衝，然後施加兩個負的三角波脈衝，並且測量其相應電荷。在施加的三角波中，頻率為1kHz，電壓為±2.5V，電場強度為2.5MV/cm。在施加上述正的三角波脈衝之前施加負的三角波脈衝（圖50A中的極化）。在本說明書等中，有時將三角波雙脈衝法稱為Triangle-PUND（Positive-up-negative-down）法。Here, the triangular wave double pulse method is explained using Figure 50A. Figure 50A shows the input voltage waveform. As shown in Figure 50A, the triangular wave double pulse method applies two positive triangular wave pulses, followed by two negative triangular wave pulses, and measures the corresponding charges. The applied triangular wave has a frequency of 1 kHz, a voltage of ±2.5 V, and an electric field strength of 2.5 MV/cm. The negative triangular wave pulse is applied before the positive triangular wave pulses (polarization in Figure 50A). In this manual and other documents, the triangular wave double pulse method is sometimes referred to as the Triangle-PUND (Positive-up-negative-down) method.
在測量疲勞特性時施加的梯形波中，頻率為100kHz，電場強度為2.5MV/cm。The trapezoidal wave applied during fatigue measurement has a frequency of 100 kHz and an electric field strength of 2.5 MV/cm.
圖50B示出樣品5所包括的電容器的疲勞特性的測量結果。注意，在圖50B中，縱軸表示電場強度E為0MV/cm時的最小極化與最大極化之差2Pr，橫軸表示循環數（Cycle）。FIG50B shows the measurement results of the fatigue characteristics of the capacitor included in Sample 5. Note that in FIG50B , the vertical axis represents the difference 2Pr between the minimum polarization and the maximum polarization when the electric field intensity E is 0 MV/cm, and the horizontal axis represents the number of cycles (Cycle).
在圖50B中，即使循環數達到1×1010次，也不在樣品5所包括的電容器中發生絕緣擊穿。用於該電容器的氧化鉿鋯膜是其厚度為10nm的較薄的膜，但是不發生絕緣擊穿。In FIG50B, even when the number of cycles reached 1×1010 times, insulation breakdown did not occur in the capacitor included in Sample 5. The zirconium oxide film used for this capacitor was a relatively thin film with a thickness of 10 nm, but insulation breakdown did not occur.
從圖50B可知，在樣品5所包括的電容器中根據循環數觀察到喚醒（wake up）及疲乏（fatigue）。注意，喚醒是指極化的電荷量增加的階段或者2Pr的絕對值變大的階段，疲乏是指極化的電荷量減少的階段或者2Pr的絕對值變小的階段。注意，循環數經過1×1010次之後的2Pr比初始的2Pr稍微小，但是可以說大致相等。如此，樣品5所包括的電容器具有良好的疲勞特性。As shown in Figure 50B, the capacitor included in Sample 5 exhibits both wake-up and fatigue depending on the number of cycles. Note that wake-up refers to the phase in which the polarized charge increases, or the phase in which the absolute value of 2Pr increases, while fatigue refers to the phase in which the polarized charge decreases, or the phase in which the absolute value of 2Pr decreases. Note that 2Pr after 1×1010 cycles is slightly smaller than the initial 2Pr, but is generally equivalent. Thus, the capacitor included in Sample 5 exhibits excellent fatigue characteristics.
＜保持測量＞ 說明對樣品5所包括的電容器進行的保持測量的結果。<Holding Measurement>This section describes the results of holding measurements performed on the capacitors included in Sample 5.
圖51A示出保持測量的工作序列。圖51B示出極化的變化的假設圖。圖51C示出保持測量的結果。Figure 51A shows the operating sequence of the hold measurement. Figure 51B shows a hypothetical diagram of polarization changes. Figure 51C shows the results of the hold measurement.
在保持測量中，使用由東陽特克尼卡製造的鐵電體特性評價系統“FCE10-F”。另外，在本實施例中，為了在將溫度條件設為85℃的情況下進行保持測量，使用包括具有溫度調整功能的載物台的探測器（prober）。The hold measurement was performed using the FCE10-F ferroelectric characteristics evaluation system manufactured by Toyo Technica. In this embodiment, a prober with a stage equipped with a temperature adjustment function was used to perform the hold measurement at a temperature of 85°C.
在保持測量中使用脈衝生成器對樣品供應電位，並對此時流過的電流進行測量。對圖51A所示的保持測量的工作序列進行說明。注意，在保持測量中採用兩個條件。In hold measurement, a pulse generator is used to apply a potential to the sample and the resulting current is measured. The hold measurement operation sequence shown in Figure 51A is explained below. Note that hold measurement employs two conditions.
對第一條件（Case1）進行說明。在期間T1中，對樣品施加正的三角波脈衝而使氧化鉿鋯膜處於正電位側的極化狀態（極化）。接著，在期間T2中，保持為0V的電位（待機時間）。在期間T2中，在4秒、1分鐘、10分鐘、100分鐘的四個條件下進行測量。然後，在期間T3中，利用上述三角波雙脈衝法測量P-E特性而取得電場強度E為0MV/cm時的最小極化與最大極化之差（極化測量）。The first condition (Case 1) is explained below. During period T1, a positive triangular pulse is applied to the sample, polarizing the zirconium oxide film to the positive potential side (polarization). Next, during period T2, the potential is maintained at 0V (standby time). During period T2, measurements are performed under four conditions: 4 seconds, 1 minute, 10 minutes, and 100 minutes. Finally, during period T3, the P-E characteristics are measured using the aforementioned triangular double-pulse method, obtaining the difference between the minimum and maximum polarizations when the electric field intensity E is 0 MV/cm (polarization measurement).
接著，對第二條件（Case2）進行說明。在期間T1中，對樣品供應負的三角波脈衝並使氧化鉿鋯膜處於負電位側的極化狀態。期間T2以後的電壓的施加方法與上述第一條件下的方法相同。Next, let's explain the second condition (Case 2). During period T1, a negative triangular pulse is applied to the sample, polarizing the zirconium oxide film to the negative potential. The voltage application method after period T2 is the same as for the first condition described above.
如圖51B所示，在上述第一條件（Case1）下不會發生極化反轉（非反轉極化）。另一方面，在上述第二條件（Case2）下發生極化反轉（反轉極化）。如此，在此進行的保持測量中有時不發生極化反轉，因此將電場強度E為0時的最小極化與最大極化之差記為ΔPr。As shown in Figure 51B, under the first condition (Case 1), no polarization reversal occurs (non-reversed polarization). On the other hand, under the second condition (Case 2), polarization reversal occurs (reversed polarization). Since polarization reversal may not occur during hold measurements, the difference between the minimum and maximum polarizations when the electric field strength E is 0 is recorded as ΔPr.
圖51C示出對樣品5所包括的電容器進行的保持測量的結果。在圖51C中，縱軸表示ΔPr[μC/cm2]，橫軸表示85℃下的保持時間（85℃烘焙時間[分]）。在圖51C中，以圓形示出的曲線圖是第一條件（非反轉極化）下的結果，以方塊示出的曲線圖是第二條件（反轉極化）下的結果。如此，在圖表中示出藉由分析測量資料而得到的ΔPr的值以及期間T2的保持期間的長度，由此可知能夠在多少期間保持極化｡Figure 51C shows the results of retention measurements for the capacitor included in Sample 5. In Figure 51C, the vertical axis represents ΔPr [μC/cm² ], and the horizontal axis represents the retention time at 85°C (85°C baking time [minutes]). The circular graph in Figure 51C shows the results under the first condition (non-inverted polarization), while the square graph shows the results under the second condition (inverted polarization). Thus, the graph shows the ΔPr values obtained by analyzing the measurement data and the length of the retention period (period T2), indicating the duration of polarization retention.
如圖51C所示，當以85℃的溫度條件進行保持時間為100分鐘的保持測量時，在不發生極化反轉的情況及發生極化反轉的情況下ΔPr都幾乎不減少。如此，樣品5所包括的電容器具有良好的保持特性。As shown in Figure 51C, when holding measurements were performed at 85°C for 100 minutes, ΔPr barely decreased in both the absence and presence of polarization reversal. Thus, the capacitor included in Sample 5 exhibited excellent holding characteristics.
＜寫入讀出評價＞ 說明對包括具有與樣品5所包括的電晶體及電容器同樣的結構的電晶體Tr1、Tr2、Tr3以及電容器Cfe的記憶單元的寫入工作及讀出工作進行評價的結果。<Write and Read Evaluation>This section describes the results of an evaluation of the write and read operations of a memory cell comprising transistors Tr1, Tr2, and Tr3 and capacitor Cfe, which have the same structure as those included in Sample 5.
圖52示出該記憶單元的電路圖。圖52所示的電晶體Tr1被用作資料寫入用電晶體。此外，電晶體Tr2及電容器Cfe被用作1Tr1C的記憶單元。此外，電晶體Tr3具有資料讀出用電晶體。如上所述，電容器Cfe是鐵電體電容器。以下，說明如下結果：對電容器Cfe進行負的極化的寫入（有時稱為data“1”的寫入）或正的極化的寫入（有時稱為data“0”的寫入），在各情況下測量電晶體Tr3的電流IR，並且進行資料的讀出。Figure 52 shows a circuit diagram of this memory cell. Transistor Tr1 shown in Figure 52 is used as a data write transistor. Furthermore, transistor Tr2 and capacitor Cfe are used as the memory cell of 1Tr1C. Furthermore, transistor Tr3 serves as a data read transistor. As mentioned above, capacitor Cfe is a ferroelectric capacitor. The following describes the results of performing either negative polarization writing (sometimes referred to as writing data "1") or positive polarization writing (sometimes referred to as writing data "0") to capacitor Cfe, measuring the currentIR of transistor Tr3 in each case, and then reading data.
電晶體Tr1的閘極與佈線SW連接，電晶體Tr1的源極和汲極中的一個與端子DIN連接，電晶體Tr1的源極和汲極中的另一個與電晶體Tr3的閘極連接。電晶體Tr2的閘極與佈線WLTOP連接，電晶體Tr2的源極和汲極中的一個與電容器Cfe一對電極中的一個連接。電晶體Tr2的源極和汲極中的另一個與電晶體Tr1的源極和汲極中的另一個及電晶體Tr3的閘極連接。電容器Cfe的一對電極中的另一個與佈線PL連接。電晶體Tr3的源極和汲極中的一個與電源線VDD連接，電晶體Tr3的源極和汲極中的另一個與電源線VSS連接。注意，電源線VDD被施加電位0.2V，電源線VSS被施加電位-1V。The gate of transistor Tr1 is connected to wiring SW, one of its source and drain is connected to terminal DIN, and the other of its source and drain is connected to the gate of transistor Tr3. The gate of transistor Tr2 is connected to wiring WLTOP, and one of its source and drain is connected to one of a pair of electrodes of capacitor Cfe. The other of its source and drain is connected to the other of the source and drain of transistor Tr1 and the gate of transistor Tr3. The other of the pair of electrodes of capacitor Cfe is connected to wiring PL. One of the source and drain of transistor Tr3 is connected to power line VDD, and the other of the source and drain of transistor Tr3 is connected to power line VSS. Note that a potential of 0.2 V is applied to power line VDD, and a potential of -1 V is applied to power line VSS.
接著，參照圖53A說明負的極化（data“1”）的寫入及讀出的評價方法。Next, the evaluation method for writing and reading negative polarization (data "1") will be described with reference to FIG. 53A.
首先，在期間Write Pr+中施加與想要寫入的極化相反的電位，而進行初始寫入。明確而言，將端子DIN的電位設為0V，將佈線SW及佈線WLTOP的電位設為1.2V。由此，電晶體Tr1及電晶體Tr2處於開啟狀態，電容器Cfe的一對電極中的一個的電位成為0V。在此，由於佈線PL的電位為2.5V，所以在電容器Cfe的一對電極間產生電位差，而發生極化。First, during the Write Pr+ period, an initial write is performed by applying a potential opposite to the desired polarity. Specifically, the potential at terminal DIN is set to 0V, and the potentials at wiring SW and wiring WLTOP are set to 1.2V. This turns on transistors Tr1 and Tr2, and the potential at one of the paired electrodes of capacitor Cfe becomes 0V. Here, since the potential at wiring PL is 2.5V, a potential difference is generated between the paired electrodes of capacitor Cfe, causing polarization.
接著，在期間Write Pr-中，藉由施加想要寫入的極化的電位進行寫入。明確而言，將端子DIN的電位設為2.5V，將佈線PL的電位設為0V。並且，將佈線WLTOP的電位設為1.2V。由此，發生與期間Write Pr+中發生的極化相反的極化。Next, during the Write Pr- period, data is written by applying a potential of the desired polarization. Specifically, the potential at terminal DIN is set to 2.5V, the potential at wiring PL is set to 0V, and the potential at wiring WLTOP is set to 1.2V. This generates a polarization opposite to that generated during the Write Pr+ period.
接著，在期間Reset中對佈線WLTOP施加-0.6V來使電晶體Tr2處於關閉狀態，對佈線SW施加1.2V來使電晶體Tr1處於開啟狀態，並且對端子DIN施加0V。由此，由於電晶體Tr3的閘極的電位成為0V，所以可以在期間Read的讀出工作中精確地進行記憶體的評價。Next, during the Reset phase, -0.6V is applied to line WLTOP to turn off transistor Tr2, 1.2V is applied to line SW to turn on transistor Tr1, and 0V is applied to terminal DIN. This causes the gate potential of transistor Tr3 to be 0V, enabling accurate memory evaluation during the Read phase.
接著，在期間Read中，將端子DIN的電位設為0V，將佈線SW的電位設為-0.6V，由此使電晶體Tr1處於關閉狀態。並且，藉由將佈線PL的電位設為2.5V進行讀出。Next, during the Read period, the potential of the terminal DIN is set to 0V, and the potential of the wiring SW is set to -0.6V, thereby turning off the transistor Tr1. Furthermore, the potential of the wiring PL is set to 2.5V to perform reading.
接著，參照圖53B說明正的極化（data“0”）的寫入及讀出的評價方法。Next, the evaluation method for writing and reading positive polarization (data "0") will be described with reference to FIG. 53B.
首先，在期間Write Pr-中，藉由施加與想要寫入的極化相反的電位進行初始寫入。明確而言，將端子DIN的電位設為2.5V，將佈線SW及佈線WLTOP的電位設為1.2V。由此，電晶體Tr1及電晶體Tr2處於開啟狀態，端子DIN的電位供應到電容器Cfe的一對電極中的一個。在此，由於佈線PL的電位為0V，所以在電容器Cfe的一對電極間發生極化。First, during the Write Pr- period, initial programming is performed by applying a potential opposite to the desired programming polarity. Specifically, the potential at terminal DIN is set to 2.5V, and the potentials at wiring SW and wiring WLTOP are set to 1.2V. This turns on transistors Tr1 and Tr2, and the potential at terminal DIN is supplied to one of the paired electrodes of capacitor Cfe. Since the potential at wiring PL is 0V, polarization occurs between the paired electrodes of capacitor Cfe.
接著，在期間Write Pr+中，藉由施加想要寫入的極化的電位進行寫入。明確而言，將端子DIN的電位設為0V，將佈線WLTOP的電位設為1.2V。並且，將佈線PL的電位設為2.5V。由此，發生與期間Write Pr-中發生的極化相反的極化。Next, during the Write Pr+ period, data is written by applying a potential of the desired polarization. Specifically, the potential of terminal DIN is set to 0V, the potential of wiring WLTOP is set to 1.2V, and the potential of wiring PL is set to 2.5V. This generates a polarization opposite to that generated during the Write Pr- period.
在期間Reset及期間Read中進行與data“1”的寫入及讀出同樣的工作。During the period reset and period read, the same operations as writing and reading data "1" are performed.
圖53C示出期間Read中的電流IR的波形。在圖53C中，縱向方向表示電流IR[A]，橫向方向表示時間（時間[任意單位]）。圖53C的實線表示讀出data“1”時的電流IR，圖53C的虛線表示讀出data“0”時的電流IR。Figure 53C shows the waveform of currentIR during the Read period. In Figure 53C , the vertical direction represents currentIR [A], and the horizontal direction represents time (time [arbitrary unit]). The solid line in Figure 53C represents currentIR when data "1" is read, and the dashed line in Figure 53C represents currentIR when data "0" is read.
如圖53C所示，在data“1”的讀出和data“0”的讀出的兩者中，根據佈線PL的電位的施加而發生極化反轉，由此電流IR增大。也就是說，可知：正確地進行data“1”的寫入及data“0”的寫入。另外，如圖53C所示，讀出data“1”時的IR的大小與讀出data“0”時的IR的大小明確不同。由此可知，可以正確地讀出data“1”及data“0”。如此，在具有與樣品5同樣的結構的記憶單元中正確地進行寫入工作及讀出工作。As shown in Figure 53C , when reading data "1" and data "0," polarization inversion occurs in response to the potential applied to wiring PL, increasing currentIR . This indicates that writing data "1" and writing data "0" are performed correctly. Furthermore, as shown in Figure 53C , the magnitude ofIR when reading data "1" is clearly different from the magnitude ofIR when reading data "0." This indicates that data "1" and data "0" are correctly read. Thus, writing and reading operations are performed correctly in a memory cell having the same structure as Sample 5.
本實施例可以與實施方式及其他實施例適當地組合。 實施例5This embodiment can be appropriately combined with the embodiments and other embodiments.Example 5
在本實施例中，評價電晶體的電特性。明確而言，評價電晶體的可靠性。In this embodiment, the electrical characteristics of a transistor are evaluated. Specifically, the reliability of the transistor is evaluated.
首先，說明用來評價電晶體的電特性（Id-Vg特性及可靠性）的樣品及電晶體的電特性的評價。First, we will explain the samples used to evaluate transistor electrical characteristics (Id-Vg characteristics and reliability) and the evaluation of transistor electrical characteristics.
＜電晶體的製造＞ 為了評價電晶體的電特性（Id-Vg特性及可靠性），準備樣品A及樣品B。樣品A及樣品B都包括電晶體。樣品A及樣品B中的電晶體都可以參照圖2A1至圖2D所示的電晶體200的結構。<Transistor Fabrication>To evaluate the transistor's electrical characteristics (Id-Vg characteristics and reliability), samples A and B were prepared. Both samples A and B included transistors. The transistor structures in both samples A and B can be referenced to transistor 200 shown in Figures 2A1 to 2D.
首先，藉由使用在矽酸鉿膜上利用濺射法沉積的其厚度為20nm的鎢膜及利用濺射法沉積的其厚度為20nm的ITSO膜的疊層膜，形成導電層220。鎢膜相當於導電層220_1，ITSO膜相當於導電層220_2。First, a conductive layer 220 is formed by sputtering a 20 nm thick tungsten film and a 20 nm thick ITSO film on the bismuth silicate film. The tungsten film corresponds to the conductive layer 220_1, and the ITSO film corresponds to the conductive layer 220_2.
接著，利用PEALD法沉積其厚度為5nm的第一氮化矽膜。接著，利用濺射法沉積其厚度為135nm的氧化矽膜並對其進行CMP處理，由此使氧化矽膜的頂面平坦化。藉由進行該CMP處理，形成導電層220上的其厚度為80nm的氧化矽膜。接著，利用濺射法沉積其厚度為10nm的第三氮化矽膜。如此，形成絕緣層280。Next, a first silicon nitride film is deposited to a thickness of 5 nm using the PEALD method. Next, a silicon oxide film is deposited to a thickness of 135 nm using the sputtering method and then subjected to a CMP treatment to planarize the top surface of the silicon oxide film. This CMP treatment forms an 80 nm thick silicon oxide film on the conductive layer 220. Next, a third silicon nitride film is deposited to a thickness of 10 nm using the sputtering method. In this manner, the insulating layer 280 is formed.
接著，使用利用濺射法沉積的其厚度為15nm的鎢膜形成導電層240_1，並且使用利用濺射法沉積的其厚度為10nm的ITSO膜形成導電層240_2。Next, the conductive layer 240_1 is formed using a tungsten film deposited by sputtering to a thickness of 15 nm, and the conductive layer 240_2 is formed using an ITSO film deposited by sputtering to a thickness of 10 nm.
然後，利用乾蝕刻法形成開口部290。Then, the opening 290 is formed by dry etching.
接著，使用利用熱ALD法沉積的其厚度為0.5nm的氧化鎵膜形成氧化物層227。作為包含鎵的前驅物使用三乙基鎵，作為氧化劑使用臭氧（O3）及氧（O2）。將基板加熱的溫度設為200℃。Next, a 0.5 nm thick gallium oxide film was deposited by thermal ALD to form an oxide layer 227. Triethyl gallium was used as a precursor containing gallium, and ozone (O3 ) and oxygen (O2 ) were used as oxidants. The substrate was heated at a temperature of 200°C.
接著，使用利用熱ALD法沉積的其厚度為5nm的氧化銦膜形成氧化物半導體層230_1。作為包含銦的前驅物，使用三乙基銦。另外，作為氧化劑，使用臭氧（O3）及氧（O2）。將基板加熱的溫度設為200℃。Next, a 5 nm thick indium oxide film was deposited using thermal ALD to form the oxide semiconductor layer 230_1. Triethyl indium was used as the indium precursor. Ozone (O₃ ) and oxygen (O₂ ) were used as the oxidizing agents. The substrate was heated to 200°C.
接著，使用利用RF濺射法沉積的其厚度為5nm的In-Ga-Zn氧化物膜形成氧化物半導體層230_2。另外，在沉積In-Ga-Zn氧化物膜時，使用In：Ga：Zn=1：1：1.2[原子數比]的氧化物靶材。作為沉積氣體使用氧及氬，將相對於氧和氬的流量總和的氧流量比設為90%。此外，將基板加熱的溫度設為250℃。Next, the oxide semiconductor layer 230_2 was formed using a 5 nm thick In—Ga—Zn oxide film deposited using RF sputtering. The In—Ga—Zn oxide film was deposited using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2. Oxygen and argon were used as deposition gases, with the oxygen flow rate ratio set to 90% relative to the total oxygen and argon flow rates. The substrate was heated at 250°C.
接著，使用利用熱ALD法沉積的其厚度為1nm的氧化鋁膜、利用PEALD法沉積的其厚度為2nm的氧化矽膜、利用熱ALD法沉積的其厚度為2nm的氧化鉿膜以及利用PEALD法沉積的其厚度為1nm的氮化矽膜的疊層膜，來形成絕緣層250。在沉積氧化鋁膜時，作為前驅物使用三甲基鋁，作為氧化劑使用臭氧，並且將基板加熱的溫度設為300℃。在沉積氧化矽膜時，作為前驅物使用胺基矽烷化合物，作為氧化劑使用氧，並且將基板加熱的溫度設為350℃。在沉積氧化鉿膜時，作為前驅物使用四氯化鉿，作為氧化劑使用臭氧，並且將基板加熱的溫度設為250℃。在沉積氮化矽膜時，將基板加熱的溫度設為400℃。注意，在沉積氧化鉿膜之後，進行1分鐘的微波電漿處理（處理條件：功率為4000W，處理溫度為400℃，處理壓力為400Pa）。Next, an insulating layer 250 was formed using a stacked film of an aluminum oxide film deposited to a thickness of 1 nm using thermal ALD, a silicon oxide film deposited to a thickness of 2 nm using PEALD, a cobalt oxide film deposited to a thickness of 2 nm using thermal ALD, and a silicon nitride film deposited to a thickness of 1 nm using PEALD. When depositing the aluminum oxide film, trimethylaluminum was used as a precursor, ozone was used as an oxidizer, and the substrate was heated at a temperature of 300° C. When depositing the silicon oxide film, an aminosilane compound was used as a precursor, oxygen was used as an oxidizer, and the substrate was heated at a temperature of 350° C. When depositing the cobalt oxide film, cobalt tetrachloride was used as a precursor, ozone was used as an oxidant, and the substrate was heated at 250°C. When depositing the silicon nitride film, the substrate was heated at 400°C. Note that after depositing the cobalt oxide film, a microwave plasma treatment was performed for one minute (treatment conditions: power 4000W, treatment temperature 400°C, treatment pressure 400Pa).
接著，使用利用金屬CVD法沉積的其厚度為5nm的氮化鈦膜及利用金屬CVD法沉積的其厚度為20nm的鎢膜的疊層膜，來形成導電層260。氮化鈦膜相當於導電層260_1，鎢膜相當於導電層260_2。Next, a conductive layer 260 is formed using a stacked film of a 5 nm thick titanium nitride film deposited by metal CVD and a 20 nm thick tungsten film deposited by metal CVD. The titanium nitride film corresponds to the conductive layer 260_1, and the tungsten film corresponds to the conductive layer 260_2.
由此，製造電晶體，並且還製造包括該電晶體的樣品A及樣品B。Thus, a transistor was manufactured, and samples A and B including the transistor were also manufactured.
接著，在電晶體的製造結束之後，對樣品B進行熱處理。作為該熱處理，在氮氛圍下以400℃的處理溫度進行4小時的處理。另外，上述熱處理相當於所謂的熱積存（TB）之一。另外，不對樣品A進行電晶體的製造結束後的熱處理。After transistor fabrication, Sample B was heat treated. This heat treatment was performed at 400°C for four hours in a nitrogen atmosphere. This heat treatment is considered a form of heat buildup (TB). Sample A was not subjected to this post-transistor heat treatment.
＜可靠性評價1＞ 接著，對樣品A及樣品B中的電晶體的可靠性進行評價。藉由在暗室中利用正閘極BT應力測試（也稱為Positive Bias Temperature Stress Test、+GBT應力測試），評價可靠性。在+GBT應力測試中，在對基板進行加熱的同時，將電晶體的源極電極及汲極電極設為相同電位，對閘極電極在一定時間內施加比對源極電極及汲極電極施加的電位高的電位。<Reliability Evaluation 1>Next, the reliability of the transistors in Samples A and B was evaluated. This was done using a positive gate BT stress test (also known as a positive bias temperature stress test, or +GBT stress test) in a darkroom. In the +GBT stress test, while the substrate is heated, the source and drain electrodes of the transistor are set to the same potential, and a higher potential than that applied to the source and drain electrodes is applied to the gate electrode for a certain period of time.
在本實施例的+GBT應力測試中，將設定溫度設為125℃，將汲極電位Vd及源極電位Vs設為0V，並且將閘極電位Vg設為+1.98V。注意，在本實施例中，關於樣品A及樣品B，對各兩個元件（N=2）進行應力測試。In the +GBT stress test of this embodiment, the set temperature was set to 125°C, the drain potential Vd and source potential Vs were set to 0 V, and the gate potential Vg was set to +1.98 V. Note that in this embodiment, the stress test was performed on two devices each (N = 2) for Sample A and Sample B.
在+GBT應力測試中，每隔一定時間進行Id-Vg測量。將電晶體的汲極電位Vd設為+1.2V，將源極電位Vs設為0V，並且將閘極電位Vg從-1.8V到+1.8V掃描，由此進行Id-Vg測量。另外，在Id-Vg測量中，使用是德科技製造的半導體參數分析儀。另外，在+GBT應力測試中，利用以電晶體的電特性的變動量為指標的方式表示從測量開始時的漂移電壓Vsh的變化量的ΔVsh。在本實施例中，將漂移電壓Vsh定義為Id-Vg曲線的傾斜度最大時的切線與Id=1.0×10-12A相交處的Vg的值。注意，漂移電壓Vsh是電流開始流過時的Vg的值，因此在Vsh為0或者正的值的情況下，可以將電晶體看作常關閉。因此，可以將本說明書等中記載的“漂移電壓”換稱為臨界電壓。During the +GBT stress test, Id-Vg measurements are performed at regular intervals. The transistor's drain potential (Vd) is set to +1.2V, the source potential (Vs) is set to 0V, and the gate potential (Vg) is swept from -1.8V to +1.8V. A semiconductor parameter analyzer manufactured by Keysight Technologies is used for Id-Vg measurements. Furthermore, during the +GBT stress test, the change in drift voltage (Vsh) from the start of the measurement is expressed as ΔVsh, which is an indicator of the change in the transistor's electrical characteristics. In this embodiment, drift voltage (Vsh) is defined as the Vg value at the intersection of the tangent to the Id-Vg curve at its maximum slope and Id = 1.0×10-12 A. Note that the drift voltage, Vsh, is the value of Vg at which current begins to flow. Therefore, when Vsh is 0 or a positive value, the transistor is considered normally off. Therefore, the term "drift voltage" used in this specification and other documents can be referred to as the critical voltage.
圖54A示出採用在電晶體的製造結束後不進行熱處理的條件的樣品A的+GBT應力測試的結果，圖54B示出採用在電晶體的製造結束後進行熱處理（400℃、4小時）的條件的樣品B的+GBT應力測試的結果。在圖54A及圖54B中，橫軸表示應力時間[小時]，縱軸表示ΔVsh[mV]。另外，在圖54A及圖54B中，使用黑色四邊形及白色菱形這兩個凡例示出兩個元件（N=2）的結果。Figure 54A shows the results of a +GBT stress test on sample A, which was conducted without heat treatment after transistor fabrication. Figure 54B shows the results of a +GBT stress test on sample B, which was conducted with heat treatment (400°C, 4 hours) after fabrication. In Figures 54A and 54B, the horizontal axis represents stress time [hours], and the vertical axis represents ΔVsh [mV]. In Figures 54A and 54B, the results for two devices (N = 2) are shown using two legends: black squares and white diamonds.
從圖54A可知：在樣品A中，當兩個元件在被施加上述應力的狀態下經過100小時、300小時、500小時及800小時，其漂移電壓的變化量ΔVsh的絕對值都為500mV以下，即其漂移電壓的變化量ΔVsh都為-500mV以上且500mV以下。因此可知，樣品A中的電晶體具有高可靠性。As shown in Figure 54A, in Sample A, when both devices were subjected to the aforementioned stress for 100 hours, 300 hours, 500 hours, and 800 hours, the absolute value of the drift voltage change, ΔVsh, remained below 500 mV. In other words, the drift voltage change, ΔVsh, was consistently above -500 mV and below 500 mV. This demonstrates that the transistors in Sample A have high reliability.
從圖54B可知：在樣品B中，即使兩個元件在被施加上述應力的狀態下經過100小時、300小時、500小時及800小時，其漂移電壓的變化量ΔVsh的絕對值都為300mV以下，即其漂移電壓的變化量ΔVsh都為-300mV以上且300mV以下。因此，可確認到樣品B中的電晶體具有高可靠性。尤其可確認到，與樣品A相比，樣品B的長期可靠性測試中的變化量少。可推測這是在電晶體的製造結束後的熱處理（400℃、4小時）中絕緣層250所包含的過量氧經過氧化物半導體層230被釋放到外部的結果。氧化物半導體層230附近的過量氧具有填充氧化物半導體層的氧空位的效果，但是有可能導致可靠性測試中的長期性的正向漂移劣化。因此，為了提高電晶體的可靠性，在製造電晶體時或者製造電晶體之後將過量氧釋放到外部的製程是很重要的製程之一。As shown in Figure 54B, even after both devices were subjected to the aforementioned stress for 100 hours, 300 hours, 500 hours, and 800 hours, the absolute value of the drift voltage change ΔVsh remained below 300 mV. In other words, the drift voltage change ΔVsh was consistently between -300 mV and 300 mV. Therefore, it can be confirmed that the transistor in Sample B has high reliability. In particular, Sample B exhibited less variation during long-term reliability testing than Sample A. This is presumably due to excess oxygen contained in the insulating layer 250 being released to the outside through the oxide semiconductor layer 230 during the post-transistor heat treatment (400°C for 4 hours). Excess oxygen near the oxide semiconductor layer 230 has the effect of filling oxygen vacancies in the oxide semiconductor layer, but it may cause long-term forward drift degradation during reliability testing. Therefore, to improve transistor reliability, a process to release excess oxygen to the outside during or after transistor manufacturing is one of the important processes.
也就是說，在暗室下的閘極BT應力測試中，本發明的一個實施方式的電晶體的臨界電壓的變化量為-500mV以上且500mV以下，該臨界電壓的變化量是藉由在設定溫度為125℃、汲極電位Vd及源極電位Vs為0V且閘極電位Vg為+1.98V的測量條件下經過100小時之後的Id-Vg測量算出的。尤其在樣品B中，在暗室下的閘極BT應力測試中，藉由在設定溫度為125℃、汲極電位Vd及源極電位Vs為0V且閘極電位Vg為+1.98V的測量條件下經過100小時之後的Id-Vg測量算出的臨界電壓的變化量為-300mV以上且300mV以下。That is, in a gate BT stress test in a darkroom, the variation in the critical voltage of the transistor of one embodiment of the present invention is greater than -500mV and less than 500mV. This variation in critical voltage is calculated by measuring the Id-Vg relationship after 100 hours under measurement conditions: a set temperature of 125°C, a drain potential Vd and source potential Vs of 0V, and a gate potential Vg of +1.98V. In particular, in sample B, during a gate BT stress test in a darkroom, the change in critical voltage calculated through Id-Vg measurement after 100 hours under measurement conditions with a set temperature of 125°C, drain potential Vd and source potential Vs of 0V, and gate potential Vg of +1.98V was greater than -300mV and less than 300mV.
＜可靠性評價2＞ 接著，在樣品B所包括的電晶體中，藉由+GBT應力測試中得到的每隔一定時間的Id-Vg測量算出臨界電壓Vth，並且作為電晶體的電特性的變動量的指標利用表示從測量開始時的臨界電壓Vth的變化量的ΔVth。注意，本評價示出上述應力測試之後還進行更長時間的應力測試的結果。<Reliability Evaluation 2>Next, for the transistors included in Sample B, the critical voltage (Vth) was calculated from Id-Vg measurements taken at regular intervals during the +GBT stress test. ΔVth, representing the change in critical voltage (Vth) from the start of the measurement, was used as an indicator of the variation in the transistor's electrical characteristics. Note that this evaluation shows the results of a further stress test conducted after the aforementioned stress test.
在橫軸標繪閘極電位Vg且縱軸標繪汲極電流Id的平方根的曲線（Vg-√Id特性）中，臨界電壓Vth算出為外插傾斜度最大的切線時的直線與汲極電流Id的平方根為0（Id=0A）時的交點處的閘極電位Vg。作為閘極電位Vg及汲極電流Id，利用樣品B的+GBT應力測試中每隔一定時間測量的Id-Vg測量的資料。In the curve (Vg-√Id characteristic) with gate potential Vg plotted on the horizontal axis and the square root of drain current Id plotted on the vertical axis, the critical voltage Vth is calculated as the gate potential Vg at the intersection of the straight line with the maximum extrapolated tangent line and the square root of drain current Id equal to 0 (Id = 0A). The gate potential Vg and drain current Id are measured using Id-Vg data at regular intervals during the +GBT stress test of sample B.
圖58示出作為樣品B中的電晶體的+GBT應力測試的結果的ΔVth的應力時間依賴性。橫軸表示應力時間[小時]，縱軸表示ΔVth[mV]。可知：即使在應力時間超過1000小時的情況下，臨界電壓Vth的變動量也小，ΔVth被抑制為-200mV以上且0V以下的範圍內。此外，還可知ΔVth的絕對值被抑制為200mV以下。換言之，在應力時間達到1700小時之前ΔVth的變動量為±100mV的範圍內。如上所述，樣品B中的電晶體具有高可靠性。Figure 58 shows the stress-time dependence of ΔVth, the result of a +GBT stress test on the transistor in Sample B. The horizontal axis represents stress time [hours], and the vertical axis represents ΔVth [mV]. It can be seen that even when the stress time exceeds 1000 hours, the fluctuation in critical voltage Vth is small, with ΔVth suppressed to a range of -200 mV to 0 V. Furthermore, the absolute value of ΔVth is suppressed to below 200 mV. In other words, the fluctuation in ΔVth remains within a range of ±100 mV until the stress time reaches 1700 hours. As described above, the transistor in Sample B has high reliability.
本實施例所示的組件、結構或方法等可以與其他實施方式等所示的組件、結構或方法等適當地組合而使用。 實施例6The components, structures, and methods described in this embodiment may be used in combination with components, structures, and methods described in other embodiments, as appropriate.Example 6
在本實施例中，藉由計算對OS電晶體的埋入通道結構進行評價。明確而言，使圖4A所示的氧化物半導體層230_1的能帶間隙變化並對其進行器件模擬。注意，在器件模擬中，參照評價氧化物膜的能帶間隙及氧化物膜間的能帶偏移的結果。In this embodiment, the buried channel structure of the OS transistor was evaluated through calculations. Specifically, the band gap of the oxide semiconductor layer 230_1 shown in FIG4A was varied and device simulations were performed. Note that the device simulations referenced the results of evaluating the band gap of the oxide film and the band offset between oxide films.
在此，說明評價氧化物膜的能帶間隙及氧化物膜間的能帶偏移的結果。Here, the results of evaluating the band gap of oxide films and the band offset between oxide films are described.
首先，製造包括氧化物膜的樣品（樣品6A及樣品6B），評價氧化物膜的能帶間隙。First, samples including oxide films (Sample 6A and Sample 6B) were produced, and the band gaps of the oxide films were evaluated.
在樣品6A中，在矽基板上利用ALD法沉積其厚度為20nm的第一氧化物膜。沉積第一氧化物膜時使用的前驅物是三乙基鎵。另外，作為氧化劑，使用臭氧（O3）及氧（O2）的混合氣體。也就是說，第一氧化物膜是利用ALD法沉積的氧化鎵膜，因此有時將第一氧化物膜記為ALD-GaOx。In sample 6A, a 20nm-thick first oxide film was deposited on a silicon substrate using the ALD method. The precursor used for depositing the first oxide film was triethylgallium. A mixed gas of ozone (O₃ ) and oxygen (O₂ ) was used as the oxidizing agent. In other words, the first oxide film is a gallium oxide film deposited using the ALD method, and is therefore sometimes referred to as ALD-GaOx.
在樣品6B中，在矽基板上利用濺射法沉積其厚度為20nm的第三氧化物膜。在沉積第三氧化物膜時，使用In：Ga：Zn=1：1：1.2[原子數比]的氧化物靶材。作為沉積氣體使用氧及氬，並且將相對於氧及氬的流量總和的氧流量比設為90%。此外，將基板加熱的溫度設為250℃。由此，第三氧化物膜的組成成為In：Ga：Zn=1：1：1[原子數比]或其附近。第三氧化物膜是利用濺射法沉積的In-Ga-Zn膜，因此有時將第三氧化物膜記為SP-IGZO。In sample 6B, a 20nm-thick third oxide film was deposited on a silicon substrate using a sputtering method. An oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2 was used for deposition. Oxygen and argon were used as deposition gases, with the oxygen flow rate ratio set to 90% relative to the combined oxygen and argon flow rates. Furthermore, the substrate was heated to a temperature of 250°C. This resulted in a composition of the third oxide film with an atomic ratio of In:Ga:Zn = 1:1:1 or approximately thereabouts. Because the third oxide film is an In-Ga-Zn film deposited using the sputtering method, it is sometimes referred to as SP-IGZO.
接著，利用全自動光譜橢圓偏光計“UT-300”測量樣品6A及樣品6B各自的氧化物膜的能隙。Next, the band gap of the oxide films of Samples 6A and 6B was measured using a fully automatic spectroscopic ellipsoidal polarimeter "UT-300".
從光譜橢偏術的結果可知，樣品6A的能帶間隙為4.232eV，樣品6B的能帶間隙為3.144eV。Spectroscopic ellipsometry results show that the band gap of sample 6A is 4.232 eV, and the band gap of sample 6B is 3.144 eV.
接著，製造層疊有兩個氧化物膜的樣品（樣品6C及樣品6D），評價氧化物膜間的能帶偏移。Next, samples with two oxide films stacked on top of each other (Sample 6C and Sample 6D) were fabricated, and the band offset between the oxide films was evaluated.
在樣品6C中，在矽基板上利用ALD法沉積其厚度為20nm的第一氧化物膜。作為第一氧化物膜的沉積條件，可以參照樣品6A中說明的內容。然後，在第一氧化物膜上利用ALD法沉積其厚度為3nm的第二氧化物膜。沉積第二氧化物膜時使用的前驅物是三乙基銦。此外，作為氧化劑，使用臭氧（O3）及氧（O2）的混合氣體。也就是說，第二氧化物膜是利用ALD法沉積的氧化銦膜，因此有時將第二氧化物膜記為ALD-InOx。In sample 6C, a 20nm-thick first oxide film was deposited on a silicon substrate using ALD. The deposition conditions for the first oxide film are similar to those described for sample 6A. A 3nm-thick second oxide film was then deposited on the first oxide film using ALD. The precursor used for depositing the second oxide film was triethylindium. Furthermore, a mixed gas of ozone (O₃ ) and oxygen (O₂ ) was used as the oxidizing agent. In other words, the second oxide film is an indium oxide film deposited using ALD, and is therefore sometimes referred to as ALD-InOx.
在樣品6D中，在矽基板上利用ALD法沉積其厚度為20nm的第二氧化物膜。作為第二氧化物膜的沉積條件，可以參照樣品6C中說明的內容。接著，在第二氧化物膜上利用濺射法沉積其厚度為3nm的第三氧化物膜。作為第三氧化物膜的沉積條件，可以參照樣品6B中說明的內容。In sample 6D, a 20nm-thick second oxide film was deposited on a silicon substrate using ALD. The deposition conditions for the second oxide film can be found in the description for sample 6C. Next, a 3nm-thick third oxide film was deposited on the second oxide film using sputtering. The deposition conditions for the third oxide film can be found in the description for sample 6B.
對樣品6C及樣品6D進行XPS分析。在XPS分析中使用PHI公司製造的QuanteraII。作為X射線源使用單色化的Al Kα射線（1486.6eV）。將檢測區域設為100μmφ。提取角為90°。檢測深度推測為8nm左右。XPS analysis was performed on samples 6C and 6D using a Quantera II manufactured by PHI. Monochromatic Al Kα radiation (1486.6 eV) was used as the X-ray source. The detection area was set to 100 μm φ, the extraction angle was 90°, and the detection depth was estimated to be approximately 8 nm.
從XPS分析可知，第一氧化物膜的價帶頂與第二氧化物膜的價帶頂的能量差為0.45eV，第二氧化物膜的價帶頂與第三氧化物膜的價帶頂的能量差為0.21eV。XPS analysis shows that the energy difference between the valence band top of the first oxide film and the valence band top of the second oxide film is 0.45 eV, and the energy difference between the valence band top of the second oxide film and the valence band top of the third oxide film is 0.21 eV.
利用上述結果製造能帶圖。圖55是所製造的能帶圖。在圖55中，縱軸表示能量，橫向方向表示各樣品。此外，圖55中的VBM表示價帶頂，圖55中的CBM表示導帶底。注意，在圖55中，第二氧化物膜的能帶間隙假設為3.0eV。Using these results, an energy band diagram was created. Figure 55 shows the resulting energy band diagram. In Figure 55 , the vertical axis represents energy, and the horizontal axis represents each sample. Furthermore, VBM in Figure 55 represents the valence band top, and CBM in Figure 55 represents the conduction band bottom. Note that in Figure 55 , the band gap of the second oxide film is assumed to be 3.0 eV.
另外，在矽基板上利用濺射法沉積其厚度為20nm的第四氧化物膜，由此製造樣品6E。在沉積第四氧化物膜時，使用In：Ga：Zn=1：3：2[原子數比]的氧化物靶材。作為沉積氣體使用氧及氬，將相對於氧及氬的流量總和的氧流量比設為20%。由此，第四氧化物膜的組成成為In：Ga：Zn=1：3：2[原子數比]或其附近。另外，將基板加熱的溫度設為250℃。從對於樣品6E的光譜橢偏術的結果可知，樣品6E的能帶間隙為3.245eV。Separately, a 20nm-thick fourth oxide film was deposited on a silicon substrate using a sputtering method, producing sample 6E. An oxide target with an atomic ratio of In:Ga:Zn = 1:3:2 was used for the deposition of the fourth oxide film. Oxygen and argon were used as deposition gases, with the oxygen flow rate ratio set to 20% relative to the combined oxygen and argon flow rates. This resulted in a composition of In:Ga:Zn = 1:3:2 or approximately 1:3:2. Furthermore, the substrate was heated at a temperature of 250°C. Spectroscopic ellipsometry of sample 6E revealed a band gap of 3.245 eV.
另外，在矽基板上利用ALD法沉積其厚度為20nm的第二氧化物膜，並在第二氧化物膜上利用濺射法沉積其厚度為3nm的第四氧化物膜，由此製造樣品6F。作為第二氧化物膜的沉積條件，可以參照樣品6C中說明的內容，作為第四氧化物膜的沉積條件，可以參照樣品6E中說明的內容。Separately, a second oxide film was deposited to a thickness of 20 nm on a silicon substrate using ALD, and a fourth oxide film was deposited to a thickness of 3 nm on the second oxide film using sputtering, thereby producing Sample 6F. The deposition conditions for the second oxide film refer to those described for Sample 6C, and the deposition conditions for the fourth oxide film refer to those described for Sample 6E.
從對於樣品6F的XPS分析的結果可知，第二氧化物膜的價帶頂與第四氧化物膜的價帶頂的能量差為0.20eV。From the results of XPS analysis of sample 6F, it can be seen that the energy difference between the valence band top of the second oxide film and the valence band top of the fourth oxide film is 0.20 eV.
由此，第四氧化物膜的能帶間隙比第三氧化物膜的能帶間隙大，並且第二氧化物膜的價帶頂與第四氧化物膜的價帶頂的能量差大致相等於第二氧化物膜的價帶頂與第三氧化物膜的價帶頂的能量差。因此可知，第四氧化物膜的導帶底位於比第三氧化物膜的導帶底更靠近真空能階一側。Therefore, the band gap of the fourth oxide film is larger than that of the third oxide film, and the energy difference between the valence band top of the second oxide film and the valence band top of the fourth oxide film is approximately equal to the energy difference between the valence band top of the second oxide film and the valence band top of the third oxide film. Therefore, it can be seen that the conduction band bottom of the fourth oxide film is located closer to the vacuum level than the conduction band bottom of the third oxide film.
接著，說明OS電晶體的埋入通道結構的計算。Next, the calculation of the buried channel structure of the OS transistor is explained.
用於計算的OS電晶體的結構可以參照圖4A。注意，在本計算中，作為絕緣層250採用第四絕緣層、第四絕緣層上的第三絕緣層、第三絕緣層上的第一絕緣層以及第一絕緣層上的第二絕緣層的四層結構。此外，在本計算中，假設採用如下結構：氧化物層227只設置在開口部290的側壁。The structure of the OS transistor used in the calculations can be seen in Figure 4A. Note that in this calculation, a four-layer structure is employed as insulating layer 250: a fourth insulating layer, a third insulating layer on top of the fourth insulating layer, a first insulating layer on top of the third insulating layer, and a second insulating layer on top of the first insulating layer. Furthermore, this calculation assumes that oxide layer 227 is provided only on the sidewalls of opening 290.
在計算中，使用Synopsys公司的Sentaurus。表1及表2示出用於計算的參數的詳細內容。在本計算中，假設如下條件：作為氧化物層227使用氧化鎵，作為氧化物半導體層230_1使用氧化銦，作為氧化物半導體層230_2使用In：Ga：Zn=1：1：1[原子數比]或其附近的組成的In-Ga-Zn氧化物。The calculations were performed using Synopsys' Sentaurus. Tables 1 and 2 show the details of the parameters used for the calculations. This calculation assumes the following conditions: gallium oxide is used as oxide layer 227, indium oxide is used as oxide semiconductor layer 230_1, and In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or a similar composition is used as oxide semiconductor layer 230_2.
[表1][Table 1]
[表2][Table 2]
表1所示的Eg是指氧化物半導體層230_1的能帶間隙。在本計算中，使Eg從2.5eV到3.3eV每隔0.1eV變化。此外，表1及表2所示的χ230_1是指氧化物半導體層230_1的電子親和力。Eg shown in Table 1 refers to the energy band gap of oxide semiconductor layer 230_1. In this calculation, Eg was varied from 2.5 eV to 3.3 eV in 0.1 eV increments. Furthermore, χ230_1 shown in Tables 1 and 2 refers to the electron affinity of oxide semiconductor layer 230_1.
圖56A至圖57C2示出計算結果。Figures 56A to 57C2 show the calculation results.
圖56A是說明OS電晶體的通態電流的Eg依賴性的圖。在圖56A中，縱軸表示通態電流Ion[μA]，橫軸表示氧化物半導體層230_1的能帶間隙Eg[eV]。注意，通態電流Ion是指汲極電位Vd為1.2V的Id-Vg特性中的Vg=Vsh+2.5V時的汲極電流的值。另外，在本實施例中，漂移電壓Vsh算出為汲極電位Vd為1.2V的Id-Vg特性中的汲極電流Id成為1pA時的閘極電位Vg的值。FIG56A illustrates the dependence of the on-state current of the OS transistor on Eg. In FIG56A, the vertical axis represents the on-state current Ion [μA], and the horizontal axis represents the energy band gap Eg [eV] of the oxide semiconductor layer 230_1. Note that the on-state current Ion refers to the drain current value when Vg = Vsh + 2.5V in the Id-Vg characteristic with a drain potential Vd of 1.2V. In this embodiment, the drift voltage Vsh is calculated as the gate potential Vg value at which the drain current Id reaches 1pA in the Id-Vg characteristic with a drain potential Vd of 1.2V.
圖56B是說明OS電晶體的漂移電壓的Eg依賴性的圖。在圖56B中，縱軸表示漂移電壓Vsh[V]，橫軸表示氧化物半導體層230_1的能帶間隙Eg[eV]。FIG56B is a graph illustrating the Eg dependence of the drift voltage of the OS transistor. In FIG56B , the vertical axis represents the drift voltage Vsh [V], and the horizontal axis represents the energy band gap Eg [eV] of the oxide semiconductor layer 230_1.
圖56C是說明OS電晶體的次臨界擺幅值（也稱為S值）的Eg依賴性的圖。在圖56C中，縱軸表示S值[mV/dec]，橫軸表示氧化物半導體層230_1的能帶間隙Eg[eV]。另外，在汲極電位Vd為1.2V的Id-Vg特性中的汲極電流Id成為1pA的點算出S值。Figure 56C illustrates the dependence of the subcritical swing value (also called the S value) of the OS transistor on Eg. In Figure 56C, the vertical axis represents the S value [mV/dec], and the horizontal axis represents the band gap Eg [eV] of the oxide semiconductor layer 230_1. The S value was calculated at the point where the drain current Id reaches 1 pA in the Id-Vg characteristic at a drain potential Vd of 1.2 V.
從圖56A可知，在氧化物半導體層230_1的能帶間隙Eg大於3.0eV時通態電流Ion降低。As can be seen from FIG. 56A , when the energy band gap Eg of the oxide semiconductor layer 230_1 is greater than 3.0 eV, the on-state current Ion decreases.
從圖56B可知，氧化物半導體層230_1的能帶間隙Eg越小漂移電壓Vsh越小，OS電晶體的電特性負向漂移。As shown in FIG. 56B , the smaller the band gap Eg of the oxide semiconductor layer 230_1, the smaller the drift voltage Vsh, and the electrical characteristics of the OS transistor drift negatively.
從圖56C可知，S值是一定的值而不依賴於氧化物半導體層230_1的能帶間隙。As can be seen from FIG. 56C , the S value is constant and does not depend on the energy band gap of the oxide semiconductor layer 230_1.
圖57A1至圖57C2是通態電流流過時的帶圖。圖57A1至圖57C2是開口部290的側壁部分的帶圖。圖57A2至圖57C2分別是圖57A1至圖57C1的放大圖，並分別是放大導帶底（CBM）、費米能階（FL）及它們附近的帶圖。圖57A1及圖57A2是氧化物半導體層230_1的能帶間隙為3.0eV時的結果，圖57B1及圖57B2是氧化物半導體層230_1的能帶間隙為3.1eV時的結果，圖57C1及圖57C2是氧化物半導體層230_1的能帶間隙為3.2eV時的結果。Figures 57A1 to 57C2 are band diagrams when on-state current flows. Figures 57A1 to 57C2 are band diagrams of the sidewall portion of opening 290. Figures 57A2 to 57C2 are enlarged views of Figures 57A1 to 57C1, respectively, showing enlarged views of the conduction band bottom (CBM), Fermi level (FL), and their vicinities. Figures 57A1 and 57A2 show the results when the band gap of oxide semiconductor layer 230_1 is 3.0 eV, Figures 57B1 and 57B2 show the results when the band gap of oxide semiconductor layer 230_1 is 3.1 eV, and Figures 57C1 and 57C2 show the results when the band gap of oxide semiconductor layer 230_1 is 3.2 eV.
從圖57A1及圖57A2可知，在氧化物半導體層230_1的能帶間隙為3.0eV的情況下，氧化物半導體層230_1的費米能階位於導帶底上，氧化物半導體層230_1中形成有通道。也就是說，可認為OS電晶體被用作埋入通道。As shown in Figures 57A1 and 57A2 , when the band gap of oxide semiconductor layer 230_1 is 3.0 eV, the Fermi level of oxide semiconductor layer 230_1 is above the conduction band bottom, and a channel is formed in oxide semiconductor layer 230_1. In other words, the OS transistor can be considered to be used as a buried channel.
從圖57B1及圖57B2可知，在氧化物半導體層230_1的能帶間隙為3.1eV的情況下，氧化物半導體層230_2及氧化物半導體層230_1的兩者的費米能階位於導帶底上，兩者中形成有通道。也就是說，可認為OS電晶體在埋入通道和表面通道混合存在的狀態下工作。As shown in Figures 57B1 and 57B2 , when the band gap of oxide semiconductor layer 230_1 is 3.1 eV, the Fermi levels of both oxide semiconductor layer 230_2 and oxide semiconductor layer 230_1 are above the conduction band bottom, forming a channel between them. In other words, the OS transistor can be considered to operate with a mixed presence of buried and surface channels.
從圖57C1及圖57C2可知，在氧化物半導體層230_1的能帶間隙為3.2eV的情況下，氧化物半導體層230_2的費米能階位於導帶底上，氧化物半導體層230_2中形成有通道。也就是說，可認為OS電晶體被用作表面通道。As shown in Figures 57C1 and 57C2 , when the band gap of oxide semiconductor layer 230_1 is 3.2 eV, the Fermi level of oxide semiconductor layer 230_2 is above the conduction band bottom, and a channel is formed in oxide semiconductor layer 230_2 . In other words, the OS transistor can be considered to be used as a surface channel.
由此可知，在氧化物半導體層230_1的能帶間隙為2.5eV以上且3.0eV以下的情況下，氧化物半導體層230_1與氧化物半導體層230_2間設置有充分的能帶偏移，OS電晶體被用作埋入通道。另外，還可知在氧化物半導體層230_1的能帶間隙為3.1eV的情況下，OS電晶體在埋入通道和表面通道混合存在的狀態下工作。另外，還可知在氧化物半導體層230_1的能帶間隙為3.2eV以上且3.3eV以下的情況下，設置在氧化物半導體層230_1與氧化物半導體層230_2間的能帶偏移變小，OS電晶體被用作表面通道。另外，用作表面通道的OS電晶體中通態電流Ion降低的原因推測為電流流在移動率低的氧化物半導體層230_2中。This indicates that when the band gap of the oxide semiconductor layer 230_1 is greater than 2.5 eV and less than 3.0 eV, a sufficient band offset is provided between the oxide semiconductor layer 230_1 and the oxide semiconductor layer 230_2, and the OS transistor functions as a buried channel. Furthermore, when the band gap of the oxide semiconductor layer 230_1 is 3.1 eV, the OS transistor operates with a mixed state of buried and surface channels. Furthermore, when the band gap of the oxide semiconductor layer 230_1 is greater than 3.2 eV and less than 3.3 eV, the band offset between the oxide semiconductor layer 230_1 and the oxide semiconductor layer 230_2 decreases, and the OS transistor functions as a surface channel. In addition, the reason why the on-state current Ion of the OS transistor used as a surface channel decreases is presumably because the current flows in the oxide semiconductor layer 230_2 with low mobility.
因此，包括包含氧化鎵的氧化物層227及包含能帶間隙為3.0eV以下的氧化銦的氧化物半導體層230_1以及包含In：Ga：Zn=1：1：1[原子數比]或其附近的組成的In-Ga-Zn氧化物的氧化物半導體層230_2的OS電晶體可以實現埋入通道。另外，如上所述，In：Ga：Zn=1：3：2[原子數比]或其附近的組成的In-Ga-Zn氧化物的導帶底位於比In：Ga：Zn=1：1：1[原子數比]或其附近的組成的In-Ga-Zn氧化物的導帶底更靠近真空能階一側，因此包括包含In：Ga：Zn=1：3：2[原子數比]或其附近的組成的In-Ga-Zn氧化物的氧化物層227、包含能帶間隙為3.0eV以下的氧化銦的氧化物半導體層230_1以及包含In：Ga：Zn=1：1：1[原子數比]或其附近的組成的In-Ga-Zn氧化物的氧化物半導體層230_2的OS電晶體也可以實現埋入通道。Therefore, the OS transistor including the oxide layer 227 containing gallium oxide, the oxide semiconductor layer 230_1 containing indium oxide with a band gap of less than 3.0 eV, and the oxide semiconductor layer 230_2 containing In-Ga-Zn oxide with a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a near-real-time ratio can realize a buried channel. In addition, as described above, the conduction band bottom of the In-Ga-Zn oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or thereabouts is located closer to the vacuum energy level than the conduction band bottom of the In-Ga-Zn oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or thereabouts. Therefore, the OS transistor including the oxide layer 227 comprising the In-Ga-Zn oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or thereabouts, the oxide semiconductor layer 230_1 comprising indium oxide having a band gap of less than 3.0 eV, and the oxide semiconductor layer 230_2 comprising the In-Ga-Zn oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or thereabouts can also realize a buried channel.
另外，在氧化物半導體層230_1的能帶間隙為2.5eV以上且3.0eV以下的情況下，氧化物半導體層230_2與氧化物半導體層230_1的能帶偏移為0.35eV以上且0.85eV以下。另外，在氧化物半導體層230_1的能帶間隙為3.1eV的情況下，氧化物半導體層230_2與氧化物半導體層230_1的能帶偏移為0.25eV。另外，在氧化物半導體層230_1的能帶間隙為3.2eV的情況下，氧化物半導體層230_2與氧化物半導體層230_1的能帶偏移為0.15eV。因此，為了將OS電晶體用作埋入通道，氧化物半導體層230_2與氧化物半導體層230_1的能帶偏移較佳為0.2eV以上，更佳為0.3eV以上，進一步較佳為0.35eV以上。此外，為了增大漂移電壓Vsh，氧化物半導體層230_2與氧化物半導體層230_1的能帶偏移較佳為0.85eV以下，更佳為0.5eV以下。如上所述，氧化物半導體層230_2與氧化物半導體層230_1的能帶偏移較佳為0.2eV以上且0.85eV以下，更佳為0.3eV以上且0.85eV以下，更佳為0.3eV以上且0.5eV以下，進一步較佳為0.35eV以上且0.5eV以下。Furthermore, when the band gap of the oxide semiconductor layer 230_1 is greater than or equal to 2.5 eV and less than or equal to 3.0 eV, the band gap offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is greater than or equal to 0.35 eV and less than or equal to 0.85 eV. Furthermore, when the band gap of the oxide semiconductor layer 230_1 is 3.1 eV, the band gap offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is 0.25 eV. Furthermore, when the band gap of the oxide semiconductor layer 230_1 is 3.2 eV, the band gap offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is 0.15 eV. Therefore, to use the OS transistor as a buried channel, the band offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is preferably greater than 0.2 eV, more preferably greater than 0.3 eV, and even more preferably greater than 0.35 eV. Furthermore, to increase the drift voltage Vsh, the band offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is preferably less than 0.85 eV, and even more preferably less than 0.5 eV. As described above, the energy band offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is preferably 0.2 eV to 0.85 eV, more preferably 0.3 eV to 0.85 eV, even more preferably 0.3 eV to 0.5 eV, and even more preferably 0.35 eV to 0.5 eV.
本實施例所示的組件、結構、方法等可以與其他實施方式等所示的組件、結構、方法等適當地組合而使用。The components, structures, methods, etc. shown in this embodiment can be used in combination with the components, structures, methods, etc. shown in other embodiments as appropriate.
61B:發光元件61G:發光元件61R:發光元件61W:發光元件100:電容器100a:電容器100b:電容器110:導電層115:導電層130:絕緣層130B:子像素130G:子像素130R:子像素140:絕緣層150:記憶單元150a:記憶單元150b:記憶單元150c:記憶單元150d:記憶單元160[2]:記憶體層160[n]:記憶體層160:記憶體層170:顯示模組171:導電層172B:EL層172G:EL層172R:EL層172W:EL層173:導電層175B:光175G:光175R:光180:絕緣層185:絕緣層190:開口部200:電晶體200A:電晶體200a:電晶體200B:電晶體200b:電晶體200C:電晶體210:絕緣層220:導電層220_1:導電層220_11:導電層220_12:導電層220_2:導電層220a:導電層220b:導電層225:絕緣層225_1:絕緣層225_2:絕緣層227:氧化物層230:氧化物半導體層230_1:氧化物半導體層230_2:氧化物半導體層230_3:氧化物半導體層230a:氧化物半導體層230b:氧化物半導體層240:導電層240_1:導電層240_2:導電層240a:導電層240b:導電層245:導電層246:導電層247:導電層250:絕緣層255:導電層260:導電層260_1:導電層260_2:導電層260b:導電層264B:彩色層264G:彩色層264R:彩色層265:導電層270:開口部271:保護層272:絕緣層280:絕緣層280_1:絕緣層280_2:絕緣層280_3:絕緣層280a:絕緣層280b:絕緣層281:絕緣層281_1:絕緣層281_2:絕緣層281_3:絕緣層283:絕緣層284:絕緣層285:絕緣層286:絕緣層290:開口部290a:開口部291:基板292:電路部293:像素電路部293a:像素電路294:像素部294a:像素295:端子部296:佈線部297:顯示部298:FPC299:基板300:電晶體311:基板313:半導體區域314a:低電阻區域314b:低電阻區域315:絕緣層316:導電層320:絕緣層322:絕緣層324:絕緣層326:絕緣層328:導電層330:導電層350:絕緣層352:絕緣層354:絕緣層356:導電層363:絕緣層400d:電晶體410:基板412:元件分離層413:半導體區域414a:低電阻區域414b:低電阻區域415:絕緣層416:導電層417:絕緣層420:絕緣層422:絕緣層424:絕緣層426:絕緣層428:導電層430:導電層450:絕緣層452:絕緣層454:絕緣層456:導電層513:絕緣層514:導電層541:基板543:黏合層545:絕緣層574:絕緣層581:絕緣層592:絕緣層594:絕緣層596:導電層598:絕緣層599:絕緣層600A:顯示裝置600B:顯示裝置607:黏合層610:基板611a:導電層611b:導電層611c:導電層613a:層613b:層613c:層614:共用層615:共用電極618a:犧牲層620:元件層625:絕緣層627:絕緣層628B:彩色層628G:彩色層628R:彩色層630:元件層631:保護層635:元件層640:連接部642:導電層643:導電層644:導電層645:導電層646:導電層648:絕緣層650:發光元件650B:發光元件650G:發光元件650R:發光元件660:元件層670:佈線層700A:電子裝置710:半導體裝置721:外殼723:安裝部730:電子構件731:插板732:封裝基板733:電極735:半導體裝置750:耳機751:顯示面板753:光學構件756:顯示區域757:邊框758:鼻墊800A:電子裝置800B:電子裝置820:顯示部821:外殼822:通訊部823:安裝部824:控制部825:成像部827:耳機部832:透鏡840:顯示裝置840_L:顯示裝置840_R:顯示裝置841:運動檢測部842:視線檢測部843:運算部844:通訊部845:外殼848:透鏡850A:電子裝置850B:電子裝置851:操作按鈕854:安裝工具855:感測器856:刻度盤900:半導體裝置910:驅動電路911:周圍電路912:控制電路915:周圍電路920:記憶體陣列923:行驅動器924:列驅動器925:輸入電路926:輸出電路927:感測放大器928:電壓生成電路930:層931:PSW932:PSW941:行解碼器942:列解碼器950:記憶單元951:記憶單元952:記憶體裝置953:記憶單元954:記憶單元955:記憶單元956:記憶單元957:記憶單元960:運算裝置970A:半導體裝置970B:半導體裝置970C:半導體裝置989:快取介面990:基板991:ALU992:ALU控制器993:指令解碼器994:中斷控制器995:時序控制器996:暫存器997:暫存器控制器998:匯流排介面999:快取3102:電晶體3104:電晶體3110:電子構件3111:模子3112:記憶體裝置3113:連接盤3114:電極焊盤3115:引線3121:層3122:層3210:安裝基板3212:印刷電路板3301:電晶體3302:電晶體3311:半導體層3312:半導體層5600:大型電腦5610:機架5620:電腦5621:個人電腦卡5622:板5623:連接端子5624:連接端子5625:連接端子5626:半導體裝置5627:半導體裝置5628:半導體裝置5629:連接端子5630:主機板5631:插槽6500:電子裝置6501:外殼6502:顯示部6503:電源按鈕6504:按鈕6505:揚聲器6506:麥克風6507:照相機6508:光源6509:控制裝置6510:保護構件6511:顯示面板6512:光學構件6513:觸控感測器面板6515:FPC6516:IC6517:印刷電路板6518:電池6519:連接端子6520:電子裝置6800:人造衛星6801:主體6802:太陽能電池板6803:天線6804:惑星6805:二次電池6807:控制裝置7000:顯示部7001:主機7001sb:伺服器7002:儲存控制電路7003:儲存7003md:記憶體裝置7004:儲存區域網路7010:儲存系統7100:電視機7101:外殼7103:支架7111:遙控器7200:膝上型個人電腦7211:外殼7212:鍵盤7213:指向裝置7214:外部連接埠7215:控制裝置7300:數位看板7301:外殼7303:揚聲器7311:資訊終端設備7400:數位看板7401:柱7411:資訊終端設備9000:外殼9000a:外殼9000b:外殼9001:顯示部9001a:顯示面板9001b:顯示面板9001c:顯示面板9001d:顯示面板9003:揚聲器9005:操作鍵9006:連接端子9007:感測器9008:麥克風9055:鉸鏈9056:操作按鈕9200:可攜式資訊終端9201:可攜式資訊終端9202:可攜式資訊終端61B: Light-emitting element61G: Light-emitting element61R: Light-emitting element61W: Light-emitting element100: Capacitor100a: Capacitor100b: Capacitor110: Conductive layer115: Conductive layer130: Insulating layer130B: Sub-pixel130G: Sub-pixel130R: Sub-pixel140: Insulating layer150: Memory cell150a: Memory cell150b: Memory cell150c: Memory cell150d: Memory cell160[2]: Memory layer160[n]: Memory layer160: Memory layer170: Display Module171: Conductive layer172B: EL layer172G: EL layer172R: EL layer172W: EL layer173: Conductive layer175B: Light175G: Light175R: Light180: Insulating layer185: Insulating layer190: Opening200: Transistor200A: Transistor200a: Transistor200B: Transistor200b: Transistor200C: Transistor210: Insulating layer220: Conductive layer220_1: Conductive layer220_11: Conductive layer220_12: Conductive layer220_2: Conductive Layer220a: Conductive layer220b: Conductive layer225: Insulating layer225_1: Insulating layer225_2: Insulating layer227: Oxide layer230: Oxide semiconductor layer230_1: Oxide semiconductor layer230_2: Oxide semiconductor layer230_3: Oxide Oxide semiconductor layer230a: Oxide semiconductor layer230b: Oxide semiconductor layer240: Conductive layer240_1: Conductive layer240_2: Conductive layer240a: Conductive layer240b: Conductive layer245: Conductive layer246: Conductive layer247: Conductive layer25 0: Insulating layer255: Conductive layer260: Conductive layer260_1: Conductive layer260_2: Conductive layer260b: Conductive layer264B: Color layer264G: Color layer264R: Color layer265: Conductive layer270: Opening271: Protective layer272 :Insulating layer280:Insulating layer280_1:Insulating layer280_2:Insulating layer280_3:Insulating layer280a:Insulating layer280b:Insulating layer281:Insulating layer281_1:Insulating layer281_2:Insulating layer281_3:Insulating layer283:Insulating Layers284: Insulating layer285: Insulating layer286: Insulating layer290: Opening290a: Opening291: Substrate292: Circuit293: Pixel circuit293a: Pixel circuit294: Pixel294a: Pixel295: Terminal296: Wiring297: Display298: FPC299: Substrate300: Transistor311: Substrate313: Semiconductor region314a: Low resistance region314b: Low resistance region315: Insulating layer316: Conductive layer320: Insulating layer322: Insulating Insulation layer324: Insulation layer326: Insulation layer328: Conductive layer330: Conductive layer350: Insulation layer352: Insulation layer354: Insulation layer356: Conductive layer363: Insulation layer400d: Transistor410: Substrate412: Component isolation layer413 : Semiconductor region414a: Low resistance region414b: Low resistance region415: Insulating layer416: Conductive layer417: Insulating layer420: Insulating layer422: Insulating layer424: Insulating layer426: Insulating layer428: Conductive layer430: Conductive layer450: Insulating layer452: Insulating layer454: Insulating layer456: Conductive layer513: Insulating layer514: Conductive layer541: Substrate543: Adhesive layer545: Insulating layer574: Insulating layer581: Insulating layer592: Insulating layer594: Insulating layer596: Conductive Electrical layer598: Insulating layer599: Insulating layer600A: Display device600B: Display device607: Adhesive layer610: Substrate611a: Conductive layer611b: Conductive layer611c: Conductive layer613a: Layer613b: Layer613c: Layer614 : Common layer615: Common electrode618a: Sacrificial layer620: Component layer625: Insulation layer627: Insulation layer628B: Color layer628G: Color layer628R: Color layer630: Component layer631: Protective layer635: Component layer640: Connector642: Conductive layer643: Conductive layer644: Conductive layer645: Conductive layer646: Conductive layer648: Insulation layer650: Light-emitting element650B: Light-emitting element650G: Light-emitting element650R: Light-emitting element660: Component layer670: Wiring layer7 00A: Electronic device710: Semiconductor device721: Housing723: Mounting unit730: Electronic components731: Plug-in board732: Package substrate733: Electrode735: Semiconductor device750: Headphones751: Display panel753: Optical components756: Display area757: Frame758: Nose pad800A: Electronic device800B: Electronic device820: Display unit821: Housing822: Communication unit823: Mounting unit824: Control unit825: Imaging unit827: Headphones832: Lens840 Display device840_L: Display device840_R: Display device841: Motion detection unit842: Line of sight detection unit843: Calculation unit844: Communication unit845: Housing848: Lens850A: Electronic device850B: Electronic device851: Operation button854: Installation tool855: Sensor856: Dial900: Semiconductor device910: Driver circuit911: Peripheral circuit912: Control circuit915: Peripheral circuit920: Memory array923: Row driver924: Column driver925 : Input circuit926: Output circuit927: Sense amplifier928: Voltage generation circuit930: Layer931: PSW932: PSW941: Row decoder942: Column decoder950: Memory cell951: Memory cell952: Memory device953: Memory cell954: Memory cell955: Memory cell956: Memory cell957: Memory cell960: Computing device970A: Semiconductor device970B: Semiconductor device970C: Semiconductor device989: Cache interface990: Substrate99 1: ALU992: ALU controller993: Instruction decoder994: Interrupt controller995: Timing controller996: Register997: Register controller998: Bus interface999: Cache3102: Transistor3104: Transistor3110: Electronic component3111: Mold3112: Memory device3113: Connector pad3114: Electrode pad3115: Lead3121: Layer3122: Layer3210: Mounting substrate3212: Printed circuit board3301: Transistor3302: Transistor3311: Semiconductor layer3312: Semiconductor layer5600: Mainframe computer5610: Rack5620: Computer5621: Personal computer card5622: Board5623: Connector5624: Connector5625: Connector5626: Semiconductor device5627: Semiconductor device5628: Semiconductor device5629: Connector5630: Motherboard5631: Slot6500: Electronic device6501: Case6502: Display6503: Power button6504: Button6505: Speaker6 506: Microphone6507: Camera6508: Light Source6509: Control Unit6510: Protective Component6511: Display Panel6512: Optical Component6513: Touch Sensor Panel6515: FPC6516: IC6517: Printed Circuit Board6518: Battery6519: Connector6520: Electronic Device6800: Satellite6801: Main Body6802: Solar Panel6803: Antenna6804: Planet6805: Secondary Battery6807: Control Unit7000: Display Unit7001: Host7001sb: Server7002: Storage Control Circuit7003: Storage7003md: Memory Device7004: Storage Local Area Network7010: Storage System7100: Television7101: Housing7103: Stand7111: Remote Control7200: Laptop7211: Housing7212: Keyboard7213: Pointing Device7214: External Port7215: Control Device7300: Digital Signage7301: Housing7303: Speaker7311: Information Terminal74 00: Digital Signage7401: Column7411: Information Terminal9000: Housing9000a: Housing9000b: Housing9001: Display9001a: Display Panel9001b: Display Panel9001c: Display Panel9001d: Display Panel9003: Speaker9005: Operation Keys9006: Connector Terminals9007: Sensor9008: Microphone9055: Hinge9056: Operation Buttons9200: Portable Information Terminal9201: Portable Information Terminal9202: Portable Information Terminal
[圖1A]及[圖1B]是示出半導體裝置的一個例子的立體圖。 [圖2A1]及[圖2A2]是示出半導體裝置的一個例子的平面圖。[圖2B]至[圖2D]是示出半導體裝置的一個例子的剖面圖。 [圖3A]及[圖3B]是示出半導體裝置的一個例子的剖面圖。[圖3C]是能帶圖。 [圖4A]及[圖4B]是示出半導體裝置的一個例子的剖面圖。 [圖5A]及[圖5B]是示出半導體裝置的一個例子的剖面圖。 [圖6]是示出半導體裝置的一個例子的剖面圖。 [圖7A1]及[圖7A2]是示出半導體裝置的一個例子的平面圖。[圖7B]及[圖7C]是示出半導體裝置的一個例子的剖面圖。 [圖8A]及[圖8B]是示出半導體裝置的一個例子的剖面圖。 [圖9A1]及[圖9A2]是示出半導體裝置的一個例子的平面圖。[圖9B]至[圖9D]是示出半導體裝置的一個例子的剖面圖。 [圖10A]及[圖10B]是示出半導體裝置的一個例子的剖面圖。 [圖11A]及[圖11B]是示出半導體裝置的一個例子的剖面圖。 [圖12]是示出半導體裝置的一個例子的剖面圖。 [圖13A]及[圖13B]是示出半導體裝置的一個例子的剖面圖。 [圖14A]及[圖14B]是示出半導體裝置的一個例子的剖面圖。 [圖15A1]及[圖15A2]是示出半導體裝置的一個例子的平面圖。[圖15B]至[圖15D]是示出半導體裝置的一個例子的剖面圖。 [圖16A]及[圖16B]是示出半導體裝置的一個例子的剖面圖。 [圖17A]至[圖17D]是示出半導體裝置的製造方法的一個例子的剖面圖。 [圖18A]至[圖18C]是示出半導體裝置的製造方法的一個例子的剖面圖。 [圖19A]是示出記憶體裝置的一個例子的平面圖。[圖19B]及[圖19C]是示出記憶體裝置的一個例子的剖面圖。 [圖20A]是示出記憶體裝置的一個例子的平面圖。[圖20B]及[圖20C]是示出記憶體裝置的一個例子的剖面圖。 [圖21A]及[圖21B]是示出記憶體裝置的一個例子的剖面圖。 [圖22A]是示出記憶體裝置的一個例子的平面圖。[圖22B]是示出記憶體裝置的一個例子的剖面圖。 [圖23]是示出記憶體裝置的一個例子的剖面圖。 [圖24]是示出記憶體裝置的一個例子的剖面圖。 [圖25]是說明半導體裝置的結構例子的方塊圖。 [圖26A]至[圖26G]是說明記憶單元的電路結構例子的圖。 [圖27A]及[圖27B]是說明半導體裝置的結構例子的立體圖。 [圖28]是說明CPU的方塊圖。 [圖29A]及[圖29B]是半導體裝置的立體圖。 [圖30A]及[圖30B]是半導體裝置的立體圖。 [圖31A]及[圖31B]是本發明的一個實施方式的半導體裝置的電路圖，[圖31C]是示出使用本發明的一個實施方式的半導體裝置的電子構件的一個例子的圖。 [圖32A]及[圖32B]是示出顯示裝置的一個例子的立體圖。 [圖33]是示出顯示裝置的一個例子的剖面圖。 [圖34]是示出顯示裝置的一個例子的剖面圖。 [圖35A]至[圖35C]是示出顯示裝置的結構例子的圖。 [圖36]是示出電子構件的一個例子的圖。 [圖37A]至[圖37C]是示出大型電腦的一個例子的圖。[圖37D]是示出太空設備的一個例子的圖。[圖37E]是示出可用於資料中心的儲存系統的一個例子的圖。 [圖38A]至[圖38F]是示出電子裝置的一個例子的圖。 [圖39A]至[圖39G]是示出電子裝置的一個例子的圖。 [圖40A]至[圖40F]是示出電子裝置的一個例子的圖。 [圖41]是示出實施例的濕蝕刻速率的圖表。 [圖42]是示出樣品所包括的電晶體的剖面圖。 [圖43A]及[圖43B]是實施例中製造的樣品的EDX線分析的結果。 [圖44A]及[圖44B]是實施例中製造的樣品的氫濃度的SIMS分析的結果。 [圖45A]是記憶單元的立體示意圖，[圖45B]是記憶單元的剖面STEM影像。 [圖46A]是示出記憶體裝置的一個例子的平面圖。[圖46B]及[圖46C]是示出記憶體裝置的一個例子的剖面圖。 [圖47]是示出電晶體的Id-Vg特性的圖。 [圖48A]及[圖48B]是示出電晶體的Id-Vg特性的圖。 [圖49]是示出實施例的P-V特性的圖。 [圖50A]是示出輸入電壓波形的圖。[圖50B]是示出疲勞特性的圖。 [圖51A]及[圖51B]是示出保持測量的方法的圖，[圖51C]是示出保持測量的結果的圖。 [圖52]是說明記憶單元電路的圖。 [圖53A]及[圖53B]是說明極化的寫入及讀出的評價方法的圖。[圖53C]是示出電流波形的圖。 [圖54A]及[圖54B]是示出電晶體的可靠性測試的評價結果的圖。 [圖55]是能帶圖。 [圖56A]至[圖56C]是示出計算的結果的圖。 [圖57A1]至[圖57C2]是示出計算的結果的圖。 [圖58]是示出電晶體的可靠性測試的評價結果的圖。[Figure 1A] and [Figure 1B] are perspective views illustrating an example of a semiconductor device.[Figure 2A1] and [Figure 2A2] are plan views illustrating an example of a semiconductor device. [Figures 2B] to [Figure 2D] are cross-sectional views illustrating an example of a semiconductor device.[Figure 3A] and [Figure 3B] are cross-sectional views illustrating an example of a semiconductor device. [Figure 3C] is an energy band diagram.[Figure 4A] and [Figure 4B] are cross-sectional views illustrating an example of a semiconductor device.[Figure 5A] and [Figure 5B] are cross-sectional views illustrating an example of a semiconductor device.[Figure 6] is a cross-sectional view illustrating an example of a semiconductor device.[Figure 7A1] and [Figure 7A2] are plan views illustrating an example of a semiconductor device. [Figure 7B] and [Figure 7C] are cross-sectional views illustrating an example of a semiconductor device.[Figure 8A] and [Figure 8B] are cross-sectional views illustrating an example of a semiconductor device.[Figure 9A1] and [Figure 9A2] are plan views illustrating an example of a semiconductor device. [Figure 9B] to [Figure 9D] are cross-sectional views illustrating an example of a semiconductor device.[Figure 10A] and [Figure 10B] are cross-sectional views illustrating an example of a semiconductor device.[Figure 11A] and [Figure 11B] are cross-sectional views illustrating an example of a semiconductor device.[Figure 12] is a cross-sectional view illustrating an example of a semiconductor device.[Figure 13A] and [Figure 13B] are cross-sectional views illustrating an example of a semiconductor device. [Figures 14A] and 14B are cross-sectional views illustrating an example of a semiconductor device.[Figures 15A1] and 15A2] are plan views illustrating an example of a semiconductor device. [Figures 15B] to 15D] are cross-sectional views illustrating an example of a semiconductor device.[Figures 16A] and 16B] are cross-sectional views illustrating an example of a semiconductor device.[Figures 17A] to 17D] are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.[Figures 18A] to 18C] are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.[Figure 19A] is a plan view illustrating an example of a memory device. [Figures 19B] and 19C] are cross-sectional views illustrating an example of a memory device.FIG20A is a plan view illustrating an example of a memory device. FIG20B and FIG20C are cross-sectional views illustrating an example of a memory device.FIG21A and FIG21B are cross-sectional views illustrating an example of a memory device.FIG22A is a plan view illustrating an example of a memory device. FIG22B is a cross-sectional view illustrating an example of a memory device.FIG23 is a cross-sectional view illustrating an example of a memory device.FIG24 is a cross-sectional view illustrating an example of a memory device.FIG25 is a block diagram illustrating an example structure of a semiconductor device.FIG26A to FIG26G are diagrams illustrating an example circuit structure of a memory cell.Figures 27A and 27B are perspective views illustrating an example structure of a semiconductor device. Figure 28 is a block diagram illustrating a CPU. Figures 29A and 29B are perspective views of a semiconductor device. Figures 30A and 30B are perspective views of a semiconductor device. Figures 31A and 31B are circuit diagrams of a semiconductor device according to an embodiment of the present invention, and Figure 31C is a diagram illustrating an example of an electronic component incorporating a semiconductor device according to an embodiment of the present invention. Figures 32A and 32B are perspective views illustrating an example of a display device. Figure 33 is a cross-sectional view illustrating an example of a display device. Figure 34 is a cross-sectional view illustrating an example of a display device. Figures 35A to 35C illustrate an example structure of a display device.Figure 36 illustrates an example of an electronic component.Figures 37A to 37C illustrate an example of a mainframe computer.Figure 37D illustrates an example of space equipment.Figure 37E illustrates an example of a storage system that can be used in a data center.Figures 38A to 38F illustrate an example of an electronic device.Figures 39A to 39G illustrate an example of an electronic device.Figures 40A to 40F illustrate an example of an electronic device.Figure 41 illustrates a graph showing the wet etching rate of an embodiment.Figure 42 illustrates a cross-sectional view of a transistor included in a sample. Figures 43A and 43B show the results of EDX analysis of samples fabricated in the embodiment.Figures 44A and 44B show the results of SIMS analysis of hydrogen concentrations in samples fabricated in the embodiment.Figure 45A is a schematic three-dimensional diagram of a memory cell, and Figure 45B is a cross-sectional STEM image of the memory cell.Figure 46A is a plan view of an example memory device. Figures 46B and 46C are cross-sectional views of an example memory device.Figure 47 is a graph showing the Id-Vg characteristics of a transistor.Figures 48A and 48B are graphs showing the Id-Vg characteristics of a transistor.Figure 49 is a graph showing the P-V characteristics of the embodiment. Figure 50A shows an input voltage waveform. Figure 50B shows fatigue characteristics.Figures 51A and 51B show the retention measurement method, and Figure 51C shows the retention measurement results.Figure 52 shows a diagram illustrating a memory cell circuit.Figures 53A and 53B show the evaluation method for writing and reading polarization. Figure 53C shows a current waveform.Figures 54A and 54B show the evaluation results of a transistor reliability test.Figure 55 shows an energy band diagram.Figures 56A to 56C show the results of calculations.Figures 57A1 to 57C2 show the results of calculations. [Figure 58] is a graph showing the evaluation results of transistor reliability tests.
200:電晶體200: Transistor
210:絕緣層210: Insulating layer
220:導電層220: Conductive layer
220_1:導電層220_1:Conductive layer
220_2:導電層220_2:Conductive layer
227:氧化物層227: Oxide layer
230_1:氧化物半導體層230_1: Oxide semiconductor layer
230_2:氧化物半導體層230_2: Oxide semiconductor layer
240_1:導電層240_1: Conductive layer
240_2:導電層240_2: Conductive layer
250:絕緣層250: Insulation layer
260:導電層260:Conductive layer
260_1:導電層260_1: Conductive layer
260_2:導電層260_2: Conductive layer
280:絕緣層280: Insulating layer
290:開口部290:Opening part
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| WO2015097586A1 (en)* | 2013-12-25 | 2015-07-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US20230335605A1 (en)* | 2022-04-15 | 2023-10-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| WO2023203425A1 (en)* | 2022-04-22 | 2023-10-26 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for semiconductor device fabrication |
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